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drm: i915: Rely on the default ->best_encoder() behavior where appropriate
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_drv.h
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1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/async.h>
29#include <linux/i2c.h>
30#include <linux/hdmi.h>
31#include <drm/i915_drm.h>
32#include "i915_drv.h"
33#include <drm/drm_crtc.h>
34#include <drm/drm_crtc_helper.h>
35#include <drm/drm_fb_helper.h>
36#include <drm/drm_dp_dual_mode_helper.h>
37#include <drm/drm_dp_mst_helper.h>
38#include <drm/drm_rect.h>
39#include <drm/drm_atomic.h>
40
41/**
42 * _wait_for - magic (register) wait macro
43 *
44 * Does the right thing for modeset paths when run under kdgb or similar atomic
45 * contexts. Note that it's important that we check the condition again after
46 * having timed out, since the timeout could be due to preemption or similar and
47 * we've never had a chance to check the condition before the timeout.
48 *
49 * TODO: When modesetting has fully transitioned to atomic, the below
50 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
51 * added.
52 */
53#define _wait_for(COND, US, W) ({ \
54 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
55 int ret__ = 0; \
56 while (!(COND)) { \
57 if (time_after(jiffies, timeout__)) { \
58 if (!(COND)) \
59 ret__ = -ETIMEDOUT; \
60 break; \
61 } \
62 if ((W) && drm_can_sleep()) { \
63 usleep_range((W), (W)*2); \
64 } else { \
65 cpu_relax(); \
66 } \
67 } \
68 ret__; \
69})
70
71#define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000)
72#define wait_for_us(COND, US) _wait_for((COND), (US), 1)
73
74/* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
75#if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
76# define _WAIT_FOR_ATOMIC_CHECK WARN_ON_ONCE(!in_atomic())
77#else
78# define _WAIT_FOR_ATOMIC_CHECK do { } while (0)
79#endif
80
81#define _wait_for_atomic(COND, US) ({ \
82 unsigned long end__; \
83 int ret__ = 0; \
84 _WAIT_FOR_ATOMIC_CHECK; \
85 BUILD_BUG_ON((US) > 50000); \
86 end__ = (local_clock() >> 10) + (US) + 1; \
87 while (!(COND)) { \
88 if (time_after((unsigned long)(local_clock() >> 10), end__)) { \
89 /* Unlike the regular wait_for(), this atomic variant \
90 * cannot be preempted (and we'll just ignore the issue\
91 * of irq interruptions) and so we know that no time \
92 * has passed since the last check of COND and can \
93 * immediately report the timeout. \
94 */ \
95 ret__ = -ETIMEDOUT; \
96 break; \
97 } \
98 cpu_relax(); \
99 } \
100 ret__; \
101})
102
103#define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000)
104#define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US))
105
106#define KHz(x) (1000 * (x))
107#define MHz(x) KHz(1000 * (x))
108
109/*
110 * Display related stuff
111 */
112
113/* store information about an Ixxx DVO */
114/* The i830->i865 use multiple DVOs with multiple i2cs */
115/* the i915, i945 have a single sDVO i2c bus - which is different */
116#define MAX_OUTPUTS 6
117/* maximum connectors per crtcs in the mode set */
118
119/* Maximum cursor sizes */
120#define GEN2_CURSOR_WIDTH 64
121#define GEN2_CURSOR_HEIGHT 64
122#define MAX_CURSOR_WIDTH 256
123#define MAX_CURSOR_HEIGHT 256
124
125#define INTEL_I2C_BUS_DVO 1
126#define INTEL_I2C_BUS_SDVO 2
127
128/* these are outputs from the chip - integrated only
129 external chips are via DVO or SDVO output */
130enum intel_output_type {
131 INTEL_OUTPUT_UNUSED = 0,
132 INTEL_OUTPUT_ANALOG = 1,
133 INTEL_OUTPUT_DVO = 2,
134 INTEL_OUTPUT_SDVO = 3,
135 INTEL_OUTPUT_LVDS = 4,
136 INTEL_OUTPUT_TVOUT = 5,
137 INTEL_OUTPUT_HDMI = 6,
138 INTEL_OUTPUT_DISPLAYPORT = 7,
139 INTEL_OUTPUT_EDP = 8,
140 INTEL_OUTPUT_DSI = 9,
141 INTEL_OUTPUT_UNKNOWN = 10,
142 INTEL_OUTPUT_DP_MST = 11,
143};
144
145#define INTEL_DVO_CHIP_NONE 0
146#define INTEL_DVO_CHIP_LVDS 1
147#define INTEL_DVO_CHIP_TMDS 2
148#define INTEL_DVO_CHIP_TVOUT 4
149
150#define INTEL_DSI_VIDEO_MODE 0
151#define INTEL_DSI_COMMAND_MODE 1
152
153struct intel_framebuffer {
154 struct drm_framebuffer base;
155 struct drm_i915_gem_object *obj;
156 struct intel_rotation_info rot_info;
157};
158
159struct intel_fbdev {
160 struct drm_fb_helper helper;
161 struct intel_framebuffer *fb;
162 int preferred_bpp;
163};
164
165struct intel_encoder {
166 struct drm_encoder base;
167
168 enum intel_output_type type;
169 unsigned int cloneable;
170 void (*hot_plug)(struct intel_encoder *);
171 bool (*compute_config)(struct intel_encoder *,
172 struct intel_crtc_state *);
173 void (*pre_pll_enable)(struct intel_encoder *);
174 void (*pre_enable)(struct intel_encoder *);
175 void (*enable)(struct intel_encoder *);
176 void (*mode_set)(struct intel_encoder *intel_encoder);
177 void (*disable)(struct intel_encoder *);
178 void (*post_disable)(struct intel_encoder *);
179 void (*post_pll_disable)(struct intel_encoder *);
180 /* Read out the current hw state of this connector, returning true if
181 * the encoder is active. If the encoder is enabled it also set the pipe
182 * it is connected to in the pipe parameter. */
183 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
184 /* Reconstructs the equivalent mode flags for the current hardware
185 * state. This must be called _after_ display->get_pipe_config has
186 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
187 * be set correctly before calling this function. */
188 void (*get_config)(struct intel_encoder *,
189 struct intel_crtc_state *pipe_config);
190 /*
191 * Called during system suspend after all pending requests for the
192 * encoder are flushed (for example for DP AUX transactions) and
193 * device interrupts are disabled.
194 */
195 void (*suspend)(struct intel_encoder *);
196 int crtc_mask;
197 enum hpd_pin hpd_pin;
198};
199
200struct intel_panel {
201 struct drm_display_mode *fixed_mode;
202 struct drm_display_mode *downclock_mode;
203 int fitting_mode;
204
205 /* backlight */
206 struct {
207 bool present;
208 u32 level;
209 u32 min;
210 u32 max;
211 bool enabled;
212 bool combination_mode; /* gen 2/4 only */
213 bool active_low_pwm;
214
215 /* PWM chip */
216 bool util_pin_active_low; /* bxt+ */
217 u8 controller; /* bxt+ only */
218 struct pwm_device *pwm;
219
220 struct backlight_device *device;
221
222 /* Connector and platform specific backlight functions */
223 int (*setup)(struct intel_connector *connector, enum pipe pipe);
224 uint32_t (*get)(struct intel_connector *connector);
225 void (*set)(struct intel_connector *connector, uint32_t level);
226 void (*disable)(struct intel_connector *connector);
227 void (*enable)(struct intel_connector *connector);
228 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
229 uint32_t hz);
230 void (*power)(struct intel_connector *, bool enable);
231 } backlight;
232};
233
234struct intel_connector {
235 struct drm_connector base;
236 /*
237 * The fixed encoder this connector is connected to.
238 */
239 struct intel_encoder *encoder;
240
241 /* Reads out the current hw, returning true if the connector is enabled
242 * and active (i.e. dpms ON state). */
243 bool (*get_hw_state)(struct intel_connector *);
244
245 /*
246 * Removes all interfaces through which the connector is accessible
247 * - like sysfs, debugfs entries -, so that no new operations can be
248 * started on the connector. Also makes sure all currently pending
249 * operations finish before returing.
250 */
251 void (*unregister)(struct intel_connector *);
252
253 /* Panel info for eDP and LVDS */
254 struct intel_panel panel;
255
256 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
257 struct edid *edid;
258 struct edid *detect_edid;
259
260 /* since POLL and HPD connectors may use the same HPD line keep the native
261 state of connector->polled in case hotplug storm detection changes it */
262 u8 polled;
263
264 void *port; /* store this opaque as its illegal to dereference it */
265
266 struct intel_dp *mst_port;
267};
268
269struct dpll {
270 /* given values */
271 int n;
272 int m1, m2;
273 int p1, p2;
274 /* derived values */
275 int dot;
276 int vco;
277 int m;
278 int p;
279};
280
281struct intel_atomic_state {
282 struct drm_atomic_state base;
283
284 unsigned int cdclk;
285
286 /*
287 * Calculated device cdclk, can be different from cdclk
288 * only when all crtc's are DPMS off.
289 */
290 unsigned int dev_cdclk;
291
292 bool dpll_set, modeset;
293
294 /*
295 * Does this transaction change the pipes that are active? This mask
296 * tracks which CRTC's have changed their active state at the end of
297 * the transaction (not counting the temporary disable during modesets).
298 * This mask should only be non-zero when intel_state->modeset is true,
299 * but the converse is not necessarily true; simply changing a mode may
300 * not flip the final active status of any CRTC's
301 */
302 unsigned int active_pipe_changes;
303
304 unsigned int active_crtcs;
305 unsigned int min_pixclk[I915_MAX_PIPES];
306
307 /* SKL/KBL Only */
308 unsigned int cdclk_pll_vco;
309
310 struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
311
312 /*
313 * Current watermarks can't be trusted during hardware readout, so
314 * don't bother calculating intermediate watermarks.
315 */
316 bool skip_intermediate_wm;
317
318 /* Gen9+ only */
319 struct skl_wm_values wm_results;
320};
321
322struct intel_plane_state {
323 struct drm_plane_state base;
324 struct drm_rect src;
325 struct drm_rect dst;
326 struct drm_rect clip;
327 bool visible;
328
329 /*
330 * scaler_id
331 * = -1 : not using a scaler
332 * >= 0 : using a scalers
333 *
334 * plane requiring a scaler:
335 * - During check_plane, its bit is set in
336 * crtc_state->scaler_state.scaler_users by calling helper function
337 * update_scaler_plane.
338 * - scaler_id indicates the scaler it got assigned.
339 *
340 * plane doesn't require a scaler:
341 * - this can happen when scaling is no more required or plane simply
342 * got disabled.
343 * - During check_plane, corresponding bit is reset in
344 * crtc_state->scaler_state.scaler_users by calling helper function
345 * update_scaler_plane.
346 */
347 int scaler_id;
348
349 struct drm_intel_sprite_colorkey ckey;
350
351 /* async flip related structures */
352 struct drm_i915_gem_request *wait_req;
353};
354
355struct intel_initial_plane_config {
356 struct intel_framebuffer *fb;
357 unsigned int tiling;
358 int size;
359 u32 base;
360};
361
362#define SKL_MIN_SRC_W 8
363#define SKL_MAX_SRC_W 4096
364#define SKL_MIN_SRC_H 8
365#define SKL_MAX_SRC_H 4096
366#define SKL_MIN_DST_W 8
367#define SKL_MAX_DST_W 4096
368#define SKL_MIN_DST_H 8
369#define SKL_MAX_DST_H 4096
370
371struct intel_scaler {
372 int in_use;
373 uint32_t mode;
374};
375
376struct intel_crtc_scaler_state {
377#define SKL_NUM_SCALERS 2
378 struct intel_scaler scalers[SKL_NUM_SCALERS];
379
380 /*
381 * scaler_users: keeps track of users requesting scalers on this crtc.
382 *
383 * If a bit is set, a user is using a scaler.
384 * Here user can be a plane or crtc as defined below:
385 * bits 0-30 - plane (bit position is index from drm_plane_index)
386 * bit 31 - crtc
387 *
388 * Instead of creating a new index to cover planes and crtc, using
389 * existing drm_plane_index for planes which is well less than 31
390 * planes and bit 31 for crtc. This should be fine to cover all
391 * our platforms.
392 *
393 * intel_atomic_setup_scalers will setup available scalers to users
394 * requesting scalers. It will gracefully fail if request exceeds
395 * avilability.
396 */
397#define SKL_CRTC_INDEX 31
398 unsigned scaler_users;
399
400 /* scaler used by crtc for panel fitting purpose */
401 int scaler_id;
402};
403
404/* drm_mode->private_flags */
405#define I915_MODE_FLAG_INHERITED 1
406
407struct intel_pipe_wm {
408 struct intel_wm_level wm[5];
409 struct intel_wm_level raw_wm[5];
410 uint32_t linetime;
411 bool fbc_wm_enabled;
412 bool pipe_enabled;
413 bool sprites_enabled;
414 bool sprites_scaled;
415};
416
417struct skl_pipe_wm {
418 struct skl_wm_level wm[8];
419 struct skl_wm_level trans_wm;
420 uint32_t linetime;
421};
422
423struct intel_crtc_wm_state {
424 union {
425 struct {
426 /*
427 * Intermediate watermarks; these can be
428 * programmed immediately since they satisfy
429 * both the current configuration we're
430 * switching away from and the new
431 * configuration we're switching to.
432 */
433 struct intel_pipe_wm intermediate;
434
435 /*
436 * Optimal watermarks, programmed post-vblank
437 * when this state is committed.
438 */
439 struct intel_pipe_wm optimal;
440 } ilk;
441
442 struct {
443 /* gen9+ only needs 1-step wm programming */
444 struct skl_pipe_wm optimal;
445
446 /* cached plane data rate */
447 unsigned plane_data_rate[I915_MAX_PLANES];
448 unsigned plane_y_data_rate[I915_MAX_PLANES];
449
450 /* minimum block allocation */
451 uint16_t minimum_blocks[I915_MAX_PLANES];
452 uint16_t minimum_y_blocks[I915_MAX_PLANES];
453 } skl;
454 };
455
456 /*
457 * Platforms with two-step watermark programming will need to
458 * update watermark programming post-vblank to switch from the
459 * safe intermediate watermarks to the optimal final
460 * watermarks.
461 */
462 bool need_postvbl_update;
463};
464
465struct intel_crtc_state {
466 struct drm_crtc_state base;
467
468 /**
469 * quirks - bitfield with hw state readout quirks
470 *
471 * For various reasons the hw state readout code might not be able to
472 * completely faithfully read out the current state. These cases are
473 * tracked with quirk flags so that fastboot and state checker can act
474 * accordingly.
475 */
476#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
477 unsigned long quirks;
478
479 unsigned fb_bits; /* framebuffers to flip */
480 bool update_pipe; /* can a fast modeset be performed? */
481 bool disable_cxsr;
482 bool update_wm_pre, update_wm_post; /* watermarks are updated */
483 bool fb_changed; /* fb on any of the planes is changed */
484
485 /* Pipe source size (ie. panel fitter input size)
486 * All planes will be positioned inside this space,
487 * and get clipped at the edges. */
488 int pipe_src_w, pipe_src_h;
489
490 /* Whether to set up the PCH/FDI. Note that we never allow sharing
491 * between pch encoders and cpu encoders. */
492 bool has_pch_encoder;
493
494 /* Are we sending infoframes on the attached port */
495 bool has_infoframe;
496
497 /* CPU Transcoder for the pipe. Currently this can only differ from the
498 * pipe on Haswell and later (where we have a special eDP transcoder)
499 * and Broxton (where we have special DSI transcoders). */
500 enum transcoder cpu_transcoder;
501
502 /*
503 * Use reduced/limited/broadcast rbg range, compressing from the full
504 * range fed into the crtcs.
505 */
506 bool limited_color_range;
507
508 /* DP has a bunch of special case unfortunately, so mark the pipe
509 * accordingly. */
510 bool has_dp_encoder;
511
512 /* DSI has special cases */
513 bool has_dsi_encoder;
514
515 /* Whether we should send NULL infoframes. Required for audio. */
516 bool has_hdmi_sink;
517
518 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
519 * has_dp_encoder is set. */
520 bool has_audio;
521
522 /*
523 * Enable dithering, used when the selected pipe bpp doesn't match the
524 * plane bpp.
525 */
526 bool dither;
527
528 /* Controls for the clock computation, to override various stages. */
529 bool clock_set;
530
531 /* SDVO TV has a bunch of special case. To make multifunction encoders
532 * work correctly, we need to track this at runtime.*/
533 bool sdvo_tv_clock;
534
535 /*
536 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
537 * required. This is set in the 2nd loop of calling encoder's
538 * ->compute_config if the first pick doesn't work out.
539 */
540 bool bw_constrained;
541
542 /* Settings for the intel dpll used on pretty much everything but
543 * haswell. */
544 struct dpll dpll;
545
546 /* Selected dpll when shared or NULL. */
547 struct intel_shared_dpll *shared_dpll;
548
549 /*
550 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
551 * - enum skl_dpll on SKL
552 */
553 uint32_t ddi_pll_sel;
554
555 /* Actual register state of the dpll, for shared dpll cross-checking. */
556 struct intel_dpll_hw_state dpll_hw_state;
557
558 /* DSI PLL registers */
559 struct {
560 u32 ctrl, div;
561 } dsi_pll;
562
563 int pipe_bpp;
564 struct intel_link_m_n dp_m_n;
565
566 /* m2_n2 for eDP downclock */
567 struct intel_link_m_n dp_m2_n2;
568 bool has_drrs;
569
570 /*
571 * Frequence the dpll for the port should run at. Differs from the
572 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
573 * already multiplied by pixel_multiplier.
574 */
575 int port_clock;
576
577 /* Used by SDVO (and if we ever fix it, HDMI). */
578 unsigned pixel_multiplier;
579
580 uint8_t lane_count;
581
582 /* Panel fitter controls for gen2-gen4 + VLV */
583 struct {
584 u32 control;
585 u32 pgm_ratios;
586 u32 lvds_border_bits;
587 } gmch_pfit;
588
589 /* Panel fitter placement and size for Ironlake+ */
590 struct {
591 u32 pos;
592 u32 size;
593 bool enabled;
594 bool force_thru;
595 } pch_pfit;
596
597 /* FDI configuration, only valid if has_pch_encoder is set. */
598 int fdi_lanes;
599 struct intel_link_m_n fdi_m_n;
600
601 bool ips_enabled;
602
603 bool enable_fbc;
604
605 bool double_wide;
606
607 bool dp_encoder_is_mst;
608 int pbn;
609
610 struct intel_crtc_scaler_state scaler_state;
611
612 /* w/a for waiting 2 vblanks during crtc enable */
613 enum pipe hsw_workaround_pipe;
614
615 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
616 bool disable_lp_wm;
617
618 struct intel_crtc_wm_state wm;
619
620 /* Gamma mode programmed on the pipe */
621 uint32_t gamma_mode;
622};
623
624struct vlv_wm_state {
625 struct vlv_pipe_wm wm[3];
626 struct vlv_sr_wm sr[3];
627 uint8_t num_active_planes;
628 uint8_t num_levels;
629 uint8_t level;
630 bool cxsr;
631};
632
633struct intel_crtc {
634 struct drm_crtc base;
635 enum pipe pipe;
636 enum plane plane;
637 u8 lut_r[256], lut_g[256], lut_b[256];
638 /*
639 * Whether the crtc and the connected output pipeline is active. Implies
640 * that crtc->enabled is set, i.e. the current mode configuration has
641 * some outputs connected to this crtc.
642 */
643 bool active;
644 unsigned long enabled_power_domains;
645 bool lowfreq_avail;
646 struct intel_overlay *overlay;
647 struct intel_flip_work *flip_work;
648
649 atomic_t unpin_work_count;
650
651 /* Display surface base address adjustement for pageflips. Note that on
652 * gen4+ this only adjusts up to a tile, offsets within a tile are
653 * handled in the hw itself (with the TILEOFF register). */
654 u32 dspaddr_offset;
655 int adjusted_x;
656 int adjusted_y;
657
658 uint32_t cursor_addr;
659 uint32_t cursor_cntl;
660 uint32_t cursor_size;
661 uint32_t cursor_base;
662
663 struct intel_crtc_state *config;
664
665 /* reset counter value when the last flip was submitted */
666 unsigned int reset_counter;
667
668 /* Access to these should be protected by dev_priv->irq_lock. */
669 bool cpu_fifo_underrun_disabled;
670 bool pch_fifo_underrun_disabled;
671
672 /* per-pipe watermark state */
673 struct {
674 /* watermarks currently being used */
675 union {
676 struct intel_pipe_wm ilk;
677 struct skl_pipe_wm skl;
678 } active;
679
680 /* allow CxSR on this pipe */
681 bool cxsr_allowed;
682 } wm;
683
684 int scanline_offset;
685
686 struct {
687 unsigned start_vbl_count;
688 ktime_t start_vbl_time;
689 int min_vbl, max_vbl;
690 int scanline_start;
691 } debug;
692
693 /* scalers available on this crtc */
694 int num_scalers;
695
696 struct vlv_wm_state wm_state;
697};
698
699struct intel_plane_wm_parameters {
700 uint32_t horiz_pixels;
701 uint32_t vert_pixels;
702 /*
703 * For packed pixel formats:
704 * bytes_per_pixel - holds bytes per pixel
705 * For planar pixel formats:
706 * bytes_per_pixel - holds bytes per pixel for uv-plane
707 * y_bytes_per_pixel - holds bytes per pixel for y-plane
708 */
709 uint8_t bytes_per_pixel;
710 uint8_t y_bytes_per_pixel;
711 bool enabled;
712 bool scaled;
713 u64 tiling;
714 unsigned int rotation;
715 uint16_t fifo_size;
716};
717
718struct intel_plane {
719 struct drm_plane base;
720 int plane;
721 enum pipe pipe;
722 bool can_scale;
723 int max_downscale;
724 uint32_t frontbuffer_bit;
725
726 /* Since we need to change the watermarks before/after
727 * enabling/disabling the planes, we need to store the parameters here
728 * as the other pieces of the struct may not reflect the values we want
729 * for the watermark calculations. Currently only Haswell uses this.
730 */
731 struct intel_plane_wm_parameters wm;
732
733 /*
734 * NOTE: Do not place new plane state fields here (e.g., when adding
735 * new plane properties). New runtime state should now be placed in
736 * the intel_plane_state structure and accessed via plane_state.
737 */
738
739 void (*update_plane)(struct drm_plane *plane,
740 const struct intel_crtc_state *crtc_state,
741 const struct intel_plane_state *plane_state);
742 void (*disable_plane)(struct drm_plane *plane,
743 struct drm_crtc *crtc);
744 int (*check_plane)(struct drm_plane *plane,
745 struct intel_crtc_state *crtc_state,
746 struct intel_plane_state *state);
747};
748
749struct intel_watermark_params {
750 unsigned long fifo_size;
751 unsigned long max_wm;
752 unsigned long default_wm;
753 unsigned long guard_size;
754 unsigned long cacheline_size;
755};
756
757struct cxsr_latency {
758 int is_desktop;
759 int is_ddr3;
760 unsigned long fsb_freq;
761 unsigned long mem_freq;
762 unsigned long display_sr;
763 unsigned long display_hpll_disable;
764 unsigned long cursor_sr;
765 unsigned long cursor_hpll_disable;
766};
767
768#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
769#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
770#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
771#define to_intel_connector(x) container_of(x, struct intel_connector, base)
772#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
773#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
774#define to_intel_plane(x) container_of(x, struct intel_plane, base)
775#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
776#define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
777
778struct intel_hdmi {
779 i915_reg_t hdmi_reg;
780 int ddc_bus;
781 struct {
782 enum drm_dp_dual_mode_type type;
783 int max_tmds_clock;
784 } dp_dual_mode;
785 bool limited_color_range;
786 bool color_range_auto;
787 bool has_hdmi_sink;
788 bool has_audio;
789 enum hdmi_force_audio force_audio;
790 bool rgb_quant_range_selectable;
791 enum hdmi_picture_aspect aspect_ratio;
792 struct intel_connector *attached_connector;
793 void (*write_infoframe)(struct drm_encoder *encoder,
794 enum hdmi_infoframe_type type,
795 const void *frame, ssize_t len);
796 void (*set_infoframes)(struct drm_encoder *encoder,
797 bool enable,
798 const struct drm_display_mode *adjusted_mode);
799 bool (*infoframe_enabled)(struct drm_encoder *encoder,
800 const struct intel_crtc_state *pipe_config);
801};
802
803struct intel_dp_mst_encoder;
804#define DP_MAX_DOWNSTREAM_PORTS 0x10
805
806/*
807 * enum link_m_n_set:
808 * When platform provides two set of M_N registers for dp, we can
809 * program them and switch between them incase of DRRS.
810 * But When only one such register is provided, we have to program the
811 * required divider value on that registers itself based on the DRRS state.
812 *
813 * M1_N1 : Program dp_m_n on M1_N1 registers
814 * dp_m2_n2 on M2_N2 registers (If supported)
815 *
816 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
817 * M2_N2 registers are not supported
818 */
819
820enum link_m_n_set {
821 /* Sets the m1_n1 and m2_n2 */
822 M1_N1 = 0,
823 M2_N2
824};
825
826struct intel_dp {
827 i915_reg_t output_reg;
828 i915_reg_t aux_ch_ctl_reg;
829 i915_reg_t aux_ch_data_reg[5];
830 uint32_t DP;
831 int link_rate;
832 uint8_t lane_count;
833 uint8_t sink_count;
834 bool has_audio;
835 bool detect_done;
836 enum hdmi_force_audio force_audio;
837 bool limited_color_range;
838 bool color_range_auto;
839 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
840 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
841 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
842 uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
843 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
844 uint8_t num_sink_rates;
845 int sink_rates[DP_MAX_SUPPORTED_RATES];
846 struct drm_dp_aux aux;
847 uint8_t train_set[4];
848 int panel_power_up_delay;
849 int panel_power_down_delay;
850 int panel_power_cycle_delay;
851 int backlight_on_delay;
852 int backlight_off_delay;
853 struct delayed_work panel_vdd_work;
854 bool want_panel_vdd;
855 unsigned long last_power_on;
856 unsigned long last_backlight_off;
857 ktime_t panel_power_off_time;
858
859 struct notifier_block edp_notifier;
860
861 /*
862 * Pipe whose power sequencer is currently locked into
863 * this port. Only relevant on VLV/CHV.
864 */
865 enum pipe pps_pipe;
866 struct edp_power_seq pps_delays;
867
868 bool can_mst; /* this port supports mst */
869 bool is_mst;
870 int active_mst_links;
871 /* connector directly attached - won't be use for modeset in mst world */
872 struct intel_connector *attached_connector;
873
874 /* mst connector list */
875 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
876 struct drm_dp_mst_topology_mgr mst_mgr;
877
878 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
879 /*
880 * This function returns the value we have to program the AUX_CTL
881 * register with to kick off an AUX transaction.
882 */
883 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
884 bool has_aux_irq,
885 int send_bytes,
886 uint32_t aux_clock_divider);
887
888 /* This is called before a link training is starterd */
889 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
890
891 bool train_set_valid;
892
893 /* Displayport compliance testing */
894 unsigned long compliance_test_type;
895 unsigned long compliance_test_data;
896 bool compliance_test_active;
897};
898
899struct intel_digital_port {
900 struct intel_encoder base;
901 enum port port;
902 u32 saved_port_bits;
903 struct intel_dp dp;
904 struct intel_hdmi hdmi;
905 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
906 bool release_cl2_override;
907 uint8_t max_lanes;
908 /* for communication with audio component; protected by av_mutex */
909 const struct drm_connector *audio_connector;
910};
911
912struct intel_dp_mst_encoder {
913 struct intel_encoder base;
914 enum pipe pipe;
915 struct intel_digital_port *primary;
916 struct intel_connector *connector;
917};
918
919static inline enum dpio_channel
920vlv_dport_to_channel(struct intel_digital_port *dport)
921{
922 switch (dport->port) {
923 case PORT_B:
924 case PORT_D:
925 return DPIO_CH0;
926 case PORT_C:
927 return DPIO_CH1;
928 default:
929 BUG();
930 }
931}
932
933static inline enum dpio_phy
934vlv_dport_to_phy(struct intel_digital_port *dport)
935{
936 switch (dport->port) {
937 case PORT_B:
938 case PORT_C:
939 return DPIO_PHY0;
940 case PORT_D:
941 return DPIO_PHY1;
942 default:
943 BUG();
944 }
945}
946
947static inline enum dpio_channel
948vlv_pipe_to_channel(enum pipe pipe)
949{
950 switch (pipe) {
951 case PIPE_A:
952 case PIPE_C:
953 return DPIO_CH0;
954 case PIPE_B:
955 return DPIO_CH1;
956 default:
957 BUG();
958 }
959}
960
961static inline struct drm_crtc *
962intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
963{
964 struct drm_i915_private *dev_priv = dev->dev_private;
965 return dev_priv->pipe_to_crtc_mapping[pipe];
966}
967
968static inline struct drm_crtc *
969intel_get_crtc_for_plane(struct drm_device *dev, int plane)
970{
971 struct drm_i915_private *dev_priv = dev->dev_private;
972 return dev_priv->plane_to_crtc_mapping[plane];
973}
974
975struct intel_flip_work {
976 struct work_struct unpin_work;
977 struct work_struct mmio_work;
978
979 struct drm_crtc *crtc;
980 struct drm_framebuffer *old_fb;
981 struct drm_i915_gem_object *pending_flip_obj;
982 struct drm_pending_vblank_event *event;
983 atomic_t pending;
984 u32 flip_count;
985 u32 gtt_offset;
986 struct drm_i915_gem_request *flip_queued_req;
987 u32 flip_queued_vblank;
988 u32 flip_ready_vblank;
989 unsigned int rotation;
990};
991
992struct intel_load_detect_pipe {
993 struct drm_atomic_state *restore_state;
994};
995
996static inline struct intel_encoder *
997intel_attached_encoder(struct drm_connector *connector)
998{
999 return to_intel_connector(connector)->encoder;
1000}
1001
1002static inline struct intel_digital_port *
1003enc_to_dig_port(struct drm_encoder *encoder)
1004{
1005 return container_of(encoder, struct intel_digital_port, base.base);
1006}
1007
1008static inline struct intel_dp_mst_encoder *
1009enc_to_mst(struct drm_encoder *encoder)
1010{
1011 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1012}
1013
1014static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1015{
1016 return &enc_to_dig_port(encoder)->dp;
1017}
1018
1019static inline struct intel_digital_port *
1020dp_to_dig_port(struct intel_dp *intel_dp)
1021{
1022 return container_of(intel_dp, struct intel_digital_port, dp);
1023}
1024
1025static inline struct intel_digital_port *
1026hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1027{
1028 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1029}
1030
1031/*
1032 * Returns the number of planes for this pipe, ie the number of sprites + 1
1033 * (primary plane). This doesn't count the cursor plane then.
1034 */
1035static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
1036{
1037 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
1038}
1039
1040/* intel_fifo_underrun.c */
1041bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1042 enum pipe pipe, bool enable);
1043bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1044 enum transcoder pch_transcoder,
1045 bool enable);
1046void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1047 enum pipe pipe);
1048void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1049 enum transcoder pch_transcoder);
1050void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1051void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1052
1053/* i915_irq.c */
1054void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1055void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1056void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1057void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1058void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1059void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1060void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1061u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1062void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1063void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1064static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1065{
1066 /*
1067 * We only use drm_irq_uninstall() at unload and VT switch, so
1068 * this is the only thing we need to check.
1069 */
1070 return dev_priv->pm.irqs_enabled;
1071}
1072
1073int intel_get_crtc_scanline(struct intel_crtc *crtc);
1074void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1075 unsigned int pipe_mask);
1076void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1077 unsigned int pipe_mask);
1078
1079/* intel_crt.c */
1080void intel_crt_init(struct drm_device *dev);
1081
1082
1083/* intel_ddi.c */
1084void intel_ddi_clk_select(struct intel_encoder *encoder,
1085 const struct intel_crtc_state *pipe_config);
1086void intel_prepare_ddi_buffer(struct intel_encoder *encoder);
1087void hsw_fdi_link_train(struct drm_crtc *crtc);
1088void intel_ddi_init(struct drm_device *dev, enum port port);
1089enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1090bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1091void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1092void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1093 enum transcoder cpu_transcoder);
1094void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1095void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1096bool intel_ddi_pll_select(struct intel_crtc *crtc,
1097 struct intel_crtc_state *crtc_state);
1098void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1099void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1100bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1101void intel_ddi_fdi_disable(struct drm_crtc *crtc);
1102void intel_ddi_get_config(struct intel_encoder *encoder,
1103 struct intel_crtc_state *pipe_config);
1104struct intel_encoder *
1105intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1106
1107void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1108void intel_ddi_clock_get(struct intel_encoder *encoder,
1109 struct intel_crtc_state *pipe_config);
1110void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1111uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1112
1113/* intel_frontbuffer.c */
1114void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
1115 enum fb_op_origin origin);
1116void intel_frontbuffer_flip_prepare(struct drm_device *dev,
1117 unsigned frontbuffer_bits);
1118void intel_frontbuffer_flip_complete(struct drm_device *dev,
1119 unsigned frontbuffer_bits);
1120void intel_frontbuffer_flip(struct drm_device *dev,
1121 unsigned frontbuffer_bits);
1122unsigned int intel_fb_align_height(struct drm_device *dev,
1123 unsigned int height,
1124 uint32_t pixel_format,
1125 uint64_t fb_format_modifier);
1126void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
1127 enum fb_op_origin origin);
1128u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1129 uint64_t fb_modifier, uint32_t pixel_format);
1130
1131/* intel_audio.c */
1132void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1133void intel_audio_codec_enable(struct intel_encoder *encoder);
1134void intel_audio_codec_disable(struct intel_encoder *encoder);
1135void i915_audio_component_init(struct drm_i915_private *dev_priv);
1136void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1137
1138/* intel_display.c */
1139void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
1140void intel_update_rawclk(struct drm_i915_private *dev_priv);
1141int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1142 const char *name, u32 reg, int ref_freq);
1143extern const struct drm_plane_funcs intel_plane_funcs;
1144void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1145unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1146bool intel_has_pending_fb_unpin(struct drm_device *dev);
1147void intel_mark_busy(struct drm_i915_private *dev_priv);
1148void intel_mark_idle(struct drm_i915_private *dev_priv);
1149void intel_crtc_restore_mode(struct drm_crtc *crtc);
1150int intel_display_suspend(struct drm_device *dev);
1151void intel_encoder_destroy(struct drm_encoder *encoder);
1152int intel_connector_init(struct intel_connector *);
1153struct intel_connector *intel_connector_alloc(void);
1154bool intel_connector_get_hw_state(struct intel_connector *connector);
1155void intel_connector_attach_encoder(struct intel_connector *connector,
1156 struct intel_encoder *encoder);
1157struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1158 struct drm_crtc *crtc);
1159enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1160int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1161 struct drm_file *file_priv);
1162enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1163 enum pipe pipe);
1164bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1165static inline void
1166intel_wait_for_vblank(struct drm_device *dev, int pipe)
1167{
1168 drm_wait_one_vblank(dev, pipe);
1169}
1170static inline void
1171intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1172{
1173 const struct intel_crtc *crtc =
1174 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1175
1176 if (crtc->active)
1177 intel_wait_for_vblank(dev, pipe);
1178}
1179
1180u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1181
1182int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1183void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1184 struct intel_digital_port *dport,
1185 unsigned int expected_mask);
1186bool intel_get_load_detect_pipe(struct drm_connector *connector,
1187 struct drm_display_mode *mode,
1188 struct intel_load_detect_pipe *old,
1189 struct drm_modeset_acquire_ctx *ctx);
1190void intel_release_load_detect_pipe(struct drm_connector *connector,
1191 struct intel_load_detect_pipe *old,
1192 struct drm_modeset_acquire_ctx *ctx);
1193int intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1194 unsigned int rotation);
1195void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1196struct drm_framebuffer *
1197__intel_framebuffer_create(struct drm_device *dev,
1198 struct drm_mode_fb_cmd2 *mode_cmd,
1199 struct drm_i915_gem_object *obj);
1200void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1201void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1202void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1203int intel_prepare_plane_fb(struct drm_plane *plane,
1204 const struct drm_plane_state *new_state);
1205void intel_cleanup_plane_fb(struct drm_plane *plane,
1206 const struct drm_plane_state *old_state);
1207int intel_plane_atomic_get_property(struct drm_plane *plane,
1208 const struct drm_plane_state *state,
1209 struct drm_property *property,
1210 uint64_t *val);
1211int intel_plane_atomic_set_property(struct drm_plane *plane,
1212 struct drm_plane_state *state,
1213 struct drm_property *property,
1214 uint64_t val);
1215int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1216 struct drm_plane_state *plane_state);
1217
1218unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1219 uint64_t fb_modifier, unsigned int cpp);
1220
1221static inline bool
1222intel_rotation_90_or_270(unsigned int rotation)
1223{
1224 return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1225}
1226
1227void intel_create_rotation_property(struct drm_device *dev,
1228 struct intel_plane *plane);
1229
1230void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231 enum pipe pipe);
1232
1233int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1234 const struct dpll *dpll);
1235void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1236int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1237
1238/* modesetting asserts */
1239void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1240 enum pipe pipe);
1241void assert_pll(struct drm_i915_private *dev_priv,
1242 enum pipe pipe, bool state);
1243#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1244#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1245void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1246#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1247#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1248void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1249 enum pipe pipe, bool state);
1250#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1251#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1252void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1253#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1254#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1255u32 intel_compute_tile_offset(int *x, int *y,
1256 const struct drm_framebuffer *fb, int plane,
1257 unsigned int pitch,
1258 unsigned int rotation);
1259void intel_prepare_reset(struct drm_i915_private *dev_priv);
1260void intel_finish_reset(struct drm_i915_private *dev_priv);
1261void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1262void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1263void broxton_init_cdclk(struct drm_i915_private *dev_priv);
1264void broxton_uninit_cdclk(struct drm_i915_private *dev_priv);
1265void broxton_ddi_phy_init(struct drm_i915_private *dev_priv);
1266void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv);
1267void broxton_ddi_phy_verify_state(struct drm_i915_private *dev_priv);
1268void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1269void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1270void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1271void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1272void skl_init_cdclk(struct drm_i915_private *dev_priv);
1273void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1274unsigned int skl_cdclk_get_vco(unsigned int freq);
1275void skl_enable_dc6(struct drm_i915_private *dev_priv);
1276void skl_disable_dc6(struct drm_i915_private *dev_priv);
1277void intel_dp_get_m_n(struct intel_crtc *crtc,
1278 struct intel_crtc_state *pipe_config);
1279void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1280int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1281bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1282 struct dpll *best_clock);
1283int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1284
1285bool intel_crtc_active(struct drm_crtc *crtc);
1286void hsw_enable_ips(struct intel_crtc *crtc);
1287void hsw_disable_ips(struct intel_crtc *crtc);
1288enum intel_display_power_domain
1289intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1290enum intel_display_power_domain
1291intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1292void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1293 struct intel_crtc_state *pipe_config);
1294
1295int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1296int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1297
1298u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
1299 struct drm_i915_gem_object *obj,
1300 unsigned int plane);
1301
1302u32 skl_plane_ctl_format(uint32_t pixel_format);
1303u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1304u32 skl_plane_ctl_rotation(unsigned int rotation);
1305
1306/* intel_csr.c */
1307void intel_csr_ucode_init(struct drm_i915_private *);
1308void intel_csr_load_program(struct drm_i915_private *);
1309void intel_csr_ucode_fini(struct drm_i915_private *);
1310void intel_csr_ucode_suspend(struct drm_i915_private *);
1311void intel_csr_ucode_resume(struct drm_i915_private *);
1312
1313/* intel_dp.c */
1314bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1315bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1316 struct intel_connector *intel_connector);
1317void intel_dp_set_link_params(struct intel_dp *intel_dp,
1318 const struct intel_crtc_state *pipe_config);
1319void intel_dp_start_link_train(struct intel_dp *intel_dp);
1320void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1321void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1322void intel_dp_encoder_reset(struct drm_encoder *encoder);
1323void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1324void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1325int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1326bool intel_dp_compute_config(struct intel_encoder *encoder,
1327 struct intel_crtc_state *pipe_config);
1328bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1329enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1330 bool long_hpd);
1331void intel_edp_backlight_on(struct intel_dp *intel_dp);
1332void intel_edp_backlight_off(struct intel_dp *intel_dp);
1333void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1334void intel_edp_panel_on(struct intel_dp *intel_dp);
1335void intel_edp_panel_off(struct intel_dp *intel_dp);
1336void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1337void intel_dp_mst_suspend(struct drm_device *dev);
1338void intel_dp_mst_resume(struct drm_device *dev);
1339int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1340int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1341void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1342void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1343uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1344void intel_plane_destroy(struct drm_plane *plane);
1345void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1346void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1347void intel_edp_drrs_invalidate(struct drm_device *dev,
1348 unsigned frontbuffer_bits);
1349void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1350bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1351 struct intel_digital_port *port);
1352
1353void
1354intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1355 uint8_t dp_train_pat);
1356void
1357intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1358void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1359uint8_t
1360intel_dp_voltage_max(struct intel_dp *intel_dp);
1361uint8_t
1362intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1363void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1364 uint8_t *link_bw, uint8_t *rate_select);
1365bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1366bool
1367intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1368
1369static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1370{
1371 return ~((1 << lane_count) - 1) & 0xf;
1372}
1373
1374/* intel_dp_aux_backlight.c */
1375int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1376
1377/* intel_dp_mst.c */
1378int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1379void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1380/* intel_dsi.c */
1381void intel_dsi_init(struct drm_device *dev);
1382
1383/* intel_dsi_dcs_backlight.c */
1384int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1385
1386/* intel_dvo.c */
1387void intel_dvo_init(struct drm_device *dev);
1388
1389
1390/* legacy fbdev emulation in intel_fbdev.c */
1391#ifdef CONFIG_DRM_FBDEV_EMULATION
1392extern int intel_fbdev_init(struct drm_device *dev);
1393extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1394extern void intel_fbdev_fini(struct drm_device *dev);
1395extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1396extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1397extern void intel_fbdev_restore_mode(struct drm_device *dev);
1398#else
1399static inline int intel_fbdev_init(struct drm_device *dev)
1400{
1401 return 0;
1402}
1403
1404static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1405{
1406}
1407
1408static inline void intel_fbdev_fini(struct drm_device *dev)
1409{
1410}
1411
1412static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1413{
1414}
1415
1416static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1417{
1418}
1419#endif
1420
1421/* intel_fbc.c */
1422void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1423 struct drm_atomic_state *state);
1424bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1425void intel_fbc_pre_update(struct intel_crtc *crtc);
1426void intel_fbc_post_update(struct intel_crtc *crtc);
1427void intel_fbc_init(struct drm_i915_private *dev_priv);
1428void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1429void intel_fbc_enable(struct intel_crtc *crtc);
1430void intel_fbc_disable(struct intel_crtc *crtc);
1431void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1432void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1433 unsigned int frontbuffer_bits,
1434 enum fb_op_origin origin);
1435void intel_fbc_flush(struct drm_i915_private *dev_priv,
1436 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1437void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1438
1439/* intel_hdmi.c */
1440void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1441void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1442 struct intel_connector *intel_connector);
1443struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1444bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1445 struct intel_crtc_state *pipe_config);
1446void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1447
1448
1449/* intel_lvds.c */
1450void intel_lvds_init(struct drm_device *dev);
1451bool intel_is_dual_link_lvds(struct drm_device *dev);
1452
1453
1454/* intel_modes.c */
1455int intel_connector_update_modes(struct drm_connector *connector,
1456 struct edid *edid);
1457int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1458void intel_attach_force_audio_property(struct drm_connector *connector);
1459void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1460void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1461
1462
1463/* intel_overlay.c */
1464void intel_setup_overlay(struct drm_i915_private *dev_priv);
1465void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1466int intel_overlay_switch_off(struct intel_overlay *overlay);
1467int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1468 struct drm_file *file_priv);
1469int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1470 struct drm_file *file_priv);
1471void intel_overlay_reset(struct drm_i915_private *dev_priv);
1472
1473
1474/* intel_panel.c */
1475int intel_panel_init(struct intel_panel *panel,
1476 struct drm_display_mode *fixed_mode,
1477 struct drm_display_mode *downclock_mode);
1478void intel_panel_fini(struct intel_panel *panel);
1479void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1480 struct drm_display_mode *adjusted_mode);
1481void intel_pch_panel_fitting(struct intel_crtc *crtc,
1482 struct intel_crtc_state *pipe_config,
1483 int fitting_mode);
1484void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1485 struct intel_crtc_state *pipe_config,
1486 int fitting_mode);
1487void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1488 u32 level, u32 max);
1489int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1490void intel_panel_enable_backlight(struct intel_connector *connector);
1491void intel_panel_disable_backlight(struct intel_connector *connector);
1492void intel_panel_destroy_backlight(struct drm_connector *connector);
1493enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1494extern struct drm_display_mode *intel_find_panel_downclock(
1495 struct drm_device *dev,
1496 struct drm_display_mode *fixed_mode,
1497 struct drm_connector *connector);
1498void intel_backlight_register(struct drm_device *dev);
1499void intel_backlight_unregister(struct drm_device *dev);
1500
1501
1502/* intel_psr.c */
1503void intel_psr_enable(struct intel_dp *intel_dp);
1504void intel_psr_disable(struct intel_dp *intel_dp);
1505void intel_psr_invalidate(struct drm_device *dev,
1506 unsigned frontbuffer_bits);
1507void intel_psr_flush(struct drm_device *dev,
1508 unsigned frontbuffer_bits,
1509 enum fb_op_origin origin);
1510void intel_psr_init(struct drm_device *dev);
1511void intel_psr_single_frame_update(struct drm_device *dev,
1512 unsigned frontbuffer_bits);
1513
1514/* intel_runtime_pm.c */
1515int intel_power_domains_init(struct drm_i915_private *);
1516void intel_power_domains_fini(struct drm_i915_private *);
1517void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1518void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1519void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1520void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1521void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1522const char *
1523intel_display_power_domain_str(enum intel_display_power_domain domain);
1524
1525bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1526 enum intel_display_power_domain domain);
1527bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1528 enum intel_display_power_domain domain);
1529void intel_display_power_get(struct drm_i915_private *dev_priv,
1530 enum intel_display_power_domain domain);
1531bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1532 enum intel_display_power_domain domain);
1533void intel_display_power_put(struct drm_i915_private *dev_priv,
1534 enum intel_display_power_domain domain);
1535
1536static inline void
1537assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1538{
1539 WARN_ONCE(dev_priv->pm.suspended,
1540 "Device suspended during HW access\n");
1541}
1542
1543static inline void
1544assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1545{
1546 assert_rpm_device_not_suspended(dev_priv);
1547 /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1548 * too much noise. */
1549 if (!atomic_read(&dev_priv->pm.wakeref_count))
1550 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1551}
1552
1553static inline int
1554assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1555{
1556 int seq = atomic_read(&dev_priv->pm.atomic_seq);
1557
1558 assert_rpm_wakelock_held(dev_priv);
1559
1560 return seq;
1561}
1562
1563static inline void
1564assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1565{
1566 WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1567 "HW access outside of RPM atomic section\n");
1568}
1569
1570/**
1571 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1572 * @dev_priv: i915 device instance
1573 *
1574 * This function disable asserts that check if we hold an RPM wakelock
1575 * reference, while keeping the device-not-suspended checks still enabled.
1576 * It's meant to be used only in special circumstances where our rule about
1577 * the wakelock refcount wrt. the device power state doesn't hold. According
1578 * to this rule at any point where we access the HW or want to keep the HW in
1579 * an active state we must hold an RPM wakelock reference acquired via one of
1580 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1581 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1582 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1583 * users should avoid using this function.
1584 *
1585 * Any calls to this function must have a symmetric call to
1586 * enable_rpm_wakeref_asserts().
1587 */
1588static inline void
1589disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1590{
1591 atomic_inc(&dev_priv->pm.wakeref_count);
1592}
1593
1594/**
1595 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1596 * @dev_priv: i915 device instance
1597 *
1598 * This function re-enables the RPM assert checks after disabling them with
1599 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1600 * circumstances otherwise its use should be avoided.
1601 *
1602 * Any calls to this function must have a symmetric call to
1603 * disable_rpm_wakeref_asserts().
1604 */
1605static inline void
1606enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1607{
1608 atomic_dec(&dev_priv->pm.wakeref_count);
1609}
1610
1611/* TODO: convert users of these to rely instead on proper RPM refcounting */
1612#define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv) \
1613 disable_rpm_wakeref_asserts(dev_priv)
1614
1615#define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv) \
1616 enable_rpm_wakeref_asserts(dev_priv)
1617
1618void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1619bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1620void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1621void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1622
1623void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1624
1625void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1626 bool override, unsigned int mask);
1627bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1628 enum dpio_channel ch, bool override);
1629
1630
1631/* intel_pm.c */
1632void intel_init_clock_gating(struct drm_device *dev);
1633void intel_suspend_hw(struct drm_device *dev);
1634int ilk_wm_max_level(const struct drm_device *dev);
1635void intel_update_watermarks(struct drm_crtc *crtc);
1636void intel_init_pm(struct drm_device *dev);
1637void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1638void intel_pm_setup(struct drm_device *dev);
1639void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1640void intel_gpu_ips_teardown(void);
1641void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1642void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1643void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1644void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1645void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1646void intel_reset_gt_powersave(struct drm_i915_private *dev_priv);
1647void gen6_update_ring_freq(struct drm_i915_private *dev_priv);
1648void gen6_rps_busy(struct drm_i915_private *dev_priv);
1649void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1650void gen6_rps_idle(struct drm_i915_private *dev_priv);
1651void gen6_rps_boost(struct drm_i915_private *dev_priv,
1652 struct intel_rps_client *rps,
1653 unsigned long submitted);
1654void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1655void vlv_wm_get_hw_state(struct drm_device *dev);
1656void ilk_wm_get_hw_state(struct drm_device *dev);
1657void skl_wm_get_hw_state(struct drm_device *dev);
1658void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1659 struct skl_ddb_allocation *ddb /* out */);
1660uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1661bool ilk_disable_lp_wm(struct drm_device *dev);
1662int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1663static inline int intel_enable_rc6(void)
1664{
1665 return i915.enable_rc6;
1666}
1667
1668/* intel_sdvo.c */
1669bool intel_sdvo_init(struct drm_device *dev,
1670 i915_reg_t reg, enum port port);
1671
1672
1673/* intel_sprite.c */
1674int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1675int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1676 struct drm_file *file_priv);
1677void intel_pipe_update_start(struct intel_crtc *crtc);
1678void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1679
1680/* intel_tv.c */
1681void intel_tv_init(struct drm_device *dev);
1682
1683/* intel_atomic.c */
1684int intel_connector_atomic_get_property(struct drm_connector *connector,
1685 const struct drm_connector_state *state,
1686 struct drm_property *property,
1687 uint64_t *val);
1688struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1689void intel_crtc_destroy_state(struct drm_crtc *crtc,
1690 struct drm_crtc_state *state);
1691struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1692void intel_atomic_state_clear(struct drm_atomic_state *);
1693struct intel_shared_dpll_config *
1694intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1695
1696static inline struct intel_crtc_state *
1697intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1698 struct intel_crtc *crtc)
1699{
1700 struct drm_crtc_state *crtc_state;
1701 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1702 if (IS_ERR(crtc_state))
1703 return ERR_CAST(crtc_state);
1704
1705 return to_intel_crtc_state(crtc_state);
1706}
1707
1708static inline struct intel_plane_state *
1709intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1710 struct intel_plane *plane)
1711{
1712 struct drm_plane_state *plane_state;
1713
1714 plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1715
1716 return to_intel_plane_state(plane_state);
1717}
1718
1719int intel_atomic_setup_scalers(struct drm_device *dev,
1720 struct intel_crtc *intel_crtc,
1721 struct intel_crtc_state *crtc_state);
1722
1723/* intel_atomic_plane.c */
1724struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1725struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1726void intel_plane_destroy_state(struct drm_plane *plane,
1727 struct drm_plane_state *state);
1728extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1729
1730/* intel_color.c */
1731void intel_color_init(struct drm_crtc *crtc);
1732int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1733void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1734void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1735
1736#endif /* __INTEL_DRV_H__ */
Linux kernel - Deliverables
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