| 1 | /* |
| 2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> |
| 3 | * Copyright © 2006-2009 Intel Corporation |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice (including the next |
| 13 | * paragraph) shall be included in all copies or substantial portions of the |
| 14 | * Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 22 | * DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: |
| 25 | * Eric Anholt <eric@anholt.net> |
| 26 | * Jesse Barnes <jesse.barnes@intel.com> |
| 27 | */ |
| 28 | |
| 29 | #include <linux/i2c.h> |
| 30 | #include <linux/slab.h> |
| 31 | #include <linux/delay.h> |
| 32 | #include "drmP.h" |
| 33 | #include "drm.h" |
| 34 | #include "drm_crtc.h" |
| 35 | #include "drm_edid.h" |
| 36 | #include "intel_drv.h" |
| 37 | #include "i915_drm.h" |
| 38 | #include "i915_drv.h" |
| 39 | |
| 40 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
| 41 | { |
| 42 | return container_of(encoder, struct intel_hdmi, base.base); |
| 43 | } |
| 44 | |
| 45 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
| 46 | { |
| 47 | return container_of(intel_attached_encoder(connector), |
| 48 | struct intel_hdmi, base); |
| 49 | } |
| 50 | |
| 51 | void intel_dip_infoframe_csum(struct dip_infoframe *frame) |
| 52 | { |
| 53 | uint8_t *data = (uint8_t *)frame; |
| 54 | uint8_t sum = 0; |
| 55 | unsigned i; |
| 56 | |
| 57 | frame->checksum = 0; |
| 58 | frame->ecc = 0; |
| 59 | |
| 60 | for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
| 61 | sum += data[i]; |
| 62 | |
| 63 | frame->checksum = 0x100 - sum; |
| 64 | } |
| 65 | |
| 66 | static u32 g4x_infoframe_index(struct dip_infoframe *frame) |
| 67 | { |
| 68 | switch (frame->type) { |
| 69 | case DIP_TYPE_AVI: |
| 70 | return VIDEO_DIP_SELECT_AVI; |
| 71 | case DIP_TYPE_SPD: |
| 72 | return VIDEO_DIP_SELECT_SPD; |
| 73 | default: |
| 74 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); |
| 75 | return 0; |
| 76 | } |
| 77 | } |
| 78 | |
| 79 | static u32 g4x_infoframe_enable(struct dip_infoframe *frame) |
| 80 | { |
| 81 | switch (frame->type) { |
| 82 | case DIP_TYPE_AVI: |
| 83 | return VIDEO_DIP_ENABLE_AVI; |
| 84 | case DIP_TYPE_SPD: |
| 85 | return VIDEO_DIP_ENABLE_SPD; |
| 86 | default: |
| 87 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); |
| 88 | return 0; |
| 89 | } |
| 90 | } |
| 91 | |
| 92 | static u32 hsw_infoframe_enable(struct dip_infoframe *frame) |
| 93 | { |
| 94 | switch (frame->type) { |
| 95 | case DIP_TYPE_AVI: |
| 96 | return VIDEO_DIP_ENABLE_AVI_HSW; |
| 97 | case DIP_TYPE_SPD: |
| 98 | return VIDEO_DIP_ENABLE_SPD_HSW; |
| 99 | default: |
| 100 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); |
| 101 | return 0; |
| 102 | } |
| 103 | } |
| 104 | |
| 105 | static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe) |
| 106 | { |
| 107 | switch (frame->type) { |
| 108 | case DIP_TYPE_AVI: |
| 109 | return HSW_TVIDEO_DIP_AVI_DATA(pipe); |
| 110 | case DIP_TYPE_SPD: |
| 111 | return HSW_TVIDEO_DIP_SPD_DATA(pipe); |
| 112 | default: |
| 113 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); |
| 114 | return 0; |
| 115 | } |
| 116 | } |
| 117 | |
| 118 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
| 119 | struct dip_infoframe *frame) |
| 120 | { |
| 121 | uint32_t *data = (uint32_t *)frame; |
| 122 | struct drm_device *dev = encoder->dev; |
| 123 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 124 | u32 val = I915_READ(VIDEO_DIP_CTL); |
| 125 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
| 126 | |
| 127 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
| 128 | |
| 129 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
| 130 | val |= g4x_infoframe_index(frame); |
| 131 | |
| 132 | val &= ~g4x_infoframe_enable(frame); |
| 133 | |
| 134 | I915_WRITE(VIDEO_DIP_CTL, val); |
| 135 | |
| 136 | for (i = 0; i < len; i += 4) { |
| 137 | I915_WRITE(VIDEO_DIP_DATA, *data); |
| 138 | data++; |
| 139 | } |
| 140 | |
| 141 | val |= g4x_infoframe_enable(frame); |
| 142 | val &= ~VIDEO_DIP_FREQ_MASK; |
| 143 | val |= VIDEO_DIP_FREQ_VSYNC; |
| 144 | |
| 145 | I915_WRITE(VIDEO_DIP_CTL, val); |
| 146 | } |
| 147 | |
| 148 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
| 149 | struct dip_infoframe *frame) |
| 150 | { |
| 151 | uint32_t *data = (uint32_t *)frame; |
| 152 | struct drm_device *dev = encoder->dev; |
| 153 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 154 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
| 155 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
| 156 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
| 157 | u32 val = I915_READ(reg); |
| 158 | |
| 159 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
| 160 | |
| 161 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
| 162 | val |= g4x_infoframe_index(frame); |
| 163 | |
| 164 | val &= ~g4x_infoframe_enable(frame); |
| 165 | |
| 166 | I915_WRITE(reg, val); |
| 167 | |
| 168 | for (i = 0; i < len; i += 4) { |
| 169 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
| 170 | data++; |
| 171 | } |
| 172 | |
| 173 | val |= g4x_infoframe_enable(frame); |
| 174 | val &= ~VIDEO_DIP_FREQ_MASK; |
| 175 | val |= VIDEO_DIP_FREQ_VSYNC; |
| 176 | |
| 177 | I915_WRITE(reg, val); |
| 178 | } |
| 179 | |
| 180 | static void cpt_write_infoframe(struct drm_encoder *encoder, |
| 181 | struct dip_infoframe *frame) |
| 182 | { |
| 183 | uint32_t *data = (uint32_t *)frame; |
| 184 | struct drm_device *dev = encoder->dev; |
| 185 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 186 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
| 187 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
| 188 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
| 189 | u32 val = I915_READ(reg); |
| 190 | |
| 191 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
| 192 | |
| 193 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
| 194 | val |= g4x_infoframe_index(frame); |
| 195 | |
| 196 | /* The DIP control register spec says that we need to update the AVI |
| 197 | * infoframe without clearing its enable bit */ |
| 198 | if (frame->type != DIP_TYPE_AVI) |
| 199 | val &= ~g4x_infoframe_enable(frame); |
| 200 | |
| 201 | I915_WRITE(reg, val); |
| 202 | |
| 203 | for (i = 0; i < len; i += 4) { |
| 204 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
| 205 | data++; |
| 206 | } |
| 207 | |
| 208 | val |= g4x_infoframe_enable(frame); |
| 209 | val &= ~VIDEO_DIP_FREQ_MASK; |
| 210 | val |= VIDEO_DIP_FREQ_VSYNC; |
| 211 | |
| 212 | I915_WRITE(reg, val); |
| 213 | } |
| 214 | |
| 215 | static void vlv_write_infoframe(struct drm_encoder *encoder, |
| 216 | struct dip_infoframe *frame) |
| 217 | { |
| 218 | uint32_t *data = (uint32_t *)frame; |
| 219 | struct drm_device *dev = encoder->dev; |
| 220 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 221 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
| 222 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
| 223 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
| 224 | u32 val = I915_READ(reg); |
| 225 | |
| 226 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
| 227 | |
| 228 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
| 229 | val |= g4x_infoframe_index(frame); |
| 230 | |
| 231 | val &= ~g4x_infoframe_enable(frame); |
| 232 | |
| 233 | I915_WRITE(reg, val); |
| 234 | |
| 235 | for (i = 0; i < len; i += 4) { |
| 236 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
| 237 | data++; |
| 238 | } |
| 239 | |
| 240 | val |= g4x_infoframe_enable(frame); |
| 241 | val &= ~VIDEO_DIP_FREQ_MASK; |
| 242 | val |= VIDEO_DIP_FREQ_VSYNC; |
| 243 | |
| 244 | I915_WRITE(reg, val); |
| 245 | } |
| 246 | |
| 247 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
| 248 | struct dip_infoframe *frame) |
| 249 | { |
| 250 | uint32_t *data = (uint32_t *)frame; |
| 251 | struct drm_device *dev = encoder->dev; |
| 252 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 253 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
| 254 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); |
| 255 | u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe); |
| 256 | unsigned int i, len = DIP_HEADER_SIZE + frame->len; |
| 257 | u32 val = I915_READ(ctl_reg); |
| 258 | |
| 259 | if (data_reg == 0) |
| 260 | return; |
| 261 | |
| 262 | val &= ~hsw_infoframe_enable(frame); |
| 263 | I915_WRITE(ctl_reg, val); |
| 264 | |
| 265 | for (i = 0; i < len; i += 4) { |
| 266 | I915_WRITE(data_reg + i, *data); |
| 267 | data++; |
| 268 | } |
| 269 | |
| 270 | val |= hsw_infoframe_enable(frame); |
| 271 | I915_WRITE(ctl_reg, val); |
| 272 | } |
| 273 | |
| 274 | static void intel_set_infoframe(struct drm_encoder *encoder, |
| 275 | struct dip_infoframe *frame) |
| 276 | { |
| 277 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
| 278 | |
| 279 | intel_dip_infoframe_csum(frame); |
| 280 | intel_hdmi->write_infoframe(encoder, frame); |
| 281 | } |
| 282 | |
| 283 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
| 284 | struct drm_display_mode *adjusted_mode) |
| 285 | { |
| 286 | struct dip_infoframe avi_if = { |
| 287 | .type = DIP_TYPE_AVI, |
| 288 | .ver = DIP_VERSION_AVI, |
| 289 | .len = DIP_LEN_AVI, |
| 290 | }; |
| 291 | |
| 292 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
| 293 | avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; |
| 294 | |
| 295 | intel_set_infoframe(encoder, &avi_if); |
| 296 | } |
| 297 | |
| 298 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
| 299 | { |
| 300 | struct dip_infoframe spd_if; |
| 301 | |
| 302 | memset(&spd_if, 0, sizeof(spd_if)); |
| 303 | spd_if.type = DIP_TYPE_SPD; |
| 304 | spd_if.ver = DIP_VERSION_SPD; |
| 305 | spd_if.len = DIP_LEN_SPD; |
| 306 | strcpy(spd_if.body.spd.vn, "Intel"); |
| 307 | strcpy(spd_if.body.spd.pd, "Integrated gfx"); |
| 308 | spd_if.body.spd.sdi = DIP_SPD_PC; |
| 309 | |
| 310 | intel_set_infoframe(encoder, &spd_if); |
| 311 | } |
| 312 | |
| 313 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
| 314 | struct drm_display_mode *adjusted_mode) |
| 315 | { |
| 316 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
| 317 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
| 318 | u32 reg = VIDEO_DIP_CTL; |
| 319 | u32 val = I915_READ(reg); |
| 320 | |
| 321 | /* If the registers were not initialized yet, they might be zeroes, |
| 322 | * which means we're selecting the AVI DIP and we're setting its |
| 323 | * frequency to once. This seems to really confuse the HW and make |
| 324 | * things stop working (the register spec says the AVI always needs to |
| 325 | * be sent every VSync). So here we avoid writing to the register more |
| 326 | * than we need and also explicitly select the AVI DIP and explicitly |
| 327 | * set its frequency to every VSync. Avoiding to write it twice seems to |
| 328 | * be enough to solve the problem, but being defensive shouldn't hurt us |
| 329 | * either. */ |
| 330 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
| 331 | |
| 332 | if (!intel_hdmi->has_hdmi_sink) { |
| 333 | if (!(val & VIDEO_DIP_ENABLE)) |
| 334 | return; |
| 335 | val &= ~VIDEO_DIP_ENABLE; |
| 336 | I915_WRITE(reg, val); |
| 337 | return; |
| 338 | } |
| 339 | |
| 340 | val &= ~VIDEO_DIP_PORT_MASK; |
| 341 | switch (intel_hdmi->sdvox_reg) { |
| 342 | case SDVOB: |
| 343 | val |= VIDEO_DIP_PORT_B; |
| 344 | break; |
| 345 | case SDVOC: |
| 346 | val |= VIDEO_DIP_PORT_C; |
| 347 | break; |
| 348 | default: |
| 349 | return; |
| 350 | } |
| 351 | |
| 352 | val |= VIDEO_DIP_ENABLE; |
| 353 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
| 354 | |
| 355 | I915_WRITE(reg, val); |
| 356 | |
| 357 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
| 358 | intel_hdmi_set_spd_infoframe(encoder); |
| 359 | } |
| 360 | |
| 361 | static void ibx_set_infoframes(struct drm_encoder *encoder, |
| 362 | struct drm_display_mode *adjusted_mode) |
| 363 | { |
| 364 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
| 365 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
| 366 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
| 367 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
| 368 | u32 val = I915_READ(reg); |
| 369 | |
| 370 | /* See the big comment in g4x_set_infoframes() */ |
| 371 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
| 372 | |
| 373 | if (!intel_hdmi->has_hdmi_sink) { |
| 374 | if (!(val & VIDEO_DIP_ENABLE)) |
| 375 | return; |
| 376 | val &= ~VIDEO_DIP_ENABLE; |
| 377 | I915_WRITE(reg, val); |
| 378 | return; |
| 379 | } |
| 380 | |
| 381 | val &= ~VIDEO_DIP_PORT_MASK; |
| 382 | switch (intel_hdmi->sdvox_reg) { |
| 383 | case HDMIB: |
| 384 | val |= VIDEO_DIP_PORT_B; |
| 385 | break; |
| 386 | case HDMIC: |
| 387 | val |= VIDEO_DIP_PORT_C; |
| 388 | break; |
| 389 | case HDMID: |
| 390 | val |= VIDEO_DIP_PORT_D; |
| 391 | break; |
| 392 | default: |
| 393 | return; |
| 394 | } |
| 395 | |
| 396 | val |= VIDEO_DIP_ENABLE; |
| 397 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
| 398 | VIDEO_DIP_ENABLE_GCP); |
| 399 | |
| 400 | I915_WRITE(reg, val); |
| 401 | |
| 402 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
| 403 | intel_hdmi_set_spd_infoframe(encoder); |
| 404 | } |
| 405 | |
| 406 | static void cpt_set_infoframes(struct drm_encoder *encoder, |
| 407 | struct drm_display_mode *adjusted_mode) |
| 408 | { |
| 409 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
| 410 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
| 411 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
| 412 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
| 413 | u32 val = I915_READ(reg); |
| 414 | |
| 415 | /* See the big comment in g4x_set_infoframes() */ |
| 416 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
| 417 | |
| 418 | if (!intel_hdmi->has_hdmi_sink) { |
| 419 | if (!(val & VIDEO_DIP_ENABLE)) |
| 420 | return; |
| 421 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); |
| 422 | I915_WRITE(reg, val); |
| 423 | return; |
| 424 | } |
| 425 | |
| 426 | /* Set both together, unset both together: see the spec. */ |
| 427 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; |
| 428 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
| 429 | VIDEO_DIP_ENABLE_GCP); |
| 430 | |
| 431 | I915_WRITE(reg, val); |
| 432 | |
| 433 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
| 434 | intel_hdmi_set_spd_infoframe(encoder); |
| 435 | } |
| 436 | |
| 437 | static void vlv_set_infoframes(struct drm_encoder *encoder, |
| 438 | struct drm_display_mode *adjusted_mode) |
| 439 | { |
| 440 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
| 441 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
| 442 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
| 443 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
| 444 | u32 val = I915_READ(reg); |
| 445 | |
| 446 | /* See the big comment in g4x_set_infoframes() */ |
| 447 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
| 448 | |
| 449 | if (!intel_hdmi->has_hdmi_sink) { |
| 450 | if (!(val & VIDEO_DIP_ENABLE)) |
| 451 | return; |
| 452 | val &= ~VIDEO_DIP_ENABLE; |
| 453 | I915_WRITE(reg, val); |
| 454 | return; |
| 455 | } |
| 456 | |
| 457 | val |= VIDEO_DIP_ENABLE; |
| 458 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
| 459 | VIDEO_DIP_ENABLE_GCP); |
| 460 | |
| 461 | I915_WRITE(reg, val); |
| 462 | |
| 463 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
| 464 | intel_hdmi_set_spd_infoframe(encoder); |
| 465 | } |
| 466 | |
| 467 | static void hsw_set_infoframes(struct drm_encoder *encoder, |
| 468 | struct drm_display_mode *adjusted_mode) |
| 469 | { |
| 470 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
| 471 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
| 472 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
| 473 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); |
| 474 | u32 val = I915_READ(reg); |
| 475 | |
| 476 | if (!intel_hdmi->has_hdmi_sink) { |
| 477 | I915_WRITE(reg, 0); |
| 478 | return; |
| 479 | } |
| 480 | |
| 481 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
| 482 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); |
| 483 | |
| 484 | I915_WRITE(reg, val); |
| 485 | |
| 486 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
| 487 | intel_hdmi_set_spd_infoframe(encoder); |
| 488 | } |
| 489 | |
| 490 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
| 491 | struct drm_display_mode *mode, |
| 492 | struct drm_display_mode *adjusted_mode) |
| 493 | { |
| 494 | struct drm_device *dev = encoder->dev; |
| 495 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 496 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
| 497 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
| 498 | u32 sdvox; |
| 499 | |
| 500 | sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE; |
| 501 | if (!HAS_PCH_SPLIT(dev)) |
| 502 | sdvox |= intel_hdmi->color_range; |
| 503 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 504 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; |
| 505 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 506 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; |
| 507 | |
| 508 | if (intel_crtc->bpp > 24) |
| 509 | sdvox |= COLOR_FORMAT_12bpc; |
| 510 | else |
| 511 | sdvox |= COLOR_FORMAT_8bpc; |
| 512 | |
| 513 | /* Required on CPT */ |
| 514 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) |
| 515 | sdvox |= HDMI_MODE_SELECT; |
| 516 | |
| 517 | if (intel_hdmi->has_audio) { |
| 518 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
| 519 | pipe_name(intel_crtc->pipe)); |
| 520 | sdvox |= SDVO_AUDIO_ENABLE; |
| 521 | sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
| 522 | intel_write_eld(encoder, adjusted_mode); |
| 523 | } |
| 524 | |
| 525 | if (HAS_PCH_CPT(dev)) |
| 526 | sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); |
| 527 | else if (intel_crtc->pipe == 1) |
| 528 | sdvox |= SDVO_PIPE_B_SELECT; |
| 529 | |
| 530 | I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
| 531 | POSTING_READ(intel_hdmi->sdvox_reg); |
| 532 | |
| 533 | intel_hdmi->set_infoframes(encoder, adjusted_mode); |
| 534 | } |
| 535 | |
| 536 | static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) |
| 537 | { |
| 538 | struct drm_device *dev = encoder->dev; |
| 539 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 540 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
| 541 | u32 temp; |
| 542 | u32 enable_bits = SDVO_ENABLE; |
| 543 | |
| 544 | if (intel_hdmi->has_audio) |
| 545 | enable_bits |= SDVO_AUDIO_ENABLE; |
| 546 | |
| 547 | temp = I915_READ(intel_hdmi->sdvox_reg); |
| 548 | |
| 549 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
| 550 | * we do this anyway which shows more stable in testing. |
| 551 | */ |
| 552 | if (HAS_PCH_SPLIT(dev)) { |
| 553 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
| 554 | POSTING_READ(intel_hdmi->sdvox_reg); |
| 555 | } |
| 556 | |
| 557 | if (mode != DRM_MODE_DPMS_ON) { |
| 558 | temp &= ~enable_bits; |
| 559 | } else { |
| 560 | temp |= enable_bits; |
| 561 | } |
| 562 | |
| 563 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
| 564 | POSTING_READ(intel_hdmi->sdvox_reg); |
| 565 | |
| 566 | /* HW workaround, need to write this twice for issue that may result |
| 567 | * in first write getting masked. |
| 568 | */ |
| 569 | if (HAS_PCH_SPLIT(dev)) { |
| 570 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
| 571 | POSTING_READ(intel_hdmi->sdvox_reg); |
| 572 | } |
| 573 | } |
| 574 | |
| 575 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
| 576 | struct drm_display_mode *mode) |
| 577 | { |
| 578 | if (mode->clock > 165000) |
| 579 | return MODE_CLOCK_HIGH; |
| 580 | if (mode->clock < 20000) |
| 581 | return MODE_CLOCK_LOW; |
| 582 | |
| 583 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 584 | return MODE_NO_DBLESCAN; |
| 585 | |
| 586 | return MODE_OK; |
| 587 | } |
| 588 | |
| 589 | static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, |
| 590 | struct drm_display_mode *mode, |
| 591 | struct drm_display_mode *adjusted_mode) |
| 592 | { |
| 593 | return true; |
| 594 | } |
| 595 | |
| 596 | static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi) |
| 597 | { |
| 598 | struct drm_device *dev = intel_hdmi->base.base.dev; |
| 599 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 600 | uint32_t bit; |
| 601 | |
| 602 | switch (intel_hdmi->sdvox_reg) { |
| 603 | case SDVOB: |
| 604 | bit = HDMIB_HOTPLUG_LIVE_STATUS; |
| 605 | break; |
| 606 | case SDVOC: |
| 607 | bit = HDMIC_HOTPLUG_LIVE_STATUS; |
| 608 | break; |
| 609 | default: |
| 610 | bit = 0; |
| 611 | break; |
| 612 | } |
| 613 | |
| 614 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
| 615 | } |
| 616 | |
| 617 | static enum drm_connector_status |
| 618 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
| 619 | { |
| 620 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
| 621 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 622 | struct edid *edid; |
| 623 | enum drm_connector_status status = connector_status_disconnected; |
| 624 | |
| 625 | if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi)) |
| 626 | return status; |
| 627 | |
| 628 | intel_hdmi->has_hdmi_sink = false; |
| 629 | intel_hdmi->has_audio = false; |
| 630 | edid = drm_get_edid(connector, |
| 631 | intel_gmbus_get_adapter(dev_priv, |
| 632 | intel_hdmi->ddc_bus)); |
| 633 | |
| 634 | if (edid) { |
| 635 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
| 636 | status = connector_status_connected; |
| 637 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
| 638 | intel_hdmi->has_hdmi_sink = |
| 639 | drm_detect_hdmi_monitor(edid); |
| 640 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
| 641 | } |
| 642 | connector->display_info.raw_edid = NULL; |
| 643 | kfree(edid); |
| 644 | } |
| 645 | |
| 646 | if (status == connector_status_connected) { |
| 647 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
| 648 | intel_hdmi->has_audio = |
| 649 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); |
| 650 | } |
| 651 | |
| 652 | return status; |
| 653 | } |
| 654 | |
| 655 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
| 656 | { |
| 657 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
| 658 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 659 | |
| 660 | /* We should parse the EDID data and find out if it's an HDMI sink so |
| 661 | * we can send audio to it. |
| 662 | */ |
| 663 | |
| 664 | return intel_ddc_get_modes(connector, |
| 665 | intel_gmbus_get_adapter(dev_priv, |
| 666 | intel_hdmi->ddc_bus)); |
| 667 | } |
| 668 | |
| 669 | static bool |
| 670 | intel_hdmi_detect_audio(struct drm_connector *connector) |
| 671 | { |
| 672 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
| 673 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 674 | struct edid *edid; |
| 675 | bool has_audio = false; |
| 676 | |
| 677 | edid = drm_get_edid(connector, |
| 678 | intel_gmbus_get_adapter(dev_priv, |
| 679 | intel_hdmi->ddc_bus)); |
| 680 | if (edid) { |
| 681 | if (edid->input & DRM_EDID_INPUT_DIGITAL) |
| 682 | has_audio = drm_detect_monitor_audio(edid); |
| 683 | |
| 684 | connector->display_info.raw_edid = NULL; |
| 685 | kfree(edid); |
| 686 | } |
| 687 | |
| 688 | return has_audio; |
| 689 | } |
| 690 | |
| 691 | static int |
| 692 | intel_hdmi_set_property(struct drm_connector *connector, |
| 693 | struct drm_property *property, |
| 694 | uint64_t val) |
| 695 | { |
| 696 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
| 697 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 698 | int ret; |
| 699 | |
| 700 | ret = drm_connector_property_set_value(connector, property, val); |
| 701 | if (ret) |
| 702 | return ret; |
| 703 | |
| 704 | if (property == dev_priv->force_audio_property) { |
| 705 | enum hdmi_force_audio i = val; |
| 706 | bool has_audio; |
| 707 | |
| 708 | if (i == intel_hdmi->force_audio) |
| 709 | return 0; |
| 710 | |
| 711 | intel_hdmi->force_audio = i; |
| 712 | |
| 713 | if (i == HDMI_AUDIO_AUTO) |
| 714 | has_audio = intel_hdmi_detect_audio(connector); |
| 715 | else |
| 716 | has_audio = (i == HDMI_AUDIO_ON); |
| 717 | |
| 718 | if (i == HDMI_AUDIO_OFF_DVI) |
| 719 | intel_hdmi->has_hdmi_sink = 0; |
| 720 | |
| 721 | intel_hdmi->has_audio = has_audio; |
| 722 | goto done; |
| 723 | } |
| 724 | |
| 725 | if (property == dev_priv->broadcast_rgb_property) { |
| 726 | if (val == !!intel_hdmi->color_range) |
| 727 | return 0; |
| 728 | |
| 729 | intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; |
| 730 | goto done; |
| 731 | } |
| 732 | |
| 733 | return -EINVAL; |
| 734 | |
| 735 | done: |
| 736 | if (intel_hdmi->base.base.crtc) { |
| 737 | struct drm_crtc *crtc = intel_hdmi->base.base.crtc; |
| 738 | drm_crtc_helper_set_mode(crtc, &crtc->mode, |
| 739 | crtc->x, crtc->y, |
| 740 | crtc->fb); |
| 741 | } |
| 742 | |
| 743 | return 0; |
| 744 | } |
| 745 | |
| 746 | static void intel_hdmi_destroy(struct drm_connector *connector) |
| 747 | { |
| 748 | drm_sysfs_connector_remove(connector); |
| 749 | drm_connector_cleanup(connector); |
| 750 | kfree(connector); |
| 751 | } |
| 752 | |
| 753 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = { |
| 754 | .dpms = intel_ddi_dpms, |
| 755 | .mode_fixup = intel_hdmi_mode_fixup, |
| 756 | .prepare = intel_encoder_prepare, |
| 757 | .mode_set = intel_ddi_mode_set, |
| 758 | .commit = intel_encoder_commit, |
| 759 | }; |
| 760 | |
| 761 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { |
| 762 | .dpms = intel_hdmi_dpms, |
| 763 | .mode_fixup = intel_hdmi_mode_fixup, |
| 764 | .prepare = intel_encoder_prepare, |
| 765 | .mode_set = intel_hdmi_mode_set, |
| 766 | .commit = intel_encoder_commit, |
| 767 | }; |
| 768 | |
| 769 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
| 770 | .dpms = drm_helper_connector_dpms, |
| 771 | .detect = intel_hdmi_detect, |
| 772 | .fill_modes = drm_helper_probe_single_connector_modes, |
| 773 | .set_property = intel_hdmi_set_property, |
| 774 | .destroy = intel_hdmi_destroy, |
| 775 | }; |
| 776 | |
| 777 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { |
| 778 | .get_modes = intel_hdmi_get_modes, |
| 779 | .mode_valid = intel_hdmi_mode_valid, |
| 780 | .best_encoder = intel_best_encoder, |
| 781 | }; |
| 782 | |
| 783 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
| 784 | .destroy = intel_encoder_destroy, |
| 785 | }; |
| 786 | |
| 787 | static void |
| 788 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) |
| 789 | { |
| 790 | intel_attach_force_audio_property(connector); |
| 791 | intel_attach_broadcast_rgb_property(connector); |
| 792 | } |
| 793 | |
| 794 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) |
| 795 | { |
| 796 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 797 | struct drm_connector *connector; |
| 798 | struct intel_encoder *intel_encoder; |
| 799 | struct intel_connector *intel_connector; |
| 800 | struct intel_hdmi *intel_hdmi; |
| 801 | int i; |
| 802 | |
| 803 | intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); |
| 804 | if (!intel_hdmi) |
| 805 | return; |
| 806 | |
| 807 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
| 808 | if (!intel_connector) { |
| 809 | kfree(intel_hdmi); |
| 810 | return; |
| 811 | } |
| 812 | |
| 813 | intel_encoder = &intel_hdmi->base; |
| 814 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
| 815 | DRM_MODE_ENCODER_TMDS); |
| 816 | |
| 817 | connector = &intel_connector->base; |
| 818 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
| 819 | DRM_MODE_CONNECTOR_HDMIA); |
| 820 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
| 821 | |
| 822 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
| 823 | |
| 824 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
| 825 | connector->interlace_allowed = 1; |
| 826 | connector->doublescan_allowed = 0; |
| 827 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
| 828 | |
| 829 | /* Set up the DDC bus. */ |
| 830 | if (sdvox_reg == SDVOB) { |
| 831 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); |
| 832 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
| 833 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
| 834 | } else if (sdvox_reg == SDVOC) { |
| 835 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); |
| 836 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
| 837 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
| 838 | } else if (sdvox_reg == HDMIB) { |
| 839 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); |
| 840 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
| 841 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
| 842 | } else if (sdvox_reg == HDMIC) { |
| 843 | intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT); |
| 844 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
| 845 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
| 846 | } else if (sdvox_reg == HDMID) { |
| 847 | intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT); |
| 848 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
| 849 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
| 850 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_B)) { |
| 851 | DRM_DEBUG_DRIVER("LPT: detected output on DDI B\n"); |
| 852 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); |
| 853 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
| 854 | intel_hdmi->ddi_port = PORT_B; |
| 855 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
| 856 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_C)) { |
| 857 | DRM_DEBUG_DRIVER("LPT: detected output on DDI C\n"); |
| 858 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); |
| 859 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
| 860 | intel_hdmi->ddi_port = PORT_C; |
| 861 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
| 862 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_D)) { |
| 863 | DRM_DEBUG_DRIVER("LPT: detected output on DDI D\n"); |
| 864 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); |
| 865 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
| 866 | intel_hdmi->ddi_port = PORT_D; |
| 867 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
| 868 | } else { |
| 869 | /* If we got an unknown sdvox_reg, things are pretty much broken |
| 870 | * in a way that we should let the kernel know about it */ |
| 871 | BUG(); |
| 872 | } |
| 873 | |
| 874 | intel_hdmi->sdvox_reg = sdvox_reg; |
| 875 | |
| 876 | if (!HAS_PCH_SPLIT(dev)) { |
| 877 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
| 878 | intel_hdmi->set_infoframes = g4x_set_infoframes; |
| 879 | I915_WRITE(VIDEO_DIP_CTL, 0); |
| 880 | } else if (IS_VALLEYVIEW(dev)) { |
| 881 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
| 882 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
| 883 | for_each_pipe(i) |
| 884 | I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0); |
| 885 | } else if (IS_HASWELL(dev)) { |
| 886 | /* FIXME: Haswell has a new set of DIP frame registers, but we are |
| 887 | * just doing the minimal required for HDMI to work at this stage. |
| 888 | */ |
| 889 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
| 890 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
| 891 | for_each_pipe(i) |
| 892 | I915_WRITE(HSW_TVIDEO_DIP_CTL(i), 0); |
| 893 | } else if (HAS_PCH_IBX(dev)) { |
| 894 | intel_hdmi->write_infoframe = ibx_write_infoframe; |
| 895 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
| 896 | for_each_pipe(i) |
| 897 | I915_WRITE(TVIDEO_DIP_CTL(i), 0); |
| 898 | } else { |
| 899 | intel_hdmi->write_infoframe = cpt_write_infoframe; |
| 900 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
| 901 | for_each_pipe(i) |
| 902 | I915_WRITE(TVIDEO_DIP_CTL(i), 0); |
| 903 | } |
| 904 | |
| 905 | if (IS_HASWELL(dev)) |
| 906 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs_hsw); |
| 907 | else |
| 908 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); |
| 909 | |
| 910 | intel_hdmi_add_properties(intel_hdmi, connector); |
| 911 | |
| 912 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
| 913 | drm_sysfs_connector_add(connector); |
| 914 | |
| 915 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
| 916 | * 0xd. Failure to do so will result in spurious interrupts being |
| 917 | * generated on the port when a cable is not attached. |
| 918 | */ |
| 919 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
| 920 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
| 921 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
| 922 | } |
| 923 | } |