| 1 | /* |
| 2 | * Copyright 2012 Red Hat Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
| 25 | #include <subdev/bios.h> |
| 26 | #include <subdev/bus.h> |
| 27 | #include <subdev/gpio.h> |
| 28 | #include <subdev/i2c.h> |
| 29 | #include <subdev/clock.h> |
| 30 | #include <subdev/therm.h> |
| 31 | #include <subdev/mxm.h> |
| 32 | #include <subdev/devinit.h> |
| 33 | #include <subdev/mc.h> |
| 34 | #include <subdev/timer.h> |
| 35 | #include <subdev/fb.h> |
| 36 | #include <subdev/instmem.h> |
| 37 | #include <subdev/vm.h> |
| 38 | #include <subdev/bar.h> |
| 39 | #include <subdev/pwr.h> |
| 40 | #include <subdev/volt.h> |
| 41 | |
| 42 | #include <engine/device.h> |
| 43 | #include <engine/dmaobj.h> |
| 44 | #include <engine/fifo.h> |
| 45 | #include <engine/software.h> |
| 46 | #include <engine/graph.h> |
| 47 | #include <engine/mpeg.h> |
| 48 | #include <engine/vp.h> |
| 49 | #include <engine/crypt.h> |
| 50 | #include <engine/bsp.h> |
| 51 | #include <engine/ppp.h> |
| 52 | #include <engine/copy.h> |
| 53 | #include <engine/disp.h> |
| 54 | #include <engine/perfmon.h> |
| 55 | |
| 56 | int |
| 57 | nv50_identify(struct nouveau_device *device) |
| 58 | { |
| 59 | switch (device->chipset) { |
| 60 | case 0x50: |
| 61 | device->cname = "G80"; |
| 62 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 63 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; |
| 64 | device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; |
| 65 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv50_clock_oclass; |
| 66 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass; |
| 67 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 68 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass; |
| 69 | device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; |
| 70 | device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; |
| 71 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 72 | device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass; |
| 73 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 74 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 75 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 76 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 77 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; |
| 78 | device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass; |
| 79 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
| 80 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
| 81 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass; |
| 82 | device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass; |
| 83 | device->oclass[NVDEV_ENGINE_PERFMON] = nv50_perfmon_oclass; |
| 84 | break; |
| 85 | case 0x84: |
| 86 | device->cname = "G84"; |
| 87 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 88 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; |
| 89 | device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; |
| 90 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; |
| 91 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
| 92 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 93 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; |
| 94 | device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; |
| 95 | device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; |
| 96 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 97 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
| 98 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 99 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 100 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 101 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 102 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; |
| 103 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
| 104 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
| 105 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
| 106 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; |
| 107 | device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; |
| 108 | device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; |
| 109 | device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; |
| 110 | device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass; |
| 111 | device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; |
| 112 | break; |
| 113 | case 0x86: |
| 114 | device->cname = "G86"; |
| 115 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 116 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; |
| 117 | device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; |
| 118 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; |
| 119 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
| 120 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 121 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; |
| 122 | device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; |
| 123 | device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; |
| 124 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 125 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
| 126 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 127 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 128 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 129 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 130 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; |
| 131 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
| 132 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
| 133 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
| 134 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; |
| 135 | device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; |
| 136 | device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; |
| 137 | device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; |
| 138 | device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass; |
| 139 | device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; |
| 140 | break; |
| 141 | case 0x92: |
| 142 | device->cname = "G92"; |
| 143 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 144 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass; |
| 145 | device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; |
| 146 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; |
| 147 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
| 148 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 149 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; |
| 150 | device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; |
| 151 | device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; |
| 152 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 153 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
| 154 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 155 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 156 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 157 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 158 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; |
| 159 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
| 160 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
| 161 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
| 162 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; |
| 163 | device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; |
| 164 | device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; |
| 165 | device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; |
| 166 | device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass; |
| 167 | device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; |
| 168 | break; |
| 169 | case 0x94: |
| 170 | device->cname = "G94"; |
| 171 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 172 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass; |
| 173 | device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; |
| 174 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; |
| 175 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
| 176 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 177 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; |
| 178 | device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; |
| 179 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 180 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 181 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
| 182 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 183 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 184 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 185 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 186 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; |
| 187 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
| 188 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
| 189 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
| 190 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; |
| 191 | device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; |
| 192 | device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; |
| 193 | device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; |
| 194 | device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; |
| 195 | device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; |
| 196 | break; |
| 197 | case 0x96: |
| 198 | device->cname = "G96"; |
| 199 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 200 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass; |
| 201 | device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; |
| 202 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; |
| 203 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
| 204 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 205 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; |
| 206 | device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; |
| 207 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 208 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 209 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
| 210 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 211 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 212 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 213 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 214 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; |
| 215 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
| 216 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
| 217 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
| 218 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; |
| 219 | device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; |
| 220 | device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; |
| 221 | device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; |
| 222 | device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; |
| 223 | device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; |
| 224 | break; |
| 225 | case 0x98: |
| 226 | device->cname = "G98"; |
| 227 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 228 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass; |
| 229 | device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; |
| 230 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; |
| 231 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
| 232 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 233 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass; |
| 234 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; |
| 235 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 236 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 237 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
| 238 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 239 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 240 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 241 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 242 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; |
| 243 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
| 244 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
| 245 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
| 246 | device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; |
| 247 | device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; |
| 248 | device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; |
| 249 | device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; |
| 250 | device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; |
| 251 | device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; |
| 252 | break; |
| 253 | case 0xa0: |
| 254 | device->cname = "G200"; |
| 255 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 256 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass; |
| 257 | device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; |
| 258 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; |
| 259 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
| 260 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 261 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; |
| 262 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; |
| 263 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 264 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 265 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
| 266 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 267 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 268 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 269 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 270 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; |
| 271 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
| 272 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
| 273 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
| 274 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; |
| 275 | device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; |
| 276 | device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; |
| 277 | device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; |
| 278 | device->oclass[NVDEV_ENGINE_DISP ] = nva0_disp_oclass; |
| 279 | device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; |
| 280 | break; |
| 281 | case 0xaa: |
| 282 | device->cname = "MCP77/MCP78"; |
| 283 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 284 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass; |
| 285 | device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; |
| 286 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass; |
| 287 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
| 288 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 289 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass; |
| 290 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; |
| 291 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 292 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 293 | device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; |
| 294 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 295 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 296 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 297 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 298 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; |
| 299 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
| 300 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
| 301 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
| 302 | device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; |
| 303 | device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; |
| 304 | device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; |
| 305 | device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; |
| 306 | device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; |
| 307 | device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; |
| 308 | break; |
| 309 | case 0xac: |
| 310 | device->cname = "MCP79/MCP7A"; |
| 311 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 312 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass; |
| 313 | device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; |
| 314 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass; |
| 315 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
| 316 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 317 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass; |
| 318 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; |
| 319 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 320 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 321 | device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; |
| 322 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 323 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 324 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 325 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 326 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; |
| 327 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
| 328 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
| 329 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
| 330 | device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; |
| 331 | device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; |
| 332 | device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; |
| 333 | device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; |
| 334 | device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; |
| 335 | device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; |
| 336 | break; |
| 337 | case 0xa3: |
| 338 | device->cname = "GT215"; |
| 339 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 340 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass; |
| 341 | device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; |
| 342 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; |
| 343 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
| 344 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 345 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass; |
| 346 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; |
| 347 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 348 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 349 | device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; |
| 350 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 351 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 352 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 353 | device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass; |
| 354 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 355 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; |
| 356 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
| 357 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
| 358 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
| 359 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; |
| 360 | device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; |
| 361 | device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; |
| 362 | device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; |
| 363 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; |
| 364 | device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; |
| 365 | device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; |
| 366 | break; |
| 367 | case 0xa5: |
| 368 | device->cname = "GT216"; |
| 369 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 370 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass; |
| 371 | device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; |
| 372 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; |
| 373 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
| 374 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 375 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass; |
| 376 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; |
| 377 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 378 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 379 | device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; |
| 380 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 381 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 382 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 383 | device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass; |
| 384 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 385 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; |
| 386 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
| 387 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
| 388 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
| 389 | device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; |
| 390 | device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; |
| 391 | device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; |
| 392 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; |
| 393 | device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; |
| 394 | device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; |
| 395 | break; |
| 396 | case 0xa8: |
| 397 | device->cname = "GT218"; |
| 398 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 399 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass; |
| 400 | device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; |
| 401 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; |
| 402 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
| 403 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 404 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass; |
| 405 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; |
| 406 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 407 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 408 | device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; |
| 409 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 410 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 411 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 412 | device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass; |
| 413 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 414 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; |
| 415 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
| 416 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
| 417 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
| 418 | device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; |
| 419 | device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; |
| 420 | device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; |
| 421 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; |
| 422 | device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; |
| 423 | device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; |
| 424 | break; |
| 425 | case 0xaf: |
| 426 | device->cname = "MCP89"; |
| 427 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 428 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass; |
| 429 | device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; |
| 430 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; |
| 431 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
| 432 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 433 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvaf_devinit_oclass; |
| 434 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; |
| 435 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 436 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 437 | device->oclass[NVDEV_SUBDEV_FB ] = nvaf_fb_oclass; |
| 438 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 439 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 440 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 441 | device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass; |
| 442 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 443 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; |
| 444 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
| 445 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
| 446 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
| 447 | device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; |
| 448 | device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; |
| 449 | device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; |
| 450 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; |
| 451 | device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; |
| 452 | device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; |
| 453 | break; |
| 454 | default: |
| 455 | nv_fatal(device, "unknown Tesla chipset\n"); |
| 456 | return -EINVAL; |
| 457 | } |
| 458 | |
| 459 | return 0; |
| 460 | } |