| 1 | #include "nv20.h" |
| 2 | #include "regs.h" |
| 3 | |
| 4 | #include <core/gpuobj.h> |
| 5 | #include <engine/fifo.h> |
| 6 | #include <engine/fifo/chan.h> |
| 7 | |
| 8 | /******************************************************************************* |
| 9 | * PGRAPH context |
| 10 | ******************************************************************************/ |
| 11 | |
| 12 | static const struct nvkm_object_func |
| 13 | nv34_gr_chan = { |
| 14 | .dtor = nv20_gr_chan_dtor, |
| 15 | .init = nv20_gr_chan_init, |
| 16 | .fini = nv20_gr_chan_fini, |
| 17 | }; |
| 18 | |
| 19 | static int |
| 20 | nv34_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, |
| 21 | const struct nvkm_oclass *oclass, struct nvkm_object **pobject) |
| 22 | { |
| 23 | struct nv20_gr *gr = nv20_gr(base); |
| 24 | struct nv20_gr_chan *chan; |
| 25 | int ret, i; |
| 26 | |
| 27 | if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) |
| 28 | return -ENOMEM; |
| 29 | nvkm_object_ctor(&nv34_gr_chan, oclass, &chan->object); |
| 30 | chan->gr = gr; |
| 31 | chan->chid = fifoch->chid; |
| 32 | *pobject = &chan->object; |
| 33 | |
| 34 | ret = nvkm_memory_new(gr->base.engine.subdev.device, |
| 35 | NVKM_MEM_TARGET_INST, 0x46dc, 16, true, |
| 36 | &chan->inst); |
| 37 | if (ret) |
| 38 | return ret; |
| 39 | |
| 40 | nvkm_kmap(chan->inst); |
| 41 | nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); |
| 42 | nvkm_wo32(chan->inst, 0x040c, 0x01000101); |
| 43 | nvkm_wo32(chan->inst, 0x0420, 0x00000111); |
| 44 | nvkm_wo32(chan->inst, 0x0424, 0x00000060); |
| 45 | nvkm_wo32(chan->inst, 0x0440, 0x00000080); |
| 46 | nvkm_wo32(chan->inst, 0x0444, 0xffff0000); |
| 47 | nvkm_wo32(chan->inst, 0x0448, 0x00000001); |
| 48 | nvkm_wo32(chan->inst, 0x045c, 0x44400000); |
| 49 | nvkm_wo32(chan->inst, 0x0480, 0xffff0000); |
| 50 | for (i = 0x04d4; i < 0x04dc; i += 4) |
| 51 | nvkm_wo32(chan->inst, i, 0x0fff0000); |
| 52 | nvkm_wo32(chan->inst, 0x04e0, 0x00011100); |
| 53 | for (i = 0x04fc; i < 0x053c; i += 4) |
| 54 | nvkm_wo32(chan->inst, i, 0x07ff0000); |
| 55 | nvkm_wo32(chan->inst, 0x0544, 0x4b7fffff); |
| 56 | nvkm_wo32(chan->inst, 0x057c, 0x00000080); |
| 57 | nvkm_wo32(chan->inst, 0x0580, 0x30201000); |
| 58 | nvkm_wo32(chan->inst, 0x0584, 0x70605040); |
| 59 | nvkm_wo32(chan->inst, 0x0588, 0xb8a89888); |
| 60 | nvkm_wo32(chan->inst, 0x058c, 0xf8e8d8c8); |
| 61 | nvkm_wo32(chan->inst, 0x05a0, 0xb0000000); |
| 62 | for (i = 0x05f0; i < 0x0630; i += 4) |
| 63 | nvkm_wo32(chan->inst, i, 0x00010588); |
| 64 | for (i = 0x0630; i < 0x0670; i += 4) |
| 65 | nvkm_wo32(chan->inst, i, 0x00030303); |
| 66 | for (i = 0x06b0; i < 0x06f0; i += 4) |
| 67 | nvkm_wo32(chan->inst, i, 0x0008aae4); |
| 68 | for (i = 0x06f0; i < 0x0730; i += 4) |
| 69 | nvkm_wo32(chan->inst, i, 0x01012000); |
| 70 | for (i = 0x0730; i < 0x0770; i += 4) |
| 71 | nvkm_wo32(chan->inst, i, 0x00080008); |
| 72 | nvkm_wo32(chan->inst, 0x0850, 0x00040000); |
| 73 | nvkm_wo32(chan->inst, 0x0854, 0x00010000); |
| 74 | for (i = 0x0858; i < 0x0868; i += 4) |
| 75 | nvkm_wo32(chan->inst, i, 0x00040004); |
| 76 | for (i = 0x15ac; i <= 0x271c ; i += 16) { |
| 77 | nvkm_wo32(chan->inst, i + 0, 0x10700ff9); |
| 78 | nvkm_wo32(chan->inst, i + 1, 0x0436086c); |
| 79 | nvkm_wo32(chan->inst, i + 2, 0x000c001b); |
| 80 | } |
| 81 | for (i = 0x274c; i < 0x275c; i += 4) |
| 82 | nvkm_wo32(chan->inst, i, 0x0000ffff); |
| 83 | nvkm_wo32(chan->inst, 0x2ae0, 0x3f800000); |
| 84 | nvkm_wo32(chan->inst, 0x2e9c, 0x3f800000); |
| 85 | nvkm_wo32(chan->inst, 0x2eb0, 0x3f800000); |
| 86 | nvkm_wo32(chan->inst, 0x2edc, 0x40000000); |
| 87 | nvkm_wo32(chan->inst, 0x2ee0, 0x3f800000); |
| 88 | nvkm_wo32(chan->inst, 0x2ee4, 0x3f000000); |
| 89 | nvkm_wo32(chan->inst, 0x2eec, 0x40000000); |
| 90 | nvkm_wo32(chan->inst, 0x2ef0, 0x3f800000); |
| 91 | nvkm_wo32(chan->inst, 0x2ef8, 0xbf800000); |
| 92 | nvkm_wo32(chan->inst, 0x2f00, 0xbf800000); |
| 93 | nvkm_done(chan->inst); |
| 94 | return 0; |
| 95 | } |
| 96 | |
| 97 | /******************************************************************************* |
| 98 | * PGRAPH engine/subdev functions |
| 99 | ******************************************************************************/ |
| 100 | |
| 101 | static const struct nvkm_gr_func |
| 102 | nv34_gr = { |
| 103 | .dtor = nv20_gr_dtor, |
| 104 | .oneinit = nv20_gr_oneinit, |
| 105 | .init = nv30_gr_init, |
| 106 | .intr = nv20_gr_intr, |
| 107 | .tile = nv20_gr_tile, |
| 108 | .chan_new = nv34_gr_chan_new, |
| 109 | .sclass = { |
| 110 | { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ |
| 111 | { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ |
| 112 | { -1, -1, 0x0030, &nv04_gr_object }, /* null */ |
| 113 | { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ |
| 114 | { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ |
| 115 | { -1, -1, 0x0044, &nv04_gr_object }, /* patt */ |
| 116 | { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ |
| 117 | { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ |
| 118 | { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ |
| 119 | { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ |
| 120 | { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ |
| 121 | { -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */ |
| 122 | { -1, -1, 0x0362, &nv04_gr_object }, /* surf2d (nv30) */ |
| 123 | { -1, -1, 0x0389, &nv04_gr_object }, /* sifm (nv30) */ |
| 124 | { -1, -1, 0x038a, &nv04_gr_object }, /* ifc (nv30) */ |
| 125 | { -1, -1, 0x039e, &nv04_gr_object }, /* swzsurf (nv30) */ |
| 126 | { -1, -1, 0x0697, &nv04_gr_object }, /* rankine */ |
| 127 | {} |
| 128 | } |
| 129 | }; |
| 130 | |
| 131 | int |
| 132 | nv34_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) |
| 133 | { |
| 134 | return nv20_gr_new_(&nv34_gr, device, index, pgr); |
| 135 | } |