| 1 | /* |
| 2 | * SL82C105/Winbond 553 IDE driver |
| 3 | * |
| 4 | * Maintainer unknown. |
| 5 | * |
| 6 | * Drive tuning added from Rebel.com's kernel sources |
| 7 | * -- Russell King (15/11/98) linux@arm.linux.org.uk |
| 8 | * |
| 9 | * Merge in Russell's HW workarounds, fix various problems |
| 10 | * with the timing registers setup. |
| 11 | * -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org |
| 12 | * |
| 13 | * Copyright (C) 2006-2007,2009 MontaVista Software, Inc. <source@mvista.com> |
| 14 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
| 15 | */ |
| 16 | |
| 17 | #include <linux/types.h> |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/kernel.h> |
| 20 | #include <linux/pci.h> |
| 21 | #include <linux/ide.h> |
| 22 | |
| 23 | #include <asm/io.h> |
| 24 | |
| 25 | #define DRV_NAME "sl82c105" |
| 26 | |
| 27 | #undef DEBUG |
| 28 | |
| 29 | #ifdef DEBUG |
| 30 | #define DBG(arg) printk arg |
| 31 | #else |
| 32 | #define DBG(fmt,...) |
| 33 | #endif |
| 34 | /* |
| 35 | * SL82C105 PCI config register 0x40 bits. |
| 36 | */ |
| 37 | #define CTRL_IDE_IRQB (1 << 30) |
| 38 | #define CTRL_IDE_IRQA (1 << 28) |
| 39 | #define CTRL_LEGIRQ (1 << 11) |
| 40 | #define CTRL_P1F16 (1 << 5) |
| 41 | #define CTRL_P1EN (1 << 4) |
| 42 | #define CTRL_P0F16 (1 << 1) |
| 43 | #define CTRL_P0EN (1 << 0) |
| 44 | |
| 45 | /* |
| 46 | * Convert a PIO mode and cycle time to the required on/off times |
| 47 | * for the interface. This has protection against runaway timings. |
| 48 | */ |
| 49 | static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio) |
| 50 | { |
| 51 | struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio); |
| 52 | unsigned int cmd_on, cmd_off; |
| 53 | u8 iordy = 0; |
| 54 | |
| 55 | cmd_on = (t->active + 29) / 30; |
| 56 | cmd_off = (ide_pio_cycle_time(drive, pio) - 30 * cmd_on + 29) / 30; |
| 57 | |
| 58 | if (cmd_on == 0) |
| 59 | cmd_on = 1; |
| 60 | |
| 61 | if (cmd_off == 0) |
| 62 | cmd_off = 1; |
| 63 | |
| 64 | if (ide_pio_need_iordy(drive, pio)) |
| 65 | iordy = 0x40; |
| 66 | |
| 67 | return (cmd_on - 1) << 8 | (cmd_off - 1) | iordy; |
| 68 | } |
| 69 | |
| 70 | /* |
| 71 | * Configure the chipset for PIO mode. |
| 72 | */ |
| 73 | static void sl82c105_set_pio_mode(ide_drive_t *drive, const u8 pio) |
| 74 | { |
| 75 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
| 76 | unsigned long timings = (unsigned long)ide_get_drivedata(drive); |
| 77 | int reg = 0x44 + drive->dn * 4; |
| 78 | u16 drv_ctrl; |
| 79 | |
| 80 | drv_ctrl = get_pio_timings(drive, pio); |
| 81 | |
| 82 | /* |
| 83 | * Store the PIO timings so that we can restore them |
| 84 | * in case DMA will be turned off... |
| 85 | */ |
| 86 | timings &= 0xffff0000; |
| 87 | timings |= drv_ctrl; |
| 88 | ide_set_drivedata(drive, (void *)timings); |
| 89 | |
| 90 | pci_write_config_word(dev, reg, drv_ctrl); |
| 91 | pci_read_config_word (dev, reg, &drv_ctrl); |
| 92 | |
| 93 | printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name, |
| 94 | ide_xfer_verbose(pio + XFER_PIO_0), |
| 95 | ide_pio_cycle_time(drive, pio), drv_ctrl); |
| 96 | } |
| 97 | |
| 98 | /* |
| 99 | * Configure the chipset for DMA mode. |
| 100 | */ |
| 101 | static void sl82c105_set_dma_mode(ide_drive_t *drive, const u8 speed) |
| 102 | { |
| 103 | static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200}; |
| 104 | unsigned long timings = (unsigned long)ide_get_drivedata(drive); |
| 105 | u16 drv_ctrl; |
| 106 | |
| 107 | DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n", |
| 108 | drive->name, ide_xfer_verbose(speed))); |
| 109 | |
| 110 | drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0]; |
| 111 | |
| 112 | /* |
| 113 | * Store the DMA timings so that we can actually program |
| 114 | * them when DMA will be turned on... |
| 115 | */ |
| 116 | timings &= 0x0000ffff; |
| 117 | timings |= (unsigned long)drv_ctrl << 16; |
| 118 | ide_set_drivedata(drive, (void *)timings); |
| 119 | } |
| 120 | |
| 121 | static int sl82c105_test_irq(ide_hwif_t *hwif) |
| 122 | { |
| 123 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
| 124 | u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA; |
| 125 | |
| 126 | pci_read_config_dword(dev, 0x40, &val); |
| 127 | |
| 128 | return (val & mask) ? 1 : 0; |
| 129 | } |
| 130 | |
| 131 | /* |
| 132 | * The SL82C105 holds off all IDE interrupts while in DMA mode until |
| 133 | * all DMA activity is completed. Sometimes this causes problems (eg, |
| 134 | * when the drive wants to report an error condition). |
| 135 | * |
| 136 | * 0x7e is a "chip testing" register. Bit 2 resets the DMA controller |
| 137 | * state machine. We need to kick this to work around various bugs. |
| 138 | */ |
| 139 | static inline void sl82c105_reset_host(struct pci_dev *dev) |
| 140 | { |
| 141 | u16 val; |
| 142 | |
| 143 | pci_read_config_word(dev, 0x7e, &val); |
| 144 | pci_write_config_word(dev, 0x7e, val | (1 << 2)); |
| 145 | pci_write_config_word(dev, 0x7e, val & ~(1 << 2)); |
| 146 | } |
| 147 | |
| 148 | /* |
| 149 | * If we get an IRQ timeout, it might be that the DMA state machine |
| 150 | * got confused. Fix from Todd Inglett. Details from Winbond. |
| 151 | * |
| 152 | * This function is called when the IDE timer expires, the drive |
| 153 | * indicates that it is READY, and we were waiting for DMA to complete. |
| 154 | */ |
| 155 | static void sl82c105_dma_lost_irq(ide_drive_t *drive) |
| 156 | { |
| 157 | ide_hwif_t *hwif = drive->hwif; |
| 158 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
| 159 | u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA; |
| 160 | u8 dma_cmd; |
| 161 | |
| 162 | printk(KERN_WARNING "sl82c105: lost IRQ, resetting host\n"); |
| 163 | |
| 164 | /* |
| 165 | * Check the raw interrupt from the drive. |
| 166 | */ |
| 167 | pci_read_config_dword(dev, 0x40, &val); |
| 168 | if (val & mask) |
| 169 | printk(KERN_INFO "sl82c105: drive was requesting IRQ, " |
| 170 | "but host lost it\n"); |
| 171 | |
| 172 | /* |
| 173 | * Was DMA enabled? If so, disable it - we're resetting the |
| 174 | * host. The IDE layer will be handling the drive for us. |
| 175 | */ |
| 176 | dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); |
| 177 | if (dma_cmd & 1) { |
| 178 | outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD); |
| 179 | printk(KERN_INFO "sl82c105: DMA was enabled\n"); |
| 180 | } |
| 181 | |
| 182 | sl82c105_reset_host(dev); |
| 183 | } |
| 184 | |
| 185 | /* |
| 186 | * ATAPI devices can cause the SL82C105 DMA state machine to go gaga. |
| 187 | * Winbond recommend that the DMA state machine is reset prior to |
| 188 | * setting the bus master DMA enable bit. |
| 189 | * |
| 190 | * The generic IDE core will have disabled the BMEN bit before this |
| 191 | * function is called. |
| 192 | */ |
| 193 | static void sl82c105_dma_start(ide_drive_t *drive) |
| 194 | { |
| 195 | ide_hwif_t *hwif = drive->hwif; |
| 196 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
| 197 | int reg = 0x44 + drive->dn * 4; |
| 198 | |
| 199 | DBG(("%s(drive:%s)\n", __func__, drive->name)); |
| 200 | |
| 201 | pci_write_config_word(dev, reg, |
| 202 | (unsigned long)ide_get_drivedata(drive) >> 16); |
| 203 | |
| 204 | sl82c105_reset_host(dev); |
| 205 | ide_dma_start(drive); |
| 206 | } |
| 207 | |
| 208 | static void sl82c105_dma_clear(ide_drive_t *drive) |
| 209 | { |
| 210 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
| 211 | |
| 212 | DBG(("sl82c105_dma_clear(drive:%s)\n", drive->name)); |
| 213 | |
| 214 | sl82c105_reset_host(dev); |
| 215 | } |
| 216 | |
| 217 | static int sl82c105_dma_end(ide_drive_t *drive) |
| 218 | { |
| 219 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
| 220 | int reg = 0x44 + drive->dn * 4; |
| 221 | int ret; |
| 222 | |
| 223 | DBG(("%s(drive:%s)\n", __func__, drive->name)); |
| 224 | |
| 225 | ret = ide_dma_end(drive); |
| 226 | |
| 227 | pci_write_config_word(dev, reg, |
| 228 | (unsigned long)ide_get_drivedata(drive)); |
| 229 | |
| 230 | return ret; |
| 231 | } |
| 232 | |
| 233 | /* |
| 234 | * ATA reset will clear the 16 bits mode in the control |
| 235 | * register, we need to reprogram it |
| 236 | */ |
| 237 | static void sl82c105_resetproc(ide_drive_t *drive) |
| 238 | { |
| 239 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
| 240 | u32 val; |
| 241 | |
| 242 | DBG(("sl82c105_resetproc(drive:%s)\n", drive->name)); |
| 243 | |
| 244 | pci_read_config_dword(dev, 0x40, &val); |
| 245 | val |= (CTRL_P1F16 | CTRL_P0F16); |
| 246 | pci_write_config_dword(dev, 0x40, val); |
| 247 | } |
| 248 | |
| 249 | /* |
| 250 | * Return the revision of the Winbond bridge |
| 251 | * which this function is part of. |
| 252 | */ |
| 253 | static u8 sl82c105_bridge_revision(struct pci_dev *dev) |
| 254 | { |
| 255 | struct pci_dev *bridge; |
| 256 | |
| 257 | /* |
| 258 | * The bridge should be part of the same device, but function 0. |
| 259 | */ |
| 260 | bridge = pci_get_bus_and_slot(dev->bus->number, |
| 261 | PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); |
| 262 | if (!bridge) |
| 263 | return -1; |
| 264 | |
| 265 | /* |
| 266 | * Make sure it is a Winbond 553 and is an ISA bridge. |
| 267 | */ |
| 268 | if (bridge->vendor != PCI_VENDOR_ID_WINBOND || |
| 269 | bridge->device != PCI_DEVICE_ID_WINBOND_83C553 || |
| 270 | bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) { |
| 271 | pci_dev_put(bridge); |
| 272 | return -1; |
| 273 | } |
| 274 | /* |
| 275 | * We need to find function 0's revision, not function 1 |
| 276 | */ |
| 277 | pci_dev_put(bridge); |
| 278 | |
| 279 | return bridge->revision; |
| 280 | } |
| 281 | |
| 282 | /* |
| 283 | * Enable the PCI device |
| 284 | * |
| 285 | * --BenH: It's arch fixup code that should enable channels that |
| 286 | * have not been enabled by firmware. I decided we can still enable |
| 287 | * channel 0 here at least, but channel 1 has to be enabled by |
| 288 | * firmware or arch code. We still set both to 16 bits mode. |
| 289 | */ |
| 290 | static int init_chipset_sl82c105(struct pci_dev *dev) |
| 291 | { |
| 292 | u32 val; |
| 293 | |
| 294 | DBG(("init_chipset_sl82c105()\n")); |
| 295 | |
| 296 | pci_read_config_dword(dev, 0x40, &val); |
| 297 | val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16; |
| 298 | pci_write_config_dword(dev, 0x40, val); |
| 299 | |
| 300 | return 0; |
| 301 | } |
| 302 | |
| 303 | static const struct ide_port_ops sl82c105_port_ops = { |
| 304 | .set_pio_mode = sl82c105_set_pio_mode, |
| 305 | .set_dma_mode = sl82c105_set_dma_mode, |
| 306 | .resetproc = sl82c105_resetproc, |
| 307 | .test_irq = sl82c105_test_irq, |
| 308 | }; |
| 309 | |
| 310 | static const struct ide_dma_ops sl82c105_dma_ops = { |
| 311 | .dma_host_set = ide_dma_host_set, |
| 312 | .dma_setup = ide_dma_setup, |
| 313 | .dma_start = sl82c105_dma_start, |
| 314 | .dma_end = sl82c105_dma_end, |
| 315 | .dma_test_irq = ide_dma_test_irq, |
| 316 | .dma_lost_irq = sl82c105_dma_lost_irq, |
| 317 | .dma_timer_expiry = ide_dma_sff_timer_expiry, |
| 318 | .dma_clear = sl82c105_dma_clear, |
| 319 | .dma_sff_read_status = ide_dma_sff_read_status, |
| 320 | }; |
| 321 | |
| 322 | static const struct ide_port_info sl82c105_chipset __devinitdata = { |
| 323 | .name = DRV_NAME, |
| 324 | .init_chipset = init_chipset_sl82c105, |
| 325 | .enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}}, |
| 326 | .port_ops = &sl82c105_port_ops, |
| 327 | .dma_ops = &sl82c105_dma_ops, |
| 328 | .host_flags = IDE_HFLAG_IO_32BIT | |
| 329 | IDE_HFLAG_UNMASK_IRQS | |
| 330 | IDE_HFLAG_SERIALIZE_DMA | |
| 331 | IDE_HFLAG_NO_AUTODMA, |
| 332 | .pio_mask = ATA_PIO5, |
| 333 | .mwdma_mask = ATA_MWDMA2, |
| 334 | }; |
| 335 | |
| 336 | static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
| 337 | { |
| 338 | struct ide_port_info d = sl82c105_chipset; |
| 339 | u8 rev = sl82c105_bridge_revision(dev); |
| 340 | |
| 341 | if (rev <= 5) { |
| 342 | /* |
| 343 | * Never ever EVER under any circumstances enable |
| 344 | * DMA when the bridge is this old. |
| 345 | */ |
| 346 | printk(KERN_INFO DRV_NAME ": Winbond W83C553 bridge " |
| 347 | "revision %d, BM-DMA disabled\n", rev); |
| 348 | d.dma_ops = NULL; |
| 349 | d.mwdma_mask = 0; |
| 350 | d.host_flags &= ~IDE_HFLAG_SERIALIZE_DMA; |
| 351 | } |
| 352 | |
| 353 | return ide_pci_init_one(dev, &d, NULL); |
| 354 | } |
| 355 | |
| 356 | static const struct pci_device_id sl82c105_pci_tbl[] = { |
| 357 | { PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0 }, |
| 358 | { 0, }, |
| 359 | }; |
| 360 | MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl); |
| 361 | |
| 362 | static struct pci_driver sl82c105_pci_driver = { |
| 363 | .name = "W82C105_IDE", |
| 364 | .id_table = sl82c105_pci_tbl, |
| 365 | .probe = sl82c105_init_one, |
| 366 | .remove = ide_pci_remove, |
| 367 | .suspend = ide_pci_suspend, |
| 368 | .resume = ide_pci_resume, |
| 369 | }; |
| 370 | |
| 371 | static int __init sl82c105_ide_init(void) |
| 372 | { |
| 373 | return ide_pci_register_driver(&sl82c105_pci_driver); |
| 374 | } |
| 375 | |
| 376 | static void __exit sl82c105_ide_exit(void) |
| 377 | { |
| 378 | pci_unregister_driver(&sl82c105_pci_driver); |
| 379 | } |
| 380 | |
| 381 | module_init(sl82c105_ide_init); |
| 382 | module_exit(sl82c105_ide_exit); |
| 383 | |
| 384 | MODULE_DESCRIPTION("PCI driver module for W82C105 IDE"); |
| 385 | MODULE_LICENSE("GPL"); |