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iommu/omap: Remove trailing semi-colon from a macro
[deliverable/linux.git] / drivers / iommu / omap-iommu.c
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CommitLineData
1/*
2 * omap iommu: tlb and pagetable primitives
3 *
4 * Copyright (C) 2008-2010 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
7 * Paul Mundt and Toshihiro Kobayashi
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/err.h>
15#include <linux/slab.h>
16#include <linux/interrupt.h>
17#include <linux/ioport.h>
18#include <linux/platform_device.h>
19#include <linux/iommu.h>
20#include <linux/omap-iommu.h>
21#include <linux/mutex.h>
22#include <linux/spinlock.h>
23#include <linux/io.h>
24#include <linux/pm_runtime.h>
25#include <linux/of.h>
26#include <linux/of_iommu.h>
27#include <linux/of_irq.h>
28#include <linux/of_platform.h>
29
30#include <asm/cacheflush.h>
31
32#include <linux/platform_data/iommu-omap.h>
33
34#include "omap-iopgtable.h"
35#include "omap-iommu.h"
36
37#define to_iommu(dev) \
38 ((struct omap_iommu *)platform_get_drvdata(to_platform_device(dev)))
39
40/* bitmap of the page sizes currently supported */
41#define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
42
43/**
44 * struct omap_iommu_domain - omap iommu domain
45 * @pgtable: the page table
46 * @iommu_dev: an omap iommu device attached to this domain. only a single
47 * iommu device can be attached for now.
48 * @dev: Device using this domain.
49 * @lock: domain lock, should be taken when attaching/detaching
50 */
51struct omap_iommu_domain {
52 u32 *pgtable;
53 struct omap_iommu *iommu_dev;
54 struct device *dev;
55 spinlock_t lock;
56 struct iommu_domain domain;
57};
58
59#define MMU_LOCK_BASE_SHIFT 10
60#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
61#define MMU_LOCK_BASE(x) \
62 ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
63
64#define MMU_LOCK_VICT_SHIFT 4
65#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
66#define MMU_LOCK_VICT(x) \
67 ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
68
69static struct platform_driver omap_iommu_driver;
70static struct kmem_cache *iopte_cachep;
71
72/**
73 * to_omap_domain - Get struct omap_iommu_domain from generic iommu_domain
74 * @dom: generic iommu domain handle
75 **/
76static struct omap_iommu_domain *to_omap_domain(struct iommu_domain *dom)
77{
78 return container_of(dom, struct omap_iommu_domain, domain);
79}
80
81/**
82 * omap_iommu_save_ctx - Save registers for pm off-mode support
83 * @dev: client device
84 **/
85void omap_iommu_save_ctx(struct device *dev)
86{
87 struct omap_iommu *obj = dev_to_omap_iommu(dev);
88 u32 *p = obj->ctx;
89 int i;
90
91 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
92 p[i] = iommu_read_reg(obj, i * sizeof(u32));
93 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
94 }
95}
96EXPORT_SYMBOL_GPL(omap_iommu_save_ctx);
97
98/**
99 * omap_iommu_restore_ctx - Restore registers for pm off-mode support
100 * @dev: client device
101 **/
102void omap_iommu_restore_ctx(struct device *dev)
103{
104 struct omap_iommu *obj = dev_to_omap_iommu(dev);
105 u32 *p = obj->ctx;
106 int i;
107
108 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
109 iommu_write_reg(obj, p[i], i * sizeof(u32));
110 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
111 }
112}
113EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx);
114
115static void __iommu_set_twl(struct omap_iommu *obj, bool on)
116{
117 u32 l = iommu_read_reg(obj, MMU_CNTL);
118
119 if (on)
120 iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
121 else
122 iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
123
124 l &= ~MMU_CNTL_MASK;
125 if (on)
126 l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
127 else
128 l |= (MMU_CNTL_MMU_EN);
129
130 iommu_write_reg(obj, l, MMU_CNTL);
131}
132
133static int omap2_iommu_enable(struct omap_iommu *obj)
134{
135 u32 l, pa;
136
137 if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K))
138 return -EINVAL;
139
140 pa = virt_to_phys(obj->iopgd);
141 if (!IS_ALIGNED(pa, SZ_16K))
142 return -EINVAL;
143
144 l = iommu_read_reg(obj, MMU_REVISION);
145 dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
146 (l >> 4) & 0xf, l & 0xf);
147
148 iommu_write_reg(obj, pa, MMU_TTB);
149
150 if (obj->has_bus_err_back)
151 iommu_write_reg(obj, MMU_GP_REG_BUS_ERR_BACK_EN, MMU_GP_REG);
152
153 __iommu_set_twl(obj, true);
154
155 return 0;
156}
157
158static void omap2_iommu_disable(struct omap_iommu *obj)
159{
160 u32 l = iommu_read_reg(obj, MMU_CNTL);
161
162 l &= ~MMU_CNTL_MASK;
163 iommu_write_reg(obj, l, MMU_CNTL);
164
165 dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
166}
167
168static int iommu_enable(struct omap_iommu *obj)
169{
170 int err;
171 struct platform_device *pdev = to_platform_device(obj->dev);
172 struct iommu_platform_data *pdata = dev_get_platdata(&pdev->dev);
173
174 if (pdata && pdata->deassert_reset) {
175 err = pdata->deassert_reset(pdev, pdata->reset_name);
176 if (err) {
177 dev_err(obj->dev, "deassert_reset failed: %d\n", err);
178 return err;
179 }
180 }
181
182 pm_runtime_get_sync(obj->dev);
183
184 err = omap2_iommu_enable(obj);
185
186 return err;
187}
188
189static void iommu_disable(struct omap_iommu *obj)
190{
191 struct platform_device *pdev = to_platform_device(obj->dev);
192 struct iommu_platform_data *pdata = dev_get_platdata(&pdev->dev);
193
194 omap2_iommu_disable(obj);
195
196 pm_runtime_put_sync(obj->dev);
197
198 if (pdata && pdata->assert_reset)
199 pdata->assert_reset(pdev, pdata->reset_name);
200}
201
202/*
203 * TLB operations
204 */
205static u32 iotlb_cr_to_virt(struct cr_regs *cr)
206{
207 u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
208 u32 mask = get_cam_va_mask(cr->cam & page_size);
209
210 return cr->cam & mask;
211}
212
213static u32 get_iopte_attr(struct iotlb_entry *e)
214{
215 u32 attr;
216
217 attr = e->mixed << 5;
218 attr |= e->endian;
219 attr |= e->elsz >> 3;
220 attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) ||
221 (e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6);
222 return attr;
223}
224
225static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da)
226{
227 u32 status, fault_addr;
228
229 status = iommu_read_reg(obj, MMU_IRQSTATUS);
230 status &= MMU_IRQ_MASK;
231 if (!status) {
232 *da = 0;
233 return 0;
234 }
235
236 fault_addr = iommu_read_reg(obj, MMU_FAULT_AD);
237 *da = fault_addr;
238
239 iommu_write_reg(obj, status, MMU_IRQSTATUS);
240
241 return status;
242}
243
244void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l)
245{
246 u32 val;
247
248 val = iommu_read_reg(obj, MMU_LOCK);
249
250 l->base = MMU_LOCK_BASE(val);
251 l->vict = MMU_LOCK_VICT(val);
252}
253
254void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l)
255{
256 u32 val;
257
258 val = (l->base << MMU_LOCK_BASE_SHIFT);
259 val |= (l->vict << MMU_LOCK_VICT_SHIFT);
260
261 iommu_write_reg(obj, val, MMU_LOCK);
262}
263
264static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
265{
266 cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
267 cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
268}
269
270static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
271{
272 iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
273 iommu_write_reg(obj, cr->ram, MMU_RAM);
274
275 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
276 iommu_write_reg(obj, 1, MMU_LD_TLB);
277}
278
279/* only used in iotlb iteration for-loop */
280struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n)
281{
282 struct cr_regs cr;
283 struct iotlb_lock l;
284
285 iotlb_lock_get(obj, &l);
286 l.vict = n;
287 iotlb_lock_set(obj, &l);
288 iotlb_read_cr(obj, &cr);
289
290 return cr;
291}
292
293#ifdef PREFETCH_IOTLB
294static struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj,
295 struct iotlb_entry *e)
296{
297 struct cr_regs *cr;
298
299 if (!e)
300 return NULL;
301
302 if (e->da & ~(get_cam_va_mask(e->pgsz))) {
303 dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
304 e->da);
305 return ERR_PTR(-EINVAL);
306 }
307
308 cr = kmalloc(sizeof(*cr), GFP_KERNEL);
309 if (!cr)
310 return ERR_PTR(-ENOMEM);
311
312 cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid;
313 cr->ram = e->pa | e->endian | e->elsz | e->mixed;
314
315 return cr;
316}
317
318/**
319 * load_iotlb_entry - Set an iommu tlb entry
320 * @obj: target iommu
321 * @e: an iommu tlb entry info
322 **/
323static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
324{
325 int err = 0;
326 struct iotlb_lock l;
327 struct cr_regs *cr;
328
329 if (!obj || !obj->nr_tlb_entries || !e)
330 return -EINVAL;
331
332 pm_runtime_get_sync(obj->dev);
333
334 iotlb_lock_get(obj, &l);
335 if (l.base == obj->nr_tlb_entries) {
336 dev_warn(obj->dev, "%s: preserve entries full\n", __func__);
337 err = -EBUSY;
338 goto out;
339 }
340 if (!e->prsvd) {
341 int i;
342 struct cr_regs tmp;
343
344 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp)
345 if (!iotlb_cr_valid(&tmp))
346 break;
347
348 if (i == obj->nr_tlb_entries) {
349 dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
350 err = -EBUSY;
351 goto out;
352 }
353
354 iotlb_lock_get(obj, &l);
355 } else {
356 l.vict = l.base;
357 iotlb_lock_set(obj, &l);
358 }
359
360 cr = iotlb_alloc_cr(obj, e);
361 if (IS_ERR(cr)) {
362 pm_runtime_put_sync(obj->dev);
363 return PTR_ERR(cr);
364 }
365
366 iotlb_load_cr(obj, cr);
367 kfree(cr);
368
369 if (e->prsvd)
370 l.base++;
371 /* increment victim for next tlb load */
372 if (++l.vict == obj->nr_tlb_entries)
373 l.vict = l.base;
374 iotlb_lock_set(obj, &l);
375out:
376 pm_runtime_put_sync(obj->dev);
377 return err;
378}
379
380#else /* !PREFETCH_IOTLB */
381
382static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
383{
384 return 0;
385}
386
387#endif /* !PREFETCH_IOTLB */
388
389static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
390{
391 return load_iotlb_entry(obj, e);
392}
393
394/**
395 * flush_iotlb_page - Clear an iommu tlb entry
396 * @obj: target iommu
397 * @da: iommu device virtual address
398 *
399 * Clear an iommu tlb entry which includes 'da' address.
400 **/
401static void flush_iotlb_page(struct omap_iommu *obj, u32 da)
402{
403 int i;
404 struct cr_regs cr;
405
406 pm_runtime_get_sync(obj->dev);
407
408 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) {
409 u32 start;
410 size_t bytes;
411
412 if (!iotlb_cr_valid(&cr))
413 continue;
414
415 start = iotlb_cr_to_virt(&cr);
416 bytes = iopgsz_to_bytes(cr.cam & 3);
417
418 if ((start <= da) && (da < start + bytes)) {
419 dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
420 __func__, start, da, bytes);
421 iotlb_load_cr(obj, &cr);
422 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
423 break;
424 }
425 }
426 pm_runtime_put_sync(obj->dev);
427
428 if (i == obj->nr_tlb_entries)
429 dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da);
430}
431
432/**
433 * flush_iotlb_all - Clear all iommu tlb entries
434 * @obj: target iommu
435 **/
436static void flush_iotlb_all(struct omap_iommu *obj)
437{
438 struct iotlb_lock l;
439
440 pm_runtime_get_sync(obj->dev);
441
442 l.base = 0;
443 l.vict = 0;
444 iotlb_lock_set(obj, &l);
445
446 iommu_write_reg(obj, 1, MMU_GFLUSH);
447
448 pm_runtime_put_sync(obj->dev);
449}
450
451/*
452 * H/W pagetable operations
453 */
454static void flush_iopgd_range(u32 *first, u32 *last)
455{
456 /* FIXME: L2 cache should be taken care of if it exists */
457 do {
458 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd"
459 : : "r" (first));
460 first += L1_CACHE_BYTES / sizeof(*first);
461 } while (first <= last);
462}
463
464static void flush_iopte_range(u32 *first, u32 *last)
465{
466 /* FIXME: L2 cache should be taken care of if it exists */
467 do {
468 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte"
469 : : "r" (first));
470 first += L1_CACHE_BYTES / sizeof(*first);
471 } while (first <= last);
472}
473
474static void iopte_free(u32 *iopte)
475{
476 /* Note: freed iopte's must be clean ready for re-use */
477 if (iopte)
478 kmem_cache_free(iopte_cachep, iopte);
479}
480
481static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da)
482{
483 u32 *iopte;
484
485 /* a table has already existed */
486 if (*iopgd)
487 goto pte_ready;
488
489 /*
490 * do the allocation outside the page table lock
491 */
492 spin_unlock(&obj->page_table_lock);
493 iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL);
494 spin_lock(&obj->page_table_lock);
495
496 if (!*iopgd) {
497 if (!iopte)
498 return ERR_PTR(-ENOMEM);
499
500 *iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
501 flush_iopgd_range(iopgd, iopgd);
502
503 dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);
504 } else {
505 /* We raced, free the reduniovant table */
506 iopte_free(iopte);
507 }
508
509pte_ready:
510 iopte = iopte_offset(iopgd, da);
511
512 dev_vdbg(obj->dev,
513 "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
514 __func__, da, iopgd, *iopgd, iopte, *iopte);
515
516 return iopte;
517}
518
519static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
520{
521 u32 *iopgd = iopgd_offset(obj, da);
522
523 if ((da | pa) & ~IOSECTION_MASK) {
524 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
525 __func__, da, pa, IOSECTION_SIZE);
526 return -EINVAL;
527 }
528
529 *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION;
530 flush_iopgd_range(iopgd, iopgd);
531 return 0;
532}
533
534static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
535{
536 u32 *iopgd = iopgd_offset(obj, da);
537 int i;
538
539 if ((da | pa) & ~IOSUPER_MASK) {
540 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
541 __func__, da, pa, IOSUPER_SIZE);
542 return -EINVAL;
543 }
544
545 for (i = 0; i < 16; i++)
546 *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER;
547 flush_iopgd_range(iopgd, iopgd + 15);
548 return 0;
549}
550
551static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
552{
553 u32 *iopgd = iopgd_offset(obj, da);
554 u32 *iopte = iopte_alloc(obj, iopgd, da);
555
556 if (IS_ERR(iopte))
557 return PTR_ERR(iopte);
558
559 *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL;
560 flush_iopte_range(iopte, iopte);
561
562 dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n",
563 __func__, da, pa, iopte, *iopte);
564
565 return 0;
566}
567
568static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
569{
570 u32 *iopgd = iopgd_offset(obj, da);
571 u32 *iopte = iopte_alloc(obj, iopgd, da);
572 int i;
573
574 if ((da | pa) & ~IOLARGE_MASK) {
575 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
576 __func__, da, pa, IOLARGE_SIZE);
577 return -EINVAL;
578 }
579
580 if (IS_ERR(iopte))
581 return PTR_ERR(iopte);
582
583 for (i = 0; i < 16; i++)
584 *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE;
585 flush_iopte_range(iopte, iopte + 15);
586 return 0;
587}
588
589static int
590iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e)
591{
592 int (*fn)(struct omap_iommu *, u32, u32, u32);
593 u32 prot;
594 int err;
595
596 if (!obj || !e)
597 return -EINVAL;
598
599 switch (e->pgsz) {
600 case MMU_CAM_PGSZ_16M:
601 fn = iopgd_alloc_super;
602 break;
603 case MMU_CAM_PGSZ_1M:
604 fn = iopgd_alloc_section;
605 break;
606 case MMU_CAM_PGSZ_64K:
607 fn = iopte_alloc_large;
608 break;
609 case MMU_CAM_PGSZ_4K:
610 fn = iopte_alloc_page;
611 break;
612 default:
613 fn = NULL;
614 BUG();
615 break;
616 }
617
618 prot = get_iopte_attr(e);
619
620 spin_lock(&obj->page_table_lock);
621 err = fn(obj, e->da, e->pa, prot);
622 spin_unlock(&obj->page_table_lock);
623
624 return err;
625}
626
627/**
628 * omap_iopgtable_store_entry - Make an iommu pte entry
629 * @obj: target iommu
630 * @e: an iommu tlb entry info
631 **/
632static int
633omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e)
634{
635 int err;
636
637 flush_iotlb_page(obj, e->da);
638 err = iopgtable_store_entry_core(obj, e);
639 if (!err)
640 prefetch_iotlb_entry(obj, e);
641 return err;
642}
643
644/**
645 * iopgtable_lookup_entry - Lookup an iommu pte entry
646 * @obj: target iommu
647 * @da: iommu device virtual address
648 * @ppgd: iommu pgd entry pointer to be returned
649 * @ppte: iommu pte entry pointer to be returned
650 **/
651static void
652iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte)
653{
654 u32 *iopgd, *iopte = NULL;
655
656 iopgd = iopgd_offset(obj, da);
657 if (!*iopgd)
658 goto out;
659
660 if (iopgd_is_table(*iopgd))
661 iopte = iopte_offset(iopgd, da);
662out:
663 *ppgd = iopgd;
664 *ppte = iopte;
665}
666
667static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da)
668{
669 size_t bytes;
670 u32 *iopgd = iopgd_offset(obj, da);
671 int nent = 1;
672
673 if (!*iopgd)
674 return 0;
675
676 if (iopgd_is_table(*iopgd)) {
677 int i;
678 u32 *iopte = iopte_offset(iopgd, da);
679
680 bytes = IOPTE_SIZE;
681 if (*iopte & IOPTE_LARGE) {
682 nent *= 16;
683 /* rewind to the 1st entry */
684 iopte = iopte_offset(iopgd, (da & IOLARGE_MASK));
685 }
686 bytes *= nent;
687 memset(iopte, 0, nent * sizeof(*iopte));
688 flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte));
689
690 /*
691 * do table walk to check if this table is necessary or not
692 */
693 iopte = iopte_offset(iopgd, 0);
694 for (i = 0; i < PTRS_PER_IOPTE; i++)
695 if (iopte[i])
696 goto out;
697
698 iopte_free(iopte);
699 nent = 1; /* for the next L1 entry */
700 } else {
701 bytes = IOPGD_SIZE;
702 if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) {
703 nent *= 16;
704 /* rewind to the 1st entry */
705 iopgd = iopgd_offset(obj, (da & IOSUPER_MASK));
706 }
707 bytes *= nent;
708 }
709 memset(iopgd, 0, nent * sizeof(*iopgd));
710 flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd));
711out:
712 return bytes;
713}
714
715/**
716 * iopgtable_clear_entry - Remove an iommu pte entry
717 * @obj: target iommu
718 * @da: iommu device virtual address
719 **/
720static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da)
721{
722 size_t bytes;
723
724 spin_lock(&obj->page_table_lock);
725
726 bytes = iopgtable_clear_entry_core(obj, da);
727 flush_iotlb_page(obj, da);
728
729 spin_unlock(&obj->page_table_lock);
730
731 return bytes;
732}
733
734static void iopgtable_clear_entry_all(struct omap_iommu *obj)
735{
736 int i;
737
738 spin_lock(&obj->page_table_lock);
739
740 for (i = 0; i < PTRS_PER_IOPGD; i++) {
741 u32 da;
742 u32 *iopgd;
743
744 da = i << IOPGD_SHIFT;
745 iopgd = iopgd_offset(obj, da);
746
747 if (!*iopgd)
748 continue;
749
750 if (iopgd_is_table(*iopgd))
751 iopte_free(iopte_offset(iopgd, 0));
752
753 *iopgd = 0;
754 flush_iopgd_range(iopgd, iopgd);
755 }
756
757 flush_iotlb_all(obj);
758
759 spin_unlock(&obj->page_table_lock);
760}
761
762/*
763 * Device IOMMU generic operations
764 */
765static irqreturn_t iommu_fault_handler(int irq, void *data)
766{
767 u32 da, errs;
768 u32 *iopgd, *iopte;
769 struct omap_iommu *obj = data;
770 struct iommu_domain *domain = obj->domain;
771 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
772
773 if (!omap_domain->iommu_dev)
774 return IRQ_NONE;
775
776 errs = iommu_report_fault(obj, &da);
777 if (errs == 0)
778 return IRQ_HANDLED;
779
780 /* Fault callback or TLB/PTE Dynamic loading */
781 if (!report_iommu_fault(domain, obj->dev, da, 0))
782 return IRQ_HANDLED;
783
784 iommu_disable(obj);
785
786 iopgd = iopgd_offset(obj, da);
787
788 if (!iopgd_is_table(*iopgd)) {
789 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:px%08x\n",
790 obj->name, errs, da, iopgd, *iopgd);
791 return IRQ_NONE;
792 }
793
794 iopte = iopte_offset(iopgd, da);
795
796 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x pte:0x%p *pte:0x%08x\n",
797 obj->name, errs, da, iopgd, *iopgd, iopte, *iopte);
798
799 return IRQ_NONE;
800}
801
802static int device_match_by_alias(struct device *dev, void *data)
803{
804 struct omap_iommu *obj = to_iommu(dev);
805 const char *name = data;
806
807 pr_debug("%s: %s %s\n", __func__, obj->name, name);
808
809 return strcmp(obj->name, name) == 0;
810}
811
812/**
813 * omap_iommu_attach() - attach iommu device to an iommu domain
814 * @name: name of target omap iommu device
815 * @iopgd: page table
816 **/
817static struct omap_iommu *omap_iommu_attach(const char *name, u32 *iopgd)
818{
819 int err;
820 struct device *dev;
821 struct omap_iommu *obj;
822
823 dev = driver_find_device(&omap_iommu_driver.driver, NULL,
824 (void *)name,
825 device_match_by_alias);
826 if (!dev)
827 return ERR_PTR(-ENODEV);
828
829 obj = to_iommu(dev);
830
831 spin_lock(&obj->iommu_lock);
832
833 obj->iopgd = iopgd;
834 err = iommu_enable(obj);
835 if (err)
836 goto err_enable;
837 flush_iotlb_all(obj);
838
839 spin_unlock(&obj->iommu_lock);
840
841 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
842 return obj;
843
844err_enable:
845 spin_unlock(&obj->iommu_lock);
846 return ERR_PTR(err);
847}
848
849/**
850 * omap_iommu_detach - release iommu device
851 * @obj: target iommu
852 **/
853static void omap_iommu_detach(struct omap_iommu *obj)
854{
855 if (!obj || IS_ERR(obj))
856 return;
857
858 spin_lock(&obj->iommu_lock);
859
860 iommu_disable(obj);
861 obj->iopgd = NULL;
862
863 spin_unlock(&obj->iommu_lock);
864
865 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
866}
867
868/*
869 * OMAP Device MMU(IOMMU) detection
870 */
871static int omap_iommu_probe(struct platform_device *pdev)
872{
873 int err = -ENODEV;
874 int irq;
875 struct omap_iommu *obj;
876 struct resource *res;
877 struct iommu_platform_data *pdata = dev_get_platdata(&pdev->dev);
878 struct device_node *of = pdev->dev.of_node;
879
880 obj = devm_kzalloc(&pdev->dev, sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL);
881 if (!obj)
882 return -ENOMEM;
883
884 if (of) {
885 obj->name = dev_name(&pdev->dev);
886 obj->nr_tlb_entries = 32;
887 err = of_property_read_u32(of, "ti,#tlb-entries",
888 &obj->nr_tlb_entries);
889 if (err && err != -EINVAL)
890 return err;
891 if (obj->nr_tlb_entries != 32 && obj->nr_tlb_entries != 8)
892 return -EINVAL;
893 if (of_find_property(of, "ti,iommu-bus-err-back", NULL))
894 obj->has_bus_err_back = MMU_GP_REG_BUS_ERR_BACK_EN;
895 } else {
896 obj->nr_tlb_entries = pdata->nr_tlb_entries;
897 obj->name = pdata->name;
898 }
899
900 obj->dev = &pdev->dev;
901 obj->ctx = (void *)obj + sizeof(*obj);
902
903 spin_lock_init(&obj->iommu_lock);
904 spin_lock_init(&obj->page_table_lock);
905
906 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
907 obj->regbase = devm_ioremap_resource(obj->dev, res);
908 if (IS_ERR(obj->regbase))
909 return PTR_ERR(obj->regbase);
910
911 irq = platform_get_irq(pdev, 0);
912 if (irq < 0)
913 return -ENODEV;
914
915 err = devm_request_irq(obj->dev, irq, iommu_fault_handler, IRQF_SHARED,
916 dev_name(obj->dev), obj);
917 if (err < 0)
918 return err;
919 platform_set_drvdata(pdev, obj);
920
921 pm_runtime_irq_safe(obj->dev);
922 pm_runtime_enable(obj->dev);
923
924 omap_iommu_debugfs_add(obj);
925
926 dev_info(&pdev->dev, "%s registered\n", obj->name);
927 return 0;
928}
929
930static int omap_iommu_remove(struct platform_device *pdev)
931{
932 struct omap_iommu *obj = platform_get_drvdata(pdev);
933
934 iopgtable_clear_entry_all(obj);
935 omap_iommu_debugfs_remove(obj);
936
937 pm_runtime_disable(obj->dev);
938
939 dev_info(&pdev->dev, "%s removed\n", obj->name);
940 return 0;
941}
942
943static const struct of_device_id omap_iommu_of_match[] = {
944 { .compatible = "ti,omap2-iommu" },
945 { .compatible = "ti,omap4-iommu" },
946 { .compatible = "ti,dra7-iommu" },
947 {},
948};
949
950static struct platform_driver omap_iommu_driver = {
951 .probe = omap_iommu_probe,
952 .remove = omap_iommu_remove,
953 .driver = {
954 .name = "omap-iommu",
955 .of_match_table = of_match_ptr(omap_iommu_of_match),
956 },
957};
958
959static void iopte_cachep_ctor(void *iopte)
960{
961 clean_dcache_area(iopte, IOPTE_TABLE_SIZE);
962}
963
964static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, int pgsz)
965{
966 memset(e, 0, sizeof(*e));
967
968 e->da = da;
969 e->pa = pa;
970 e->valid = MMU_CAM_V;
971 e->pgsz = pgsz;
972 e->endian = MMU_RAM_ENDIAN_LITTLE;
973 e->elsz = MMU_RAM_ELSZ_8;
974 e->mixed = 0;
975
976 return iopgsz_to_bytes(e->pgsz);
977}
978
979static int omap_iommu_map(struct iommu_domain *domain, unsigned long da,
980 phys_addr_t pa, size_t bytes, int prot)
981{
982 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
983 struct omap_iommu *oiommu = omap_domain->iommu_dev;
984 struct device *dev = oiommu->dev;
985 struct iotlb_entry e;
986 int omap_pgsz;
987 u32 ret;
988
989 omap_pgsz = bytes_to_iopgsz(bytes);
990 if (omap_pgsz < 0) {
991 dev_err(dev, "invalid size to map: %d\n", bytes);
992 return -EINVAL;
993 }
994
995 dev_dbg(dev, "mapping da 0x%lx to pa %pa size 0x%x\n", da, &pa, bytes);
996
997 iotlb_init_entry(&e, da, pa, omap_pgsz);
998
999 ret = omap_iopgtable_store_entry(oiommu, &e);
1000 if (ret)
1001 dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", ret);
1002
1003 return ret;
1004}
1005
1006static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da,
1007 size_t size)
1008{
1009 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1010 struct omap_iommu *oiommu = omap_domain->iommu_dev;
1011 struct device *dev = oiommu->dev;
1012
1013 dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size);
1014
1015 return iopgtable_clear_entry(oiommu, da);
1016}
1017
1018static int
1019omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
1020{
1021 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1022 struct omap_iommu *oiommu;
1023 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1024 int ret = 0;
1025
1026 if (!arch_data || !arch_data->name) {
1027 dev_err(dev, "device doesn't have an associated iommu\n");
1028 return -EINVAL;
1029 }
1030
1031 spin_lock(&omap_domain->lock);
1032
1033 /* only a single device is supported per domain for now */
1034 if (omap_domain->iommu_dev) {
1035 dev_err(dev, "iommu domain is already attached\n");
1036 ret = -EBUSY;
1037 goto out;
1038 }
1039
1040 /* get a handle to and enable the omap iommu */
1041 oiommu = omap_iommu_attach(arch_data->name, omap_domain->pgtable);
1042 if (IS_ERR(oiommu)) {
1043 ret = PTR_ERR(oiommu);
1044 dev_err(dev, "can't get omap iommu: %d\n", ret);
1045 goto out;
1046 }
1047
1048 omap_domain->iommu_dev = arch_data->iommu_dev = oiommu;
1049 omap_domain->dev = dev;
1050 oiommu->domain = domain;
1051
1052out:
1053 spin_unlock(&omap_domain->lock);
1054 return ret;
1055}
1056
1057static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain,
1058 struct device *dev)
1059{
1060 struct omap_iommu *oiommu = dev_to_omap_iommu(dev);
1061 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1062
1063 /* only a single device is supported per domain for now */
1064 if (omap_domain->iommu_dev != oiommu) {
1065 dev_err(dev, "invalid iommu device\n");
1066 return;
1067 }
1068
1069 iopgtable_clear_entry_all(oiommu);
1070
1071 omap_iommu_detach(oiommu);
1072
1073 omap_domain->iommu_dev = arch_data->iommu_dev = NULL;
1074 omap_domain->dev = NULL;
1075 oiommu->domain = NULL;
1076}
1077
1078static void omap_iommu_detach_dev(struct iommu_domain *domain,
1079 struct device *dev)
1080{
1081 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1082
1083 spin_lock(&omap_domain->lock);
1084 _omap_iommu_detach_dev(omap_domain, dev);
1085 spin_unlock(&omap_domain->lock);
1086}
1087
1088static struct iommu_domain *omap_iommu_domain_alloc(unsigned type)
1089{
1090 struct omap_iommu_domain *omap_domain;
1091
1092 if (type != IOMMU_DOMAIN_UNMANAGED)
1093 return NULL;
1094
1095 omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL);
1096 if (!omap_domain) {
1097 pr_err("kzalloc failed\n");
1098 goto out;
1099 }
1100
1101 omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL);
1102 if (!omap_domain->pgtable) {
1103 pr_err("kzalloc failed\n");
1104 goto fail_nomem;
1105 }
1106
1107 /*
1108 * should never fail, but please keep this around to ensure
1109 * we keep the hardware happy
1110 */
1111 BUG_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE));
1112
1113 clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE);
1114 spin_lock_init(&omap_domain->lock);
1115
1116 omap_domain->domain.geometry.aperture_start = 0;
1117 omap_domain->domain.geometry.aperture_end = (1ULL << 32) - 1;
1118 omap_domain->domain.geometry.force_aperture = true;
1119
1120 return &omap_domain->domain;
1121
1122fail_nomem:
1123 kfree(omap_domain);
1124out:
1125 return NULL;
1126}
1127
1128static void omap_iommu_domain_free(struct iommu_domain *domain)
1129{
1130 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1131
1132 /*
1133 * An iommu device is still attached
1134 * (currently, only one device can be attached) ?
1135 */
1136 if (omap_domain->iommu_dev)
1137 _omap_iommu_detach_dev(omap_domain, omap_domain->dev);
1138
1139 kfree(omap_domain->pgtable);
1140 kfree(omap_domain);
1141}
1142
1143static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain,
1144 dma_addr_t da)
1145{
1146 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1147 struct omap_iommu *oiommu = omap_domain->iommu_dev;
1148 struct device *dev = oiommu->dev;
1149 u32 *pgd, *pte;
1150 phys_addr_t ret = 0;
1151
1152 iopgtable_lookup_entry(oiommu, da, &pgd, &pte);
1153
1154 if (pte) {
1155 if (iopte_is_small(*pte))
1156 ret = omap_iommu_translate(*pte, da, IOPTE_MASK);
1157 else if (iopte_is_large(*pte))
1158 ret = omap_iommu_translate(*pte, da, IOLARGE_MASK);
1159 else
1160 dev_err(dev, "bogus pte 0x%x, da 0x%llx", *pte,
1161 (unsigned long long)da);
1162 } else {
1163 if (iopgd_is_section(*pgd))
1164 ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK);
1165 else if (iopgd_is_super(*pgd))
1166 ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK);
1167 else
1168 dev_err(dev, "bogus pgd 0x%x, da 0x%llx", *pgd,
1169 (unsigned long long)da);
1170 }
1171
1172 return ret;
1173}
1174
1175static int omap_iommu_add_device(struct device *dev)
1176{
1177 struct omap_iommu_arch_data *arch_data;
1178 struct device_node *np;
1179 struct platform_device *pdev;
1180
1181 /*
1182 * Allocate the archdata iommu structure for DT-based devices.
1183 *
1184 * TODO: Simplify this when removing non-DT support completely from the
1185 * IOMMU users.
1186 */
1187 if (!dev->of_node)
1188 return 0;
1189
1190 np = of_parse_phandle(dev->of_node, "iommus", 0);
1191 if (!np)
1192 return 0;
1193
1194 pdev = of_find_device_by_node(np);
1195 if (WARN_ON(!pdev)) {
1196 of_node_put(np);
1197 return -EINVAL;
1198 }
1199
1200 arch_data = kzalloc(sizeof(*arch_data), GFP_KERNEL);
1201 if (!arch_data) {
1202 of_node_put(np);
1203 return -ENOMEM;
1204 }
1205
1206 arch_data->name = kstrdup(dev_name(&pdev->dev), GFP_KERNEL);
1207 dev->archdata.iommu = arch_data;
1208
1209 of_node_put(np);
1210
1211 return 0;
1212}
1213
1214static void omap_iommu_remove_device(struct device *dev)
1215{
1216 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1217
1218 if (!dev->of_node || !arch_data)
1219 return;
1220
1221 kfree(arch_data->name);
1222 kfree(arch_data);
1223}
1224
1225static const struct iommu_ops omap_iommu_ops = {
1226 .domain_alloc = omap_iommu_domain_alloc,
1227 .domain_free = omap_iommu_domain_free,
1228 .attach_dev = omap_iommu_attach_dev,
1229 .detach_dev = omap_iommu_detach_dev,
1230 .map = omap_iommu_map,
1231 .unmap = omap_iommu_unmap,
1232 .map_sg = default_iommu_map_sg,
1233 .iova_to_phys = omap_iommu_iova_to_phys,
1234 .add_device = omap_iommu_add_device,
1235 .remove_device = omap_iommu_remove_device,
1236 .pgsize_bitmap = OMAP_IOMMU_PGSIZES,
1237};
1238
1239static int __init omap_iommu_init(void)
1240{
1241 struct kmem_cache *p;
1242 const unsigned long flags = SLAB_HWCACHE_ALIGN;
1243 size_t align = 1 << 10; /* L2 pagetable alignement */
1244 struct device_node *np;
1245
1246 np = of_find_matching_node(NULL, omap_iommu_of_match);
1247 if (!np)
1248 return 0;
1249
1250 of_node_put(np);
1251
1252 p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags,
1253 iopte_cachep_ctor);
1254 if (!p)
1255 return -ENOMEM;
1256 iopte_cachep = p;
1257
1258 bus_set_iommu(&platform_bus_type, &omap_iommu_ops);
1259
1260 omap_iommu_debugfs_init();
1261
1262 return platform_driver_register(&omap_iommu_driver);
1263}
1264subsys_initcall(omap_iommu_init);
1265/* must be ready before omap3isp is probed */
Linux kernel - Deliverables
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