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[deliverable/linux.git] / drivers / mtd / nand / bf5xx_nand.c
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1/* linux/drivers/mtd/nand/bf5xx_nand.c
2 *
3 * Copyright 2006-2008 Analog Devices Inc.
4 * http://blackfin.uclinux.org/
5 * Bryan Wu <bryan.wu@analog.com>
6 *
7 * Blackfin BF5xx on-chip NAND flash controller driver
8 *
9 * Derived from drivers/mtd/nand/s3c2410.c
10 * Copyright (c) 2007 Ben Dooks <ben@simtec.co.uk>
11 *
12 * Derived from drivers/mtd/nand/cafe.c
13 * Copyright © 2006 Red Hat, Inc.
14 * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
15 *
16 * Changelog:
17 * 12-Jun-2007 Bryan Wu: Initial version
18 * 18-Jul-2007 Bryan Wu:
19 * - ECC_HW and ECC_SW supported
20 * - DMA supported in ECC_HW
21 * - YAFFS tested as rootfs in both ECC_HW and ECC_SW
22 *
23 * This program is free software; you can redistribute it and/or modify
24 * it under the terms of the GNU General Public License as published by
25 * the Free Software Foundation; either version 2 of the License, or
26 * (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
36*/
37
38#include <linux/module.h>
39#include <linux/types.h>
40#include <linux/kernel.h>
41#include <linux/string.h>
42#include <linux/ioport.h>
43#include <linux/platform_device.h>
44#include <linux/delay.h>
45#include <linux/dma-mapping.h>
46#include <linux/err.h>
47#include <linux/slab.h>
48#include <linux/io.h>
49#include <linux/bitops.h>
50
51#include <linux/mtd/mtd.h>
52#include <linux/mtd/nand.h>
53#include <linux/mtd/nand_ecc.h>
54#include <linux/mtd/partitions.h>
55
56#include <asm/blackfin.h>
57#include <asm/dma.h>
58#include <asm/cacheflush.h>
59#include <asm/nand.h>
60#include <asm/portmux.h>
61
62#define DRV_NAME "bf5xx-nand"
63#define DRV_VERSION "1.2"
64#define DRV_AUTHOR "Bryan Wu <bryan.wu@analog.com>"
65#define DRV_DESC "BF5xx on-chip NAND FLash Controller Driver"
66
67/* NFC_STAT Masks */
68#define NBUSY 0x01 /* Not Busy */
69#define WB_FULL 0x02 /* Write Buffer Full */
70#define PG_WR_STAT 0x04 /* Page Write Pending */
71#define PG_RD_STAT 0x08 /* Page Read Pending */
72#define WB_EMPTY 0x10 /* Write Buffer Empty */
73
74/* NFC_IRQSTAT Masks */
75#define NBUSYIRQ 0x01 /* Not Busy IRQ */
76#define WB_OVF 0x02 /* Write Buffer Overflow */
77#define WB_EDGE 0x04 /* Write Buffer Edge Detect */
78#define RD_RDY 0x08 /* Read Data Ready */
79#define WR_DONE 0x10 /* Page Write Done */
80
81/* NFC_RST Masks */
82#define ECC_RST 0x01 /* ECC (and NFC counters) Reset */
83
84/* NFC_PGCTL Masks */
85#define PG_RD_START 0x01 /* Page Read Start */
86#define PG_WR_START 0x02 /* Page Write Start */
87
88#ifdef CONFIG_MTD_NAND_BF5XX_HWECC
89static int hardware_ecc = 1;
90#else
91static int hardware_ecc;
92#endif
93
94static const unsigned short bfin_nfc_pin_req[] =
95 {P_NAND_CE,
96 P_NAND_RB,
97 P_NAND_D0,
98 P_NAND_D1,
99 P_NAND_D2,
100 P_NAND_D3,
101 P_NAND_D4,
102 P_NAND_D5,
103 P_NAND_D6,
104 P_NAND_D7,
105 P_NAND_WE,
106 P_NAND_RE,
107 P_NAND_CLE,
108 P_NAND_ALE,
109 0};
110
111#ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
112static int bootrom_ooblayout_ecc(struct mtd_info *mtd, int section,
113 struct mtd_oob_region *oobregion)
114{
115 if (section > 7)
116 return -ERANGE;
117
118 oobregion->offset = section * 8;
119 oobregion->length = 3;
120
121 return 0;
122}
123
124static int bootrom_ooblayout_free(struct mtd_info *mtd, int section,
125 struct mtd_oob_region *oobregion)
126{
127 if (section > 7)
128 return -ERANGE;
129
130 oobregion->offset = (section * 8) + 3;
131 oobregion->length = 5;
132
133 return 0;
134}
135
136static const struct mtd_ooblayout_ops bootrom_ooblayout_ops = {
137 .ecc = bootrom_ooblayout_ecc,
138 .free = bootrom_ooblayout_free,
139};
140#endif
141
142/*
143 * Data structures for bf5xx nand flash controller driver
144 */
145
146/* bf5xx nand info */
147struct bf5xx_nand_info {
148 /* mtd info */
149 struct nand_hw_control controller;
150 struct nand_chip chip;
151
152 /* platform info */
153 struct bf5xx_nand_platform *platform;
154
155 /* device info */
156 struct device *device;
157
158 /* DMA stuff */
159 struct completion dma_completion;
160};
161
162/*
163 * Conversion functions
164 */
165static struct bf5xx_nand_info *mtd_to_nand_info(struct mtd_info *mtd)
166{
167 return container_of(mtd_to_nand(mtd), struct bf5xx_nand_info,
168 chip);
169}
170
171static struct bf5xx_nand_info *to_nand_info(struct platform_device *pdev)
172{
173 return platform_get_drvdata(pdev);
174}
175
176static struct bf5xx_nand_platform *to_nand_plat(struct platform_device *pdev)
177{
178 return dev_get_platdata(&pdev->dev);
179}
180
181/*
182 * struct nand_chip interface function pointers
183 */
184
185/*
186 * bf5xx_nand_hwcontrol
187 *
188 * Issue command and address cycles to the chip
189 */
190static void bf5xx_nand_hwcontrol(struct mtd_info *mtd, int cmd,
191 unsigned int ctrl)
192{
193 if (cmd == NAND_CMD_NONE)
194 return;
195
196 while (bfin_read_NFC_STAT() & WB_FULL)
197 cpu_relax();
198
199 if (ctrl & NAND_CLE)
200 bfin_write_NFC_CMD(cmd);
201 else if (ctrl & NAND_ALE)
202 bfin_write_NFC_ADDR(cmd);
203 SSYNC();
204}
205
206/*
207 * bf5xx_nand_devready()
208 *
209 * returns 0 if the nand is busy, 1 if it is ready
210 */
211static int bf5xx_nand_devready(struct mtd_info *mtd)
212{
213 unsigned short val = bfin_read_NFC_STAT();
214
215 if ((val & NBUSY) == NBUSY)
216 return 1;
217 else
218 return 0;
219}
220
221/*
222 * ECC functions
223 * These allow the bf5xx to use the controller's ECC
224 * generator block to ECC the data as it passes through
225 */
226
227/*
228 * ECC error correction function
229 */
230static int bf5xx_nand_correct_data_256(struct mtd_info *mtd, u_char *dat,
231 u_char *read_ecc, u_char *calc_ecc)
232{
233 struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
234 u32 syndrome[5];
235 u32 calced, stored;
236 int i;
237 unsigned short failing_bit, failing_byte;
238 u_char data;
239
240 calced = calc_ecc[0] | (calc_ecc[1] << 8) | (calc_ecc[2] << 16);
241 stored = read_ecc[0] | (read_ecc[1] << 8) | (read_ecc[2] << 16);
242
243 syndrome[0] = (calced ^ stored);
244
245 /*
246 * syndrome 0: all zero
247 * No error in data
248 * No action
249 */
250 if (!syndrome[0] || !calced || !stored)
251 return 0;
252
253 /*
254 * sysdrome 0: only one bit is one
255 * ECC data was incorrect
256 * No action
257 */
258 if (hweight32(syndrome[0]) == 1) {
259 dev_err(info->device, "ECC data was incorrect!\n");
260 return -EBADMSG;
261 }
262
263 syndrome[1] = (calced & 0x7FF) ^ (stored & 0x7FF);
264 syndrome[2] = (calced & 0x7FF) ^ ((calced >> 11) & 0x7FF);
265 syndrome[3] = (stored & 0x7FF) ^ ((stored >> 11) & 0x7FF);
266 syndrome[4] = syndrome[2] ^ syndrome[3];
267
268 for (i = 0; i < 5; i++)
269 dev_info(info->device, "syndrome[%d] 0x%08x\n", i, syndrome[i]);
270
271 dev_info(info->device,
272 "calced[0x%08x], stored[0x%08x]\n",
273 calced, stored);
274
275 /*
276 * sysdrome 0: exactly 11 bits are one, each parity
277 * and parity' pair is 1 & 0 or 0 & 1.
278 * 1-bit correctable error
279 * Correct the error
280 */
281 if (hweight32(syndrome[0]) == 11 && syndrome[4] == 0x7FF) {
282 dev_info(info->device,
283 "1-bit correctable error, correct it.\n");
284 dev_info(info->device,
285 "syndrome[1] 0x%08x\n", syndrome[1]);
286
287 failing_bit = syndrome[1] & 0x7;
288 failing_byte = syndrome[1] >> 0x3;
289 data = *(dat + failing_byte);
290 data = data ^ (0x1 << failing_bit);
291 *(dat + failing_byte) = data;
292
293 return 1;
294 }
295
296 /*
297 * sysdrome 0: random data
298 * More than 1-bit error, non-correctable error
299 * Discard data, mark bad block
300 */
301 dev_err(info->device,
302 "More than 1-bit error, non-correctable error.\n");
303 dev_err(info->device,
304 "Please discard data, mark bad block\n");
305
306 return -EBADMSG;
307}
308
309static int bf5xx_nand_correct_data(struct mtd_info *mtd, u_char *dat,
310 u_char *read_ecc, u_char *calc_ecc)
311{
312 struct nand_chip *chip = mtd_to_nand(mtd);
313 int ret, bitflips = 0;
314
315 ret = bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc);
316 if (ret < 0)
317 return ret;
318
319 bitflips = ret;
320
321 /* If ecc size is 512, correct second 256 bytes */
322 if (chip->ecc.size == 512) {
323 dat += 256;
324 read_ecc += 3;
325 calc_ecc += 3;
326 ret = bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc);
327 if (ret < 0)
328 return ret;
329
330 bitflips += ret;
331 }
332
333 return bitflips;
334}
335
336static void bf5xx_nand_enable_hwecc(struct mtd_info *mtd, int mode)
337{
338 return;
339}
340
341static int bf5xx_nand_calculate_ecc(struct mtd_info *mtd,
342 const u_char *dat, u_char *ecc_code)
343{
344 struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
345 struct nand_chip *chip = mtd_to_nand(mtd);
346 u16 ecc0, ecc1;
347 u32 code[2];
348 u8 *p;
349
350 /* first 3 bytes ECC code for 256 page size */
351 ecc0 = bfin_read_NFC_ECC0();
352 ecc1 = bfin_read_NFC_ECC1();
353
354 code[0] = (ecc0 & 0x7ff) | ((ecc1 & 0x7ff) << 11);
355
356 dev_dbg(info->device, "returning ecc 0x%08x\n", code[0]);
357
358 p = (u8 *) code;
359 memcpy(ecc_code, p, 3);
360
361 /* second 3 bytes ECC code for 512 ecc size */
362 if (chip->ecc.size == 512) {
363 ecc0 = bfin_read_NFC_ECC2();
364 ecc1 = bfin_read_NFC_ECC3();
365 code[1] = (ecc0 & 0x7ff) | ((ecc1 & 0x7ff) << 11);
366
367 /* second 3 bytes in ecc_code for second 256
368 * bytes of 512 page size
369 */
370 p = (u8 *) (code + 1);
371 memcpy((ecc_code + 3), p, 3);
372 dev_dbg(info->device, "returning ecc 0x%08x\n", code[1]);
373 }
374
375 return 0;
376}
377
378/*
379 * PIO mode for buffer writing and reading
380 */
381static void bf5xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
382{
383 int i;
384 unsigned short val;
385
386 /*
387 * Data reads are requested by first writing to NFC_DATA_RD
388 * and then reading back from NFC_READ.
389 */
390 for (i = 0; i < len; i++) {
391 while (bfin_read_NFC_STAT() & WB_FULL)
392 cpu_relax();
393
394 /* Contents do not matter */
395 bfin_write_NFC_DATA_RD(0x0000);
396 SSYNC();
397
398 while ((bfin_read_NFC_IRQSTAT() & RD_RDY) != RD_RDY)
399 cpu_relax();
400
401 buf[i] = bfin_read_NFC_READ();
402
403 val = bfin_read_NFC_IRQSTAT();
404 val |= RD_RDY;
405 bfin_write_NFC_IRQSTAT(val);
406 SSYNC();
407 }
408}
409
410static uint8_t bf5xx_nand_read_byte(struct mtd_info *mtd)
411{
412 uint8_t val;
413
414 bf5xx_nand_read_buf(mtd, &val, 1);
415
416 return val;
417}
418
419static void bf5xx_nand_write_buf(struct mtd_info *mtd,
420 const uint8_t *buf, int len)
421{
422 int i;
423
424 for (i = 0; i < len; i++) {
425 while (bfin_read_NFC_STAT() & WB_FULL)
426 cpu_relax();
427
428 bfin_write_NFC_DATA_WR(buf[i]);
429 SSYNC();
430 }
431}
432
433static void bf5xx_nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
434{
435 int i;
436 u16 *p = (u16 *) buf;
437 len >>= 1;
438
439 /*
440 * Data reads are requested by first writing to NFC_DATA_RD
441 * and then reading back from NFC_READ.
442 */
443 bfin_write_NFC_DATA_RD(0x5555);
444
445 SSYNC();
446
447 for (i = 0; i < len; i++)
448 p[i] = bfin_read_NFC_READ();
449}
450
451static void bf5xx_nand_write_buf16(struct mtd_info *mtd,
452 const uint8_t *buf, int len)
453{
454 int i;
455 u16 *p = (u16 *) buf;
456 len >>= 1;
457
458 for (i = 0; i < len; i++)
459 bfin_write_NFC_DATA_WR(p[i]);
460
461 SSYNC();
462}
463
464/*
465 * DMA functions for buffer writing and reading
466 */
467static irqreturn_t bf5xx_nand_dma_irq(int irq, void *dev_id)
468{
469 struct bf5xx_nand_info *info = dev_id;
470
471 clear_dma_irqstat(CH_NFC);
472 disable_dma(CH_NFC);
473 complete(&info->dma_completion);
474
475 return IRQ_HANDLED;
476}
477
478static void bf5xx_nand_dma_rw(struct mtd_info *mtd,
479 uint8_t *buf, int is_read)
480{
481 struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
482 struct nand_chip *chip = mtd_to_nand(mtd);
483 unsigned short val;
484
485 dev_dbg(info->device, " mtd->%p, buf->%p, is_read %d\n",
486 mtd, buf, is_read);
487
488 /*
489 * Before starting a dma transfer, be sure to invalidate/flush
490 * the cache over the address range of your DMA buffer to
491 * prevent cache coherency problems. Otherwise very subtle bugs
492 * can be introduced to your driver.
493 */
494 if (is_read)
495 invalidate_dcache_range((unsigned int)buf,
496 (unsigned int)(buf + chip->ecc.size));
497 else
498 flush_dcache_range((unsigned int)buf,
499 (unsigned int)(buf + chip->ecc.size));
500
501 /*
502 * This register must be written before each page is
503 * transferred to generate the correct ECC register
504 * values.
505 */
506 bfin_write_NFC_RST(ECC_RST);
507 SSYNC();
508 while (bfin_read_NFC_RST() & ECC_RST)
509 cpu_relax();
510
511 disable_dma(CH_NFC);
512 clear_dma_irqstat(CH_NFC);
513
514 /* setup DMA register with Blackfin DMA API */
515 set_dma_config(CH_NFC, 0x0);
516 set_dma_start_addr(CH_NFC, (unsigned long) buf);
517
518 /* The DMAs have different size on BF52x and BF54x */
519#ifdef CONFIG_BF52x
520 set_dma_x_count(CH_NFC, (chip->ecc.size >> 1));
521 set_dma_x_modify(CH_NFC, 2);
522 val = DI_EN | WDSIZE_16;
523#endif
524
525#ifdef CONFIG_BF54x
526 set_dma_x_count(CH_NFC, (chip->ecc.size >> 2));
527 set_dma_x_modify(CH_NFC, 4);
528 val = DI_EN | WDSIZE_32;
529#endif
530 /* setup write or read operation */
531 if (is_read)
532 val |= WNR;
533 set_dma_config(CH_NFC, val);
534 enable_dma(CH_NFC);
535
536 /* Start PAGE read/write operation */
537 if (is_read)
538 bfin_write_NFC_PGCTL(PG_RD_START);
539 else
540 bfin_write_NFC_PGCTL(PG_WR_START);
541 wait_for_completion(&info->dma_completion);
542}
543
544static void bf5xx_nand_dma_read_buf(struct mtd_info *mtd,
545 uint8_t *buf, int len)
546{
547 struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
548 struct nand_chip *chip = mtd_to_nand(mtd);
549
550 dev_dbg(info->device, "mtd->%p, buf->%p, int %d\n", mtd, buf, len);
551
552 if (len == chip->ecc.size)
553 bf5xx_nand_dma_rw(mtd, buf, 1);
554 else
555 bf5xx_nand_read_buf(mtd, buf, len);
556}
557
558static void bf5xx_nand_dma_write_buf(struct mtd_info *mtd,
559 const uint8_t *buf, int len)
560{
561 struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
562 struct nand_chip *chip = mtd_to_nand(mtd);
563
564 dev_dbg(info->device, "mtd->%p, buf->%p, len %d\n", mtd, buf, len);
565
566 if (len == chip->ecc.size)
567 bf5xx_nand_dma_rw(mtd, (uint8_t *)buf, 0);
568 else
569 bf5xx_nand_write_buf(mtd, buf, len);
570}
571
572static int bf5xx_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
573 uint8_t *buf, int oob_required, int page)
574{
575 bf5xx_nand_read_buf(mtd, buf, mtd->writesize);
576 bf5xx_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize);
577
578 return 0;
579}
580
581static int bf5xx_nand_write_page_raw(struct mtd_info *mtd,
582 struct nand_chip *chip, const uint8_t *buf, int oob_required,
583 int page)
584{
585 bf5xx_nand_write_buf(mtd, buf, mtd->writesize);
586 bf5xx_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
587
588 return 0;
589}
590
591/*
592 * System initialization functions
593 */
594static int bf5xx_nand_dma_init(struct bf5xx_nand_info *info)
595{
596 int ret;
597
598 /* Do not use dma */
599 if (!hardware_ecc)
600 return 0;
601
602 init_completion(&info->dma_completion);
603
604 /* Request NFC DMA channel */
605 ret = request_dma(CH_NFC, "BF5XX NFC driver");
606 if (ret < 0) {
607 dev_err(info->device, " unable to get DMA channel\n");
608 return ret;
609 }
610
611#ifdef CONFIG_BF54x
612 /* Setup DMAC1 channel mux for NFC which shared with SDH */
613 bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() & ~1);
614 SSYNC();
615#endif
616
617 set_dma_callback(CH_NFC, bf5xx_nand_dma_irq, info);
618
619 /* Turn off the DMA channel first */
620 disable_dma(CH_NFC);
621 return 0;
622}
623
624static void bf5xx_nand_dma_remove(struct bf5xx_nand_info *info)
625{
626 /* Free NFC DMA channel */
627 if (hardware_ecc)
628 free_dma(CH_NFC);
629}
630
631/*
632 * BF5XX NFC hardware initialization
633 * - pin mux setup
634 * - clear interrupt status
635 */
636static int bf5xx_nand_hw_init(struct bf5xx_nand_info *info)
637{
638 int err = 0;
639 unsigned short val;
640 struct bf5xx_nand_platform *plat = info->platform;
641
642 /* setup NFC_CTL register */
643 dev_info(info->device,
644 "data_width=%d, wr_dly=%d, rd_dly=%d\n",
645 (plat->data_width ? 16 : 8),
646 plat->wr_dly, plat->rd_dly);
647
648 val = (1 << NFC_PG_SIZE_OFFSET) |
649 (plat->data_width << NFC_NWIDTH_OFFSET) |
650 (plat->rd_dly << NFC_RDDLY_OFFSET) |
651 (plat->wr_dly << NFC_WRDLY_OFFSET);
652 dev_dbg(info->device, "NFC_CTL is 0x%04x\n", val);
653
654 bfin_write_NFC_CTL(val);
655 SSYNC();
656
657 /* clear interrupt status */
658 bfin_write_NFC_IRQMASK(0x0);
659 SSYNC();
660 val = bfin_read_NFC_IRQSTAT();
661 bfin_write_NFC_IRQSTAT(val);
662 SSYNC();
663
664 /* DMA initialization */
665 if (bf5xx_nand_dma_init(info))
666 err = -ENXIO;
667
668 return err;
669}
670
671/*
672 * Device management interface
673 */
674static int bf5xx_nand_add_partition(struct bf5xx_nand_info *info)
675{
676 struct mtd_info *mtd = nand_to_mtd(&info->chip);
677 struct mtd_partition *parts = info->platform->partitions;
678 int nr = info->platform->nr_partitions;
679
680 return mtd_device_register(mtd, parts, nr);
681}
682
683static int bf5xx_nand_remove(struct platform_device *pdev)
684{
685 struct bf5xx_nand_info *info = to_nand_info(pdev);
686
687 /* first thing we need to do is release all our mtds
688 * and their partitions, then go through freeing the
689 * resources used
690 */
691 nand_release(nand_to_mtd(&info->chip));
692
693 peripheral_free_list(bfin_nfc_pin_req);
694 bf5xx_nand_dma_remove(info);
695
696 return 0;
697}
698
699static int bf5xx_nand_scan(struct mtd_info *mtd)
700{
701 struct nand_chip *chip = mtd_to_nand(mtd);
702 int ret;
703
704 ret = nand_scan_ident(mtd, 1, NULL);
705 if (ret)
706 return ret;
707
708 if (hardware_ecc) {
709 /*
710 * for nand with page size > 512B, think it as several sections with 512B
711 */
712 if (likely(mtd->writesize >= 512)) {
713 chip->ecc.size = 512;
714 chip->ecc.bytes = 6;
715 chip->ecc.strength = 2;
716 } else {
717 chip->ecc.size = 256;
718 chip->ecc.bytes = 3;
719 chip->ecc.strength = 1;
720 bfin_write_NFC_CTL(bfin_read_NFC_CTL() & ~(1 << NFC_PG_SIZE_OFFSET));
721 SSYNC();
722 }
723 }
724
725 return nand_scan_tail(mtd);
726}
727
728/*
729 * bf5xx_nand_probe
730 *
731 * called by device layer when it finds a device matching
732 * one our driver can handled. This code checks to see if
733 * it can allocate all necessary resources then calls the
734 * nand layer to look for devices
735 */
736static int bf5xx_nand_probe(struct platform_device *pdev)
737{
738 struct bf5xx_nand_platform *plat = to_nand_plat(pdev);
739 struct bf5xx_nand_info *info = NULL;
740 struct nand_chip *chip = NULL;
741 struct mtd_info *mtd = NULL;
742 int err = 0;
743
744 dev_dbg(&pdev->dev, "(%p)\n", pdev);
745
746 if (!plat) {
747 dev_err(&pdev->dev, "no platform specific information\n");
748 return -EINVAL;
749 }
750
751 if (peripheral_request_list(bfin_nfc_pin_req, DRV_NAME)) {
752 dev_err(&pdev->dev, "requesting Peripherals failed\n");
753 return -EFAULT;
754 }
755
756 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
757 if (info == NULL) {
758 err = -ENOMEM;
759 goto out_err;
760 }
761
762 platform_set_drvdata(pdev, info);
763
764 nand_hw_control_init(&info->controller);
765
766 info->device = &pdev->dev;
767 info->platform = plat;
768
769 /* initialise chip data struct */
770 chip = &info->chip;
771 mtd = nand_to_mtd(&info->chip);
772
773 if (plat->data_width)
774 chip->options |= NAND_BUSWIDTH_16;
775
776 chip->options |= NAND_CACHEPRG | NAND_SKIP_BBTSCAN;
777
778 chip->read_buf = (plat->data_width) ?
779 bf5xx_nand_read_buf16 : bf5xx_nand_read_buf;
780 chip->write_buf = (plat->data_width) ?
781 bf5xx_nand_write_buf16 : bf5xx_nand_write_buf;
782
783 chip->read_byte = bf5xx_nand_read_byte;
784
785 chip->cmd_ctrl = bf5xx_nand_hwcontrol;
786 chip->dev_ready = bf5xx_nand_devready;
787
788 nand_set_controller_data(chip, mtd);
789 chip->controller = &info->controller;
790
791 chip->IO_ADDR_R = (void __iomem *) NFC_READ;
792 chip->IO_ADDR_W = (void __iomem *) NFC_DATA_WR;
793
794 chip->chip_delay = 0;
795
796 /* initialise mtd info data struct */
797 mtd->dev.parent = &pdev->dev;
798
799 /* initialise the hardware */
800 err = bf5xx_nand_hw_init(info);
801 if (err)
802 goto out_err;
803
804 /* setup hardware ECC data struct */
805 if (hardware_ecc) {
806#ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
807 mtd_set_ooblayout(mtd, &bootrom_ooblayout_ops);
808#endif
809 chip->read_buf = bf5xx_nand_dma_read_buf;
810 chip->write_buf = bf5xx_nand_dma_write_buf;
811 chip->ecc.calculate = bf5xx_nand_calculate_ecc;
812 chip->ecc.correct = bf5xx_nand_correct_data;
813 chip->ecc.mode = NAND_ECC_HW;
814 chip->ecc.hwctl = bf5xx_nand_enable_hwecc;
815 chip->ecc.read_page_raw = bf5xx_nand_read_page_raw;
816 chip->ecc.write_page_raw = bf5xx_nand_write_page_raw;
817 } else {
818 chip->ecc.mode = NAND_ECC_SOFT;
819 chip->ecc.algo = NAND_ECC_HAMMING;
820 }
821
822 /* scan hardware nand chip and setup mtd info data struct */
823 if (bf5xx_nand_scan(mtd)) {
824 err = -ENXIO;
825 goto out_err_nand_scan;
826 }
827
828#ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
829 chip->badblockpos = 63;
830#endif
831
832 /* add NAND partition */
833 bf5xx_nand_add_partition(info);
834
835 dev_dbg(&pdev->dev, "initialised ok\n");
836 return 0;
837
838out_err_nand_scan:
839 bf5xx_nand_dma_remove(info);
840out_err:
841 peripheral_free_list(bfin_nfc_pin_req);
842
843 return err;
844}
845
846/* driver device registration */
847static struct platform_driver bf5xx_nand_driver = {
848 .probe = bf5xx_nand_probe,
849 .remove = bf5xx_nand_remove,
850 .driver = {
851 .name = DRV_NAME,
852 },
853};
854
855module_platform_driver(bf5xx_nand_driver);
856
857MODULE_LICENSE("GPL");
858MODULE_AUTHOR(DRV_AUTHOR);
859MODULE_DESCRIPTION(DRV_DESC);
860MODULE_ALIAS("platform:" DRV_NAME);
Linux kernel - Deliverables
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