projects / deliverable / linux.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
ipg.c: remove id [SUNDANCE, 0x1021]
[deliverable/linux.git] / drivers / net / 3c59x.c
... / ...
CommitLineData
1/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2/*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20*/
21
22/*
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
25 *
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
29 */
30
31
32#define DRV_NAME "3c59x"
33
34
35
36/* A few values that may be tweaked. */
37/* Keep the ring sizes a power of two for efficiency. */
38#define TX_RING_SIZE 16
39#define RX_RING_SIZE 32
40#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
41
42/* "Knobs" that adjust features and parameters. */
43/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
45#ifndef __arm__
46static int rx_copybreak = 200;
47#else
48/* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50static int rx_copybreak = 1513;
51#endif
52/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53static const int mtu = 1500;
54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55static int max_interrupt_work = 32;
56/* Tx timeout interval (millisecs) */
57static int watchdog = 5000;
58
59/* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
62 */
63#define tx_interrupt_mitigation 1
64
65/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66#define vortex_debug debug
67#ifdef VORTEX_DEBUG
68static int vortex_debug = VORTEX_DEBUG;
69#else
70static int vortex_debug = 1;
71#endif
72
73#include <linux/module.h>
74#include <linux/kernel.h>
75#include <linux/string.h>
76#include <linux/timer.h>
77#include <linux/errno.h>
78#include <linux/in.h>
79#include <linux/ioport.h>
80#include <linux/interrupt.h>
81#include <linux/pci.h>
82#include <linux/mii.h>
83#include <linux/init.h>
84#include <linux/netdevice.h>
85#include <linux/etherdevice.h>
86#include <linux/skbuff.h>
87#include <linux/ethtool.h>
88#include <linux/highmem.h>
89#include <linux/eisa.h>
90#include <linux/bitops.h>
91#include <linux/jiffies.h>
92#include <linux/gfp.h>
93#include <asm/irq.h> /* For nr_irqs only. */
94#include <asm/io.h>
95#include <asm/uaccess.h>
96
97/* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
99
100#define RUN_AT(x) (jiffies + (x))
101
102#include <linux/delay.h>
103
104
105static const char version[] __devinitconst =
106 DRV_NAME ": Donald Becker and others.\n";
107
108MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
109MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
110MODULE_LICENSE("GPL");
111
112
113/* Operational parameter that usually are not changed. */
114
115/* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119#define VORTEX_TOTAL_SIZE 0x20
120#define BOOMERANG_TOTAL_SIZE 0x40
121
122/* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125static char mii_preamble_required;
126
127#define PFX DRV_NAME ": "
128
129
130
131/*
132 Theory of Operation
133
134I. Board Compatibility
135
136This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
140
141The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
144
145II. Board-specific settings
146
147PCI bus devices are configured by the system at boot time, so no jumpers
148need to be set on the board. The system BIOS should be set to assign the
149PCI INTA signal to an otherwise unused system IRQ line.
150
151The EEPROM settings for media type and forced-full-duplex are observed.
152The EEPROM media type should be left at the default "autoselect" unless using
15310base2 or AUI connections which cannot be reliably detected.
154
155III. Driver operation
156
157The 3c59x series use an interface that's very similar to the previous 3c5x9
158series. The primary interface is two programmed-I/O FIFOs, with an
159alternate single-contiguous-region bus-master transfer (see next).
160
161The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164programmed-I/O interface that has been removed in 'B' and subsequent board
165revisions.
166
167One extension that is advertised in a very large font is that the adapters
168are capable of being bus masters. On the Vortex chip this capability was
169only for a single contiguous region making it far less useful than the full
170bus master capability. There is a significant performance impact of taking
171an extra interrupt or polling for the completion of each transfer, as well
172as difficulty sharing the single transfer engine between the transmit and
173receive threads. Using DMA transfers is a win only with large blocks or
174with the flawed versions of the Intel Orion motherboard PCI controller.
175
176The Boomerang chip's full-bus-master interface is useful, and has the
177currently-unused advantages over other similar chips that queued transmit
178packets may be reordered and receive buffer groups are associated with a
179single frame.
180
181With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182Rather than a fixed intermediate receive buffer, this scheme allocates
183full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184the copying breakpoint: it is chosen to trade-off the memory wasted by
185passing the full-sized skbuff to the queue layer for all frames vs. the
186copying cost of copying a frame to a correctly-sized skbuff.
187
188IIIC. Synchronization
189The driver runs as two independent, single-threaded flows of control. One
190is the send-packet routine, which enforces single-threaded use by the
191dev->tbusy flag. The other thread is the interrupt handler, which is single
192threaded by the hardware and other software.
193
194IV. Notes
195
196Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
1973c590, 3c595, and 3c900 boards.
198The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199the EISA version is called "Demon". According to Terry these names come
200from rides at the local amusement park.
201
202The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203This driver only supports ethernet packets because of the skbuff allocation
204limit of 4K.
205*/
206
207/* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
209*/
210enum pci_flags_bit {
211 PCI_USES_MASTER=4,
212};
213
214enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
220
221enum vortex_chips {
222 CH_3C590 = 0,
223 CH_3C592,
224 CH_3C597,
225 CH_3C595_1,
226 CH_3C595_2,
227
228 CH_3C595_3,
229 CH_3C900_1,
230 CH_3C900_2,
231 CH_3C900_3,
232 CH_3C900_4,
233
234 CH_3C900_5,
235 CH_3C900B_FL,
236 CH_3C905_1,
237 CH_3C905_2,
238 CH_3C905B_TX,
239 CH_3C905B_1,
240
241 CH_3C905B_2,
242 CH_3C905B_FX,
243 CH_3C905C,
244 CH_3C9202,
245 CH_3C980,
246 CH_3C9805,
247
248 CH_3CSOHO100_TX,
249 CH_3C555,
250 CH_3C556,
251 CH_3C556B,
252 CH_3C575,
253
254 CH_3C575_1,
255 CH_3CCFE575,
256 CH_3CCFE575CT,
257 CH_3CCFE656,
258 CH_3CCFEM656,
259
260 CH_3CCFEM656_1,
261 CH_3C450,
262 CH_3C920,
263 CH_3C982A,
264 CH_3C982B,
265
266 CH_905BT4,
267 CH_920B_EMB_WNM,
268};
269
270
271/* note: this array directly indexed by above enums, and MUST
272 * be kept in sync with both the enums above, and the PCI device
273 * table below
274 */
275static struct vortex_chip_info {
276 const char *name;
277 int flags;
278 int drv_flags;
279 int io_size;
280} vortex_info_tbl[] __devinitdata = {
281 {"3c590 Vortex 10Mbps",
282 PCI_USES_MASTER, IS_VORTEX, 32, },
283 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
284 PCI_USES_MASTER, IS_VORTEX, 32, },
285 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
286 PCI_USES_MASTER, IS_VORTEX, 32, },
287 {"3c595 Vortex 100baseTx",
288 PCI_USES_MASTER, IS_VORTEX, 32, },
289 {"3c595 Vortex 100baseT4",
290 PCI_USES_MASTER, IS_VORTEX, 32, },
291
292 {"3c595 Vortex 100base-MII",
293 PCI_USES_MASTER, IS_VORTEX, 32, },
294 {"3c900 Boomerang 10baseT",
295 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
296 {"3c900 Boomerang 10Mbps Combo",
297 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
298 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
299 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
300 {"3c900 Cyclone 10Mbps Combo",
301 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
302
303 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
304 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
305 {"3c900B-FL Cyclone 10base-FL",
306 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
307 {"3c905 Boomerang 100baseTx",
308 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
309 {"3c905 Boomerang 100baseT4",
310 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
311 {"3C905B-TX Fast Etherlink XL PCI",
312 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
313 {"3c905B Cyclone 100baseTx",
314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
315
316 {"3c905B Cyclone 10/100/BNC",
317 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
318 {"3c905B-FX Cyclone 100baseFx",
319 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
320 {"3c905C Tornado",
321 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
322 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
323 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
324 {"3c980 Cyclone",
325 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
326
327 {"3c980C Python-T",
328 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
329 {"3cSOHO100-TX Hurricane",
330 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
331 {"3c555 Laptop Hurricane",
332 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
333 {"3c556 Laptop Tornado",
334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
335 HAS_HWCKSM, 128, },
336 {"3c556B Laptop Hurricane",
337 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
338 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
339
340 {"3c575 [Megahertz] 10/100 LAN CardBus",
341 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
342 {"3c575 Boomerang CardBus",
343 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
344 {"3CCFE575BT Cyclone CardBus",
345 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
346 INVERT_LED_PWR|HAS_HWCKSM, 128, },
347 {"3CCFE575CT Tornado CardBus",
348 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
349 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
350 {"3CCFE656 Cyclone CardBus",
351 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
352 INVERT_LED_PWR|HAS_HWCKSM, 128, },
353
354 {"3CCFEM656B Cyclone+Winmodem CardBus",
355 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
356 INVERT_LED_PWR|HAS_HWCKSM, 128, },
357 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
359 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
360 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
361 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
362 {"3c920 Tornado",
363 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
364 {"3c982 Hydra Dual Port A",
365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
366
367 {"3c982 Hydra Dual Port B",
368 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
369 {"3c905B-T4",
370 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
371 {"3c920B-EMB-WNM Tornado",
372 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
373
374 {NULL,}, /* NULL terminated list. */
375};
376
377
378static DEFINE_PCI_DEVICE_TABLE(vortex_pci_tbl) = {
379 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
380 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
381 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
382 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
383 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
384
385 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
386 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
387 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
388 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
389 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
390
391 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
392 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
393 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
394 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
395 { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX },
396 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
397
398 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
399 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
400 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
401 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
402 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
403 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
404
405 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
406 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
407 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
408 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
409 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
410
411 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
412 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
413 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
414 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
415 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
416
417 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
418 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
419 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
420 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
421 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
422
423 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
424 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
425
426 {0,} /* 0 terminated list. */
427};
428MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
429
430
431/* Operational definitions.
432 These are not used by other compilation units and thus are not
433 exported in a ".h" file.
434
435 First the windows. There are eight register windows, with the command
436 and status registers available in each.
437 */
438#define EL3_CMD 0x0e
439#define EL3_STATUS 0x0e
440
441/* The top five bits written to EL3_CMD are a command, the lower
442 11 bits are the parameter, if applicable.
443 Note that 11 parameters bits was fine for ethernet, but the new chip
444 can handle FDDI length frames (~4500 octets) and now parameters count
445 32-bit 'Dwords' rather than octets. */
446
447enum vortex_cmd {
448 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
449 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
450 UpStall = 6<<11, UpUnstall = (6<<11)+1,
451 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
452 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
453 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
454 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
455 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
456 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
457 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
458
459/* The SetRxFilter command accepts the following classes: */
460enum RxFilter {
461 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
462
463/* Bits in the general status register. */
464enum vortex_status {
465 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
466 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
467 IntReq = 0x0040, StatsFull = 0x0080,
468 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
469 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
470 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
471};
472
473/* Register window 1 offsets, the window used in normal operation.
474 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
475enum Window1 {
476 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
477 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
478 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
479};
480enum Window0 {
481 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
482 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
483 IntrStatus=0x0E, /* Valid in all windows. */
484};
485enum Win0_EEPROM_bits {
486 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
487 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
488 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
489};
490/* EEPROM locations. */
491enum eeprom_offset {
492 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
493 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
494 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
495 DriverTune=13, Checksum=15};
496
497enum Window2 { /* Window 2. */
498 Wn2_ResetOptions=12,
499};
500enum Window3 { /* Window 3: MAC/config bits. */
501 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
502};
503
504#define BFEXT(value, offset, bitcount) \
505 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
506
507#define BFINS(lhs, rhs, offset, bitcount) \
508 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
509 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
510
511#define RAM_SIZE(v) BFEXT(v, 0, 3)
512#define RAM_WIDTH(v) BFEXT(v, 3, 1)
513#define RAM_SPEED(v) BFEXT(v, 4, 2)
514#define ROM_SIZE(v) BFEXT(v, 6, 2)
515#define RAM_SPLIT(v) BFEXT(v, 16, 2)
516#define XCVR(v) BFEXT(v, 20, 4)
517#define AUTOSELECT(v) BFEXT(v, 24, 1)
518
519enum Window4 { /* Window 4: Xcvr/media bits. */
520 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
521};
522enum Win4_Media_bits {
523 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
524 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
525 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
526 Media_LnkBeat = 0x0800,
527};
528enum Window7 { /* Window 7: Bus Master control. */
529 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
530 Wn7_MasterStatus = 12,
531};
532/* Boomerang bus master control registers. */
533enum MasterCtrl {
534 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
535 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
536};
537
538/* The Rx and Tx descriptor lists.
539 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
540 alignment contraint on tx_ring[] and rx_ring[]. */
541#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
542#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
543struct boom_rx_desc {
544 __le32 next; /* Last entry points to 0. */
545 __le32 status;
546 __le32 addr; /* Up to 63 addr/len pairs possible. */
547 __le32 length; /* Set LAST_FRAG to indicate last pair. */
548};
549/* Values for the Rx status entry. */
550enum rx_desc_status {
551 RxDComplete=0x00008000, RxDError=0x4000,
552 /* See boomerang_rx() for actual error bits */
553 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
554 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
555};
556
557#ifdef MAX_SKB_FRAGS
558#define DO_ZEROCOPY 1
559#else
560#define DO_ZEROCOPY 0
561#endif
562
563struct boom_tx_desc {
564 __le32 next; /* Last entry points to 0. */
565 __le32 status; /* bits 0:12 length, others see below. */
566#if DO_ZEROCOPY
567 struct {
568 __le32 addr;
569 __le32 length;
570 } frag[1+MAX_SKB_FRAGS];
571#else
572 __le32 addr;
573 __le32 length;
574#endif
575};
576
577/* Values for the Tx status entry. */
578enum tx_desc_status {
579 CRCDisable=0x2000, TxDComplete=0x8000,
580 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
581 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
582};
583
584/* Chip features we care about in vp->capabilities, read from the EEPROM. */
585enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
586
587struct vortex_extra_stats {
588 unsigned long tx_deferred;
589 unsigned long tx_max_collisions;
590 unsigned long tx_multiple_collisions;
591 unsigned long tx_single_collisions;
592 unsigned long rx_bad_ssd;
593};
594
595struct vortex_private {
596 /* The Rx and Tx rings should be quad-word-aligned. */
597 struct boom_rx_desc* rx_ring;
598 struct boom_tx_desc* tx_ring;
599 dma_addr_t rx_ring_dma;
600 dma_addr_t tx_ring_dma;
601 /* The addresses of transmit- and receive-in-place skbuffs. */
602 struct sk_buff* rx_skbuff[RX_RING_SIZE];
603 struct sk_buff* tx_skbuff[TX_RING_SIZE];
604 unsigned int cur_rx, cur_tx; /* The next free ring entry */
605 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
606 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
607 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
608 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
609
610 /* PCI configuration space information. */
611 struct device *gendev;
612 void __iomem *ioaddr; /* IO address space */
613 void __iomem *cb_fn_base; /* CardBus function status addr space. */
614
615 /* Some values here only for performance evaluation and path-coverage */
616 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
617 int card_idx;
618
619 /* The remainder are related to chip state, mostly media selection. */
620 struct timer_list timer; /* Media selection timer. */
621 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
622 int options; /* User-settable misc. driver options. */
623 unsigned int media_override:4, /* Passed-in media type. */
624 default_media:4, /* Read from the EEPROM/Wn3_Config. */
625 full_duplex:1, autoselect:1,
626 bus_master:1, /* Vortex can only do a fragment bus-m. */
627 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
628 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
629 partner_flow_ctrl:1, /* Partner supports flow control */
630 has_nway:1,
631 enable_wol:1, /* Wake-on-LAN is enabled */
632 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
633 open:1,
634 medialock:1,
635 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
636 large_frames:1, /* accept large frames */
637 handling_irq:1; /* private in_irq indicator */
638 /* {get|set}_wol operations are already serialized by rtnl.
639 * no additional locking is required for the enable_wol and acpi_set_WOL()
640 */
641 int drv_flags;
642 u16 status_enable;
643 u16 intr_enable;
644 u16 available_media; /* From Wn3_Options. */
645 u16 capabilities, info1, info2; /* Various, from EEPROM. */
646 u16 advertising; /* NWay media advertisement */
647 unsigned char phys[2]; /* MII device addresses. */
648 u16 deferred; /* Resend these interrupts when we
649 * bale from the ISR */
650 u16 io_size; /* Size of PCI region (for release_region) */
651
652 /* Serialises access to hardware other than MII and variables below.
653 * The lock hierarchy is rtnl_lock > {lock, mii_lock} > window_lock. */
654 spinlock_t lock;
655
656 spinlock_t mii_lock; /* Serialises access to MII */
657 struct mii_if_info mii; /* MII lib hooks/info */
658 spinlock_t window_lock; /* Serialises access to windowed regs */
659 int window; /* Register window */
660};
661
662static void window_set(struct vortex_private *vp, int window)
663{
664 if (window != vp->window) {
665 iowrite16(SelectWindow + window, vp->ioaddr + EL3_CMD);
666 vp->window = window;
667 }
668}
669
670#define DEFINE_WINDOW_IO(size) \
671static u ## size \
672window_read ## size(struct vortex_private *vp, int window, int addr) \
673{ \
674 unsigned long flags; \
675 u ## size ret; \
676 spin_lock_irqsave(&vp->window_lock, flags); \
677 window_set(vp, window); \
678 ret = ioread ## size(vp->ioaddr + addr); \
679 spin_unlock_irqrestore(&vp->window_lock, flags); \
680 return ret; \
681} \
682static void \
683window_write ## size(struct vortex_private *vp, u ## size value, \
684 int window, int addr) \
685{ \
686 unsigned long flags; \
687 spin_lock_irqsave(&vp->window_lock, flags); \
688 window_set(vp, window); \
689 iowrite ## size(value, vp->ioaddr + addr); \
690 spin_unlock_irqrestore(&vp->window_lock, flags); \
691}
692DEFINE_WINDOW_IO(8)
693DEFINE_WINDOW_IO(16)
694DEFINE_WINDOW_IO(32)
695
696#ifdef CONFIG_PCI
697#define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
698#else
699#define DEVICE_PCI(dev) NULL
700#endif
701
702#define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
703
704#ifdef CONFIG_EISA
705#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
706#else
707#define DEVICE_EISA(dev) NULL
708#endif
709
710#define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
711
712/* The action to take with a media selection timer tick.
713 Note that we deviate from the 3Com order by checking 10base2 before AUI.
714 */
715enum xcvr_types {
716 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
717 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
718};
719
720static const struct media_table {
721 char *name;
722 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
723 mask:8, /* The transceiver-present bit in Wn3_Config.*/
724 next:8; /* The media type to try next. */
725 int wait; /* Time before we check media status. */
726} media_tbl[] = {
727 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
728 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
729 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
730 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
731 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
732 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
733 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
734 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
735 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
736 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
737 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
738};
739
740static struct {
741 const char str[ETH_GSTRING_LEN];
742} ethtool_stats_keys[] = {
743 { "tx_deferred" },
744 { "tx_max_collisions" },
745 { "tx_multiple_collisions" },
746 { "tx_single_collisions" },
747 { "rx_bad_ssd" },
748};
749
750/* number of ETHTOOL_GSTATS u64's */
751#define VORTEX_NUM_STATS 5
752
753static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
754 int chip_idx, int card_idx);
755static int vortex_up(struct net_device *dev);
756static void vortex_down(struct net_device *dev, int final);
757static int vortex_open(struct net_device *dev);
758static void mdio_sync(struct vortex_private *vp, int bits);
759static int mdio_read(struct net_device *dev, int phy_id, int location);
760static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
761static void vortex_timer(unsigned long arg);
762static void rx_oom_timer(unsigned long arg);
763static netdev_tx_t vortex_start_xmit(struct sk_buff *skb,
764 struct net_device *dev);
765static netdev_tx_t boomerang_start_xmit(struct sk_buff *skb,
766 struct net_device *dev);
767static int vortex_rx(struct net_device *dev);
768static int boomerang_rx(struct net_device *dev);
769static irqreturn_t vortex_interrupt(int irq, void *dev_id);
770static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
771static int vortex_close(struct net_device *dev);
772static void dump_tx_ring(struct net_device *dev);
773static void update_stats(void __iomem *ioaddr, struct net_device *dev);
774static struct net_device_stats *vortex_get_stats(struct net_device *dev);
775static void set_rx_mode(struct net_device *dev);
776#ifdef CONFIG_PCI
777static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
778#endif
779static void vortex_tx_timeout(struct net_device *dev);
780static void acpi_set_WOL(struct net_device *dev);
781static const struct ethtool_ops vortex_ethtool_ops;
782static void set_8021q_mode(struct net_device *dev, int enable);
783
784/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
785/* Option count limit only -- unlimited interfaces are supported. */
786#define MAX_UNITS 8
787static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
788static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
789static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
790static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
791static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
792static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
793static int global_options = -1;
794static int global_full_duplex = -1;
795static int global_enable_wol = -1;
796static int global_use_mmio = -1;
797
798/* Variables to work-around the Compaq PCI BIOS32 problem. */
799static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
800static struct net_device *compaq_net_device;
801
802static int vortex_cards_found;
803
804module_param(debug, int, 0);
805module_param(global_options, int, 0);
806module_param_array(options, int, NULL, 0);
807module_param(global_full_duplex, int, 0);
808module_param_array(full_duplex, int, NULL, 0);
809module_param_array(hw_checksums, int, NULL, 0);
810module_param_array(flow_ctrl, int, NULL, 0);
811module_param(global_enable_wol, int, 0);
812module_param_array(enable_wol, int, NULL, 0);
813module_param(rx_copybreak, int, 0);
814module_param(max_interrupt_work, int, 0);
815module_param(compaq_ioaddr, int, 0);
816module_param(compaq_irq, int, 0);
817module_param(compaq_device_id, int, 0);
818module_param(watchdog, int, 0);
819module_param(global_use_mmio, int, 0);
820module_param_array(use_mmio, int, NULL, 0);
821MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
822MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
823MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
824MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
825MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
826MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
827MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
828MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
829MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
830MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
831MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
832MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
833MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
834MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
835MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
836MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
837MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
838
839#ifdef CONFIG_NET_POLL_CONTROLLER
840static void poll_vortex(struct net_device *dev)
841{
842 struct vortex_private *vp = netdev_priv(dev);
843 unsigned long flags;
844 local_irq_save(flags);
845 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
846 local_irq_restore(flags);
847}
848#endif
849
850#ifdef CONFIG_PM
851
852static int vortex_suspend(struct device *dev)
853{
854 struct pci_dev *pdev = to_pci_dev(dev);
855 struct net_device *ndev = pci_get_drvdata(pdev);
856
857 if (!ndev || !netif_running(ndev))
858 return 0;
859
860 netif_device_detach(ndev);
861 vortex_down(ndev, 1);
862
863 return 0;
864}
865
866static int vortex_resume(struct device *dev)
867{
868 struct pci_dev *pdev = to_pci_dev(dev);
869 struct net_device *ndev = pci_get_drvdata(pdev);
870 int err;
871
872 if (!ndev || !netif_running(ndev))
873 return 0;
874
875 err = vortex_up(ndev);
876 if (err)
877 return err;
878
879 netif_device_attach(ndev);
880
881 return 0;
882}
883
884static const struct dev_pm_ops vortex_pm_ops = {
885 .suspend = vortex_suspend,
886 .resume = vortex_resume,
887 .freeze = vortex_suspend,
888 .thaw = vortex_resume,
889 .poweroff = vortex_suspend,
890 .restore = vortex_resume,
891};
892
893#define VORTEX_PM_OPS (&vortex_pm_ops)
894
895#else /* !CONFIG_PM */
896
897#define VORTEX_PM_OPS NULL
898
899#endif /* !CONFIG_PM */
900
901#ifdef CONFIG_EISA
902static struct eisa_device_id vortex_eisa_ids[] = {
903 { "TCM5920", CH_3C592 },
904 { "TCM5970", CH_3C597 },
905 { "" }
906};
907MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
908
909static int __init vortex_eisa_probe(struct device *device)
910{
911 void __iomem *ioaddr;
912 struct eisa_device *edev;
913
914 edev = to_eisa_device(device);
915
916 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
917 return -EBUSY;
918
919 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
920
921 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
922 edev->id.driver_data, vortex_cards_found)) {
923 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
924 return -ENODEV;
925 }
926
927 vortex_cards_found++;
928
929 return 0;
930}
931
932static int __devexit vortex_eisa_remove(struct device *device)
933{
934 struct eisa_device *edev;
935 struct net_device *dev;
936 struct vortex_private *vp;
937 void __iomem *ioaddr;
938
939 edev = to_eisa_device(device);
940 dev = eisa_get_drvdata(edev);
941
942 if (!dev) {
943 pr_err("vortex_eisa_remove called for Compaq device!\n");
944 BUG();
945 }
946
947 vp = netdev_priv(dev);
948 ioaddr = vp->ioaddr;
949
950 unregister_netdev(dev);
951 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
952 release_region(dev->base_addr, VORTEX_TOTAL_SIZE);
953
954 free_netdev(dev);
955 return 0;
956}
957
958static struct eisa_driver vortex_eisa_driver = {
959 .id_table = vortex_eisa_ids,
960 .driver = {
961 .name = "3c59x",
962 .probe = vortex_eisa_probe,
963 .remove = __devexit_p(vortex_eisa_remove)
964 }
965};
966
967#endif /* CONFIG_EISA */
968
969/* returns count found (>= 0), or negative on error */
970static int __init vortex_eisa_init(void)
971{
972 int eisa_found = 0;
973 int orig_cards_found = vortex_cards_found;
974
975#ifdef CONFIG_EISA
976 int err;
977
978 err = eisa_driver_register (&vortex_eisa_driver);
979 if (!err) {
980 /*
981 * Because of the way EISA bus is probed, we cannot assume
982 * any device have been found when we exit from
983 * eisa_driver_register (the bus root driver may not be
984 * initialized yet). So we blindly assume something was
985 * found, and let the sysfs magic happend...
986 */
987 eisa_found = 1;
988 }
989#endif
990
991 /* Special code to work-around the Compaq PCI BIOS32 problem. */
992 if (compaq_ioaddr) {
993 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
994 compaq_irq, compaq_device_id, vortex_cards_found++);
995 }
996
997 return vortex_cards_found - orig_cards_found + eisa_found;
998}
999
1000/* returns count (>= 0), or negative on error */
1001static int __devinit vortex_init_one(struct pci_dev *pdev,
1002 const struct pci_device_id *ent)
1003{
1004 int rc, unit, pci_bar;
1005 struct vortex_chip_info *vci;
1006 void __iomem *ioaddr;
1007
1008 /* wake up and enable device */
1009 rc = pci_enable_device(pdev);
1010 if (rc < 0)
1011 goto out;
1012
1013 unit = vortex_cards_found;
1014
1015 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
1016 /* Determine the default if the user didn't override us */
1017 vci = &vortex_info_tbl[ent->driver_data];
1018 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
1019 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
1020 pci_bar = use_mmio[unit] ? 1 : 0;
1021 else
1022 pci_bar = global_use_mmio ? 1 : 0;
1023
1024 ioaddr = pci_iomap(pdev, pci_bar, 0);
1025 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
1026 ioaddr = pci_iomap(pdev, 0, 0);
1027 if (!ioaddr) {
1028 pci_disable_device(pdev);
1029 rc = -ENOMEM;
1030 goto out;
1031 }
1032
1033 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
1034 ent->driver_data, unit);
1035 if (rc < 0) {
1036 pci_iounmap(pdev, ioaddr);
1037 pci_disable_device(pdev);
1038 goto out;
1039 }
1040
1041 vortex_cards_found++;
1042
1043out:
1044 return rc;
1045}
1046
1047static const struct net_device_ops boomrang_netdev_ops = {
1048 .ndo_open = vortex_open,
1049 .ndo_stop = vortex_close,
1050 .ndo_start_xmit = boomerang_start_xmit,
1051 .ndo_tx_timeout = vortex_tx_timeout,
1052 .ndo_get_stats = vortex_get_stats,
1053#ifdef CONFIG_PCI
1054 .ndo_do_ioctl = vortex_ioctl,
1055#endif
1056 .ndo_set_multicast_list = set_rx_mode,
1057 .ndo_change_mtu = eth_change_mtu,
1058 .ndo_set_mac_address = eth_mac_addr,
1059 .ndo_validate_addr = eth_validate_addr,
1060#ifdef CONFIG_NET_POLL_CONTROLLER
1061 .ndo_poll_controller = poll_vortex,
1062#endif
1063};
1064
1065static const struct net_device_ops vortex_netdev_ops = {
1066 .ndo_open = vortex_open,
1067 .ndo_stop = vortex_close,
1068 .ndo_start_xmit = vortex_start_xmit,
1069 .ndo_tx_timeout = vortex_tx_timeout,
1070 .ndo_get_stats = vortex_get_stats,
1071#ifdef CONFIG_PCI
1072 .ndo_do_ioctl = vortex_ioctl,
1073#endif
1074 .ndo_set_multicast_list = set_rx_mode,
1075 .ndo_change_mtu = eth_change_mtu,
1076 .ndo_set_mac_address = eth_mac_addr,
1077 .ndo_validate_addr = eth_validate_addr,
1078#ifdef CONFIG_NET_POLL_CONTROLLER
1079 .ndo_poll_controller = poll_vortex,
1080#endif
1081};
1082
1083/*
1084 * Start up the PCI/EISA device which is described by *gendev.
1085 * Return 0 on success.
1086 *
1087 * NOTE: pdev can be NULL, for the case of a Compaq device
1088 */
1089static int __devinit vortex_probe1(struct device *gendev,
1090 void __iomem *ioaddr, int irq,
1091 int chip_idx, int card_idx)
1092{
1093 struct vortex_private *vp;
1094 int option;
1095 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1096 int i, step;
1097 struct net_device *dev;
1098 static int printed_version;
1099 int retval, print_info;
1100 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1101 const char *print_name = "3c59x";
1102 struct pci_dev *pdev = NULL;
1103 struct eisa_device *edev = NULL;
1104
1105 if (!printed_version) {
1106 pr_info("%s", version);
1107 printed_version = 1;
1108 }
1109
1110 if (gendev) {
1111 if ((pdev = DEVICE_PCI(gendev))) {
1112 print_name = pci_name(pdev);
1113 }
1114
1115 if ((edev = DEVICE_EISA(gendev))) {
1116 print_name = dev_name(&edev->dev);
1117 }
1118 }
1119
1120 dev = alloc_etherdev(sizeof(*vp));
1121 retval = -ENOMEM;
1122 if (!dev) {
1123 pr_err(PFX "unable to allocate etherdev, aborting\n");
1124 goto out;
1125 }
1126 SET_NETDEV_DEV(dev, gendev);
1127 vp = netdev_priv(dev);
1128
1129 option = global_options;
1130
1131 /* The lower four bits are the media type. */
1132 if (dev->mem_start) {
1133 /*
1134 * The 'options' param is passed in as the third arg to the
1135 * LILO 'ether=' argument for non-modular use
1136 */
1137 option = dev->mem_start;
1138 }
1139 else if (card_idx < MAX_UNITS) {
1140 if (options[card_idx] >= 0)
1141 option = options[card_idx];
1142 }
1143
1144 if (option > 0) {
1145 if (option & 0x8000)
1146 vortex_debug = 7;
1147 if (option & 0x4000)
1148 vortex_debug = 2;
1149 if (option & 0x0400)
1150 vp->enable_wol = 1;
1151 }
1152
1153 print_info = (vortex_debug > 1);
1154 if (print_info)
1155 pr_info("See Documentation/networking/vortex.txt\n");
1156
1157 pr_info("%s: 3Com %s %s at %p.\n",
1158 print_name,
1159 pdev ? "PCI" : "EISA",
1160 vci->name,
1161 ioaddr);
1162
1163 dev->base_addr = (unsigned long)ioaddr;
1164 dev->irq = irq;
1165 dev->mtu = mtu;
1166 vp->ioaddr = ioaddr;
1167 vp->large_frames = mtu > 1500;
1168 vp->drv_flags = vci->drv_flags;
1169 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1170 vp->io_size = vci->io_size;
1171 vp->card_idx = card_idx;
1172 vp->window = -1;
1173
1174 /* module list only for Compaq device */
1175 if (gendev == NULL) {
1176 compaq_net_device = dev;
1177 }
1178
1179 /* PCI-only startup logic */
1180 if (pdev) {
1181 /* EISA resources already marked, so only PCI needs to do this here */
1182 /* Ignore return value, because Cardbus drivers already allocate for us */
1183 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1184 vp->must_free_region = 1;
1185
1186 /* enable bus-mastering if necessary */
1187 if (vci->flags & PCI_USES_MASTER)
1188 pci_set_master(pdev);
1189
1190 if (vci->drv_flags & IS_VORTEX) {
1191 u8 pci_latency;
1192 u8 new_latency = 248;
1193
1194 /* Check the PCI latency value. On the 3c590 series the latency timer
1195 must be set to the maximum value to avoid data corruption that occurs
1196 when the timer expires during a transfer. This bug exists the Vortex
1197 chip only. */
1198 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1199 if (pci_latency < new_latency) {
1200 pr_info("%s: Overriding PCI latency timer (CFLT) setting of %d, new value is %d.\n",
1201 print_name, pci_latency, new_latency);
1202 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1203 }
1204 }
1205 }
1206
1207 spin_lock_init(&vp->lock);
1208 spin_lock_init(&vp->mii_lock);
1209 spin_lock_init(&vp->window_lock);
1210 vp->gendev = gendev;
1211 vp->mii.dev = dev;
1212 vp->mii.mdio_read = mdio_read;
1213 vp->mii.mdio_write = mdio_write;
1214 vp->mii.phy_id_mask = 0x1f;
1215 vp->mii.reg_num_mask = 0x1f;
1216
1217 /* Makes sure rings are at least 16 byte aligned. */
1218 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1219 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1220 &vp->rx_ring_dma);
1221 retval = -ENOMEM;
1222 if (!vp->rx_ring)
1223 goto free_region;
1224
1225 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1226 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1227
1228 /* if we are a PCI driver, we store info in pdev->driver_data
1229 * instead of a module list */
1230 if (pdev)
1231 pci_set_drvdata(pdev, dev);
1232 if (edev)
1233 eisa_set_drvdata(edev, dev);
1234
1235 vp->media_override = 7;
1236 if (option >= 0) {
1237 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1238 if (vp->media_override != 7)
1239 vp->medialock = 1;
1240 vp->full_duplex = (option & 0x200) ? 1 : 0;
1241 vp->bus_master = (option & 16) ? 1 : 0;
1242 }
1243
1244 if (global_full_duplex > 0)
1245 vp->full_duplex = 1;
1246 if (global_enable_wol > 0)
1247 vp->enable_wol = 1;
1248
1249 if (card_idx < MAX_UNITS) {
1250 if (full_duplex[card_idx] > 0)
1251 vp->full_duplex = 1;
1252 if (flow_ctrl[card_idx] > 0)
1253 vp->flow_ctrl = 1;
1254 if (enable_wol[card_idx] > 0)
1255 vp->enable_wol = 1;
1256 }
1257
1258 vp->mii.force_media = vp->full_duplex;
1259 vp->options = option;
1260 /* Read the station address from the EEPROM. */
1261 {
1262 int base;
1263
1264 if (vci->drv_flags & EEPROM_8BIT)
1265 base = 0x230;
1266 else if (vci->drv_flags & EEPROM_OFFSET)
1267 base = EEPROM_Read + 0x30;
1268 else
1269 base = EEPROM_Read;
1270
1271 for (i = 0; i < 0x40; i++) {
1272 int timer;
1273 window_write16(vp, base + i, 0, Wn0EepromCmd);
1274 /* Pause for at least 162 us. for the read to take place. */
1275 for (timer = 10; timer >= 0; timer--) {
1276 udelay(162);
1277 if ((window_read16(vp, 0, Wn0EepromCmd) &
1278 0x8000) == 0)
1279 break;
1280 }
1281 eeprom[i] = window_read16(vp, 0, Wn0EepromData);
1282 }
1283 }
1284 for (i = 0; i < 0x18; i++)
1285 checksum ^= eeprom[i];
1286 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1287 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1288 while (i < 0x21)
1289 checksum ^= eeprom[i++];
1290 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1291 }
1292 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1293 pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1294 for (i = 0; i < 3; i++)
1295 ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
1296 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1297 if (print_info)
1298 pr_cont(" %pM", dev->dev_addr);
1299 /* Unfortunately an all zero eeprom passes the checksum and this
1300 gets found in the wild in failure cases. Crypto is hard 8) */
1301 if (!is_valid_ether_addr(dev->dev_addr)) {
1302 retval = -EINVAL;
1303 pr_err("*** EEPROM MAC address is invalid.\n");
1304 goto free_ring; /* With every pack */
1305 }
1306 for (i = 0; i < 6; i++)
1307 window_write8(vp, dev->dev_addr[i], 2, i);
1308
1309 if (print_info)
1310 pr_cont(", IRQ %d\n", dev->irq);
1311 /* Tell them about an invalid IRQ. */
1312 if (dev->irq <= 0 || dev->irq >= nr_irqs)
1313 pr_warning(" *** Warning: IRQ %d is unlikely to work! ***\n",
1314 dev->irq);
1315
1316 step = (window_read8(vp, 4, Wn4_NetDiag) & 0x1e) >> 1;
1317 if (print_info) {
1318 pr_info(" product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n",
1319 eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1320 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1321 }
1322
1323
1324 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1325 unsigned short n;
1326
1327 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1328 if (!vp->cb_fn_base) {
1329 retval = -ENOMEM;
1330 goto free_ring;
1331 }
1332
1333 if (print_info) {
1334 pr_info("%s: CardBus functions mapped %16.16llx->%p\n",
1335 print_name,
1336 (unsigned long long)pci_resource_start(pdev, 2),
1337 vp->cb_fn_base);
1338 }
1339
1340 n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1341 if (vp->drv_flags & INVERT_LED_PWR)
1342 n |= 0x10;
1343 if (vp->drv_flags & INVERT_MII_PWR)
1344 n |= 0x4000;
1345 window_write16(vp, n, 2, Wn2_ResetOptions);
1346 if (vp->drv_flags & WNO_XCVR_PWR) {
1347 window_write16(vp, 0x0800, 0, 0);
1348 }
1349 }
1350
1351 /* Extract our information from the EEPROM data. */
1352 vp->info1 = eeprom[13];
1353 vp->info2 = eeprom[15];
1354 vp->capabilities = eeprom[16];
1355
1356 if (vp->info1 & 0x8000) {
1357 vp->full_duplex = 1;
1358 if (print_info)
1359 pr_info("Full duplex capable\n");
1360 }
1361
1362 {
1363 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1364 unsigned int config;
1365 vp->available_media = window_read16(vp, 3, Wn3_Options);
1366 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1367 vp->available_media = 0x40;
1368 config = window_read32(vp, 3, Wn3_Config);
1369 if (print_info) {
1370 pr_debug(" Internal config register is %4.4x, transceivers %#x.\n",
1371 config, window_read16(vp, 3, Wn3_Options));
1372 pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1373 8 << RAM_SIZE(config),
1374 RAM_WIDTH(config) ? "word" : "byte",
1375 ram_split[RAM_SPLIT(config)],
1376 AUTOSELECT(config) ? "autoselect/" : "",
1377 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1378 media_tbl[XCVR(config)].name);
1379 }
1380 vp->default_media = XCVR(config);
1381 if (vp->default_media == XCVR_NWAY)
1382 vp->has_nway = 1;
1383 vp->autoselect = AUTOSELECT(config);
1384 }
1385
1386 if (vp->media_override != 7) {
1387 pr_info("%s: Media override to transceiver type %d (%s).\n",
1388 print_name, vp->media_override,
1389 media_tbl[vp->media_override].name);
1390 dev->if_port = vp->media_override;
1391 } else
1392 dev->if_port = vp->default_media;
1393
1394 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1395 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1396 int phy, phy_idx = 0;
1397 mii_preamble_required++;
1398 if (vp->drv_flags & EXTRA_PREAMBLE)
1399 mii_preamble_required++;
1400 mdio_sync(vp, 32);
1401 mdio_read(dev, 24, MII_BMSR);
1402 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1403 int mii_status, phyx;
1404
1405 /*
1406 * For the 3c905CX we look at index 24 first, because it bogusly
1407 * reports an external PHY at all indices
1408 */
1409 if (phy == 0)
1410 phyx = 24;
1411 else if (phy <= 24)
1412 phyx = phy - 1;
1413 else
1414 phyx = phy;
1415 mii_status = mdio_read(dev, phyx, MII_BMSR);
1416 if (mii_status && mii_status != 0xffff) {
1417 vp->phys[phy_idx++] = phyx;
1418 if (print_info) {
1419 pr_info(" MII transceiver found at address %d, status %4x.\n",
1420 phyx, mii_status);
1421 }
1422 if ((mii_status & 0x0040) == 0)
1423 mii_preamble_required++;
1424 }
1425 }
1426 mii_preamble_required--;
1427 if (phy_idx == 0) {
1428 pr_warning(" ***WARNING*** No MII transceivers found!\n");
1429 vp->phys[0] = 24;
1430 } else {
1431 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1432 if (vp->full_duplex) {
1433 /* Only advertise the FD media types. */
1434 vp->advertising &= ~0x02A0;
1435 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1436 }
1437 }
1438 vp->mii.phy_id = vp->phys[0];
1439 }
1440
1441 if (vp->capabilities & CapBusMaster) {
1442 vp->full_bus_master_tx = 1;
1443 if (print_info) {
1444 pr_info(" Enabling bus-master transmits and %s receives.\n",
1445 (vp->info2 & 1) ? "early" : "whole-frame" );
1446 }
1447 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1448 vp->bus_master = 0; /* AKPM: vortex only */
1449 }
1450
1451 /* The 3c59x-specific entries in the device structure. */
1452 if (vp->full_bus_master_tx) {
1453 dev->netdev_ops = &boomrang_netdev_ops;
1454 /* Actually, it still should work with iommu. */
1455 if (card_idx < MAX_UNITS &&
1456 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1457 hw_checksums[card_idx] == 1)) {
1458 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1459 }
1460 } else
1461 dev->netdev_ops = &vortex_netdev_ops;
1462
1463 if (print_info) {
1464 pr_info("%s: scatter/gather %sabled. h/w checksums %sabled\n",
1465 print_name,
1466 (dev->features & NETIF_F_SG) ? "en":"dis",
1467 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1468 }
1469
1470 dev->ethtool_ops = &vortex_ethtool_ops;
1471 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1472
1473 if (pdev) {
1474 vp->pm_state_valid = 1;
1475 pci_save_state(VORTEX_PCI(vp));
1476 acpi_set_WOL(dev);
1477 }
1478 retval = register_netdev(dev);
1479 if (retval == 0)
1480 return 0;
1481
1482free_ring:
1483 pci_free_consistent(pdev,
1484 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1485 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1486 vp->rx_ring,
1487 vp->rx_ring_dma);
1488free_region:
1489 if (vp->must_free_region)
1490 release_region(dev->base_addr, vci->io_size);
1491 free_netdev(dev);
1492 pr_err(PFX "vortex_probe1 fails. Returns %d\n", retval);
1493out:
1494 return retval;
1495}
1496
1497static void
1498issue_and_wait(struct net_device *dev, int cmd)
1499{
1500 struct vortex_private *vp = netdev_priv(dev);
1501 void __iomem *ioaddr = vp->ioaddr;
1502 int i;
1503
1504 iowrite16(cmd, ioaddr + EL3_CMD);
1505 for (i = 0; i < 2000; i++) {
1506 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1507 return;
1508 }
1509
1510 /* OK, that didn't work. Do it the slow way. One second */
1511 for (i = 0; i < 100000; i++) {
1512 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1513 if (vortex_debug > 1)
1514 pr_info("%s: command 0x%04x took %d usecs\n",
1515 dev->name, cmd, i * 10);
1516 return;
1517 }
1518 udelay(10);
1519 }
1520 pr_err("%s: command 0x%04x did not complete! Status=0x%x\n",
1521 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1522}
1523
1524static void
1525vortex_set_duplex(struct net_device *dev)
1526{
1527 struct vortex_private *vp = netdev_priv(dev);
1528
1529 pr_info("%s: setting %s-duplex.\n",
1530 dev->name, (vp->full_duplex) ? "full" : "half");
1531
1532 /* Set the full-duplex bit. */
1533 window_write16(vp,
1534 ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1535 (vp->large_frames ? 0x40 : 0) |
1536 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1537 0x100 : 0),
1538 3, Wn3_MAC_Ctrl);
1539}
1540
1541static void vortex_check_media(struct net_device *dev, unsigned int init)
1542{
1543 struct vortex_private *vp = netdev_priv(dev);
1544 unsigned int ok_to_print = 0;
1545
1546 if (vortex_debug > 3)
1547 ok_to_print = 1;
1548
1549 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1550 vp->full_duplex = vp->mii.full_duplex;
1551 vortex_set_duplex(dev);
1552 } else if (init) {
1553 vortex_set_duplex(dev);
1554 }
1555}
1556
1557static int
1558vortex_up(struct net_device *dev)
1559{
1560 struct vortex_private *vp = netdev_priv(dev);
1561 void __iomem *ioaddr = vp->ioaddr;
1562 unsigned int config;
1563 int i, mii_reg1, mii_reg5, err = 0;
1564
1565 if (VORTEX_PCI(vp)) {
1566 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
1567 if (vp->pm_state_valid)
1568 pci_restore_state(VORTEX_PCI(vp));
1569 err = pci_enable_device(VORTEX_PCI(vp));
1570 if (err) {
1571 pr_warning("%s: Could not enable device\n",
1572 dev->name);
1573 goto err_out;
1574 }
1575 }
1576
1577 /* Before initializing select the active media port. */
1578 config = window_read32(vp, 3, Wn3_Config);
1579
1580 if (vp->media_override != 7) {
1581 pr_info("%s: Media override to transceiver %d (%s).\n",
1582 dev->name, vp->media_override,
1583 media_tbl[vp->media_override].name);
1584 dev->if_port = vp->media_override;
1585 } else if (vp->autoselect) {
1586 if (vp->has_nway) {
1587 if (vortex_debug > 1)
1588 pr_info("%s: using NWAY device table, not %d\n",
1589 dev->name, dev->if_port);
1590 dev->if_port = XCVR_NWAY;
1591 } else {
1592 /* Find first available media type, starting with 100baseTx. */
1593 dev->if_port = XCVR_100baseTx;
1594 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1595 dev->if_port = media_tbl[dev->if_port].next;
1596 if (vortex_debug > 1)
1597 pr_info("%s: first available media type: %s\n",
1598 dev->name, media_tbl[dev->if_port].name);
1599 }
1600 } else {
1601 dev->if_port = vp->default_media;
1602 if (vortex_debug > 1)
1603 pr_info("%s: using default media %s\n",
1604 dev->name, media_tbl[dev->if_port].name);
1605 }
1606
1607 init_timer(&vp->timer);
1608 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1609 vp->timer.data = (unsigned long)dev;
1610 vp->timer.function = vortex_timer; /* timer handler */
1611 add_timer(&vp->timer);
1612
1613 init_timer(&vp->rx_oom_timer);
1614 vp->rx_oom_timer.data = (unsigned long)dev;
1615 vp->rx_oom_timer.function = rx_oom_timer;
1616
1617 if (vortex_debug > 1)
1618 pr_debug("%s: Initial media type %s.\n",
1619 dev->name, media_tbl[dev->if_port].name);
1620
1621 vp->full_duplex = vp->mii.force_media;
1622 config = BFINS(config, dev->if_port, 20, 4);
1623 if (vortex_debug > 6)
1624 pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config);
1625 window_write32(vp, config, 3, Wn3_Config);
1626
1627 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1628 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1629 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1630 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1631 vp->mii.full_duplex = vp->full_duplex;
1632
1633 vortex_check_media(dev, 1);
1634 }
1635 else
1636 vortex_set_duplex(dev);
1637
1638 issue_and_wait(dev, TxReset);
1639 /*
1640 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1641 */
1642 issue_and_wait(dev, RxReset|0x04);
1643
1644
1645 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1646
1647 if (vortex_debug > 1) {
1648 pr_debug("%s: vortex_up() irq %d media status %4.4x.\n",
1649 dev->name, dev->irq, window_read16(vp, 4, Wn4_Media));
1650 }
1651
1652 /* Set the station address and mask in window 2 each time opened. */
1653 for (i = 0; i < 6; i++)
1654 window_write8(vp, dev->dev_addr[i], 2, i);
1655 for (; i < 12; i+=2)
1656 window_write16(vp, 0, 2, i);
1657
1658 if (vp->cb_fn_base) {
1659 unsigned short n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1660 if (vp->drv_flags & INVERT_LED_PWR)
1661 n |= 0x10;
1662 if (vp->drv_flags & INVERT_MII_PWR)
1663 n |= 0x4000;
1664 window_write16(vp, n, 2, Wn2_ResetOptions);
1665 }
1666
1667 if (dev->if_port == XCVR_10base2)
1668 /* Start the thinnet transceiver. We should really wait 50ms...*/
1669 iowrite16(StartCoax, ioaddr + EL3_CMD);
1670 if (dev->if_port != XCVR_NWAY) {
1671 window_write16(vp,
1672 (window_read16(vp, 4, Wn4_Media) &
1673 ~(Media_10TP|Media_SQE)) |
1674 media_tbl[dev->if_port].media_bits,
1675 4, Wn4_Media);
1676 }
1677
1678 /* Switch to the stats window, and clear all stats by reading. */
1679 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1680 for (i = 0; i < 10; i++)
1681 window_read8(vp, 6, i);
1682 window_read16(vp, 6, 10);
1683 window_read16(vp, 6, 12);
1684 /* New: On the Vortex we must also clear the BadSSD counter. */
1685 window_read8(vp, 4, 12);
1686 /* ..and on the Boomerang we enable the extra statistics bits. */
1687 window_write16(vp, 0x0040, 4, Wn4_NetDiag);
1688
1689 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1690 vp->cur_rx = vp->dirty_rx = 0;
1691 /* Initialize the RxEarly register as recommended. */
1692 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1693 iowrite32(0x0020, ioaddr + PktStatus);
1694 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1695 }
1696 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1697 vp->cur_tx = vp->dirty_tx = 0;
1698 if (vp->drv_flags & IS_BOOMERANG)
1699 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1700 /* Clear the Rx, Tx rings. */
1701 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1702 vp->rx_ring[i].status = 0;
1703 for (i = 0; i < TX_RING_SIZE; i++)
1704 vp->tx_skbuff[i] = NULL;
1705 iowrite32(0, ioaddr + DownListPtr);
1706 }
1707 /* Set receiver mode: presumably accept b-case and phys addr only. */
1708 set_rx_mode(dev);
1709 /* enable 802.1q tagged frames */
1710 set_8021q_mode(dev, 1);
1711 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1712
1713 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1714 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1715 /* Allow status bits to be seen. */
1716 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1717 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1718 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1719 (vp->bus_master ? DMADone : 0);
1720 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1721 (vp->full_bus_master_rx ? 0 : RxComplete) |
1722 StatsFull | HostError | TxComplete | IntReq
1723 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
1724 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1725 /* Ack all pending events, and set active indicator mask. */
1726 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1727 ioaddr + EL3_CMD);
1728 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1729 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
1730 iowrite32(0x8000, vp->cb_fn_base + 4);
1731 netif_start_queue (dev);
1732err_out:
1733 return err;
1734}
1735
1736static int
1737vortex_open(struct net_device *dev)
1738{
1739 struct vortex_private *vp = netdev_priv(dev);
1740 int i;
1741 int retval;
1742
1743 /* Use the now-standard shared IRQ implementation. */
1744 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1745 boomerang_interrupt : vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
1746 pr_err("%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1747 goto err;
1748 }
1749
1750 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1751 if (vortex_debug > 2)
1752 pr_debug("%s: Filling in the Rx ring.\n", dev->name);
1753 for (i = 0; i < RX_RING_SIZE; i++) {
1754 struct sk_buff *skb;
1755 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1756 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1757 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1758
1759 skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN,
1760 GFP_KERNEL);
1761 vp->rx_skbuff[i] = skb;
1762 if (skb == NULL)
1763 break; /* Bad news! */
1764
1765 skb_reserve(skb, NET_IP_ALIGN); /* Align IP on 16 byte boundaries */
1766 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1767 }
1768 if (i != RX_RING_SIZE) {
1769 int j;
1770 pr_emerg("%s: no memory for rx ring\n", dev->name);
1771 for (j = 0; j < i; j++) {
1772 if (vp->rx_skbuff[j]) {
1773 dev_kfree_skb(vp->rx_skbuff[j]);
1774 vp->rx_skbuff[j] = NULL;
1775 }
1776 }
1777 retval = -ENOMEM;
1778 goto err_free_irq;
1779 }
1780 /* Wrap the ring. */
1781 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1782 }
1783
1784 retval = vortex_up(dev);
1785 if (!retval)
1786 goto out;
1787
1788err_free_irq:
1789 free_irq(dev->irq, dev);
1790err:
1791 if (vortex_debug > 1)
1792 pr_err("%s: vortex_open() fails: returning %d\n", dev->name, retval);
1793out:
1794 return retval;
1795}
1796
1797static void
1798vortex_timer(unsigned long data)
1799{
1800 struct net_device *dev = (struct net_device *)data;
1801 struct vortex_private *vp = netdev_priv(dev);
1802 void __iomem *ioaddr = vp->ioaddr;
1803 int next_tick = 60*HZ;
1804 int ok = 0;
1805 int media_status;
1806
1807 if (vortex_debug > 2) {
1808 pr_debug("%s: Media selection timer tick happened, %s.\n",
1809 dev->name, media_tbl[dev->if_port].name);
1810 pr_debug("dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1811 }
1812
1813 media_status = window_read16(vp, 4, Wn4_Media);
1814 switch (dev->if_port) {
1815 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1816 if (media_status & Media_LnkBeat) {
1817 netif_carrier_on(dev);
1818 ok = 1;
1819 if (vortex_debug > 1)
1820 pr_debug("%s: Media %s has link beat, %x.\n",
1821 dev->name, media_tbl[dev->if_port].name, media_status);
1822 } else {
1823 netif_carrier_off(dev);
1824 if (vortex_debug > 1) {
1825 pr_debug("%s: Media %s has no link beat, %x.\n",
1826 dev->name, media_tbl[dev->if_port].name, media_status);
1827 }
1828 }
1829 break;
1830 case XCVR_MII: case XCVR_NWAY:
1831 {
1832 ok = 1;
1833 vortex_check_media(dev, 0);
1834 }
1835 break;
1836 default: /* Other media types handled by Tx timeouts. */
1837 if (vortex_debug > 1)
1838 pr_debug("%s: Media %s has no indication, %x.\n",
1839 dev->name, media_tbl[dev->if_port].name, media_status);
1840 ok = 1;
1841 }
1842
1843 if (!netif_carrier_ok(dev))
1844 next_tick = 5*HZ;
1845
1846 if (vp->medialock)
1847 goto leave_media_alone;
1848
1849 if (!ok) {
1850 unsigned int config;
1851
1852 spin_lock_irq(&vp->lock);
1853
1854 do {
1855 dev->if_port = media_tbl[dev->if_port].next;
1856 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1857 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1858 dev->if_port = vp->default_media;
1859 if (vortex_debug > 1)
1860 pr_debug("%s: Media selection failing, using default %s port.\n",
1861 dev->name, media_tbl[dev->if_port].name);
1862 } else {
1863 if (vortex_debug > 1)
1864 pr_debug("%s: Media selection failed, now trying %s port.\n",
1865 dev->name, media_tbl[dev->if_port].name);
1866 next_tick = media_tbl[dev->if_port].wait;
1867 }
1868 window_write16(vp,
1869 (media_status & ~(Media_10TP|Media_SQE)) |
1870 media_tbl[dev->if_port].media_bits,
1871 4, Wn4_Media);
1872
1873 config = window_read32(vp, 3, Wn3_Config);
1874 config = BFINS(config, dev->if_port, 20, 4);
1875 window_write32(vp, config, 3, Wn3_Config);
1876
1877 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1878 ioaddr + EL3_CMD);
1879 if (vortex_debug > 1)
1880 pr_debug("wrote 0x%08x to Wn3_Config\n", config);
1881 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1882
1883 spin_unlock_irq(&vp->lock);
1884 }
1885
1886leave_media_alone:
1887 if (vortex_debug > 2)
1888 pr_debug("%s: Media selection timer finished, %s.\n",
1889 dev->name, media_tbl[dev->if_port].name);
1890
1891 mod_timer(&vp->timer, RUN_AT(next_tick));
1892 if (vp->deferred)
1893 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1894}
1895
1896static void vortex_tx_timeout(struct net_device *dev)
1897{
1898 struct vortex_private *vp = netdev_priv(dev);
1899 void __iomem *ioaddr = vp->ioaddr;
1900
1901 pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
1902 dev->name, ioread8(ioaddr + TxStatus),
1903 ioread16(ioaddr + EL3_STATUS));
1904 pr_err(" diagnostics: net %04x media %04x dma %08x fifo %04x\n",
1905 window_read16(vp, 4, Wn4_NetDiag),
1906 window_read16(vp, 4, Wn4_Media),
1907 ioread32(ioaddr + PktStatus),
1908 window_read16(vp, 4, Wn4_FIFODiag));
1909 /* Slight code bloat to be user friendly. */
1910 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1911 pr_err("%s: Transmitter encountered 16 collisions --"
1912 " network cable problem?\n", dev->name);
1913 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1914 pr_err("%s: Interrupt posted but not delivered --"
1915 " IRQ blocked by another device?\n", dev->name);
1916 /* Bad idea here.. but we might as well handle a few events. */
1917 {
1918 /*
1919 * Block interrupts because vortex_interrupt does a bare spin_lock()
1920 */
1921 unsigned long flags;
1922 local_irq_save(flags);
1923 if (vp->full_bus_master_tx)
1924 boomerang_interrupt(dev->irq, dev);
1925 else
1926 vortex_interrupt(dev->irq, dev);
1927 local_irq_restore(flags);
1928 }
1929 }
1930
1931 if (vortex_debug > 0)
1932 dump_tx_ring(dev);
1933
1934 issue_and_wait(dev, TxReset);
1935
1936 dev->stats.tx_errors++;
1937 if (vp->full_bus_master_tx) {
1938 pr_debug("%s: Resetting the Tx ring pointer.\n", dev->name);
1939 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1940 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1941 ioaddr + DownListPtr);
1942 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1943 netif_wake_queue (dev);
1944 if (vp->drv_flags & IS_BOOMERANG)
1945 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1946 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1947 } else {
1948 dev->stats.tx_dropped++;
1949 netif_wake_queue(dev);
1950 }
1951
1952 /* Issue Tx Enable */
1953 iowrite16(TxEnable, ioaddr + EL3_CMD);
1954 dev->trans_start = jiffies; /* prevent tx timeout */
1955}
1956
1957/*
1958 * Handle uncommon interrupt sources. This is a separate routine to minimize
1959 * the cache impact.
1960 */
1961static void
1962vortex_error(struct net_device *dev, int status)
1963{
1964 struct vortex_private *vp = netdev_priv(dev);
1965 void __iomem *ioaddr = vp->ioaddr;
1966 int do_tx_reset = 0, reset_mask = 0;
1967 unsigned char tx_status = 0;
1968
1969 if (vortex_debug > 2) {
1970 pr_err("%s: vortex_error(), status=0x%x\n", dev->name, status);
1971 }
1972
1973 if (status & TxComplete) { /* Really "TxError" for us. */
1974 tx_status = ioread8(ioaddr + TxStatus);
1975 /* Presumably a tx-timeout. We must merely re-enable. */
1976 if (vortex_debug > 2 ||
1977 (tx_status != 0x88 && vortex_debug > 0)) {
1978 pr_err("%s: Transmit error, Tx status register %2.2x.\n",
1979 dev->name, tx_status);
1980 if (tx_status == 0x82) {
1981 pr_err("Probably a duplex mismatch. See "
1982 "Documentation/networking/vortex.txt\n");
1983 }
1984 dump_tx_ring(dev);
1985 }
1986 if (tx_status & 0x14) dev->stats.tx_fifo_errors++;
1987 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
1988 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
1989 iowrite8(0, ioaddr + TxStatus);
1990 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1991 do_tx_reset = 1;
1992 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1993 do_tx_reset = 1;
1994 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1995 } else { /* Merely re-enable the transmitter. */
1996 iowrite16(TxEnable, ioaddr + EL3_CMD);
1997 }
1998 }
1999
2000 if (status & RxEarly) /* Rx early is unused. */
2001 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
2002
2003 if (status & StatsFull) { /* Empty statistics. */
2004 static int DoneDidThat;
2005 if (vortex_debug > 4)
2006 pr_debug("%s: Updating stats.\n", dev->name);
2007 update_stats(ioaddr, dev);
2008 /* HACK: Disable statistics as an interrupt source. */
2009 /* This occurs when we have the wrong media type! */
2010 if (DoneDidThat == 0 &&
2011 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
2012 pr_warning("%s: Updating statistics failed, disabling "
2013 "stats as an interrupt source.\n", dev->name);
2014 iowrite16(SetIntrEnb |
2015 (window_read16(vp, 5, 10) & ~StatsFull),
2016 ioaddr + EL3_CMD);
2017 vp->intr_enable &= ~StatsFull;
2018 DoneDidThat++;
2019 }
2020 }
2021 if (status & IntReq) { /* Restore all interrupt sources. */
2022 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
2023 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
2024 }
2025 if (status & HostError) {
2026 u16 fifo_diag;
2027 fifo_diag = window_read16(vp, 4, Wn4_FIFODiag);
2028 pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n",
2029 dev->name, fifo_diag);
2030 /* Adapter failure requires Tx/Rx reset and reinit. */
2031 if (vp->full_bus_master_tx) {
2032 int bus_status = ioread32(ioaddr + PktStatus);
2033 /* 0x80000000 PCI master abort. */
2034 /* 0x40000000 PCI target abort. */
2035 if (vortex_debug)
2036 pr_err("%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
2037
2038 /* In this case, blow the card away */
2039 /* Must not enter D3 or we can't legally issue the reset! */
2040 vortex_down(dev, 0);
2041 issue_and_wait(dev, TotalReset | 0xff);
2042 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2043 } else if (fifo_diag & 0x0400)
2044 do_tx_reset = 1;
2045 if (fifo_diag & 0x3000) {
2046 /* Reset Rx fifo and upload logic */
2047 issue_and_wait(dev, RxReset|0x07);
2048 /* Set the Rx filter to the current state. */
2049 set_rx_mode(dev);
2050 /* enable 802.1q VLAN tagged frames */
2051 set_8021q_mode(dev, 1);
2052 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2053 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
2054 }
2055 }
2056
2057 if (do_tx_reset) {
2058 issue_and_wait(dev, TxReset|reset_mask);
2059 iowrite16(TxEnable, ioaddr + EL3_CMD);
2060 if (!vp->full_bus_master_tx)
2061 netif_wake_queue(dev);
2062 }
2063}
2064
2065static netdev_tx_t
2066vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2067{
2068 struct vortex_private *vp = netdev_priv(dev);
2069 void __iomem *ioaddr = vp->ioaddr;
2070
2071 /* Put out the doubleword header... */
2072 iowrite32(skb->len, ioaddr + TX_FIFO);
2073 if (vp->bus_master) {
2074 /* Set the bus-master controller to transfer the packet. */
2075 int len = (skb->len + 3) & ~3;
2076 vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len,
2077 PCI_DMA_TODEVICE);
2078 spin_lock_irq(&vp->window_lock);
2079 window_set(vp, 7);
2080 iowrite32(vp->tx_skb_dma, ioaddr + Wn7_MasterAddr);
2081 iowrite16(len, ioaddr + Wn7_MasterLen);
2082 spin_unlock_irq(&vp->window_lock);
2083 vp->tx_skb = skb;
2084 iowrite16(StartDMADown, ioaddr + EL3_CMD);
2085 /* netif_wake_queue() will be called at the DMADone interrupt. */
2086 } else {
2087 /* ... and the packet rounded to a doubleword. */
2088 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
2089 dev_kfree_skb (skb);
2090 if (ioread16(ioaddr + TxFree) > 1536) {
2091 netif_start_queue (dev); /* AKPM: redundant? */
2092 } else {
2093 /* Interrupt us when the FIFO has room for max-sized packet. */
2094 netif_stop_queue(dev);
2095 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2096 }
2097 }
2098
2099
2100 /* Clear the Tx status stack. */
2101 {
2102 int tx_status;
2103 int i = 32;
2104
2105 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
2106 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2107 if (vortex_debug > 2)
2108 pr_debug("%s: Tx error, status %2.2x.\n",
2109 dev->name, tx_status);
2110 if (tx_status & 0x04) dev->stats.tx_fifo_errors++;
2111 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
2112 if (tx_status & 0x30) {
2113 issue_and_wait(dev, TxReset);
2114 }
2115 iowrite16(TxEnable, ioaddr + EL3_CMD);
2116 }
2117 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
2118 }
2119 }
2120 return NETDEV_TX_OK;
2121}
2122
2123static netdev_tx_t
2124boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2125{
2126 struct vortex_private *vp = netdev_priv(dev);
2127 void __iomem *ioaddr = vp->ioaddr;
2128 /* Calculate the next Tx descriptor entry. */
2129 int entry = vp->cur_tx % TX_RING_SIZE;
2130 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2131 unsigned long flags;
2132
2133 if (vortex_debug > 6) {
2134 pr_debug("boomerang_start_xmit()\n");
2135 pr_debug("%s: Trying to send a packet, Tx index %d.\n",
2136 dev->name, vp->cur_tx);
2137 }
2138
2139 /*
2140 * We can't allow a recursion from our interrupt handler back into the
2141 * tx routine, as they take the same spin lock, and that causes
2142 * deadlock. Just return NETDEV_TX_BUSY and let the stack try again in
2143 * a bit
2144 */
2145 if (vp->handling_irq)
2146 return NETDEV_TX_BUSY;
2147
2148 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2149 if (vortex_debug > 0)
2150 pr_warning("%s: BUG! Tx Ring full, refusing to send buffer.\n",
2151 dev->name);
2152 netif_stop_queue(dev);
2153 return NETDEV_TX_BUSY;
2154 }
2155
2156 vp->tx_skbuff[entry] = skb;
2157
2158 vp->tx_ring[entry].next = 0;
2159#if DO_ZEROCOPY
2160 if (skb->ip_summed != CHECKSUM_PARTIAL)
2161 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2162 else
2163 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2164
2165 if (!skb_shinfo(skb)->nr_frags) {
2166 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2167 skb->len, PCI_DMA_TODEVICE));
2168 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2169 } else {
2170 int i;
2171
2172 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2173 skb_headlen(skb), PCI_DMA_TODEVICE));
2174 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb_headlen(skb));
2175
2176 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2177 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2178
2179 vp->tx_ring[entry].frag[i+1].addr =
2180 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2181 (void*)page_address(frag->page) + frag->page_offset,
2182 frag->size, PCI_DMA_TODEVICE));
2183
2184 if (i == skb_shinfo(skb)->nr_frags-1)
2185 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2186 else
2187 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2188 }
2189 }
2190#else
2191 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2192 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2193 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2194#endif
2195
2196 spin_lock_irqsave(&vp->lock, flags);
2197 /* Wait for the stall to complete. */
2198 issue_and_wait(dev, DownStall);
2199 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
2200 if (ioread32(ioaddr + DownListPtr) == 0) {
2201 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
2202 vp->queued_packet++;
2203 }
2204
2205 vp->cur_tx++;
2206 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2207 netif_stop_queue (dev);
2208 } else { /* Clear previous interrupt enable. */
2209#if defined(tx_interrupt_mitigation)
2210 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2211 * were selected, this would corrupt DN_COMPLETE. No?
2212 */
2213 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2214#endif
2215 }
2216 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2217 spin_unlock_irqrestore(&vp->lock, flags);
2218 return NETDEV_TX_OK;
2219}
2220
2221/* The interrupt handler does all of the Rx thread work and cleans up
2222 after the Tx thread. */
2223
2224/*
2225 * This is the ISR for the vortex series chips.
2226 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2227 */
2228
2229static irqreturn_t
2230vortex_interrupt(int irq, void *dev_id)
2231{
2232 struct net_device *dev = dev_id;
2233 struct vortex_private *vp = netdev_priv(dev);
2234 void __iomem *ioaddr;
2235 int status;
2236 int work_done = max_interrupt_work;
2237 int handled = 0;
2238
2239 ioaddr = vp->ioaddr;
2240 spin_lock(&vp->lock);
2241
2242 status = ioread16(ioaddr + EL3_STATUS);
2243
2244 if (vortex_debug > 6)
2245 pr_debug("vortex_interrupt(). status=0x%4x\n", status);
2246
2247 if ((status & IntLatch) == 0)
2248 goto handler_exit; /* No interrupt: shared IRQs cause this */
2249 handled = 1;
2250
2251 if (status & IntReq) {
2252 status |= vp->deferred;
2253 vp->deferred = 0;
2254 }
2255
2256 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2257 goto handler_exit;
2258
2259 if (vortex_debug > 4)
2260 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2261 dev->name, status, ioread8(ioaddr + Timer));
2262
2263 spin_lock(&vp->window_lock);
2264 window_set(vp, 7);
2265
2266 do {
2267 if (vortex_debug > 5)
2268 pr_debug("%s: In interrupt loop, status %4.4x.\n",
2269 dev->name, status);
2270 if (status & RxComplete)
2271 vortex_rx(dev);
2272
2273 if (status & TxAvailable) {
2274 if (vortex_debug > 5)
2275 pr_debug(" TX room bit was handled.\n");
2276 /* There's room in the FIFO for a full-sized packet. */
2277 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2278 netif_wake_queue (dev);
2279 }
2280
2281 if (status & DMADone) {
2282 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2283 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
2284 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2285 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
2286 if (ioread16(ioaddr + TxFree) > 1536) {
2287 /*
2288 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2289 * insufficient FIFO room, the TxAvailable test will succeed and call
2290 * netif_wake_queue()
2291 */
2292 netif_wake_queue(dev);
2293 } else { /* Interrupt when FIFO has room for max-sized packet. */
2294 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2295 netif_stop_queue(dev);
2296 }
2297 }
2298 }
2299 /* Check for all uncommon interrupts at once. */
2300 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2301 if (status == 0xffff)
2302 break;
2303 if (status & RxEarly)
2304 vortex_rx(dev);
2305 spin_unlock(&vp->window_lock);
2306 vortex_error(dev, status);
2307 spin_lock(&vp->window_lock);
2308 window_set(vp, 7);
2309 }
2310
2311 if (--work_done < 0) {
2312 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2313 dev->name, status);
2314 /* Disable all pending interrupts. */
2315 do {
2316 vp->deferred |= status;
2317 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2318 ioaddr + EL3_CMD);
2319 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2320 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2321 /* The timer will reenable interrupts. */
2322 mod_timer(&vp->timer, jiffies + 1*HZ);
2323 break;
2324 }
2325 /* Acknowledge the IRQ. */
2326 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2327 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
2328
2329 spin_unlock(&vp->window_lock);
2330
2331 if (vortex_debug > 4)
2332 pr_debug("%s: exiting interrupt, status %4.4x.\n",
2333 dev->name, status);
2334handler_exit:
2335 spin_unlock(&vp->lock);
2336 return IRQ_RETVAL(handled);
2337}
2338
2339/*
2340 * This is the ISR for the boomerang series chips.
2341 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2342 */
2343
2344static irqreturn_t
2345boomerang_interrupt(int irq, void *dev_id)
2346{
2347 struct net_device *dev = dev_id;
2348 struct vortex_private *vp = netdev_priv(dev);
2349 void __iomem *ioaddr;
2350 int status;
2351 int work_done = max_interrupt_work;
2352
2353 ioaddr = vp->ioaddr;
2354
2355
2356 /*
2357 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2358 * and boomerang_start_xmit
2359 */
2360 spin_lock(&vp->lock);
2361 vp->handling_irq = 1;
2362
2363 status = ioread16(ioaddr + EL3_STATUS);
2364
2365 if (vortex_debug > 6)
2366 pr_debug("boomerang_interrupt. status=0x%4x\n", status);
2367
2368 if ((status & IntLatch) == 0)
2369 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2370
2371 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2372 if (vortex_debug > 1)
2373 pr_debug("boomerang_interrupt(1): status = 0xffff\n");
2374 goto handler_exit;
2375 }
2376
2377 if (status & IntReq) {
2378 status |= vp->deferred;
2379 vp->deferred = 0;
2380 }
2381
2382 if (vortex_debug > 4)
2383 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2384 dev->name, status, ioread8(ioaddr + Timer));
2385 do {
2386 if (vortex_debug > 5)
2387 pr_debug("%s: In interrupt loop, status %4.4x.\n",
2388 dev->name, status);
2389 if (status & UpComplete) {
2390 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
2391 if (vortex_debug > 5)
2392 pr_debug("boomerang_interrupt->boomerang_rx\n");
2393 boomerang_rx(dev);
2394 }
2395
2396 if (status & DownComplete) {
2397 unsigned int dirty_tx = vp->dirty_tx;
2398
2399 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
2400 while (vp->cur_tx - dirty_tx > 0) {
2401 int entry = dirty_tx % TX_RING_SIZE;
2402#if 1 /* AKPM: the latter is faster, but cyclone-only */
2403 if (ioread32(ioaddr + DownListPtr) ==
2404 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2405 break; /* It still hasn't been processed. */
2406#else
2407 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2408 break; /* It still hasn't been processed. */
2409#endif
2410
2411 if (vp->tx_skbuff[entry]) {
2412 struct sk_buff *skb = vp->tx_skbuff[entry];
2413#if DO_ZEROCOPY
2414 int i;
2415 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2416 pci_unmap_single(VORTEX_PCI(vp),
2417 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2418 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2419 PCI_DMA_TODEVICE);
2420#else
2421 pci_unmap_single(VORTEX_PCI(vp),
2422 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2423#endif
2424 dev_kfree_skb_irq(skb);
2425 vp->tx_skbuff[entry] = NULL;
2426 } else {
2427 pr_debug("boomerang_interrupt: no skb!\n");
2428 }
2429 /* dev->stats.tx_packets++; Counted below. */
2430 dirty_tx++;
2431 }
2432 vp->dirty_tx = dirty_tx;
2433 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2434 if (vortex_debug > 6)
2435 pr_debug("boomerang_interrupt: wake queue\n");
2436 netif_wake_queue (dev);
2437 }
2438 }
2439
2440 /* Check for all uncommon interrupts at once. */
2441 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2442 vortex_error(dev, status);
2443
2444 if (--work_done < 0) {
2445 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2446 dev->name, status);
2447 /* Disable all pending interrupts. */
2448 do {
2449 vp->deferred |= status;
2450 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2451 ioaddr + EL3_CMD);
2452 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2453 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2454 /* The timer will reenable interrupts. */
2455 mod_timer(&vp->timer, jiffies + 1*HZ);
2456 break;
2457 }
2458 /* Acknowledge the IRQ. */
2459 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2460 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
2461 iowrite32(0x8000, vp->cb_fn_base + 4);
2462
2463 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
2464
2465 if (vortex_debug > 4)
2466 pr_debug("%s: exiting interrupt, status %4.4x.\n",
2467 dev->name, status);
2468handler_exit:
2469 vp->handling_irq = 0;
2470 spin_unlock(&vp->lock);
2471 return IRQ_HANDLED;
2472}
2473
2474static int vortex_rx(struct net_device *dev)
2475{
2476 struct vortex_private *vp = netdev_priv(dev);
2477 void __iomem *ioaddr = vp->ioaddr;
2478 int i;
2479 short rx_status;
2480
2481 if (vortex_debug > 5)
2482 pr_debug("vortex_rx(): status %4.4x, rx_status %4.4x.\n",
2483 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2484 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
2485 if (rx_status & 0x4000) { /* Error, update stats. */
2486 unsigned char rx_error = ioread8(ioaddr + RxErrors);
2487 if (vortex_debug > 2)
2488 pr_debug(" Rx error: status %2.2x.\n", rx_error);
2489 dev->stats.rx_errors++;
2490 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2491 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2492 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2493 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2494 if (rx_error & 0x10) dev->stats.rx_length_errors++;
2495 } else {
2496 /* The packet length: up to 4.5K!. */
2497 int pkt_len = rx_status & 0x1fff;
2498 struct sk_buff *skb;
2499
2500 skb = dev_alloc_skb(pkt_len + 5);
2501 if (vortex_debug > 4)
2502 pr_debug("Receiving packet size %d status %4.4x.\n",
2503 pkt_len, rx_status);
2504 if (skb != NULL) {
2505 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2506 /* 'skb_put()' points to the start of sk_buff data area. */
2507 if (vp->bus_master &&
2508 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
2509 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2510 pkt_len, PCI_DMA_FROMDEVICE);
2511 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2512 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2513 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2514 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
2515 ;
2516 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2517 } else {
2518 ioread32_rep(ioaddr + RX_FIFO,
2519 skb_put(skb, pkt_len),
2520 (pkt_len + 3) >> 2);
2521 }
2522 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
2523 skb->protocol = eth_type_trans(skb, dev);
2524 netif_rx(skb);
2525 dev->stats.rx_packets++;
2526 /* Wait a limited time to go to next packet. */
2527 for (i = 200; i >= 0; i--)
2528 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
2529 break;
2530 continue;
2531 } else if (vortex_debug > 0)
2532 pr_notice("%s: No memory to allocate a sk_buff of size %d.\n",
2533 dev->name, pkt_len);
2534 dev->stats.rx_dropped++;
2535 }
2536 issue_and_wait(dev, RxDiscard);
2537 }
2538
2539 return 0;
2540}
2541
2542static int
2543boomerang_rx(struct net_device *dev)
2544{
2545 struct vortex_private *vp = netdev_priv(dev);
2546 int entry = vp->cur_rx % RX_RING_SIZE;
2547 void __iomem *ioaddr = vp->ioaddr;
2548 int rx_status;
2549 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2550
2551 if (vortex_debug > 5)
2552 pr_debug("boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
2553
2554 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2555 if (--rx_work_limit < 0)
2556 break;
2557 if (rx_status & RxDError) { /* Error, update stats. */
2558 unsigned char rx_error = rx_status >> 16;
2559 if (vortex_debug > 2)
2560 pr_debug(" Rx error: status %2.2x.\n", rx_error);
2561 dev->stats.rx_errors++;
2562 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2563 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2564 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2565 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2566 if (rx_error & 0x10) dev->stats.rx_length_errors++;
2567 } else {
2568 /* The packet length: up to 4.5K!. */
2569 int pkt_len = rx_status & 0x1fff;
2570 struct sk_buff *skb;
2571 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2572
2573 if (vortex_debug > 4)
2574 pr_debug("Receiving packet size %d status %4.4x.\n",
2575 pkt_len, rx_status);
2576
2577 /* Check if the packet is long enough to just accept without
2578 copying to a properly sized skbuff. */
2579 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
2580 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2581 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2582 /* 'skb_put()' points to the start of sk_buff data area. */
2583 memcpy(skb_put(skb, pkt_len),
2584 vp->rx_skbuff[entry]->data,
2585 pkt_len);
2586 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2587 vp->rx_copy++;
2588 } else {
2589 /* Pass up the skbuff already on the Rx ring. */
2590 skb = vp->rx_skbuff[entry];
2591 vp->rx_skbuff[entry] = NULL;
2592 skb_put(skb, pkt_len);
2593 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2594 vp->rx_nocopy++;
2595 }
2596 skb->protocol = eth_type_trans(skb, dev);
2597 { /* Use hardware checksum info. */
2598 int csum_bits = rx_status & 0xee000000;
2599 if (csum_bits &&
2600 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2601 csum_bits == (IPChksumValid | UDPChksumValid))) {
2602 skb->ip_summed = CHECKSUM_UNNECESSARY;
2603 vp->rx_csumhits++;
2604 }
2605 }
2606 netif_rx(skb);
2607 dev->stats.rx_packets++;
2608 }
2609 entry = (++vp->cur_rx) % RX_RING_SIZE;
2610 }
2611 /* Refill the Rx ring buffers. */
2612 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2613 struct sk_buff *skb;
2614 entry = vp->dirty_rx % RX_RING_SIZE;
2615 if (vp->rx_skbuff[entry] == NULL) {
2616 skb = netdev_alloc_skb_ip_align(dev, PKT_BUF_SZ);
2617 if (skb == NULL) {
2618 static unsigned long last_jif;
2619 if (time_after(jiffies, last_jif + 10 * HZ)) {
2620 pr_warning("%s: memory shortage\n", dev->name);
2621 last_jif = jiffies;
2622 }
2623 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2624 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2625 break; /* Bad news! */
2626 }
2627
2628 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
2629 vp->rx_skbuff[entry] = skb;
2630 }
2631 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
2632 iowrite16(UpUnstall, ioaddr + EL3_CMD);
2633 }
2634 return 0;
2635}
2636
2637/*
2638 * If we've hit a total OOM refilling the Rx ring we poll once a second
2639 * for some memory. Otherwise there is no way to restart the rx process.
2640 */
2641static void
2642rx_oom_timer(unsigned long arg)
2643{
2644 struct net_device *dev = (struct net_device *)arg;
2645 struct vortex_private *vp = netdev_priv(dev);
2646
2647 spin_lock_irq(&vp->lock);
2648 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2649 boomerang_rx(dev);
2650 if (vortex_debug > 1) {
2651 pr_debug("%s: rx_oom_timer %s\n", dev->name,
2652 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2653 }
2654 spin_unlock_irq(&vp->lock);
2655}
2656
2657static void
2658vortex_down(struct net_device *dev, int final_down)
2659{
2660 struct vortex_private *vp = netdev_priv(dev);
2661 void __iomem *ioaddr = vp->ioaddr;
2662
2663 netif_stop_queue (dev);
2664
2665 del_timer_sync(&vp->rx_oom_timer);
2666 del_timer_sync(&vp->timer);
2667
2668 /* Turn off statistics ASAP. We update dev->stats below. */
2669 iowrite16(StatsDisable, ioaddr + EL3_CMD);
2670
2671 /* Disable the receiver and transmitter. */
2672 iowrite16(RxDisable, ioaddr + EL3_CMD);
2673 iowrite16(TxDisable, ioaddr + EL3_CMD);
2674
2675 /* Disable receiving 802.1q tagged frames */
2676 set_8021q_mode(dev, 0);
2677
2678 if (dev->if_port == XCVR_10base2)
2679 /* Turn off thinnet power. Green! */
2680 iowrite16(StopCoax, ioaddr + EL3_CMD);
2681
2682 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2683
2684 update_stats(ioaddr, dev);
2685 if (vp->full_bus_master_rx)
2686 iowrite32(0, ioaddr + UpListPtr);
2687 if (vp->full_bus_master_tx)
2688 iowrite32(0, ioaddr + DownListPtr);
2689
2690 if (final_down && VORTEX_PCI(vp)) {
2691 vp->pm_state_valid = 1;
2692 pci_save_state(VORTEX_PCI(vp));
2693 acpi_set_WOL(dev);
2694 }
2695}
2696
2697static int
2698vortex_close(struct net_device *dev)
2699{
2700 struct vortex_private *vp = netdev_priv(dev);
2701 void __iomem *ioaddr = vp->ioaddr;
2702 int i;
2703
2704 if (netif_device_present(dev))
2705 vortex_down(dev, 1);
2706
2707 if (vortex_debug > 1) {
2708 pr_debug("%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
2709 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
2710 pr_debug("%s: vortex close stats: rx_nocopy %d rx_copy %d"
2711 " tx_queued %d Rx pre-checksummed %d.\n",
2712 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2713 }
2714
2715#if DO_ZEROCOPY
2716 if (vp->rx_csumhits &&
2717 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2718 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2719 pr_warning("%s supports hardware checksums, and we're not using them!\n", dev->name);
2720 }
2721#endif
2722
2723 free_irq(dev->irq, dev);
2724
2725 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2726 for (i = 0; i < RX_RING_SIZE; i++)
2727 if (vp->rx_skbuff[i]) {
2728 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2729 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2730 dev_kfree_skb(vp->rx_skbuff[i]);
2731 vp->rx_skbuff[i] = NULL;
2732 }
2733 }
2734 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2735 for (i = 0; i < TX_RING_SIZE; i++) {
2736 if (vp->tx_skbuff[i]) {
2737 struct sk_buff *skb = vp->tx_skbuff[i];
2738#if DO_ZEROCOPY
2739 int k;
2740
2741 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2742 pci_unmap_single(VORTEX_PCI(vp),
2743 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2744 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2745 PCI_DMA_TODEVICE);
2746#else
2747 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2748#endif
2749 dev_kfree_skb(skb);
2750 vp->tx_skbuff[i] = NULL;
2751 }
2752 }
2753 }
2754
2755 return 0;
2756}
2757
2758static void
2759dump_tx_ring(struct net_device *dev)
2760{
2761 if (vortex_debug > 0) {
2762 struct vortex_private *vp = netdev_priv(dev);
2763 void __iomem *ioaddr = vp->ioaddr;
2764
2765 if (vp->full_bus_master_tx) {
2766 int i;
2767 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
2768
2769 pr_err(" Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2770 vp->full_bus_master_tx,
2771 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2772 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2773 pr_err(" Transmit list %8.8x vs. %p.\n",
2774 ioread32(ioaddr + DownListPtr),
2775 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2776 issue_and_wait(dev, DownStall);
2777 for (i = 0; i < TX_RING_SIZE; i++) {
2778 unsigned int length;
2779
2780#if DO_ZEROCOPY
2781 length = le32_to_cpu(vp->tx_ring[i].frag[0].length);
2782#else
2783 length = le32_to_cpu(vp->tx_ring[i].length);
2784#endif
2785 pr_err(" %d: @%p length %8.8x status %8.8x\n",
2786 i, &vp->tx_ring[i], length,
2787 le32_to_cpu(vp->tx_ring[i].status));
2788 }
2789 if (!stalled)
2790 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2791 }
2792 }
2793}
2794
2795static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2796{
2797 struct vortex_private *vp = netdev_priv(dev);
2798 void __iomem *ioaddr = vp->ioaddr;
2799 unsigned long flags;
2800
2801 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2802 spin_lock_irqsave (&vp->lock, flags);
2803 update_stats(ioaddr, dev);
2804 spin_unlock_irqrestore (&vp->lock, flags);
2805 }
2806 return &dev->stats;
2807}
2808
2809/* Update statistics.
2810 Unlike with the EL3 we need not worry about interrupts changing
2811 the window setting from underneath us, but we must still guard
2812 against a race condition with a StatsUpdate interrupt updating the
2813 table. This is done by checking that the ASM (!) code generated uses
2814 atomic updates with '+='.
2815 */
2816static void update_stats(void __iomem *ioaddr, struct net_device *dev)
2817{
2818 struct vortex_private *vp = netdev_priv(dev);
2819
2820 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2821 /* Switch to the stats window, and read everything. */
2822 dev->stats.tx_carrier_errors += window_read8(vp, 6, 0);
2823 dev->stats.tx_heartbeat_errors += window_read8(vp, 6, 1);
2824 dev->stats.tx_window_errors += window_read8(vp, 6, 4);
2825 dev->stats.rx_fifo_errors += window_read8(vp, 6, 5);
2826 dev->stats.tx_packets += window_read8(vp, 6, 6);
2827 dev->stats.tx_packets += (window_read8(vp, 6, 9) &
2828 0x30) << 4;
2829 /* Rx packets */ window_read8(vp, 6, 7); /* Must read to clear */
2830 /* Don't bother with register 9, an extension of registers 6&7.
2831 If we do use the 6&7 values the atomic update assumption above
2832 is invalid. */
2833 dev->stats.rx_bytes += window_read16(vp, 6, 10);
2834 dev->stats.tx_bytes += window_read16(vp, 6, 12);
2835 /* Extra stats for get_ethtool_stats() */
2836 vp->xstats.tx_multiple_collisions += window_read8(vp, 6, 2);
2837 vp->xstats.tx_single_collisions += window_read8(vp, 6, 3);
2838 vp->xstats.tx_deferred += window_read8(vp, 6, 8);
2839 vp->xstats.rx_bad_ssd += window_read8(vp, 4, 12);
2840
2841 dev->stats.collisions = vp->xstats.tx_multiple_collisions
2842 + vp->xstats.tx_single_collisions
2843 + vp->xstats.tx_max_collisions;
2844
2845 {
2846 u8 up = window_read8(vp, 4, 13);
2847 dev->stats.rx_bytes += (up & 0x0f) << 16;
2848 dev->stats.tx_bytes += (up & 0xf0) << 12;
2849 }
2850}
2851
2852static int vortex_nway_reset(struct net_device *dev)
2853{
2854 struct vortex_private *vp = netdev_priv(dev);
2855
2856 return mii_nway_restart(&vp->mii);
2857}
2858
2859static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2860{
2861 struct vortex_private *vp = netdev_priv(dev);
2862
2863 return mii_ethtool_gset(&vp->mii, cmd);
2864}
2865
2866static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2867{
2868 struct vortex_private *vp = netdev_priv(dev);
2869
2870 return mii_ethtool_sset(&vp->mii, cmd);
2871}
2872
2873static u32 vortex_get_msglevel(struct net_device *dev)
2874{
2875 return vortex_debug;
2876}
2877
2878static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2879{
2880 vortex_debug = dbg;
2881}
2882
2883static int vortex_get_sset_count(struct net_device *dev, int sset)
2884{
2885 switch (sset) {
2886 case ETH_SS_STATS:
2887 return VORTEX_NUM_STATS;
2888 default:
2889 return -EOPNOTSUPP;
2890 }
2891}
2892
2893static void vortex_get_ethtool_stats(struct net_device *dev,
2894 struct ethtool_stats *stats, u64 *data)
2895{
2896 struct vortex_private *vp = netdev_priv(dev);
2897 void __iomem *ioaddr = vp->ioaddr;
2898 unsigned long flags;
2899
2900 spin_lock_irqsave(&vp->lock, flags);
2901 update_stats(ioaddr, dev);
2902 spin_unlock_irqrestore(&vp->lock, flags);
2903
2904 data[0] = vp->xstats.tx_deferred;
2905 data[1] = vp->xstats.tx_max_collisions;
2906 data[2] = vp->xstats.tx_multiple_collisions;
2907 data[3] = vp->xstats.tx_single_collisions;
2908 data[4] = vp->xstats.rx_bad_ssd;
2909}
2910
2911
2912static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2913{
2914 switch (stringset) {
2915 case ETH_SS_STATS:
2916 memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
2917 break;
2918 default:
2919 WARN_ON(1);
2920 break;
2921 }
2922}
2923
2924static void vortex_get_drvinfo(struct net_device *dev,
2925 struct ethtool_drvinfo *info)
2926{
2927 struct vortex_private *vp = netdev_priv(dev);
2928
2929 strcpy(info->driver, DRV_NAME);
2930 if (VORTEX_PCI(vp)) {
2931 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
2932 } else {
2933 if (VORTEX_EISA(vp))
2934 strcpy(info->bus_info, dev_name(vp->gendev));
2935 else
2936 sprintf(info->bus_info, "EISA 0x%lx %d",
2937 dev->base_addr, dev->irq);
2938 }
2939}
2940
2941static void vortex_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2942{
2943 struct vortex_private *vp = netdev_priv(dev);
2944
2945 if (!VORTEX_PCI(vp))
2946 return;
2947
2948 wol->supported = WAKE_MAGIC;
2949
2950 wol->wolopts = 0;
2951 if (vp->enable_wol)
2952 wol->wolopts |= WAKE_MAGIC;
2953}
2954
2955static int vortex_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2956{
2957 struct vortex_private *vp = netdev_priv(dev);
2958
2959 if (!VORTEX_PCI(vp))
2960 return -EOPNOTSUPP;
2961
2962 if (wol->wolopts & ~WAKE_MAGIC)
2963 return -EINVAL;
2964
2965 if (wol->wolopts & WAKE_MAGIC)
2966 vp->enable_wol = 1;
2967 else
2968 vp->enable_wol = 0;
2969 acpi_set_WOL(dev);
2970
2971 return 0;
2972}
2973
2974static const struct ethtool_ops vortex_ethtool_ops = {
2975 .get_drvinfo = vortex_get_drvinfo,
2976 .get_strings = vortex_get_strings,
2977 .get_msglevel = vortex_get_msglevel,
2978 .set_msglevel = vortex_set_msglevel,
2979 .get_ethtool_stats = vortex_get_ethtool_stats,
2980 .get_sset_count = vortex_get_sset_count,
2981 .get_settings = vortex_get_settings,
2982 .set_settings = vortex_set_settings,
2983 .get_link = ethtool_op_get_link,
2984 .nway_reset = vortex_nway_reset,
2985 .get_wol = vortex_get_wol,
2986 .set_wol = vortex_set_wol,
2987};
2988
2989#ifdef CONFIG_PCI
2990/*
2991 * Must power the device up to do MDIO operations
2992 */
2993static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2994{
2995 int err;
2996 struct vortex_private *vp = netdev_priv(dev);
2997 pci_power_t state = 0;
2998
2999 if(VORTEX_PCI(vp))
3000 state = VORTEX_PCI(vp)->current_state;
3001
3002 /* The kernel core really should have pci_get_power_state() */
3003
3004 if(state != 0)
3005 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
3006 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
3007 if(state != 0)
3008 pci_set_power_state(VORTEX_PCI(vp), state);
3009
3010 return err;
3011}
3012#endif
3013
3014
3015/* Pre-Cyclone chips have no documented multicast filter, so the only
3016 multicast setting is to receive all multicast frames. At least
3017 the chip has a very clean way to set the mode, unlike many others. */
3018static void set_rx_mode(struct net_device *dev)
3019{
3020 struct vortex_private *vp = netdev_priv(dev);
3021 void __iomem *ioaddr = vp->ioaddr;
3022 int new_mode;
3023
3024 if (dev->flags & IFF_PROMISC) {
3025 if (vortex_debug > 3)
3026 pr_notice("%s: Setting promiscuous mode.\n", dev->name);
3027 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
3028 } else if (!netdev_mc_empty(dev) || dev->flags & IFF_ALLMULTI) {
3029 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
3030 } else
3031 new_mode = SetRxFilter | RxStation | RxBroadcast;
3032
3033 iowrite16(new_mode, ioaddr + EL3_CMD);
3034}
3035
3036#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
3037/* Setup the card so that it can receive frames with an 802.1q VLAN tag.
3038 Note that this must be done after each RxReset due to some backwards
3039 compatibility logic in the Cyclone and Tornado ASICs */
3040
3041/* The Ethernet Type used for 802.1q tagged frames */
3042#define VLAN_ETHER_TYPE 0x8100
3043
3044static void set_8021q_mode(struct net_device *dev, int enable)
3045{
3046 struct vortex_private *vp = netdev_priv(dev);
3047 int mac_ctrl;
3048
3049 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
3050 /* cyclone and tornado chipsets can recognize 802.1q
3051 * tagged frames and treat them correctly */
3052
3053 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
3054 if (enable)
3055 max_pkt_size += 4; /* 802.1Q VLAN tag */
3056
3057 window_write16(vp, max_pkt_size, 3, Wn3_MaxPktSize);
3058
3059 /* set VlanEtherType to let the hardware checksumming
3060 treat tagged frames correctly */
3061 window_write16(vp, VLAN_ETHER_TYPE, 7, Wn7_VlanEtherType);
3062 } else {
3063 /* on older cards we have to enable large frames */
3064
3065 vp->large_frames = dev->mtu > 1500 || enable;
3066
3067 mac_ctrl = window_read16(vp, 3, Wn3_MAC_Ctrl);
3068 if (vp->large_frames)
3069 mac_ctrl |= 0x40;
3070 else
3071 mac_ctrl &= ~0x40;
3072 window_write16(vp, mac_ctrl, 3, Wn3_MAC_Ctrl);
3073 }
3074}
3075#else
3076
3077static void set_8021q_mode(struct net_device *dev, int enable)
3078{
3079}
3080
3081
3082#endif
3083
3084/* MII transceiver control section.
3085 Read and write the MII registers using software-generated serial
3086 MDIO protocol. See the MII specifications or DP83840A data sheet
3087 for details. */
3088
3089/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3090 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3091 "overclocking" issues. */
3092static void mdio_delay(struct vortex_private *vp)
3093{
3094 window_read32(vp, 4, Wn4_PhysicalMgmt);
3095}
3096
3097#define MDIO_SHIFT_CLK 0x01
3098#define MDIO_DIR_WRITE 0x04
3099#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3100#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3101#define MDIO_DATA_READ 0x02
3102#define MDIO_ENB_IN 0x00
3103
3104/* Generate the preamble required for initial synchronization and
3105 a few older transceivers. */
3106static void mdio_sync(struct vortex_private *vp, int bits)
3107{
3108 /* Establish sync by sending at least 32 logic ones. */
3109 while (-- bits >= 0) {
3110 window_write16(vp, MDIO_DATA_WRITE1, 4, Wn4_PhysicalMgmt);
3111 mdio_delay(vp);
3112 window_write16(vp, MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK,
3113 4, Wn4_PhysicalMgmt);
3114 mdio_delay(vp);
3115 }
3116}
3117
3118static int mdio_read(struct net_device *dev, int phy_id, int location)
3119{
3120 int i;
3121 struct vortex_private *vp = netdev_priv(dev);
3122 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3123 unsigned int retval = 0;
3124
3125 spin_lock_bh(&vp->mii_lock);
3126
3127 if (mii_preamble_required)
3128 mdio_sync(vp, 32);
3129
3130 /* Shift the read command bits out. */
3131 for (i = 14; i >= 0; i--) {
3132 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3133 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3134 mdio_delay(vp);
3135 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3136 4, Wn4_PhysicalMgmt);
3137 mdio_delay(vp);
3138 }
3139 /* Read the two transition, 16 data, and wire-idle bits. */
3140 for (i = 19; i > 0; i--) {
3141 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3142 mdio_delay(vp);
3143 retval = (retval << 1) |
3144 ((window_read16(vp, 4, Wn4_PhysicalMgmt) &
3145 MDIO_DATA_READ) ? 1 : 0);
3146 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3147 4, Wn4_PhysicalMgmt);
3148 mdio_delay(vp);
3149 }
3150
3151 spin_unlock_bh(&vp->mii_lock);
3152
3153 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3154}
3155
3156static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3157{
3158 struct vortex_private *vp = netdev_priv(dev);
3159 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
3160 int i;
3161
3162 spin_lock_bh(&vp->mii_lock);
3163
3164 if (mii_preamble_required)
3165 mdio_sync(vp, 32);
3166
3167 /* Shift the command bits out. */
3168 for (i = 31; i >= 0; i--) {
3169 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3170 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3171 mdio_delay(vp);
3172 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3173 4, Wn4_PhysicalMgmt);
3174 mdio_delay(vp);
3175 }
3176 /* Leave the interface idle. */
3177 for (i = 1; i >= 0; i--) {
3178 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3179 mdio_delay(vp);
3180 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3181 4, Wn4_PhysicalMgmt);
3182 mdio_delay(vp);
3183 }
3184
3185 spin_unlock_bh(&vp->mii_lock);
3186}
3187
3188/* ACPI: Advanced Configuration and Power Interface. */
3189/* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3190static void acpi_set_WOL(struct net_device *dev)
3191{
3192 struct vortex_private *vp = netdev_priv(dev);
3193 void __iomem *ioaddr = vp->ioaddr;
3194
3195 device_set_wakeup_enable(vp->gendev, vp->enable_wol);
3196
3197 if (vp->enable_wol) {
3198 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3199 window_write16(vp, 2, 7, 0x0c);
3200 /* The RxFilter must accept the WOL frames. */
3201 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3202 iowrite16(RxEnable, ioaddr + EL3_CMD);
3203
3204 if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
3205 pr_info("%s: WOL not supported.\n", pci_name(VORTEX_PCI(vp)));
3206
3207 vp->enable_wol = 0;
3208 return;
3209 }
3210
3211 if (VORTEX_PCI(vp)->current_state < PCI_D3hot)
3212 return;
3213
3214 /* Change the power state to D3; RxEnable doesn't take effect. */
3215 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
3216 }
3217}
3218
3219
3220static void __devexit vortex_remove_one(struct pci_dev *pdev)
3221{
3222 struct net_device *dev = pci_get_drvdata(pdev);
3223 struct vortex_private *vp;
3224
3225 if (!dev) {
3226 pr_err("vortex_remove_one called for Compaq device!\n");
3227 BUG();
3228 }
3229
3230 vp = netdev_priv(dev);
3231
3232 if (vp->cb_fn_base)
3233 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3234
3235 unregister_netdev(dev);
3236
3237 if (VORTEX_PCI(vp)) {
3238 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3239 if (vp->pm_state_valid)
3240 pci_restore_state(VORTEX_PCI(vp));
3241 pci_disable_device(VORTEX_PCI(vp));
3242 }
3243 /* Should really use issue_and_wait() here */
3244 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3245 vp->ioaddr + EL3_CMD);
3246
3247 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
3248
3249 pci_free_consistent(pdev,
3250 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3251 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3252 vp->rx_ring,
3253 vp->rx_ring_dma);
3254 if (vp->must_free_region)
3255 release_region(dev->base_addr, vp->io_size);
3256 free_netdev(dev);
3257}
3258
3259
3260static struct pci_driver vortex_driver = {
3261 .name = "3c59x",
3262 .probe = vortex_init_one,
3263 .remove = __devexit_p(vortex_remove_one),
3264 .id_table = vortex_pci_tbl,
3265 .driver.pm = VORTEX_PM_OPS,
3266};
3267
3268
3269static int vortex_have_pci;
3270static int vortex_have_eisa;
3271
3272
3273static int __init vortex_init(void)
3274{
3275 int pci_rc, eisa_rc;
3276
3277 pci_rc = pci_register_driver(&vortex_driver);
3278 eisa_rc = vortex_eisa_init();
3279
3280 if (pci_rc == 0)
3281 vortex_have_pci = 1;
3282 if (eisa_rc > 0)
3283 vortex_have_eisa = 1;
3284
3285 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3286}
3287
3288
3289static void __exit vortex_eisa_cleanup(void)
3290{
3291 struct vortex_private *vp;
3292 void __iomem *ioaddr;
3293
3294#ifdef CONFIG_EISA
3295 /* Take care of the EISA devices */
3296 eisa_driver_unregister(&vortex_eisa_driver);
3297#endif
3298
3299 if (compaq_net_device) {
3300 vp = netdev_priv(compaq_net_device);
3301 ioaddr = ioport_map(compaq_net_device->base_addr,
3302 VORTEX_TOTAL_SIZE);
3303
3304 unregister_netdev(compaq_net_device);
3305 iowrite16(TotalReset, ioaddr + EL3_CMD);
3306 release_region(compaq_net_device->base_addr,
3307 VORTEX_TOTAL_SIZE);
3308
3309 free_netdev(compaq_net_device);
3310 }
3311}
3312
3313
3314static void __exit vortex_cleanup(void)
3315{
3316 if (vortex_have_pci)
3317 pci_unregister_driver(&vortex_driver);
3318 if (vortex_have_eisa)
3319 vortex_eisa_cleanup();
3320}
3321
3322
3323module_init(vortex_init);
3324module_exit(vortex_cleanup);
Linux kernel - Deliverables
This page took 0.051303 seconds and 5 git commands to generate.