| 1 | /* |
| 2 | * Copyright (c) 2011 Broadcom Corporation |
| 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
| 5 | * purpose with or without fee is hereby granted, provided that the above |
| 6 | * copyright notice and this permission notice appear in all copies. |
| 7 | * |
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
| 11 | * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION |
| 13 | * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN |
| 14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | */ |
| 16 | /* ***** SDIO interface chip backplane handle functions ***** */ |
| 17 | |
| 18 | #include <linux/types.h> |
| 19 | #include <linux/netdevice.h> |
| 20 | #include <linux/mmc/card.h> |
| 21 | #include <linux/ssb/ssb_regs.h> |
| 22 | #include <linux/bcma/bcma.h> |
| 23 | |
| 24 | #include <chipcommon.h> |
| 25 | #include <brcm_hw_ids.h> |
| 26 | #include <brcmu_wifi.h> |
| 27 | #include <brcmu_utils.h> |
| 28 | #include <soc.h> |
| 29 | #include "dhd_dbg.h" |
| 30 | #include "sdio_host.h" |
| 31 | #include "sdio_chip.h" |
| 32 | |
| 33 | /* chip core base & ramsize */ |
| 34 | /* bcm4329 */ |
| 35 | /* SDIO device core, ID 0x829 */ |
| 36 | #define BCM4329_CORE_BUS_BASE 0x18011000 |
| 37 | /* internal memory core, ID 0x80e */ |
| 38 | #define BCM4329_CORE_SOCRAM_BASE 0x18003000 |
| 39 | /* ARM Cortex M3 core, ID 0x82a */ |
| 40 | #define BCM4329_CORE_ARM_BASE 0x18002000 |
| 41 | #define BCM4329_RAMSIZE 0x48000 |
| 42 | |
| 43 | #define SBCOREREV(sbidh) \ |
| 44 | ((((sbidh) & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT) | \ |
| 45 | ((sbidh) & SSB_IDHIGH_RCLO)) |
| 46 | |
| 47 | /* SOC Interconnect types (aka chip types) */ |
| 48 | #define SOCI_SB 0 |
| 49 | #define SOCI_AI 1 |
| 50 | |
| 51 | /* EROM CompIdentB */ |
| 52 | #define CIB_REV_MASK 0xff000000 |
| 53 | #define CIB_REV_SHIFT 24 |
| 54 | |
| 55 | #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu)) |
| 56 | /* SDIO Pad drive strength to select value mappings */ |
| 57 | struct sdiod_drive_str { |
| 58 | u8 strength; /* Pad Drive Strength in mA */ |
| 59 | u8 sel; /* Chip-specific select value */ |
| 60 | }; |
| 61 | /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */ |
| 62 | static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = { |
| 63 | {32, 0x6}, |
| 64 | {26, 0x7}, |
| 65 | {22, 0x4}, |
| 66 | {16, 0x5}, |
| 67 | {12, 0x2}, |
| 68 | {8, 0x3}, |
| 69 | {4, 0x0}, |
| 70 | {0, 0x1} |
| 71 | }; |
| 72 | |
| 73 | u8 |
| 74 | brcmf_sdio_chip_getinfidx(struct chip_info *ci, u16 coreid) |
| 75 | { |
| 76 | u8 idx; |
| 77 | |
| 78 | for (idx = 0; idx < BRCMF_MAX_CORENUM; idx++) |
| 79 | if (coreid == ci->c_inf[idx].id) |
| 80 | return idx; |
| 81 | |
| 82 | return BRCMF_MAX_CORENUM; |
| 83 | } |
| 84 | |
| 85 | static u32 |
| 86 | brcmf_sdio_sb_corerev(struct brcmf_sdio_dev *sdiodev, |
| 87 | struct chip_info *ci, u16 coreid) |
| 88 | { |
| 89 | u32 regdata; |
| 90 | u8 idx; |
| 91 | |
| 92 | idx = brcmf_sdio_chip_getinfidx(ci, coreid); |
| 93 | |
| 94 | regdata = brcmf_sdio_regrl(sdiodev, |
| 95 | CORE_SB(ci->c_inf[idx].base, sbidhigh), |
| 96 | NULL); |
| 97 | return SBCOREREV(regdata); |
| 98 | } |
| 99 | |
| 100 | static u32 |
| 101 | brcmf_sdio_ai_corerev(struct brcmf_sdio_dev *sdiodev, |
| 102 | struct chip_info *ci, u16 coreid) |
| 103 | { |
| 104 | u8 idx; |
| 105 | |
| 106 | idx = brcmf_sdio_chip_getinfidx(ci, coreid); |
| 107 | |
| 108 | return (ci->c_inf[idx].cib & CIB_REV_MASK) >> CIB_REV_SHIFT; |
| 109 | } |
| 110 | |
| 111 | static bool |
| 112 | brcmf_sdio_sb_iscoreup(struct brcmf_sdio_dev *sdiodev, |
| 113 | struct chip_info *ci, u16 coreid) |
| 114 | { |
| 115 | u32 regdata; |
| 116 | u8 idx; |
| 117 | |
| 118 | idx = brcmf_sdio_chip_getinfidx(ci, coreid); |
| 119 | |
| 120 | regdata = brcmf_sdio_regrl(sdiodev, |
| 121 | CORE_SB(ci->c_inf[idx].base, sbtmstatelow), |
| 122 | NULL); |
| 123 | regdata &= (SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT | |
| 124 | SSB_IMSTATE_REJECT | SSB_TMSLOW_CLOCK); |
| 125 | return (SSB_TMSLOW_CLOCK == regdata); |
| 126 | } |
| 127 | |
| 128 | static bool |
| 129 | brcmf_sdio_ai_iscoreup(struct brcmf_sdio_dev *sdiodev, |
| 130 | struct chip_info *ci, u16 coreid) |
| 131 | { |
| 132 | u32 regdata; |
| 133 | u8 idx; |
| 134 | bool ret; |
| 135 | |
| 136 | idx = brcmf_sdio_chip_getinfidx(ci, coreid); |
| 137 | |
| 138 | regdata = brcmf_sdio_regrl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL, |
| 139 | NULL); |
| 140 | ret = (regdata & (BCMA_IOCTL_FGC | BCMA_IOCTL_CLK)) == BCMA_IOCTL_CLK; |
| 141 | |
| 142 | regdata = brcmf_sdio_regrl(sdiodev, |
| 143 | ci->c_inf[idx].wrapbase+BCMA_RESET_CTL, |
| 144 | NULL); |
| 145 | ret = ret && ((regdata & BCMA_RESET_CTL_RESET) == 0); |
| 146 | |
| 147 | return ret; |
| 148 | } |
| 149 | |
| 150 | static void |
| 151 | brcmf_sdio_sb_coredisable(struct brcmf_sdio_dev *sdiodev, |
| 152 | struct chip_info *ci, u16 coreid) |
| 153 | { |
| 154 | u32 regdata, base; |
| 155 | u8 idx; |
| 156 | |
| 157 | idx = brcmf_sdio_chip_getinfidx(ci, coreid); |
| 158 | base = ci->c_inf[idx].base; |
| 159 | |
| 160 | regdata = brcmf_sdio_regrl(sdiodev, CORE_SB(base, sbtmstatelow), NULL); |
| 161 | if (regdata & SSB_TMSLOW_RESET) |
| 162 | return; |
| 163 | |
| 164 | regdata = brcmf_sdio_regrl(sdiodev, CORE_SB(base, sbtmstatelow), NULL); |
| 165 | if ((regdata & SSB_TMSLOW_CLOCK) != 0) { |
| 166 | /* |
| 167 | * set target reject and spin until busy is clear |
| 168 | * (preserve core-specific bits) |
| 169 | */ |
| 170 | regdata = brcmf_sdio_regrl(sdiodev, CORE_SB(base, sbtmstatelow), |
| 171 | NULL); |
| 172 | brcmf_sdio_regwl(sdiodev, CORE_SB(base, sbtmstatelow), |
| 173 | regdata | SSB_TMSLOW_REJECT, NULL); |
| 174 | |
| 175 | regdata = brcmf_sdio_regrl(sdiodev, CORE_SB(base, sbtmstatelow), |
| 176 | NULL); |
| 177 | udelay(1); |
| 178 | SPINWAIT((brcmf_sdio_regrl(sdiodev, |
| 179 | CORE_SB(base, sbtmstatehigh), |
| 180 | NULL) & |
| 181 | SSB_TMSHIGH_BUSY), 100000); |
| 182 | |
| 183 | regdata = brcmf_sdio_regrl(sdiodev, |
| 184 | CORE_SB(base, sbtmstatehigh), |
| 185 | NULL); |
| 186 | if (regdata & SSB_TMSHIGH_BUSY) |
| 187 | brcmf_err("core state still busy\n"); |
| 188 | |
| 189 | regdata = brcmf_sdio_regrl(sdiodev, CORE_SB(base, sbidlow), |
| 190 | NULL); |
| 191 | if (regdata & SSB_IDLOW_INITIATOR) { |
| 192 | regdata = brcmf_sdio_regrl(sdiodev, |
| 193 | CORE_SB(base, sbimstate), |
| 194 | NULL); |
| 195 | regdata |= SSB_IMSTATE_REJECT; |
| 196 | brcmf_sdio_regwl(sdiodev, CORE_SB(base, sbimstate), |
| 197 | regdata, NULL); |
| 198 | regdata = brcmf_sdio_regrl(sdiodev, |
| 199 | CORE_SB(base, sbimstate), |
| 200 | NULL); |
| 201 | udelay(1); |
| 202 | SPINWAIT((brcmf_sdio_regrl(sdiodev, |
| 203 | CORE_SB(base, sbimstate), |
| 204 | NULL) & |
| 205 | SSB_IMSTATE_BUSY), 100000); |
| 206 | } |
| 207 | |
| 208 | /* set reset and reject while enabling the clocks */ |
| 209 | regdata = SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | |
| 210 | SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET; |
| 211 | brcmf_sdio_regwl(sdiodev, CORE_SB(base, sbtmstatelow), |
| 212 | regdata, NULL); |
| 213 | regdata = brcmf_sdio_regrl(sdiodev, CORE_SB(base, sbtmstatelow), |
| 214 | NULL); |
| 215 | udelay(10); |
| 216 | |
| 217 | /* clear the initiator reject bit */ |
| 218 | regdata = brcmf_sdio_regrl(sdiodev, CORE_SB(base, sbidlow), |
| 219 | NULL); |
| 220 | if (regdata & SSB_IDLOW_INITIATOR) { |
| 221 | regdata = brcmf_sdio_regrl(sdiodev, |
| 222 | CORE_SB(base, sbimstate), |
| 223 | NULL); |
| 224 | regdata &= ~SSB_IMSTATE_REJECT; |
| 225 | brcmf_sdio_regwl(sdiodev, CORE_SB(base, sbimstate), |
| 226 | regdata, NULL); |
| 227 | } |
| 228 | } |
| 229 | |
| 230 | /* leave reset and reject asserted */ |
| 231 | brcmf_sdio_regwl(sdiodev, CORE_SB(base, sbtmstatelow), |
| 232 | (SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET), NULL); |
| 233 | udelay(1); |
| 234 | } |
| 235 | |
| 236 | static void |
| 237 | brcmf_sdio_ai_coredisable(struct brcmf_sdio_dev *sdiodev, |
| 238 | struct chip_info *ci, u16 coreid) |
| 239 | { |
| 240 | u8 idx; |
| 241 | u32 regdata; |
| 242 | |
| 243 | idx = brcmf_sdio_chip_getinfidx(ci, coreid); |
| 244 | |
| 245 | /* if core is already in reset, just return */ |
| 246 | regdata = brcmf_sdio_regrl(sdiodev, |
| 247 | ci->c_inf[idx].wrapbase+BCMA_RESET_CTL, |
| 248 | NULL); |
| 249 | if ((regdata & BCMA_RESET_CTL_RESET) != 0) |
| 250 | return; |
| 251 | |
| 252 | brcmf_sdio_regwl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL, 0, NULL); |
| 253 | regdata = brcmf_sdio_regrl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL, |
| 254 | NULL); |
| 255 | udelay(10); |
| 256 | |
| 257 | brcmf_sdio_regwl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_RESET_CTL, |
| 258 | BCMA_RESET_CTL_RESET, NULL); |
| 259 | udelay(1); |
| 260 | } |
| 261 | |
| 262 | static void |
| 263 | brcmf_sdio_sb_resetcore(struct brcmf_sdio_dev *sdiodev, |
| 264 | struct chip_info *ci, u16 coreid) |
| 265 | { |
| 266 | u32 regdata; |
| 267 | u8 idx; |
| 268 | |
| 269 | idx = brcmf_sdio_chip_getinfidx(ci, coreid); |
| 270 | |
| 271 | /* |
| 272 | * Must do the disable sequence first to work for |
| 273 | * arbitrary current core state. |
| 274 | */ |
| 275 | brcmf_sdio_sb_coredisable(sdiodev, ci, coreid); |
| 276 | |
| 277 | /* |
| 278 | * Now do the initialization sequence. |
| 279 | * set reset while enabling the clock and |
| 280 | * forcing them on throughout the core |
| 281 | */ |
| 282 | brcmf_sdio_regwl(sdiodev, |
| 283 | CORE_SB(ci->c_inf[idx].base, sbtmstatelow), |
| 284 | SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET, |
| 285 | NULL); |
| 286 | regdata = brcmf_sdio_regrl(sdiodev, |
| 287 | CORE_SB(ci->c_inf[idx].base, sbtmstatelow), |
| 288 | NULL); |
| 289 | udelay(1); |
| 290 | |
| 291 | /* clear any serror */ |
| 292 | regdata = brcmf_sdio_regrl(sdiodev, |
| 293 | CORE_SB(ci->c_inf[idx].base, sbtmstatehigh), |
| 294 | NULL); |
| 295 | if (regdata & SSB_TMSHIGH_SERR) |
| 296 | brcmf_sdio_regwl(sdiodev, |
| 297 | CORE_SB(ci->c_inf[idx].base, sbtmstatehigh), |
| 298 | 0, NULL); |
| 299 | |
| 300 | regdata = brcmf_sdio_regrl(sdiodev, |
| 301 | CORE_SB(ci->c_inf[idx].base, sbimstate), |
| 302 | NULL); |
| 303 | if (regdata & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) |
| 304 | brcmf_sdio_regwl(sdiodev, |
| 305 | CORE_SB(ci->c_inf[idx].base, sbimstate), |
| 306 | regdata & ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO), |
| 307 | NULL); |
| 308 | |
| 309 | /* clear reset and allow it to propagate throughout the core */ |
| 310 | brcmf_sdio_regwl(sdiodev, CORE_SB(ci->c_inf[idx].base, sbtmstatelow), |
| 311 | SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK, NULL); |
| 312 | regdata = brcmf_sdio_regrl(sdiodev, |
| 313 | CORE_SB(ci->c_inf[idx].base, sbtmstatelow), |
| 314 | NULL); |
| 315 | udelay(1); |
| 316 | |
| 317 | /* leave clock enabled */ |
| 318 | brcmf_sdio_regwl(sdiodev, CORE_SB(ci->c_inf[idx].base, sbtmstatelow), |
| 319 | SSB_TMSLOW_CLOCK, NULL); |
| 320 | regdata = brcmf_sdio_regrl(sdiodev, |
| 321 | CORE_SB(ci->c_inf[idx].base, sbtmstatelow), |
| 322 | NULL); |
| 323 | udelay(1); |
| 324 | } |
| 325 | |
| 326 | static void |
| 327 | brcmf_sdio_ai_resetcore(struct brcmf_sdio_dev *sdiodev, |
| 328 | struct chip_info *ci, u16 coreid) |
| 329 | { |
| 330 | u8 idx; |
| 331 | u32 regdata; |
| 332 | |
| 333 | idx = brcmf_sdio_chip_getinfidx(ci, coreid); |
| 334 | |
| 335 | /* must disable first to work for arbitrary current core state */ |
| 336 | brcmf_sdio_ai_coredisable(sdiodev, ci, coreid); |
| 337 | |
| 338 | /* now do initialization sequence */ |
| 339 | brcmf_sdio_regwl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL, |
| 340 | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK, NULL); |
| 341 | regdata = brcmf_sdio_regrl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL, |
| 342 | NULL); |
| 343 | brcmf_sdio_regwl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_RESET_CTL, |
| 344 | 0, NULL); |
| 345 | udelay(1); |
| 346 | |
| 347 | brcmf_sdio_regwl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL, |
| 348 | BCMA_IOCTL_CLK, NULL); |
| 349 | regdata = brcmf_sdio_regrl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL, |
| 350 | NULL); |
| 351 | udelay(1); |
| 352 | } |
| 353 | |
| 354 | static int brcmf_sdio_chip_recognition(struct brcmf_sdio_dev *sdiodev, |
| 355 | struct chip_info *ci, u32 regs) |
| 356 | { |
| 357 | u32 regdata; |
| 358 | |
| 359 | /* |
| 360 | * Get CC core rev |
| 361 | * Chipid is assume to be at offset 0 from regs arg |
| 362 | * For different chiptypes or old sdio hosts w/o chipcommon, |
| 363 | * other ways of recognition should be added here. |
| 364 | */ |
| 365 | ci->c_inf[0].id = BCMA_CORE_CHIPCOMMON; |
| 366 | ci->c_inf[0].base = regs; |
| 367 | regdata = brcmf_sdio_regrl(sdiodev, |
| 368 | CORE_CC_REG(ci->c_inf[0].base, chipid), |
| 369 | NULL); |
| 370 | ci->chip = regdata & CID_ID_MASK; |
| 371 | ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT; |
| 372 | ci->socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT; |
| 373 | |
| 374 | brcmf_dbg(INFO, "chipid=0x%x chiprev=%d\n", ci->chip, ci->chiprev); |
| 375 | |
| 376 | /* Address of cores for new chips should be added here */ |
| 377 | switch (ci->chip) { |
| 378 | case BCM43241_CHIP_ID: |
| 379 | ci->c_inf[0].wrapbase = 0x18100000; |
| 380 | ci->c_inf[0].cib = 0x2a084411; |
| 381 | ci->c_inf[1].id = BCMA_CORE_SDIO_DEV; |
| 382 | ci->c_inf[1].base = 0x18002000; |
| 383 | ci->c_inf[1].wrapbase = 0x18102000; |
| 384 | ci->c_inf[1].cib = 0x0e004211; |
| 385 | ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM; |
| 386 | ci->c_inf[2].base = 0x18004000; |
| 387 | ci->c_inf[2].wrapbase = 0x18104000; |
| 388 | ci->c_inf[2].cib = 0x14080401; |
| 389 | ci->c_inf[3].id = BCMA_CORE_ARM_CM3; |
| 390 | ci->c_inf[3].base = 0x18003000; |
| 391 | ci->c_inf[3].wrapbase = 0x18103000; |
| 392 | ci->c_inf[3].cib = 0x07004211; |
| 393 | ci->ramsize = 0x90000; |
| 394 | break; |
| 395 | case BCM4329_CHIP_ID: |
| 396 | ci->c_inf[1].id = BCMA_CORE_SDIO_DEV; |
| 397 | ci->c_inf[1].base = BCM4329_CORE_BUS_BASE; |
| 398 | ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM; |
| 399 | ci->c_inf[2].base = BCM4329_CORE_SOCRAM_BASE; |
| 400 | ci->c_inf[3].id = BCMA_CORE_ARM_CM3; |
| 401 | ci->c_inf[3].base = BCM4329_CORE_ARM_BASE; |
| 402 | ci->ramsize = BCM4329_RAMSIZE; |
| 403 | break; |
| 404 | case BCM4330_CHIP_ID: |
| 405 | ci->c_inf[0].wrapbase = 0x18100000; |
| 406 | ci->c_inf[0].cib = 0x27004211; |
| 407 | ci->c_inf[1].id = BCMA_CORE_SDIO_DEV; |
| 408 | ci->c_inf[1].base = 0x18002000; |
| 409 | ci->c_inf[1].wrapbase = 0x18102000; |
| 410 | ci->c_inf[1].cib = 0x07004211; |
| 411 | ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM; |
| 412 | ci->c_inf[2].base = 0x18004000; |
| 413 | ci->c_inf[2].wrapbase = 0x18104000; |
| 414 | ci->c_inf[2].cib = 0x0d080401; |
| 415 | ci->c_inf[3].id = BCMA_CORE_ARM_CM3; |
| 416 | ci->c_inf[3].base = 0x18003000; |
| 417 | ci->c_inf[3].wrapbase = 0x18103000; |
| 418 | ci->c_inf[3].cib = 0x03004211; |
| 419 | ci->ramsize = 0x48000; |
| 420 | break; |
| 421 | case BCM4334_CHIP_ID: |
| 422 | ci->c_inf[0].wrapbase = 0x18100000; |
| 423 | ci->c_inf[0].cib = 0x29004211; |
| 424 | ci->c_inf[1].id = BCMA_CORE_SDIO_DEV; |
| 425 | ci->c_inf[1].base = 0x18002000; |
| 426 | ci->c_inf[1].wrapbase = 0x18102000; |
| 427 | ci->c_inf[1].cib = 0x0d004211; |
| 428 | ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM; |
| 429 | ci->c_inf[2].base = 0x18004000; |
| 430 | ci->c_inf[2].wrapbase = 0x18104000; |
| 431 | ci->c_inf[2].cib = 0x13080401; |
| 432 | ci->c_inf[3].id = BCMA_CORE_ARM_CM3; |
| 433 | ci->c_inf[3].base = 0x18003000; |
| 434 | ci->c_inf[3].wrapbase = 0x18103000; |
| 435 | ci->c_inf[3].cib = 0x07004211; |
| 436 | ci->ramsize = 0x80000; |
| 437 | break; |
| 438 | default: |
| 439 | brcmf_err("chipid 0x%x is not supported\n", ci->chip); |
| 440 | return -ENODEV; |
| 441 | } |
| 442 | |
| 443 | switch (ci->socitype) { |
| 444 | case SOCI_SB: |
| 445 | ci->iscoreup = brcmf_sdio_sb_iscoreup; |
| 446 | ci->corerev = brcmf_sdio_sb_corerev; |
| 447 | ci->coredisable = brcmf_sdio_sb_coredisable; |
| 448 | ci->resetcore = brcmf_sdio_sb_resetcore; |
| 449 | break; |
| 450 | case SOCI_AI: |
| 451 | ci->iscoreup = brcmf_sdio_ai_iscoreup; |
| 452 | ci->corerev = brcmf_sdio_ai_corerev; |
| 453 | ci->coredisable = brcmf_sdio_ai_coredisable; |
| 454 | ci->resetcore = brcmf_sdio_ai_resetcore; |
| 455 | break; |
| 456 | default: |
| 457 | brcmf_err("socitype %u not supported\n", ci->socitype); |
| 458 | return -ENODEV; |
| 459 | } |
| 460 | |
| 461 | return 0; |
| 462 | } |
| 463 | |
| 464 | static int |
| 465 | brcmf_sdio_chip_buscoreprep(struct brcmf_sdio_dev *sdiodev) |
| 466 | { |
| 467 | int err = 0; |
| 468 | u8 clkval, clkset; |
| 469 | |
| 470 | /* Try forcing SDIO core to do ALPAvail request only */ |
| 471 | clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ; |
| 472 | brcmf_sdio_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); |
| 473 | if (err) { |
| 474 | brcmf_err("error writing for HT off\n"); |
| 475 | return err; |
| 476 | } |
| 477 | |
| 478 | /* If register supported, wait for ALPAvail and then force ALP */ |
| 479 | /* This may take up to 15 milliseconds */ |
| 480 | clkval = brcmf_sdio_regrb(sdiodev, |
| 481 | SBSDIO_FUNC1_CHIPCLKCSR, NULL); |
| 482 | |
| 483 | if ((clkval & ~SBSDIO_AVBITS) != clkset) { |
| 484 | brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n", |
| 485 | clkset, clkval); |
| 486 | return -EACCES; |
| 487 | } |
| 488 | |
| 489 | SPINWAIT(((clkval = brcmf_sdio_regrb(sdiodev, |
| 490 | SBSDIO_FUNC1_CHIPCLKCSR, NULL)), |
| 491 | !SBSDIO_ALPAV(clkval)), |
| 492 | PMU_MAX_TRANSITION_DLY); |
| 493 | if (!SBSDIO_ALPAV(clkval)) { |
| 494 | brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n", |
| 495 | clkval); |
| 496 | return -EBUSY; |
| 497 | } |
| 498 | |
| 499 | clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP; |
| 500 | brcmf_sdio_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); |
| 501 | udelay(65); |
| 502 | |
| 503 | /* Also, disable the extra SDIO pull-ups */ |
| 504 | brcmf_sdio_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL); |
| 505 | |
| 506 | return 0; |
| 507 | } |
| 508 | |
| 509 | static void |
| 510 | brcmf_sdio_chip_buscoresetup(struct brcmf_sdio_dev *sdiodev, |
| 511 | struct chip_info *ci) |
| 512 | { |
| 513 | u32 base = ci->c_inf[0].base; |
| 514 | |
| 515 | /* get chipcommon rev */ |
| 516 | ci->c_inf[0].rev = ci->corerev(sdiodev, ci, ci->c_inf[0].id); |
| 517 | |
| 518 | /* get chipcommon capabilites */ |
| 519 | ci->c_inf[0].caps = brcmf_sdio_regrl(sdiodev, |
| 520 | CORE_CC_REG(base, capabilities), |
| 521 | NULL); |
| 522 | |
| 523 | /* get pmu caps & rev */ |
| 524 | if (ci->c_inf[0].caps & CC_CAP_PMU) { |
| 525 | ci->pmucaps = |
| 526 | brcmf_sdio_regrl(sdiodev, |
| 527 | CORE_CC_REG(base, pmucapabilities), |
| 528 | NULL); |
| 529 | ci->pmurev = ci->pmucaps & PCAP_REV_MASK; |
| 530 | } |
| 531 | |
| 532 | ci->c_inf[1].rev = ci->corerev(sdiodev, ci, ci->c_inf[1].id); |
| 533 | |
| 534 | brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n", |
| 535 | ci->c_inf[0].rev, ci->pmurev, |
| 536 | ci->c_inf[1].rev, ci->c_inf[1].id); |
| 537 | |
| 538 | /* |
| 539 | * Make sure any on-chip ARM is off (in case strapping is wrong), |
| 540 | * or downloaded code was already running. |
| 541 | */ |
| 542 | ci->coredisable(sdiodev, ci, BCMA_CORE_ARM_CM3); |
| 543 | } |
| 544 | |
| 545 | int brcmf_sdio_chip_attach(struct brcmf_sdio_dev *sdiodev, |
| 546 | struct chip_info **ci_ptr, u32 regs) |
| 547 | { |
| 548 | int ret; |
| 549 | struct chip_info *ci; |
| 550 | |
| 551 | brcmf_dbg(TRACE, "Enter\n"); |
| 552 | |
| 553 | /* alloc chip_info_t */ |
| 554 | ci = kzalloc(sizeof(struct chip_info), GFP_ATOMIC); |
| 555 | if (!ci) |
| 556 | return -ENOMEM; |
| 557 | |
| 558 | ret = brcmf_sdio_chip_buscoreprep(sdiodev); |
| 559 | if (ret != 0) |
| 560 | goto err; |
| 561 | |
| 562 | ret = brcmf_sdio_chip_recognition(sdiodev, ci, regs); |
| 563 | if (ret != 0) |
| 564 | goto err; |
| 565 | |
| 566 | brcmf_sdio_chip_buscoresetup(sdiodev, ci); |
| 567 | |
| 568 | brcmf_sdio_regwl(sdiodev, CORE_CC_REG(ci->c_inf[0].base, gpiopullup), |
| 569 | 0, NULL); |
| 570 | brcmf_sdio_regwl(sdiodev, CORE_CC_REG(ci->c_inf[0].base, gpiopulldown), |
| 571 | 0, NULL); |
| 572 | |
| 573 | *ci_ptr = ci; |
| 574 | return 0; |
| 575 | |
| 576 | err: |
| 577 | kfree(ci); |
| 578 | return ret; |
| 579 | } |
| 580 | |
| 581 | void |
| 582 | brcmf_sdio_chip_detach(struct chip_info **ci_ptr) |
| 583 | { |
| 584 | brcmf_dbg(TRACE, "Enter\n"); |
| 585 | |
| 586 | kfree(*ci_ptr); |
| 587 | *ci_ptr = NULL; |
| 588 | } |
| 589 | |
| 590 | static char *brcmf_sdio_chip_name(uint chipid, char *buf, uint len) |
| 591 | { |
| 592 | const char *fmt; |
| 593 | |
| 594 | fmt = ((chipid > 0xa000) || (chipid < 0x4000)) ? "%d" : "%x"; |
| 595 | snprintf(buf, len, fmt, chipid); |
| 596 | return buf; |
| 597 | } |
| 598 | |
| 599 | void |
| 600 | brcmf_sdio_chip_drivestrengthinit(struct brcmf_sdio_dev *sdiodev, |
| 601 | struct chip_info *ci, u32 drivestrength) |
| 602 | { |
| 603 | struct sdiod_drive_str *str_tab = NULL; |
| 604 | u32 str_mask = 0; |
| 605 | u32 str_shift = 0; |
| 606 | char chn[8]; |
| 607 | u32 base = ci->c_inf[0].base; |
| 608 | |
| 609 | if (!(ci->c_inf[0].caps & CC_CAP_PMU)) |
| 610 | return; |
| 611 | |
| 612 | switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) { |
| 613 | case SDIOD_DRVSTR_KEY(BCM4330_CHIP_ID, 12): |
| 614 | str_tab = (struct sdiod_drive_str *)&sdiod_drvstr_tab1_1v8; |
| 615 | str_mask = 0x00003800; |
| 616 | str_shift = 11; |
| 617 | break; |
| 618 | default: |
| 619 | brcmf_err("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n", |
| 620 | brcmf_sdio_chip_name(ci->chip, chn, 8), |
| 621 | ci->chiprev, ci->pmurev); |
| 622 | break; |
| 623 | } |
| 624 | |
| 625 | if (str_tab != NULL) { |
| 626 | u32 drivestrength_sel = 0; |
| 627 | u32 cc_data_temp; |
| 628 | int i; |
| 629 | |
| 630 | for (i = 0; str_tab[i].strength != 0; i++) { |
| 631 | if (drivestrength >= str_tab[i].strength) { |
| 632 | drivestrength_sel = str_tab[i].sel; |
| 633 | break; |
| 634 | } |
| 635 | } |
| 636 | |
| 637 | brcmf_sdio_regwl(sdiodev, CORE_CC_REG(base, chipcontrol_addr), |
| 638 | 1, NULL); |
| 639 | cc_data_temp = |
| 640 | brcmf_sdio_regrl(sdiodev, |
| 641 | CORE_CC_REG(base, chipcontrol_addr), |
| 642 | NULL); |
| 643 | cc_data_temp &= ~str_mask; |
| 644 | drivestrength_sel <<= str_shift; |
| 645 | cc_data_temp |= drivestrength_sel; |
| 646 | brcmf_sdio_regwl(sdiodev, CORE_CC_REG(base, chipcontrol_addr), |
| 647 | cc_data_temp, NULL); |
| 648 | |
| 649 | brcmf_dbg(INFO, "SDIO: %dmA drive strength selected, set to 0x%08x\n", |
| 650 | drivestrength, cc_data_temp); |
| 651 | } |
| 652 | } |