| 1 | /****************************************************************************** |
| 2 | * |
| 3 | * This file is provided under a dual BSD/GPLv2 license. When using or |
| 4 | * redistributing this file, you may do so under either license. |
| 5 | * |
| 6 | * GPL LICENSE SUMMARY |
| 7 | * |
| 8 | * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of version 2 of the GNU General Public License as |
| 12 | * published by the Free Software Foundation. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, but |
| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 17 | * General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, |
| 22 | * USA |
| 23 | * |
| 24 | * The full GNU General Public License is included in this distribution |
| 25 | * in the file called LICENSE.GPL. |
| 26 | * |
| 27 | * Contact Information: |
| 28 | * James P. Ketrenos <ipw2100-admin@linux.intel.com> |
| 29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 30 | * |
| 31 | * BSD LICENSE |
| 32 | * |
| 33 | * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved. |
| 34 | * All rights reserved. |
| 35 | * |
| 36 | * Redistribution and use in source and binary forms, with or without |
| 37 | * modification, are permitted provided that the following conditions |
| 38 | * are met: |
| 39 | * |
| 40 | * * Redistributions of source code must retain the above copyright |
| 41 | * notice, this list of conditions and the following disclaimer. |
| 42 | * * Redistributions in binary form must reproduce the above copyright |
| 43 | * notice, this list of conditions and the following disclaimer in |
| 44 | * the documentation and/or other materials provided with the |
| 45 | * distribution. |
| 46 | * * Neither the name Intel Corporation nor the names of its |
| 47 | * contributors may be used to endorse or promote products derived |
| 48 | * from this software without specific prior written permission. |
| 49 | * |
| 50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 61 | * |
| 62 | *****************************************************************************/ |
| 63 | /* |
| 64 | * Please use this file (iwl-4965-hw.h) only for hardware-related definitions. |
| 65 | * Use iwl-4965-commands.h for uCode API definitions. |
| 66 | * Use iwl-4965.h for driver implementation definitions. |
| 67 | */ |
| 68 | |
| 69 | #ifndef __iwl_4965_hw_h__ |
| 70 | #define __iwl_4965_hw_h__ |
| 71 | |
| 72 | /* |
| 73 | * uCode queue management definitions ... |
| 74 | * Queue #4 is the command queue for 3945 and 4965; map it to Tx FIFO chnl 4. |
| 75 | * The first queue used for block-ack aggregation is #7 (4965 only). |
| 76 | * All block-ack aggregation queues should map to Tx DMA/FIFO channel 7. |
| 77 | */ |
| 78 | #define IWL_CMD_QUEUE_NUM 4 |
| 79 | #define IWL_CMD_FIFO_NUM 4 |
| 80 | #define IWL_BACK_QUEUE_FIRST_ID 7 |
| 81 | |
| 82 | /* Tx rates */ |
| 83 | #define IWL_CCK_RATES 4 |
| 84 | #define IWL_OFDM_RATES 8 |
| 85 | #define IWL_HT_RATES 16 |
| 86 | #define IWL_MAX_RATES (IWL_CCK_RATES+IWL_OFDM_RATES+IWL_HT_RATES) |
| 87 | |
| 88 | /* Time constants */ |
| 89 | #define SHORT_SLOT_TIME 9 |
| 90 | #define LONG_SLOT_TIME 20 |
| 91 | |
| 92 | /* RSSI to dBm */ |
| 93 | #define IWL_RSSI_OFFSET 44 |
| 94 | |
| 95 | /* |
| 96 | * EEPROM related constants, enums, and structures. |
| 97 | */ |
| 98 | |
| 99 | /* |
| 100 | * EEPROM access time values: |
| 101 | * |
| 102 | * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG, |
| 103 | * then clearing (with subsequent read/modify/write) CSR_EEPROM_REG bit |
| 104 | * CSR_EEPROM_REG_BIT_CMD (0x2). |
| 105 | * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1). |
| 106 | * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec. |
| 107 | * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG. |
| 108 | */ |
| 109 | #define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */ |
| 110 | #define IWL_EEPROM_ACCESS_DELAY 10 /* uSec */ |
| 111 | |
| 112 | /* |
| 113 | * Regulatory channel usage flags in EEPROM struct iwl4965_eeprom_channel.flags. |
| 114 | * |
| 115 | * IBSS and/or AP operation is allowed *only* on those channels with |
| 116 | * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because |
| 117 | * RADAR detection is not supported by the 4965 driver, but is a |
| 118 | * requirement for establishing a new network for legal operation on channels |
| 119 | * requiring RADAR detection or restricting ACTIVE scanning. |
| 120 | * |
| 121 | * NOTE: "WIDE" flag does not indicate anything about "FAT" 40 MHz channels. |
| 122 | * It only indicates that 20 MHz channel use is supported; FAT channel |
| 123 | * usage is indicated by a separate set of regulatory flags for each |
| 124 | * FAT channel pair. |
| 125 | * |
| 126 | * NOTE: Using a channel inappropriately will result in a uCode error! |
| 127 | */ |
| 128 | enum { |
| 129 | EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */ |
| 130 | EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */ |
| 131 | /* Bit 2 Reserved */ |
| 132 | EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */ |
| 133 | EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */ |
| 134 | EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */ |
| 135 | EEPROM_CHANNEL_NARROW = (1 << 6), /* 10 MHz channel (not used) */ |
| 136 | EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */ |
| 137 | }; |
| 138 | |
| 139 | /* SKU Capabilities */ |
| 140 | #define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0) |
| 141 | #define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1) |
| 142 | |
| 143 | /* *regulatory* channel data format in eeprom, one for each channel. |
| 144 | * There are separate entries for FAT (40 MHz) vs. normal (20 MHz) channels. */ |
| 145 | struct iwl4965_eeprom_channel { |
| 146 | u8 flags; /* EEPROM_CHANNEL_* flags copied from EEPROM */ |
| 147 | s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */ |
| 148 | } __attribute__ ((packed)); |
| 149 | |
| 150 | /* 4965 has two radio transmitters (and 3 radio receivers) */ |
| 151 | #define EEPROM_TX_POWER_TX_CHAINS (2) |
| 152 | |
| 153 | /* 4965 has room for up to 8 sets of txpower calibration data */ |
| 154 | #define EEPROM_TX_POWER_BANDS (8) |
| 155 | |
| 156 | /* 4965 factory calibration measures txpower gain settings for |
| 157 | * each of 3 target output levels */ |
| 158 | #define EEPROM_TX_POWER_MEASUREMENTS (3) |
| 159 | |
| 160 | /* 4965 driver does not work with txpower calibration version < 5. |
| 161 | * Look for this in calib_version member of struct iwl4965_eeprom. */ |
| 162 | #define EEPROM_TX_POWER_VERSION_NEW (5) |
| 163 | |
| 164 | |
| 165 | /* |
| 166 | * 4965 factory calibration data for one txpower level, on one channel, |
| 167 | * measured on one of the 2 tx chains (radio transmitter and associated |
| 168 | * antenna). EEPROM contains: |
| 169 | * |
| 170 | * 1) Temperature (degrees Celsius) of device when measurement was made. |
| 171 | * |
| 172 | * 2) Gain table index used to achieve the target measurement power. |
| 173 | * This refers to the "well-known" gain tables (see iwl-4965-hw.h). |
| 174 | * |
| 175 | * 3) Actual measured output power, in half-dBm ("34" = 17 dBm). |
| 176 | * |
| 177 | * 4) RF power amplifier detector level measurement (not used). |
| 178 | */ |
| 179 | struct iwl4965_eeprom_calib_measure { |
| 180 | u8 temperature; /* Device temperature (Celsius) */ |
| 181 | u8 gain_idx; /* Index into gain table */ |
| 182 | u8 actual_pow; /* Measured RF output power, half-dBm */ |
| 183 | s8 pa_det; /* Power amp detector level (not used) */ |
| 184 | } __attribute__ ((packed)); |
| 185 | |
| 186 | |
| 187 | /* |
| 188 | * 4965 measurement set for one channel. EEPROM contains: |
| 189 | * |
| 190 | * 1) Channel number measured |
| 191 | * |
| 192 | * 2) Measurements for each of 3 power levels for each of 2 radio transmitters |
| 193 | * (a.k.a. "tx chains") (6 measurements altogether) |
| 194 | */ |
| 195 | struct iwl4965_eeprom_calib_ch_info { |
| 196 | u8 ch_num; |
| 197 | struct iwl4965_eeprom_calib_measure measurements[EEPROM_TX_POWER_TX_CHAINS] |
| 198 | [EEPROM_TX_POWER_MEASUREMENTS]; |
| 199 | } __attribute__ ((packed)); |
| 200 | |
| 201 | /* |
| 202 | * 4965 txpower subband info. |
| 203 | * |
| 204 | * For each frequency subband, EEPROM contains the following: |
| 205 | * |
| 206 | * 1) First and last channels within range of the subband. "0" values |
| 207 | * indicate that this sample set is not being used. |
| 208 | * |
| 209 | * 2) Sample measurement sets for 2 channels close to the range endpoints. |
| 210 | */ |
| 211 | struct iwl4965_eeprom_calib_subband_info { |
| 212 | u8 ch_from; /* channel number of lowest channel in subband */ |
| 213 | u8 ch_to; /* channel number of highest channel in subband */ |
| 214 | struct iwl4965_eeprom_calib_ch_info ch1; |
| 215 | struct iwl4965_eeprom_calib_ch_info ch2; |
| 216 | } __attribute__ ((packed)); |
| 217 | |
| 218 | |
| 219 | /* |
| 220 | * 4965 txpower calibration info. EEPROM contains: |
| 221 | * |
| 222 | * 1) Factory-measured saturation power levels (maximum levels at which |
| 223 | * tx power amplifier can output a signal without too much distortion). |
| 224 | * There is one level for 2.4 GHz band and one for 5 GHz band. These |
| 225 | * values apply to all channels within each of the bands. |
| 226 | * |
| 227 | * 2) Factory-measured power supply voltage level. This is assumed to be |
| 228 | * constant (i.e. same value applies to all channels/bands) while the |
| 229 | * factory measurements are being made. |
| 230 | * |
| 231 | * 3) Up to 8 sets of factory-measured txpower calibration values. |
| 232 | * These are for different frequency ranges, since txpower gain |
| 233 | * characteristics of the analog radio circuitry vary with frequency. |
| 234 | * |
| 235 | * Not all sets need to be filled with data; |
| 236 | * struct iwl4965_eeprom_calib_subband_info contains range of channels |
| 237 | * (0 if unused) for each set of data. |
| 238 | */ |
| 239 | struct iwl4965_eeprom_calib_info { |
| 240 | u8 saturation_power24; /* half-dBm (e.g. "34" = 17 dBm) */ |
| 241 | u8 saturation_power52; /* half-dBm */ |
| 242 | s16 voltage; /* signed */ |
| 243 | struct iwl4965_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS]; |
| 244 | } __attribute__ ((packed)); |
| 245 | |
| 246 | |
| 247 | /* |
| 248 | * 4965 EEPROM map |
| 249 | */ |
| 250 | struct iwl4965_eeprom { |
| 251 | u8 reserved0[16]; |
| 252 | #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */ |
| 253 | u16 device_id; /* abs.ofs: 16 */ |
| 254 | u8 reserved1[2]; |
| 255 | #define EEPROM_PMC (2*0x0A) /* 2 bytes */ |
| 256 | u16 pmc; /* abs.ofs: 20 */ |
| 257 | u8 reserved2[20]; |
| 258 | #define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */ |
| 259 | u8 mac_address[6]; /* abs.ofs: 42 */ |
| 260 | u8 reserved3[58]; |
| 261 | #define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */ |
| 262 | u16 board_revision; /* abs.ofs: 106 */ |
| 263 | u8 reserved4[11]; |
| 264 | #define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */ |
| 265 | u8 board_pba_number[9]; /* abs.ofs: 119 */ |
| 266 | u8 reserved5[8]; |
| 267 | #define EEPROM_VERSION (2*0x44) /* 2 bytes */ |
| 268 | u16 version; /* abs.ofs: 136 */ |
| 269 | #define EEPROM_SKU_CAP (2*0x45) /* 1 bytes */ |
| 270 | u8 sku_cap; /* abs.ofs: 138 */ |
| 271 | #define EEPROM_LEDS_MODE (2*0x45+1) /* 1 bytes */ |
| 272 | u8 leds_mode; /* abs.ofs: 139 */ |
| 273 | #define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */ |
| 274 | u16 oem_mode; |
| 275 | #define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */ |
| 276 | u16 wowlan_mode; /* abs.ofs: 142 */ |
| 277 | #define EEPROM_LEDS_TIME_INTERVAL (2*0x48) /* 2 bytes */ |
| 278 | u16 leds_time_interval; /* abs.ofs: 144 */ |
| 279 | #define EEPROM_LEDS_OFF_TIME (2*0x49) /* 1 bytes */ |
| 280 | u8 leds_off_time; /* abs.ofs: 146 */ |
| 281 | #define EEPROM_LEDS_ON_TIME (2*0x49+1) /* 1 bytes */ |
| 282 | u8 leds_on_time; /* abs.ofs: 147 */ |
| 283 | #define EEPROM_ALMGOR_M_VERSION (2*0x4A) /* 1 bytes */ |
| 284 | u8 almgor_m_version; /* abs.ofs: 148 */ |
| 285 | #define EEPROM_ANTENNA_SWITCH_TYPE (2*0x4A+1) /* 1 bytes */ |
| 286 | u8 antenna_switch_type; /* abs.ofs: 149 */ |
| 287 | u8 reserved6[8]; |
| 288 | #define EEPROM_4965_BOARD_REVISION (2*0x4F) /* 2 bytes */ |
| 289 | u16 board_revision_4965; /* abs.ofs: 158 */ |
| 290 | u8 reserved7[13]; |
| 291 | #define EEPROM_4965_BOARD_PBA (2*0x56+1) /* 9 bytes */ |
| 292 | u8 board_pba_number_4965[9]; /* abs.ofs: 173 */ |
| 293 | u8 reserved8[10]; |
| 294 | #define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */ |
| 295 | u8 sku_id[4]; /* abs.ofs: 192 */ |
| 296 | |
| 297 | /* |
| 298 | * Per-channel regulatory data. |
| 299 | * |
| 300 | * Each channel that *might* be supported by 3945 or 4965 has a fixed location |
| 301 | * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory |
| 302 | * txpower (MSB). |
| 303 | * |
| 304 | * Entries immediately below are for 20 MHz channel width. FAT (40 MHz) |
| 305 | * channels (only for 4965, not supported by 3945) appear later in the EEPROM. |
| 306 | * |
| 307 | * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 |
| 308 | */ |
| 309 | #define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */ |
| 310 | u16 band_1_count; /* abs.ofs: 196 */ |
| 311 | #define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */ |
| 312 | struct iwl4965_eeprom_channel band_1_channels[14]; /* abs.ofs: 196 */ |
| 313 | |
| 314 | /* |
| 315 | * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196, |
| 316 | * 5.0 GHz channels 7, 8, 11, 12, 16 |
| 317 | * (4915-5080MHz) (none of these is ever supported) |
| 318 | */ |
| 319 | #define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */ |
| 320 | u16 band_2_count; /* abs.ofs: 226 */ |
| 321 | #define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */ |
| 322 | struct iwl4965_eeprom_channel band_2_channels[13]; /* abs.ofs: 228 */ |
| 323 | |
| 324 | /* |
| 325 | * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 |
| 326 | * (5170-5320MHz) |
| 327 | */ |
| 328 | #define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */ |
| 329 | u16 band_3_count; /* abs.ofs: 254 */ |
| 330 | #define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */ |
| 331 | struct iwl4965_eeprom_channel band_3_channels[12]; /* abs.ofs: 256 */ |
| 332 | |
| 333 | /* |
| 334 | * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 |
| 335 | * (5500-5700MHz) |
| 336 | */ |
| 337 | #define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */ |
| 338 | u16 band_4_count; /* abs.ofs: 280 */ |
| 339 | #define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */ |
| 340 | struct iwl4965_eeprom_channel band_4_channels[11]; /* abs.ofs: 282 */ |
| 341 | |
| 342 | /* |
| 343 | * 5.7 GHz channels 145, 149, 153, 157, 161, 165 |
| 344 | * (5725-5825MHz) |
| 345 | */ |
| 346 | #define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */ |
| 347 | u16 band_5_count; /* abs.ofs: 304 */ |
| 348 | #define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */ |
| 349 | struct iwl4965_eeprom_channel band_5_channels[6]; /* abs.ofs: 306 */ |
| 350 | |
| 351 | u8 reserved10[2]; |
| 352 | |
| 353 | |
| 354 | /* |
| 355 | * 2.4 GHz FAT channels 1 (5), 2 (6), 3 (7), 4 (8), 5 (9), 6 (10), 7 (11) |
| 356 | * |
| 357 | * The channel listed is the center of the lower 20 MHz half of the channel. |
| 358 | * The overall center frequency is actually 2 channels (10 MHz) above that, |
| 359 | * and the upper half of each FAT channel is centered 4 channels (20 MHz) away |
| 360 | * from the lower half; e.g. the upper half of FAT channel 1 is channel 5, |
| 361 | * and the overall FAT channel width centers on channel 3. |
| 362 | * |
| 363 | * NOTE: The RXON command uses 20 MHz channel numbers to specify the |
| 364 | * control channel to which to tune. RXON also specifies whether the |
| 365 | * control channel is the upper or lower half of a FAT channel. |
| 366 | * |
| 367 | * NOTE: 4965 does not support FAT channels on 2.4 GHz. |
| 368 | */ |
| 369 | #define EEPROM_REGULATORY_BAND_24_FAT_CHANNELS (2*0xA0) /* 14 bytes */ |
| 370 | struct iwl4965_eeprom_channel band_24_channels[7]; /* abs.ofs: 320 */ |
| 371 | u8 reserved11[2]; |
| 372 | |
| 373 | /* |
| 374 | * 5.2 GHz FAT channels 36 (40), 44 (48), 52 (56), 60 (64), |
| 375 | * 100 (104), 108 (112), 116 (120), 124 (128), 132 (136), 149 (153), 157 (161) |
| 376 | */ |
| 377 | #define EEPROM_REGULATORY_BAND_52_FAT_CHANNELS (2*0xA8) /* 22 bytes */ |
| 378 | struct iwl4965_eeprom_channel band_52_channels[11]; /* abs.ofs: 336 */ |
| 379 | u8 reserved12[6]; |
| 380 | |
| 381 | /* |
| 382 | * 4965 driver requires txpower calibration format version 5 or greater. |
| 383 | * Driver does not work with txpower calibration version < 5. |
| 384 | * This value is simply a 16-bit number, no major/minor versions here. |
| 385 | */ |
| 386 | #define EEPROM_CALIB_VERSION_OFFSET (2*0xB6) /* 2 bytes */ |
| 387 | u16 calib_version; /* abs.ofs: 364 */ |
| 388 | u8 reserved13[2]; |
| 389 | u8 reserved14[96]; /* abs.ofs: 368 */ |
| 390 | |
| 391 | /* |
| 392 | * 4965 Txpower calibration data. |
| 393 | */ |
| 394 | #define EEPROM_IWL_CALIB_TXPOWER_OFFSET (2*0xE8) /* 48 bytes */ |
| 395 | struct iwl4965_eeprom_calib_info calib_info; /* abs.ofs: 464 */ |
| 396 | |
| 397 | u8 reserved16[140]; /* fill out to full 1024 byte block */ |
| 398 | |
| 399 | |
| 400 | } __attribute__ ((packed)); |
| 401 | |
| 402 | #define IWL_EEPROM_IMAGE_SIZE 1024 |
| 403 | |
| 404 | /* End of EEPROM */ |
| 405 | |
| 406 | #include "iwl-4965-commands.h" |
| 407 | |
| 408 | #define PCI_LINK_CTRL 0x0F0 |
| 409 | #define PCI_POWER_SOURCE 0x0C8 |
| 410 | #define PCI_REG_WUM8 0x0E8 |
| 411 | #define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000) |
| 412 | |
| 413 | /*=== CSR (control and status registers) ===*/ |
| 414 | #define CSR_BASE (0x000) |
| 415 | |
| 416 | #define CSR_SW_VER (CSR_BASE+0x000) |
| 417 | #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */ |
| 418 | #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */ |
| 419 | #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */ |
| 420 | #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */ |
| 421 | #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/ |
| 422 | #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */ |
| 423 | #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/ |
| 424 | #define CSR_GP_CNTRL (CSR_BASE+0x024) |
| 425 | |
| 426 | /* |
| 427 | * Hardware revision info |
| 428 | * Bit fields: |
| 429 | * 31-8: Reserved |
| 430 | * 7-4: Type of device: 0x0 = 4965, 0xd = 3945 |
| 431 | * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D |
| 432 | * 1-0: "Dash" value, as in A-1, etc. |
| 433 | * |
| 434 | * NOTE: Revision step affects calculation of CCK txpower for 4965. |
| 435 | */ |
| 436 | #define CSR_HW_REV (CSR_BASE+0x028) |
| 437 | |
| 438 | /* EEPROM reads */ |
| 439 | #define CSR_EEPROM_REG (CSR_BASE+0x02c) |
| 440 | #define CSR_EEPROM_GP (CSR_BASE+0x030) |
| 441 | #define CSR_GP_UCODE (CSR_BASE+0x044) |
| 442 | #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054) |
| 443 | #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058) |
| 444 | #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) |
| 445 | #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060) |
| 446 | #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) |
| 447 | |
| 448 | /* |
| 449 | * Indicates hardware rev, to determine CCK backoff for txpower calculation. |
| 450 | * Bit fields: |
| 451 | * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step |
| 452 | */ |
| 453 | #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C) |
| 454 | |
| 455 | /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), |
| 456 | * acknowledged (reset) by host writing "1" to flagged bits. */ |
| 457 | #define CSR_INT_BIT_FH_RX (1<<31) /* Rx DMA, cmd responses, FH_INT[17:16] */ |
| 458 | #define CSR_INT_BIT_HW_ERR (1<<29) /* DMA hardware error FH_INT[31] */ |
| 459 | #define CSR_INT_BIT_DNLD (1<<28) /* uCode Download */ |
| 460 | #define CSR_INT_BIT_FH_TX (1<<27) /* Tx DMA FH_INT[1:0] */ |
| 461 | #define CSR_INT_BIT_MAC_CLK_ACTV (1<<26) /* NIC controller's clock toggled on/off */ |
| 462 | #define CSR_INT_BIT_SW_ERR (1<<25) /* uCode error */ |
| 463 | #define CSR_INT_BIT_RF_KILL (1<<7) /* HW RFKILL switch GP_CNTRL[27] toggled */ |
| 464 | #define CSR_INT_BIT_CT_KILL (1<<6) /* Critical temp (chip too hot) rfkill */ |
| 465 | #define CSR_INT_BIT_SW_RX (1<<3) /* Rx, command responses, 3945 */ |
| 466 | #define CSR_INT_BIT_WAKEUP (1<<1) /* NIC controller waking up (pwr mgmt) */ |
| 467 | #define CSR_INT_BIT_ALIVE (1<<0) /* uCode interrupts once it initializes */ |
| 468 | |
| 469 | #define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \ |
| 470 | CSR_INT_BIT_HW_ERR | \ |
| 471 | CSR_INT_BIT_FH_TX | \ |
| 472 | CSR_INT_BIT_SW_ERR | \ |
| 473 | CSR_INT_BIT_RF_KILL | \ |
| 474 | CSR_INT_BIT_SW_RX | \ |
| 475 | CSR_INT_BIT_WAKEUP | \ |
| 476 | CSR_INT_BIT_ALIVE) |
| 477 | |
| 478 | /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ |
| 479 | #define CSR_FH_INT_BIT_ERR (1<<31) /* Error */ |
| 480 | #define CSR_FH_INT_BIT_HI_PRIOR (1<<30) /* High priority Rx, bypass coalescing */ |
| 481 | #define CSR_FH_INT_BIT_RX_CHNL1 (1<<17) /* Rx channel 1 */ |
| 482 | #define CSR_FH_INT_BIT_RX_CHNL0 (1<<16) /* Rx channel 0 */ |
| 483 | #define CSR_FH_INT_BIT_TX_CHNL1 (1<<1) /* Tx channel 1 */ |
| 484 | #define CSR_FH_INT_BIT_TX_CHNL0 (1<<0) /* Tx channel 0 */ |
| 485 | |
| 486 | #define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \ |
| 487 | CSR_FH_INT_BIT_RX_CHNL1 | \ |
| 488 | CSR_FH_INT_BIT_RX_CHNL0) |
| 489 | |
| 490 | #define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \ |
| 491 | CSR_FH_INT_BIT_TX_CHNL0) |
| 492 | |
| 493 | |
| 494 | /* RESET */ |
| 495 | #define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) |
| 496 | #define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) |
| 497 | #define CSR_RESET_REG_FLAG_SW_RESET (0x00000080) |
| 498 | #define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) |
| 499 | #define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) |
| 500 | |
| 501 | /* GP (general purpose) CONTROL */ |
| 502 | #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) |
| 503 | #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) |
| 504 | #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) |
| 505 | #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) |
| 506 | |
| 507 | #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) |
| 508 | |
| 509 | #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) |
| 510 | #define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) |
| 511 | #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) |
| 512 | |
| 513 | |
| 514 | /* EEPROM REG */ |
| 515 | #define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) |
| 516 | #define CSR_EEPROM_REG_BIT_CMD (0x00000002) |
| 517 | |
| 518 | /* EEPROM GP */ |
| 519 | #define CSR_EEPROM_GP_VALID_MSK (0x00000006) |
| 520 | #define CSR_EEPROM_GP_BAD_SIGNATURE (0x00000000) |
| 521 | #define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) |
| 522 | |
| 523 | /* UCODE DRV GP */ |
| 524 | #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) |
| 525 | #define CSR_UCODE_SW_BIT_RFKILL (0x00000002) |
| 526 | #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) |
| 527 | #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) |
| 528 | |
| 529 | /* GPIO */ |
| 530 | #define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) |
| 531 | #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) |
| 532 | #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC CSR_GPIO_IN_BIT_AUX_POWER |
| 533 | |
| 534 | /* GI Chicken Bits */ |
| 535 | #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) |
| 536 | #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) |
| 537 | |
| 538 | /*=== HBUS (Host-side Bus) ===*/ |
| 539 | #define HBUS_BASE (0x400) |
| 540 | |
| 541 | /* |
| 542 | * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM |
| 543 | * structures, error log, event log, verifying uCode load). |
| 544 | * First write to address register, then read from or write to data register |
| 545 | * to complete the job. Once the address register is set up, accesses to |
| 546 | * data registers auto-increment the address by one dword. |
| 547 | * Bit usage for address registers (read or write): |
| 548 | * 0-31: memory address within device |
| 549 | */ |
| 550 | #define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c) |
| 551 | #define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010) |
| 552 | #define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018) |
| 553 | #define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c) |
| 554 | |
| 555 | /* |
| 556 | * Registers for accessing device's internal peripheral registers |
| 557 | * (e.g. SCD, BSM, etc.). First write to address register, |
| 558 | * then read from or write to data register to complete the job. |
| 559 | * Bit usage for address registers (read or write): |
| 560 | * 0-15: register address (offset) within device |
| 561 | * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) |
| 562 | */ |
| 563 | #define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044) |
| 564 | #define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048) |
| 565 | #define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c) |
| 566 | #define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050) |
| 567 | |
| 568 | /* |
| 569 | * Per-Tx-queue write pointer (index, really!) (3945 and 4965). |
| 570 | * Indicates index to next TFD that driver will fill (1 past latest filled). |
| 571 | * Bit usage: |
| 572 | * 0-7: queue write index (0-255) |
| 573 | * 11-8: queue selector (0-15) |
| 574 | */ |
| 575 | #define HBUS_TARG_WRPTR (HBUS_BASE+0x060) |
| 576 | |
| 577 | #define HBUS_TARG_MBX_C (HBUS_BASE+0x030) |
| 578 | |
| 579 | /*=== FH (data Flow Handler) ===*/ |
| 580 | #define FH_BASE (0x800) |
| 581 | |
| 582 | #define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG) |
| 583 | |
| 584 | /* RSSR */ |
| 585 | #define FH_RSSR_CTRL (FH_RSSR_TABLE+0x000) |
| 586 | #define FH_RSSR_STATUS (FH_RSSR_TABLE+0x004) |
| 587 | /* TCSR */ |
| 588 | #define FH_TCSR(_channel) (FH_TCSR_TABLE+(_channel)*0x20) |
| 589 | #define FH_TCSR_CONFIG(_channel) (FH_TCSR(_channel)+0x00) |
| 590 | #define FH_TCSR_CREDIT(_channel) (FH_TCSR(_channel)+0x04) |
| 591 | #define FH_TCSR_BUFF_STTS(_channel) (FH_TCSR(_channel)+0x08) |
| 592 | /* TSSR */ |
| 593 | #define FH_TSSR_CBB_BASE (FH_TSSR_TABLE+0x000) |
| 594 | #define FH_TSSR_MSG_CONFIG (FH_TSSR_TABLE+0x008) |
| 595 | #define FH_TSSR_TX_STATUS (FH_TSSR_TABLE+0x010) |
| 596 | |
| 597 | |
| 598 | #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) |
| 599 | |
| 600 | #define TFD_QUEUE_SIZE_MAX (256) |
| 601 | |
| 602 | #define IWL_NUM_SCAN_RATES (2) |
| 603 | |
| 604 | #define IWL_DEFAULT_TX_RETRY 15 |
| 605 | |
| 606 | #define RX_QUEUE_SIZE 256 |
| 607 | #define RX_QUEUE_MASK 255 |
| 608 | #define RX_QUEUE_SIZE_LOG 8 |
| 609 | |
| 610 | #define TFD_TX_CMD_SLOTS 256 |
| 611 | #define TFD_CMD_SLOTS 32 |
| 612 | |
| 613 | #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl4965_cmd) - \ |
| 614 | sizeof(struct iwl4965_cmd_meta)) |
| 615 | |
| 616 | /* |
| 617 | * RX related structures and functions |
| 618 | */ |
| 619 | #define RX_FREE_BUFFERS 64 |
| 620 | #define RX_LOW_WATERMARK 8 |
| 621 | |
| 622 | /* Size of one Rx buffer in host DRAM */ |
| 623 | #define IWL_RX_BUF_SIZE (4 * 1024) |
| 624 | |
| 625 | /* Sizes and addresses for instruction and data memory (SRAM) in |
| 626 | * 4965's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */ |
| 627 | #define RTC_INST_LOWER_BOUND (0x000000) |
| 628 | #define KDR_RTC_INST_UPPER_BOUND (0x018000) |
| 629 | |
| 630 | #define RTC_DATA_LOWER_BOUND (0x800000) |
| 631 | #define KDR_RTC_DATA_UPPER_BOUND (0x80A000) |
| 632 | |
| 633 | #define KDR_RTC_INST_SIZE (KDR_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND) |
| 634 | #define KDR_RTC_DATA_SIZE (KDR_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND) |
| 635 | |
| 636 | #define IWL_MAX_INST_SIZE KDR_RTC_INST_SIZE |
| 637 | #define IWL_MAX_DATA_SIZE KDR_RTC_DATA_SIZE |
| 638 | |
| 639 | /* Size of uCode instruction memory in bootstrap state machine */ |
| 640 | #define IWL_MAX_BSM_SIZE BSM_SRAM_SIZE |
| 641 | |
| 642 | static inline int iwl4965_hw_valid_rtc_data_addr(u32 addr) |
| 643 | { |
| 644 | return (addr >= RTC_DATA_LOWER_BOUND) && |
| 645 | (addr < KDR_RTC_DATA_UPPER_BOUND); |
| 646 | } |
| 647 | |
| 648 | /********************* START TEMPERATURE *************************************/ |
| 649 | |
| 650 | /* |
| 651 | * 4965 temperature calculation. |
| 652 | * |
| 653 | * The driver must calculate the device temperature before calculating |
| 654 | * a txpower setting (amplifier gain is temperature dependent). The |
| 655 | * calculation uses 4 measurements, 3 of which (R1, R2, R3) are calibration |
| 656 | * values used for the life of the driver, and one of which (R4) is the |
| 657 | * real-time temperature indicator. |
| 658 | * |
| 659 | * uCode provides all 4 values to the driver via the "initialize alive" |
| 660 | * notification (see struct iwl4965_init_alive_resp). After the runtime uCode |
| 661 | * image loads, uCode updates the R4 value via statistics notifications |
| 662 | * (see STATISTICS_NOTIFICATION), which occur after each received beacon |
| 663 | * when associated, or can be requested via REPLY_STATISTICS_CMD. |
| 664 | * |
| 665 | * NOTE: uCode provides the R4 value as a 23-bit signed value. Driver |
| 666 | * must sign-extend to 32 bits before applying formula below. |
| 667 | * |
| 668 | * Formula: |
| 669 | * |
| 670 | * degrees Kelvin = ((97 * 259 * (R4 - R2) / (R3 - R1)) / 100) + 8 |
| 671 | * |
| 672 | * NOTE: The basic formula is 259 * (R4-R2) / (R3-R1). The 97/100 is |
| 673 | * an additional correction, which should be centered around 0 degrees |
| 674 | * Celsius (273 degrees Kelvin). The 8 (3 percent of 273) compensates for |
| 675 | * centering the 97/100 correction around 0 degrees K. |
| 676 | * |
| 677 | * Add 273 to Kelvin value to find degrees Celsius, for comparing current |
| 678 | * temperature with factory-measured temperatures when calculating txpower |
| 679 | * settings. |
| 680 | */ |
| 681 | #define TEMPERATURE_CALIB_KELVIN_OFFSET 8 |
| 682 | #define TEMPERATURE_CALIB_A_VAL 259 |
| 683 | |
| 684 | /* Limit range of calculated temperature to be between these Kelvin values */ |
| 685 | #define IWL_TX_POWER_TEMPERATURE_MIN (263) |
| 686 | #define IWL_TX_POWER_TEMPERATURE_MAX (410) |
| 687 | |
| 688 | #define IWL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \ |
| 689 | (((t) < IWL_TX_POWER_TEMPERATURE_MIN) || \ |
| 690 | ((t) > IWL_TX_POWER_TEMPERATURE_MAX)) |
| 691 | |
| 692 | /********************* END TEMPERATURE ***************************************/ |
| 693 | |
| 694 | /********************* START TXPOWER *****************************************/ |
| 695 | |
| 696 | enum { |
| 697 | CALIB_CH_GROUP_1 = 0, |
| 698 | CALIB_CH_GROUP_2 = 1, |
| 699 | CALIB_CH_GROUP_3 = 2, |
| 700 | CALIB_CH_GROUP_4 = 3, |
| 701 | CALIB_CH_GROUP_5 = 4, |
| 702 | CALIB_CH_GROUP_MAX |
| 703 | }; |
| 704 | |
| 705 | #define IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION (6) |
| 706 | |
| 707 | #define IWL_TX_POWER_TARGET_POWER_MIN (0) /* 0 dBm = 1 milliwatt */ |
| 708 | #define IWL_TX_POWER_TARGET_POWER_MAX (16) /* 16 dBm */ |
| 709 | |
| 710 | #define MIN_TX_GAIN_INDEX (0) |
| 711 | #define MIN_TX_GAIN_INDEX_52GHZ_EXT (-9) |
| 712 | |
| 713 | #define IWL_TX_POWER_DEFAULT_REGULATORY_24 (34) |
| 714 | #define IWL_TX_POWER_DEFAULT_REGULATORY_52 (34) |
| 715 | #define IWL_TX_POWER_REGULATORY_MIN (0) |
| 716 | #define IWL_TX_POWER_REGULATORY_MAX (34) |
| 717 | #define IWL_TX_POWER_DEFAULT_SATURATION_24 (38) |
| 718 | #define IWL_TX_POWER_DEFAULT_SATURATION_52 (38) |
| 719 | #define IWL_TX_POWER_SATURATION_MIN (20) |
| 720 | #define IWL_TX_POWER_SATURATION_MAX (50) |
| 721 | |
| 722 | /* First and last channels of all groups */ |
| 723 | #define CALIB_IWL_TX_ATTEN_GR1_FCH 34 |
| 724 | #define CALIB_IWL_TX_ATTEN_GR1_LCH 43 |
| 725 | #define CALIB_IWL_TX_ATTEN_GR2_FCH 44 |
| 726 | #define CALIB_IWL_TX_ATTEN_GR2_LCH 70 |
| 727 | #define CALIB_IWL_TX_ATTEN_GR3_FCH 71 |
| 728 | #define CALIB_IWL_TX_ATTEN_GR3_LCH 124 |
| 729 | #define CALIB_IWL_TX_ATTEN_GR4_FCH 125 |
| 730 | #define CALIB_IWL_TX_ATTEN_GR4_LCH 200 |
| 731 | #define CALIB_IWL_TX_ATTEN_GR5_FCH 1 |
| 732 | #define CALIB_IWL_TX_ATTEN_GR5_LCH 20 |
| 733 | |
| 734 | /********************* END TXPOWER *****************************************/ |
| 735 | |
| 736 | /* Flow Handler Definitions */ |
| 737 | |
| 738 | /**********************/ |
| 739 | /* Addresses */ |
| 740 | /**********************/ |
| 741 | |
| 742 | #define FH_MEM_LOWER_BOUND (0x1000) |
| 743 | #define FH_MEM_UPPER_BOUND (0x1EF0) |
| 744 | |
| 745 | #define IWL_FH_REGS_LOWER_BOUND (0x1000) |
| 746 | #define IWL_FH_REGS_UPPER_BOUND (0x2000) |
| 747 | |
| 748 | #define IWL_FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C) |
| 749 | |
| 750 | /* CBBC Area - Circular buffers base address cache pointers table */ |
| 751 | #define FH_MEM_CBBC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) |
| 752 | #define FH_MEM_CBBC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10) |
| 753 | /* queues 0 - 15 */ |
| 754 | #define FH_MEM_CBBC_QUEUE(x) (FH_MEM_CBBC_LOWER_BOUND + (x) * 0x4) |
| 755 | |
| 756 | /* RSCSR Area */ |
| 757 | #define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0) |
| 758 | #define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) |
| 759 | #define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND) |
| 760 | |
| 761 | #define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0) |
| 762 | #define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004) |
| 763 | #define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008) |
| 764 | |
| 765 | /* RCSR Area - Registers address map */ |
| 766 | #define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) |
| 767 | #define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0) |
| 768 | #define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND) |
| 769 | |
| 770 | #define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0) |
| 771 | |
| 772 | /* RSSR Area - Rx shared ctrl & status registers */ |
| 773 | #define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40) |
| 774 | #define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) |
| 775 | #define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND) |
| 776 | #define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004) |
| 777 | #define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV (FH_MEM_RSSR_LOWER_BOUND + 0x008) |
| 778 | |
| 779 | /* TCSR */ |
| 780 | #define IWL_FH_TCSR_LOWER_BOUND (IWL_FH_REGS_LOWER_BOUND + 0xD00) |
| 781 | #define IWL_FH_TCSR_UPPER_BOUND (IWL_FH_REGS_LOWER_BOUND + 0xE60) |
| 782 | |
| 783 | #define IWL_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ |
| 784 | (IWL_FH_TCSR_LOWER_BOUND + 0x20 * _chnl) |
| 785 | |
| 786 | /* TSSR Area - Tx shared status registers */ |
| 787 | /* TSSR */ |
| 788 | #define IWL_FH_TSSR_LOWER_BOUND (IWL_FH_REGS_LOWER_BOUND + 0xEA0) |
| 789 | #define IWL_FH_TSSR_UPPER_BOUND (IWL_FH_REGS_LOWER_BOUND + 0xEC0) |
| 790 | |
| 791 | #define IWL_FH_TSSR_TX_STATUS_REG (IWL_FH_TSSR_LOWER_BOUND + 0x010) |
| 792 | |
| 793 | #define IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) \ |
| 794 | ((1 << (_chnl)) << 24) |
| 795 | #define IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl) \ |
| 796 | ((1 << (_chnl)) << 16) |
| 797 | |
| 798 | #define IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) \ |
| 799 | (IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) | \ |
| 800 | IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl)) |
| 801 | |
| 802 | #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008) |
| 803 | |
| 804 | #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) |
| 805 | |
| 806 | /* RCSR: channel 0 rx_config register defines */ |
| 807 | |
| 808 | #define FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT (20) |
| 809 | |
| 810 | #define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) |
| 811 | |
| 812 | #define IWL_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) |
| 813 | |
| 814 | /* RCSR channel 0 config register values */ |
| 815 | #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) |
| 816 | |
| 817 | #define SCD_WIN_SIZE 64 |
| 818 | #define SCD_FRAME_LIMIT 64 |
| 819 | |
| 820 | /* SRAM structures */ |
| 821 | #define SCD_CONTEXT_DATA_OFFSET 0x380 |
| 822 | #define SCD_TX_STTS_BITMAP_OFFSET 0x400 |
| 823 | #define SCD_TRANSLATE_TBL_OFFSET 0x500 |
| 824 | #define SCD_CONTEXT_QUEUE_OFFSET(x) (SCD_CONTEXT_DATA_OFFSET + ((x) * 8)) |
| 825 | #define SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \ |
| 826 | ((SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc) |
| 827 | |
| 828 | #define SCD_TXFACT_REG_TXFIFO_MASK(lo, hi) \ |
| 829 | ((1<<(hi))|((1<<(hi))-(1<<(lo)))) |
| 830 | |
| 831 | #define SCD_QUEUE_STTS_REG_POS_ACTIVE (0) |
| 832 | #define SCD_QUEUE_STTS_REG_POS_TXF (1) |
| 833 | #define SCD_QUEUE_STTS_REG_POS_WSL (5) |
| 834 | #define SCD_QUEUE_STTS_REG_POS_SCD_ACK (8) |
| 835 | #define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (10) |
| 836 | #define SCD_QUEUE_STTS_REG_MSK (0x0007FC00) |
| 837 | |
| 838 | #define SCD_QUEUE_CTX_REG1_WIN_SIZE_POS (0) |
| 839 | #define SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK (0x0000007F) |
| 840 | |
| 841 | #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) |
| 842 | #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) |
| 843 | |
| 844 | #define CSR_HW_IF_CONFIG_REG_BIT_KEDRON_R (0x00000010) |
| 845 | #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00) |
| 846 | #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) |
| 847 | #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) |
| 848 | #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) |
| 849 | |
| 850 | static inline u8 iwl4965_hw_get_rate(__le32 rate_n_flags) |
| 851 | { |
| 852 | return le32_to_cpu(rate_n_flags) & 0xFF; |
| 853 | } |
| 854 | static inline u16 iwl4965_hw_get_rate_n_flags(__le32 rate_n_flags) |
| 855 | { |
| 856 | return le32_to_cpu(rate_n_flags) & 0xFFFF; |
| 857 | } |
| 858 | static inline __le32 iwl4965_hw_set_rate_n_flags(u8 rate, u16 flags) |
| 859 | { |
| 860 | return cpu_to_le32(flags|(u16)rate); |
| 861 | } |
| 862 | |
| 863 | struct iwl4965_tfd_frame_data { |
| 864 | __le32 tb1_addr; |
| 865 | |
| 866 | __le32 val1; |
| 867 | /* __le32 ptb1_32_35:4; */ |
| 868 | #define IWL_tb1_addr_hi_POS 0 |
| 869 | #define IWL_tb1_addr_hi_LEN 4 |
| 870 | #define IWL_tb1_addr_hi_SYM val1 |
| 871 | /* __le32 tb_len1:12; */ |
| 872 | #define IWL_tb1_len_POS 4 |
| 873 | #define IWL_tb1_len_LEN 12 |
| 874 | #define IWL_tb1_len_SYM val1 |
| 875 | /* __le32 ptb2_0_15:16; */ |
| 876 | #define IWL_tb2_addr_lo16_POS 16 |
| 877 | #define IWL_tb2_addr_lo16_LEN 16 |
| 878 | #define IWL_tb2_addr_lo16_SYM val1 |
| 879 | |
| 880 | __le32 val2; |
| 881 | /* __le32 ptb2_16_35:20; */ |
| 882 | #define IWL_tb2_addr_hi20_POS 0 |
| 883 | #define IWL_tb2_addr_hi20_LEN 20 |
| 884 | #define IWL_tb2_addr_hi20_SYM val2 |
| 885 | /* __le32 tb_len2:12; */ |
| 886 | #define IWL_tb2_len_POS 20 |
| 887 | #define IWL_tb2_len_LEN 12 |
| 888 | #define IWL_tb2_len_SYM val2 |
| 889 | } __attribute__ ((packed)); |
| 890 | |
| 891 | struct iwl4965_tfd_frame { |
| 892 | __le32 val0; |
| 893 | /* __le32 rsvd1:24; */ |
| 894 | /* __le32 num_tbs:5; */ |
| 895 | #define IWL_num_tbs_POS 24 |
| 896 | #define IWL_num_tbs_LEN 5 |
| 897 | #define IWL_num_tbs_SYM val0 |
| 898 | /* __le32 rsvd2:1; */ |
| 899 | /* __le32 padding:2; */ |
| 900 | struct iwl4965_tfd_frame_data pa[10]; |
| 901 | __le32 reserved; |
| 902 | } __attribute__ ((packed)); |
| 903 | |
| 904 | #define IWL4965_MAX_WIN_SIZE 64 |
| 905 | #define IWL4965_QUEUE_SIZE 256 |
| 906 | #define IWL4965_NUM_FIFOS 7 |
| 907 | #define IWL_MAX_NUM_QUEUES 16 |
| 908 | |
| 909 | struct iwl4965_queue_byte_cnt_entry { |
| 910 | __le16 val; |
| 911 | /* __le16 byte_cnt:12; */ |
| 912 | #define IWL_byte_cnt_POS 0 |
| 913 | #define IWL_byte_cnt_LEN 12 |
| 914 | #define IWL_byte_cnt_SYM val |
| 915 | /* __le16 rsvd:4; */ |
| 916 | } __attribute__ ((packed)); |
| 917 | |
| 918 | struct iwl4965_sched_queue_byte_cnt_tbl { |
| 919 | struct iwl4965_queue_byte_cnt_entry tfd_offset[IWL4965_QUEUE_SIZE + |
| 920 | IWL4965_MAX_WIN_SIZE]; |
| 921 | u8 dont_care[1024 - |
| 922 | (IWL4965_QUEUE_SIZE + IWL4965_MAX_WIN_SIZE) * |
| 923 | sizeof(__le16)]; |
| 924 | } __attribute__ ((packed)); |
| 925 | |
| 926 | /* Base physical address of iwl4965_shared is provided to KDR_SCD_DRAM_BASE_ADDR |
| 927 | * and &iwl4965_shared.val0 is provided to FH_RSCSR_CHNL0_STTS_WPTR_REG */ |
| 928 | struct iwl4965_shared { |
| 929 | struct iwl4965_sched_queue_byte_cnt_tbl |
| 930 | queues_byte_cnt_tbls[IWL_MAX_NUM_QUEUES]; |
| 931 | __le32 val0; |
| 932 | |
| 933 | /* __le32 rb_closed_stts_rb_num:12; */ |
| 934 | #define IWL_rb_closed_stts_rb_num_POS 0 |
| 935 | #define IWL_rb_closed_stts_rb_num_LEN 12 |
| 936 | #define IWL_rb_closed_stts_rb_num_SYM val0 |
| 937 | /* __le32 rsrv1:4; */ |
| 938 | /* __le32 rb_closed_stts_rx_frame_num:12; */ |
| 939 | #define IWL_rb_closed_stts_rx_frame_num_POS 16 |
| 940 | #define IWL_rb_closed_stts_rx_frame_num_LEN 12 |
| 941 | #define IWL_rb_closed_stts_rx_frame_num_SYM val0 |
| 942 | /* __le32 rsrv2:4; */ |
| 943 | |
| 944 | __le32 val1; |
| 945 | /* __le32 frame_finished_stts_rb_num:12; */ |
| 946 | #define IWL_frame_finished_stts_rb_num_POS 0 |
| 947 | #define IWL_frame_finished_stts_rb_num_LEN 12 |
| 948 | #define IWL_frame_finished_stts_rb_num_SYM val1 |
| 949 | /* __le32 rsrv3:4; */ |
| 950 | /* __le32 frame_finished_stts_rx_frame_num:12; */ |
| 951 | #define IWL_frame_finished_stts_rx_frame_num_POS 16 |
| 952 | #define IWL_frame_finished_stts_rx_frame_num_LEN 12 |
| 953 | #define IWL_frame_finished_stts_rx_frame_num_SYM val1 |
| 954 | /* __le32 rsrv4:4; */ |
| 955 | |
| 956 | __le32 padding1; /* so that allocation will be aligned to 16B */ |
| 957 | __le32 padding2; |
| 958 | } __attribute__ ((packed)); |
| 959 | |
| 960 | #endif /* __iwl4965_4965_hw_h__ */ |