| 1 | /****************************************************************************** |
| 2 | * |
| 3 | * GPL LICENSE SUMMARY |
| 4 | * |
| 5 | * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of version 2 of the GNU General Public License as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, but |
| 12 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, |
| 19 | * USA |
| 20 | * |
| 21 | * The full GNU General Public License is included in this distribution |
| 22 | * in the file called LICENSE.GPL. |
| 23 | * |
| 24 | * Contact Information: |
| 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
| 26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 27 | *****************************************************************************/ |
| 28 | |
| 29 | #include <linux/kernel.h> |
| 30 | #include <linux/module.h> |
| 31 | #include <linux/etherdevice.h> |
| 32 | #include <net/mac80211.h> |
| 33 | |
| 34 | #include "iwl-eeprom.h" |
| 35 | #include "iwl-dev.h" /* FIXME: remove */ |
| 36 | #include "iwl-debug.h" |
| 37 | #include "iwl-core.h" |
| 38 | #include "iwl-io.h" |
| 39 | #include "iwl-power.h" |
| 40 | #include "iwl-sta.h" |
| 41 | #include "iwl-helpers.h" |
| 42 | |
| 43 | |
| 44 | MODULE_DESCRIPTION("iwl core"); |
| 45 | MODULE_VERSION(IWLWIFI_VERSION); |
| 46 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
| 47 | MODULE_LICENSE("GPL"); |
| 48 | |
| 49 | static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = { |
| 50 | {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP, |
| 51 | 0, COEX_UNASSOC_IDLE_FLAGS}, |
| 52 | {COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP, |
| 53 | 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS}, |
| 54 | {COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP, |
| 55 | 0, COEX_UNASSOC_AUTO_SCAN_FLAGS}, |
| 56 | {COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP, |
| 57 | 0, COEX_CALIBRATION_FLAGS}, |
| 58 | {COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP, |
| 59 | 0, COEX_PERIODIC_CALIBRATION_FLAGS}, |
| 60 | {COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP, |
| 61 | 0, COEX_CONNECTION_ESTAB_FLAGS}, |
| 62 | {COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP, |
| 63 | 0, COEX_ASSOCIATED_IDLE_FLAGS}, |
| 64 | {COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP, |
| 65 | 0, COEX_ASSOC_MANUAL_SCAN_FLAGS}, |
| 66 | {COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP, |
| 67 | 0, COEX_ASSOC_AUTO_SCAN_FLAGS}, |
| 68 | {COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP, |
| 69 | 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS}, |
| 70 | {COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS}, |
| 71 | {COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS}, |
| 72 | {COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP, |
| 73 | 0, COEX_STAND_ALONE_DEBUG_FLAGS}, |
| 74 | {COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP, |
| 75 | 0, COEX_IPAN_ASSOC_LEVEL_FLAGS}, |
| 76 | {COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS}, |
| 77 | {COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS} |
| 78 | }; |
| 79 | |
| 80 | #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \ |
| 81 | [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \ |
| 82 | IWL_RATE_SISO_##s##M_PLCP, \ |
| 83 | IWL_RATE_MIMO2_##s##M_PLCP,\ |
| 84 | IWL_RATE_MIMO3_##s##M_PLCP,\ |
| 85 | IWL_RATE_##r##M_IEEE, \ |
| 86 | IWL_RATE_##ip##M_INDEX, \ |
| 87 | IWL_RATE_##in##M_INDEX, \ |
| 88 | IWL_RATE_##rp##M_INDEX, \ |
| 89 | IWL_RATE_##rn##M_INDEX, \ |
| 90 | IWL_RATE_##pp##M_INDEX, \ |
| 91 | IWL_RATE_##np##M_INDEX } |
| 92 | |
| 93 | u32 iwl_debug_level; |
| 94 | EXPORT_SYMBOL(iwl_debug_level); |
| 95 | |
| 96 | static irqreturn_t iwl_isr(int irq, void *data); |
| 97 | |
| 98 | /* |
| 99 | * Parameter order: |
| 100 | * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate |
| 101 | * |
| 102 | * If there isn't a valid next or previous rate then INV is used which |
| 103 | * maps to IWL_RATE_INVALID |
| 104 | * |
| 105 | */ |
| 106 | const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = { |
| 107 | IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */ |
| 108 | IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */ |
| 109 | IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */ |
| 110 | IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */ |
| 111 | IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */ |
| 112 | IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */ |
| 113 | IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */ |
| 114 | IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */ |
| 115 | IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */ |
| 116 | IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */ |
| 117 | IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */ |
| 118 | IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */ |
| 119 | IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */ |
| 120 | /* FIXME:RS: ^^ should be INV (legacy) */ |
| 121 | }; |
| 122 | EXPORT_SYMBOL(iwl_rates); |
| 123 | |
| 124 | /** |
| 125 | * translate ucode response to mac80211 tx status control values |
| 126 | */ |
| 127 | void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags, |
| 128 | struct ieee80211_tx_info *info) |
| 129 | { |
| 130 | struct ieee80211_tx_rate *r = &info->control.rates[0]; |
| 131 | |
| 132 | info->antenna_sel_tx = |
| 133 | ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS); |
| 134 | if (rate_n_flags & RATE_MCS_HT_MSK) |
| 135 | r->flags |= IEEE80211_TX_RC_MCS; |
| 136 | if (rate_n_flags & RATE_MCS_GF_MSK) |
| 137 | r->flags |= IEEE80211_TX_RC_GREEN_FIELD; |
| 138 | if (rate_n_flags & RATE_MCS_HT40_MSK) |
| 139 | r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; |
| 140 | if (rate_n_flags & RATE_MCS_DUP_MSK) |
| 141 | r->flags |= IEEE80211_TX_RC_DUP_DATA; |
| 142 | if (rate_n_flags & RATE_MCS_SGI_MSK) |
| 143 | r->flags |= IEEE80211_TX_RC_SHORT_GI; |
| 144 | r->idx = iwl_hwrate_to_mac80211_idx(rate_n_flags, info->band); |
| 145 | } |
| 146 | EXPORT_SYMBOL(iwl_hwrate_to_tx_control); |
| 147 | |
| 148 | int iwl_hwrate_to_plcp_idx(u32 rate_n_flags) |
| 149 | { |
| 150 | int idx = 0; |
| 151 | |
| 152 | /* HT rate format */ |
| 153 | if (rate_n_flags & RATE_MCS_HT_MSK) { |
| 154 | idx = (rate_n_flags & 0xff); |
| 155 | |
| 156 | if (idx >= IWL_RATE_MIMO3_6M_PLCP) |
| 157 | idx = idx - IWL_RATE_MIMO3_6M_PLCP; |
| 158 | else if (idx >= IWL_RATE_MIMO2_6M_PLCP) |
| 159 | idx = idx - IWL_RATE_MIMO2_6M_PLCP; |
| 160 | |
| 161 | idx += IWL_FIRST_OFDM_RATE; |
| 162 | /* skip 9M not supported in ht*/ |
| 163 | if (idx >= IWL_RATE_9M_INDEX) |
| 164 | idx += 1; |
| 165 | if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE)) |
| 166 | return idx; |
| 167 | |
| 168 | /* legacy rate format, search for match in table */ |
| 169 | } else { |
| 170 | for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++) |
| 171 | if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF)) |
| 172 | return idx; |
| 173 | } |
| 174 | |
| 175 | return -1; |
| 176 | } |
| 177 | EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx); |
| 178 | |
| 179 | int iwl_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band) |
| 180 | { |
| 181 | int idx = 0; |
| 182 | int band_offset = 0; |
| 183 | |
| 184 | /* HT rate format: mac80211 wants an MCS number, which is just LSB */ |
| 185 | if (rate_n_flags & RATE_MCS_HT_MSK) { |
| 186 | idx = (rate_n_flags & 0xff); |
| 187 | return idx; |
| 188 | /* Legacy rate format, search for match in table */ |
| 189 | } else { |
| 190 | if (band == IEEE80211_BAND_5GHZ) |
| 191 | band_offset = IWL_FIRST_OFDM_RATE; |
| 192 | for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++) |
| 193 | if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF)) |
| 194 | return idx - band_offset; |
| 195 | } |
| 196 | |
| 197 | return -1; |
| 198 | } |
| 199 | |
| 200 | u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant) |
| 201 | { |
| 202 | int i; |
| 203 | u8 ind = ant; |
| 204 | for (i = 0; i < RATE_ANT_NUM - 1; i++) { |
| 205 | ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0; |
| 206 | if (priv->hw_params.valid_tx_ant & BIT(ind)) |
| 207 | return ind; |
| 208 | } |
| 209 | return ant; |
| 210 | } |
| 211 | |
| 212 | const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; |
| 213 | EXPORT_SYMBOL(iwl_bcast_addr); |
| 214 | |
| 215 | |
| 216 | /* This function both allocates and initializes hw and priv. */ |
| 217 | struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg, |
| 218 | struct ieee80211_ops *hw_ops) |
| 219 | { |
| 220 | struct iwl_priv *priv; |
| 221 | |
| 222 | /* mac80211 allocates memory for this device instance, including |
| 223 | * space for this driver's private structure */ |
| 224 | struct ieee80211_hw *hw = |
| 225 | ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops); |
| 226 | if (hw == NULL) { |
| 227 | printk(KERN_ERR "%s: Can not allocate network device\n", |
| 228 | cfg->name); |
| 229 | goto out; |
| 230 | } |
| 231 | |
| 232 | priv = hw->priv; |
| 233 | priv->hw = hw; |
| 234 | |
| 235 | out: |
| 236 | return hw; |
| 237 | } |
| 238 | EXPORT_SYMBOL(iwl_alloc_all); |
| 239 | |
| 240 | void iwl_hw_detect(struct iwl_priv *priv) |
| 241 | { |
| 242 | priv->hw_rev = _iwl_read32(priv, CSR_HW_REV); |
| 243 | priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG); |
| 244 | pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id); |
| 245 | } |
| 246 | EXPORT_SYMBOL(iwl_hw_detect); |
| 247 | |
| 248 | int iwl_hw_nic_init(struct iwl_priv *priv) |
| 249 | { |
| 250 | unsigned long flags; |
| 251 | struct iwl_rx_queue *rxq = &priv->rxq; |
| 252 | int ret; |
| 253 | |
| 254 | /* nic_init */ |
| 255 | spin_lock_irqsave(&priv->lock, flags); |
| 256 | priv->cfg->ops->lib->apm_ops.init(priv); |
| 257 | iwl_write32(priv, CSR_INT_COALESCING, 512 / 32); |
| 258 | spin_unlock_irqrestore(&priv->lock, flags); |
| 259 | |
| 260 | ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN); |
| 261 | |
| 262 | priv->cfg->ops->lib->apm_ops.config(priv); |
| 263 | |
| 264 | /* Allocate the RX queue, or reset if it is already allocated */ |
| 265 | if (!rxq->bd) { |
| 266 | ret = iwl_rx_queue_alloc(priv); |
| 267 | if (ret) { |
| 268 | IWL_ERR(priv, "Unable to initialize Rx queue\n"); |
| 269 | return -ENOMEM; |
| 270 | } |
| 271 | } else |
| 272 | iwl_rx_queue_reset(priv, rxq); |
| 273 | |
| 274 | iwl_rx_replenish(priv); |
| 275 | |
| 276 | iwl_rx_init(priv, rxq); |
| 277 | |
| 278 | spin_lock_irqsave(&priv->lock, flags); |
| 279 | |
| 280 | rxq->need_update = 1; |
| 281 | iwl_rx_queue_update_write_ptr(priv, rxq); |
| 282 | |
| 283 | spin_unlock_irqrestore(&priv->lock, flags); |
| 284 | |
| 285 | /* Allocate and init all Tx and Command queues */ |
| 286 | ret = iwl_txq_ctx_reset(priv); |
| 287 | if (ret) |
| 288 | return ret; |
| 289 | |
| 290 | set_bit(STATUS_INIT, &priv->status); |
| 291 | |
| 292 | return 0; |
| 293 | } |
| 294 | EXPORT_SYMBOL(iwl_hw_nic_init); |
| 295 | |
| 296 | /* |
| 297 | * QoS support |
| 298 | */ |
| 299 | void iwl_activate_qos(struct iwl_priv *priv, u8 force) |
| 300 | { |
| 301 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
| 302 | return; |
| 303 | |
| 304 | priv->qos_data.def_qos_parm.qos_flags = 0; |
| 305 | |
| 306 | if (priv->qos_data.qos_cap.q_AP.queue_request && |
| 307 | !priv->qos_data.qos_cap.q_AP.txop_request) |
| 308 | priv->qos_data.def_qos_parm.qos_flags |= |
| 309 | QOS_PARAM_FLG_TXOP_TYPE_MSK; |
| 310 | if (priv->qos_data.qos_active) |
| 311 | priv->qos_data.def_qos_parm.qos_flags |= |
| 312 | QOS_PARAM_FLG_UPDATE_EDCA_MSK; |
| 313 | |
| 314 | if (priv->current_ht_config.is_ht) |
| 315 | priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK; |
| 316 | |
| 317 | if (force || iwl_is_associated(priv)) { |
| 318 | IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n", |
| 319 | priv->qos_data.qos_active, |
| 320 | priv->qos_data.def_qos_parm.qos_flags); |
| 321 | |
| 322 | iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM, |
| 323 | sizeof(struct iwl_qosparam_cmd), |
| 324 | &priv->qos_data.def_qos_parm, NULL); |
| 325 | } |
| 326 | } |
| 327 | EXPORT_SYMBOL(iwl_activate_qos); |
| 328 | |
| 329 | /* |
| 330 | * AC CWmin CW max AIFSN TXOP Limit TXOP Limit |
| 331 | * (802.11b) (802.11a/g) |
| 332 | * AC_BK 15 1023 7 0 0 |
| 333 | * AC_BE 15 1023 3 0 0 |
| 334 | * AC_VI 7 15 2 6.016ms 3.008ms |
| 335 | * AC_VO 3 7 2 3.264ms 1.504ms |
| 336 | */ |
| 337 | void iwl_reset_qos(struct iwl_priv *priv) |
| 338 | { |
| 339 | u16 cw_min = 15; |
| 340 | u16 cw_max = 1023; |
| 341 | u8 aifs = 2; |
| 342 | bool is_legacy = false; |
| 343 | unsigned long flags; |
| 344 | int i; |
| 345 | |
| 346 | spin_lock_irqsave(&priv->lock, flags); |
| 347 | /* QoS always active in AP and ADHOC mode |
| 348 | * In STA mode wait for association |
| 349 | */ |
| 350 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC || |
| 351 | priv->iw_mode == NL80211_IFTYPE_AP) |
| 352 | priv->qos_data.qos_active = 1; |
| 353 | else |
| 354 | priv->qos_data.qos_active = 0; |
| 355 | |
| 356 | /* check for legacy mode */ |
| 357 | if ((priv->iw_mode == NL80211_IFTYPE_ADHOC && |
| 358 | (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) || |
| 359 | (priv->iw_mode == NL80211_IFTYPE_STATION && |
| 360 | (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) { |
| 361 | cw_min = 31; |
| 362 | is_legacy = 1; |
| 363 | } |
| 364 | |
| 365 | if (priv->qos_data.qos_active) |
| 366 | aifs = 3; |
| 367 | |
| 368 | /* AC_BE */ |
| 369 | priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min); |
| 370 | priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max); |
| 371 | priv->qos_data.def_qos_parm.ac[0].aifsn = aifs; |
| 372 | priv->qos_data.def_qos_parm.ac[0].edca_txop = 0; |
| 373 | priv->qos_data.def_qos_parm.ac[0].reserved1 = 0; |
| 374 | |
| 375 | if (priv->qos_data.qos_active) { |
| 376 | /* AC_BK */ |
| 377 | i = 1; |
| 378 | priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min); |
| 379 | priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max); |
| 380 | priv->qos_data.def_qos_parm.ac[i].aifsn = 7; |
| 381 | priv->qos_data.def_qos_parm.ac[i].edca_txop = 0; |
| 382 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; |
| 383 | |
| 384 | /* AC_VI */ |
| 385 | i = 2; |
| 386 | priv->qos_data.def_qos_parm.ac[i].cw_min = |
| 387 | cpu_to_le16((cw_min + 1) / 2 - 1); |
| 388 | priv->qos_data.def_qos_parm.ac[i].cw_max = |
| 389 | cpu_to_le16(cw_min); |
| 390 | priv->qos_data.def_qos_parm.ac[i].aifsn = 2; |
| 391 | if (is_legacy) |
| 392 | priv->qos_data.def_qos_parm.ac[i].edca_txop = |
| 393 | cpu_to_le16(6016); |
| 394 | else |
| 395 | priv->qos_data.def_qos_parm.ac[i].edca_txop = |
| 396 | cpu_to_le16(3008); |
| 397 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; |
| 398 | |
| 399 | /* AC_VO */ |
| 400 | i = 3; |
| 401 | priv->qos_data.def_qos_parm.ac[i].cw_min = |
| 402 | cpu_to_le16((cw_min + 1) / 4 - 1); |
| 403 | priv->qos_data.def_qos_parm.ac[i].cw_max = |
| 404 | cpu_to_le16((cw_min + 1) / 2 - 1); |
| 405 | priv->qos_data.def_qos_parm.ac[i].aifsn = 2; |
| 406 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; |
| 407 | if (is_legacy) |
| 408 | priv->qos_data.def_qos_parm.ac[i].edca_txop = |
| 409 | cpu_to_le16(3264); |
| 410 | else |
| 411 | priv->qos_data.def_qos_parm.ac[i].edca_txop = |
| 412 | cpu_to_le16(1504); |
| 413 | } else { |
| 414 | for (i = 1; i < 4; i++) { |
| 415 | priv->qos_data.def_qos_parm.ac[i].cw_min = |
| 416 | cpu_to_le16(cw_min); |
| 417 | priv->qos_data.def_qos_parm.ac[i].cw_max = |
| 418 | cpu_to_le16(cw_max); |
| 419 | priv->qos_data.def_qos_parm.ac[i].aifsn = aifs; |
| 420 | priv->qos_data.def_qos_parm.ac[i].edca_txop = 0; |
| 421 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; |
| 422 | } |
| 423 | } |
| 424 | IWL_DEBUG_QOS(priv, "set QoS to default \n"); |
| 425 | |
| 426 | spin_unlock_irqrestore(&priv->lock, flags); |
| 427 | } |
| 428 | EXPORT_SYMBOL(iwl_reset_qos); |
| 429 | |
| 430 | #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */ |
| 431 | #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */ |
| 432 | static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv, |
| 433 | struct ieee80211_sta_ht_cap *ht_info, |
| 434 | enum ieee80211_band band) |
| 435 | { |
| 436 | u16 max_bit_rate = 0; |
| 437 | u8 rx_chains_num = priv->hw_params.rx_chains_num; |
| 438 | u8 tx_chains_num = priv->hw_params.tx_chains_num; |
| 439 | |
| 440 | ht_info->cap = 0; |
| 441 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); |
| 442 | |
| 443 | ht_info->ht_supported = true; |
| 444 | |
| 445 | if (priv->cfg->ht_greenfield_support) |
| 446 | ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD; |
| 447 | ht_info->cap |= IEEE80211_HT_CAP_SGI_20; |
| 448 | if (priv->cfg->support_sm_ps) |
| 449 | ht_info->cap |= (IEEE80211_HT_CAP_SM_PS & |
| 450 | (WLAN_HT_CAP_SM_PS_DYNAMIC << 2)); |
| 451 | else |
| 452 | ht_info->cap |= (IEEE80211_HT_CAP_SM_PS & |
| 453 | (WLAN_HT_CAP_SM_PS_DISABLED << 2)); |
| 454 | |
| 455 | max_bit_rate = MAX_BIT_RATE_20_MHZ; |
| 456 | if (priv->hw_params.ht40_channel & BIT(band)) { |
| 457 | ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; |
| 458 | ht_info->cap |= IEEE80211_HT_CAP_SGI_40; |
| 459 | ht_info->mcs.rx_mask[4] = 0x01; |
| 460 | max_bit_rate = MAX_BIT_RATE_40_MHZ; |
| 461 | } |
| 462 | |
| 463 | if (priv->cfg->mod_params->amsdu_size_8K) |
| 464 | ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU; |
| 465 | |
| 466 | ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF; |
| 467 | ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF; |
| 468 | |
| 469 | ht_info->mcs.rx_mask[0] = 0xFF; |
| 470 | if (rx_chains_num >= 2) |
| 471 | ht_info->mcs.rx_mask[1] = 0xFF; |
| 472 | if (rx_chains_num >= 3) |
| 473 | ht_info->mcs.rx_mask[2] = 0xFF; |
| 474 | |
| 475 | /* Highest supported Rx data rate */ |
| 476 | max_bit_rate *= rx_chains_num; |
| 477 | WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK); |
| 478 | ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate); |
| 479 | |
| 480 | /* Tx MCS capabilities */ |
| 481 | ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; |
| 482 | if (tx_chains_num != rx_chains_num) { |
| 483 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; |
| 484 | ht_info->mcs.tx_params |= ((tx_chains_num - 1) << |
| 485 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); |
| 486 | } |
| 487 | } |
| 488 | |
| 489 | /** |
| 490 | * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom |
| 491 | */ |
| 492 | int iwlcore_init_geos(struct iwl_priv *priv) |
| 493 | { |
| 494 | struct iwl_channel_info *ch; |
| 495 | struct ieee80211_supported_band *sband; |
| 496 | struct ieee80211_channel *channels; |
| 497 | struct ieee80211_channel *geo_ch; |
| 498 | struct ieee80211_rate *rates; |
| 499 | int i = 0; |
| 500 | |
| 501 | if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates || |
| 502 | priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) { |
| 503 | IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n"); |
| 504 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); |
| 505 | return 0; |
| 506 | } |
| 507 | |
| 508 | channels = kzalloc(sizeof(struct ieee80211_channel) * |
| 509 | priv->channel_count, GFP_KERNEL); |
| 510 | if (!channels) |
| 511 | return -ENOMEM; |
| 512 | |
| 513 | rates = kzalloc((sizeof(struct ieee80211_rate) * IWL_RATE_COUNT_LEGACY), |
| 514 | GFP_KERNEL); |
| 515 | if (!rates) { |
| 516 | kfree(channels); |
| 517 | return -ENOMEM; |
| 518 | } |
| 519 | |
| 520 | /* 5.2GHz channels start after the 2.4GHz channels */ |
| 521 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; |
| 522 | sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)]; |
| 523 | /* just OFDM */ |
| 524 | sband->bitrates = &rates[IWL_FIRST_OFDM_RATE]; |
| 525 | sband->n_bitrates = IWL_RATE_COUNT_LEGACY - IWL_FIRST_OFDM_RATE; |
| 526 | |
| 527 | if (priv->cfg->sku & IWL_SKU_N) |
| 528 | iwlcore_init_ht_hw_capab(priv, &sband->ht_cap, |
| 529 | IEEE80211_BAND_5GHZ); |
| 530 | |
| 531 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; |
| 532 | sband->channels = channels; |
| 533 | /* OFDM & CCK */ |
| 534 | sband->bitrates = rates; |
| 535 | sband->n_bitrates = IWL_RATE_COUNT_LEGACY; |
| 536 | |
| 537 | if (priv->cfg->sku & IWL_SKU_N) |
| 538 | iwlcore_init_ht_hw_capab(priv, &sband->ht_cap, |
| 539 | IEEE80211_BAND_2GHZ); |
| 540 | |
| 541 | priv->ieee_channels = channels; |
| 542 | priv->ieee_rates = rates; |
| 543 | |
| 544 | for (i = 0; i < priv->channel_count; i++) { |
| 545 | ch = &priv->channel_info[i]; |
| 546 | |
| 547 | /* FIXME: might be removed if scan is OK */ |
| 548 | if (!is_channel_valid(ch)) |
| 549 | continue; |
| 550 | |
| 551 | if (is_channel_a_band(ch)) |
| 552 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; |
| 553 | else |
| 554 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; |
| 555 | |
| 556 | geo_ch = &sband->channels[sband->n_channels++]; |
| 557 | |
| 558 | geo_ch->center_freq = |
| 559 | ieee80211_channel_to_frequency(ch->channel); |
| 560 | geo_ch->max_power = ch->max_power_avg; |
| 561 | geo_ch->max_antenna_gain = 0xff; |
| 562 | geo_ch->hw_value = ch->channel; |
| 563 | |
| 564 | if (is_channel_valid(ch)) { |
| 565 | if (!(ch->flags & EEPROM_CHANNEL_IBSS)) |
| 566 | geo_ch->flags |= IEEE80211_CHAN_NO_IBSS; |
| 567 | |
| 568 | if (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) |
| 569 | geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN; |
| 570 | |
| 571 | if (ch->flags & EEPROM_CHANNEL_RADAR) |
| 572 | geo_ch->flags |= IEEE80211_CHAN_RADAR; |
| 573 | |
| 574 | geo_ch->flags |= ch->ht40_extension_channel; |
| 575 | |
| 576 | if (ch->max_power_avg > priv->tx_power_device_lmt) |
| 577 | priv->tx_power_device_lmt = ch->max_power_avg; |
| 578 | } else { |
| 579 | geo_ch->flags |= IEEE80211_CHAN_DISABLED; |
| 580 | } |
| 581 | |
| 582 | IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n", |
| 583 | ch->channel, geo_ch->center_freq, |
| 584 | is_channel_a_band(ch) ? "5.2" : "2.4", |
| 585 | geo_ch->flags & IEEE80211_CHAN_DISABLED ? |
| 586 | "restricted" : "valid", |
| 587 | geo_ch->flags); |
| 588 | } |
| 589 | |
| 590 | if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && |
| 591 | priv->cfg->sku & IWL_SKU_A) { |
| 592 | IWL_INFO(priv, "Incorrectly detected BG card as ABG. " |
| 593 | "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n", |
| 594 | priv->pci_dev->device, |
| 595 | priv->pci_dev->subsystem_device); |
| 596 | priv->cfg->sku &= ~IWL_SKU_A; |
| 597 | } |
| 598 | |
| 599 | IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n", |
| 600 | priv->bands[IEEE80211_BAND_2GHZ].n_channels, |
| 601 | priv->bands[IEEE80211_BAND_5GHZ].n_channels); |
| 602 | |
| 603 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); |
| 604 | |
| 605 | return 0; |
| 606 | } |
| 607 | EXPORT_SYMBOL(iwlcore_init_geos); |
| 608 | |
| 609 | /* |
| 610 | * iwlcore_free_geos - undo allocations in iwlcore_init_geos |
| 611 | */ |
| 612 | void iwlcore_free_geos(struct iwl_priv *priv) |
| 613 | { |
| 614 | kfree(priv->ieee_channels); |
| 615 | kfree(priv->ieee_rates); |
| 616 | clear_bit(STATUS_GEO_CONFIGURED, &priv->status); |
| 617 | } |
| 618 | EXPORT_SYMBOL(iwlcore_free_geos); |
| 619 | |
| 620 | /* |
| 621 | * iwlcore_rts_tx_cmd_flag: Set rts/cts. 3945 and 4965 only share this |
| 622 | * function. |
| 623 | */ |
| 624 | void iwlcore_rts_tx_cmd_flag(struct ieee80211_tx_info *info, |
| 625 | __le32 *tx_flags) |
| 626 | { |
| 627 | if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) { |
| 628 | *tx_flags |= TX_CMD_FLG_RTS_MSK; |
| 629 | *tx_flags &= ~TX_CMD_FLG_CTS_MSK; |
| 630 | } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { |
| 631 | *tx_flags &= ~TX_CMD_FLG_RTS_MSK; |
| 632 | *tx_flags |= TX_CMD_FLG_CTS_MSK; |
| 633 | } |
| 634 | } |
| 635 | EXPORT_SYMBOL(iwlcore_rts_tx_cmd_flag); |
| 636 | |
| 637 | static bool is_single_rx_stream(struct iwl_priv *priv) |
| 638 | { |
| 639 | return !priv->current_ht_config.is_ht || |
| 640 | priv->current_ht_config.single_chain_sufficient; |
| 641 | } |
| 642 | |
| 643 | static u8 iwl_is_channel_extension(struct iwl_priv *priv, |
| 644 | enum ieee80211_band band, |
| 645 | u16 channel, u8 extension_chan_offset) |
| 646 | { |
| 647 | const struct iwl_channel_info *ch_info; |
| 648 | |
| 649 | ch_info = iwl_get_channel_info(priv, band, channel); |
| 650 | if (!is_channel_valid(ch_info)) |
| 651 | return 0; |
| 652 | |
| 653 | if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) |
| 654 | return !(ch_info->ht40_extension_channel & |
| 655 | IEEE80211_CHAN_NO_HT40PLUS); |
| 656 | else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) |
| 657 | return !(ch_info->ht40_extension_channel & |
| 658 | IEEE80211_CHAN_NO_HT40MINUS); |
| 659 | |
| 660 | return 0; |
| 661 | } |
| 662 | |
| 663 | u8 iwl_is_ht40_tx_allowed(struct iwl_priv *priv, |
| 664 | struct ieee80211_sta_ht_cap *sta_ht_inf) |
| 665 | { |
| 666 | struct iwl_ht_config *ht_conf = &priv->current_ht_config; |
| 667 | |
| 668 | if (!ht_conf->is_ht || !ht_conf->is_40mhz) |
| 669 | return 0; |
| 670 | |
| 671 | /* We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
| 672 | * the bit will not set if it is pure 40MHz case |
| 673 | */ |
| 674 | if (sta_ht_inf) { |
| 675 | if (!sta_ht_inf->ht_supported) |
| 676 | return 0; |
| 677 | } |
| 678 | #ifdef CONFIG_IWLWIFI_DEBUG |
| 679 | if (priv->disable_ht40) |
| 680 | return 0; |
| 681 | #endif |
| 682 | return iwl_is_channel_extension(priv, priv->band, |
| 683 | le16_to_cpu(priv->staging_rxon.channel), |
| 684 | ht_conf->extension_chan_offset); |
| 685 | } |
| 686 | EXPORT_SYMBOL(iwl_is_ht40_tx_allowed); |
| 687 | |
| 688 | static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val) |
| 689 | { |
| 690 | u16 new_val = 0; |
| 691 | u16 beacon_factor = 0; |
| 692 | |
| 693 | beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val; |
| 694 | new_val = beacon_val / beacon_factor; |
| 695 | |
| 696 | if (!new_val) |
| 697 | new_val = max_beacon_val; |
| 698 | |
| 699 | return new_val; |
| 700 | } |
| 701 | |
| 702 | void iwl_setup_rxon_timing(struct iwl_priv *priv) |
| 703 | { |
| 704 | u64 tsf; |
| 705 | s32 interval_tm, rem; |
| 706 | unsigned long flags; |
| 707 | struct ieee80211_conf *conf = NULL; |
| 708 | u16 beacon_int; |
| 709 | |
| 710 | conf = ieee80211_get_hw_conf(priv->hw); |
| 711 | |
| 712 | spin_lock_irqsave(&priv->lock, flags); |
| 713 | priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp); |
| 714 | priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval); |
| 715 | |
| 716 | if (priv->iw_mode == NL80211_IFTYPE_STATION) { |
| 717 | beacon_int = priv->beacon_int; |
| 718 | priv->rxon_timing.atim_window = 0; |
| 719 | } else { |
| 720 | beacon_int = priv->vif->bss_conf.beacon_int; |
| 721 | |
| 722 | /* TODO: we need to get atim_window from upper stack |
| 723 | * for now we set to 0 */ |
| 724 | priv->rxon_timing.atim_window = 0; |
| 725 | } |
| 726 | |
| 727 | beacon_int = iwl_adjust_beacon_interval(beacon_int, |
| 728 | priv->hw_params.max_beacon_itrvl * 1024); |
| 729 | priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int); |
| 730 | |
| 731 | tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */ |
| 732 | interval_tm = beacon_int * 1024; |
| 733 | rem = do_div(tsf, interval_tm); |
| 734 | priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem); |
| 735 | |
| 736 | spin_unlock_irqrestore(&priv->lock, flags); |
| 737 | IWL_DEBUG_ASSOC(priv, |
| 738 | "beacon interval %d beacon timer %d beacon tim %d\n", |
| 739 | le16_to_cpu(priv->rxon_timing.beacon_interval), |
| 740 | le32_to_cpu(priv->rxon_timing.beacon_init_val), |
| 741 | le16_to_cpu(priv->rxon_timing.atim_window)); |
| 742 | } |
| 743 | EXPORT_SYMBOL(iwl_setup_rxon_timing); |
| 744 | |
| 745 | void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt) |
| 746 | { |
| 747 | struct iwl_rxon_cmd *rxon = &priv->staging_rxon; |
| 748 | |
| 749 | if (hw_decrypt) |
| 750 | rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK; |
| 751 | else |
| 752 | rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK; |
| 753 | |
| 754 | } |
| 755 | EXPORT_SYMBOL(iwl_set_rxon_hwcrypto); |
| 756 | |
| 757 | /** |
| 758 | * iwl_check_rxon_cmd - validate RXON structure is valid |
| 759 | * |
| 760 | * NOTE: This is really only useful during development and can eventually |
| 761 | * be #ifdef'd out once the driver is stable and folks aren't actively |
| 762 | * making changes |
| 763 | */ |
| 764 | int iwl_check_rxon_cmd(struct iwl_priv *priv) |
| 765 | { |
| 766 | int error = 0; |
| 767 | int counter = 1; |
| 768 | struct iwl_rxon_cmd *rxon = &priv->staging_rxon; |
| 769 | |
| 770 | if (rxon->flags & RXON_FLG_BAND_24G_MSK) { |
| 771 | error |= le32_to_cpu(rxon->flags & |
| 772 | (RXON_FLG_TGJ_NARROW_BAND_MSK | |
| 773 | RXON_FLG_RADAR_DETECT_MSK)); |
| 774 | if (error) |
| 775 | IWL_WARN(priv, "check 24G fields %d | %d\n", |
| 776 | counter++, error); |
| 777 | } else { |
| 778 | error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ? |
| 779 | 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK); |
| 780 | if (error) |
| 781 | IWL_WARN(priv, "check 52 fields %d | %d\n", |
| 782 | counter++, error); |
| 783 | error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK); |
| 784 | if (error) |
| 785 | IWL_WARN(priv, "check 52 CCK %d | %d\n", |
| 786 | counter++, error); |
| 787 | } |
| 788 | error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1; |
| 789 | if (error) |
| 790 | IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error); |
| 791 | |
| 792 | /* make sure basic rates 6Mbps and 1Mbps are supported */ |
| 793 | error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) && |
| 794 | ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0)); |
| 795 | if (error) |
| 796 | IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error); |
| 797 | |
| 798 | error |= (le16_to_cpu(rxon->assoc_id) > 2007); |
| 799 | if (error) |
| 800 | IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error); |
| 801 | |
| 802 | error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) |
| 803 | == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)); |
| 804 | if (error) |
| 805 | IWL_WARN(priv, "check CCK and short slot %d | %d\n", |
| 806 | counter++, error); |
| 807 | |
| 808 | error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) |
| 809 | == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)); |
| 810 | if (error) |
| 811 | IWL_WARN(priv, "check CCK & auto detect %d | %d\n", |
| 812 | counter++, error); |
| 813 | |
| 814 | error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK | |
| 815 | RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK); |
| 816 | if (error) |
| 817 | IWL_WARN(priv, "check TGG and auto detect %d | %d\n", |
| 818 | counter++, error); |
| 819 | |
| 820 | if (error) |
| 821 | IWL_WARN(priv, "Tuning to channel %d\n", |
| 822 | le16_to_cpu(rxon->channel)); |
| 823 | |
| 824 | if (error) { |
| 825 | IWL_ERR(priv, "Not a valid iwl_rxon_assoc_cmd field values\n"); |
| 826 | return -1; |
| 827 | } |
| 828 | return 0; |
| 829 | } |
| 830 | EXPORT_SYMBOL(iwl_check_rxon_cmd); |
| 831 | |
| 832 | /** |
| 833 | * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed |
| 834 | * @priv: staging_rxon is compared to active_rxon |
| 835 | * |
| 836 | * If the RXON structure is changing enough to require a new tune, |
| 837 | * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that |
| 838 | * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required. |
| 839 | */ |
| 840 | int iwl_full_rxon_required(struct iwl_priv *priv) |
| 841 | { |
| 842 | |
| 843 | /* These items are only settable from the full RXON command */ |
| 844 | if (!(iwl_is_associated(priv)) || |
| 845 | compare_ether_addr(priv->staging_rxon.bssid_addr, |
| 846 | priv->active_rxon.bssid_addr) || |
| 847 | compare_ether_addr(priv->staging_rxon.node_addr, |
| 848 | priv->active_rxon.node_addr) || |
| 849 | compare_ether_addr(priv->staging_rxon.wlap_bssid_addr, |
| 850 | priv->active_rxon.wlap_bssid_addr) || |
| 851 | (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) || |
| 852 | (priv->staging_rxon.channel != priv->active_rxon.channel) || |
| 853 | (priv->staging_rxon.air_propagation != |
| 854 | priv->active_rxon.air_propagation) || |
| 855 | (priv->staging_rxon.ofdm_ht_single_stream_basic_rates != |
| 856 | priv->active_rxon.ofdm_ht_single_stream_basic_rates) || |
| 857 | (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates != |
| 858 | priv->active_rxon.ofdm_ht_dual_stream_basic_rates) || |
| 859 | (priv->staging_rxon.ofdm_ht_triple_stream_basic_rates != |
| 860 | priv->active_rxon.ofdm_ht_triple_stream_basic_rates) || |
| 861 | (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id)) |
| 862 | return 1; |
| 863 | |
| 864 | /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can |
| 865 | * be updated with the RXON_ASSOC command -- however only some |
| 866 | * flag transitions are allowed using RXON_ASSOC */ |
| 867 | |
| 868 | /* Check if we are not switching bands */ |
| 869 | if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) != |
| 870 | (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)) |
| 871 | return 1; |
| 872 | |
| 873 | /* Check if we are switching association toggle */ |
| 874 | if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) != |
| 875 | (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) |
| 876 | return 1; |
| 877 | |
| 878 | return 0; |
| 879 | } |
| 880 | EXPORT_SYMBOL(iwl_full_rxon_required); |
| 881 | |
| 882 | u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv) |
| 883 | { |
| 884 | int i; |
| 885 | int rate_mask; |
| 886 | |
| 887 | /* Set rate mask*/ |
| 888 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) |
| 889 | rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK; |
| 890 | else |
| 891 | rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK; |
| 892 | |
| 893 | /* Find lowest valid rate */ |
| 894 | for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID; |
| 895 | i = iwl_rates[i].next_ieee) { |
| 896 | if (rate_mask & (1 << i)) |
| 897 | return iwl_rates[i].plcp; |
| 898 | } |
| 899 | |
| 900 | /* No valid rate was found. Assign the lowest one */ |
| 901 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) |
| 902 | return IWL_RATE_1M_PLCP; |
| 903 | else |
| 904 | return IWL_RATE_6M_PLCP; |
| 905 | } |
| 906 | EXPORT_SYMBOL(iwl_rate_get_lowest_plcp); |
| 907 | |
| 908 | void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_config *ht_conf) |
| 909 | { |
| 910 | struct iwl_rxon_cmd *rxon = &priv->staging_rxon; |
| 911 | |
| 912 | if (!ht_conf->is_ht) { |
| 913 | rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK | |
| 914 | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK | |
| 915 | RXON_FLG_HT40_PROT_MSK | |
| 916 | RXON_FLG_HT_PROT_MSK); |
| 917 | return; |
| 918 | } |
| 919 | |
| 920 | /* FIXME: if the definition of ht_protection changed, the "translation" |
| 921 | * will be needed for rxon->flags |
| 922 | */ |
| 923 | rxon->flags |= cpu_to_le32(ht_conf->ht_protection << RXON_FLG_HT_OPERATING_MODE_POS); |
| 924 | |
| 925 | /* Set up channel bandwidth: |
| 926 | * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */ |
| 927 | /* clear the HT channel mode before set the mode */ |
| 928 | rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK | |
| 929 | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); |
| 930 | if (iwl_is_ht40_tx_allowed(priv, NULL)) { |
| 931 | /* pure ht40 */ |
| 932 | if (ht_conf->ht_protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) { |
| 933 | rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40; |
| 934 | /* Note: control channel is opposite of extension channel */ |
| 935 | switch (ht_conf->extension_chan_offset) { |
| 936 | case IEEE80211_HT_PARAM_CHA_SEC_ABOVE: |
| 937 | rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; |
| 938 | break; |
| 939 | case IEEE80211_HT_PARAM_CHA_SEC_BELOW: |
| 940 | rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; |
| 941 | break; |
| 942 | } |
| 943 | } else { |
| 944 | /* Note: control channel is opposite of extension channel */ |
| 945 | switch (ht_conf->extension_chan_offset) { |
| 946 | case IEEE80211_HT_PARAM_CHA_SEC_ABOVE: |
| 947 | rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); |
| 948 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED; |
| 949 | break; |
| 950 | case IEEE80211_HT_PARAM_CHA_SEC_BELOW: |
| 951 | rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; |
| 952 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED; |
| 953 | break; |
| 954 | case IEEE80211_HT_PARAM_CHA_SEC_NONE: |
| 955 | default: |
| 956 | /* channel location only valid if in Mixed mode */ |
| 957 | IWL_ERR(priv, "invalid extension channel offset\n"); |
| 958 | break; |
| 959 | } |
| 960 | } |
| 961 | } else { |
| 962 | rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY; |
| 963 | } |
| 964 | |
| 965 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
| 966 | priv->cfg->ops->hcmd->set_rxon_chain(priv); |
| 967 | |
| 968 | IWL_DEBUG_ASSOC(priv, "rxon flags 0x%X operation mode :0x%X " |
| 969 | "extension channel offset 0x%x\n", |
| 970 | le32_to_cpu(rxon->flags), ht_conf->ht_protection, |
| 971 | ht_conf->extension_chan_offset); |
| 972 | return; |
| 973 | } |
| 974 | EXPORT_SYMBOL(iwl_set_rxon_ht); |
| 975 | |
| 976 | #define IWL_NUM_RX_CHAINS_MULTIPLE 3 |
| 977 | #define IWL_NUM_RX_CHAINS_SINGLE 2 |
| 978 | #define IWL_NUM_IDLE_CHAINS_DUAL 2 |
| 979 | #define IWL_NUM_IDLE_CHAINS_SINGLE 1 |
| 980 | |
| 981 | /* |
| 982 | * Determine how many receiver/antenna chains to use. |
| 983 | * |
| 984 | * More provides better reception via diversity. Fewer saves power |
| 985 | * at the expense of throughput, but only when not in powersave to |
| 986 | * start with. |
| 987 | * |
| 988 | * MIMO (dual stream) requires at least 2, but works better with 3. |
| 989 | * This does not determine *which* chains to use, just how many. |
| 990 | */ |
| 991 | static int iwl_get_active_rx_chain_count(struct iwl_priv *priv) |
| 992 | { |
| 993 | /* # of Rx chains to use when expecting MIMO. */ |
| 994 | if (is_single_rx_stream(priv)) |
| 995 | return IWL_NUM_RX_CHAINS_SINGLE; |
| 996 | else |
| 997 | return IWL_NUM_RX_CHAINS_MULTIPLE; |
| 998 | } |
| 999 | |
| 1000 | /* |
| 1001 | * When we are in power saving mode, unless device support spatial |
| 1002 | * multiplexing power save, use the active count for rx chain count. |
| 1003 | */ |
| 1004 | static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt) |
| 1005 | { |
| 1006 | int idle_cnt = active_cnt; |
| 1007 | bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status); |
| 1008 | |
| 1009 | if (priv->cfg->support_sm_ps) { |
| 1010 | /* # Rx chains when idling and maybe trying to save power */ |
| 1011 | switch (priv->current_ht_config.sm_ps) { |
| 1012 | case WLAN_HT_CAP_SM_PS_STATIC: |
| 1013 | case WLAN_HT_CAP_SM_PS_DYNAMIC: |
| 1014 | idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL : |
| 1015 | IWL_NUM_IDLE_CHAINS_SINGLE; |
| 1016 | break; |
| 1017 | case WLAN_HT_CAP_SM_PS_DISABLED: |
| 1018 | idle_cnt = (is_cam) ? active_cnt : |
| 1019 | IWL_NUM_IDLE_CHAINS_SINGLE; |
| 1020 | break; |
| 1021 | case WLAN_HT_CAP_SM_PS_INVALID: |
| 1022 | default: |
| 1023 | IWL_ERR(priv, "invalid sm_ps mode %d\n", |
| 1024 | priv->current_ht_config.sm_ps); |
| 1025 | WARN_ON(1); |
| 1026 | break; |
| 1027 | } |
| 1028 | } |
| 1029 | return idle_cnt; |
| 1030 | } |
| 1031 | |
| 1032 | /* up to 4 chains */ |
| 1033 | static u8 iwl_count_chain_bitmap(u32 chain_bitmap) |
| 1034 | { |
| 1035 | u8 res; |
| 1036 | res = (chain_bitmap & BIT(0)) >> 0; |
| 1037 | res += (chain_bitmap & BIT(1)) >> 1; |
| 1038 | res += (chain_bitmap & BIT(2)) >> 2; |
| 1039 | res += (chain_bitmap & BIT(3)) >> 3; |
| 1040 | return res; |
| 1041 | } |
| 1042 | |
| 1043 | /** |
| 1044 | * iwl_is_monitor_mode - Determine if interface in monitor mode |
| 1045 | * |
| 1046 | * priv->iw_mode is set in add_interface, but add_interface is |
| 1047 | * never called for monitor mode. The only way mac80211 informs us about |
| 1048 | * monitor mode is through configuring filters (call to configure_filter). |
| 1049 | */ |
| 1050 | bool iwl_is_monitor_mode(struct iwl_priv *priv) |
| 1051 | { |
| 1052 | return !!(priv->staging_rxon.filter_flags & RXON_FILTER_PROMISC_MSK); |
| 1053 | } |
| 1054 | EXPORT_SYMBOL(iwl_is_monitor_mode); |
| 1055 | |
| 1056 | /** |
| 1057 | * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image |
| 1058 | * |
| 1059 | * Selects how many and which Rx receivers/antennas/chains to use. |
| 1060 | * This should not be used for scan command ... it puts data in wrong place. |
| 1061 | */ |
| 1062 | void iwl_set_rxon_chain(struct iwl_priv *priv) |
| 1063 | { |
| 1064 | bool is_single = is_single_rx_stream(priv); |
| 1065 | bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status); |
| 1066 | u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt; |
| 1067 | u32 active_chains; |
| 1068 | u16 rx_chain; |
| 1069 | |
| 1070 | /* Tell uCode which antennas are actually connected. |
| 1071 | * Before first association, we assume all antennas are connected. |
| 1072 | * Just after first association, iwl_chain_noise_calibration() |
| 1073 | * checks which antennas actually *are* connected. */ |
| 1074 | if (priv->chain_noise_data.active_chains) |
| 1075 | active_chains = priv->chain_noise_data.active_chains; |
| 1076 | else |
| 1077 | active_chains = priv->hw_params.valid_rx_ant; |
| 1078 | |
| 1079 | rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS; |
| 1080 | |
| 1081 | /* How many receivers should we use? */ |
| 1082 | active_rx_cnt = iwl_get_active_rx_chain_count(priv); |
| 1083 | idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt); |
| 1084 | |
| 1085 | |
| 1086 | /* correct rx chain count according hw settings |
| 1087 | * and chain noise calibration |
| 1088 | */ |
| 1089 | valid_rx_cnt = iwl_count_chain_bitmap(active_chains); |
| 1090 | if (valid_rx_cnt < active_rx_cnt) |
| 1091 | active_rx_cnt = valid_rx_cnt; |
| 1092 | |
| 1093 | if (valid_rx_cnt < idle_rx_cnt) |
| 1094 | idle_rx_cnt = valid_rx_cnt; |
| 1095 | |
| 1096 | rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS; |
| 1097 | rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS; |
| 1098 | |
| 1099 | /* copied from 'iwl_bg_request_scan()' */ |
| 1100 | /* Force use of chains B and C (0x6) for Rx for 4965 |
| 1101 | * Avoid A (0x1) because of its off-channel reception on A-band. |
| 1102 | * MIMO is not used here, but value is required */ |
| 1103 | if (iwl_is_monitor_mode(priv) && |
| 1104 | !(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) && |
| 1105 | ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)) { |
| 1106 | rx_chain = ANT_ABC << RXON_RX_CHAIN_VALID_POS; |
| 1107 | rx_chain |= ANT_BC << RXON_RX_CHAIN_FORCE_SEL_POS; |
| 1108 | rx_chain |= ANT_ABC << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS; |
| 1109 | rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS; |
| 1110 | } |
| 1111 | |
| 1112 | priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain); |
| 1113 | |
| 1114 | if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam) |
| 1115 | priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK; |
| 1116 | else |
| 1117 | priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK; |
| 1118 | |
| 1119 | IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n", |
| 1120 | priv->staging_rxon.rx_chain, |
| 1121 | active_rx_cnt, idle_rx_cnt); |
| 1122 | |
| 1123 | WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 || |
| 1124 | active_rx_cnt < idle_rx_cnt); |
| 1125 | } |
| 1126 | EXPORT_SYMBOL(iwl_set_rxon_chain); |
| 1127 | |
| 1128 | /** |
| 1129 | * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON |
| 1130 | * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz |
| 1131 | * @channel: Any channel valid for the requested phymode |
| 1132 | |
| 1133 | * In addition to setting the staging RXON, priv->phymode is also set. |
| 1134 | * |
| 1135 | * NOTE: Does not commit to the hardware; it sets appropriate bit fields |
| 1136 | * in the staging RXON flag structure based on the phymode |
| 1137 | */ |
| 1138 | int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch) |
| 1139 | { |
| 1140 | enum ieee80211_band band = ch->band; |
| 1141 | u16 channel = ieee80211_frequency_to_channel(ch->center_freq); |
| 1142 | |
| 1143 | if (!iwl_get_channel_info(priv, band, channel)) { |
| 1144 | IWL_DEBUG_INFO(priv, "Could not set channel to %d [%d]\n", |
| 1145 | channel, band); |
| 1146 | return -EINVAL; |
| 1147 | } |
| 1148 | |
| 1149 | if ((le16_to_cpu(priv->staging_rxon.channel) == channel) && |
| 1150 | (priv->band == band)) |
| 1151 | return 0; |
| 1152 | |
| 1153 | priv->staging_rxon.channel = cpu_to_le16(channel); |
| 1154 | if (band == IEEE80211_BAND_5GHZ) |
| 1155 | priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK; |
| 1156 | else |
| 1157 | priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK; |
| 1158 | |
| 1159 | priv->band = band; |
| 1160 | |
| 1161 | IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band); |
| 1162 | |
| 1163 | return 0; |
| 1164 | } |
| 1165 | EXPORT_SYMBOL(iwl_set_rxon_channel); |
| 1166 | |
| 1167 | void iwl_set_flags_for_band(struct iwl_priv *priv, |
| 1168 | enum ieee80211_band band) |
| 1169 | { |
| 1170 | if (band == IEEE80211_BAND_5GHZ) { |
| 1171 | priv->staging_rxon.flags &= |
| 1172 | ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
| 1173 | | RXON_FLG_CCK_MSK); |
| 1174 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; |
| 1175 | } else { |
| 1176 | /* Copied from iwl_post_associate() */ |
| 1177 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) |
| 1178 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; |
| 1179 | else |
| 1180 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
| 1181 | |
| 1182 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
| 1183 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
| 1184 | |
| 1185 | priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK; |
| 1186 | priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK; |
| 1187 | priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK; |
| 1188 | } |
| 1189 | } |
| 1190 | |
| 1191 | /* |
| 1192 | * initialize rxon structure with default values from eeprom |
| 1193 | */ |
| 1194 | void iwl_connection_init_rx_config(struct iwl_priv *priv, int mode) |
| 1195 | { |
| 1196 | const struct iwl_channel_info *ch_info; |
| 1197 | |
| 1198 | memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon)); |
| 1199 | |
| 1200 | switch (mode) { |
| 1201 | case NL80211_IFTYPE_AP: |
| 1202 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP; |
| 1203 | break; |
| 1204 | |
| 1205 | case NL80211_IFTYPE_STATION: |
| 1206 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS; |
| 1207 | priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK; |
| 1208 | break; |
| 1209 | |
| 1210 | case NL80211_IFTYPE_ADHOC: |
| 1211 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS; |
| 1212 | priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK; |
| 1213 | priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK | |
| 1214 | RXON_FILTER_ACCEPT_GRP_MSK; |
| 1215 | break; |
| 1216 | |
| 1217 | default: |
| 1218 | IWL_ERR(priv, "Unsupported interface type %d\n", mode); |
| 1219 | break; |
| 1220 | } |
| 1221 | |
| 1222 | #if 0 |
| 1223 | /* TODO: Figure out when short_preamble would be set and cache from |
| 1224 | * that */ |
| 1225 | if (!hw_to_local(priv->hw)->short_preamble) |
| 1226 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
| 1227 | else |
| 1228 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
| 1229 | #endif |
| 1230 | |
| 1231 | ch_info = iwl_get_channel_info(priv, priv->band, |
| 1232 | le16_to_cpu(priv->active_rxon.channel)); |
| 1233 | |
| 1234 | if (!ch_info) |
| 1235 | ch_info = &priv->channel_info[0]; |
| 1236 | |
| 1237 | /* |
| 1238 | * in some case A channels are all non IBSS |
| 1239 | * in this case force B/G channel |
| 1240 | */ |
| 1241 | if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) && |
| 1242 | !(is_channel_ibss(ch_info))) |
| 1243 | ch_info = &priv->channel_info[0]; |
| 1244 | |
| 1245 | priv->staging_rxon.channel = cpu_to_le16(ch_info->channel); |
| 1246 | priv->band = ch_info->band; |
| 1247 | |
| 1248 | iwl_set_flags_for_band(priv, priv->band); |
| 1249 | |
| 1250 | priv->staging_rxon.ofdm_basic_rates = |
| 1251 | (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; |
| 1252 | priv->staging_rxon.cck_basic_rates = |
| 1253 | (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; |
| 1254 | |
| 1255 | /* clear both MIX and PURE40 mode flag */ |
| 1256 | priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED | |
| 1257 | RXON_FLG_CHANNEL_MODE_PURE_40); |
| 1258 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
| 1259 | memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN); |
| 1260 | priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff; |
| 1261 | priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff; |
| 1262 | priv->staging_rxon.ofdm_ht_triple_stream_basic_rates = 0xff; |
| 1263 | } |
| 1264 | EXPORT_SYMBOL(iwl_connection_init_rx_config); |
| 1265 | |
| 1266 | static void iwl_set_rate(struct iwl_priv *priv) |
| 1267 | { |
| 1268 | const struct ieee80211_supported_band *hw = NULL; |
| 1269 | struct ieee80211_rate *rate; |
| 1270 | int i; |
| 1271 | |
| 1272 | hw = iwl_get_hw_mode(priv, priv->band); |
| 1273 | if (!hw) { |
| 1274 | IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n"); |
| 1275 | return; |
| 1276 | } |
| 1277 | |
| 1278 | priv->active_rate = 0; |
| 1279 | priv->active_rate_basic = 0; |
| 1280 | |
| 1281 | for (i = 0; i < hw->n_bitrates; i++) { |
| 1282 | rate = &(hw->bitrates[i]); |
| 1283 | if (rate->hw_value < IWL_RATE_COUNT_LEGACY) |
| 1284 | priv->active_rate |= (1 << rate->hw_value); |
| 1285 | } |
| 1286 | |
| 1287 | IWL_DEBUG_RATE(priv, "Set active_rate = %0x, active_rate_basic = %0x\n", |
| 1288 | priv->active_rate, priv->active_rate_basic); |
| 1289 | |
| 1290 | /* |
| 1291 | * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK) |
| 1292 | * otherwise set it to the default of all CCK rates and 6, 12, 24 for |
| 1293 | * OFDM |
| 1294 | */ |
| 1295 | if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK) |
| 1296 | priv->staging_rxon.cck_basic_rates = |
| 1297 | ((priv->active_rate_basic & |
| 1298 | IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF; |
| 1299 | else |
| 1300 | priv->staging_rxon.cck_basic_rates = |
| 1301 | (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; |
| 1302 | |
| 1303 | if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK) |
| 1304 | priv->staging_rxon.ofdm_basic_rates = |
| 1305 | ((priv->active_rate_basic & |
| 1306 | (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >> |
| 1307 | IWL_FIRST_OFDM_RATE) & 0xFF; |
| 1308 | else |
| 1309 | priv->staging_rxon.ofdm_basic_rates = |
| 1310 | (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; |
| 1311 | } |
| 1312 | |
| 1313 | void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) |
| 1314 | { |
| 1315 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
| 1316 | struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon; |
| 1317 | struct iwl_csa_notification *csa = &(pkt->u.csa_notif); |
| 1318 | |
| 1319 | if (priv->switch_rxon.switch_in_progress) { |
| 1320 | if (!le32_to_cpu(csa->status) && |
| 1321 | (csa->channel == priv->switch_rxon.channel)) { |
| 1322 | rxon->channel = csa->channel; |
| 1323 | priv->staging_rxon.channel = csa->channel; |
| 1324 | IWL_DEBUG_11H(priv, "CSA notif: channel %d\n", |
| 1325 | le16_to_cpu(csa->channel)); |
| 1326 | } else |
| 1327 | IWL_ERR(priv, "CSA notif (fail) : channel %d\n", |
| 1328 | le16_to_cpu(csa->channel)); |
| 1329 | |
| 1330 | priv->switch_rxon.switch_in_progress = false; |
| 1331 | } |
| 1332 | } |
| 1333 | EXPORT_SYMBOL(iwl_rx_csa); |
| 1334 | |
| 1335 | #ifdef CONFIG_IWLWIFI_DEBUG |
| 1336 | void iwl_print_rx_config_cmd(struct iwl_priv *priv) |
| 1337 | { |
| 1338 | struct iwl_rxon_cmd *rxon = &priv->staging_rxon; |
| 1339 | |
| 1340 | IWL_DEBUG_RADIO(priv, "RX CONFIG:\n"); |
| 1341 | iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon)); |
| 1342 | IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel)); |
| 1343 | IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags)); |
| 1344 | IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n", |
| 1345 | le32_to_cpu(rxon->filter_flags)); |
| 1346 | IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type); |
| 1347 | IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n", |
| 1348 | rxon->ofdm_basic_rates); |
| 1349 | IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates); |
| 1350 | IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr); |
| 1351 | IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr); |
| 1352 | IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id)); |
| 1353 | } |
| 1354 | EXPORT_SYMBOL(iwl_print_rx_config_cmd); |
| 1355 | #endif |
| 1356 | /** |
| 1357 | * iwl_irq_handle_error - called for HW or SW error interrupt from card |
| 1358 | */ |
| 1359 | void iwl_irq_handle_error(struct iwl_priv *priv) |
| 1360 | { |
| 1361 | /* Set the FW error flag -- cleared on iwl_down */ |
| 1362 | set_bit(STATUS_FW_ERROR, &priv->status); |
| 1363 | |
| 1364 | /* Cancel currently queued command. */ |
| 1365 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); |
| 1366 | |
| 1367 | #ifdef CONFIG_IWLWIFI_DEBUG |
| 1368 | if (iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) { |
| 1369 | priv->cfg->ops->lib->dump_nic_error_log(priv); |
| 1370 | priv->cfg->ops->lib->dump_nic_event_log(priv); |
| 1371 | iwl_print_rx_config_cmd(priv); |
| 1372 | } |
| 1373 | #endif |
| 1374 | |
| 1375 | wake_up_interruptible(&priv->wait_command_queue); |
| 1376 | |
| 1377 | /* Keep the restart process from trying to send host |
| 1378 | * commands by clearing the INIT status bit */ |
| 1379 | clear_bit(STATUS_READY, &priv->status); |
| 1380 | |
| 1381 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) { |
| 1382 | IWL_DEBUG(priv, IWL_DL_FW_ERRORS, |
| 1383 | "Restarting adapter due to uCode error.\n"); |
| 1384 | |
| 1385 | if (priv->cfg->mod_params->restart_fw) |
| 1386 | queue_work(priv->workqueue, &priv->restart); |
| 1387 | } |
| 1388 | } |
| 1389 | EXPORT_SYMBOL(iwl_irq_handle_error); |
| 1390 | |
| 1391 | int iwl_apm_stop_master(struct iwl_priv *priv) |
| 1392 | { |
| 1393 | int ret = 0; |
| 1394 | |
| 1395 | /* stop device's busmaster DMA activity */ |
| 1396 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); |
| 1397 | |
| 1398 | ret = iwl_poll_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED, |
| 1399 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); |
| 1400 | if (ret) |
| 1401 | IWL_WARN(priv, "Master Disable Timed Out, 100 usec\n"); |
| 1402 | |
| 1403 | IWL_DEBUG_INFO(priv, "stop master\n"); |
| 1404 | |
| 1405 | return ret; |
| 1406 | } |
| 1407 | EXPORT_SYMBOL(iwl_apm_stop_master); |
| 1408 | |
| 1409 | void iwl_apm_stop(struct iwl_priv *priv) |
| 1410 | { |
| 1411 | IWL_DEBUG_INFO(priv, "Stop card, put in low power state\n"); |
| 1412 | |
| 1413 | /* Stop device's DMA activity */ |
| 1414 | iwl_apm_stop_master(priv); |
| 1415 | |
| 1416 | /* Reset the entire device */ |
| 1417 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); |
| 1418 | |
| 1419 | udelay(10); |
| 1420 | |
| 1421 | /* |
| 1422 | * Clear "initialization complete" bit to move adapter from |
| 1423 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. |
| 1424 | */ |
| 1425 | iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); |
| 1426 | } |
| 1427 | EXPORT_SYMBOL(iwl_apm_stop); |
| 1428 | |
| 1429 | |
| 1430 | /* |
| 1431 | * Start up NIC's basic functionality after it has been reset |
| 1432 | * (e.g. after platform boot, or shutdown via iwl_apm_stop()) |
| 1433 | * NOTE: This does not load uCode nor start the embedded processor |
| 1434 | */ |
| 1435 | int iwl_apm_init(struct iwl_priv *priv) |
| 1436 | { |
| 1437 | int ret = 0; |
| 1438 | u16 lctl; |
| 1439 | |
| 1440 | IWL_DEBUG_INFO(priv, "Init card's basic functions\n"); |
| 1441 | |
| 1442 | /* |
| 1443 | * Use "set_bit" below rather than "write", to preserve any hardware |
| 1444 | * bits already set by default after reset. |
| 1445 | */ |
| 1446 | |
| 1447 | /* Disable L0S exit timer (platform NMI Work/Around) */ |
| 1448 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, |
| 1449 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); |
| 1450 | |
| 1451 | /* |
| 1452 | * Disable L0s without affecting L1; |
| 1453 | * don't wait for ICH L0s (ICH bug W/A) |
| 1454 | */ |
| 1455 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, |
| 1456 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); |
| 1457 | |
| 1458 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ |
| 1459 | iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); |
| 1460 | |
| 1461 | /* |
| 1462 | * Enable HAP INTA (interrupt from management bus) to |
| 1463 | * wake device's PCI Express link L1a -> L0s |
| 1464 | * NOTE: This is no-op for 3945 (non-existant bit) |
| 1465 | */ |
| 1466 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
| 1467 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); |
| 1468 | |
| 1469 | /* |
| 1470 | * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition. |
| 1471 | * Check if BIOS (or OS) enabled L1-ASPM on this device. |
| 1472 | * If so (likely), disable L0S, so device moves directly L0->L1; |
| 1473 | * costs negligible amount of power savings. |
| 1474 | * If not (unlikely), enable L0S, so there is at least some |
| 1475 | * power savings, even without L1. |
| 1476 | */ |
| 1477 | if (priv->cfg->set_l0s) { |
| 1478 | lctl = iwl_pcie_link_ctl(priv); |
| 1479 | if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == |
| 1480 | PCI_CFG_LINK_CTRL_VAL_L1_EN) { |
| 1481 | /* L1-ASPM enabled; disable(!) L0S */ |
| 1482 | iwl_set_bit(priv, CSR_GIO_REG, |
| 1483 | CSR_GIO_REG_VAL_L0S_ENABLED); |
| 1484 | IWL_DEBUG_POWER(priv, "L1 Enabled; Disabling L0S\n"); |
| 1485 | } else { |
| 1486 | /* L1-ASPM disabled; enable(!) L0S */ |
| 1487 | iwl_clear_bit(priv, CSR_GIO_REG, |
| 1488 | CSR_GIO_REG_VAL_L0S_ENABLED); |
| 1489 | IWL_DEBUG_POWER(priv, "L1 Disabled; Enabling L0S\n"); |
| 1490 | } |
| 1491 | } |
| 1492 | |
| 1493 | /* Configure analog phase-lock-loop before activating to D0A */ |
| 1494 | if (priv->cfg->pll_cfg_val) |
| 1495 | iwl_set_bit(priv, CSR_ANA_PLL_CFG, priv->cfg->pll_cfg_val); |
| 1496 | |
| 1497 | /* |
| 1498 | * Set "initialization complete" bit to move adapter from |
| 1499 | * D0U* --> D0A* (powered-up active) state. |
| 1500 | */ |
| 1501 | iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); |
| 1502 | |
| 1503 | /* |
| 1504 | * Wait for clock stabilization; once stabilized, access to |
| 1505 | * device-internal resources is supported, e.g. iwl_write_prph() |
| 1506 | * and accesses to uCode SRAM. |
| 1507 | */ |
| 1508 | ret = iwl_poll_bit(priv, CSR_GP_CNTRL, |
| 1509 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, |
| 1510 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); |
| 1511 | if (ret < 0) { |
| 1512 | IWL_DEBUG_INFO(priv, "Failed to init the card\n"); |
| 1513 | goto out; |
| 1514 | } |
| 1515 | |
| 1516 | /* |
| 1517 | * Enable DMA and BSM (if used) clocks, wait for them to stabilize. |
| 1518 | * BSM (Boostrap State Machine) is only in 3945 and 4965; |
| 1519 | * later devices (i.e. 5000 and later) have non-volatile SRAM, |
| 1520 | * and don't need BSM to restore data after power-saving sleep. |
| 1521 | * |
| 1522 | * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits |
| 1523 | * do not disable clocks. This preserves any hardware bits already |
| 1524 | * set by default in "CLK_CTRL_REG" after reset. |
| 1525 | */ |
| 1526 | if (priv->cfg->use_bsm) |
| 1527 | iwl_write_prph(priv, APMG_CLK_EN_REG, |
| 1528 | APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT); |
| 1529 | else |
| 1530 | iwl_write_prph(priv, APMG_CLK_EN_REG, |
| 1531 | APMG_CLK_VAL_DMA_CLK_RQT); |
| 1532 | udelay(20); |
| 1533 | |
| 1534 | /* Disable L1-Active */ |
| 1535 | iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, |
| 1536 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); |
| 1537 | |
| 1538 | out: |
| 1539 | return ret; |
| 1540 | } |
| 1541 | EXPORT_SYMBOL(iwl_apm_init); |
| 1542 | |
| 1543 | |
| 1544 | |
| 1545 | void iwl_configure_filter(struct ieee80211_hw *hw, |
| 1546 | unsigned int changed_flags, |
| 1547 | unsigned int *total_flags, |
| 1548 | u64 multicast) |
| 1549 | { |
| 1550 | struct iwl_priv *priv = hw->priv; |
| 1551 | __le32 *filter_flags = &priv->staging_rxon.filter_flags; |
| 1552 | |
| 1553 | IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n", |
| 1554 | changed_flags, *total_flags); |
| 1555 | |
| 1556 | if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) { |
| 1557 | if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) |
| 1558 | *filter_flags |= RXON_FILTER_PROMISC_MSK; |
| 1559 | else |
| 1560 | *filter_flags &= ~RXON_FILTER_PROMISC_MSK; |
| 1561 | } |
| 1562 | if (changed_flags & FIF_ALLMULTI) { |
| 1563 | if (*total_flags & FIF_ALLMULTI) |
| 1564 | *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK; |
| 1565 | else |
| 1566 | *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK; |
| 1567 | } |
| 1568 | if (changed_flags & FIF_CONTROL) { |
| 1569 | if (*total_flags & FIF_CONTROL) |
| 1570 | *filter_flags |= RXON_FILTER_CTL2HOST_MSK; |
| 1571 | else |
| 1572 | *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK; |
| 1573 | } |
| 1574 | if (changed_flags & FIF_BCN_PRBRESP_PROMISC) { |
| 1575 | if (*total_flags & FIF_BCN_PRBRESP_PROMISC) |
| 1576 | *filter_flags |= RXON_FILTER_BCON_AWARE_MSK; |
| 1577 | else |
| 1578 | *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK; |
| 1579 | } |
| 1580 | |
| 1581 | /* We avoid iwl_commit_rxon here to commit the new filter flags |
| 1582 | * since mac80211 will call ieee80211_hw_config immediately. |
| 1583 | * (mc_list is not supported at this time). Otherwise, we need to |
| 1584 | * queue a background iwl_commit_rxon work. |
| 1585 | */ |
| 1586 | |
| 1587 | *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS | |
| 1588 | FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL; |
| 1589 | } |
| 1590 | EXPORT_SYMBOL(iwl_configure_filter); |
| 1591 | |
| 1592 | int iwl_set_hw_params(struct iwl_priv *priv) |
| 1593 | { |
| 1594 | priv->hw_params.max_rxq_size = RX_QUEUE_SIZE; |
| 1595 | priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG; |
| 1596 | if (priv->cfg->mod_params->amsdu_size_8K) |
| 1597 | priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K); |
| 1598 | else |
| 1599 | priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K); |
| 1600 | |
| 1601 | priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL; |
| 1602 | |
| 1603 | if (priv->cfg->mod_params->disable_11n) |
| 1604 | priv->cfg->sku &= ~IWL_SKU_N; |
| 1605 | |
| 1606 | /* Device-specific setup */ |
| 1607 | return priv->cfg->ops->lib->set_hw_params(priv); |
| 1608 | } |
| 1609 | EXPORT_SYMBOL(iwl_set_hw_params); |
| 1610 | |
| 1611 | int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force) |
| 1612 | { |
| 1613 | int ret = 0; |
| 1614 | s8 prev_tx_power = priv->tx_power_user_lmt; |
| 1615 | |
| 1616 | if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) { |
| 1617 | IWL_WARN(priv, "Requested user TXPOWER %d below lower limit %d.\n", |
| 1618 | tx_power, |
| 1619 | IWL_TX_POWER_TARGET_POWER_MIN); |
| 1620 | return -EINVAL; |
| 1621 | } |
| 1622 | |
| 1623 | if (tx_power > priv->tx_power_device_lmt) { |
| 1624 | IWL_WARN(priv, |
| 1625 | "Requested user TXPOWER %d above upper limit %d.\n", |
| 1626 | tx_power, priv->tx_power_device_lmt); |
| 1627 | return -EINVAL; |
| 1628 | } |
| 1629 | |
| 1630 | if (priv->tx_power_user_lmt != tx_power) |
| 1631 | force = true; |
| 1632 | |
| 1633 | /* if nic is not up don't send command */ |
| 1634 | if (iwl_is_ready_rf(priv)) { |
| 1635 | priv->tx_power_user_lmt = tx_power; |
| 1636 | if (force && priv->cfg->ops->lib->send_tx_power) |
| 1637 | ret = priv->cfg->ops->lib->send_tx_power(priv); |
| 1638 | else if (!priv->cfg->ops->lib->send_tx_power) |
| 1639 | ret = -EOPNOTSUPP; |
| 1640 | /* |
| 1641 | * if fail to set tx_power, restore the orig. tx power |
| 1642 | */ |
| 1643 | if (ret) |
| 1644 | priv->tx_power_user_lmt = prev_tx_power; |
| 1645 | } |
| 1646 | |
| 1647 | /* |
| 1648 | * Even this is an async host command, the command |
| 1649 | * will always report success from uCode |
| 1650 | * So once driver can placing the command into the queue |
| 1651 | * successfully, driver can use priv->tx_power_user_lmt |
| 1652 | * to reflect the current tx power |
| 1653 | */ |
| 1654 | return ret; |
| 1655 | } |
| 1656 | EXPORT_SYMBOL(iwl_set_tx_power); |
| 1657 | |
| 1658 | #define ICT_COUNT (PAGE_SIZE/sizeof(u32)) |
| 1659 | |
| 1660 | /* Free dram table */ |
| 1661 | void iwl_free_isr_ict(struct iwl_priv *priv) |
| 1662 | { |
| 1663 | if (priv->ict_tbl_vir) { |
| 1664 | pci_free_consistent(priv->pci_dev, (sizeof(u32) * ICT_COUNT) + |
| 1665 | PAGE_SIZE, priv->ict_tbl_vir, |
| 1666 | priv->ict_tbl_dma); |
| 1667 | priv->ict_tbl_vir = NULL; |
| 1668 | } |
| 1669 | } |
| 1670 | EXPORT_SYMBOL(iwl_free_isr_ict); |
| 1671 | |
| 1672 | |
| 1673 | /* allocate dram shared table it is a PAGE_SIZE aligned |
| 1674 | * also reset all data related to ICT table interrupt. |
| 1675 | */ |
| 1676 | int iwl_alloc_isr_ict(struct iwl_priv *priv) |
| 1677 | { |
| 1678 | |
| 1679 | if (priv->cfg->use_isr_legacy) |
| 1680 | return 0; |
| 1681 | /* allocate shrared data table */ |
| 1682 | priv->ict_tbl_vir = pci_alloc_consistent(priv->pci_dev, (sizeof(u32) * |
| 1683 | ICT_COUNT) + PAGE_SIZE, |
| 1684 | &priv->ict_tbl_dma); |
| 1685 | if (!priv->ict_tbl_vir) |
| 1686 | return -ENOMEM; |
| 1687 | |
| 1688 | /* align table to PAGE_SIZE boundry */ |
| 1689 | priv->aligned_ict_tbl_dma = ALIGN(priv->ict_tbl_dma, PAGE_SIZE); |
| 1690 | |
| 1691 | IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n", |
| 1692 | (unsigned long long)priv->ict_tbl_dma, |
| 1693 | (unsigned long long)priv->aligned_ict_tbl_dma, |
| 1694 | (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma)); |
| 1695 | |
| 1696 | priv->ict_tbl = priv->ict_tbl_vir + |
| 1697 | (priv->aligned_ict_tbl_dma - priv->ict_tbl_dma); |
| 1698 | |
| 1699 | IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n", |
| 1700 | priv->ict_tbl, priv->ict_tbl_vir, |
| 1701 | (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma)); |
| 1702 | |
| 1703 | /* reset table and index to all 0 */ |
| 1704 | memset(priv->ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE); |
| 1705 | priv->ict_index = 0; |
| 1706 | |
| 1707 | /* add periodic RX interrupt */ |
| 1708 | priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC; |
| 1709 | return 0; |
| 1710 | } |
| 1711 | EXPORT_SYMBOL(iwl_alloc_isr_ict); |
| 1712 | |
| 1713 | /* Device is going up inform it about using ICT interrupt table, |
| 1714 | * also we need to tell the driver to start using ICT interrupt. |
| 1715 | */ |
| 1716 | int iwl_reset_ict(struct iwl_priv *priv) |
| 1717 | { |
| 1718 | u32 val; |
| 1719 | unsigned long flags; |
| 1720 | |
| 1721 | if (!priv->ict_tbl_vir) |
| 1722 | return 0; |
| 1723 | |
| 1724 | spin_lock_irqsave(&priv->lock, flags); |
| 1725 | iwl_disable_interrupts(priv); |
| 1726 | |
| 1727 | memset(&priv->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT); |
| 1728 | |
| 1729 | val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT; |
| 1730 | |
| 1731 | val |= CSR_DRAM_INT_TBL_ENABLE; |
| 1732 | val |= CSR_DRAM_INIT_TBL_WRAP_CHECK; |
| 1733 | |
| 1734 | IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X " |
| 1735 | "aligned dma address %Lx\n", |
| 1736 | val, (unsigned long long)priv->aligned_ict_tbl_dma); |
| 1737 | |
| 1738 | iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val); |
| 1739 | priv->use_ict = true; |
| 1740 | priv->ict_index = 0; |
| 1741 | iwl_write32(priv, CSR_INT, priv->inta_mask); |
| 1742 | iwl_enable_interrupts(priv); |
| 1743 | spin_unlock_irqrestore(&priv->lock, flags); |
| 1744 | |
| 1745 | return 0; |
| 1746 | } |
| 1747 | EXPORT_SYMBOL(iwl_reset_ict); |
| 1748 | |
| 1749 | /* Device is going down disable ict interrupt usage */ |
| 1750 | void iwl_disable_ict(struct iwl_priv *priv) |
| 1751 | { |
| 1752 | unsigned long flags; |
| 1753 | |
| 1754 | spin_lock_irqsave(&priv->lock, flags); |
| 1755 | priv->use_ict = false; |
| 1756 | spin_unlock_irqrestore(&priv->lock, flags); |
| 1757 | } |
| 1758 | EXPORT_SYMBOL(iwl_disable_ict); |
| 1759 | |
| 1760 | /* interrupt handler using ict table, with this interrupt driver will |
| 1761 | * stop using INTA register to get device's interrupt, reading this register |
| 1762 | * is expensive, device will write interrupts in ICT dram table, increment |
| 1763 | * index then will fire interrupt to driver, driver will OR all ICT table |
| 1764 | * entries from current index up to table entry with 0 value. the result is |
| 1765 | * the interrupt we need to service, driver will set the entries back to 0 and |
| 1766 | * set index. |
| 1767 | */ |
| 1768 | irqreturn_t iwl_isr_ict(int irq, void *data) |
| 1769 | { |
| 1770 | struct iwl_priv *priv = data; |
| 1771 | u32 inta, inta_mask; |
| 1772 | u32 val = 0; |
| 1773 | |
| 1774 | if (!priv) |
| 1775 | return IRQ_NONE; |
| 1776 | |
| 1777 | /* dram interrupt table not set yet, |
| 1778 | * use legacy interrupt. |
| 1779 | */ |
| 1780 | if (!priv->use_ict) |
| 1781 | return iwl_isr(irq, data); |
| 1782 | |
| 1783 | spin_lock(&priv->lock); |
| 1784 | |
| 1785 | /* Disable (but don't clear!) interrupts here to avoid |
| 1786 | * back-to-back ISRs and sporadic interrupts from our NIC. |
| 1787 | * If we have something to service, the tasklet will re-enable ints. |
| 1788 | * If we *don't* have something, we'll re-enable before leaving here. |
| 1789 | */ |
| 1790 | inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */ |
| 1791 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); |
| 1792 | |
| 1793 | |
| 1794 | /* Ignore interrupt if there's nothing in NIC to service. |
| 1795 | * This may be due to IRQ shared with another device, |
| 1796 | * or due to sporadic interrupts thrown from our NIC. */ |
| 1797 | if (!priv->ict_tbl[priv->ict_index]) { |
| 1798 | IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n"); |
| 1799 | goto none; |
| 1800 | } |
| 1801 | |
| 1802 | /* read all entries that not 0 start with ict_index */ |
| 1803 | while (priv->ict_tbl[priv->ict_index]) { |
| 1804 | |
| 1805 | val |= le32_to_cpu(priv->ict_tbl[priv->ict_index]); |
| 1806 | IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n", |
| 1807 | priv->ict_index, |
| 1808 | le32_to_cpu(priv->ict_tbl[priv->ict_index])); |
| 1809 | priv->ict_tbl[priv->ict_index] = 0; |
| 1810 | priv->ict_index = iwl_queue_inc_wrap(priv->ict_index, |
| 1811 | ICT_COUNT); |
| 1812 | |
| 1813 | } |
| 1814 | |
| 1815 | /* We should not get this value, just ignore it. */ |
| 1816 | if (val == 0xffffffff) |
| 1817 | val = 0; |
| 1818 | |
| 1819 | inta = (0xff & val) | ((0xff00 & val) << 16); |
| 1820 | IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n", |
| 1821 | inta, inta_mask, val); |
| 1822 | |
| 1823 | inta &= priv->inta_mask; |
| 1824 | priv->inta |= inta; |
| 1825 | |
| 1826 | /* iwl_irq_tasklet() will service interrupts and re-enable them */ |
| 1827 | if (likely(inta)) |
| 1828 | tasklet_schedule(&priv->irq_tasklet); |
| 1829 | else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) { |
| 1830 | /* Allow interrupt if was disabled by this handler and |
| 1831 | * no tasklet was schedules, We should not enable interrupt, |
| 1832 | * tasklet will enable it. |
| 1833 | */ |
| 1834 | iwl_enable_interrupts(priv); |
| 1835 | } |
| 1836 | |
| 1837 | spin_unlock(&priv->lock); |
| 1838 | return IRQ_HANDLED; |
| 1839 | |
| 1840 | none: |
| 1841 | /* re-enable interrupts here since we don't have anything to service. |
| 1842 | * only Re-enable if disabled by irq. |
| 1843 | */ |
| 1844 | if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) |
| 1845 | iwl_enable_interrupts(priv); |
| 1846 | |
| 1847 | spin_unlock(&priv->lock); |
| 1848 | return IRQ_NONE; |
| 1849 | } |
| 1850 | EXPORT_SYMBOL(iwl_isr_ict); |
| 1851 | |
| 1852 | |
| 1853 | static irqreturn_t iwl_isr(int irq, void *data) |
| 1854 | { |
| 1855 | struct iwl_priv *priv = data; |
| 1856 | u32 inta, inta_mask; |
| 1857 | #ifdef CONFIG_IWLWIFI_DEBUG |
| 1858 | u32 inta_fh; |
| 1859 | #endif |
| 1860 | if (!priv) |
| 1861 | return IRQ_NONE; |
| 1862 | |
| 1863 | spin_lock(&priv->lock); |
| 1864 | |
| 1865 | /* Disable (but don't clear!) interrupts here to avoid |
| 1866 | * back-to-back ISRs and sporadic interrupts from our NIC. |
| 1867 | * If we have something to service, the tasklet will re-enable ints. |
| 1868 | * If we *don't* have something, we'll re-enable before leaving here. */ |
| 1869 | inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */ |
| 1870 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); |
| 1871 | |
| 1872 | /* Discover which interrupts are active/pending */ |
| 1873 | inta = iwl_read32(priv, CSR_INT); |
| 1874 | |
| 1875 | /* Ignore interrupt if there's nothing in NIC to service. |
| 1876 | * This may be due to IRQ shared with another device, |
| 1877 | * or due to sporadic interrupts thrown from our NIC. */ |
| 1878 | if (!inta) { |
| 1879 | IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n"); |
| 1880 | goto none; |
| 1881 | } |
| 1882 | |
| 1883 | if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { |
| 1884 | /* Hardware disappeared. It might have already raised |
| 1885 | * an interrupt */ |
| 1886 | IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta); |
| 1887 | goto unplugged; |
| 1888 | } |
| 1889 | |
| 1890 | #ifdef CONFIG_IWLWIFI_DEBUG |
| 1891 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
| 1892 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
| 1893 | IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, " |
| 1894 | "fh 0x%08x\n", inta, inta_mask, inta_fh); |
| 1895 | } |
| 1896 | #endif |
| 1897 | |
| 1898 | priv->inta |= inta; |
| 1899 | /* iwl_irq_tasklet() will service interrupts and re-enable them */ |
| 1900 | if (likely(inta)) |
| 1901 | tasklet_schedule(&priv->irq_tasklet); |
| 1902 | else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) |
| 1903 | iwl_enable_interrupts(priv); |
| 1904 | |
| 1905 | unplugged: |
| 1906 | spin_unlock(&priv->lock); |
| 1907 | return IRQ_HANDLED; |
| 1908 | |
| 1909 | none: |
| 1910 | /* re-enable interrupts here since we don't have anything to service. */ |
| 1911 | /* only Re-enable if diabled by irq and no schedules tasklet. */ |
| 1912 | if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) |
| 1913 | iwl_enable_interrupts(priv); |
| 1914 | |
| 1915 | spin_unlock(&priv->lock); |
| 1916 | return IRQ_NONE; |
| 1917 | } |
| 1918 | |
| 1919 | irqreturn_t iwl_isr_legacy(int irq, void *data) |
| 1920 | { |
| 1921 | struct iwl_priv *priv = data; |
| 1922 | u32 inta, inta_mask; |
| 1923 | u32 inta_fh; |
| 1924 | if (!priv) |
| 1925 | return IRQ_NONE; |
| 1926 | |
| 1927 | spin_lock(&priv->lock); |
| 1928 | |
| 1929 | /* Disable (but don't clear!) interrupts here to avoid |
| 1930 | * back-to-back ISRs and sporadic interrupts from our NIC. |
| 1931 | * If we have something to service, the tasklet will re-enable ints. |
| 1932 | * If we *don't* have something, we'll re-enable before leaving here. */ |
| 1933 | inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */ |
| 1934 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); |
| 1935 | |
| 1936 | /* Discover which interrupts are active/pending */ |
| 1937 | inta = iwl_read32(priv, CSR_INT); |
| 1938 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
| 1939 | |
| 1940 | /* Ignore interrupt if there's nothing in NIC to service. |
| 1941 | * This may be due to IRQ shared with another device, |
| 1942 | * or due to sporadic interrupts thrown from our NIC. */ |
| 1943 | if (!inta && !inta_fh) { |
| 1944 | IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n"); |
| 1945 | goto none; |
| 1946 | } |
| 1947 | |
| 1948 | if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { |
| 1949 | /* Hardware disappeared. It might have already raised |
| 1950 | * an interrupt */ |
| 1951 | IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta); |
| 1952 | goto unplugged; |
| 1953 | } |
| 1954 | |
| 1955 | IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
| 1956 | inta, inta_mask, inta_fh); |
| 1957 | |
| 1958 | inta &= ~CSR_INT_BIT_SCD; |
| 1959 | |
| 1960 | /* iwl_irq_tasklet() will service interrupts and re-enable them */ |
| 1961 | if (likely(inta || inta_fh)) |
| 1962 | tasklet_schedule(&priv->irq_tasklet); |
| 1963 | |
| 1964 | unplugged: |
| 1965 | spin_unlock(&priv->lock); |
| 1966 | return IRQ_HANDLED; |
| 1967 | |
| 1968 | none: |
| 1969 | /* re-enable interrupts here since we don't have anything to service. */ |
| 1970 | /* only Re-enable if diabled by irq */ |
| 1971 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) |
| 1972 | iwl_enable_interrupts(priv); |
| 1973 | spin_unlock(&priv->lock); |
| 1974 | return IRQ_NONE; |
| 1975 | } |
| 1976 | EXPORT_SYMBOL(iwl_isr_legacy); |
| 1977 | |
| 1978 | int iwl_send_bt_config(struct iwl_priv *priv) |
| 1979 | { |
| 1980 | struct iwl_bt_cmd bt_cmd = { |
| 1981 | .flags = BT_COEX_MODE_4W, |
| 1982 | .lead_time = BT_LEAD_TIME_DEF, |
| 1983 | .max_kill = BT_MAX_KILL_DEF, |
| 1984 | .kill_ack_mask = 0, |
| 1985 | .kill_cts_mask = 0, |
| 1986 | }; |
| 1987 | |
| 1988 | return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG, |
| 1989 | sizeof(struct iwl_bt_cmd), &bt_cmd); |
| 1990 | } |
| 1991 | EXPORT_SYMBOL(iwl_send_bt_config); |
| 1992 | |
| 1993 | int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags) |
| 1994 | { |
| 1995 | u32 stat_flags = 0; |
| 1996 | struct iwl_host_cmd cmd = { |
| 1997 | .id = REPLY_STATISTICS_CMD, |
| 1998 | .flags = flags, |
| 1999 | .len = sizeof(stat_flags), |
| 2000 | .data = (u8 *) &stat_flags, |
| 2001 | }; |
| 2002 | return iwl_send_cmd(priv, &cmd); |
| 2003 | } |
| 2004 | EXPORT_SYMBOL(iwl_send_statistics_request); |
| 2005 | |
| 2006 | /** |
| 2007 | * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host, |
| 2008 | * using sample data 100 bytes apart. If these sample points are good, |
| 2009 | * it's a pretty good bet that everything between them is good, too. |
| 2010 | */ |
| 2011 | static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len) |
| 2012 | { |
| 2013 | u32 val; |
| 2014 | int ret = 0; |
| 2015 | u32 errcnt = 0; |
| 2016 | u32 i; |
| 2017 | |
| 2018 | IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len); |
| 2019 | |
| 2020 | for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { |
| 2021 | /* read data comes through single port, auto-incr addr */ |
| 2022 | /* NOTE: Use the debugless read so we don't flood kernel log |
| 2023 | * if IWL_DL_IO is set */ |
| 2024 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
| 2025 | i + IWL49_RTC_INST_LOWER_BOUND); |
| 2026 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
| 2027 | if (val != le32_to_cpu(*image)) { |
| 2028 | ret = -EIO; |
| 2029 | errcnt++; |
| 2030 | if (errcnt >= 3) |
| 2031 | break; |
| 2032 | } |
| 2033 | } |
| 2034 | |
| 2035 | return ret; |
| 2036 | } |
| 2037 | |
| 2038 | /** |
| 2039 | * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host, |
| 2040 | * looking at all data. |
| 2041 | */ |
| 2042 | static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image, |
| 2043 | u32 len) |
| 2044 | { |
| 2045 | u32 val; |
| 2046 | u32 save_len = len; |
| 2047 | int ret = 0; |
| 2048 | u32 errcnt; |
| 2049 | |
| 2050 | IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len); |
| 2051 | |
| 2052 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
| 2053 | IWL49_RTC_INST_LOWER_BOUND); |
| 2054 | |
| 2055 | errcnt = 0; |
| 2056 | for (; len > 0; len -= sizeof(u32), image++) { |
| 2057 | /* read data comes through single port, auto-incr addr */ |
| 2058 | /* NOTE: Use the debugless read so we don't flood kernel log |
| 2059 | * if IWL_DL_IO is set */ |
| 2060 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
| 2061 | if (val != le32_to_cpu(*image)) { |
| 2062 | IWL_ERR(priv, "uCode INST section is invalid at " |
| 2063 | "offset 0x%x, is 0x%x, s/b 0x%x\n", |
| 2064 | save_len - len, val, le32_to_cpu(*image)); |
| 2065 | ret = -EIO; |
| 2066 | errcnt++; |
| 2067 | if (errcnt >= 20) |
| 2068 | break; |
| 2069 | } |
| 2070 | } |
| 2071 | |
| 2072 | if (!errcnt) |
| 2073 | IWL_DEBUG_INFO(priv, |
| 2074 | "ucode image in INSTRUCTION memory is good\n"); |
| 2075 | |
| 2076 | return ret; |
| 2077 | } |
| 2078 | |
| 2079 | /** |
| 2080 | * iwl_verify_ucode - determine which instruction image is in SRAM, |
| 2081 | * and verify its contents |
| 2082 | */ |
| 2083 | int iwl_verify_ucode(struct iwl_priv *priv) |
| 2084 | { |
| 2085 | __le32 *image; |
| 2086 | u32 len; |
| 2087 | int ret; |
| 2088 | |
| 2089 | /* Try bootstrap */ |
| 2090 | image = (__le32 *)priv->ucode_boot.v_addr; |
| 2091 | len = priv->ucode_boot.len; |
| 2092 | ret = iwlcore_verify_inst_sparse(priv, image, len); |
| 2093 | if (!ret) { |
| 2094 | IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n"); |
| 2095 | return 0; |
| 2096 | } |
| 2097 | |
| 2098 | /* Try initialize */ |
| 2099 | image = (__le32 *)priv->ucode_init.v_addr; |
| 2100 | len = priv->ucode_init.len; |
| 2101 | ret = iwlcore_verify_inst_sparse(priv, image, len); |
| 2102 | if (!ret) { |
| 2103 | IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n"); |
| 2104 | return 0; |
| 2105 | } |
| 2106 | |
| 2107 | /* Try runtime/protocol */ |
| 2108 | image = (__le32 *)priv->ucode_code.v_addr; |
| 2109 | len = priv->ucode_code.len; |
| 2110 | ret = iwlcore_verify_inst_sparse(priv, image, len); |
| 2111 | if (!ret) { |
| 2112 | IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n"); |
| 2113 | return 0; |
| 2114 | } |
| 2115 | |
| 2116 | IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n"); |
| 2117 | |
| 2118 | /* Since nothing seems to match, show first several data entries in |
| 2119 | * instruction SRAM, so maybe visual inspection will give a clue. |
| 2120 | * Selection of bootstrap image (vs. other images) is arbitrary. */ |
| 2121 | image = (__le32 *)priv->ucode_boot.v_addr; |
| 2122 | len = priv->ucode_boot.len; |
| 2123 | ret = iwl_verify_inst_full(priv, image, len); |
| 2124 | |
| 2125 | return ret; |
| 2126 | } |
| 2127 | EXPORT_SYMBOL(iwl_verify_ucode); |
| 2128 | |
| 2129 | |
| 2130 | void iwl_rf_kill_ct_config(struct iwl_priv *priv) |
| 2131 | { |
| 2132 | struct iwl_ct_kill_config cmd; |
| 2133 | struct iwl_ct_kill_throttling_config adv_cmd; |
| 2134 | unsigned long flags; |
| 2135 | int ret = 0; |
| 2136 | |
| 2137 | spin_lock_irqsave(&priv->lock, flags); |
| 2138 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, |
| 2139 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); |
| 2140 | spin_unlock_irqrestore(&priv->lock, flags); |
| 2141 | priv->thermal_throttle.ct_kill_toggle = false; |
| 2142 | |
| 2143 | if (priv->cfg->support_ct_kill_exit) { |
| 2144 | adv_cmd.critical_temperature_enter = |
| 2145 | cpu_to_le32(priv->hw_params.ct_kill_threshold); |
| 2146 | adv_cmd.critical_temperature_exit = |
| 2147 | cpu_to_le32(priv->hw_params.ct_kill_exit_threshold); |
| 2148 | |
| 2149 | ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD, |
| 2150 | sizeof(adv_cmd), &adv_cmd); |
| 2151 | if (ret) |
| 2152 | IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n"); |
| 2153 | else |
| 2154 | IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD " |
| 2155 | "succeeded, " |
| 2156 | "critical temperature enter is %d," |
| 2157 | "exit is %d\n", |
| 2158 | priv->hw_params.ct_kill_threshold, |
| 2159 | priv->hw_params.ct_kill_exit_threshold); |
| 2160 | } else { |
| 2161 | cmd.critical_temperature_R = |
| 2162 | cpu_to_le32(priv->hw_params.ct_kill_threshold); |
| 2163 | |
| 2164 | ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD, |
| 2165 | sizeof(cmd), &cmd); |
| 2166 | if (ret) |
| 2167 | IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n"); |
| 2168 | else |
| 2169 | IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD " |
| 2170 | "succeeded, " |
| 2171 | "critical temperature is %d\n", |
| 2172 | priv->hw_params.ct_kill_threshold); |
| 2173 | } |
| 2174 | } |
| 2175 | EXPORT_SYMBOL(iwl_rf_kill_ct_config); |
| 2176 | |
| 2177 | |
| 2178 | /* |
| 2179 | * CARD_STATE_CMD |
| 2180 | * |
| 2181 | * Use: Sets the device's internal card state to enable, disable, or halt |
| 2182 | * |
| 2183 | * When in the 'enable' state the card operates as normal. |
| 2184 | * When in the 'disable' state, the card enters into a low power mode. |
| 2185 | * When in the 'halt' state, the card is shut down and must be fully |
| 2186 | * restarted to come back on. |
| 2187 | */ |
| 2188 | int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag) |
| 2189 | { |
| 2190 | struct iwl_host_cmd cmd = { |
| 2191 | .id = REPLY_CARD_STATE_CMD, |
| 2192 | .len = sizeof(u32), |
| 2193 | .data = &flags, |
| 2194 | .flags = meta_flag, |
| 2195 | }; |
| 2196 | |
| 2197 | return iwl_send_cmd(priv, &cmd); |
| 2198 | } |
| 2199 | |
| 2200 | void iwl_rx_pm_sleep_notif(struct iwl_priv *priv, |
| 2201 | struct iwl_rx_mem_buffer *rxb) |
| 2202 | { |
| 2203 | #ifdef CONFIG_IWLWIFI_DEBUG |
| 2204 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
| 2205 | struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif); |
| 2206 | IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n", |
| 2207 | sleep->pm_sleep_mode, sleep->pm_wakeup_src); |
| 2208 | #endif |
| 2209 | } |
| 2210 | EXPORT_SYMBOL(iwl_rx_pm_sleep_notif); |
| 2211 | |
| 2212 | void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv, |
| 2213 | struct iwl_rx_mem_buffer *rxb) |
| 2214 | { |
| 2215 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
| 2216 | u32 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; |
| 2217 | IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled " |
| 2218 | "notification for %s:\n", len, |
| 2219 | get_cmd_string(pkt->hdr.cmd)); |
| 2220 | iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, len); |
| 2221 | } |
| 2222 | EXPORT_SYMBOL(iwl_rx_pm_debug_statistics_notif); |
| 2223 | |
| 2224 | void iwl_rx_reply_error(struct iwl_priv *priv, |
| 2225 | struct iwl_rx_mem_buffer *rxb) |
| 2226 | { |
| 2227 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
| 2228 | |
| 2229 | IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) " |
| 2230 | "seq 0x%04X ser 0x%08X\n", |
| 2231 | le32_to_cpu(pkt->u.err_resp.error_type), |
| 2232 | get_cmd_string(pkt->u.err_resp.cmd_id), |
| 2233 | pkt->u.err_resp.cmd_id, |
| 2234 | le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num), |
| 2235 | le32_to_cpu(pkt->u.err_resp.error_info)); |
| 2236 | } |
| 2237 | EXPORT_SYMBOL(iwl_rx_reply_error); |
| 2238 | |
| 2239 | void iwl_clear_isr_stats(struct iwl_priv *priv) |
| 2240 | { |
| 2241 | memset(&priv->isr_stats, 0, sizeof(priv->isr_stats)); |
| 2242 | } |
| 2243 | |
| 2244 | int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue, |
| 2245 | const struct ieee80211_tx_queue_params *params) |
| 2246 | { |
| 2247 | struct iwl_priv *priv = hw->priv; |
| 2248 | unsigned long flags; |
| 2249 | int q; |
| 2250 | |
| 2251 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
| 2252 | |
| 2253 | if (!iwl_is_ready_rf(priv)) { |
| 2254 | IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n"); |
| 2255 | return -EIO; |
| 2256 | } |
| 2257 | |
| 2258 | if (queue >= AC_NUM) { |
| 2259 | IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue); |
| 2260 | return 0; |
| 2261 | } |
| 2262 | |
| 2263 | q = AC_NUM - 1 - queue; |
| 2264 | |
| 2265 | spin_lock_irqsave(&priv->lock, flags); |
| 2266 | |
| 2267 | priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min); |
| 2268 | priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max); |
| 2269 | priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs; |
| 2270 | priv->qos_data.def_qos_parm.ac[q].edca_txop = |
| 2271 | cpu_to_le16((params->txop * 32)); |
| 2272 | |
| 2273 | priv->qos_data.def_qos_parm.ac[q].reserved1 = 0; |
| 2274 | priv->qos_data.qos_active = 1; |
| 2275 | |
| 2276 | if (priv->iw_mode == NL80211_IFTYPE_AP) |
| 2277 | iwl_activate_qos(priv, 1); |
| 2278 | else if (priv->assoc_id && iwl_is_associated(priv)) |
| 2279 | iwl_activate_qos(priv, 0); |
| 2280 | |
| 2281 | spin_unlock_irqrestore(&priv->lock, flags); |
| 2282 | |
| 2283 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
| 2284 | return 0; |
| 2285 | } |
| 2286 | EXPORT_SYMBOL(iwl_mac_conf_tx); |
| 2287 | |
| 2288 | static void iwl_ht_conf(struct iwl_priv *priv, |
| 2289 | struct ieee80211_bss_conf *bss_conf) |
| 2290 | { |
| 2291 | struct iwl_ht_config *ht_conf = &priv->current_ht_config; |
| 2292 | struct ieee80211_sta *sta; |
| 2293 | |
| 2294 | IWL_DEBUG_MAC80211(priv, "enter: \n"); |
| 2295 | |
| 2296 | if (!ht_conf->is_ht) |
| 2297 | return; |
| 2298 | |
| 2299 | ht_conf->ht_protection = |
| 2300 | bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION; |
| 2301 | ht_conf->non_GF_STA_present = |
| 2302 | !!(bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); |
| 2303 | |
| 2304 | ht_conf->single_chain_sufficient = false; |
| 2305 | |
| 2306 | switch (priv->iw_mode) { |
| 2307 | case NL80211_IFTYPE_STATION: |
| 2308 | rcu_read_lock(); |
| 2309 | sta = ieee80211_find_sta(priv->vif, priv->bssid); |
| 2310 | if (sta) { |
| 2311 | struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap; |
| 2312 | int maxstreams; |
| 2313 | |
| 2314 | maxstreams = (ht_cap->mcs.tx_params & |
| 2315 | IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK) |
| 2316 | >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT; |
| 2317 | maxstreams += 1; |
| 2318 | |
| 2319 | ht_conf->sm_ps = |
| 2320 | (u8)((ht_cap->cap & IEEE80211_HT_CAP_SM_PS) |
| 2321 | >> 2); |
| 2322 | IWL_DEBUG_MAC80211(priv, "sm_ps: 0x%x\n", |
| 2323 | ht_conf->sm_ps); |
| 2324 | |
| 2325 | if ((ht_cap->mcs.rx_mask[1] == 0) && |
| 2326 | (ht_cap->mcs.rx_mask[2] == 0)) |
| 2327 | ht_conf->single_chain_sufficient = true; |
| 2328 | if (maxstreams <= 1) |
| 2329 | ht_conf->single_chain_sufficient = true; |
| 2330 | } else { |
| 2331 | /* |
| 2332 | * If at all, this can only happen through a race |
| 2333 | * when the AP disconnects us while we're still |
| 2334 | * setting up the connection, in that case mac80211 |
| 2335 | * will soon tell us about that. |
| 2336 | */ |
| 2337 | ht_conf->single_chain_sufficient = true; |
| 2338 | } |
| 2339 | rcu_read_unlock(); |
| 2340 | break; |
| 2341 | case NL80211_IFTYPE_ADHOC: |
| 2342 | ht_conf->single_chain_sufficient = true; |
| 2343 | break; |
| 2344 | default: |
| 2345 | break; |
| 2346 | } |
| 2347 | |
| 2348 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
| 2349 | } |
| 2350 | |
| 2351 | #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6) |
| 2352 | void iwl_bss_info_changed(struct ieee80211_hw *hw, |
| 2353 | struct ieee80211_vif *vif, |
| 2354 | struct ieee80211_bss_conf *bss_conf, |
| 2355 | u32 changes) |
| 2356 | { |
| 2357 | struct iwl_priv *priv = hw->priv; |
| 2358 | int ret; |
| 2359 | |
| 2360 | IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes); |
| 2361 | |
| 2362 | if (!iwl_is_alive(priv)) |
| 2363 | return; |
| 2364 | |
| 2365 | mutex_lock(&priv->mutex); |
| 2366 | |
| 2367 | if (changes & BSS_CHANGED_BEACON && |
| 2368 | priv->iw_mode == NL80211_IFTYPE_AP) { |
| 2369 | dev_kfree_skb(priv->ibss_beacon); |
| 2370 | priv->ibss_beacon = ieee80211_beacon_get(hw, vif); |
| 2371 | } |
| 2372 | |
| 2373 | if (changes & BSS_CHANGED_BEACON_INT) { |
| 2374 | priv->beacon_int = bss_conf->beacon_int; |
| 2375 | /* TODO: in AP mode, do something to make this take effect */ |
| 2376 | } |
| 2377 | |
| 2378 | if (changes & BSS_CHANGED_BSSID) { |
| 2379 | IWL_DEBUG_MAC80211(priv, "BSSID %pM\n", bss_conf->bssid); |
| 2380 | |
| 2381 | /* |
| 2382 | * If there is currently a HW scan going on in the |
| 2383 | * background then we need to cancel it else the RXON |
| 2384 | * below/in post_associate will fail. |
| 2385 | */ |
| 2386 | if (iwl_scan_cancel_timeout(priv, 100)) { |
| 2387 | IWL_WARN(priv, "Aborted scan still in progress after 100ms\n"); |
| 2388 | IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n"); |
| 2389 | mutex_unlock(&priv->mutex); |
| 2390 | return; |
| 2391 | } |
| 2392 | |
| 2393 | /* mac80211 only sets assoc when in STATION mode */ |
| 2394 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC || |
| 2395 | bss_conf->assoc) { |
| 2396 | memcpy(priv->staging_rxon.bssid_addr, |
| 2397 | bss_conf->bssid, ETH_ALEN); |
| 2398 | |
| 2399 | /* currently needed in a few places */ |
| 2400 | memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN); |
| 2401 | } else { |
| 2402 | priv->staging_rxon.filter_flags &= |
| 2403 | ~RXON_FILTER_ASSOC_MSK; |
| 2404 | } |
| 2405 | |
| 2406 | } |
| 2407 | |
| 2408 | /* |
| 2409 | * This needs to be after setting the BSSID in case |
| 2410 | * mac80211 decides to do both changes at once because |
| 2411 | * it will invoke post_associate. |
| 2412 | */ |
| 2413 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC && |
| 2414 | changes & BSS_CHANGED_BEACON) { |
| 2415 | struct sk_buff *beacon = ieee80211_beacon_get(hw, vif); |
| 2416 | |
| 2417 | if (beacon) |
| 2418 | iwl_mac_beacon_update(hw, beacon); |
| 2419 | } |
| 2420 | |
| 2421 | if (changes & BSS_CHANGED_ERP_PREAMBLE) { |
| 2422 | IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n", |
| 2423 | bss_conf->use_short_preamble); |
| 2424 | if (bss_conf->use_short_preamble) |
| 2425 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
| 2426 | else |
| 2427 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
| 2428 | } |
| 2429 | |
| 2430 | if (changes & BSS_CHANGED_ERP_CTS_PROT) { |
| 2431 | IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot); |
| 2432 | if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ)) |
| 2433 | priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK; |
| 2434 | else |
| 2435 | priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK; |
| 2436 | } |
| 2437 | |
| 2438 | if (changes & BSS_CHANGED_BASIC_RATES) { |
| 2439 | /* XXX use this information |
| 2440 | * |
| 2441 | * To do that, remove code from iwl_set_rate() and put something |
| 2442 | * like this here: |
| 2443 | * |
| 2444 | if (A-band) |
| 2445 | priv->staging_rxon.ofdm_basic_rates = |
| 2446 | bss_conf->basic_rates; |
| 2447 | else |
| 2448 | priv->staging_rxon.ofdm_basic_rates = |
| 2449 | bss_conf->basic_rates >> 4; |
| 2450 | priv->staging_rxon.cck_basic_rates = |
| 2451 | bss_conf->basic_rates & 0xF; |
| 2452 | */ |
| 2453 | } |
| 2454 | |
| 2455 | if (changes & BSS_CHANGED_HT) { |
| 2456 | iwl_ht_conf(priv, bss_conf); |
| 2457 | |
| 2458 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
| 2459 | priv->cfg->ops->hcmd->set_rxon_chain(priv); |
| 2460 | } |
| 2461 | |
| 2462 | if (changes & BSS_CHANGED_ASSOC) { |
| 2463 | IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc); |
| 2464 | if (bss_conf->assoc) { |
| 2465 | priv->assoc_id = bss_conf->aid; |
| 2466 | priv->beacon_int = bss_conf->beacon_int; |
| 2467 | priv->timestamp = bss_conf->timestamp; |
| 2468 | priv->assoc_capability = bss_conf->assoc_capability; |
| 2469 | |
| 2470 | iwl_led_associate(priv); |
| 2471 | |
| 2472 | /* |
| 2473 | * We have just associated, don't start scan too early |
| 2474 | * leave time for EAPOL exchange to complete. |
| 2475 | * |
| 2476 | * XXX: do this in mac80211 |
| 2477 | */ |
| 2478 | priv->next_scan_jiffies = jiffies + |
| 2479 | IWL_DELAY_NEXT_SCAN_AFTER_ASSOC; |
| 2480 | if (!iwl_is_rfkill(priv)) |
| 2481 | priv->cfg->ops->lib->post_associate(priv); |
| 2482 | } else { |
| 2483 | priv->assoc_id = 0; |
| 2484 | iwl_led_disassociate(priv); |
| 2485 | } |
| 2486 | } |
| 2487 | |
| 2488 | if (changes && iwl_is_associated(priv) && priv->assoc_id) { |
| 2489 | IWL_DEBUG_MAC80211(priv, "Changes (%#x) while associated\n", |
| 2490 | changes); |
| 2491 | ret = iwl_send_rxon_assoc(priv); |
| 2492 | if (!ret) { |
| 2493 | /* Sync active_rxon with latest change. */ |
| 2494 | memcpy((void *)&priv->active_rxon, |
| 2495 | &priv->staging_rxon, |
| 2496 | sizeof(struct iwl_rxon_cmd)); |
| 2497 | } |
| 2498 | } |
| 2499 | |
| 2500 | mutex_unlock(&priv->mutex); |
| 2501 | |
| 2502 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
| 2503 | } |
| 2504 | EXPORT_SYMBOL(iwl_bss_info_changed); |
| 2505 | |
| 2506 | int iwl_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb) |
| 2507 | { |
| 2508 | struct iwl_priv *priv = hw->priv; |
| 2509 | unsigned long flags; |
| 2510 | __le64 timestamp; |
| 2511 | |
| 2512 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
| 2513 | |
| 2514 | if (!iwl_is_ready_rf(priv)) { |
| 2515 | IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n"); |
| 2516 | return -EIO; |
| 2517 | } |
| 2518 | |
| 2519 | if (priv->iw_mode != NL80211_IFTYPE_ADHOC) { |
| 2520 | IWL_DEBUG_MAC80211(priv, "leave - not IBSS\n"); |
| 2521 | return -EIO; |
| 2522 | } |
| 2523 | |
| 2524 | spin_lock_irqsave(&priv->lock, flags); |
| 2525 | |
| 2526 | if (priv->ibss_beacon) |
| 2527 | dev_kfree_skb(priv->ibss_beacon); |
| 2528 | |
| 2529 | priv->ibss_beacon = skb; |
| 2530 | |
| 2531 | priv->assoc_id = 0; |
| 2532 | timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp; |
| 2533 | priv->timestamp = le64_to_cpu(timestamp); |
| 2534 | |
| 2535 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
| 2536 | spin_unlock_irqrestore(&priv->lock, flags); |
| 2537 | |
| 2538 | iwl_reset_qos(priv); |
| 2539 | |
| 2540 | priv->cfg->ops->lib->post_associate(priv); |
| 2541 | |
| 2542 | |
| 2543 | return 0; |
| 2544 | } |
| 2545 | EXPORT_SYMBOL(iwl_mac_beacon_update); |
| 2546 | |
| 2547 | int iwl_set_mode(struct iwl_priv *priv, int mode) |
| 2548 | { |
| 2549 | if (mode == NL80211_IFTYPE_ADHOC) { |
| 2550 | const struct iwl_channel_info *ch_info; |
| 2551 | |
| 2552 | ch_info = iwl_get_channel_info(priv, |
| 2553 | priv->band, |
| 2554 | le16_to_cpu(priv->staging_rxon.channel)); |
| 2555 | |
| 2556 | if (!ch_info || !is_channel_ibss(ch_info)) { |
| 2557 | IWL_ERR(priv, "channel %d not IBSS channel\n", |
| 2558 | le16_to_cpu(priv->staging_rxon.channel)); |
| 2559 | return -EINVAL; |
| 2560 | } |
| 2561 | } |
| 2562 | |
| 2563 | iwl_connection_init_rx_config(priv, mode); |
| 2564 | |
| 2565 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
| 2566 | priv->cfg->ops->hcmd->set_rxon_chain(priv); |
| 2567 | |
| 2568 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
| 2569 | |
| 2570 | iwl_clear_stations_table(priv); |
| 2571 | |
| 2572 | /* dont commit rxon if rf-kill is on*/ |
| 2573 | if (!iwl_is_ready_rf(priv)) |
| 2574 | return -EAGAIN; |
| 2575 | |
| 2576 | iwlcore_commit_rxon(priv); |
| 2577 | |
| 2578 | return 0; |
| 2579 | } |
| 2580 | EXPORT_SYMBOL(iwl_set_mode); |
| 2581 | |
| 2582 | int iwl_mac_add_interface(struct ieee80211_hw *hw, |
| 2583 | struct ieee80211_if_init_conf *conf) |
| 2584 | { |
| 2585 | struct iwl_priv *priv = hw->priv; |
| 2586 | unsigned long flags; |
| 2587 | |
| 2588 | IWL_DEBUG_MAC80211(priv, "enter: type %d\n", conf->type); |
| 2589 | |
| 2590 | if (priv->vif) { |
| 2591 | IWL_DEBUG_MAC80211(priv, "leave - vif != NULL\n"); |
| 2592 | return -EOPNOTSUPP; |
| 2593 | } |
| 2594 | |
| 2595 | spin_lock_irqsave(&priv->lock, flags); |
| 2596 | priv->vif = conf->vif; |
| 2597 | priv->iw_mode = conf->type; |
| 2598 | |
| 2599 | spin_unlock_irqrestore(&priv->lock, flags); |
| 2600 | |
| 2601 | mutex_lock(&priv->mutex); |
| 2602 | |
| 2603 | if (conf->mac_addr) { |
| 2604 | IWL_DEBUG_MAC80211(priv, "Set %pM\n", conf->mac_addr); |
| 2605 | memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN); |
| 2606 | } |
| 2607 | |
| 2608 | if (iwl_set_mode(priv, conf->type) == -EAGAIN) |
| 2609 | /* we are not ready, will run again when ready */ |
| 2610 | set_bit(STATUS_MODE_PENDING, &priv->status); |
| 2611 | |
| 2612 | mutex_unlock(&priv->mutex); |
| 2613 | |
| 2614 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
| 2615 | return 0; |
| 2616 | } |
| 2617 | EXPORT_SYMBOL(iwl_mac_add_interface); |
| 2618 | |
| 2619 | void iwl_mac_remove_interface(struct ieee80211_hw *hw, |
| 2620 | struct ieee80211_if_init_conf *conf) |
| 2621 | { |
| 2622 | struct iwl_priv *priv = hw->priv; |
| 2623 | |
| 2624 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
| 2625 | |
| 2626 | mutex_lock(&priv->mutex); |
| 2627 | |
| 2628 | if (iwl_is_ready_rf(priv)) { |
| 2629 | iwl_scan_cancel_timeout(priv, 100); |
| 2630 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
| 2631 | iwlcore_commit_rxon(priv); |
| 2632 | } |
| 2633 | if (priv->vif == conf->vif) { |
| 2634 | priv->vif = NULL; |
| 2635 | memset(priv->bssid, 0, ETH_ALEN); |
| 2636 | } |
| 2637 | mutex_unlock(&priv->mutex); |
| 2638 | |
| 2639 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
| 2640 | |
| 2641 | } |
| 2642 | EXPORT_SYMBOL(iwl_mac_remove_interface); |
| 2643 | |
| 2644 | /** |
| 2645 | * iwl_mac_config - mac80211 config callback |
| 2646 | * |
| 2647 | * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to |
| 2648 | * be set inappropriately and the driver currently sets the hardware up to |
| 2649 | * use it whenever needed. |
| 2650 | */ |
| 2651 | int iwl_mac_config(struct ieee80211_hw *hw, u32 changed) |
| 2652 | { |
| 2653 | struct iwl_priv *priv = hw->priv; |
| 2654 | const struct iwl_channel_info *ch_info; |
| 2655 | struct ieee80211_conf *conf = &hw->conf; |
| 2656 | struct iwl_ht_config *ht_conf = &priv->current_ht_config; |
| 2657 | unsigned long flags = 0; |
| 2658 | int ret = 0; |
| 2659 | u16 ch; |
| 2660 | int scan_active = 0; |
| 2661 | |
| 2662 | mutex_lock(&priv->mutex); |
| 2663 | |
| 2664 | IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n", |
| 2665 | conf->channel->hw_value, changed); |
| 2666 | |
| 2667 | if (unlikely(!priv->cfg->mod_params->disable_hw_scan && |
| 2668 | test_bit(STATUS_SCANNING, &priv->status))) { |
| 2669 | scan_active = 1; |
| 2670 | IWL_DEBUG_MAC80211(priv, "leave - scanning\n"); |
| 2671 | } |
| 2672 | |
| 2673 | |
| 2674 | /* during scanning mac80211 will delay channel setting until |
| 2675 | * scan finish with changed = 0 |
| 2676 | */ |
| 2677 | if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) { |
| 2678 | if (scan_active) |
| 2679 | goto set_ch_out; |
| 2680 | |
| 2681 | ch = ieee80211_frequency_to_channel(conf->channel->center_freq); |
| 2682 | ch_info = iwl_get_channel_info(priv, conf->channel->band, ch); |
| 2683 | if (!is_channel_valid(ch_info)) { |
| 2684 | IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n"); |
| 2685 | ret = -EINVAL; |
| 2686 | goto set_ch_out; |
| 2687 | } |
| 2688 | |
| 2689 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC && |
| 2690 | !is_channel_ibss(ch_info)) { |
| 2691 | IWL_ERR(priv, "channel %d in band %d not " |
| 2692 | "IBSS channel\n", |
| 2693 | conf->channel->hw_value, conf->channel->band); |
| 2694 | ret = -EINVAL; |
| 2695 | goto set_ch_out; |
| 2696 | } |
| 2697 | |
| 2698 | spin_lock_irqsave(&priv->lock, flags); |
| 2699 | |
| 2700 | /* Configure HT40 channels */ |
| 2701 | ht_conf->is_ht = conf_is_ht(conf); |
| 2702 | if (ht_conf->is_ht) { |
| 2703 | if (conf_is_ht40_minus(conf)) { |
| 2704 | ht_conf->extension_chan_offset = |
| 2705 | IEEE80211_HT_PARAM_CHA_SEC_BELOW; |
| 2706 | ht_conf->is_40mhz = true; |
| 2707 | } else if (conf_is_ht40_plus(conf)) { |
| 2708 | ht_conf->extension_chan_offset = |
| 2709 | IEEE80211_HT_PARAM_CHA_SEC_ABOVE; |
| 2710 | ht_conf->is_40mhz = true; |
| 2711 | } else { |
| 2712 | ht_conf->extension_chan_offset = |
| 2713 | IEEE80211_HT_PARAM_CHA_SEC_NONE; |
| 2714 | ht_conf->is_40mhz = false; |
| 2715 | } |
| 2716 | } else |
| 2717 | ht_conf->is_40mhz = false; |
| 2718 | /* Default to no protection. Protection mode will later be set |
| 2719 | * from BSS config in iwl_ht_conf */ |
| 2720 | ht_conf->ht_protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE; |
| 2721 | |
| 2722 | /* if we are switching from ht to 2.4 clear flags |
| 2723 | * from any ht related info since 2.4 does not |
| 2724 | * support ht */ |
| 2725 | if ((le16_to_cpu(priv->staging_rxon.channel) != ch)) |
| 2726 | priv->staging_rxon.flags = 0; |
| 2727 | |
| 2728 | iwl_set_rxon_channel(priv, conf->channel); |
| 2729 | |
| 2730 | iwl_set_flags_for_band(priv, conf->channel->band); |
| 2731 | spin_unlock_irqrestore(&priv->lock, flags); |
| 2732 | if (iwl_is_associated(priv) && |
| 2733 | (le16_to_cpu(priv->active_rxon.channel) != ch) && |
| 2734 | priv->cfg->ops->lib->set_channel_switch) { |
| 2735 | iwl_set_rate(priv); |
| 2736 | /* |
| 2737 | * at this point, staging_rxon has the |
| 2738 | * configuration for channel switch |
| 2739 | */ |
| 2740 | ret = priv->cfg->ops->lib->set_channel_switch(priv, |
| 2741 | ch); |
| 2742 | if (!ret) { |
| 2743 | iwl_print_rx_config_cmd(priv); |
| 2744 | goto out; |
| 2745 | } |
| 2746 | priv->switch_rxon.switch_in_progress = false; |
| 2747 | } |
| 2748 | set_ch_out: |
| 2749 | /* The list of supported rates and rate mask can be different |
| 2750 | * for each band; since the band may have changed, reset |
| 2751 | * the rate mask to what mac80211 lists */ |
| 2752 | iwl_set_rate(priv); |
| 2753 | } |
| 2754 | |
| 2755 | if (changed & (IEEE80211_CONF_CHANGE_PS | |
| 2756 | IEEE80211_CONF_CHANGE_IDLE)) { |
| 2757 | ret = iwl_power_update_mode(priv, false); |
| 2758 | if (ret) |
| 2759 | IWL_DEBUG_MAC80211(priv, "Error setting sleep level\n"); |
| 2760 | } |
| 2761 | |
| 2762 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
| 2763 | IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n", |
| 2764 | priv->tx_power_user_lmt, conf->power_level); |
| 2765 | |
| 2766 | iwl_set_tx_power(priv, conf->power_level, false); |
| 2767 | } |
| 2768 | |
| 2769 | /* call to ensure that 4965 rx_chain is set properly in monitor mode */ |
| 2770 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
| 2771 | priv->cfg->ops->hcmd->set_rxon_chain(priv); |
| 2772 | |
| 2773 | if (!iwl_is_ready(priv)) { |
| 2774 | IWL_DEBUG_MAC80211(priv, "leave - not ready\n"); |
| 2775 | goto out; |
| 2776 | } |
| 2777 | |
| 2778 | if (scan_active) |
| 2779 | goto out; |
| 2780 | |
| 2781 | if (memcmp(&priv->active_rxon, |
| 2782 | &priv->staging_rxon, sizeof(priv->staging_rxon))) |
| 2783 | iwlcore_commit_rxon(priv); |
| 2784 | else |
| 2785 | IWL_DEBUG_INFO(priv, "Not re-sending same RXON configuration.\n"); |
| 2786 | |
| 2787 | |
| 2788 | out: |
| 2789 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
| 2790 | mutex_unlock(&priv->mutex); |
| 2791 | return ret; |
| 2792 | } |
| 2793 | EXPORT_SYMBOL(iwl_mac_config); |
| 2794 | |
| 2795 | int iwl_mac_get_tx_stats(struct ieee80211_hw *hw, |
| 2796 | struct ieee80211_tx_queue_stats *stats) |
| 2797 | { |
| 2798 | struct iwl_priv *priv = hw->priv; |
| 2799 | int i, avail; |
| 2800 | struct iwl_tx_queue *txq; |
| 2801 | struct iwl_queue *q; |
| 2802 | unsigned long flags; |
| 2803 | |
| 2804 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
| 2805 | |
| 2806 | if (!iwl_is_ready_rf(priv)) { |
| 2807 | IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n"); |
| 2808 | return -EIO; |
| 2809 | } |
| 2810 | |
| 2811 | spin_lock_irqsave(&priv->lock, flags); |
| 2812 | |
| 2813 | for (i = 0; i < AC_NUM; i++) { |
| 2814 | txq = &priv->txq[i]; |
| 2815 | q = &txq->q; |
| 2816 | avail = iwl_queue_space(q); |
| 2817 | |
| 2818 | stats[i].len = q->n_window - avail; |
| 2819 | stats[i].limit = q->n_window - q->high_mark; |
| 2820 | stats[i].count = q->n_window; |
| 2821 | |
| 2822 | } |
| 2823 | spin_unlock_irqrestore(&priv->lock, flags); |
| 2824 | |
| 2825 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
| 2826 | |
| 2827 | return 0; |
| 2828 | } |
| 2829 | EXPORT_SYMBOL(iwl_mac_get_tx_stats); |
| 2830 | |
| 2831 | void iwl_mac_reset_tsf(struct ieee80211_hw *hw) |
| 2832 | { |
| 2833 | struct iwl_priv *priv = hw->priv; |
| 2834 | unsigned long flags; |
| 2835 | |
| 2836 | mutex_lock(&priv->mutex); |
| 2837 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
| 2838 | |
| 2839 | spin_lock_irqsave(&priv->lock, flags); |
| 2840 | memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_config)); |
| 2841 | spin_unlock_irqrestore(&priv->lock, flags); |
| 2842 | |
| 2843 | iwl_reset_qos(priv); |
| 2844 | |
| 2845 | spin_lock_irqsave(&priv->lock, flags); |
| 2846 | priv->assoc_id = 0; |
| 2847 | priv->assoc_capability = 0; |
| 2848 | priv->assoc_station_added = 0; |
| 2849 | |
| 2850 | /* new association get rid of ibss beacon skb */ |
| 2851 | if (priv->ibss_beacon) |
| 2852 | dev_kfree_skb(priv->ibss_beacon); |
| 2853 | |
| 2854 | priv->ibss_beacon = NULL; |
| 2855 | |
| 2856 | priv->beacon_int = priv->vif->bss_conf.beacon_int; |
| 2857 | priv->timestamp = 0; |
| 2858 | if ((priv->iw_mode == NL80211_IFTYPE_STATION)) |
| 2859 | priv->beacon_int = 0; |
| 2860 | |
| 2861 | spin_unlock_irqrestore(&priv->lock, flags); |
| 2862 | |
| 2863 | if (!iwl_is_ready_rf(priv)) { |
| 2864 | IWL_DEBUG_MAC80211(priv, "leave - not ready\n"); |
| 2865 | mutex_unlock(&priv->mutex); |
| 2866 | return; |
| 2867 | } |
| 2868 | |
| 2869 | /* we are restarting association process |
| 2870 | * clear RXON_FILTER_ASSOC_MSK bit |
| 2871 | */ |
| 2872 | if (priv->iw_mode != NL80211_IFTYPE_AP) { |
| 2873 | iwl_scan_cancel_timeout(priv, 100); |
| 2874 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
| 2875 | iwlcore_commit_rxon(priv); |
| 2876 | } |
| 2877 | |
| 2878 | if (priv->iw_mode != NL80211_IFTYPE_ADHOC) { |
| 2879 | IWL_DEBUG_MAC80211(priv, "leave - not in IBSS\n"); |
| 2880 | mutex_unlock(&priv->mutex); |
| 2881 | return; |
| 2882 | } |
| 2883 | |
| 2884 | iwl_set_rate(priv); |
| 2885 | |
| 2886 | mutex_unlock(&priv->mutex); |
| 2887 | |
| 2888 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
| 2889 | } |
| 2890 | EXPORT_SYMBOL(iwl_mac_reset_tsf); |
| 2891 | |
| 2892 | int iwl_alloc_txq_mem(struct iwl_priv *priv) |
| 2893 | { |
| 2894 | if (!priv->txq) |
| 2895 | priv->txq = kzalloc( |
| 2896 | sizeof(struct iwl_tx_queue) * priv->cfg->num_of_queues, |
| 2897 | GFP_KERNEL); |
| 2898 | if (!priv->txq) { |
| 2899 | IWL_ERR(priv, "Not enough memory for txq \n"); |
| 2900 | return -ENOMEM; |
| 2901 | } |
| 2902 | return 0; |
| 2903 | } |
| 2904 | EXPORT_SYMBOL(iwl_alloc_txq_mem); |
| 2905 | |
| 2906 | void iwl_free_txq_mem(struct iwl_priv *priv) |
| 2907 | { |
| 2908 | kfree(priv->txq); |
| 2909 | priv->txq = NULL; |
| 2910 | } |
| 2911 | EXPORT_SYMBOL(iwl_free_txq_mem); |
| 2912 | |
| 2913 | int iwl_send_wimax_coex(struct iwl_priv *priv) |
| 2914 | { |
| 2915 | struct iwl_wimax_coex_cmd uninitialized_var(coex_cmd); |
| 2916 | |
| 2917 | if (priv->cfg->support_wimax_coexist) { |
| 2918 | /* UnMask wake up src at associated sleep */ |
| 2919 | coex_cmd.flags |= COEX_FLAGS_ASSOC_WA_UNMASK_MSK; |
| 2920 | |
| 2921 | /* UnMask wake up src at unassociated sleep */ |
| 2922 | coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK; |
| 2923 | memcpy(coex_cmd.sta_prio, cu_priorities, |
| 2924 | sizeof(struct iwl_wimax_coex_event_entry) * |
| 2925 | COEX_NUM_OF_EVENTS); |
| 2926 | |
| 2927 | /* enabling the coexistence feature */ |
| 2928 | coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK; |
| 2929 | |
| 2930 | /* enabling the priorities tables */ |
| 2931 | coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK; |
| 2932 | } else { |
| 2933 | /* coexistence is disabled */ |
| 2934 | memset(&coex_cmd, 0, sizeof(coex_cmd)); |
| 2935 | } |
| 2936 | return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD, |
| 2937 | sizeof(coex_cmd), &coex_cmd); |
| 2938 | } |
| 2939 | EXPORT_SYMBOL(iwl_send_wimax_coex); |
| 2940 | |
| 2941 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
| 2942 | |
| 2943 | #define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES) |
| 2944 | |
| 2945 | void iwl_reset_traffic_log(struct iwl_priv *priv) |
| 2946 | { |
| 2947 | priv->tx_traffic_idx = 0; |
| 2948 | priv->rx_traffic_idx = 0; |
| 2949 | if (priv->tx_traffic) |
| 2950 | memset(priv->tx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE); |
| 2951 | if (priv->rx_traffic) |
| 2952 | memset(priv->rx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE); |
| 2953 | } |
| 2954 | |
| 2955 | int iwl_alloc_traffic_mem(struct iwl_priv *priv) |
| 2956 | { |
| 2957 | u32 traffic_size = IWL_TRAFFIC_DUMP_SIZE; |
| 2958 | |
| 2959 | if (iwl_debug_level & IWL_DL_TX) { |
| 2960 | if (!priv->tx_traffic) { |
| 2961 | priv->tx_traffic = |
| 2962 | kzalloc(traffic_size, GFP_KERNEL); |
| 2963 | if (!priv->tx_traffic) |
| 2964 | return -ENOMEM; |
| 2965 | } |
| 2966 | } |
| 2967 | if (iwl_debug_level & IWL_DL_RX) { |
| 2968 | if (!priv->rx_traffic) { |
| 2969 | priv->rx_traffic = |
| 2970 | kzalloc(traffic_size, GFP_KERNEL); |
| 2971 | if (!priv->rx_traffic) |
| 2972 | return -ENOMEM; |
| 2973 | } |
| 2974 | } |
| 2975 | iwl_reset_traffic_log(priv); |
| 2976 | return 0; |
| 2977 | } |
| 2978 | EXPORT_SYMBOL(iwl_alloc_traffic_mem); |
| 2979 | |
| 2980 | void iwl_free_traffic_mem(struct iwl_priv *priv) |
| 2981 | { |
| 2982 | kfree(priv->tx_traffic); |
| 2983 | priv->tx_traffic = NULL; |
| 2984 | |
| 2985 | kfree(priv->rx_traffic); |
| 2986 | priv->rx_traffic = NULL; |
| 2987 | } |
| 2988 | EXPORT_SYMBOL(iwl_free_traffic_mem); |
| 2989 | |
| 2990 | void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv, |
| 2991 | u16 length, struct ieee80211_hdr *header) |
| 2992 | { |
| 2993 | __le16 fc; |
| 2994 | u16 len; |
| 2995 | |
| 2996 | if (likely(!(iwl_debug_level & IWL_DL_TX))) |
| 2997 | return; |
| 2998 | |
| 2999 | if (!priv->tx_traffic) |
| 3000 | return; |
| 3001 | |
| 3002 | fc = header->frame_control; |
| 3003 | if (ieee80211_is_data(fc)) { |
| 3004 | len = (length > IWL_TRAFFIC_ENTRY_SIZE) |
| 3005 | ? IWL_TRAFFIC_ENTRY_SIZE : length; |
| 3006 | memcpy((priv->tx_traffic + |
| 3007 | (priv->tx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)), |
| 3008 | header, len); |
| 3009 | priv->tx_traffic_idx = |
| 3010 | (priv->tx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES; |
| 3011 | } |
| 3012 | } |
| 3013 | EXPORT_SYMBOL(iwl_dbg_log_tx_data_frame); |
| 3014 | |
| 3015 | void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv, |
| 3016 | u16 length, struct ieee80211_hdr *header) |
| 3017 | { |
| 3018 | __le16 fc; |
| 3019 | u16 len; |
| 3020 | |
| 3021 | if (likely(!(iwl_debug_level & IWL_DL_RX))) |
| 3022 | return; |
| 3023 | |
| 3024 | if (!priv->rx_traffic) |
| 3025 | return; |
| 3026 | |
| 3027 | fc = header->frame_control; |
| 3028 | if (ieee80211_is_data(fc)) { |
| 3029 | len = (length > IWL_TRAFFIC_ENTRY_SIZE) |
| 3030 | ? IWL_TRAFFIC_ENTRY_SIZE : length; |
| 3031 | memcpy((priv->rx_traffic + |
| 3032 | (priv->rx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)), |
| 3033 | header, len); |
| 3034 | priv->rx_traffic_idx = |
| 3035 | (priv->rx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES; |
| 3036 | } |
| 3037 | } |
| 3038 | EXPORT_SYMBOL(iwl_dbg_log_rx_data_frame); |
| 3039 | |
| 3040 | const char *get_mgmt_string(int cmd) |
| 3041 | { |
| 3042 | switch (cmd) { |
| 3043 | IWL_CMD(MANAGEMENT_ASSOC_REQ); |
| 3044 | IWL_CMD(MANAGEMENT_ASSOC_RESP); |
| 3045 | IWL_CMD(MANAGEMENT_REASSOC_REQ); |
| 3046 | IWL_CMD(MANAGEMENT_REASSOC_RESP); |
| 3047 | IWL_CMD(MANAGEMENT_PROBE_REQ); |
| 3048 | IWL_CMD(MANAGEMENT_PROBE_RESP); |
| 3049 | IWL_CMD(MANAGEMENT_BEACON); |
| 3050 | IWL_CMD(MANAGEMENT_ATIM); |
| 3051 | IWL_CMD(MANAGEMENT_DISASSOC); |
| 3052 | IWL_CMD(MANAGEMENT_AUTH); |
| 3053 | IWL_CMD(MANAGEMENT_DEAUTH); |
| 3054 | IWL_CMD(MANAGEMENT_ACTION); |
| 3055 | default: |
| 3056 | return "UNKNOWN"; |
| 3057 | |
| 3058 | } |
| 3059 | } |
| 3060 | |
| 3061 | const char *get_ctrl_string(int cmd) |
| 3062 | { |
| 3063 | switch (cmd) { |
| 3064 | IWL_CMD(CONTROL_BACK_REQ); |
| 3065 | IWL_CMD(CONTROL_BACK); |
| 3066 | IWL_CMD(CONTROL_PSPOLL); |
| 3067 | IWL_CMD(CONTROL_RTS); |
| 3068 | IWL_CMD(CONTROL_CTS); |
| 3069 | IWL_CMD(CONTROL_ACK); |
| 3070 | IWL_CMD(CONTROL_CFEND); |
| 3071 | IWL_CMD(CONTROL_CFENDACK); |
| 3072 | default: |
| 3073 | return "UNKNOWN"; |
| 3074 | |
| 3075 | } |
| 3076 | } |
| 3077 | |
| 3078 | void iwl_clear_tx_stats(struct iwl_priv *priv) |
| 3079 | { |
| 3080 | memset(&priv->tx_stats, 0, sizeof(struct traffic_stats)); |
| 3081 | |
| 3082 | } |
| 3083 | |
| 3084 | void iwl_clear_rx_stats(struct iwl_priv *priv) |
| 3085 | { |
| 3086 | memset(&priv->rx_stats, 0, sizeof(struct traffic_stats)); |
| 3087 | } |
| 3088 | |
| 3089 | /* |
| 3090 | * if CONFIG_IWLWIFI_DEBUGFS defined, iwl_update_stats function will |
| 3091 | * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass. |
| 3092 | * Use debugFs to display the rx/rx_statistics |
| 3093 | * if CONFIG_IWLWIFI_DEBUGFS not being defined, then no MGMT and CTRL |
| 3094 | * information will be recorded, but DATA pkt still will be recorded |
| 3095 | * for the reason of iwl_led.c need to control the led blinking based on |
| 3096 | * number of tx and rx data. |
| 3097 | * |
| 3098 | */ |
| 3099 | void iwl_update_stats(struct iwl_priv *priv, bool is_tx, __le16 fc, u16 len) |
| 3100 | { |
| 3101 | struct traffic_stats *stats; |
| 3102 | |
| 3103 | if (is_tx) |
| 3104 | stats = &priv->tx_stats; |
| 3105 | else |
| 3106 | stats = &priv->rx_stats; |
| 3107 | |
| 3108 | if (ieee80211_is_mgmt(fc)) { |
| 3109 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { |
| 3110 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ): |
| 3111 | stats->mgmt[MANAGEMENT_ASSOC_REQ]++; |
| 3112 | break; |
| 3113 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP): |
| 3114 | stats->mgmt[MANAGEMENT_ASSOC_RESP]++; |
| 3115 | break; |
| 3116 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ): |
| 3117 | stats->mgmt[MANAGEMENT_REASSOC_REQ]++; |
| 3118 | break; |
| 3119 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP): |
| 3120 | stats->mgmt[MANAGEMENT_REASSOC_RESP]++; |
| 3121 | break; |
| 3122 | case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ): |
| 3123 | stats->mgmt[MANAGEMENT_PROBE_REQ]++; |
| 3124 | break; |
| 3125 | case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP): |
| 3126 | stats->mgmt[MANAGEMENT_PROBE_RESP]++; |
| 3127 | break; |
| 3128 | case cpu_to_le16(IEEE80211_STYPE_BEACON): |
| 3129 | stats->mgmt[MANAGEMENT_BEACON]++; |
| 3130 | break; |
| 3131 | case cpu_to_le16(IEEE80211_STYPE_ATIM): |
| 3132 | stats->mgmt[MANAGEMENT_ATIM]++; |
| 3133 | break; |
| 3134 | case cpu_to_le16(IEEE80211_STYPE_DISASSOC): |
| 3135 | stats->mgmt[MANAGEMENT_DISASSOC]++; |
| 3136 | break; |
| 3137 | case cpu_to_le16(IEEE80211_STYPE_AUTH): |
| 3138 | stats->mgmt[MANAGEMENT_AUTH]++; |
| 3139 | break; |
| 3140 | case cpu_to_le16(IEEE80211_STYPE_DEAUTH): |
| 3141 | stats->mgmt[MANAGEMENT_DEAUTH]++; |
| 3142 | break; |
| 3143 | case cpu_to_le16(IEEE80211_STYPE_ACTION): |
| 3144 | stats->mgmt[MANAGEMENT_ACTION]++; |
| 3145 | break; |
| 3146 | } |
| 3147 | } else if (ieee80211_is_ctl(fc)) { |
| 3148 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { |
| 3149 | case cpu_to_le16(IEEE80211_STYPE_BACK_REQ): |
| 3150 | stats->ctrl[CONTROL_BACK_REQ]++; |
| 3151 | break; |
| 3152 | case cpu_to_le16(IEEE80211_STYPE_BACK): |
| 3153 | stats->ctrl[CONTROL_BACK]++; |
| 3154 | break; |
| 3155 | case cpu_to_le16(IEEE80211_STYPE_PSPOLL): |
| 3156 | stats->ctrl[CONTROL_PSPOLL]++; |
| 3157 | break; |
| 3158 | case cpu_to_le16(IEEE80211_STYPE_RTS): |
| 3159 | stats->ctrl[CONTROL_RTS]++; |
| 3160 | break; |
| 3161 | case cpu_to_le16(IEEE80211_STYPE_CTS): |
| 3162 | stats->ctrl[CONTROL_CTS]++; |
| 3163 | break; |
| 3164 | case cpu_to_le16(IEEE80211_STYPE_ACK): |
| 3165 | stats->ctrl[CONTROL_ACK]++; |
| 3166 | break; |
| 3167 | case cpu_to_le16(IEEE80211_STYPE_CFEND): |
| 3168 | stats->ctrl[CONTROL_CFEND]++; |
| 3169 | break; |
| 3170 | case cpu_to_le16(IEEE80211_STYPE_CFENDACK): |
| 3171 | stats->ctrl[CONTROL_CFENDACK]++; |
| 3172 | break; |
| 3173 | } |
| 3174 | } else { |
| 3175 | /* data */ |
| 3176 | stats->data_cnt++; |
| 3177 | stats->data_bytes += len; |
| 3178 | } |
| 3179 | } |
| 3180 | EXPORT_SYMBOL(iwl_update_stats); |
| 3181 | #endif |
| 3182 | |
| 3183 | #ifdef CONFIG_PM |
| 3184 | |
| 3185 | int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
| 3186 | { |
| 3187 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
| 3188 | |
| 3189 | /* |
| 3190 | * This function is called when system goes into suspend state |
| 3191 | * mac80211 will call iwl_mac_stop() from the mac80211 suspend function |
| 3192 | * first but since iwl_mac_stop() has no knowledge of who the caller is, |
| 3193 | * it will not call apm_ops.stop() to stop the DMA operation. |
| 3194 | * Calling apm_ops.stop here to make sure we stop the DMA. |
| 3195 | */ |
| 3196 | priv->cfg->ops->lib->apm_ops.stop(priv); |
| 3197 | |
| 3198 | pci_save_state(pdev); |
| 3199 | pci_disable_device(pdev); |
| 3200 | pci_set_power_state(pdev, PCI_D3hot); |
| 3201 | |
| 3202 | return 0; |
| 3203 | } |
| 3204 | EXPORT_SYMBOL(iwl_pci_suspend); |
| 3205 | |
| 3206 | int iwl_pci_resume(struct pci_dev *pdev) |
| 3207 | { |
| 3208 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
| 3209 | int ret; |
| 3210 | |
| 3211 | pci_set_power_state(pdev, PCI_D0); |
| 3212 | ret = pci_enable_device(pdev); |
| 3213 | if (ret) |
| 3214 | return ret; |
| 3215 | pci_restore_state(pdev); |
| 3216 | iwl_enable_interrupts(priv); |
| 3217 | |
| 3218 | return 0; |
| 3219 | } |
| 3220 | EXPORT_SYMBOL(iwl_pci_resume); |
| 3221 | |
| 3222 | #endif /* CONFIG_PM */ |