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sh-pfc: Rename struct sh_pfc nr_pins field to nr_gpio_pins
[deliverable/linux.git] / drivers / pinctrl / sh-pfc / core.c
... / ...
CommitLineData
1/*
2 * SuperH Pin Function Controller support.
3 *
4 * Copyright (C) 2008 Magnus Damm
5 * Copyright (C) 2009 - 2012 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11
12#define DRV_NAME "sh-pfc"
13
14#include <linux/bitops.h>
15#include <linux/err.h>
16#include <linux/errno.h>
17#include <linux/io.h>
18#include <linux/ioport.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/pinctrl/machine.h>
24#include <linux/platform_device.h>
25#include <linux/slab.h>
26
27#include "core.h"
28
29static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev)
30{
31 struct resource *res;
32 int k;
33
34 if (pdev->num_resources == 0)
35 return -EINVAL;
36
37 pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources *
38 sizeof(*pfc->window), GFP_NOWAIT);
39 if (!pfc->window)
40 return -ENOMEM;
41
42 pfc->num_windows = pdev->num_resources;
43
44 for (k = 0, res = pdev->resource; k < pdev->num_resources; k++, res++) {
45 WARN_ON(resource_type(res) != IORESOURCE_MEM);
46 pfc->window[k].phys = res->start;
47 pfc->window[k].size = resource_size(res);
48 pfc->window[k].virt = devm_ioremap_nocache(pfc->dev, res->start,
49 resource_size(res));
50 if (!pfc->window[k].virt)
51 return -ENOMEM;
52 }
53
54 return 0;
55}
56
57static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
58 unsigned long address)
59{
60 struct sh_pfc_window *window;
61 unsigned int i;
62
63 /* scan through physical windows and convert address */
64 for (i = 0; i < pfc->num_windows; i++) {
65 window = pfc->window + i;
66
67 if (address < window->phys)
68 continue;
69
70 if (address >= (window->phys + window->size))
71 continue;
72
73 return window->virt + (address - window->phys);
74 }
75
76 BUG();
77 return NULL;
78}
79
80int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
81{
82 unsigned int offset;
83 unsigned int i;
84
85 if (pfc->info->ranges == NULL)
86 return pin;
87
88 for (i = 0, offset = 0; i < pfc->info->nr_ranges; ++i) {
89 const struct pinmux_range *range = &pfc->info->ranges[i];
90
91 if (pin <= range->end)
92 return pin >= range->begin
93 ? offset + pin - range->begin : -1;
94
95 offset += range->end - range->begin + 1;
96 }
97
98 return -EINVAL;
99}
100
101static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
102{
103 if (enum_id < r->begin)
104 return 0;
105
106 if (enum_id > r->end)
107 return 0;
108
109 return 1;
110}
111
112unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
113 unsigned long reg_width)
114{
115 switch (reg_width) {
116 case 8:
117 return ioread8(mapped_reg);
118 case 16:
119 return ioread16(mapped_reg);
120 case 32:
121 return ioread32(mapped_reg);
122 }
123
124 BUG();
125 return 0;
126}
127
128void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
129 unsigned long data)
130{
131 switch (reg_width) {
132 case 8:
133 iowrite8(data, mapped_reg);
134 return;
135 case 16:
136 iowrite16(data, mapped_reg);
137 return;
138 case 32:
139 iowrite32(data, mapped_reg);
140 return;
141 }
142
143 BUG();
144}
145
146static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
147 const struct pinmux_cfg_reg *crp,
148 unsigned long in_pos,
149 void __iomem **mapped_regp,
150 unsigned long *maskp,
151 unsigned long *posp)
152{
153 int k;
154
155 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
156
157 if (crp->field_width) {
158 *maskp = (1 << crp->field_width) - 1;
159 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
160 } else {
161 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
162 *posp = crp->reg_width;
163 for (k = 0; k <= in_pos; k++)
164 *posp -= crp->var_field_width[k];
165 }
166}
167
168static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
169 const struct pinmux_cfg_reg *crp,
170 unsigned long field, unsigned long value)
171{
172 void __iomem *mapped_reg;
173 unsigned long mask, pos, data;
174
175 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
176
177 dev_dbg(pfc->dev, "write_reg addr = %lx, value = %ld, field = %ld, "
178 "r_width = %ld, f_width = %ld\n",
179 crp->reg, value, field, crp->reg_width, crp->field_width);
180
181 mask = ~(mask << pos);
182 value = value << pos;
183
184 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
185 data &= mask;
186 data |= value;
187
188 if (pfc->info->unlock_reg)
189 sh_pfc_write_raw_reg(
190 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
191 ~data);
192
193 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
194}
195
196static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
197 const struct pinmux_cfg_reg **crp, int *fieldp,
198 int *valuep)
199{
200 const struct pinmux_cfg_reg *config_reg;
201 unsigned long r_width, f_width, curr_width, ncomb;
202 int k, m, n, pos, bit_pos;
203
204 k = 0;
205 while (1) {
206 config_reg = pfc->info->cfg_regs + k;
207
208 r_width = config_reg->reg_width;
209 f_width = config_reg->field_width;
210
211 if (!r_width)
212 break;
213
214 pos = 0;
215 m = 0;
216 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
217 if (f_width)
218 curr_width = f_width;
219 else
220 curr_width = config_reg->var_field_width[m];
221
222 ncomb = 1 << curr_width;
223 for (n = 0; n < ncomb; n++) {
224 if (config_reg->enum_ids[pos + n] == enum_id) {
225 *crp = config_reg;
226 *fieldp = m;
227 *valuep = n;
228 return 0;
229 }
230 }
231 pos += ncomb;
232 m++;
233 }
234 k++;
235 }
236
237 return -EINVAL;
238}
239
240static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
241 u16 *enum_idp)
242{
243 const u16 *data = pfc->info->gpio_data;
244 int k;
245
246 if (pos) {
247 *enum_idp = data[pos + 1];
248 return pos + 1;
249 }
250
251 for (k = 0; k < pfc->info->gpio_data_size; k++) {
252 if (data[k] == mark) {
253 *enum_idp = data[k + 1];
254 return k + 1;
255 }
256 }
257
258 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
259 mark);
260 return -EINVAL;
261}
262
263int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
264{
265 const struct pinmux_cfg_reg *cr = NULL;
266 u16 enum_id;
267 const struct pinmux_range *range;
268 int in_range, pos, field, value;
269 int ret;
270
271 switch (pinmux_type) {
272 case PINMUX_TYPE_GPIO:
273 case PINMUX_TYPE_FUNCTION:
274 range = NULL;
275 break;
276
277 case PINMUX_TYPE_OUTPUT:
278 range = &pfc->info->output;
279 break;
280
281 case PINMUX_TYPE_INPUT:
282 range = &pfc->info->input;
283 break;
284
285 default:
286 return -EINVAL;
287 }
288
289 pos = 0;
290 enum_id = 0;
291 field = 0;
292 value = 0;
293
294 /* Iterate over all the configuration fields we need to update. */
295 while (1) {
296 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
297 if (pos < 0)
298 return pos;
299
300 if (!enum_id)
301 break;
302
303 /* Check if the configuration field selects a function. If it
304 * doesn't, skip the field if it's not applicable to the
305 * requested pinmux type.
306 */
307 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
308 if (!in_range) {
309 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
310 /* Functions are allowed to modify all
311 * fields.
312 */
313 in_range = 1;
314 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
315 /* Input/output types can only modify fields
316 * that correspond to their respective ranges.
317 */
318 in_range = sh_pfc_enum_in_range(enum_id, range);
319
320 /*
321 * special case pass through for fixed
322 * input-only or output-only pins without
323 * function enum register association.
324 */
325 if (in_range && enum_id == range->force)
326 continue;
327 }
328 /* GPIOs are only allowed to modify function fields. */
329 }
330
331 if (!in_range)
332 continue;
333
334 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
335 if (ret < 0)
336 return ret;
337
338 sh_pfc_write_config_reg(pfc, cr, field, value);
339 }
340
341 return 0;
342}
343
344#ifdef CONFIG_OF
345static const struct of_device_id sh_pfc_of_table[] = {
346#ifdef CONFIG_PINCTRL_PFC_R8A73A4
347 {
348 .compatible = "renesas,pfc-r8a73a4",
349 .data = &r8a73a4_pinmux_info,
350 },
351#endif
352#ifdef CONFIG_PINCTRL_PFC_R8A7740
353 {
354 .compatible = "renesas,pfc-r8a7740",
355 .data = &r8a7740_pinmux_info,
356 },
357#endif
358#ifdef CONFIG_PINCTRL_PFC_R8A7778
359 {
360 .compatible = "renesas,pfc-r8a7778",
361 .data = &r8a7778_pinmux_info,
362 },
363#endif
364#ifdef CONFIG_PINCTRL_PFC_R8A7779
365 {
366 .compatible = "renesas,pfc-r8a7779",
367 .data = &r8a7779_pinmux_info,
368 },
369#endif
370#ifdef CONFIG_PINCTRL_PFC_R8A7790
371 {
372 .compatible = "renesas,pfc-r8a7790",
373 .data = &r8a7790_pinmux_info,
374 },
375#endif
376#ifdef CONFIG_PINCTRL_PFC_SH7372
377 {
378 .compatible = "renesas,pfc-sh7372",
379 .data = &sh7372_pinmux_info,
380 },
381#endif
382#ifdef CONFIG_PINCTRL_PFC_SH73A0
383 {
384 .compatible = "renesas,pfc-sh73a0",
385 .data = &sh73a0_pinmux_info,
386 },
387#endif
388 { },
389};
390MODULE_DEVICE_TABLE(of, sh_pfc_of_table);
391#endif
392
393static int sh_pfc_probe(struct platform_device *pdev)
394{
395 const struct platform_device_id *platid = platform_get_device_id(pdev);
396#ifdef CONFIG_OF
397 struct device_node *np = pdev->dev.of_node;
398#endif
399 const struct sh_pfc_soc_info *info;
400 struct sh_pfc *pfc;
401 int ret;
402
403#ifdef CONFIG_OF
404 if (np)
405 info = of_match_device(sh_pfc_of_table, &pdev->dev)->data;
406 else
407#endif
408 info = platid ? (const void *)platid->driver_data : NULL;
409
410 if (info == NULL)
411 return -ENODEV;
412
413 pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
414 if (pfc == NULL)
415 return -ENOMEM;
416
417 pfc->info = info;
418 pfc->dev = &pdev->dev;
419
420 ret = sh_pfc_ioremap(pfc, pdev);
421 if (unlikely(ret < 0))
422 return ret;
423
424 spin_lock_init(&pfc->lock);
425
426 if (info->ops && info->ops->init) {
427 ret = info->ops->init(pfc);
428 if (ret < 0)
429 return ret;
430 }
431
432 pinctrl_provide_dummies();
433
434 /*
435 * Initialize pinctrl bindings first
436 */
437 ret = sh_pfc_register_pinctrl(pfc);
438 if (unlikely(ret != 0))
439 goto error;
440
441#ifdef CONFIG_GPIO_SH_PFC
442 /*
443 * Then the GPIO chip
444 */
445 ret = sh_pfc_register_gpiochip(pfc);
446 if (unlikely(ret != 0)) {
447 /*
448 * If the GPIO chip fails to come up we still leave the
449 * PFC state as it is, given that there are already
450 * extant users of it that have succeeded by this point.
451 */
452 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
453 }
454#endif
455
456 platform_set_drvdata(pdev, pfc);
457
458 dev_info(pfc->dev, "%s support registered\n", info->name);
459
460 return 0;
461
462error:
463 if (info->ops && info->ops->exit)
464 info->ops->exit(pfc);
465 return ret;
466}
467
468static int sh_pfc_remove(struct platform_device *pdev)
469{
470 struct sh_pfc *pfc = platform_get_drvdata(pdev);
471
472#ifdef CONFIG_GPIO_SH_PFC
473 sh_pfc_unregister_gpiochip(pfc);
474#endif
475 sh_pfc_unregister_pinctrl(pfc);
476
477 if (pfc->info->ops && pfc->info->ops->exit)
478 pfc->info->ops->exit(pfc);
479
480 platform_set_drvdata(pdev, NULL);
481
482 return 0;
483}
484
485static const struct platform_device_id sh_pfc_id_table[] = {
486#ifdef CONFIG_PINCTRL_PFC_R8A73A4
487 { "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info },
488#endif
489#ifdef CONFIG_PINCTRL_PFC_R8A7740
490 { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
491#endif
492#ifdef CONFIG_PINCTRL_PFC_R8A7778
493 { "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info },
494#endif
495#ifdef CONFIG_PINCTRL_PFC_R8A7779
496 { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
497#endif
498#ifdef CONFIG_PINCTRL_PFC_R8A7790
499 { "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info },
500#endif
501#ifdef CONFIG_PINCTRL_PFC_SH7203
502 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
503#endif
504#ifdef CONFIG_PINCTRL_PFC_SH7264
505 { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
506#endif
507#ifdef CONFIG_PINCTRL_PFC_SH7269
508 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
509#endif
510#ifdef CONFIG_PINCTRL_PFC_SH7372
511 { "pfc-sh7372", (kernel_ulong_t)&sh7372_pinmux_info },
512#endif
513#ifdef CONFIG_PINCTRL_PFC_SH73A0
514 { "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info },
515#endif
516#ifdef CONFIG_PINCTRL_PFC_SH7720
517 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
518#endif
519#ifdef CONFIG_PINCTRL_PFC_SH7722
520 { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
521#endif
522#ifdef CONFIG_PINCTRL_PFC_SH7723
523 { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
524#endif
525#ifdef CONFIG_PINCTRL_PFC_SH7724
526 { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
527#endif
528#ifdef CONFIG_PINCTRL_PFC_SH7734
529 { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
530#endif
531#ifdef CONFIG_PINCTRL_PFC_SH7757
532 { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
533#endif
534#ifdef CONFIG_PINCTRL_PFC_SH7785
535 { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
536#endif
537#ifdef CONFIG_PINCTRL_PFC_SH7786
538 { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
539#endif
540#ifdef CONFIG_PINCTRL_PFC_SHX3
541 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
542#endif
543 { "sh-pfc", 0 },
544 { },
545};
546MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);
547
548static struct platform_driver sh_pfc_driver = {
549 .probe = sh_pfc_probe,
550 .remove = sh_pfc_remove,
551 .id_table = sh_pfc_id_table,
552 .driver = {
553 .name = DRV_NAME,
554 .owner = THIS_MODULE,
555 .of_match_table = of_match_ptr(sh_pfc_of_table),
556 },
557};
558
559static int __init sh_pfc_init(void)
560{
561 return platform_driver_register(&sh_pfc_driver);
562}
563postcore_initcall(sh_pfc_init);
564
565static void __exit sh_pfc_exit(void)
566{
567 platform_driver_unregister(&sh_pfc_driver);
568}
569module_exit(sh_pfc_exit);
570
571MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
572MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
573MODULE_LICENSE("GPL v2");
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