| 1 | /* |
| 2 | * Intel Low Power Subsystem PWM controller driver |
| 3 | * |
| 4 | * Copyright (C) 2014, Intel Corporation |
| 5 | * Author: Mika Westerberg <mika.westerberg@linux.intel.com> |
| 6 | * Author: Chew Kean Ho <kean.ho.chew@intel.com> |
| 7 | * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com> |
| 8 | * Author: Chew Chiau Ee <chiau.ee.chew@intel.com> |
| 9 | * Author: Alan Cox <alan@linux.intel.com> |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License version 2 as |
| 13 | * published by the Free Software Foundation. |
| 14 | */ |
| 15 | |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/module.h> |
| 18 | |
| 19 | #include "pwm-lpss.h" |
| 20 | |
| 21 | #define PWM 0x00000000 |
| 22 | #define PWM_ENABLE BIT(31) |
| 23 | #define PWM_SW_UPDATE BIT(30) |
| 24 | #define PWM_BASE_UNIT_SHIFT 8 |
| 25 | #define PWM_BASE_UNIT_MASK 0x00ffff00 |
| 26 | #define PWM_ON_TIME_DIV_MASK 0x000000ff |
| 27 | #define PWM_DIVISION_CORRECTION 0x2 |
| 28 | #define PWM_LIMIT (0x8000 + PWM_DIVISION_CORRECTION) |
| 29 | #define NSECS_PER_SEC 1000000000UL |
| 30 | |
| 31 | struct pwm_lpss_chip { |
| 32 | struct pwm_chip chip; |
| 33 | void __iomem *regs; |
| 34 | unsigned long clk_rate; |
| 35 | }; |
| 36 | |
| 37 | /* BayTrail */ |
| 38 | const struct pwm_lpss_boardinfo pwm_lpss_byt_info = { |
| 39 | 25000000 |
| 40 | }; |
| 41 | EXPORT_SYMBOL_GPL(pwm_lpss_byt_info); |
| 42 | |
| 43 | /* Braswell */ |
| 44 | const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = { |
| 45 | 19200000 |
| 46 | }; |
| 47 | EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info); |
| 48 | |
| 49 | static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip) |
| 50 | { |
| 51 | return container_of(chip, struct pwm_lpss_chip, chip); |
| 52 | } |
| 53 | |
| 54 | static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm, |
| 55 | int duty_ns, int period_ns) |
| 56 | { |
| 57 | struct pwm_lpss_chip *lpwm = to_lpwm(chip); |
| 58 | u8 on_time_div; |
| 59 | unsigned long c; |
| 60 | unsigned long long base_unit, freq = NSECS_PER_SEC; |
| 61 | u32 ctrl; |
| 62 | |
| 63 | do_div(freq, period_ns); |
| 64 | |
| 65 | /* The equation is: base_unit = ((freq / c) * 65536) + correction */ |
| 66 | base_unit = freq * 65536; |
| 67 | |
| 68 | c = lpwm->clk_rate; |
| 69 | if (!c) |
| 70 | return -EINVAL; |
| 71 | |
| 72 | do_div(base_unit, c); |
| 73 | base_unit += PWM_DIVISION_CORRECTION; |
| 74 | if (base_unit > PWM_LIMIT) |
| 75 | return -EINVAL; |
| 76 | |
| 77 | if (duty_ns <= 0) |
| 78 | duty_ns = 1; |
| 79 | on_time_div = 255 - (255 * duty_ns / period_ns); |
| 80 | |
| 81 | ctrl = readl(lpwm->regs + PWM); |
| 82 | ctrl &= ~(PWM_BASE_UNIT_MASK | PWM_ON_TIME_DIV_MASK); |
| 83 | ctrl |= (u16) base_unit << PWM_BASE_UNIT_SHIFT; |
| 84 | ctrl |= on_time_div; |
| 85 | /* request PWM to update on next cycle */ |
| 86 | ctrl |= PWM_SW_UPDATE; |
| 87 | writel(ctrl, lpwm->regs + PWM); |
| 88 | |
| 89 | return 0; |
| 90 | } |
| 91 | |
| 92 | static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
| 93 | { |
| 94 | struct pwm_lpss_chip *lpwm = to_lpwm(chip); |
| 95 | u32 ctrl; |
| 96 | |
| 97 | ctrl = readl(lpwm->regs + PWM); |
| 98 | writel(ctrl | PWM_ENABLE, lpwm->regs + PWM); |
| 99 | |
| 100 | return 0; |
| 101 | } |
| 102 | |
| 103 | static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm) |
| 104 | { |
| 105 | struct pwm_lpss_chip *lpwm = to_lpwm(chip); |
| 106 | u32 ctrl; |
| 107 | |
| 108 | ctrl = readl(lpwm->regs + PWM); |
| 109 | writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM); |
| 110 | } |
| 111 | |
| 112 | static const struct pwm_ops pwm_lpss_ops = { |
| 113 | .config = pwm_lpss_config, |
| 114 | .enable = pwm_lpss_enable, |
| 115 | .disable = pwm_lpss_disable, |
| 116 | .owner = THIS_MODULE, |
| 117 | }; |
| 118 | |
| 119 | struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r, |
| 120 | const struct pwm_lpss_boardinfo *info) |
| 121 | { |
| 122 | struct pwm_lpss_chip *lpwm; |
| 123 | int ret; |
| 124 | |
| 125 | lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL); |
| 126 | if (!lpwm) |
| 127 | return ERR_PTR(-ENOMEM); |
| 128 | |
| 129 | lpwm->regs = devm_ioremap_resource(dev, r); |
| 130 | if (IS_ERR(lpwm->regs)) |
| 131 | return ERR_CAST(lpwm->regs); |
| 132 | |
| 133 | lpwm->clk_rate = info->clk_rate; |
| 134 | lpwm->chip.dev = dev; |
| 135 | lpwm->chip.ops = &pwm_lpss_ops; |
| 136 | lpwm->chip.base = -1; |
| 137 | lpwm->chip.npwm = 1; |
| 138 | |
| 139 | ret = pwmchip_add(&lpwm->chip); |
| 140 | if (ret) { |
| 141 | dev_err(dev, "failed to add PWM chip: %d\n", ret); |
| 142 | return ERR_PTR(ret); |
| 143 | } |
| 144 | |
| 145 | return lpwm; |
| 146 | } |
| 147 | EXPORT_SYMBOL_GPL(pwm_lpss_probe); |
| 148 | |
| 149 | int pwm_lpss_remove(struct pwm_lpss_chip *lpwm) |
| 150 | { |
| 151 | u32 ctrl; |
| 152 | |
| 153 | ctrl = readl(lpwm->regs + PWM); |
| 154 | writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM); |
| 155 | |
| 156 | return pwmchip_remove(&lpwm->chip); |
| 157 | } |
| 158 | EXPORT_SYMBOL_GPL(pwm_lpss_remove); |
| 159 | |
| 160 | MODULE_DESCRIPTION("PWM driver for Intel LPSS"); |
| 161 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); |
| 162 | MODULE_LICENSE("GPL v2"); |