| 1 | /* tc-arm.c -- Assemble for the ARM |
| 2 | Copyright (C) 1994-2019 Free Software Foundation, Inc. |
| 3 | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) |
| 4 | Modified by David Taylor (dtaylor@armltd.co.uk) |
| 5 | Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) |
| 6 | Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) |
| 7 | Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) |
| 8 | |
| 9 | This file is part of GAS, the GNU Assembler. |
| 10 | |
| 11 | GAS is free software; you can redistribute it and/or modify |
| 12 | it under the terms of the GNU General Public License as published by |
| 13 | the Free Software Foundation; either version 3, or (at your option) |
| 14 | any later version. |
| 15 | |
| 16 | GAS is distributed in the hope that it will be useful, |
| 17 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | GNU General Public License for more details. |
| 20 | |
| 21 | You should have received a copy of the GNU General Public License |
| 22 | along with GAS; see the file COPYING. If not, write to the Free |
| 23 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
| 24 | 02110-1301, USA. */ |
| 25 | |
| 26 | #include "as.h" |
| 27 | #include <limits.h> |
| 28 | #include <stdarg.h> |
| 29 | #define NO_RELOC 0 |
| 30 | #include "safe-ctype.h" |
| 31 | #include "subsegs.h" |
| 32 | #include "obstack.h" |
| 33 | #include "libiberty.h" |
| 34 | #include "opcode/arm.h" |
| 35 | |
| 36 | #ifdef OBJ_ELF |
| 37 | #include "elf/arm.h" |
| 38 | #include "dw2gencfi.h" |
| 39 | #endif |
| 40 | |
| 41 | #include "dwarf2dbg.h" |
| 42 | |
| 43 | #ifdef OBJ_ELF |
| 44 | /* Must be at least the size of the largest unwind opcode (currently two). */ |
| 45 | #define ARM_OPCODE_CHUNK_SIZE 8 |
| 46 | |
| 47 | /* This structure holds the unwinding state. */ |
| 48 | |
| 49 | static struct |
| 50 | { |
| 51 | symbolS * proc_start; |
| 52 | symbolS * table_entry; |
| 53 | symbolS * personality_routine; |
| 54 | int personality_index; |
| 55 | /* The segment containing the function. */ |
| 56 | segT saved_seg; |
| 57 | subsegT saved_subseg; |
| 58 | /* Opcodes generated from this function. */ |
| 59 | unsigned char * opcodes; |
| 60 | int opcode_count; |
| 61 | int opcode_alloc; |
| 62 | /* The number of bytes pushed to the stack. */ |
| 63 | offsetT frame_size; |
| 64 | /* We don't add stack adjustment opcodes immediately so that we can merge |
| 65 | multiple adjustments. We can also omit the final adjustment |
| 66 | when using a frame pointer. */ |
| 67 | offsetT pending_offset; |
| 68 | /* These two fields are set by both unwind_movsp and unwind_setfp. They |
| 69 | hold the reg+offset to use when restoring sp from a frame pointer. */ |
| 70 | offsetT fp_offset; |
| 71 | int fp_reg; |
| 72 | /* Nonzero if an unwind_setfp directive has been seen. */ |
| 73 | unsigned fp_used:1; |
| 74 | /* Nonzero if the last opcode restores sp from fp_reg. */ |
| 75 | unsigned sp_restored:1; |
| 76 | } unwind; |
| 77 | |
| 78 | /* Whether --fdpic was given. */ |
| 79 | static int arm_fdpic; |
| 80 | |
| 81 | #endif /* OBJ_ELF */ |
| 82 | |
| 83 | /* Results from operand parsing worker functions. */ |
| 84 | |
| 85 | typedef enum |
| 86 | { |
| 87 | PARSE_OPERAND_SUCCESS, |
| 88 | PARSE_OPERAND_FAIL, |
| 89 | PARSE_OPERAND_FAIL_NO_BACKTRACK |
| 90 | } parse_operand_result; |
| 91 | |
| 92 | enum arm_float_abi |
| 93 | { |
| 94 | ARM_FLOAT_ABI_HARD, |
| 95 | ARM_FLOAT_ABI_SOFTFP, |
| 96 | ARM_FLOAT_ABI_SOFT |
| 97 | }; |
| 98 | |
| 99 | /* Types of processor to assemble for. */ |
| 100 | #ifndef CPU_DEFAULT |
| 101 | /* The code that was here used to select a default CPU depending on compiler |
| 102 | pre-defines which were only present when doing native builds, thus |
| 103 | changing gas' default behaviour depending upon the build host. |
| 104 | |
| 105 | If you have a target that requires a default CPU option then the you |
| 106 | should define CPU_DEFAULT here. */ |
| 107 | #endif |
| 108 | |
| 109 | #ifndef FPU_DEFAULT |
| 110 | # ifdef TE_LINUX |
| 111 | # define FPU_DEFAULT FPU_ARCH_FPA |
| 112 | # elif defined (TE_NetBSD) |
| 113 | # ifdef OBJ_ELF |
| 114 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ |
| 115 | # else |
| 116 | /* Legacy a.out format. */ |
| 117 | # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ |
| 118 | # endif |
| 119 | # elif defined (TE_VXWORKS) |
| 120 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ |
| 121 | # else |
| 122 | /* For backwards compatibility, default to FPA. */ |
| 123 | # define FPU_DEFAULT FPU_ARCH_FPA |
| 124 | # endif |
| 125 | #endif /* ifndef FPU_DEFAULT */ |
| 126 | |
| 127 | #define streq(a, b) (strcmp (a, b) == 0) |
| 128 | |
| 129 | /* Current set of feature bits available (CPU+FPU). Different from |
| 130 | selected_cpu + selected_fpu in case of autodetection since the CPU |
| 131 | feature bits are then all set. */ |
| 132 | static arm_feature_set cpu_variant; |
| 133 | /* Feature bits used in each execution state. Used to set build attribute |
| 134 | (in particular Tag_*_ISA_use) in CPU autodetection mode. */ |
| 135 | static arm_feature_set arm_arch_used; |
| 136 | static arm_feature_set thumb_arch_used; |
| 137 | |
| 138 | /* Flags stored in private area of BFD structure. */ |
| 139 | static int uses_apcs_26 = FALSE; |
| 140 | static int atpcs = FALSE; |
| 141 | static int support_interwork = FALSE; |
| 142 | static int uses_apcs_float = FALSE; |
| 143 | static int pic_code = FALSE; |
| 144 | static int fix_v4bx = FALSE; |
| 145 | /* Warn on using deprecated features. */ |
| 146 | static int warn_on_deprecated = TRUE; |
| 147 | |
| 148 | /* Understand CodeComposer Studio assembly syntax. */ |
| 149 | bfd_boolean codecomposer_syntax = FALSE; |
| 150 | |
| 151 | /* Variables that we set while parsing command-line options. Once all |
| 152 | options have been read we re-process these values to set the real |
| 153 | assembly flags. */ |
| 154 | |
| 155 | /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1 |
| 156 | instead of -mcpu=arm1). */ |
| 157 | static const arm_feature_set *legacy_cpu = NULL; |
| 158 | static const arm_feature_set *legacy_fpu = NULL; |
| 159 | |
| 160 | /* CPU, extension and FPU feature bits selected by -mcpu. */ |
| 161 | static const arm_feature_set *mcpu_cpu_opt = NULL; |
| 162 | static arm_feature_set *mcpu_ext_opt = NULL; |
| 163 | static const arm_feature_set *mcpu_fpu_opt = NULL; |
| 164 | |
| 165 | /* CPU, extension and FPU feature bits selected by -march. */ |
| 166 | static const arm_feature_set *march_cpu_opt = NULL; |
| 167 | static arm_feature_set *march_ext_opt = NULL; |
| 168 | static const arm_feature_set *march_fpu_opt = NULL; |
| 169 | |
| 170 | /* Feature bits selected by -mfpu. */ |
| 171 | static const arm_feature_set *mfpu_opt = NULL; |
| 172 | |
| 173 | /* Constants for known architecture features. */ |
| 174 | static const arm_feature_set fpu_default = FPU_DEFAULT; |
| 175 | static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V1; |
| 176 | static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; |
| 177 | static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V3; |
| 178 | static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED = FPU_ARCH_NEON_V1; |
| 179 | static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; |
| 180 | static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; |
| 181 | #ifdef OBJ_ELF |
| 182 | static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; |
| 183 | #endif |
| 184 | static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; |
| 185 | |
| 186 | #ifdef CPU_DEFAULT |
| 187 | static const arm_feature_set cpu_default = CPU_DEFAULT; |
| 188 | #endif |
| 189 | |
| 190 | static const arm_feature_set arm_ext_v1 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1); |
| 191 | static const arm_feature_set arm_ext_v2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V2); |
| 192 | static const arm_feature_set arm_ext_v2s = ARM_FEATURE_CORE_LOW (ARM_EXT_V2S); |
| 193 | static const arm_feature_set arm_ext_v3 = ARM_FEATURE_CORE_LOW (ARM_EXT_V3); |
| 194 | static const arm_feature_set arm_ext_v3m = ARM_FEATURE_CORE_LOW (ARM_EXT_V3M); |
| 195 | static const arm_feature_set arm_ext_v4 = ARM_FEATURE_CORE_LOW (ARM_EXT_V4); |
| 196 | static const arm_feature_set arm_ext_v4t = ARM_FEATURE_CORE_LOW (ARM_EXT_V4T); |
| 197 | static const arm_feature_set arm_ext_v5 = ARM_FEATURE_CORE_LOW (ARM_EXT_V5); |
| 198 | static const arm_feature_set arm_ext_v4t_5 = |
| 199 | ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5); |
| 200 | static const arm_feature_set arm_ext_v5t = ARM_FEATURE_CORE_LOW (ARM_EXT_V5T); |
| 201 | static const arm_feature_set arm_ext_v5e = ARM_FEATURE_CORE_LOW (ARM_EXT_V5E); |
| 202 | static const arm_feature_set arm_ext_v5exp = ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP); |
| 203 | static const arm_feature_set arm_ext_v5j = ARM_FEATURE_CORE_LOW (ARM_EXT_V5J); |
| 204 | static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6); |
| 205 | static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K); |
| 206 | static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2); |
| 207 | /* Only for compatability of hint instructions. */ |
| 208 | static const arm_feature_set arm_ext_v6k_v6t2 = |
| 209 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6K | ARM_EXT_V6T2); |
| 210 | static const arm_feature_set arm_ext_v6_notm = |
| 211 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM); |
| 212 | static const arm_feature_set arm_ext_v6_dsp = |
| 213 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP); |
| 214 | static const arm_feature_set arm_ext_barrier = |
| 215 | ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER); |
| 216 | static const arm_feature_set arm_ext_msr = |
| 217 | ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR); |
| 218 | static const arm_feature_set arm_ext_div = ARM_FEATURE_CORE_LOW (ARM_EXT_DIV); |
| 219 | static const arm_feature_set arm_ext_v7 = ARM_FEATURE_CORE_LOW (ARM_EXT_V7); |
| 220 | static const arm_feature_set arm_ext_v7a = ARM_FEATURE_CORE_LOW (ARM_EXT_V7A); |
| 221 | static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R); |
| 222 | #ifdef OBJ_ELF |
| 223 | static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M); |
| 224 | #endif |
| 225 | static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8); |
| 226 | static const arm_feature_set arm_ext_m = |
| 227 | ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_V7M, |
| 228 | ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN); |
| 229 | static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP); |
| 230 | static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC); |
| 231 | static const arm_feature_set arm_ext_os = ARM_FEATURE_CORE_LOW (ARM_EXT_OS); |
| 232 | static const arm_feature_set arm_ext_adiv = ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV); |
| 233 | static const arm_feature_set arm_ext_virt = ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT); |
| 234 | static const arm_feature_set arm_ext_pan = ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN); |
| 235 | static const arm_feature_set arm_ext_v8m = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M); |
| 236 | static const arm_feature_set arm_ext_v8m_main = |
| 237 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN); |
| 238 | static const arm_feature_set arm_ext_v8_1m_main = |
| 239 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN); |
| 240 | /* Instructions in ARMv8-M only found in M profile architectures. */ |
| 241 | static const arm_feature_set arm_ext_v8m_m_only = |
| 242 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN); |
| 243 | static const arm_feature_set arm_ext_v6t2_v8m = |
| 244 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M); |
| 245 | /* Instructions shared between ARMv8-A and ARMv8-M. */ |
| 246 | static const arm_feature_set arm_ext_atomics = |
| 247 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS); |
| 248 | #ifdef OBJ_ELF |
| 249 | /* DSP instructions Tag_DSP_extension refers to. */ |
| 250 | static const arm_feature_set arm_ext_dsp = |
| 251 | ARM_FEATURE_CORE_LOW (ARM_EXT_V5E | ARM_EXT_V5ExP | ARM_EXT_V6_DSP); |
| 252 | #endif |
| 253 | static const arm_feature_set arm_ext_ras = |
| 254 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS); |
| 255 | /* FP16 instructions. */ |
| 256 | static const arm_feature_set arm_ext_fp16 = |
| 257 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST); |
| 258 | static const arm_feature_set arm_ext_fp16_fml = |
| 259 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML); |
| 260 | static const arm_feature_set arm_ext_v8_2 = |
| 261 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A); |
| 262 | static const arm_feature_set arm_ext_v8_3 = |
| 263 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A); |
| 264 | static const arm_feature_set arm_ext_sb = |
| 265 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB); |
| 266 | static const arm_feature_set arm_ext_predres = |
| 267 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES); |
| 268 | |
| 269 | static const arm_feature_set arm_arch_any = ARM_ANY; |
| 270 | #ifdef OBJ_ELF |
| 271 | static const arm_feature_set fpu_any = FPU_ANY; |
| 272 | #endif |
| 273 | static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED = ARM_FEATURE (-1, -1, -1); |
| 274 | static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; |
| 275 | static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; |
| 276 | |
| 277 | static const arm_feature_set arm_cext_iwmmxt2 = |
| 278 | ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2); |
| 279 | static const arm_feature_set arm_cext_iwmmxt = |
| 280 | ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT); |
| 281 | static const arm_feature_set arm_cext_xscale = |
| 282 | ARM_FEATURE_COPROC (ARM_CEXT_XSCALE); |
| 283 | static const arm_feature_set arm_cext_maverick = |
| 284 | ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK); |
| 285 | static const arm_feature_set fpu_fpa_ext_v1 = |
| 286 | ARM_FEATURE_COPROC (FPU_FPA_EXT_V1); |
| 287 | static const arm_feature_set fpu_fpa_ext_v2 = |
| 288 | ARM_FEATURE_COPROC (FPU_FPA_EXT_V2); |
| 289 | static const arm_feature_set fpu_vfp_ext_v1xd = |
| 290 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD); |
| 291 | static const arm_feature_set fpu_vfp_ext_v1 = |
| 292 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V1); |
| 293 | static const arm_feature_set fpu_vfp_ext_v2 = |
| 294 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V2); |
| 295 | static const arm_feature_set fpu_vfp_ext_v3xd = |
| 296 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD); |
| 297 | static const arm_feature_set fpu_vfp_ext_v3 = |
| 298 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V3); |
| 299 | static const arm_feature_set fpu_vfp_ext_d32 = |
| 300 | ARM_FEATURE_COPROC (FPU_VFP_EXT_D32); |
| 301 | static const arm_feature_set fpu_neon_ext_v1 = |
| 302 | ARM_FEATURE_COPROC (FPU_NEON_EXT_V1); |
| 303 | static const arm_feature_set fpu_vfp_v3_or_neon_ext = |
| 304 | ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); |
| 305 | static const arm_feature_set mve_ext = |
| 306 | ARM_FEATURE_COPROC (FPU_MVE); |
| 307 | static const arm_feature_set mve_fp_ext = |
| 308 | ARM_FEATURE_COPROC (FPU_MVE_FP); |
| 309 | #ifdef OBJ_ELF |
| 310 | static const arm_feature_set fpu_vfp_fp16 = |
| 311 | ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16); |
| 312 | static const arm_feature_set fpu_neon_ext_fma = |
| 313 | ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA); |
| 314 | #endif |
| 315 | static const arm_feature_set fpu_vfp_ext_fma = |
| 316 | ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA); |
| 317 | static const arm_feature_set fpu_vfp_ext_armv8 = |
| 318 | ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8); |
| 319 | static const arm_feature_set fpu_vfp_ext_armv8xd = |
| 320 | ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD); |
| 321 | static const arm_feature_set fpu_neon_ext_armv8 = |
| 322 | ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8); |
| 323 | static const arm_feature_set fpu_crypto_ext_armv8 = |
| 324 | ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8); |
| 325 | static const arm_feature_set crc_ext_armv8 = |
| 326 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8); |
| 327 | static const arm_feature_set fpu_neon_ext_v8_1 = |
| 328 | ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA); |
| 329 | static const arm_feature_set fpu_neon_ext_dotprod = |
| 330 | ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD); |
| 331 | |
| 332 | static int mfloat_abi_opt = -1; |
| 333 | /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch |
| 334 | directive. */ |
| 335 | static arm_feature_set selected_arch = ARM_ARCH_NONE; |
| 336 | /* Extension feature bits selected by the last -mcpu/-march or .arch_extension |
| 337 | directive. */ |
| 338 | static arm_feature_set selected_ext = ARM_ARCH_NONE; |
| 339 | /* Feature bits selected by the last -mcpu/-march or by the combination of the |
| 340 | last .cpu/.arch directive .arch_extension directives since that |
| 341 | directive. */ |
| 342 | static arm_feature_set selected_cpu = ARM_ARCH_NONE; |
| 343 | /* FPU feature bits selected by the last -mfpu or .fpu directive. */ |
| 344 | static arm_feature_set selected_fpu = FPU_NONE; |
| 345 | /* Feature bits selected by the last .object_arch directive. */ |
| 346 | static arm_feature_set selected_object_arch = ARM_ARCH_NONE; |
| 347 | /* Must be long enough to hold any of the names in arm_cpus. */ |
| 348 | static char selected_cpu_name[20]; |
| 349 | |
| 350 | extern FLONUM_TYPE generic_floating_point_number; |
| 351 | |
| 352 | /* Return if no cpu was selected on command-line. */ |
| 353 | static bfd_boolean |
| 354 | no_cpu_selected (void) |
| 355 | { |
| 356 | return ARM_FEATURE_EQUAL (selected_cpu, arm_arch_none); |
| 357 | } |
| 358 | |
| 359 | #ifdef OBJ_ELF |
| 360 | # ifdef EABI_DEFAULT |
| 361 | static int meabi_flags = EABI_DEFAULT; |
| 362 | # else |
| 363 | static int meabi_flags = EF_ARM_EABI_UNKNOWN; |
| 364 | # endif |
| 365 | |
| 366 | static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES]; |
| 367 | |
| 368 | bfd_boolean |
| 369 | arm_is_eabi (void) |
| 370 | { |
| 371 | return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4); |
| 372 | } |
| 373 | #endif |
| 374 | |
| 375 | #ifdef OBJ_ELF |
| 376 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
| 377 | symbolS * GOT_symbol; |
| 378 | #endif |
| 379 | |
| 380 | /* 0: assemble for ARM, |
| 381 | 1: assemble for Thumb, |
| 382 | 2: assemble for Thumb even though target CPU does not support thumb |
| 383 | instructions. */ |
| 384 | static int thumb_mode = 0; |
| 385 | /* A value distinct from the possible values for thumb_mode that we |
| 386 | can use to record whether thumb_mode has been copied into the |
| 387 | tc_frag_data field of a frag. */ |
| 388 | #define MODE_RECORDED (1 << 4) |
| 389 | |
| 390 | /* Specifies the intrinsic IT insn behavior mode. */ |
| 391 | enum implicit_it_mode |
| 392 | { |
| 393 | IMPLICIT_IT_MODE_NEVER = 0x00, |
| 394 | IMPLICIT_IT_MODE_ARM = 0x01, |
| 395 | IMPLICIT_IT_MODE_THUMB = 0x02, |
| 396 | IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB) |
| 397 | }; |
| 398 | static int implicit_it_mode = IMPLICIT_IT_MODE_ARM; |
| 399 | |
| 400 | /* If unified_syntax is true, we are processing the new unified |
| 401 | ARM/Thumb syntax. Important differences from the old ARM mode: |
| 402 | |
| 403 | - Immediate operands do not require a # prefix. |
| 404 | - Conditional affixes always appear at the end of the |
| 405 | instruction. (For backward compatibility, those instructions |
| 406 | that formerly had them in the middle, continue to accept them |
| 407 | there.) |
| 408 | - The IT instruction may appear, and if it does is validated |
| 409 | against subsequent conditional affixes. It does not generate |
| 410 | machine code. |
| 411 | |
| 412 | Important differences from the old Thumb mode: |
| 413 | |
| 414 | - Immediate operands do not require a # prefix. |
| 415 | - Most of the V6T2 instructions are only available in unified mode. |
| 416 | - The .N and .W suffixes are recognized and honored (it is an error |
| 417 | if they cannot be honored). |
| 418 | - All instructions set the flags if and only if they have an 's' affix. |
| 419 | - Conditional affixes may be used. They are validated against |
| 420 | preceding IT instructions. Unlike ARM mode, you cannot use a |
| 421 | conditional affix except in the scope of an IT instruction. */ |
| 422 | |
| 423 | static bfd_boolean unified_syntax = FALSE; |
| 424 | |
| 425 | /* An immediate operand can start with #, and ld*, st*, pld operands |
| 426 | can contain [ and ]. We need to tell APP not to elide whitespace |
| 427 | before a [, which can appear as the first operand for pld. |
| 428 | Likewise, a { can appear as the first operand for push, pop, vld*, etc. */ |
| 429 | const char arm_symbol_chars[] = "#[]{}"; |
| 430 | |
| 431 | enum neon_el_type |
| 432 | { |
| 433 | NT_invtype, |
| 434 | NT_untyped, |
| 435 | NT_integer, |
| 436 | NT_float, |
| 437 | NT_poly, |
| 438 | NT_signed, |
| 439 | NT_unsigned |
| 440 | }; |
| 441 | |
| 442 | struct neon_type_el |
| 443 | { |
| 444 | enum neon_el_type type; |
| 445 | unsigned size; |
| 446 | }; |
| 447 | |
| 448 | #define NEON_MAX_TYPE_ELS 4 |
| 449 | |
| 450 | struct neon_type |
| 451 | { |
| 452 | struct neon_type_el el[NEON_MAX_TYPE_ELS]; |
| 453 | unsigned elems; |
| 454 | }; |
| 455 | |
| 456 | enum pred_instruction_type |
| 457 | { |
| 458 | OUTSIDE_PRED_INSN, |
| 459 | INSIDE_VPT_INSN, |
| 460 | INSIDE_IT_INSN, |
| 461 | INSIDE_IT_LAST_INSN, |
| 462 | IF_INSIDE_IT_LAST_INSN, /* Either outside or inside; |
| 463 | if inside, should be the last one. */ |
| 464 | NEUTRAL_IT_INSN, /* This could be either inside or outside, |
| 465 | i.e. BKPT and NOP. */ |
| 466 | IT_INSN, /* The IT insn has been parsed. */ |
| 467 | VPT_INSN, /* The VPT/VPST insn has been parsed. */ |
| 468 | MVE_OUTSIDE_PRED_INSN , /* Instruction to indicate a MVE instruction without |
| 469 | a predication code. */ |
| 470 | MVE_UNPREDICABLE_INSN /* MVE instruction that is non-predicable. */ |
| 471 | }; |
| 472 | |
| 473 | /* The maximum number of operands we need. */ |
| 474 | #define ARM_IT_MAX_OPERANDS 6 |
| 475 | #define ARM_IT_MAX_RELOCS 3 |
| 476 | |
| 477 | struct arm_it |
| 478 | { |
| 479 | const char * error; |
| 480 | unsigned long instruction; |
| 481 | int size; |
| 482 | int size_req; |
| 483 | int cond; |
| 484 | /* "uncond_value" is set to the value in place of the conditional field in |
| 485 | unconditional versions of the instruction, or -1 if nothing is |
| 486 | appropriate. */ |
| 487 | int uncond_value; |
| 488 | struct neon_type vectype; |
| 489 | /* This does not indicate an actual NEON instruction, only that |
| 490 | the mnemonic accepts neon-style type suffixes. */ |
| 491 | int is_neon; |
| 492 | /* Set to the opcode if the instruction needs relaxation. |
| 493 | Zero if the instruction is not relaxed. */ |
| 494 | unsigned long relax; |
| 495 | struct |
| 496 | { |
| 497 | bfd_reloc_code_real_type type; |
| 498 | expressionS exp; |
| 499 | int pc_rel; |
| 500 | } relocs[ARM_IT_MAX_RELOCS]; |
| 501 | |
| 502 | enum pred_instruction_type pred_insn_type; |
| 503 | |
| 504 | struct |
| 505 | { |
| 506 | unsigned reg; |
| 507 | signed int imm; |
| 508 | struct neon_type_el vectype; |
| 509 | unsigned present : 1; /* Operand present. */ |
| 510 | unsigned isreg : 1; /* Operand was a register. */ |
| 511 | unsigned immisreg : 2; /* .imm field is a second register. |
| 512 | 0: imm, 1: gpr, 2: MVE Q-register. */ |
| 513 | unsigned isscalar : 2; /* Operand is a (SIMD) scalar: |
| 514 | 0) not scalar, |
| 515 | 1) Neon scalar, |
| 516 | 2) MVE scalar. */ |
| 517 | unsigned immisalign : 1; /* Immediate is an alignment specifier. */ |
| 518 | unsigned immisfloat : 1; /* Immediate was parsed as a float. */ |
| 519 | /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV |
| 520 | instructions. This allows us to disambiguate ARM <-> vector insns. */ |
| 521 | unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ |
| 522 | unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ |
| 523 | unsigned isquad : 1; /* Operand is SIMD quad register. */ |
| 524 | unsigned issingle : 1; /* Operand is VFP single-precision register. */ |
| 525 | unsigned iszr : 1; /* Operand is ZR register. */ |
| 526 | unsigned hasreloc : 1; /* Operand has relocation suffix. */ |
| 527 | unsigned writeback : 1; /* Operand has trailing ! */ |
| 528 | unsigned preind : 1; /* Preindexed address. */ |
| 529 | unsigned postind : 1; /* Postindexed address. */ |
| 530 | unsigned negative : 1; /* Index register was negated. */ |
| 531 | unsigned shifted : 1; /* Shift applied to operation. */ |
| 532 | unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ |
| 533 | } operands[ARM_IT_MAX_OPERANDS]; |
| 534 | }; |
| 535 | |
| 536 | static struct arm_it inst; |
| 537 | |
| 538 | #define NUM_FLOAT_VALS 8 |
| 539 | |
| 540 | const char * fp_const[] = |
| 541 | { |
| 542 | "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 |
| 543 | }; |
| 544 | |
| 545 | LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; |
| 546 | |
| 547 | #define FAIL (-1) |
| 548 | #define SUCCESS (0) |
| 549 | |
| 550 | #define SUFF_S 1 |
| 551 | #define SUFF_D 2 |
| 552 | #define SUFF_E 3 |
| 553 | #define SUFF_P 4 |
| 554 | |
| 555 | #define CP_T_X 0x00008000 |
| 556 | #define CP_T_Y 0x00400000 |
| 557 | |
| 558 | #define CONDS_BIT 0x00100000 |
| 559 | #define LOAD_BIT 0x00100000 |
| 560 | |
| 561 | #define DOUBLE_LOAD_FLAG 0x00000001 |
| 562 | |
| 563 | struct asm_cond |
| 564 | { |
| 565 | const char * template_name; |
| 566 | unsigned long value; |
| 567 | }; |
| 568 | |
| 569 | #define COND_ALWAYS 0xE |
| 570 | |
| 571 | struct asm_psr |
| 572 | { |
| 573 | const char * template_name; |
| 574 | unsigned long field; |
| 575 | }; |
| 576 | |
| 577 | struct asm_barrier_opt |
| 578 | { |
| 579 | const char * template_name; |
| 580 | unsigned long value; |
| 581 | const arm_feature_set arch; |
| 582 | }; |
| 583 | |
| 584 | /* The bit that distinguishes CPSR and SPSR. */ |
| 585 | #define SPSR_BIT (1 << 22) |
| 586 | |
| 587 | /* The individual PSR flag bits. */ |
| 588 | #define PSR_c (1 << 16) |
| 589 | #define PSR_x (1 << 17) |
| 590 | #define PSR_s (1 << 18) |
| 591 | #define PSR_f (1 << 19) |
| 592 | |
| 593 | struct reloc_entry |
| 594 | { |
| 595 | const char * name; |
| 596 | bfd_reloc_code_real_type reloc; |
| 597 | }; |
| 598 | |
| 599 | enum vfp_reg_pos |
| 600 | { |
| 601 | VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, |
| 602 | VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn |
| 603 | }; |
| 604 | |
| 605 | enum vfp_ldstm_type |
| 606 | { |
| 607 | VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX |
| 608 | }; |
| 609 | |
| 610 | /* Bits for DEFINED field in neon_typed_alias. */ |
| 611 | #define NTA_HASTYPE 1 |
| 612 | #define NTA_HASINDEX 2 |
| 613 | |
| 614 | struct neon_typed_alias |
| 615 | { |
| 616 | unsigned char defined; |
| 617 | unsigned char index; |
| 618 | struct neon_type_el eltype; |
| 619 | }; |
| 620 | |
| 621 | /* ARM register categories. This includes coprocessor numbers and various |
| 622 | architecture extensions' registers. Each entry should have an error message |
| 623 | in reg_expected_msgs below. */ |
| 624 | enum arm_reg_type |
| 625 | { |
| 626 | REG_TYPE_RN, |
| 627 | REG_TYPE_CP, |
| 628 | REG_TYPE_CN, |
| 629 | REG_TYPE_FN, |
| 630 | REG_TYPE_VFS, |
| 631 | REG_TYPE_VFD, |
| 632 | REG_TYPE_NQ, |
| 633 | REG_TYPE_VFSD, |
| 634 | REG_TYPE_NDQ, |
| 635 | REG_TYPE_NSD, |
| 636 | REG_TYPE_NSDQ, |
| 637 | REG_TYPE_VFC, |
| 638 | REG_TYPE_MVF, |
| 639 | REG_TYPE_MVD, |
| 640 | REG_TYPE_MVFX, |
| 641 | REG_TYPE_MVDX, |
| 642 | REG_TYPE_MVAX, |
| 643 | REG_TYPE_MQ, |
| 644 | REG_TYPE_DSPSC, |
| 645 | REG_TYPE_MMXWR, |
| 646 | REG_TYPE_MMXWC, |
| 647 | REG_TYPE_MMXWCG, |
| 648 | REG_TYPE_XSCALE, |
| 649 | REG_TYPE_RNB, |
| 650 | REG_TYPE_ZR |
| 651 | }; |
| 652 | |
| 653 | /* Structure for a hash table entry for a register. |
| 654 | If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra |
| 655 | information which states whether a vector type or index is specified (for a |
| 656 | register alias created with .dn or .qn). Otherwise NEON should be NULL. */ |
| 657 | struct reg_entry |
| 658 | { |
| 659 | const char * name; |
| 660 | unsigned int number; |
| 661 | unsigned char type; |
| 662 | unsigned char builtin; |
| 663 | struct neon_typed_alias * neon; |
| 664 | }; |
| 665 | |
| 666 | /* Diagnostics used when we don't get a register of the expected type. */ |
| 667 | const char * const reg_expected_msgs[] = |
| 668 | { |
| 669 | [REG_TYPE_RN] = N_("ARM register expected"), |
| 670 | [REG_TYPE_CP] = N_("bad or missing co-processor number"), |
| 671 | [REG_TYPE_CN] = N_("co-processor register expected"), |
| 672 | [REG_TYPE_FN] = N_("FPA register expected"), |
| 673 | [REG_TYPE_VFS] = N_("VFP single precision register expected"), |
| 674 | [REG_TYPE_VFD] = N_("VFP/Neon double precision register expected"), |
| 675 | [REG_TYPE_NQ] = N_("Neon quad precision register expected"), |
| 676 | [REG_TYPE_VFSD] = N_("VFP single or double precision register expected"), |
| 677 | [REG_TYPE_NDQ] = N_("Neon double or quad precision register expected"), |
| 678 | [REG_TYPE_NSD] = N_("Neon single or double precision register expected"), |
| 679 | [REG_TYPE_NSDQ] = N_("VFP single, double or Neon quad precision register" |
| 680 | " expected"), |
| 681 | [REG_TYPE_VFC] = N_("VFP system register expected"), |
| 682 | [REG_TYPE_MVF] = N_("Maverick MVF register expected"), |
| 683 | [REG_TYPE_MVD] = N_("Maverick MVD register expected"), |
| 684 | [REG_TYPE_MVFX] = N_("Maverick MVFX register expected"), |
| 685 | [REG_TYPE_MVDX] = N_("Maverick MVDX register expected"), |
| 686 | [REG_TYPE_MVAX] = N_("Maverick MVAX register expected"), |
| 687 | [REG_TYPE_DSPSC] = N_("Maverick DSPSC register expected"), |
| 688 | [REG_TYPE_MMXWR] = N_("iWMMXt data register expected"), |
| 689 | [REG_TYPE_MMXWC] = N_("iWMMXt control register expected"), |
| 690 | [REG_TYPE_MMXWCG] = N_("iWMMXt scalar register expected"), |
| 691 | [REG_TYPE_XSCALE] = N_("XScale accumulator register expected"), |
| 692 | [REG_TYPE_MQ] = N_("MVE vector register expected"), |
| 693 | [REG_TYPE_RNB] = N_("") |
| 694 | }; |
| 695 | |
| 696 | /* Some well known registers that we refer to directly elsewhere. */ |
| 697 | #define REG_R12 12 |
| 698 | #define REG_SP 13 |
| 699 | #define REG_LR 14 |
| 700 | #define REG_PC 15 |
| 701 | |
| 702 | /* ARM instructions take 4bytes in the object file, Thumb instructions |
| 703 | take 2: */ |
| 704 | #define INSN_SIZE 4 |
| 705 | |
| 706 | struct asm_opcode |
| 707 | { |
| 708 | /* Basic string to match. */ |
| 709 | const char * template_name; |
| 710 | |
| 711 | /* Parameters to instruction. */ |
| 712 | unsigned int operands[8]; |
| 713 | |
| 714 | /* Conditional tag - see opcode_lookup. */ |
| 715 | unsigned int tag : 4; |
| 716 | |
| 717 | /* Basic instruction code. */ |
| 718 | unsigned int avalue; |
| 719 | |
| 720 | /* Thumb-format instruction code. */ |
| 721 | unsigned int tvalue; |
| 722 | |
| 723 | /* Which architecture variant provides this instruction. */ |
| 724 | const arm_feature_set * avariant; |
| 725 | const arm_feature_set * tvariant; |
| 726 | |
| 727 | /* Function to call to encode instruction in ARM format. */ |
| 728 | void (* aencode) (void); |
| 729 | |
| 730 | /* Function to call to encode instruction in Thumb format. */ |
| 731 | void (* tencode) (void); |
| 732 | |
| 733 | /* Indicates whether this instruction may be vector predicated. */ |
| 734 | unsigned int mayBeVecPred : 1; |
| 735 | }; |
| 736 | |
| 737 | /* Defines for various bits that we will want to toggle. */ |
| 738 | #define INST_IMMEDIATE 0x02000000 |
| 739 | #define OFFSET_REG 0x02000000 |
| 740 | #define HWOFFSET_IMM 0x00400000 |
| 741 | #define SHIFT_BY_REG 0x00000010 |
| 742 | #define PRE_INDEX 0x01000000 |
| 743 | #define INDEX_UP 0x00800000 |
| 744 | #define WRITE_BACK 0x00200000 |
| 745 | #define LDM_TYPE_2_OR_3 0x00400000 |
| 746 | #define CPSI_MMOD 0x00020000 |
| 747 | |
| 748 | #define LITERAL_MASK 0xf000f000 |
| 749 | #define OPCODE_MASK 0xfe1fffff |
| 750 | #define V4_STR_BIT 0x00000020 |
| 751 | #define VLDR_VMOV_SAME 0x0040f000 |
| 752 | |
| 753 | #define T2_SUBS_PC_LR 0xf3de8f00 |
| 754 | |
| 755 | #define DATA_OP_SHIFT 21 |
| 756 | #define SBIT_SHIFT 20 |
| 757 | |
| 758 | #define T2_OPCODE_MASK 0xfe1fffff |
| 759 | #define T2_DATA_OP_SHIFT 21 |
| 760 | #define T2_SBIT_SHIFT 20 |
| 761 | |
| 762 | #define A_COND_MASK 0xf0000000 |
| 763 | #define A_PUSH_POP_OP_MASK 0x0fff0000 |
| 764 | |
| 765 | /* Opcodes for pushing/poping registers to/from the stack. */ |
| 766 | #define A1_OPCODE_PUSH 0x092d0000 |
| 767 | #define A2_OPCODE_PUSH 0x052d0004 |
| 768 | #define A2_OPCODE_POP 0x049d0004 |
| 769 | |
| 770 | /* Codes to distinguish the arithmetic instructions. */ |
| 771 | #define OPCODE_AND 0 |
| 772 | #define OPCODE_EOR 1 |
| 773 | #define OPCODE_SUB 2 |
| 774 | #define OPCODE_RSB 3 |
| 775 | #define OPCODE_ADD 4 |
| 776 | #define OPCODE_ADC 5 |
| 777 | #define OPCODE_SBC 6 |
| 778 | #define OPCODE_RSC 7 |
| 779 | #define OPCODE_TST 8 |
| 780 | #define OPCODE_TEQ 9 |
| 781 | #define OPCODE_CMP 10 |
| 782 | #define OPCODE_CMN 11 |
| 783 | #define OPCODE_ORR 12 |
| 784 | #define OPCODE_MOV 13 |
| 785 | #define OPCODE_BIC 14 |
| 786 | #define OPCODE_MVN 15 |
| 787 | |
| 788 | #define T2_OPCODE_AND 0 |
| 789 | #define T2_OPCODE_BIC 1 |
| 790 | #define T2_OPCODE_ORR 2 |
| 791 | #define T2_OPCODE_ORN 3 |
| 792 | #define T2_OPCODE_EOR 4 |
| 793 | #define T2_OPCODE_ADD 8 |
| 794 | #define T2_OPCODE_ADC 10 |
| 795 | #define T2_OPCODE_SBC 11 |
| 796 | #define T2_OPCODE_SUB 13 |
| 797 | #define T2_OPCODE_RSB 14 |
| 798 | |
| 799 | #define T_OPCODE_MUL 0x4340 |
| 800 | #define T_OPCODE_TST 0x4200 |
| 801 | #define T_OPCODE_CMN 0x42c0 |
| 802 | #define T_OPCODE_NEG 0x4240 |
| 803 | #define T_OPCODE_MVN 0x43c0 |
| 804 | |
| 805 | #define T_OPCODE_ADD_R3 0x1800 |
| 806 | #define T_OPCODE_SUB_R3 0x1a00 |
| 807 | #define T_OPCODE_ADD_HI 0x4400 |
| 808 | #define T_OPCODE_ADD_ST 0xb000 |
| 809 | #define T_OPCODE_SUB_ST 0xb080 |
| 810 | #define T_OPCODE_ADD_SP 0xa800 |
| 811 | #define T_OPCODE_ADD_PC 0xa000 |
| 812 | #define T_OPCODE_ADD_I8 0x3000 |
| 813 | #define T_OPCODE_SUB_I8 0x3800 |
| 814 | #define T_OPCODE_ADD_I3 0x1c00 |
| 815 | #define T_OPCODE_SUB_I3 0x1e00 |
| 816 | |
| 817 | #define T_OPCODE_ASR_R 0x4100 |
| 818 | #define T_OPCODE_LSL_R 0x4080 |
| 819 | #define T_OPCODE_LSR_R 0x40c0 |
| 820 | #define T_OPCODE_ROR_R 0x41c0 |
| 821 | #define T_OPCODE_ASR_I 0x1000 |
| 822 | #define T_OPCODE_LSL_I 0x0000 |
| 823 | #define T_OPCODE_LSR_I 0x0800 |
| 824 | |
| 825 | #define T_OPCODE_MOV_I8 0x2000 |
| 826 | #define T_OPCODE_CMP_I8 0x2800 |
| 827 | #define T_OPCODE_CMP_LR 0x4280 |
| 828 | #define T_OPCODE_MOV_HR 0x4600 |
| 829 | #define T_OPCODE_CMP_HR 0x4500 |
| 830 | |
| 831 | #define T_OPCODE_LDR_PC 0x4800 |
| 832 | #define T_OPCODE_LDR_SP 0x9800 |
| 833 | #define T_OPCODE_STR_SP 0x9000 |
| 834 | #define T_OPCODE_LDR_IW 0x6800 |
| 835 | #define T_OPCODE_STR_IW 0x6000 |
| 836 | #define T_OPCODE_LDR_IH 0x8800 |
| 837 | #define T_OPCODE_STR_IH 0x8000 |
| 838 | #define T_OPCODE_LDR_IB 0x7800 |
| 839 | #define T_OPCODE_STR_IB 0x7000 |
| 840 | #define T_OPCODE_LDR_RW 0x5800 |
| 841 | #define T_OPCODE_STR_RW 0x5000 |
| 842 | #define T_OPCODE_LDR_RH 0x5a00 |
| 843 | #define T_OPCODE_STR_RH 0x5200 |
| 844 | #define T_OPCODE_LDR_RB 0x5c00 |
| 845 | #define T_OPCODE_STR_RB 0x5400 |
| 846 | |
| 847 | #define T_OPCODE_PUSH 0xb400 |
| 848 | #define T_OPCODE_POP 0xbc00 |
| 849 | |
| 850 | #define T_OPCODE_BRANCH 0xe000 |
| 851 | |
| 852 | #define THUMB_SIZE 2 /* Size of thumb instruction. */ |
| 853 | #define THUMB_PP_PC_LR 0x0100 |
| 854 | #define THUMB_LOAD_BIT 0x0800 |
| 855 | #define THUMB2_LOAD_BIT 0x00100000 |
| 856 | |
| 857 | #define BAD_SYNTAX _("syntax error") |
| 858 | #define BAD_ARGS _("bad arguments to instruction") |
| 859 | #define BAD_SP _("r13 not allowed here") |
| 860 | #define BAD_PC _("r15 not allowed here") |
| 861 | #define BAD_ODD _("Odd register not allowed here") |
| 862 | #define BAD_EVEN _("Even register not allowed here") |
| 863 | #define BAD_COND _("instruction cannot be conditional") |
| 864 | #define BAD_OVERLAP _("registers may not be the same") |
| 865 | #define BAD_HIREG _("lo register required") |
| 866 | #define BAD_THUMB32 _("instruction not supported in Thumb16 mode") |
| 867 | #define BAD_ADDR_MODE _("instruction does not accept this addressing mode") |
| 868 | #define BAD_BRANCH _("branch must be last instruction in IT block") |
| 869 | #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2") |
| 870 | #define BAD_NOT_IT _("instruction not allowed in IT block") |
| 871 | #define BAD_NOT_VPT _("instruction missing MVE vector predication code") |
| 872 | #define BAD_FPU _("selected FPU does not support instruction") |
| 873 | #define BAD_OUT_IT _("thumb conditional instruction should be in IT block") |
| 874 | #define BAD_OUT_VPT \ |
| 875 | _("vector predicated instruction should be in VPT/VPST block") |
| 876 | #define BAD_IT_COND _("incorrect condition in IT block") |
| 877 | #define BAD_VPT_COND _("incorrect condition in VPT/VPST block") |
| 878 | #define BAD_IT_IT _("IT falling in the range of a previous IT block") |
| 879 | #define MISSING_FNSTART _("missing .fnstart before unwinding directive") |
| 880 | #define BAD_PC_ADDRESSING \ |
| 881 | _("cannot use register index with PC-relative addressing") |
| 882 | #define BAD_PC_WRITEBACK \ |
| 883 | _("cannot use writeback with PC-relative addressing") |
| 884 | #define BAD_RANGE _("branch out of range") |
| 885 | #define BAD_FP16 _("selected processor does not support fp16 instruction") |
| 886 | #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour") |
| 887 | #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only") |
| 888 | #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \ |
| 889 | "block") |
| 890 | #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \ |
| 891 | "block") |
| 892 | #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \ |
| 893 | " operand") |
| 894 | #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \ |
| 895 | " operand") |
| 896 | #define BAD_SIMD_TYPE _("bad type in SIMD instruction") |
| 897 | #define BAD_MVE_AUTO \ |
| 898 | _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \ |
| 899 | " use a valid -march or -mcpu option.") |
| 900 | #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\ |
| 901 | "and source operands makes instruction UNPREDICTABLE") |
| 902 | #define BAD_EL_TYPE _("bad element type for instruction") |
| 903 | #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected") |
| 904 | |
| 905 | static struct hash_control * arm_ops_hsh; |
| 906 | static struct hash_control * arm_cond_hsh; |
| 907 | static struct hash_control * arm_vcond_hsh; |
| 908 | static struct hash_control * arm_shift_hsh; |
| 909 | static struct hash_control * arm_psr_hsh; |
| 910 | static struct hash_control * arm_v7m_psr_hsh; |
| 911 | static struct hash_control * arm_reg_hsh; |
| 912 | static struct hash_control * arm_reloc_hsh; |
| 913 | static struct hash_control * arm_barrier_opt_hsh; |
| 914 | |
| 915 | /* Stuff needed to resolve the label ambiguity |
| 916 | As: |
| 917 | ... |
| 918 | label: <insn> |
| 919 | may differ from: |
| 920 | ... |
| 921 | label: |
| 922 | <insn> */ |
| 923 | |
| 924 | symbolS * last_label_seen; |
| 925 | static int label_is_thumb_function_name = FALSE; |
| 926 | |
| 927 | /* Literal pool structure. Held on a per-section |
| 928 | and per-sub-section basis. */ |
| 929 | |
| 930 | #define MAX_LITERAL_POOL_SIZE 1024 |
| 931 | typedef struct literal_pool |
| 932 | { |
| 933 | expressionS literals [MAX_LITERAL_POOL_SIZE]; |
| 934 | unsigned int next_free_entry; |
| 935 | unsigned int id; |
| 936 | symbolS * symbol; |
| 937 | segT section; |
| 938 | subsegT sub_section; |
| 939 | #ifdef OBJ_ELF |
| 940 | struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE]; |
| 941 | #endif |
| 942 | struct literal_pool * next; |
| 943 | unsigned int alignment; |
| 944 | } literal_pool; |
| 945 | |
| 946 | /* Pointer to a linked list of literal pools. */ |
| 947 | literal_pool * list_of_pools = NULL; |
| 948 | |
| 949 | typedef enum asmfunc_states |
| 950 | { |
| 951 | OUTSIDE_ASMFUNC, |
| 952 | WAITING_ASMFUNC_NAME, |
| 953 | WAITING_ENDASMFUNC |
| 954 | } asmfunc_states; |
| 955 | |
| 956 | static asmfunc_states asmfunc_state = OUTSIDE_ASMFUNC; |
| 957 | |
| 958 | #ifdef OBJ_ELF |
| 959 | # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred |
| 960 | #else |
| 961 | static struct current_pred now_pred; |
| 962 | #endif |
| 963 | |
| 964 | static inline int |
| 965 | now_pred_compatible (int cond) |
| 966 | { |
| 967 | return (cond & ~1) == (now_pred.cc & ~1); |
| 968 | } |
| 969 | |
| 970 | static inline int |
| 971 | conditional_insn (void) |
| 972 | { |
| 973 | return inst.cond != COND_ALWAYS; |
| 974 | } |
| 975 | |
| 976 | static int in_pred_block (void); |
| 977 | |
| 978 | static int handle_pred_state (void); |
| 979 | |
| 980 | static void force_automatic_it_block_close (void); |
| 981 | |
| 982 | static void it_fsm_post_encode (void); |
| 983 | |
| 984 | #define set_pred_insn_type(type) \ |
| 985 | do \ |
| 986 | { \ |
| 987 | inst.pred_insn_type = type; \ |
| 988 | if (handle_pred_state () == FAIL) \ |
| 989 | return; \ |
| 990 | } \ |
| 991 | while (0) |
| 992 | |
| 993 | #define set_pred_insn_type_nonvoid(type, failret) \ |
| 994 | do \ |
| 995 | { \ |
| 996 | inst.pred_insn_type = type; \ |
| 997 | if (handle_pred_state () == FAIL) \ |
| 998 | return failret; \ |
| 999 | } \ |
| 1000 | while(0) |
| 1001 | |
| 1002 | #define set_pred_insn_type_last() \ |
| 1003 | do \ |
| 1004 | { \ |
| 1005 | if (inst.cond == COND_ALWAYS) \ |
| 1006 | set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \ |
| 1007 | else \ |
| 1008 | set_pred_insn_type (INSIDE_IT_LAST_INSN); \ |
| 1009 | } \ |
| 1010 | while (0) |
| 1011 | |
| 1012 | /* Pure syntax. */ |
| 1013 | |
| 1014 | /* This array holds the chars that always start a comment. If the |
| 1015 | pre-processor is disabled, these aren't very useful. */ |
| 1016 | char arm_comment_chars[] = "@"; |
| 1017 | |
| 1018 | /* This array holds the chars that only start a comment at the beginning of |
| 1019 | a line. If the line seems to have the form '# 123 filename' |
| 1020 | .line and .file directives will appear in the pre-processed output. */ |
| 1021 | /* Note that input_file.c hand checks for '#' at the beginning of the |
| 1022 | first line of the input file. This is because the compiler outputs |
| 1023 | #NO_APP at the beginning of its output. */ |
| 1024 | /* Also note that comments like this one will always work. */ |
| 1025 | const char line_comment_chars[] = "#"; |
| 1026 | |
| 1027 | char arm_line_separator_chars[] = ";"; |
| 1028 | |
| 1029 | /* Chars that can be used to separate mant |
| 1030 | from exp in floating point numbers. */ |
| 1031 | const char EXP_CHARS[] = "eE"; |
| 1032 | |
| 1033 | /* Chars that mean this number is a floating point constant. */ |
| 1034 | /* As in 0f12.456 */ |
| 1035 | /* or 0d1.2345e12 */ |
| 1036 | |
| 1037 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
| 1038 | |
| 1039 | /* Prefix characters that indicate the start of an immediate |
| 1040 | value. */ |
| 1041 | #define is_immediate_prefix(C) ((C) == '#' || (C) == '$') |
| 1042 | |
| 1043 | /* Separator character handling. */ |
| 1044 | |
| 1045 | #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) |
| 1046 | |
| 1047 | static inline int |
| 1048 | skip_past_char (char ** str, char c) |
| 1049 | { |
| 1050 | /* PR gas/14987: Allow for whitespace before the expected character. */ |
| 1051 | skip_whitespace (*str); |
| 1052 | |
| 1053 | if (**str == c) |
| 1054 | { |
| 1055 | (*str)++; |
| 1056 | return SUCCESS; |
| 1057 | } |
| 1058 | else |
| 1059 | return FAIL; |
| 1060 | } |
| 1061 | |
| 1062 | #define skip_past_comma(str) skip_past_char (str, ',') |
| 1063 | |
| 1064 | /* Arithmetic expressions (possibly involving symbols). */ |
| 1065 | |
| 1066 | /* Return TRUE if anything in the expression is a bignum. */ |
| 1067 | |
| 1068 | static bfd_boolean |
| 1069 | walk_no_bignums (symbolS * sp) |
| 1070 | { |
| 1071 | if (symbol_get_value_expression (sp)->X_op == O_big) |
| 1072 | return TRUE; |
| 1073 | |
| 1074 | if (symbol_get_value_expression (sp)->X_add_symbol) |
| 1075 | { |
| 1076 | return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) |
| 1077 | || (symbol_get_value_expression (sp)->X_op_symbol |
| 1078 | && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); |
| 1079 | } |
| 1080 | |
| 1081 | return FALSE; |
| 1082 | } |
| 1083 | |
| 1084 | static bfd_boolean in_my_get_expression = FALSE; |
| 1085 | |
| 1086 | /* Third argument to my_get_expression. */ |
| 1087 | #define GE_NO_PREFIX 0 |
| 1088 | #define GE_IMM_PREFIX 1 |
| 1089 | #define GE_OPT_PREFIX 2 |
| 1090 | /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) |
| 1091 | immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ |
| 1092 | #define GE_OPT_PREFIX_BIG 3 |
| 1093 | |
| 1094 | static int |
| 1095 | my_get_expression (expressionS * ep, char ** str, int prefix_mode) |
| 1096 | { |
| 1097 | char * save_in; |
| 1098 | |
| 1099 | /* In unified syntax, all prefixes are optional. */ |
| 1100 | if (unified_syntax) |
| 1101 | prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode |
| 1102 | : GE_OPT_PREFIX; |
| 1103 | |
| 1104 | switch (prefix_mode) |
| 1105 | { |
| 1106 | case GE_NO_PREFIX: break; |
| 1107 | case GE_IMM_PREFIX: |
| 1108 | if (!is_immediate_prefix (**str)) |
| 1109 | { |
| 1110 | inst.error = _("immediate expression requires a # prefix"); |
| 1111 | return FAIL; |
| 1112 | } |
| 1113 | (*str)++; |
| 1114 | break; |
| 1115 | case GE_OPT_PREFIX: |
| 1116 | case GE_OPT_PREFIX_BIG: |
| 1117 | if (is_immediate_prefix (**str)) |
| 1118 | (*str)++; |
| 1119 | break; |
| 1120 | default: |
| 1121 | abort (); |
| 1122 | } |
| 1123 | |
| 1124 | memset (ep, 0, sizeof (expressionS)); |
| 1125 | |
| 1126 | save_in = input_line_pointer; |
| 1127 | input_line_pointer = *str; |
| 1128 | in_my_get_expression = TRUE; |
| 1129 | expression (ep); |
| 1130 | in_my_get_expression = FALSE; |
| 1131 | |
| 1132 | if (ep->X_op == O_illegal || ep->X_op == O_absent) |
| 1133 | { |
| 1134 | /* We found a bad or missing expression in md_operand(). */ |
| 1135 | *str = input_line_pointer; |
| 1136 | input_line_pointer = save_in; |
| 1137 | if (inst.error == NULL) |
| 1138 | inst.error = (ep->X_op == O_absent |
| 1139 | ? _("missing expression") :_("bad expression")); |
| 1140 | return 1; |
| 1141 | } |
| 1142 | |
| 1143 | /* Get rid of any bignums now, so that we don't generate an error for which |
| 1144 | we can't establish a line number later on. Big numbers are never valid |
| 1145 | in instructions, which is where this routine is always called. */ |
| 1146 | if (prefix_mode != GE_OPT_PREFIX_BIG |
| 1147 | && (ep->X_op == O_big |
| 1148 | || (ep->X_add_symbol |
| 1149 | && (walk_no_bignums (ep->X_add_symbol) |
| 1150 | || (ep->X_op_symbol |
| 1151 | && walk_no_bignums (ep->X_op_symbol)))))) |
| 1152 | { |
| 1153 | inst.error = _("invalid constant"); |
| 1154 | *str = input_line_pointer; |
| 1155 | input_line_pointer = save_in; |
| 1156 | return 1; |
| 1157 | } |
| 1158 | |
| 1159 | *str = input_line_pointer; |
| 1160 | input_line_pointer = save_in; |
| 1161 | return SUCCESS; |
| 1162 | } |
| 1163 | |
| 1164 | /* Turn a string in input_line_pointer into a floating point constant |
| 1165 | of type TYPE, and store the appropriate bytes in *LITP. The number |
| 1166 | of LITTLENUMS emitted is stored in *SIZEP. An error message is |
| 1167 | returned, or NULL on OK. |
| 1168 | |
| 1169 | Note that fp constants aren't represent in the normal way on the ARM. |
| 1170 | In big endian mode, things are as expected. However, in little endian |
| 1171 | mode fp constants are big-endian word-wise, and little-endian byte-wise |
| 1172 | within the words. For example, (double) 1.1 in big endian mode is |
| 1173 | the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is |
| 1174 | the byte sequence 99 99 f1 3f 9a 99 99 99. |
| 1175 | |
| 1176 | ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ |
| 1177 | |
| 1178 | const char * |
| 1179 | md_atof (int type, char * litP, int * sizeP) |
| 1180 | { |
| 1181 | int prec; |
| 1182 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
| 1183 | char *t; |
| 1184 | int i; |
| 1185 | |
| 1186 | switch (type) |
| 1187 | { |
| 1188 | case 'f': |
| 1189 | case 'F': |
| 1190 | case 's': |
| 1191 | case 'S': |
| 1192 | prec = 2; |
| 1193 | break; |
| 1194 | |
| 1195 | case 'd': |
| 1196 | case 'D': |
| 1197 | case 'r': |
| 1198 | case 'R': |
| 1199 | prec = 4; |
| 1200 | break; |
| 1201 | |
| 1202 | case 'x': |
| 1203 | case 'X': |
| 1204 | prec = 5; |
| 1205 | break; |
| 1206 | |
| 1207 | case 'p': |
| 1208 | case 'P': |
| 1209 | prec = 5; |
| 1210 | break; |
| 1211 | |
| 1212 | default: |
| 1213 | *sizeP = 0; |
| 1214 | return _("Unrecognized or unsupported floating point constant"); |
| 1215 | } |
| 1216 | |
| 1217 | t = atof_ieee (input_line_pointer, type, words); |
| 1218 | if (t) |
| 1219 | input_line_pointer = t; |
| 1220 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
| 1221 | |
| 1222 | if (target_big_endian) |
| 1223 | { |
| 1224 | for (i = 0; i < prec; i++) |
| 1225 | { |
| 1226 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
| 1227 | litP += sizeof (LITTLENUM_TYPE); |
| 1228 | } |
| 1229 | } |
| 1230 | else |
| 1231 | { |
| 1232 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) |
| 1233 | for (i = prec - 1; i >= 0; i--) |
| 1234 | { |
| 1235 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
| 1236 | litP += sizeof (LITTLENUM_TYPE); |
| 1237 | } |
| 1238 | else |
| 1239 | /* For a 4 byte float the order of elements in `words' is 1 0. |
| 1240 | For an 8 byte float the order is 1 0 3 2. */ |
| 1241 | for (i = 0; i < prec; i += 2) |
| 1242 | { |
| 1243 | md_number_to_chars (litP, (valueT) words[i + 1], |
| 1244 | sizeof (LITTLENUM_TYPE)); |
| 1245 | md_number_to_chars (litP + sizeof (LITTLENUM_TYPE), |
| 1246 | (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
| 1247 | litP += 2 * sizeof (LITTLENUM_TYPE); |
| 1248 | } |
| 1249 | } |
| 1250 | |
| 1251 | return NULL; |
| 1252 | } |
| 1253 | |
| 1254 | /* We handle all bad expressions here, so that we can report the faulty |
| 1255 | instruction in the error message. */ |
| 1256 | |
| 1257 | void |
| 1258 | md_operand (expressionS * exp) |
| 1259 | { |
| 1260 | if (in_my_get_expression) |
| 1261 | exp->X_op = O_illegal; |
| 1262 | } |
| 1263 | |
| 1264 | /* Immediate values. */ |
| 1265 | |
| 1266 | #ifdef OBJ_ELF |
| 1267 | /* Generic immediate-value read function for use in directives. |
| 1268 | Accepts anything that 'expression' can fold to a constant. |
| 1269 | *val receives the number. */ |
| 1270 | |
| 1271 | static int |
| 1272 | immediate_for_directive (int *val) |
| 1273 | { |
| 1274 | expressionS exp; |
| 1275 | exp.X_op = O_illegal; |
| 1276 | |
| 1277 | if (is_immediate_prefix (*input_line_pointer)) |
| 1278 | { |
| 1279 | input_line_pointer++; |
| 1280 | expression (&exp); |
| 1281 | } |
| 1282 | |
| 1283 | if (exp.X_op != O_constant) |
| 1284 | { |
| 1285 | as_bad (_("expected #constant")); |
| 1286 | ignore_rest_of_line (); |
| 1287 | return FAIL; |
| 1288 | } |
| 1289 | *val = exp.X_add_number; |
| 1290 | return SUCCESS; |
| 1291 | } |
| 1292 | #endif |
| 1293 | |
| 1294 | /* Register parsing. */ |
| 1295 | |
| 1296 | /* Generic register parser. CCP points to what should be the |
| 1297 | beginning of a register name. If it is indeed a valid register |
| 1298 | name, advance CCP over it and return the reg_entry structure; |
| 1299 | otherwise return NULL. Does not issue diagnostics. */ |
| 1300 | |
| 1301 | static struct reg_entry * |
| 1302 | arm_reg_parse_multi (char **ccp) |
| 1303 | { |
| 1304 | char *start = *ccp; |
| 1305 | char *p; |
| 1306 | struct reg_entry *reg; |
| 1307 | |
| 1308 | skip_whitespace (start); |
| 1309 | |
| 1310 | #ifdef REGISTER_PREFIX |
| 1311 | if (*start != REGISTER_PREFIX) |
| 1312 | return NULL; |
| 1313 | start++; |
| 1314 | #endif |
| 1315 | #ifdef OPTIONAL_REGISTER_PREFIX |
| 1316 | if (*start == OPTIONAL_REGISTER_PREFIX) |
| 1317 | start++; |
| 1318 | #endif |
| 1319 | |
| 1320 | p = start; |
| 1321 | if (!ISALPHA (*p) || !is_name_beginner (*p)) |
| 1322 | return NULL; |
| 1323 | |
| 1324 | do |
| 1325 | p++; |
| 1326 | while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); |
| 1327 | |
| 1328 | reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); |
| 1329 | |
| 1330 | if (!reg) |
| 1331 | return NULL; |
| 1332 | |
| 1333 | *ccp = p; |
| 1334 | return reg; |
| 1335 | } |
| 1336 | |
| 1337 | static int |
| 1338 | arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, |
| 1339 | enum arm_reg_type type) |
| 1340 | { |
| 1341 | /* Alternative syntaxes are accepted for a few register classes. */ |
| 1342 | switch (type) |
| 1343 | { |
| 1344 | case REG_TYPE_MVF: |
| 1345 | case REG_TYPE_MVD: |
| 1346 | case REG_TYPE_MVFX: |
| 1347 | case REG_TYPE_MVDX: |
| 1348 | /* Generic coprocessor register names are allowed for these. */ |
| 1349 | if (reg && reg->type == REG_TYPE_CN) |
| 1350 | return reg->number; |
| 1351 | break; |
| 1352 | |
| 1353 | case REG_TYPE_CP: |
| 1354 | /* For backward compatibility, a bare number is valid here. */ |
| 1355 | { |
| 1356 | unsigned long processor = strtoul (start, ccp, 10); |
| 1357 | if (*ccp != start && processor <= 15) |
| 1358 | return processor; |
| 1359 | } |
| 1360 | /* Fall through. */ |
| 1361 | |
| 1362 | case REG_TYPE_MMXWC: |
| 1363 | /* WC includes WCG. ??? I'm not sure this is true for all |
| 1364 | instructions that take WC registers. */ |
| 1365 | if (reg && reg->type == REG_TYPE_MMXWCG) |
| 1366 | return reg->number; |
| 1367 | break; |
| 1368 | |
| 1369 | default: |
| 1370 | break; |
| 1371 | } |
| 1372 | |
| 1373 | return FAIL; |
| 1374 | } |
| 1375 | |
| 1376 | /* As arm_reg_parse_multi, but the register must be of type TYPE, and the |
| 1377 | return value is the register number or FAIL. */ |
| 1378 | |
| 1379 | static int |
| 1380 | arm_reg_parse (char **ccp, enum arm_reg_type type) |
| 1381 | { |
| 1382 | char *start = *ccp; |
| 1383 | struct reg_entry *reg = arm_reg_parse_multi (ccp); |
| 1384 | int ret; |
| 1385 | |
| 1386 | /* Do not allow a scalar (reg+index) to parse as a register. */ |
| 1387 | if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) |
| 1388 | return FAIL; |
| 1389 | |
| 1390 | if (reg && reg->type == type) |
| 1391 | return reg->number; |
| 1392 | |
| 1393 | if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) |
| 1394 | return ret; |
| 1395 | |
| 1396 | *ccp = start; |
| 1397 | return FAIL; |
| 1398 | } |
| 1399 | |
| 1400 | /* Parse a Neon type specifier. *STR should point at the leading '.' |
| 1401 | character. Does no verification at this stage that the type fits the opcode |
| 1402 | properly. E.g., |
| 1403 | |
| 1404 | .i32.i32.s16 |
| 1405 | .s32.f32 |
| 1406 | .u16 |
| 1407 | |
| 1408 | Can all be legally parsed by this function. |
| 1409 | |
| 1410 | Fills in neon_type struct pointer with parsed information, and updates STR |
| 1411 | to point after the parsed type specifier. Returns SUCCESS if this was a legal |
| 1412 | type, FAIL if not. */ |
| 1413 | |
| 1414 | static int |
| 1415 | parse_neon_type (struct neon_type *type, char **str) |
| 1416 | { |
| 1417 | char *ptr = *str; |
| 1418 | |
| 1419 | if (type) |
| 1420 | type->elems = 0; |
| 1421 | |
| 1422 | while (type->elems < NEON_MAX_TYPE_ELS) |
| 1423 | { |
| 1424 | enum neon_el_type thistype = NT_untyped; |
| 1425 | unsigned thissize = -1u; |
| 1426 | |
| 1427 | if (*ptr != '.') |
| 1428 | break; |
| 1429 | |
| 1430 | ptr++; |
| 1431 | |
| 1432 | /* Just a size without an explicit type. */ |
| 1433 | if (ISDIGIT (*ptr)) |
| 1434 | goto parsesize; |
| 1435 | |
| 1436 | switch (TOLOWER (*ptr)) |
| 1437 | { |
| 1438 | case 'i': thistype = NT_integer; break; |
| 1439 | case 'f': thistype = NT_float; break; |
| 1440 | case 'p': thistype = NT_poly; break; |
| 1441 | case 's': thistype = NT_signed; break; |
| 1442 | case 'u': thistype = NT_unsigned; break; |
| 1443 | case 'd': |
| 1444 | thistype = NT_float; |
| 1445 | thissize = 64; |
| 1446 | ptr++; |
| 1447 | goto done; |
| 1448 | default: |
| 1449 | as_bad (_("unexpected character `%c' in type specifier"), *ptr); |
| 1450 | return FAIL; |
| 1451 | } |
| 1452 | |
| 1453 | ptr++; |
| 1454 | |
| 1455 | /* .f is an abbreviation for .f32. */ |
| 1456 | if (thistype == NT_float && !ISDIGIT (*ptr)) |
| 1457 | thissize = 32; |
| 1458 | else |
| 1459 | { |
| 1460 | parsesize: |
| 1461 | thissize = strtoul (ptr, &ptr, 10); |
| 1462 | |
| 1463 | if (thissize != 8 && thissize != 16 && thissize != 32 |
| 1464 | && thissize != 64) |
| 1465 | { |
| 1466 | as_bad (_("bad size %d in type specifier"), thissize); |
| 1467 | return FAIL; |
| 1468 | } |
| 1469 | } |
| 1470 | |
| 1471 | done: |
| 1472 | if (type) |
| 1473 | { |
| 1474 | type->el[type->elems].type = thistype; |
| 1475 | type->el[type->elems].size = thissize; |
| 1476 | type->elems++; |
| 1477 | } |
| 1478 | } |
| 1479 | |
| 1480 | /* Empty/missing type is not a successful parse. */ |
| 1481 | if (type->elems == 0) |
| 1482 | return FAIL; |
| 1483 | |
| 1484 | *str = ptr; |
| 1485 | |
| 1486 | return SUCCESS; |
| 1487 | } |
| 1488 | |
| 1489 | /* Errors may be set multiple times during parsing or bit encoding |
| 1490 | (particularly in the Neon bits), but usually the earliest error which is set |
| 1491 | will be the most meaningful. Avoid overwriting it with later (cascading) |
| 1492 | errors by calling this function. */ |
| 1493 | |
| 1494 | static void |
| 1495 | first_error (const char *err) |
| 1496 | { |
| 1497 | if (!inst.error) |
| 1498 | inst.error = err; |
| 1499 | } |
| 1500 | |
| 1501 | /* Parse a single type, e.g. ".s32", leading period included. */ |
| 1502 | static int |
| 1503 | parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) |
| 1504 | { |
| 1505 | char *str = *ccp; |
| 1506 | struct neon_type optype; |
| 1507 | |
| 1508 | if (*str == '.') |
| 1509 | { |
| 1510 | if (parse_neon_type (&optype, &str) == SUCCESS) |
| 1511 | { |
| 1512 | if (optype.elems == 1) |
| 1513 | *vectype = optype.el[0]; |
| 1514 | else |
| 1515 | { |
| 1516 | first_error (_("only one type should be specified for operand")); |
| 1517 | return FAIL; |
| 1518 | } |
| 1519 | } |
| 1520 | else |
| 1521 | { |
| 1522 | first_error (_("vector type expected")); |
| 1523 | return FAIL; |
| 1524 | } |
| 1525 | } |
| 1526 | else |
| 1527 | return FAIL; |
| 1528 | |
| 1529 | *ccp = str; |
| 1530 | |
| 1531 | return SUCCESS; |
| 1532 | } |
| 1533 | |
| 1534 | /* Special meanings for indices (which have a range of 0-7), which will fit into |
| 1535 | a 4-bit integer. */ |
| 1536 | |
| 1537 | #define NEON_ALL_LANES 15 |
| 1538 | #define NEON_INTERLEAVE_LANES 14 |
| 1539 | |
| 1540 | /* Record a use of the given feature. */ |
| 1541 | static void |
| 1542 | record_feature_use (const arm_feature_set *feature) |
| 1543 | { |
| 1544 | if (thumb_mode) |
| 1545 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature); |
| 1546 | else |
| 1547 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature); |
| 1548 | } |
| 1549 | |
| 1550 | /* If the given feature available in the selected CPU, mark it as used. |
| 1551 | Returns TRUE iff feature is available. */ |
| 1552 | static bfd_boolean |
| 1553 | mark_feature_used (const arm_feature_set *feature) |
| 1554 | { |
| 1555 | |
| 1556 | /* Do not support the use of MVE only instructions when in auto-detection or |
| 1557 | -march=all. */ |
| 1558 | if (((feature == &mve_ext) || (feature == &mve_fp_ext)) |
| 1559 | && ARM_CPU_IS_ANY (cpu_variant)) |
| 1560 | { |
| 1561 | first_error (BAD_MVE_AUTO); |
| 1562 | return FALSE; |
| 1563 | } |
| 1564 | /* Ensure the option is valid on the current architecture. */ |
| 1565 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature)) |
| 1566 | return FALSE; |
| 1567 | |
| 1568 | /* Add the appropriate architecture feature for the barrier option used. |
| 1569 | */ |
| 1570 | record_feature_use (feature); |
| 1571 | |
| 1572 | return TRUE; |
| 1573 | } |
| 1574 | |
| 1575 | /* Parse either a register or a scalar, with an optional type. Return the |
| 1576 | register number, and optionally fill in the actual type of the register |
| 1577 | when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and |
| 1578 | type/index information in *TYPEINFO. */ |
| 1579 | |
| 1580 | static int |
| 1581 | parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, |
| 1582 | enum arm_reg_type *rtype, |
| 1583 | struct neon_typed_alias *typeinfo) |
| 1584 | { |
| 1585 | char *str = *ccp; |
| 1586 | struct reg_entry *reg = arm_reg_parse_multi (&str); |
| 1587 | struct neon_typed_alias atype; |
| 1588 | struct neon_type_el parsetype; |
| 1589 | |
| 1590 | atype.defined = 0; |
| 1591 | atype.index = -1; |
| 1592 | atype.eltype.type = NT_invtype; |
| 1593 | atype.eltype.size = -1; |
| 1594 | |
| 1595 | /* Try alternate syntax for some types of register. Note these are mutually |
| 1596 | exclusive with the Neon syntax extensions. */ |
| 1597 | if (reg == NULL) |
| 1598 | { |
| 1599 | int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); |
| 1600 | if (altreg != FAIL) |
| 1601 | *ccp = str; |
| 1602 | if (typeinfo) |
| 1603 | *typeinfo = atype; |
| 1604 | return altreg; |
| 1605 | } |
| 1606 | |
| 1607 | /* Undo polymorphism when a set of register types may be accepted. */ |
| 1608 | if ((type == REG_TYPE_NDQ |
| 1609 | && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) |
| 1610 | || (type == REG_TYPE_VFSD |
| 1611 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) |
| 1612 | || (type == REG_TYPE_NSDQ |
| 1613 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD |
| 1614 | || reg->type == REG_TYPE_NQ)) |
| 1615 | || (type == REG_TYPE_NSD |
| 1616 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) |
| 1617 | || (type == REG_TYPE_MMXWC |
| 1618 | && (reg->type == REG_TYPE_MMXWCG))) |
| 1619 | type = (enum arm_reg_type) reg->type; |
| 1620 | |
| 1621 | if (type == REG_TYPE_MQ) |
| 1622 | { |
| 1623 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 1624 | return FAIL; |
| 1625 | |
| 1626 | if (!reg || reg->type != REG_TYPE_NQ) |
| 1627 | return FAIL; |
| 1628 | |
| 1629 | if (reg->number > 14 && !mark_feature_used (&fpu_vfp_ext_d32)) |
| 1630 | { |
| 1631 | first_error (_("expected MVE register [q0..q7]")); |
| 1632 | return FAIL; |
| 1633 | } |
| 1634 | type = REG_TYPE_NQ; |
| 1635 | } |
| 1636 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) |
| 1637 | && (type == REG_TYPE_NQ)) |
| 1638 | return FAIL; |
| 1639 | |
| 1640 | |
| 1641 | if (type != reg->type) |
| 1642 | return FAIL; |
| 1643 | |
| 1644 | if (reg->neon) |
| 1645 | atype = *reg->neon; |
| 1646 | |
| 1647 | if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) |
| 1648 | { |
| 1649 | if ((atype.defined & NTA_HASTYPE) != 0) |
| 1650 | { |
| 1651 | first_error (_("can't redefine type for operand")); |
| 1652 | return FAIL; |
| 1653 | } |
| 1654 | atype.defined |= NTA_HASTYPE; |
| 1655 | atype.eltype = parsetype; |
| 1656 | } |
| 1657 | |
| 1658 | if (skip_past_char (&str, '[') == SUCCESS) |
| 1659 | { |
| 1660 | if (type != REG_TYPE_VFD |
| 1661 | && !(type == REG_TYPE_VFS |
| 1662 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_2)) |
| 1663 | && !(type == REG_TYPE_NQ |
| 1664 | && ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))) |
| 1665 | { |
| 1666 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 1667 | first_error (_("only D and Q registers may be indexed")); |
| 1668 | else |
| 1669 | first_error (_("only D registers may be indexed")); |
| 1670 | return FAIL; |
| 1671 | } |
| 1672 | |
| 1673 | if ((atype.defined & NTA_HASINDEX) != 0) |
| 1674 | { |
| 1675 | first_error (_("can't change index for operand")); |
| 1676 | return FAIL; |
| 1677 | } |
| 1678 | |
| 1679 | atype.defined |= NTA_HASINDEX; |
| 1680 | |
| 1681 | if (skip_past_char (&str, ']') == SUCCESS) |
| 1682 | atype.index = NEON_ALL_LANES; |
| 1683 | else |
| 1684 | { |
| 1685 | expressionS exp; |
| 1686 | |
| 1687 | my_get_expression (&exp, &str, GE_NO_PREFIX); |
| 1688 | |
| 1689 | if (exp.X_op != O_constant) |
| 1690 | { |
| 1691 | first_error (_("constant expression required")); |
| 1692 | return FAIL; |
| 1693 | } |
| 1694 | |
| 1695 | if (skip_past_char (&str, ']') == FAIL) |
| 1696 | return FAIL; |
| 1697 | |
| 1698 | atype.index = exp.X_add_number; |
| 1699 | } |
| 1700 | } |
| 1701 | |
| 1702 | if (typeinfo) |
| 1703 | *typeinfo = atype; |
| 1704 | |
| 1705 | if (rtype) |
| 1706 | *rtype = type; |
| 1707 | |
| 1708 | *ccp = str; |
| 1709 | |
| 1710 | return reg->number; |
| 1711 | } |
| 1712 | |
| 1713 | /* Like arm_reg_parse, but also allow the following extra features: |
| 1714 | - If RTYPE is non-zero, return the (possibly restricted) type of the |
| 1715 | register (e.g. Neon double or quad reg when either has been requested). |
| 1716 | - If this is a Neon vector type with additional type information, fill |
| 1717 | in the struct pointed to by VECTYPE (if non-NULL). |
| 1718 | This function will fault on encountering a scalar. */ |
| 1719 | |
| 1720 | static int |
| 1721 | arm_typed_reg_parse (char **ccp, enum arm_reg_type type, |
| 1722 | enum arm_reg_type *rtype, struct neon_type_el *vectype) |
| 1723 | { |
| 1724 | struct neon_typed_alias atype; |
| 1725 | char *str = *ccp; |
| 1726 | int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); |
| 1727 | |
| 1728 | if (reg == FAIL) |
| 1729 | return FAIL; |
| 1730 | |
| 1731 | /* Do not allow regname(... to parse as a register. */ |
| 1732 | if (*str == '(') |
| 1733 | return FAIL; |
| 1734 | |
| 1735 | /* Do not allow a scalar (reg+index) to parse as a register. */ |
| 1736 | if ((atype.defined & NTA_HASINDEX) != 0) |
| 1737 | { |
| 1738 | first_error (_("register operand expected, but got scalar")); |
| 1739 | return FAIL; |
| 1740 | } |
| 1741 | |
| 1742 | if (vectype) |
| 1743 | *vectype = atype.eltype; |
| 1744 | |
| 1745 | *ccp = str; |
| 1746 | |
| 1747 | return reg; |
| 1748 | } |
| 1749 | |
| 1750 | #define NEON_SCALAR_REG(X) ((X) >> 4) |
| 1751 | #define NEON_SCALAR_INDEX(X) ((X) & 15) |
| 1752 | |
| 1753 | /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't |
| 1754 | have enough information to be able to do a good job bounds-checking. So, we |
| 1755 | just do easy checks here, and do further checks later. */ |
| 1756 | |
| 1757 | static int |
| 1758 | parse_scalar (char **ccp, int elsize, struct neon_type_el *type, enum |
| 1759 | arm_reg_type reg_type) |
| 1760 | { |
| 1761 | int reg; |
| 1762 | char *str = *ccp; |
| 1763 | struct neon_typed_alias atype; |
| 1764 | unsigned reg_size; |
| 1765 | |
| 1766 | reg = parse_typed_reg_or_scalar (&str, reg_type, NULL, &atype); |
| 1767 | |
| 1768 | switch (reg_type) |
| 1769 | { |
| 1770 | case REG_TYPE_VFS: |
| 1771 | reg_size = 32; |
| 1772 | break; |
| 1773 | case REG_TYPE_VFD: |
| 1774 | reg_size = 64; |
| 1775 | break; |
| 1776 | case REG_TYPE_MQ: |
| 1777 | reg_size = 128; |
| 1778 | break; |
| 1779 | default: |
| 1780 | gas_assert (0); |
| 1781 | return FAIL; |
| 1782 | } |
| 1783 | |
| 1784 | if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) |
| 1785 | return FAIL; |
| 1786 | |
| 1787 | if (reg_type != REG_TYPE_MQ && atype.index == NEON_ALL_LANES) |
| 1788 | { |
| 1789 | first_error (_("scalar must have an index")); |
| 1790 | return FAIL; |
| 1791 | } |
| 1792 | else if (atype.index >= reg_size / elsize) |
| 1793 | { |
| 1794 | first_error (_("scalar index out of range")); |
| 1795 | return FAIL; |
| 1796 | } |
| 1797 | |
| 1798 | if (type) |
| 1799 | *type = atype.eltype; |
| 1800 | |
| 1801 | *ccp = str; |
| 1802 | |
| 1803 | return reg * 16 + atype.index; |
| 1804 | } |
| 1805 | |
| 1806 | /* Types of registers in a list. */ |
| 1807 | |
| 1808 | enum reg_list_els |
| 1809 | { |
| 1810 | REGLIST_RN, |
| 1811 | REGLIST_CLRM, |
| 1812 | REGLIST_VFP_S, |
| 1813 | REGLIST_VFP_S_VPR, |
| 1814 | REGLIST_VFP_D, |
| 1815 | REGLIST_VFP_D_VPR, |
| 1816 | REGLIST_NEON_D |
| 1817 | }; |
| 1818 | |
| 1819 | /* Parse an ARM register list. Returns the bitmask, or FAIL. */ |
| 1820 | |
| 1821 | static long |
| 1822 | parse_reg_list (char ** strp, enum reg_list_els etype) |
| 1823 | { |
| 1824 | char *str = *strp; |
| 1825 | long range = 0; |
| 1826 | int another_range; |
| 1827 | |
| 1828 | gas_assert (etype == REGLIST_RN || etype == REGLIST_CLRM); |
| 1829 | |
| 1830 | /* We come back here if we get ranges concatenated by '+' or '|'. */ |
| 1831 | do |
| 1832 | { |
| 1833 | skip_whitespace (str); |
| 1834 | |
| 1835 | another_range = 0; |
| 1836 | |
| 1837 | if (*str == '{') |
| 1838 | { |
| 1839 | int in_range = 0; |
| 1840 | int cur_reg = -1; |
| 1841 | |
| 1842 | str++; |
| 1843 | do |
| 1844 | { |
| 1845 | int reg; |
| 1846 | const char apsr_str[] = "apsr"; |
| 1847 | int apsr_str_len = strlen (apsr_str); |
| 1848 | |
| 1849 | reg = arm_reg_parse (&str, REGLIST_RN); |
| 1850 | if (etype == REGLIST_CLRM) |
| 1851 | { |
| 1852 | if (reg == REG_SP || reg == REG_PC) |
| 1853 | reg = FAIL; |
| 1854 | else if (reg == FAIL |
| 1855 | && !strncasecmp (str, apsr_str, apsr_str_len) |
| 1856 | && !ISALPHA (*(str + apsr_str_len))) |
| 1857 | { |
| 1858 | reg = 15; |
| 1859 | str += apsr_str_len; |
| 1860 | } |
| 1861 | |
| 1862 | if (reg == FAIL) |
| 1863 | { |
| 1864 | first_error (_("r0-r12, lr or APSR expected")); |
| 1865 | return FAIL; |
| 1866 | } |
| 1867 | } |
| 1868 | else /* etype == REGLIST_RN. */ |
| 1869 | { |
| 1870 | if (reg == FAIL) |
| 1871 | { |
| 1872 | first_error (_(reg_expected_msgs[REGLIST_RN])); |
| 1873 | return FAIL; |
| 1874 | } |
| 1875 | } |
| 1876 | |
| 1877 | if (in_range) |
| 1878 | { |
| 1879 | int i; |
| 1880 | |
| 1881 | if (reg <= cur_reg) |
| 1882 | { |
| 1883 | first_error (_("bad range in register list")); |
| 1884 | return FAIL; |
| 1885 | } |
| 1886 | |
| 1887 | for (i = cur_reg + 1; i < reg; i++) |
| 1888 | { |
| 1889 | if (range & (1 << i)) |
| 1890 | as_tsktsk |
| 1891 | (_("Warning: duplicated register (r%d) in register list"), |
| 1892 | i); |
| 1893 | else |
| 1894 | range |= 1 << i; |
| 1895 | } |
| 1896 | in_range = 0; |
| 1897 | } |
| 1898 | |
| 1899 | if (range & (1 << reg)) |
| 1900 | as_tsktsk (_("Warning: duplicated register (r%d) in register list"), |
| 1901 | reg); |
| 1902 | else if (reg <= cur_reg) |
| 1903 | as_tsktsk (_("Warning: register range not in ascending order")); |
| 1904 | |
| 1905 | range |= 1 << reg; |
| 1906 | cur_reg = reg; |
| 1907 | } |
| 1908 | while (skip_past_comma (&str) != FAIL |
| 1909 | || (in_range = 1, *str++ == '-')); |
| 1910 | str--; |
| 1911 | |
| 1912 | if (skip_past_char (&str, '}') == FAIL) |
| 1913 | { |
| 1914 | first_error (_("missing `}'")); |
| 1915 | return FAIL; |
| 1916 | } |
| 1917 | } |
| 1918 | else if (etype == REGLIST_RN) |
| 1919 | { |
| 1920 | expressionS exp; |
| 1921 | |
| 1922 | if (my_get_expression (&exp, &str, GE_NO_PREFIX)) |
| 1923 | return FAIL; |
| 1924 | |
| 1925 | if (exp.X_op == O_constant) |
| 1926 | { |
| 1927 | if (exp.X_add_number |
| 1928 | != (exp.X_add_number & 0x0000ffff)) |
| 1929 | { |
| 1930 | inst.error = _("invalid register mask"); |
| 1931 | return FAIL; |
| 1932 | } |
| 1933 | |
| 1934 | if ((range & exp.X_add_number) != 0) |
| 1935 | { |
| 1936 | int regno = range & exp.X_add_number; |
| 1937 | |
| 1938 | regno &= -regno; |
| 1939 | regno = (1 << regno) - 1; |
| 1940 | as_tsktsk |
| 1941 | (_("Warning: duplicated register (r%d) in register list"), |
| 1942 | regno); |
| 1943 | } |
| 1944 | |
| 1945 | range |= exp.X_add_number; |
| 1946 | } |
| 1947 | else |
| 1948 | { |
| 1949 | if (inst.relocs[0].type != 0) |
| 1950 | { |
| 1951 | inst.error = _("expression too complex"); |
| 1952 | return FAIL; |
| 1953 | } |
| 1954 | |
| 1955 | memcpy (&inst.relocs[0].exp, &exp, sizeof (expressionS)); |
| 1956 | inst.relocs[0].type = BFD_RELOC_ARM_MULTI; |
| 1957 | inst.relocs[0].pc_rel = 0; |
| 1958 | } |
| 1959 | } |
| 1960 | |
| 1961 | if (*str == '|' || *str == '+') |
| 1962 | { |
| 1963 | str++; |
| 1964 | another_range = 1; |
| 1965 | } |
| 1966 | } |
| 1967 | while (another_range); |
| 1968 | |
| 1969 | *strp = str; |
| 1970 | return range; |
| 1971 | } |
| 1972 | |
| 1973 | /* Parse a VFP register list. If the string is invalid return FAIL. |
| 1974 | Otherwise return the number of registers, and set PBASE to the first |
| 1975 | register. Parses registers of type ETYPE. |
| 1976 | If REGLIST_NEON_D is used, several syntax enhancements are enabled: |
| 1977 | - Q registers can be used to specify pairs of D registers |
| 1978 | - { } can be omitted from around a singleton register list |
| 1979 | FIXME: This is not implemented, as it would require backtracking in |
| 1980 | some cases, e.g.: |
| 1981 | vtbl.8 d3,d4,d5 |
| 1982 | This could be done (the meaning isn't really ambiguous), but doesn't |
| 1983 | fit in well with the current parsing framework. |
| 1984 | - 32 D registers may be used (also true for VFPv3). |
| 1985 | FIXME: Types are ignored in these register lists, which is probably a |
| 1986 | bug. */ |
| 1987 | |
| 1988 | static int |
| 1989 | parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype, |
| 1990 | bfd_boolean *partial_match) |
| 1991 | { |
| 1992 | char *str = *ccp; |
| 1993 | int base_reg; |
| 1994 | int new_base; |
| 1995 | enum arm_reg_type regtype = (enum arm_reg_type) 0; |
| 1996 | int max_regs = 0; |
| 1997 | int count = 0; |
| 1998 | int warned = 0; |
| 1999 | unsigned long mask = 0; |
| 2000 | int i; |
| 2001 | bfd_boolean vpr_seen = FALSE; |
| 2002 | bfd_boolean expect_vpr = |
| 2003 | (etype == REGLIST_VFP_S_VPR) || (etype == REGLIST_VFP_D_VPR); |
| 2004 | |
| 2005 | if (skip_past_char (&str, '{') == FAIL) |
| 2006 | { |
| 2007 | inst.error = _("expecting {"); |
| 2008 | return FAIL; |
| 2009 | } |
| 2010 | |
| 2011 | switch (etype) |
| 2012 | { |
| 2013 | case REGLIST_VFP_S: |
| 2014 | case REGLIST_VFP_S_VPR: |
| 2015 | regtype = REG_TYPE_VFS; |
| 2016 | max_regs = 32; |
| 2017 | break; |
| 2018 | |
| 2019 | case REGLIST_VFP_D: |
| 2020 | case REGLIST_VFP_D_VPR: |
| 2021 | regtype = REG_TYPE_VFD; |
| 2022 | break; |
| 2023 | |
| 2024 | case REGLIST_NEON_D: |
| 2025 | regtype = REG_TYPE_NDQ; |
| 2026 | break; |
| 2027 | |
| 2028 | default: |
| 2029 | gas_assert (0); |
| 2030 | } |
| 2031 | |
| 2032 | if (etype != REGLIST_VFP_S && etype != REGLIST_VFP_S_VPR) |
| 2033 | { |
| 2034 | /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */ |
| 2035 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) |
| 2036 | { |
| 2037 | max_regs = 32; |
| 2038 | if (thumb_mode) |
| 2039 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
| 2040 | fpu_vfp_ext_d32); |
| 2041 | else |
| 2042 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, |
| 2043 | fpu_vfp_ext_d32); |
| 2044 | } |
| 2045 | else |
| 2046 | max_regs = 16; |
| 2047 | } |
| 2048 | |
| 2049 | base_reg = max_regs; |
| 2050 | *partial_match = FALSE; |
| 2051 | |
| 2052 | do |
| 2053 | { |
| 2054 | int setmask = 1, addregs = 1; |
| 2055 | const char vpr_str[] = "vpr"; |
| 2056 | int vpr_str_len = strlen (vpr_str); |
| 2057 | |
| 2058 | new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); |
| 2059 | |
| 2060 | if (expect_vpr) |
| 2061 | { |
| 2062 | if (new_base == FAIL |
| 2063 | && !strncasecmp (str, vpr_str, vpr_str_len) |
| 2064 | && !ISALPHA (*(str + vpr_str_len)) |
| 2065 | && !vpr_seen) |
| 2066 | { |
| 2067 | vpr_seen = TRUE; |
| 2068 | str += vpr_str_len; |
| 2069 | if (count == 0) |
| 2070 | base_reg = 0; /* Canonicalize VPR only on d0 with 0 regs. */ |
| 2071 | } |
| 2072 | else if (vpr_seen) |
| 2073 | { |
| 2074 | first_error (_("VPR expected last")); |
| 2075 | return FAIL; |
| 2076 | } |
| 2077 | else if (new_base == FAIL) |
| 2078 | { |
| 2079 | if (regtype == REG_TYPE_VFS) |
| 2080 | first_error (_("VFP single precision register or VPR " |
| 2081 | "expected")); |
| 2082 | else /* regtype == REG_TYPE_VFD. */ |
| 2083 | first_error (_("VFP/Neon double precision register or VPR " |
| 2084 | "expected")); |
| 2085 | return FAIL; |
| 2086 | } |
| 2087 | } |
| 2088 | else if (new_base == FAIL) |
| 2089 | { |
| 2090 | first_error (_(reg_expected_msgs[regtype])); |
| 2091 | return FAIL; |
| 2092 | } |
| 2093 | |
| 2094 | *partial_match = TRUE; |
| 2095 | if (vpr_seen) |
| 2096 | continue; |
| 2097 | |
| 2098 | if (new_base >= max_regs) |
| 2099 | { |
| 2100 | first_error (_("register out of range in list")); |
| 2101 | return FAIL; |
| 2102 | } |
| 2103 | |
| 2104 | /* Note: a value of 2 * n is returned for the register Q<n>. */ |
| 2105 | if (regtype == REG_TYPE_NQ) |
| 2106 | { |
| 2107 | setmask = 3; |
| 2108 | addregs = 2; |
| 2109 | } |
| 2110 | |
| 2111 | if (new_base < base_reg) |
| 2112 | base_reg = new_base; |
| 2113 | |
| 2114 | if (mask & (setmask << new_base)) |
| 2115 | { |
| 2116 | first_error (_("invalid register list")); |
| 2117 | return FAIL; |
| 2118 | } |
| 2119 | |
| 2120 | if ((mask >> new_base) != 0 && ! warned && !vpr_seen) |
| 2121 | { |
| 2122 | as_tsktsk (_("register list not in ascending order")); |
| 2123 | warned = 1; |
| 2124 | } |
| 2125 | |
| 2126 | mask |= setmask << new_base; |
| 2127 | count += addregs; |
| 2128 | |
| 2129 | if (*str == '-') /* We have the start of a range expression */ |
| 2130 | { |
| 2131 | int high_range; |
| 2132 | |
| 2133 | str++; |
| 2134 | |
| 2135 | if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) |
| 2136 | == FAIL) |
| 2137 | { |
| 2138 | inst.error = gettext (reg_expected_msgs[regtype]); |
| 2139 | return FAIL; |
| 2140 | } |
| 2141 | |
| 2142 | if (high_range >= max_regs) |
| 2143 | { |
| 2144 | first_error (_("register out of range in list")); |
| 2145 | return FAIL; |
| 2146 | } |
| 2147 | |
| 2148 | if (regtype == REG_TYPE_NQ) |
| 2149 | high_range = high_range + 1; |
| 2150 | |
| 2151 | if (high_range <= new_base) |
| 2152 | { |
| 2153 | inst.error = _("register range not in ascending order"); |
| 2154 | return FAIL; |
| 2155 | } |
| 2156 | |
| 2157 | for (new_base += addregs; new_base <= high_range; new_base += addregs) |
| 2158 | { |
| 2159 | if (mask & (setmask << new_base)) |
| 2160 | { |
| 2161 | inst.error = _("invalid register list"); |
| 2162 | return FAIL; |
| 2163 | } |
| 2164 | |
| 2165 | mask |= setmask << new_base; |
| 2166 | count += addregs; |
| 2167 | } |
| 2168 | } |
| 2169 | } |
| 2170 | while (skip_past_comma (&str) != FAIL); |
| 2171 | |
| 2172 | str++; |
| 2173 | |
| 2174 | /* Sanity check -- should have raised a parse error above. */ |
| 2175 | if ((!vpr_seen && count == 0) || count > max_regs) |
| 2176 | abort (); |
| 2177 | |
| 2178 | *pbase = base_reg; |
| 2179 | |
| 2180 | if (expect_vpr && !vpr_seen) |
| 2181 | { |
| 2182 | first_error (_("VPR expected last")); |
| 2183 | return FAIL; |
| 2184 | } |
| 2185 | |
| 2186 | /* Final test -- the registers must be consecutive. */ |
| 2187 | mask >>= base_reg; |
| 2188 | for (i = 0; i < count; i++) |
| 2189 | { |
| 2190 | if ((mask & (1u << i)) == 0) |
| 2191 | { |
| 2192 | inst.error = _("non-contiguous register range"); |
| 2193 | return FAIL; |
| 2194 | } |
| 2195 | } |
| 2196 | |
| 2197 | *ccp = str; |
| 2198 | |
| 2199 | return count; |
| 2200 | } |
| 2201 | |
| 2202 | /* True if two alias types are the same. */ |
| 2203 | |
| 2204 | static bfd_boolean |
| 2205 | neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) |
| 2206 | { |
| 2207 | if (!a && !b) |
| 2208 | return TRUE; |
| 2209 | |
| 2210 | if (!a || !b) |
| 2211 | return FALSE; |
| 2212 | |
| 2213 | if (a->defined != b->defined) |
| 2214 | return FALSE; |
| 2215 | |
| 2216 | if ((a->defined & NTA_HASTYPE) != 0 |
| 2217 | && (a->eltype.type != b->eltype.type |
| 2218 | || a->eltype.size != b->eltype.size)) |
| 2219 | return FALSE; |
| 2220 | |
| 2221 | if ((a->defined & NTA_HASINDEX) != 0 |
| 2222 | && (a->index != b->index)) |
| 2223 | return FALSE; |
| 2224 | |
| 2225 | return TRUE; |
| 2226 | } |
| 2227 | |
| 2228 | /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions. |
| 2229 | The base register is put in *PBASE. |
| 2230 | The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of |
| 2231 | the return value. |
| 2232 | The register stride (minus one) is put in bit 4 of the return value. |
| 2233 | Bits [6:5] encode the list length (minus one). |
| 2234 | The type of the list elements is put in *ELTYPE, if non-NULL. */ |
| 2235 | |
| 2236 | #define NEON_LANE(X) ((X) & 0xf) |
| 2237 | #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) |
| 2238 | #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) |
| 2239 | |
| 2240 | static int |
| 2241 | parse_neon_el_struct_list (char **str, unsigned *pbase, |
| 2242 | int mve, |
| 2243 | struct neon_type_el *eltype) |
| 2244 | { |
| 2245 | char *ptr = *str; |
| 2246 | int base_reg = -1; |
| 2247 | int reg_incr = -1; |
| 2248 | int count = 0; |
| 2249 | int lane = -1; |
| 2250 | int leading_brace = 0; |
| 2251 | enum arm_reg_type rtype = REG_TYPE_NDQ; |
| 2252 | const char *const incr_error = mve ? _("register stride must be 1") : |
| 2253 | _("register stride must be 1 or 2"); |
| 2254 | const char *const type_error = _("mismatched element/structure types in list"); |
| 2255 | struct neon_typed_alias firsttype; |
| 2256 | firsttype.defined = 0; |
| 2257 | firsttype.eltype.type = NT_invtype; |
| 2258 | firsttype.eltype.size = -1; |
| 2259 | firsttype.index = -1; |
| 2260 | |
| 2261 | if (skip_past_char (&ptr, '{') == SUCCESS) |
| 2262 | leading_brace = 1; |
| 2263 | |
| 2264 | do |
| 2265 | { |
| 2266 | struct neon_typed_alias atype; |
| 2267 | if (mve) |
| 2268 | rtype = REG_TYPE_MQ; |
| 2269 | int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); |
| 2270 | |
| 2271 | if (getreg == FAIL) |
| 2272 | { |
| 2273 | first_error (_(reg_expected_msgs[rtype])); |
| 2274 | return FAIL; |
| 2275 | } |
| 2276 | |
| 2277 | if (base_reg == -1) |
| 2278 | { |
| 2279 | base_reg = getreg; |
| 2280 | if (rtype == REG_TYPE_NQ) |
| 2281 | { |
| 2282 | reg_incr = 1; |
| 2283 | } |
| 2284 | firsttype = atype; |
| 2285 | } |
| 2286 | else if (reg_incr == -1) |
| 2287 | { |
| 2288 | reg_incr = getreg - base_reg; |
| 2289 | if (reg_incr < 1 || reg_incr > 2) |
| 2290 | { |
| 2291 | first_error (_(incr_error)); |
| 2292 | return FAIL; |
| 2293 | } |
| 2294 | } |
| 2295 | else if (getreg != base_reg + reg_incr * count) |
| 2296 | { |
| 2297 | first_error (_(incr_error)); |
| 2298 | return FAIL; |
| 2299 | } |
| 2300 | |
| 2301 | if (! neon_alias_types_same (&atype, &firsttype)) |
| 2302 | { |
| 2303 | first_error (_(type_error)); |
| 2304 | return FAIL; |
| 2305 | } |
| 2306 | |
| 2307 | /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list |
| 2308 | modes. */ |
| 2309 | if (ptr[0] == '-') |
| 2310 | { |
| 2311 | struct neon_typed_alias htype; |
| 2312 | int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; |
| 2313 | if (lane == -1) |
| 2314 | lane = NEON_INTERLEAVE_LANES; |
| 2315 | else if (lane != NEON_INTERLEAVE_LANES) |
| 2316 | { |
| 2317 | first_error (_(type_error)); |
| 2318 | return FAIL; |
| 2319 | } |
| 2320 | if (reg_incr == -1) |
| 2321 | reg_incr = 1; |
| 2322 | else if (reg_incr != 1) |
| 2323 | { |
| 2324 | first_error (_("don't use Rn-Rm syntax with non-unit stride")); |
| 2325 | return FAIL; |
| 2326 | } |
| 2327 | ptr++; |
| 2328 | hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); |
| 2329 | if (hireg == FAIL) |
| 2330 | { |
| 2331 | first_error (_(reg_expected_msgs[rtype])); |
| 2332 | return FAIL; |
| 2333 | } |
| 2334 | if (! neon_alias_types_same (&htype, &firsttype)) |
| 2335 | { |
| 2336 | first_error (_(type_error)); |
| 2337 | return FAIL; |
| 2338 | } |
| 2339 | count += hireg + dregs - getreg; |
| 2340 | continue; |
| 2341 | } |
| 2342 | |
| 2343 | /* If we're using Q registers, we can't use [] or [n] syntax. */ |
| 2344 | if (rtype == REG_TYPE_NQ) |
| 2345 | { |
| 2346 | count += 2; |
| 2347 | continue; |
| 2348 | } |
| 2349 | |
| 2350 | if ((atype.defined & NTA_HASINDEX) != 0) |
| 2351 | { |
| 2352 | if (lane == -1) |
| 2353 | lane = atype.index; |
| 2354 | else if (lane != atype.index) |
| 2355 | { |
| 2356 | first_error (_(type_error)); |
| 2357 | return FAIL; |
| 2358 | } |
| 2359 | } |
| 2360 | else if (lane == -1) |
| 2361 | lane = NEON_INTERLEAVE_LANES; |
| 2362 | else if (lane != NEON_INTERLEAVE_LANES) |
| 2363 | { |
| 2364 | first_error (_(type_error)); |
| 2365 | return FAIL; |
| 2366 | } |
| 2367 | count++; |
| 2368 | } |
| 2369 | while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); |
| 2370 | |
| 2371 | /* No lane set by [x]. We must be interleaving structures. */ |
| 2372 | if (lane == -1) |
| 2373 | lane = NEON_INTERLEAVE_LANES; |
| 2374 | |
| 2375 | /* Sanity check. */ |
| 2376 | if (lane == -1 || base_reg == -1 || count < 1 || (!mve && count > 4) |
| 2377 | || (count > 1 && reg_incr == -1)) |
| 2378 | { |
| 2379 | first_error (_("error parsing element/structure list")); |
| 2380 | return FAIL; |
| 2381 | } |
| 2382 | |
| 2383 | if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) |
| 2384 | { |
| 2385 | first_error (_("expected }")); |
| 2386 | return FAIL; |
| 2387 | } |
| 2388 | |
| 2389 | if (reg_incr == -1) |
| 2390 | reg_incr = 1; |
| 2391 | |
| 2392 | if (eltype) |
| 2393 | *eltype = firsttype.eltype; |
| 2394 | |
| 2395 | *pbase = base_reg; |
| 2396 | *str = ptr; |
| 2397 | |
| 2398 | return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); |
| 2399 | } |
| 2400 | |
| 2401 | /* Parse an explicit relocation suffix on an expression. This is |
| 2402 | either nothing, or a word in parentheses. Note that if !OBJ_ELF, |
| 2403 | arm_reloc_hsh contains no entries, so this function can only |
| 2404 | succeed if there is no () after the word. Returns -1 on error, |
| 2405 | BFD_RELOC_UNUSED if there wasn't any suffix. */ |
| 2406 | |
| 2407 | static int |
| 2408 | parse_reloc (char **str) |
| 2409 | { |
| 2410 | struct reloc_entry *r; |
| 2411 | char *p, *q; |
| 2412 | |
| 2413 | if (**str != '(') |
| 2414 | return BFD_RELOC_UNUSED; |
| 2415 | |
| 2416 | p = *str + 1; |
| 2417 | q = p; |
| 2418 | |
| 2419 | while (*q && *q != ')' && *q != ',') |
| 2420 | q++; |
| 2421 | if (*q != ')') |
| 2422 | return -1; |
| 2423 | |
| 2424 | if ((r = (struct reloc_entry *) |
| 2425 | hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) |
| 2426 | return -1; |
| 2427 | |
| 2428 | *str = q + 1; |
| 2429 | return r->reloc; |
| 2430 | } |
| 2431 | |
| 2432 | /* Directives: register aliases. */ |
| 2433 | |
| 2434 | static struct reg_entry * |
| 2435 | insert_reg_alias (char *str, unsigned number, int type) |
| 2436 | { |
| 2437 | struct reg_entry *new_reg; |
| 2438 | const char *name; |
| 2439 | |
| 2440 | if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0) |
| 2441 | { |
| 2442 | if (new_reg->builtin) |
| 2443 | as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); |
| 2444 | |
| 2445 | /* Only warn about a redefinition if it's not defined as the |
| 2446 | same register. */ |
| 2447 | else if (new_reg->number != number || new_reg->type != type) |
| 2448 | as_warn (_("ignoring redefinition of register alias '%s'"), str); |
| 2449 | |
| 2450 | return NULL; |
| 2451 | } |
| 2452 | |
| 2453 | name = xstrdup (str); |
| 2454 | new_reg = XNEW (struct reg_entry); |
| 2455 | |
| 2456 | new_reg->name = name; |
| 2457 | new_reg->number = number; |
| 2458 | new_reg->type = type; |
| 2459 | new_reg->builtin = FALSE; |
| 2460 | new_reg->neon = NULL; |
| 2461 | |
| 2462 | if (hash_insert (arm_reg_hsh, name, (void *) new_reg)) |
| 2463 | abort (); |
| 2464 | |
| 2465 | return new_reg; |
| 2466 | } |
| 2467 | |
| 2468 | static void |
| 2469 | insert_neon_reg_alias (char *str, int number, int type, |
| 2470 | struct neon_typed_alias *atype) |
| 2471 | { |
| 2472 | struct reg_entry *reg = insert_reg_alias (str, number, type); |
| 2473 | |
| 2474 | if (!reg) |
| 2475 | { |
| 2476 | first_error (_("attempt to redefine typed alias")); |
| 2477 | return; |
| 2478 | } |
| 2479 | |
| 2480 | if (atype) |
| 2481 | { |
| 2482 | reg->neon = XNEW (struct neon_typed_alias); |
| 2483 | *reg->neon = *atype; |
| 2484 | } |
| 2485 | } |
| 2486 | |
| 2487 | /* Look for the .req directive. This is of the form: |
| 2488 | |
| 2489 | new_register_name .req existing_register_name |
| 2490 | |
| 2491 | If we find one, or if it looks sufficiently like one that we want to |
| 2492 | handle any error here, return TRUE. Otherwise return FALSE. */ |
| 2493 | |
| 2494 | static bfd_boolean |
| 2495 | create_register_alias (char * newname, char *p) |
| 2496 | { |
| 2497 | struct reg_entry *old; |
| 2498 | char *oldname, *nbuf; |
| 2499 | size_t nlen; |
| 2500 | |
| 2501 | /* The input scrubber ensures that whitespace after the mnemonic is |
| 2502 | collapsed to single spaces. */ |
| 2503 | oldname = p; |
| 2504 | if (strncmp (oldname, " .req ", 6) != 0) |
| 2505 | return FALSE; |
| 2506 | |
| 2507 | oldname += 6; |
| 2508 | if (*oldname == '\0') |
| 2509 | return FALSE; |
| 2510 | |
| 2511 | old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname); |
| 2512 | if (!old) |
| 2513 | { |
| 2514 | as_warn (_("unknown register '%s' -- .req ignored"), oldname); |
| 2515 | return TRUE; |
| 2516 | } |
| 2517 | |
| 2518 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
| 2519 | the desired alias name, and p points to its end. If not, then |
| 2520 | the desired alias name is in the global original_case_string. */ |
| 2521 | #ifdef TC_CASE_SENSITIVE |
| 2522 | nlen = p - newname; |
| 2523 | #else |
| 2524 | newname = original_case_string; |
| 2525 | nlen = strlen (newname); |
| 2526 | #endif |
| 2527 | |
| 2528 | nbuf = xmemdup0 (newname, nlen); |
| 2529 | |
| 2530 | /* Create aliases under the new name as stated; an all-lowercase |
| 2531 | version of the new name; and an all-uppercase version of the new |
| 2532 | name. */ |
| 2533 | if (insert_reg_alias (nbuf, old->number, old->type) != NULL) |
| 2534 | { |
| 2535 | for (p = nbuf; *p; p++) |
| 2536 | *p = TOUPPER (*p); |
| 2537 | |
| 2538 | if (strncmp (nbuf, newname, nlen)) |
| 2539 | { |
| 2540 | /* If this attempt to create an additional alias fails, do not bother |
| 2541 | trying to create the all-lower case alias. We will fail and issue |
| 2542 | a second, duplicate error message. This situation arises when the |
| 2543 | programmer does something like: |
| 2544 | foo .req r0 |
| 2545 | Foo .req r1 |
| 2546 | The second .req creates the "Foo" alias but then fails to create |
| 2547 | the artificial FOO alias because it has already been created by the |
| 2548 | first .req. */ |
| 2549 | if (insert_reg_alias (nbuf, old->number, old->type) == NULL) |
| 2550 | { |
| 2551 | free (nbuf); |
| 2552 | return TRUE; |
| 2553 | } |
| 2554 | } |
| 2555 | |
| 2556 | for (p = nbuf; *p; p++) |
| 2557 | *p = TOLOWER (*p); |
| 2558 | |
| 2559 | if (strncmp (nbuf, newname, nlen)) |
| 2560 | insert_reg_alias (nbuf, old->number, old->type); |
| 2561 | } |
| 2562 | |
| 2563 | free (nbuf); |
| 2564 | return TRUE; |
| 2565 | } |
| 2566 | |
| 2567 | /* Create a Neon typed/indexed register alias using directives, e.g.: |
| 2568 | X .dn d5.s32[1] |
| 2569 | Y .qn 6.s16 |
| 2570 | Z .dn d7 |
| 2571 | T .dn Z[0] |
| 2572 | These typed registers can be used instead of the types specified after the |
| 2573 | Neon mnemonic, so long as all operands given have types. Types can also be |
| 2574 | specified directly, e.g.: |
| 2575 | vadd d0.s32, d1.s32, d2.s32 */ |
| 2576 | |
| 2577 | static bfd_boolean |
| 2578 | create_neon_reg_alias (char *newname, char *p) |
| 2579 | { |
| 2580 | enum arm_reg_type basetype; |
| 2581 | struct reg_entry *basereg; |
| 2582 | struct reg_entry mybasereg; |
| 2583 | struct neon_type ntype; |
| 2584 | struct neon_typed_alias typeinfo; |
| 2585 | char *namebuf, *nameend ATTRIBUTE_UNUSED; |
| 2586 | int namelen; |
| 2587 | |
| 2588 | typeinfo.defined = 0; |
| 2589 | typeinfo.eltype.type = NT_invtype; |
| 2590 | typeinfo.eltype.size = -1; |
| 2591 | typeinfo.index = -1; |
| 2592 | |
| 2593 | nameend = p; |
| 2594 | |
| 2595 | if (strncmp (p, " .dn ", 5) == 0) |
| 2596 | basetype = REG_TYPE_VFD; |
| 2597 | else if (strncmp (p, " .qn ", 5) == 0) |
| 2598 | basetype = REG_TYPE_NQ; |
| 2599 | else |
| 2600 | return FALSE; |
| 2601 | |
| 2602 | p += 5; |
| 2603 | |
| 2604 | if (*p == '\0') |
| 2605 | return FALSE; |
| 2606 | |
| 2607 | basereg = arm_reg_parse_multi (&p); |
| 2608 | |
| 2609 | if (basereg && basereg->type != basetype) |
| 2610 | { |
| 2611 | as_bad (_("bad type for register")); |
| 2612 | return FALSE; |
| 2613 | } |
| 2614 | |
| 2615 | if (basereg == NULL) |
| 2616 | { |
| 2617 | expressionS exp; |
| 2618 | /* Try parsing as an integer. */ |
| 2619 | my_get_expression (&exp, &p, GE_NO_PREFIX); |
| 2620 | if (exp.X_op != O_constant) |
| 2621 | { |
| 2622 | as_bad (_("expression must be constant")); |
| 2623 | return FALSE; |
| 2624 | } |
| 2625 | basereg = &mybasereg; |
| 2626 | basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 |
| 2627 | : exp.X_add_number; |
| 2628 | basereg->neon = 0; |
| 2629 | } |
| 2630 | |
| 2631 | if (basereg->neon) |
| 2632 | typeinfo = *basereg->neon; |
| 2633 | |
| 2634 | if (parse_neon_type (&ntype, &p) == SUCCESS) |
| 2635 | { |
| 2636 | /* We got a type. */ |
| 2637 | if (typeinfo.defined & NTA_HASTYPE) |
| 2638 | { |
| 2639 | as_bad (_("can't redefine the type of a register alias")); |
| 2640 | return FALSE; |
| 2641 | } |
| 2642 | |
| 2643 | typeinfo.defined |= NTA_HASTYPE; |
| 2644 | if (ntype.elems != 1) |
| 2645 | { |
| 2646 | as_bad (_("you must specify a single type only")); |
| 2647 | return FALSE; |
| 2648 | } |
| 2649 | typeinfo.eltype = ntype.el[0]; |
| 2650 | } |
| 2651 | |
| 2652 | if (skip_past_char (&p, '[') == SUCCESS) |
| 2653 | { |
| 2654 | expressionS exp; |
| 2655 | /* We got a scalar index. */ |
| 2656 | |
| 2657 | if (typeinfo.defined & NTA_HASINDEX) |
| 2658 | { |
| 2659 | as_bad (_("can't redefine the index of a scalar alias")); |
| 2660 | return FALSE; |
| 2661 | } |
| 2662 | |
| 2663 | my_get_expression (&exp, &p, GE_NO_PREFIX); |
| 2664 | |
| 2665 | if (exp.X_op != O_constant) |
| 2666 | { |
| 2667 | as_bad (_("scalar index must be constant")); |
| 2668 | return FALSE; |
| 2669 | } |
| 2670 | |
| 2671 | typeinfo.defined |= NTA_HASINDEX; |
| 2672 | typeinfo.index = exp.X_add_number; |
| 2673 | |
| 2674 | if (skip_past_char (&p, ']') == FAIL) |
| 2675 | { |
| 2676 | as_bad (_("expecting ]")); |
| 2677 | return FALSE; |
| 2678 | } |
| 2679 | } |
| 2680 | |
| 2681 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
| 2682 | the desired alias name, and p points to its end. If not, then |
| 2683 | the desired alias name is in the global original_case_string. */ |
| 2684 | #ifdef TC_CASE_SENSITIVE |
| 2685 | namelen = nameend - newname; |
| 2686 | #else |
| 2687 | newname = original_case_string; |
| 2688 | namelen = strlen (newname); |
| 2689 | #endif |
| 2690 | |
| 2691 | namebuf = xmemdup0 (newname, namelen); |
| 2692 | |
| 2693 | insert_neon_reg_alias (namebuf, basereg->number, basetype, |
| 2694 | typeinfo.defined != 0 ? &typeinfo : NULL); |
| 2695 | |
| 2696 | /* Insert name in all uppercase. */ |
| 2697 | for (p = namebuf; *p; p++) |
| 2698 | *p = TOUPPER (*p); |
| 2699 | |
| 2700 | if (strncmp (namebuf, newname, namelen)) |
| 2701 | insert_neon_reg_alias (namebuf, basereg->number, basetype, |
| 2702 | typeinfo.defined != 0 ? &typeinfo : NULL); |
| 2703 | |
| 2704 | /* Insert name in all lowercase. */ |
| 2705 | for (p = namebuf; *p; p++) |
| 2706 | *p = TOLOWER (*p); |
| 2707 | |
| 2708 | if (strncmp (namebuf, newname, namelen)) |
| 2709 | insert_neon_reg_alias (namebuf, basereg->number, basetype, |
| 2710 | typeinfo.defined != 0 ? &typeinfo : NULL); |
| 2711 | |
| 2712 | free (namebuf); |
| 2713 | return TRUE; |
| 2714 | } |
| 2715 | |
| 2716 | /* Should never be called, as .req goes between the alias and the |
| 2717 | register name, not at the beginning of the line. */ |
| 2718 | |
| 2719 | static void |
| 2720 | s_req (int a ATTRIBUTE_UNUSED) |
| 2721 | { |
| 2722 | as_bad (_("invalid syntax for .req directive")); |
| 2723 | } |
| 2724 | |
| 2725 | static void |
| 2726 | s_dn (int a ATTRIBUTE_UNUSED) |
| 2727 | { |
| 2728 | as_bad (_("invalid syntax for .dn directive")); |
| 2729 | } |
| 2730 | |
| 2731 | static void |
| 2732 | s_qn (int a ATTRIBUTE_UNUSED) |
| 2733 | { |
| 2734 | as_bad (_("invalid syntax for .qn directive")); |
| 2735 | } |
| 2736 | |
| 2737 | /* The .unreq directive deletes an alias which was previously defined |
| 2738 | by .req. For example: |
| 2739 | |
| 2740 | my_alias .req r11 |
| 2741 | .unreq my_alias */ |
| 2742 | |
| 2743 | static void |
| 2744 | s_unreq (int a ATTRIBUTE_UNUSED) |
| 2745 | { |
| 2746 | char * name; |
| 2747 | char saved_char; |
| 2748 | |
| 2749 | name = input_line_pointer; |
| 2750 | |
| 2751 | while (*input_line_pointer != 0 |
| 2752 | && *input_line_pointer != ' ' |
| 2753 | && *input_line_pointer != '\n') |
| 2754 | ++input_line_pointer; |
| 2755 | |
| 2756 | saved_char = *input_line_pointer; |
| 2757 | *input_line_pointer = 0; |
| 2758 | |
| 2759 | if (!*name) |
| 2760 | as_bad (_("invalid syntax for .unreq directive")); |
| 2761 | else |
| 2762 | { |
| 2763 | struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh, |
| 2764 | name); |
| 2765 | |
| 2766 | if (!reg) |
| 2767 | as_bad (_("unknown register alias '%s'"), name); |
| 2768 | else if (reg->builtin) |
| 2769 | as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"), |
| 2770 | name); |
| 2771 | else |
| 2772 | { |
| 2773 | char * p; |
| 2774 | char * nbuf; |
| 2775 | |
| 2776 | hash_delete (arm_reg_hsh, name, FALSE); |
| 2777 | free ((char *) reg->name); |
| 2778 | if (reg->neon) |
| 2779 | free (reg->neon); |
| 2780 | free (reg); |
| 2781 | |
| 2782 | /* Also locate the all upper case and all lower case versions. |
| 2783 | Do not complain if we cannot find one or the other as it |
| 2784 | was probably deleted above. */ |
| 2785 | |
| 2786 | nbuf = strdup (name); |
| 2787 | for (p = nbuf; *p; p++) |
| 2788 | *p = TOUPPER (*p); |
| 2789 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
| 2790 | if (reg) |
| 2791 | { |
| 2792 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
| 2793 | free ((char *) reg->name); |
| 2794 | if (reg->neon) |
| 2795 | free (reg->neon); |
| 2796 | free (reg); |
| 2797 | } |
| 2798 | |
| 2799 | for (p = nbuf; *p; p++) |
| 2800 | *p = TOLOWER (*p); |
| 2801 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
| 2802 | if (reg) |
| 2803 | { |
| 2804 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
| 2805 | free ((char *) reg->name); |
| 2806 | if (reg->neon) |
| 2807 | free (reg->neon); |
| 2808 | free (reg); |
| 2809 | } |
| 2810 | |
| 2811 | free (nbuf); |
| 2812 | } |
| 2813 | } |
| 2814 | |
| 2815 | *input_line_pointer = saved_char; |
| 2816 | demand_empty_rest_of_line (); |
| 2817 | } |
| 2818 | |
| 2819 | /* Directives: Instruction set selection. */ |
| 2820 | |
| 2821 | #ifdef OBJ_ELF |
| 2822 | /* This code is to handle mapping symbols as defined in the ARM ELF spec. |
| 2823 | (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). |
| 2824 | Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), |
| 2825 | and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ |
| 2826 | |
| 2827 | /* Create a new mapping symbol for the transition to STATE. */ |
| 2828 | |
| 2829 | static void |
| 2830 | make_mapping_symbol (enum mstate state, valueT value, fragS *frag) |
| 2831 | { |
| 2832 | symbolS * symbolP; |
| 2833 | const char * symname; |
| 2834 | int type; |
| 2835 | |
| 2836 | switch (state) |
| 2837 | { |
| 2838 | case MAP_DATA: |
| 2839 | symname = "$d"; |
| 2840 | type = BSF_NO_FLAGS; |
| 2841 | break; |
| 2842 | case MAP_ARM: |
| 2843 | symname = "$a"; |
| 2844 | type = BSF_NO_FLAGS; |
| 2845 | break; |
| 2846 | case MAP_THUMB: |
| 2847 | symname = "$t"; |
| 2848 | type = BSF_NO_FLAGS; |
| 2849 | break; |
| 2850 | default: |
| 2851 | abort (); |
| 2852 | } |
| 2853 | |
| 2854 | symbolP = symbol_new (symname, now_seg, value, frag); |
| 2855 | symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; |
| 2856 | |
| 2857 | switch (state) |
| 2858 | { |
| 2859 | case MAP_ARM: |
| 2860 | THUMB_SET_FUNC (symbolP, 0); |
| 2861 | ARM_SET_THUMB (symbolP, 0); |
| 2862 | ARM_SET_INTERWORK (symbolP, support_interwork); |
| 2863 | break; |
| 2864 | |
| 2865 | case MAP_THUMB: |
| 2866 | THUMB_SET_FUNC (symbolP, 1); |
| 2867 | ARM_SET_THUMB (symbolP, 1); |
| 2868 | ARM_SET_INTERWORK (symbolP, support_interwork); |
| 2869 | break; |
| 2870 | |
| 2871 | case MAP_DATA: |
| 2872 | default: |
| 2873 | break; |
| 2874 | } |
| 2875 | |
| 2876 | /* Save the mapping symbols for future reference. Also check that |
| 2877 | we do not place two mapping symbols at the same offset within a |
| 2878 | frag. We'll handle overlap between frags in |
| 2879 | check_mapping_symbols. |
| 2880 | |
| 2881 | If .fill or other data filling directive generates zero sized data, |
| 2882 | the mapping symbol for the following code will have the same value |
| 2883 | as the one generated for the data filling directive. In this case, |
| 2884 | we replace the old symbol with the new one at the same address. */ |
| 2885 | if (value == 0) |
| 2886 | { |
| 2887 | if (frag->tc_frag_data.first_map != NULL) |
| 2888 | { |
| 2889 | know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0); |
| 2890 | symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP); |
| 2891 | } |
| 2892 | frag->tc_frag_data.first_map = symbolP; |
| 2893 | } |
| 2894 | if (frag->tc_frag_data.last_map != NULL) |
| 2895 | { |
| 2896 | know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP)); |
| 2897 | if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP)) |
| 2898 | symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP); |
| 2899 | } |
| 2900 | frag->tc_frag_data.last_map = symbolP; |
| 2901 | } |
| 2902 | |
| 2903 | /* We must sometimes convert a region marked as code to data during |
| 2904 | code alignment, if an odd number of bytes have to be padded. The |
| 2905 | code mapping symbol is pushed to an aligned address. */ |
| 2906 | |
| 2907 | static void |
| 2908 | insert_data_mapping_symbol (enum mstate state, |
| 2909 | valueT value, fragS *frag, offsetT bytes) |
| 2910 | { |
| 2911 | /* If there was already a mapping symbol, remove it. */ |
| 2912 | if (frag->tc_frag_data.last_map != NULL |
| 2913 | && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value) |
| 2914 | { |
| 2915 | symbolS *symp = frag->tc_frag_data.last_map; |
| 2916 | |
| 2917 | if (value == 0) |
| 2918 | { |
| 2919 | know (frag->tc_frag_data.first_map == symp); |
| 2920 | frag->tc_frag_data.first_map = NULL; |
| 2921 | } |
| 2922 | frag->tc_frag_data.last_map = NULL; |
| 2923 | symbol_remove (symp, &symbol_rootP, &symbol_lastP); |
| 2924 | } |
| 2925 | |
| 2926 | make_mapping_symbol (MAP_DATA, value, frag); |
| 2927 | make_mapping_symbol (state, value + bytes, frag); |
| 2928 | } |
| 2929 | |
| 2930 | static void mapping_state_2 (enum mstate state, int max_chars); |
| 2931 | |
| 2932 | /* Set the mapping state to STATE. Only call this when about to |
| 2933 | emit some STATE bytes to the file. */ |
| 2934 | |
| 2935 | #define TRANSITION(from, to) (mapstate == (from) && state == (to)) |
| 2936 | void |
| 2937 | mapping_state (enum mstate state) |
| 2938 | { |
| 2939 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
| 2940 | |
| 2941 | if (mapstate == state) |
| 2942 | /* The mapping symbol has already been emitted. |
| 2943 | There is nothing else to do. */ |
| 2944 | return; |
| 2945 | |
| 2946 | if (state == MAP_ARM || state == MAP_THUMB) |
| 2947 | /* PR gas/12931 |
| 2948 | All ARM instructions require 4-byte alignment. |
| 2949 | (Almost) all Thumb instructions require 2-byte alignment. |
| 2950 | |
| 2951 | When emitting instructions into any section, mark the section |
| 2952 | appropriately. |
| 2953 | |
| 2954 | Some Thumb instructions are alignment-sensitive modulo 4 bytes, |
| 2955 | but themselves require 2-byte alignment; this applies to some |
| 2956 | PC- relative forms. However, these cases will involve implicit |
| 2957 | literal pool generation or an explicit .align >=2, both of |
| 2958 | which will cause the section to me marked with sufficient |
| 2959 | alignment. Thus, we don't handle those cases here. */ |
| 2960 | record_alignment (now_seg, state == MAP_ARM ? 2 : 1); |
| 2961 | |
| 2962 | if (TRANSITION (MAP_UNDEFINED, MAP_DATA)) |
| 2963 | /* This case will be evaluated later. */ |
| 2964 | return; |
| 2965 | |
| 2966 | mapping_state_2 (state, 0); |
| 2967 | } |
| 2968 | |
| 2969 | /* Same as mapping_state, but MAX_CHARS bytes have already been |
| 2970 | allocated. Put the mapping symbol that far back. */ |
| 2971 | |
| 2972 | static void |
| 2973 | mapping_state_2 (enum mstate state, int max_chars) |
| 2974 | { |
| 2975 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
| 2976 | |
| 2977 | if (!SEG_NORMAL (now_seg)) |
| 2978 | return; |
| 2979 | |
| 2980 | if (mapstate == state) |
| 2981 | /* The mapping symbol has already been emitted. |
| 2982 | There is nothing else to do. */ |
| 2983 | return; |
| 2984 | |
| 2985 | if (TRANSITION (MAP_UNDEFINED, MAP_ARM) |
| 2986 | || TRANSITION (MAP_UNDEFINED, MAP_THUMB)) |
| 2987 | { |
| 2988 | struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root; |
| 2989 | const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0); |
| 2990 | |
| 2991 | if (add_symbol) |
| 2992 | make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first); |
| 2993 | } |
| 2994 | |
| 2995 | seg_info (now_seg)->tc_segment_info_data.mapstate = state; |
| 2996 | make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now); |
| 2997 | } |
| 2998 | #undef TRANSITION |
| 2999 | #else |
| 3000 | #define mapping_state(x) ((void)0) |
| 3001 | #define mapping_state_2(x, y) ((void)0) |
| 3002 | #endif |
| 3003 | |
| 3004 | /* Find the real, Thumb encoded start of a Thumb function. */ |
| 3005 | |
| 3006 | #ifdef OBJ_COFF |
| 3007 | static symbolS * |
| 3008 | find_real_start (symbolS * symbolP) |
| 3009 | { |
| 3010 | char * real_start; |
| 3011 | const char * name = S_GET_NAME (symbolP); |
| 3012 | symbolS * new_target; |
| 3013 | |
| 3014 | /* This definition must agree with the one in gcc/config/arm/thumb.c. */ |
| 3015 | #define STUB_NAME ".real_start_of" |
| 3016 | |
| 3017 | if (name == NULL) |
| 3018 | abort (); |
| 3019 | |
| 3020 | /* The compiler may generate BL instructions to local labels because |
| 3021 | it needs to perform a branch to a far away location. These labels |
| 3022 | do not have a corresponding ".real_start_of" label. We check |
| 3023 | both for S_IS_LOCAL and for a leading dot, to give a way to bypass |
| 3024 | the ".real_start_of" convention for nonlocal branches. */ |
| 3025 | if (S_IS_LOCAL (symbolP) || name[0] == '.') |
| 3026 | return symbolP; |
| 3027 | |
| 3028 | real_start = concat (STUB_NAME, name, NULL); |
| 3029 | new_target = symbol_find (real_start); |
| 3030 | free (real_start); |
| 3031 | |
| 3032 | if (new_target == NULL) |
| 3033 | { |
| 3034 | as_warn (_("Failed to find real start of function: %s\n"), name); |
| 3035 | new_target = symbolP; |
| 3036 | } |
| 3037 | |
| 3038 | return new_target; |
| 3039 | } |
| 3040 | #endif |
| 3041 | |
| 3042 | static void |
| 3043 | opcode_select (int width) |
| 3044 | { |
| 3045 | switch (width) |
| 3046 | { |
| 3047 | case 16: |
| 3048 | if (! thumb_mode) |
| 3049 | { |
| 3050 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
| 3051 | as_bad (_("selected processor does not support THUMB opcodes")); |
| 3052 | |
| 3053 | thumb_mode = 1; |
| 3054 | /* No need to force the alignment, since we will have been |
| 3055 | coming from ARM mode, which is word-aligned. */ |
| 3056 | record_alignment (now_seg, 1); |
| 3057 | } |
| 3058 | break; |
| 3059 | |
| 3060 | case 32: |
| 3061 | if (thumb_mode) |
| 3062 | { |
| 3063 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
| 3064 | as_bad (_("selected processor does not support ARM opcodes")); |
| 3065 | |
| 3066 | thumb_mode = 0; |
| 3067 | |
| 3068 | if (!need_pass_2) |
| 3069 | frag_align (2, 0, 0); |
| 3070 | |
| 3071 | record_alignment (now_seg, 1); |
| 3072 | } |
| 3073 | break; |
| 3074 | |
| 3075 | default: |
| 3076 | as_bad (_("invalid instruction size selected (%d)"), width); |
| 3077 | } |
| 3078 | } |
| 3079 | |
| 3080 | static void |
| 3081 | s_arm (int ignore ATTRIBUTE_UNUSED) |
| 3082 | { |
| 3083 | opcode_select (32); |
| 3084 | demand_empty_rest_of_line (); |
| 3085 | } |
| 3086 | |
| 3087 | static void |
| 3088 | s_thumb (int ignore ATTRIBUTE_UNUSED) |
| 3089 | { |
| 3090 | opcode_select (16); |
| 3091 | demand_empty_rest_of_line (); |
| 3092 | } |
| 3093 | |
| 3094 | static void |
| 3095 | s_code (int unused ATTRIBUTE_UNUSED) |
| 3096 | { |
| 3097 | int temp; |
| 3098 | |
| 3099 | temp = get_absolute_expression (); |
| 3100 | switch (temp) |
| 3101 | { |
| 3102 | case 16: |
| 3103 | case 32: |
| 3104 | opcode_select (temp); |
| 3105 | break; |
| 3106 | |
| 3107 | default: |
| 3108 | as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); |
| 3109 | } |
| 3110 | } |
| 3111 | |
| 3112 | static void |
| 3113 | s_force_thumb (int ignore ATTRIBUTE_UNUSED) |
| 3114 | { |
| 3115 | /* If we are not already in thumb mode go into it, EVEN if |
| 3116 | the target processor does not support thumb instructions. |
| 3117 | This is used by gcc/config/arm/lib1funcs.asm for example |
| 3118 | to compile interworking support functions even if the |
| 3119 | target processor should not support interworking. */ |
| 3120 | if (! thumb_mode) |
| 3121 | { |
| 3122 | thumb_mode = 2; |
| 3123 | record_alignment (now_seg, 1); |
| 3124 | } |
| 3125 | |
| 3126 | demand_empty_rest_of_line (); |
| 3127 | } |
| 3128 | |
| 3129 | static void |
| 3130 | s_thumb_func (int ignore ATTRIBUTE_UNUSED) |
| 3131 | { |
| 3132 | s_thumb (0); |
| 3133 | |
| 3134 | /* The following label is the name/address of the start of a Thumb function. |
| 3135 | We need to know this for the interworking support. */ |
| 3136 | label_is_thumb_function_name = TRUE; |
| 3137 | } |
| 3138 | |
| 3139 | /* Perform a .set directive, but also mark the alias as |
| 3140 | being a thumb function. */ |
| 3141 | |
| 3142 | static void |
| 3143 | s_thumb_set (int equiv) |
| 3144 | { |
| 3145 | /* XXX the following is a duplicate of the code for s_set() in read.c |
| 3146 | We cannot just call that code as we need to get at the symbol that |
| 3147 | is created. */ |
| 3148 | char * name; |
| 3149 | char delim; |
| 3150 | char * end_name; |
| 3151 | symbolS * symbolP; |
| 3152 | |
| 3153 | /* Especial apologies for the random logic: |
| 3154 | This just grew, and could be parsed much more simply! |
| 3155 | Dean - in haste. */ |
| 3156 | delim = get_symbol_name (& name); |
| 3157 | end_name = input_line_pointer; |
| 3158 | (void) restore_line_pointer (delim); |
| 3159 | |
| 3160 | if (*input_line_pointer != ',') |
| 3161 | { |
| 3162 | *end_name = 0; |
| 3163 | as_bad (_("expected comma after name \"%s\""), name); |
| 3164 | *end_name = delim; |
| 3165 | ignore_rest_of_line (); |
| 3166 | return; |
| 3167 | } |
| 3168 | |
| 3169 | input_line_pointer++; |
| 3170 | *end_name = 0; |
| 3171 | |
| 3172 | if (name[0] == '.' && name[1] == '\0') |
| 3173 | { |
| 3174 | /* XXX - this should not happen to .thumb_set. */ |
| 3175 | abort (); |
| 3176 | } |
| 3177 | |
| 3178 | if ((symbolP = symbol_find (name)) == NULL |
| 3179 | && (symbolP = md_undefined_symbol (name)) == NULL) |
| 3180 | { |
| 3181 | #ifndef NO_LISTING |
| 3182 | /* When doing symbol listings, play games with dummy fragments living |
| 3183 | outside the normal fragment chain to record the file and line info |
| 3184 | for this symbol. */ |
| 3185 | if (listing & LISTING_SYMBOLS) |
| 3186 | { |
| 3187 | extern struct list_info_struct * listing_tail; |
| 3188 | fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS)); |
| 3189 | |
| 3190 | memset (dummy_frag, 0, sizeof (fragS)); |
| 3191 | dummy_frag->fr_type = rs_fill; |
| 3192 | dummy_frag->line = listing_tail; |
| 3193 | symbolP = symbol_new (name, undefined_section, 0, dummy_frag); |
| 3194 | dummy_frag->fr_symbol = symbolP; |
| 3195 | } |
| 3196 | else |
| 3197 | #endif |
| 3198 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); |
| 3199 | |
| 3200 | #ifdef OBJ_COFF |
| 3201 | /* "set" symbols are local unless otherwise specified. */ |
| 3202 | SF_SET_LOCAL (symbolP); |
| 3203 | #endif /* OBJ_COFF */ |
| 3204 | } /* Make a new symbol. */ |
| 3205 | |
| 3206 | symbol_table_insert (symbolP); |
| 3207 | |
| 3208 | * end_name = delim; |
| 3209 | |
| 3210 | if (equiv |
| 3211 | && S_IS_DEFINED (symbolP) |
| 3212 | && S_GET_SEGMENT (symbolP) != reg_section) |
| 3213 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); |
| 3214 | |
| 3215 | pseudo_set (symbolP); |
| 3216 | |
| 3217 | demand_empty_rest_of_line (); |
| 3218 | |
| 3219 | /* XXX Now we come to the Thumb specific bit of code. */ |
| 3220 | |
| 3221 | THUMB_SET_FUNC (symbolP, 1); |
| 3222 | ARM_SET_THUMB (symbolP, 1); |
| 3223 | #if defined OBJ_ELF || defined OBJ_COFF |
| 3224 | ARM_SET_INTERWORK (symbolP, support_interwork); |
| 3225 | #endif |
| 3226 | } |
| 3227 | |
| 3228 | /* Directives: Mode selection. */ |
| 3229 | |
| 3230 | /* .syntax [unified|divided] - choose the new unified syntax |
| 3231 | (same for Arm and Thumb encoding, modulo slight differences in what |
| 3232 | can be represented) or the old divergent syntax for each mode. */ |
| 3233 | static void |
| 3234 | s_syntax (int unused ATTRIBUTE_UNUSED) |
| 3235 | { |
| 3236 | char *name, delim; |
| 3237 | |
| 3238 | delim = get_symbol_name (& name); |
| 3239 | |
| 3240 | if (!strcasecmp (name, "unified")) |
| 3241 | unified_syntax = TRUE; |
| 3242 | else if (!strcasecmp (name, "divided")) |
| 3243 | unified_syntax = FALSE; |
| 3244 | else |
| 3245 | { |
| 3246 | as_bad (_("unrecognized syntax mode \"%s\""), name); |
| 3247 | return; |
| 3248 | } |
| 3249 | (void) restore_line_pointer (delim); |
| 3250 | demand_empty_rest_of_line (); |
| 3251 | } |
| 3252 | |
| 3253 | /* Directives: sectioning and alignment. */ |
| 3254 | |
| 3255 | static void |
| 3256 | s_bss (int ignore ATTRIBUTE_UNUSED) |
| 3257 | { |
| 3258 | /* We don't support putting frags in the BSS segment, we fake it by |
| 3259 | marking in_bss, then looking at s_skip for clues. */ |
| 3260 | subseg_set (bss_section, 0); |
| 3261 | demand_empty_rest_of_line (); |
| 3262 | |
| 3263 | #ifdef md_elf_section_change_hook |
| 3264 | md_elf_section_change_hook (); |
| 3265 | #endif |
| 3266 | } |
| 3267 | |
| 3268 | static void |
| 3269 | s_even (int ignore ATTRIBUTE_UNUSED) |
| 3270 | { |
| 3271 | /* Never make frag if expect extra pass. */ |
| 3272 | if (!need_pass_2) |
| 3273 | frag_align (1, 0, 0); |
| 3274 | |
| 3275 | record_alignment (now_seg, 1); |
| 3276 | |
| 3277 | demand_empty_rest_of_line (); |
| 3278 | } |
| 3279 | |
| 3280 | /* Directives: CodeComposer Studio. */ |
| 3281 | |
| 3282 | /* .ref (for CodeComposer Studio syntax only). */ |
| 3283 | static void |
| 3284 | s_ccs_ref (int unused ATTRIBUTE_UNUSED) |
| 3285 | { |
| 3286 | if (codecomposer_syntax) |
| 3287 | ignore_rest_of_line (); |
| 3288 | else |
| 3289 | as_bad (_(".ref pseudo-op only available with -mccs flag.")); |
| 3290 | } |
| 3291 | |
| 3292 | /* If name is not NULL, then it is used for marking the beginning of a |
| 3293 | function, whereas if it is NULL then it means the function end. */ |
| 3294 | static void |
| 3295 | asmfunc_debug (const char * name) |
| 3296 | { |
| 3297 | static const char * last_name = NULL; |
| 3298 | |
| 3299 | if (name != NULL) |
| 3300 | { |
| 3301 | gas_assert (last_name == NULL); |
| 3302 | last_name = name; |
| 3303 | |
| 3304 | if (debug_type == DEBUG_STABS) |
| 3305 | stabs_generate_asm_func (name, name); |
| 3306 | } |
| 3307 | else |
| 3308 | { |
| 3309 | gas_assert (last_name != NULL); |
| 3310 | |
| 3311 | if (debug_type == DEBUG_STABS) |
| 3312 | stabs_generate_asm_endfunc (last_name, last_name); |
| 3313 | |
| 3314 | last_name = NULL; |
| 3315 | } |
| 3316 | } |
| 3317 | |
| 3318 | static void |
| 3319 | s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED) |
| 3320 | { |
| 3321 | if (codecomposer_syntax) |
| 3322 | { |
| 3323 | switch (asmfunc_state) |
| 3324 | { |
| 3325 | case OUTSIDE_ASMFUNC: |
| 3326 | asmfunc_state = WAITING_ASMFUNC_NAME; |
| 3327 | break; |
| 3328 | |
| 3329 | case WAITING_ASMFUNC_NAME: |
| 3330 | as_bad (_(".asmfunc repeated.")); |
| 3331 | break; |
| 3332 | |
| 3333 | case WAITING_ENDASMFUNC: |
| 3334 | as_bad (_(".asmfunc without function.")); |
| 3335 | break; |
| 3336 | } |
| 3337 | demand_empty_rest_of_line (); |
| 3338 | } |
| 3339 | else |
| 3340 | as_bad (_(".asmfunc pseudo-op only available with -mccs flag.")); |
| 3341 | } |
| 3342 | |
| 3343 | static void |
| 3344 | s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED) |
| 3345 | { |
| 3346 | if (codecomposer_syntax) |
| 3347 | { |
| 3348 | switch (asmfunc_state) |
| 3349 | { |
| 3350 | case OUTSIDE_ASMFUNC: |
| 3351 | as_bad (_(".endasmfunc without a .asmfunc.")); |
| 3352 | break; |
| 3353 | |
| 3354 | case WAITING_ASMFUNC_NAME: |
| 3355 | as_bad (_(".endasmfunc without function.")); |
| 3356 | break; |
| 3357 | |
| 3358 | case WAITING_ENDASMFUNC: |
| 3359 | asmfunc_state = OUTSIDE_ASMFUNC; |
| 3360 | asmfunc_debug (NULL); |
| 3361 | break; |
| 3362 | } |
| 3363 | demand_empty_rest_of_line (); |
| 3364 | } |
| 3365 | else |
| 3366 | as_bad (_(".endasmfunc pseudo-op only available with -mccs flag.")); |
| 3367 | } |
| 3368 | |
| 3369 | static void |
| 3370 | s_ccs_def (int name) |
| 3371 | { |
| 3372 | if (codecomposer_syntax) |
| 3373 | s_globl (name); |
| 3374 | else |
| 3375 | as_bad (_(".def pseudo-op only available with -mccs flag.")); |
| 3376 | } |
| 3377 | |
| 3378 | /* Directives: Literal pools. */ |
| 3379 | |
| 3380 | static literal_pool * |
| 3381 | find_literal_pool (void) |
| 3382 | { |
| 3383 | literal_pool * pool; |
| 3384 | |
| 3385 | for (pool = list_of_pools; pool != NULL; pool = pool->next) |
| 3386 | { |
| 3387 | if (pool->section == now_seg |
| 3388 | && pool->sub_section == now_subseg) |
| 3389 | break; |
| 3390 | } |
| 3391 | |
| 3392 | return pool; |
| 3393 | } |
| 3394 | |
| 3395 | static literal_pool * |
| 3396 | find_or_make_literal_pool (void) |
| 3397 | { |
| 3398 | /* Next literal pool ID number. */ |
| 3399 | static unsigned int latest_pool_num = 1; |
| 3400 | literal_pool * pool; |
| 3401 | |
| 3402 | pool = find_literal_pool (); |
| 3403 | |
| 3404 | if (pool == NULL) |
| 3405 | { |
| 3406 | /* Create a new pool. */ |
| 3407 | pool = XNEW (literal_pool); |
| 3408 | if (! pool) |
| 3409 | return NULL; |
| 3410 | |
| 3411 | pool->next_free_entry = 0; |
| 3412 | pool->section = now_seg; |
| 3413 | pool->sub_section = now_subseg; |
| 3414 | pool->next = list_of_pools; |
| 3415 | pool->symbol = NULL; |
| 3416 | pool->alignment = 2; |
| 3417 | |
| 3418 | /* Add it to the list. */ |
| 3419 | list_of_pools = pool; |
| 3420 | } |
| 3421 | |
| 3422 | /* New pools, and emptied pools, will have a NULL symbol. */ |
| 3423 | if (pool->symbol == NULL) |
| 3424 | { |
| 3425 | pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, |
| 3426 | (valueT) 0, &zero_address_frag); |
| 3427 | pool->id = latest_pool_num ++; |
| 3428 | } |
| 3429 | |
| 3430 | /* Done. */ |
| 3431 | return pool; |
| 3432 | } |
| 3433 | |
| 3434 | /* Add the literal in the global 'inst' |
| 3435 | structure to the relevant literal pool. */ |
| 3436 | |
| 3437 | static int |
| 3438 | add_to_lit_pool (unsigned int nbytes) |
| 3439 | { |
| 3440 | #define PADDING_SLOT 0x1 |
| 3441 | #define LIT_ENTRY_SIZE_MASK 0xFF |
| 3442 | literal_pool * pool; |
| 3443 | unsigned int entry, pool_size = 0; |
| 3444 | bfd_boolean padding_slot_p = FALSE; |
| 3445 | unsigned imm1 = 0; |
| 3446 | unsigned imm2 = 0; |
| 3447 | |
| 3448 | if (nbytes == 8) |
| 3449 | { |
| 3450 | imm1 = inst.operands[1].imm; |
| 3451 | imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg |
| 3452 | : inst.relocs[0].exp.X_unsigned ? 0 |
| 3453 | : ((bfd_int64_t) inst.operands[1].imm) >> 32); |
| 3454 | if (target_big_endian) |
| 3455 | { |
| 3456 | imm1 = imm2; |
| 3457 | imm2 = inst.operands[1].imm; |
| 3458 | } |
| 3459 | } |
| 3460 | |
| 3461 | pool = find_or_make_literal_pool (); |
| 3462 | |
| 3463 | /* Check if this literal value is already in the pool. */ |
| 3464 | for (entry = 0; entry < pool->next_free_entry; entry ++) |
| 3465 | { |
| 3466 | if (nbytes == 4) |
| 3467 | { |
| 3468 | if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op) |
| 3469 | && (inst.relocs[0].exp.X_op == O_constant) |
| 3470 | && (pool->literals[entry].X_add_number |
| 3471 | == inst.relocs[0].exp.X_add_number) |
| 3472 | && (pool->literals[entry].X_md == nbytes) |
| 3473 | && (pool->literals[entry].X_unsigned |
| 3474 | == inst.relocs[0].exp.X_unsigned)) |
| 3475 | break; |
| 3476 | |
| 3477 | if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op) |
| 3478 | && (inst.relocs[0].exp.X_op == O_symbol) |
| 3479 | && (pool->literals[entry].X_add_number |
| 3480 | == inst.relocs[0].exp.X_add_number) |
| 3481 | && (pool->literals[entry].X_add_symbol |
| 3482 | == inst.relocs[0].exp.X_add_symbol) |
| 3483 | && (pool->literals[entry].X_op_symbol |
| 3484 | == inst.relocs[0].exp.X_op_symbol) |
| 3485 | && (pool->literals[entry].X_md == nbytes)) |
| 3486 | break; |
| 3487 | } |
| 3488 | else if ((nbytes == 8) |
| 3489 | && !(pool_size & 0x7) |
| 3490 | && ((entry + 1) != pool->next_free_entry) |
| 3491 | && (pool->literals[entry].X_op == O_constant) |
| 3492 | && (pool->literals[entry].X_add_number == (offsetT) imm1) |
| 3493 | && (pool->literals[entry].X_unsigned |
| 3494 | == inst.relocs[0].exp.X_unsigned) |
| 3495 | && (pool->literals[entry + 1].X_op == O_constant) |
| 3496 | && (pool->literals[entry + 1].X_add_number == (offsetT) imm2) |
| 3497 | && (pool->literals[entry + 1].X_unsigned |
| 3498 | == inst.relocs[0].exp.X_unsigned)) |
| 3499 | break; |
| 3500 | |
| 3501 | padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT); |
| 3502 | if (padding_slot_p && (nbytes == 4)) |
| 3503 | break; |
| 3504 | |
| 3505 | pool_size += 4; |
| 3506 | } |
| 3507 | |
| 3508 | /* Do we need to create a new entry? */ |
| 3509 | if (entry == pool->next_free_entry) |
| 3510 | { |
| 3511 | if (entry >= MAX_LITERAL_POOL_SIZE) |
| 3512 | { |
| 3513 | inst.error = _("literal pool overflow"); |
| 3514 | return FAIL; |
| 3515 | } |
| 3516 | |
| 3517 | if (nbytes == 8) |
| 3518 | { |
| 3519 | /* For 8-byte entries, we align to an 8-byte boundary, |
| 3520 | and split it into two 4-byte entries, because on 32-bit |
| 3521 | host, 8-byte constants are treated as big num, thus |
| 3522 | saved in "generic_bignum" which will be overwritten |
| 3523 | by later assignments. |
| 3524 | |
| 3525 | We also need to make sure there is enough space for |
| 3526 | the split. |
| 3527 | |
| 3528 | We also check to make sure the literal operand is a |
| 3529 | constant number. */ |
| 3530 | if (!(inst.relocs[0].exp.X_op == O_constant |
| 3531 | || inst.relocs[0].exp.X_op == O_big)) |
| 3532 | { |
| 3533 | inst.error = _("invalid type for literal pool"); |
| 3534 | return FAIL; |
| 3535 | } |
| 3536 | else if (pool_size & 0x7) |
| 3537 | { |
| 3538 | if ((entry + 2) >= MAX_LITERAL_POOL_SIZE) |
| 3539 | { |
| 3540 | inst.error = _("literal pool overflow"); |
| 3541 | return FAIL; |
| 3542 | } |
| 3543 | |
| 3544 | pool->literals[entry] = inst.relocs[0].exp; |
| 3545 | pool->literals[entry].X_op = O_constant; |
| 3546 | pool->literals[entry].X_add_number = 0; |
| 3547 | pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4; |
| 3548 | pool->next_free_entry += 1; |
| 3549 | pool_size += 4; |
| 3550 | } |
| 3551 | else if ((entry + 1) >= MAX_LITERAL_POOL_SIZE) |
| 3552 | { |
| 3553 | inst.error = _("literal pool overflow"); |
| 3554 | return FAIL; |
| 3555 | } |
| 3556 | |
| 3557 | pool->literals[entry] = inst.relocs[0].exp; |
| 3558 | pool->literals[entry].X_op = O_constant; |
| 3559 | pool->literals[entry].X_add_number = imm1; |
| 3560 | pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned; |
| 3561 | pool->literals[entry++].X_md = 4; |
| 3562 | pool->literals[entry] = inst.relocs[0].exp; |
| 3563 | pool->literals[entry].X_op = O_constant; |
| 3564 | pool->literals[entry].X_add_number = imm2; |
| 3565 | pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned; |
| 3566 | pool->literals[entry].X_md = 4; |
| 3567 | pool->alignment = 3; |
| 3568 | pool->next_free_entry += 1; |
| 3569 | } |
| 3570 | else |
| 3571 | { |
| 3572 | pool->literals[entry] = inst.relocs[0].exp; |
| 3573 | pool->literals[entry].X_md = 4; |
| 3574 | } |
| 3575 | |
| 3576 | #ifdef OBJ_ELF |
| 3577 | /* PR ld/12974: Record the location of the first source line to reference |
| 3578 | this entry in the literal pool. If it turns out during linking that the |
| 3579 | symbol does not exist we will be able to give an accurate line number for |
| 3580 | the (first use of the) missing reference. */ |
| 3581 | if (debug_type == DEBUG_DWARF2) |
| 3582 | dwarf2_where (pool->locs + entry); |
| 3583 | #endif |
| 3584 | pool->next_free_entry += 1; |
| 3585 | } |
| 3586 | else if (padding_slot_p) |
| 3587 | { |
| 3588 | pool->literals[entry] = inst.relocs[0].exp; |
| 3589 | pool->literals[entry].X_md = nbytes; |
| 3590 | } |
| 3591 | |
| 3592 | inst.relocs[0].exp.X_op = O_symbol; |
| 3593 | inst.relocs[0].exp.X_add_number = pool_size; |
| 3594 | inst.relocs[0].exp.X_add_symbol = pool->symbol; |
| 3595 | |
| 3596 | return SUCCESS; |
| 3597 | } |
| 3598 | |
| 3599 | bfd_boolean |
| 3600 | tc_start_label_without_colon (void) |
| 3601 | { |
| 3602 | bfd_boolean ret = TRUE; |
| 3603 | |
| 3604 | if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME) |
| 3605 | { |
| 3606 | const char *label = input_line_pointer; |
| 3607 | |
| 3608 | while (!is_end_of_line[(int) label[-1]]) |
| 3609 | --label; |
| 3610 | |
| 3611 | if (*label == '.') |
| 3612 | { |
| 3613 | as_bad (_("Invalid label '%s'"), label); |
| 3614 | ret = FALSE; |
| 3615 | } |
| 3616 | |
| 3617 | asmfunc_debug (label); |
| 3618 | |
| 3619 | asmfunc_state = WAITING_ENDASMFUNC; |
| 3620 | } |
| 3621 | |
| 3622 | return ret; |
| 3623 | } |
| 3624 | |
| 3625 | /* Can't use symbol_new here, so have to create a symbol and then at |
| 3626 | a later date assign it a value. That's what these functions do. */ |
| 3627 | |
| 3628 | static void |
| 3629 | symbol_locate (symbolS * symbolP, |
| 3630 | const char * name, /* It is copied, the caller can modify. */ |
| 3631 | segT segment, /* Segment identifier (SEG_<something>). */ |
| 3632 | valueT valu, /* Symbol value. */ |
| 3633 | fragS * frag) /* Associated fragment. */ |
| 3634 | { |
| 3635 | size_t name_length; |
| 3636 | char * preserved_copy_of_name; |
| 3637 | |
| 3638 | name_length = strlen (name) + 1; /* +1 for \0. */ |
| 3639 | obstack_grow (¬es, name, name_length); |
| 3640 | preserved_copy_of_name = (char *) obstack_finish (¬es); |
| 3641 | |
| 3642 | #ifdef tc_canonicalize_symbol_name |
| 3643 | preserved_copy_of_name = |
| 3644 | tc_canonicalize_symbol_name (preserved_copy_of_name); |
| 3645 | #endif |
| 3646 | |
| 3647 | S_SET_NAME (symbolP, preserved_copy_of_name); |
| 3648 | |
| 3649 | S_SET_SEGMENT (symbolP, segment); |
| 3650 | S_SET_VALUE (symbolP, valu); |
| 3651 | symbol_clear_list_pointers (symbolP); |
| 3652 | |
| 3653 | symbol_set_frag (symbolP, frag); |
| 3654 | |
| 3655 | /* Link to end of symbol chain. */ |
| 3656 | { |
| 3657 | extern int symbol_table_frozen; |
| 3658 | |
| 3659 | if (symbol_table_frozen) |
| 3660 | abort (); |
| 3661 | } |
| 3662 | |
| 3663 | symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); |
| 3664 | |
| 3665 | obj_symbol_new_hook (symbolP); |
| 3666 | |
| 3667 | #ifdef tc_symbol_new_hook |
| 3668 | tc_symbol_new_hook (symbolP); |
| 3669 | #endif |
| 3670 | |
| 3671 | #ifdef DEBUG_SYMS |
| 3672 | verify_symbol_chain (symbol_rootP, symbol_lastP); |
| 3673 | #endif /* DEBUG_SYMS */ |
| 3674 | } |
| 3675 | |
| 3676 | static void |
| 3677 | s_ltorg (int ignored ATTRIBUTE_UNUSED) |
| 3678 | { |
| 3679 | unsigned int entry; |
| 3680 | literal_pool * pool; |
| 3681 | char sym_name[20]; |
| 3682 | |
| 3683 | pool = find_literal_pool (); |
| 3684 | if (pool == NULL |
| 3685 | || pool->symbol == NULL |
| 3686 | || pool->next_free_entry == 0) |
| 3687 | return; |
| 3688 | |
| 3689 | /* Align pool as you have word accesses. |
| 3690 | Only make a frag if we have to. */ |
| 3691 | if (!need_pass_2) |
| 3692 | frag_align (pool->alignment, 0, 0); |
| 3693 | |
| 3694 | record_alignment (now_seg, 2); |
| 3695 | |
| 3696 | #ifdef OBJ_ELF |
| 3697 | seg_info (now_seg)->tc_segment_info_data.mapstate = MAP_DATA; |
| 3698 | make_mapping_symbol (MAP_DATA, (valueT) frag_now_fix (), frag_now); |
| 3699 | #endif |
| 3700 | sprintf (sym_name, "$$lit_\002%x", pool->id); |
| 3701 | |
| 3702 | symbol_locate (pool->symbol, sym_name, now_seg, |
| 3703 | (valueT) frag_now_fix (), frag_now); |
| 3704 | symbol_table_insert (pool->symbol); |
| 3705 | |
| 3706 | ARM_SET_THUMB (pool->symbol, thumb_mode); |
| 3707 | |
| 3708 | #if defined OBJ_COFF || defined OBJ_ELF |
| 3709 | ARM_SET_INTERWORK (pool->symbol, support_interwork); |
| 3710 | #endif |
| 3711 | |
| 3712 | for (entry = 0; entry < pool->next_free_entry; entry ++) |
| 3713 | { |
| 3714 | #ifdef OBJ_ELF |
| 3715 | if (debug_type == DEBUG_DWARF2) |
| 3716 | dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry); |
| 3717 | #endif |
| 3718 | /* First output the expression in the instruction to the pool. */ |
| 3719 | emit_expr (&(pool->literals[entry]), |
| 3720 | pool->literals[entry].X_md & LIT_ENTRY_SIZE_MASK); |
| 3721 | } |
| 3722 | |
| 3723 | /* Mark the pool as empty. */ |
| 3724 | pool->next_free_entry = 0; |
| 3725 | pool->symbol = NULL; |
| 3726 | } |
| 3727 | |
| 3728 | #ifdef OBJ_ELF |
| 3729 | /* Forward declarations for functions below, in the MD interface |
| 3730 | section. */ |
| 3731 | static void fix_new_arm (fragS *, int, short, expressionS *, int, int); |
| 3732 | static valueT create_unwind_entry (int); |
| 3733 | static void start_unwind_section (const segT, int); |
| 3734 | static void add_unwind_opcode (valueT, int); |
| 3735 | static void flush_pending_unwind (void); |
| 3736 | |
| 3737 | /* Directives: Data. */ |
| 3738 | |
| 3739 | static void |
| 3740 | s_arm_elf_cons (int nbytes) |
| 3741 | { |
| 3742 | expressionS exp; |
| 3743 | |
| 3744 | #ifdef md_flush_pending_output |
| 3745 | md_flush_pending_output (); |
| 3746 | #endif |
| 3747 | |
| 3748 | if (is_it_end_of_statement ()) |
| 3749 | { |
| 3750 | demand_empty_rest_of_line (); |
| 3751 | return; |
| 3752 | } |
| 3753 | |
| 3754 | #ifdef md_cons_align |
| 3755 | md_cons_align (nbytes); |
| 3756 | #endif |
| 3757 | |
| 3758 | mapping_state (MAP_DATA); |
| 3759 | do |
| 3760 | { |
| 3761 | int reloc; |
| 3762 | char *base = input_line_pointer; |
| 3763 | |
| 3764 | expression (& exp); |
| 3765 | |
| 3766 | if (exp.X_op != O_symbol) |
| 3767 | emit_expr (&exp, (unsigned int) nbytes); |
| 3768 | else |
| 3769 | { |
| 3770 | char *before_reloc = input_line_pointer; |
| 3771 | reloc = parse_reloc (&input_line_pointer); |
| 3772 | if (reloc == -1) |
| 3773 | { |
| 3774 | as_bad (_("unrecognized relocation suffix")); |
| 3775 | ignore_rest_of_line (); |
| 3776 | return; |
| 3777 | } |
| 3778 | else if (reloc == BFD_RELOC_UNUSED) |
| 3779 | emit_expr (&exp, (unsigned int) nbytes); |
| 3780 | else |
| 3781 | { |
| 3782 | reloc_howto_type *howto = (reloc_howto_type *) |
| 3783 | bfd_reloc_type_lookup (stdoutput, |
| 3784 | (bfd_reloc_code_real_type) reloc); |
| 3785 | int size = bfd_get_reloc_size (howto); |
| 3786 | |
| 3787 | if (reloc == BFD_RELOC_ARM_PLT32) |
| 3788 | { |
| 3789 | as_bad (_("(plt) is only valid on branch targets")); |
| 3790 | reloc = BFD_RELOC_UNUSED; |
| 3791 | size = 0; |
| 3792 | } |
| 3793 | |
| 3794 | if (size > nbytes) |
| 3795 | as_bad (ngettext ("%s relocations do not fit in %d byte", |
| 3796 | "%s relocations do not fit in %d bytes", |
| 3797 | nbytes), |
| 3798 | howto->name, nbytes); |
| 3799 | else |
| 3800 | { |
| 3801 | /* We've parsed an expression stopping at O_symbol. |
| 3802 | But there may be more expression left now that we |
| 3803 | have parsed the relocation marker. Parse it again. |
| 3804 | XXX Surely there is a cleaner way to do this. */ |
| 3805 | char *p = input_line_pointer; |
| 3806 | int offset; |
| 3807 | char *save_buf = XNEWVEC (char, input_line_pointer - base); |
| 3808 | |
| 3809 | memcpy (save_buf, base, input_line_pointer - base); |
| 3810 | memmove (base + (input_line_pointer - before_reloc), |
| 3811 | base, before_reloc - base); |
| 3812 | |
| 3813 | input_line_pointer = base + (input_line_pointer-before_reloc); |
| 3814 | expression (&exp); |
| 3815 | memcpy (base, save_buf, p - base); |
| 3816 | |
| 3817 | offset = nbytes - size; |
| 3818 | p = frag_more (nbytes); |
| 3819 | memset (p, 0, nbytes); |
| 3820 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, |
| 3821 | size, &exp, 0, (enum bfd_reloc_code_real) reloc); |
| 3822 | free (save_buf); |
| 3823 | } |
| 3824 | } |
| 3825 | } |
| 3826 | } |
| 3827 | while (*input_line_pointer++ == ','); |
| 3828 | |
| 3829 | /* Put terminator back into stream. */ |
| 3830 | input_line_pointer --; |
| 3831 | demand_empty_rest_of_line (); |
| 3832 | } |
| 3833 | |
| 3834 | /* Emit an expression containing a 32-bit thumb instruction. |
| 3835 | Implementation based on put_thumb32_insn. */ |
| 3836 | |
| 3837 | static void |
| 3838 | emit_thumb32_expr (expressionS * exp) |
| 3839 | { |
| 3840 | expressionS exp_high = *exp; |
| 3841 | |
| 3842 | exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16; |
| 3843 | emit_expr (& exp_high, (unsigned int) THUMB_SIZE); |
| 3844 | exp->X_add_number &= 0xffff; |
| 3845 | emit_expr (exp, (unsigned int) THUMB_SIZE); |
| 3846 | } |
| 3847 | |
| 3848 | /* Guess the instruction size based on the opcode. */ |
| 3849 | |
| 3850 | static int |
| 3851 | thumb_insn_size (int opcode) |
| 3852 | { |
| 3853 | if ((unsigned int) opcode < 0xe800u) |
| 3854 | return 2; |
| 3855 | else if ((unsigned int) opcode >= 0xe8000000u) |
| 3856 | return 4; |
| 3857 | else |
| 3858 | return 0; |
| 3859 | } |
| 3860 | |
| 3861 | static bfd_boolean |
| 3862 | emit_insn (expressionS *exp, int nbytes) |
| 3863 | { |
| 3864 | int size = 0; |
| 3865 | |
| 3866 | if (exp->X_op == O_constant) |
| 3867 | { |
| 3868 | size = nbytes; |
| 3869 | |
| 3870 | if (size == 0) |
| 3871 | size = thumb_insn_size (exp->X_add_number); |
| 3872 | |
| 3873 | if (size != 0) |
| 3874 | { |
| 3875 | if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu) |
| 3876 | { |
| 3877 | as_bad (_(".inst.n operand too big. "\ |
| 3878 | "Use .inst.w instead")); |
| 3879 | size = 0; |
| 3880 | } |
| 3881 | else |
| 3882 | { |
| 3883 | if (now_pred.state == AUTOMATIC_PRED_BLOCK) |
| 3884 | set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN, 0); |
| 3885 | else |
| 3886 | set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN, 0); |
| 3887 | |
| 3888 | if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian) |
| 3889 | emit_thumb32_expr (exp); |
| 3890 | else |
| 3891 | emit_expr (exp, (unsigned int) size); |
| 3892 | |
| 3893 | it_fsm_post_encode (); |
| 3894 | } |
| 3895 | } |
| 3896 | else |
| 3897 | as_bad (_("cannot determine Thumb instruction size. " \ |
| 3898 | "Use .inst.n/.inst.w instead")); |
| 3899 | } |
| 3900 | else |
| 3901 | as_bad (_("constant expression required")); |
| 3902 | |
| 3903 | return (size != 0); |
| 3904 | } |
| 3905 | |
| 3906 | /* Like s_arm_elf_cons but do not use md_cons_align and |
| 3907 | set the mapping state to MAP_ARM/MAP_THUMB. */ |
| 3908 | |
| 3909 | static void |
| 3910 | s_arm_elf_inst (int nbytes) |
| 3911 | { |
| 3912 | if (is_it_end_of_statement ()) |
| 3913 | { |
| 3914 | demand_empty_rest_of_line (); |
| 3915 | return; |
| 3916 | } |
| 3917 | |
| 3918 | /* Calling mapping_state () here will not change ARM/THUMB, |
| 3919 | but will ensure not to be in DATA state. */ |
| 3920 | |
| 3921 | if (thumb_mode) |
| 3922 | mapping_state (MAP_THUMB); |
| 3923 | else |
| 3924 | { |
| 3925 | if (nbytes != 0) |
| 3926 | { |
| 3927 | as_bad (_("width suffixes are invalid in ARM mode")); |
| 3928 | ignore_rest_of_line (); |
| 3929 | return; |
| 3930 | } |
| 3931 | |
| 3932 | nbytes = 4; |
| 3933 | |
| 3934 | mapping_state (MAP_ARM); |
| 3935 | } |
| 3936 | |
| 3937 | do |
| 3938 | { |
| 3939 | expressionS exp; |
| 3940 | |
| 3941 | expression (& exp); |
| 3942 | |
| 3943 | if (! emit_insn (& exp, nbytes)) |
| 3944 | { |
| 3945 | ignore_rest_of_line (); |
| 3946 | return; |
| 3947 | } |
| 3948 | } |
| 3949 | while (*input_line_pointer++ == ','); |
| 3950 | |
| 3951 | /* Put terminator back into stream. */ |
| 3952 | input_line_pointer --; |
| 3953 | demand_empty_rest_of_line (); |
| 3954 | } |
| 3955 | |
| 3956 | /* Parse a .rel31 directive. */ |
| 3957 | |
| 3958 | static void |
| 3959 | s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) |
| 3960 | { |
| 3961 | expressionS exp; |
| 3962 | char *p; |
| 3963 | valueT highbit; |
| 3964 | |
| 3965 | highbit = 0; |
| 3966 | if (*input_line_pointer == '1') |
| 3967 | highbit = 0x80000000; |
| 3968 | else if (*input_line_pointer != '0') |
| 3969 | as_bad (_("expected 0 or 1")); |
| 3970 | |
| 3971 | input_line_pointer++; |
| 3972 | if (*input_line_pointer != ',') |
| 3973 | as_bad (_("missing comma")); |
| 3974 | input_line_pointer++; |
| 3975 | |
| 3976 | #ifdef md_flush_pending_output |
| 3977 | md_flush_pending_output (); |
| 3978 | #endif |
| 3979 | |
| 3980 | #ifdef md_cons_align |
| 3981 | md_cons_align (4); |
| 3982 | #endif |
| 3983 | |
| 3984 | mapping_state (MAP_DATA); |
| 3985 | |
| 3986 | expression (&exp); |
| 3987 | |
| 3988 | p = frag_more (4); |
| 3989 | md_number_to_chars (p, highbit, 4); |
| 3990 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, |
| 3991 | BFD_RELOC_ARM_PREL31); |
| 3992 | |
| 3993 | demand_empty_rest_of_line (); |
| 3994 | } |
| 3995 | |
| 3996 | /* Directives: AEABI stack-unwind tables. */ |
| 3997 | |
| 3998 | /* Parse an unwind_fnstart directive. Simply records the current location. */ |
| 3999 | |
| 4000 | static void |
| 4001 | s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) |
| 4002 | { |
| 4003 | demand_empty_rest_of_line (); |
| 4004 | if (unwind.proc_start) |
| 4005 | { |
| 4006 | as_bad (_("duplicate .fnstart directive")); |
| 4007 | return; |
| 4008 | } |
| 4009 | |
| 4010 | /* Mark the start of the function. */ |
| 4011 | unwind.proc_start = expr_build_dot (); |
| 4012 | |
| 4013 | /* Reset the rest of the unwind info. */ |
| 4014 | unwind.opcode_count = 0; |
| 4015 | unwind.table_entry = NULL; |
| 4016 | unwind.personality_routine = NULL; |
| 4017 | unwind.personality_index = -1; |
| 4018 | unwind.frame_size = 0; |
| 4019 | unwind.fp_offset = 0; |
| 4020 | unwind.fp_reg = REG_SP; |
| 4021 | unwind.fp_used = 0; |
| 4022 | unwind.sp_restored = 0; |
| 4023 | } |
| 4024 | |
| 4025 | |
| 4026 | /* Parse a handlerdata directive. Creates the exception handling table entry |
| 4027 | for the function. */ |
| 4028 | |
| 4029 | static void |
| 4030 | s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) |
| 4031 | { |
| 4032 | demand_empty_rest_of_line (); |
| 4033 | if (!unwind.proc_start) |
| 4034 | as_bad (MISSING_FNSTART); |
| 4035 | |
| 4036 | if (unwind.table_entry) |
| 4037 | as_bad (_("duplicate .handlerdata directive")); |
| 4038 | |
| 4039 | create_unwind_entry (1); |
| 4040 | } |
| 4041 | |
| 4042 | /* Parse an unwind_fnend directive. Generates the index table entry. */ |
| 4043 | |
| 4044 | static void |
| 4045 | s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) |
| 4046 | { |
| 4047 | long where; |
| 4048 | char *ptr; |
| 4049 | valueT val; |
| 4050 | unsigned int marked_pr_dependency; |
| 4051 | |
| 4052 | demand_empty_rest_of_line (); |
| 4053 | |
| 4054 | if (!unwind.proc_start) |
| 4055 | { |
| 4056 | as_bad (_(".fnend directive without .fnstart")); |
| 4057 | return; |
| 4058 | } |
| 4059 | |
| 4060 | /* Add eh table entry. */ |
| 4061 | if (unwind.table_entry == NULL) |
| 4062 | val = create_unwind_entry (0); |
| 4063 | else |
| 4064 | val = 0; |
| 4065 | |
| 4066 | /* Add index table entry. This is two words. */ |
| 4067 | start_unwind_section (unwind.saved_seg, 1); |
| 4068 | frag_align (2, 0, 0); |
| 4069 | record_alignment (now_seg, 2); |
| 4070 | |
| 4071 | ptr = frag_more (8); |
| 4072 | memset (ptr, 0, 8); |
| 4073 | where = frag_now_fix () - 8; |
| 4074 | |
| 4075 | /* Self relative offset of the function start. */ |
| 4076 | fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, |
| 4077 | BFD_RELOC_ARM_PREL31); |
| 4078 | |
| 4079 | /* Indicate dependency on EHABI-defined personality routines to the |
| 4080 | linker, if it hasn't been done already. */ |
| 4081 | marked_pr_dependency |
| 4082 | = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency; |
| 4083 | if (unwind.personality_index >= 0 && unwind.personality_index < 3 |
| 4084 | && !(marked_pr_dependency & (1 << unwind.personality_index))) |
| 4085 | { |
| 4086 | static const char *const name[] = |
| 4087 | { |
| 4088 | "__aeabi_unwind_cpp_pr0", |
| 4089 | "__aeabi_unwind_cpp_pr1", |
| 4090 | "__aeabi_unwind_cpp_pr2" |
| 4091 | }; |
| 4092 | symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); |
| 4093 | fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); |
| 4094 | seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency |
| 4095 | |= 1 << unwind.personality_index; |
| 4096 | } |
| 4097 | |
| 4098 | if (val) |
| 4099 | /* Inline exception table entry. */ |
| 4100 | md_number_to_chars (ptr + 4, val, 4); |
| 4101 | else |
| 4102 | /* Self relative offset of the table entry. */ |
| 4103 | fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, |
| 4104 | BFD_RELOC_ARM_PREL31); |
| 4105 | |
| 4106 | /* Restore the original section. */ |
| 4107 | subseg_set (unwind.saved_seg, unwind.saved_subseg); |
| 4108 | |
| 4109 | unwind.proc_start = NULL; |
| 4110 | } |
| 4111 | |
| 4112 | |
| 4113 | /* Parse an unwind_cantunwind directive. */ |
| 4114 | |
| 4115 | static void |
| 4116 | s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) |
| 4117 | { |
| 4118 | demand_empty_rest_of_line (); |
| 4119 | if (!unwind.proc_start) |
| 4120 | as_bad (MISSING_FNSTART); |
| 4121 | |
| 4122 | if (unwind.personality_routine || unwind.personality_index != -1) |
| 4123 | as_bad (_("personality routine specified for cantunwind frame")); |
| 4124 | |
| 4125 | unwind.personality_index = -2; |
| 4126 | } |
| 4127 | |
| 4128 | |
| 4129 | /* Parse a personalityindex directive. */ |
| 4130 | |
| 4131 | static void |
| 4132 | s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) |
| 4133 | { |
| 4134 | expressionS exp; |
| 4135 | |
| 4136 | if (!unwind.proc_start) |
| 4137 | as_bad (MISSING_FNSTART); |
| 4138 | |
| 4139 | if (unwind.personality_routine || unwind.personality_index != -1) |
| 4140 | as_bad (_("duplicate .personalityindex directive")); |
| 4141 | |
| 4142 | expression (&exp); |
| 4143 | |
| 4144 | if (exp.X_op != O_constant |
| 4145 | || exp.X_add_number < 0 || exp.X_add_number > 15) |
| 4146 | { |
| 4147 | as_bad (_("bad personality routine number")); |
| 4148 | ignore_rest_of_line (); |
| 4149 | return; |
| 4150 | } |
| 4151 | |
| 4152 | unwind.personality_index = exp.X_add_number; |
| 4153 | |
| 4154 | demand_empty_rest_of_line (); |
| 4155 | } |
| 4156 | |
| 4157 | |
| 4158 | /* Parse a personality directive. */ |
| 4159 | |
| 4160 | static void |
| 4161 | s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) |
| 4162 | { |
| 4163 | char *name, *p, c; |
| 4164 | |
| 4165 | if (!unwind.proc_start) |
| 4166 | as_bad (MISSING_FNSTART); |
| 4167 | |
| 4168 | if (unwind.personality_routine || unwind.personality_index != -1) |
| 4169 | as_bad (_("duplicate .personality directive")); |
| 4170 | |
| 4171 | c = get_symbol_name (& name); |
| 4172 | p = input_line_pointer; |
| 4173 | if (c == '"') |
| 4174 | ++ input_line_pointer; |
| 4175 | unwind.personality_routine = symbol_find_or_make (name); |
| 4176 | *p = c; |
| 4177 | demand_empty_rest_of_line (); |
| 4178 | } |
| 4179 | |
| 4180 | |
| 4181 | /* Parse a directive saving core registers. */ |
| 4182 | |
| 4183 | static void |
| 4184 | s_arm_unwind_save_core (void) |
| 4185 | { |
| 4186 | valueT op; |
| 4187 | long range; |
| 4188 | int n; |
| 4189 | |
| 4190 | range = parse_reg_list (&input_line_pointer, REGLIST_RN); |
| 4191 | if (range == FAIL) |
| 4192 | { |
| 4193 | as_bad (_("expected register list")); |
| 4194 | ignore_rest_of_line (); |
| 4195 | return; |
| 4196 | } |
| 4197 | |
| 4198 | demand_empty_rest_of_line (); |
| 4199 | |
| 4200 | /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} |
| 4201 | into .unwind_save {..., sp...}. We aren't bothered about the value of |
| 4202 | ip because it is clobbered by calls. */ |
| 4203 | if (unwind.sp_restored && unwind.fp_reg == 12 |
| 4204 | && (range & 0x3000) == 0x1000) |
| 4205 | { |
| 4206 | unwind.opcode_count--; |
| 4207 | unwind.sp_restored = 0; |
| 4208 | range = (range | 0x2000) & ~0x1000; |
| 4209 | unwind.pending_offset = 0; |
| 4210 | } |
| 4211 | |
| 4212 | /* Pop r4-r15. */ |
| 4213 | if (range & 0xfff0) |
| 4214 | { |
| 4215 | /* See if we can use the short opcodes. These pop a block of up to 8 |
| 4216 | registers starting with r4, plus maybe r14. */ |
| 4217 | for (n = 0; n < 8; n++) |
| 4218 | { |
| 4219 | /* Break at the first non-saved register. */ |
| 4220 | if ((range & (1 << (n + 4))) == 0) |
| 4221 | break; |
| 4222 | } |
| 4223 | /* See if there are any other bits set. */ |
| 4224 | if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) |
| 4225 | { |
| 4226 | /* Use the long form. */ |
| 4227 | op = 0x8000 | ((range >> 4) & 0xfff); |
| 4228 | add_unwind_opcode (op, 2); |
| 4229 | } |
| 4230 | else |
| 4231 | { |
| 4232 | /* Use the short form. */ |
| 4233 | if (range & 0x4000) |
| 4234 | op = 0xa8; /* Pop r14. */ |
| 4235 | else |
| 4236 | op = 0xa0; /* Do not pop r14. */ |
| 4237 | op |= (n - 1); |
| 4238 | add_unwind_opcode (op, 1); |
| 4239 | } |
| 4240 | } |
| 4241 | |
| 4242 | /* Pop r0-r3. */ |
| 4243 | if (range & 0xf) |
| 4244 | { |
| 4245 | op = 0xb100 | (range & 0xf); |
| 4246 | add_unwind_opcode (op, 2); |
| 4247 | } |
| 4248 | |
| 4249 | /* Record the number of bytes pushed. */ |
| 4250 | for (n = 0; n < 16; n++) |
| 4251 | { |
| 4252 | if (range & (1 << n)) |
| 4253 | unwind.frame_size += 4; |
| 4254 | } |
| 4255 | } |
| 4256 | |
| 4257 | |
| 4258 | /* Parse a directive saving FPA registers. */ |
| 4259 | |
| 4260 | static void |
| 4261 | s_arm_unwind_save_fpa (int reg) |
| 4262 | { |
| 4263 | expressionS exp; |
| 4264 | int num_regs; |
| 4265 | valueT op; |
| 4266 | |
| 4267 | /* Get Number of registers to transfer. */ |
| 4268 | if (skip_past_comma (&input_line_pointer) != FAIL) |
| 4269 | expression (&exp); |
| 4270 | else |
| 4271 | exp.X_op = O_illegal; |
| 4272 | |
| 4273 | if (exp.X_op != O_constant) |
| 4274 | { |
| 4275 | as_bad (_("expected , <constant>")); |
| 4276 | ignore_rest_of_line (); |
| 4277 | return; |
| 4278 | } |
| 4279 | |
| 4280 | num_regs = exp.X_add_number; |
| 4281 | |
| 4282 | if (num_regs < 1 || num_regs > 4) |
| 4283 | { |
| 4284 | as_bad (_("number of registers must be in the range [1:4]")); |
| 4285 | ignore_rest_of_line (); |
| 4286 | return; |
| 4287 | } |
| 4288 | |
| 4289 | demand_empty_rest_of_line (); |
| 4290 | |
| 4291 | if (reg == 4) |
| 4292 | { |
| 4293 | /* Short form. */ |
| 4294 | op = 0xb4 | (num_regs - 1); |
| 4295 | add_unwind_opcode (op, 1); |
| 4296 | } |
| 4297 | else |
| 4298 | { |
| 4299 | /* Long form. */ |
| 4300 | op = 0xc800 | (reg << 4) | (num_regs - 1); |
| 4301 | add_unwind_opcode (op, 2); |
| 4302 | } |
| 4303 | unwind.frame_size += num_regs * 12; |
| 4304 | } |
| 4305 | |
| 4306 | |
| 4307 | /* Parse a directive saving VFP registers for ARMv6 and above. */ |
| 4308 | |
| 4309 | static void |
| 4310 | s_arm_unwind_save_vfp_armv6 (void) |
| 4311 | { |
| 4312 | int count; |
| 4313 | unsigned int start; |
| 4314 | valueT op; |
| 4315 | int num_vfpv3_regs = 0; |
| 4316 | int num_regs_below_16; |
| 4317 | bfd_boolean partial_match; |
| 4318 | |
| 4319 | count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D, |
| 4320 | &partial_match); |
| 4321 | if (count == FAIL) |
| 4322 | { |
| 4323 | as_bad (_("expected register list")); |
| 4324 | ignore_rest_of_line (); |
| 4325 | return; |
| 4326 | } |
| 4327 | |
| 4328 | demand_empty_rest_of_line (); |
| 4329 | |
| 4330 | /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather |
| 4331 | than FSTMX/FLDMX-style ones). */ |
| 4332 | |
| 4333 | /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ |
| 4334 | if (start >= 16) |
| 4335 | num_vfpv3_regs = count; |
| 4336 | else if (start + count > 16) |
| 4337 | num_vfpv3_regs = start + count - 16; |
| 4338 | |
| 4339 | if (num_vfpv3_regs > 0) |
| 4340 | { |
| 4341 | int start_offset = start > 16 ? start - 16 : 0; |
| 4342 | op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); |
| 4343 | add_unwind_opcode (op, 2); |
| 4344 | } |
| 4345 | |
| 4346 | /* Generate opcode for registers numbered in the range 0 .. 15. */ |
| 4347 | num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; |
| 4348 | gas_assert (num_regs_below_16 + num_vfpv3_regs == count); |
| 4349 | if (num_regs_below_16 > 0) |
| 4350 | { |
| 4351 | op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); |
| 4352 | add_unwind_opcode (op, 2); |
| 4353 | } |
| 4354 | |
| 4355 | unwind.frame_size += count * 8; |
| 4356 | } |
| 4357 | |
| 4358 | |
| 4359 | /* Parse a directive saving VFP registers for pre-ARMv6. */ |
| 4360 | |
| 4361 | static void |
| 4362 | s_arm_unwind_save_vfp (void) |
| 4363 | { |
| 4364 | int count; |
| 4365 | unsigned int reg; |
| 4366 | valueT op; |
| 4367 | bfd_boolean partial_match; |
| 4368 | |
| 4369 | count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D, |
| 4370 | &partial_match); |
| 4371 | if (count == FAIL) |
| 4372 | { |
| 4373 | as_bad (_("expected register list")); |
| 4374 | ignore_rest_of_line (); |
| 4375 | return; |
| 4376 | } |
| 4377 | |
| 4378 | demand_empty_rest_of_line (); |
| 4379 | |
| 4380 | if (reg == 8) |
| 4381 | { |
| 4382 | /* Short form. */ |
| 4383 | op = 0xb8 | (count - 1); |
| 4384 | add_unwind_opcode (op, 1); |
| 4385 | } |
| 4386 | else |
| 4387 | { |
| 4388 | /* Long form. */ |
| 4389 | op = 0xb300 | (reg << 4) | (count - 1); |
| 4390 | add_unwind_opcode (op, 2); |
| 4391 | } |
| 4392 | unwind.frame_size += count * 8 + 4; |
| 4393 | } |
| 4394 | |
| 4395 | |
| 4396 | /* Parse a directive saving iWMMXt data registers. */ |
| 4397 | |
| 4398 | static void |
| 4399 | s_arm_unwind_save_mmxwr (void) |
| 4400 | { |
| 4401 | int reg; |
| 4402 | int hi_reg; |
| 4403 | int i; |
| 4404 | unsigned mask = 0; |
| 4405 | valueT op; |
| 4406 | |
| 4407 | if (*input_line_pointer == '{') |
| 4408 | input_line_pointer++; |
| 4409 | |
| 4410 | do |
| 4411 | { |
| 4412 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
| 4413 | |
| 4414 | if (reg == FAIL) |
| 4415 | { |
| 4416 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
| 4417 | goto error; |
| 4418 | } |
| 4419 | |
| 4420 | if (mask >> reg) |
| 4421 | as_tsktsk (_("register list not in ascending order")); |
| 4422 | mask |= 1 << reg; |
| 4423 | |
| 4424 | if (*input_line_pointer == '-') |
| 4425 | { |
| 4426 | input_line_pointer++; |
| 4427 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
| 4428 | if (hi_reg == FAIL) |
| 4429 | { |
| 4430 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
| 4431 | goto error; |
| 4432 | } |
| 4433 | else if (reg >= hi_reg) |
| 4434 | { |
| 4435 | as_bad (_("bad register range")); |
| 4436 | goto error; |
| 4437 | } |
| 4438 | for (; reg < hi_reg; reg++) |
| 4439 | mask |= 1 << reg; |
| 4440 | } |
| 4441 | } |
| 4442 | while (skip_past_comma (&input_line_pointer) != FAIL); |
| 4443 | |
| 4444 | skip_past_char (&input_line_pointer, '}'); |
| 4445 | |
| 4446 | demand_empty_rest_of_line (); |
| 4447 | |
| 4448 | /* Generate any deferred opcodes because we're going to be looking at |
| 4449 | the list. */ |
| 4450 | flush_pending_unwind (); |
| 4451 | |
| 4452 | for (i = 0; i < 16; i++) |
| 4453 | { |
| 4454 | if (mask & (1 << i)) |
| 4455 | unwind.frame_size += 8; |
| 4456 | } |
| 4457 | |
| 4458 | /* Attempt to combine with a previous opcode. We do this because gcc |
| 4459 | likes to output separate unwind directives for a single block of |
| 4460 | registers. */ |
| 4461 | if (unwind.opcode_count > 0) |
| 4462 | { |
| 4463 | i = unwind.opcodes[unwind.opcode_count - 1]; |
| 4464 | if ((i & 0xf8) == 0xc0) |
| 4465 | { |
| 4466 | i &= 7; |
| 4467 | /* Only merge if the blocks are contiguous. */ |
| 4468 | if (i < 6) |
| 4469 | { |
| 4470 | if ((mask & 0xfe00) == (1 << 9)) |
| 4471 | { |
| 4472 | mask |= ((1 << (i + 11)) - 1) & 0xfc00; |
| 4473 | unwind.opcode_count--; |
| 4474 | } |
| 4475 | } |
| 4476 | else if (i == 6 && unwind.opcode_count >= 2) |
| 4477 | { |
| 4478 | i = unwind.opcodes[unwind.opcode_count - 2]; |
| 4479 | reg = i >> 4; |
| 4480 | i &= 0xf; |
| 4481 | |
| 4482 | op = 0xffff << (reg - 1); |
| 4483 | if (reg > 0 |
| 4484 | && ((mask & op) == (1u << (reg - 1)))) |
| 4485 | { |
| 4486 | op = (1 << (reg + i + 1)) - 1; |
| 4487 | op &= ~((1 << reg) - 1); |
| 4488 | mask |= op; |
| 4489 | unwind.opcode_count -= 2; |
| 4490 | } |
| 4491 | } |
| 4492 | } |
| 4493 | } |
| 4494 | |
| 4495 | hi_reg = 15; |
| 4496 | /* We want to generate opcodes in the order the registers have been |
| 4497 | saved, ie. descending order. */ |
| 4498 | for (reg = 15; reg >= -1; reg--) |
| 4499 | { |
| 4500 | /* Save registers in blocks. */ |
| 4501 | if (reg < 0 |
| 4502 | || !(mask & (1 << reg))) |
| 4503 | { |
| 4504 | /* We found an unsaved reg. Generate opcodes to save the |
| 4505 | preceding block. */ |
| 4506 | if (reg != hi_reg) |
| 4507 | { |
| 4508 | if (reg == 9) |
| 4509 | { |
| 4510 | /* Short form. */ |
| 4511 | op = 0xc0 | (hi_reg - 10); |
| 4512 | add_unwind_opcode (op, 1); |
| 4513 | } |
| 4514 | else |
| 4515 | { |
| 4516 | /* Long form. */ |
| 4517 | op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); |
| 4518 | add_unwind_opcode (op, 2); |
| 4519 | } |
| 4520 | } |
| 4521 | hi_reg = reg - 1; |
| 4522 | } |
| 4523 | } |
| 4524 | |
| 4525 | return; |
| 4526 | error: |
| 4527 | ignore_rest_of_line (); |
| 4528 | } |
| 4529 | |
| 4530 | static void |
| 4531 | s_arm_unwind_save_mmxwcg (void) |
| 4532 | { |
| 4533 | int reg; |
| 4534 | int hi_reg; |
| 4535 | unsigned mask = 0; |
| 4536 | valueT op; |
| 4537 | |
| 4538 | if (*input_line_pointer == '{') |
| 4539 | input_line_pointer++; |
| 4540 | |
| 4541 | skip_whitespace (input_line_pointer); |
| 4542 | |
| 4543 | do |
| 4544 | { |
| 4545 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
| 4546 | |
| 4547 | if (reg == FAIL) |
| 4548 | { |
| 4549 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
| 4550 | goto error; |
| 4551 | } |
| 4552 | |
| 4553 | reg -= 8; |
| 4554 | if (mask >> reg) |
| 4555 | as_tsktsk (_("register list not in ascending order")); |
| 4556 | mask |= 1 << reg; |
| 4557 | |
| 4558 | if (*input_line_pointer == '-') |
| 4559 | { |
| 4560 | input_line_pointer++; |
| 4561 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
| 4562 | if (hi_reg == FAIL) |
| 4563 | { |
| 4564 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
| 4565 | goto error; |
| 4566 | } |
| 4567 | else if (reg >= hi_reg) |
| 4568 | { |
| 4569 | as_bad (_("bad register range")); |
| 4570 | goto error; |
| 4571 | } |
| 4572 | for (; reg < hi_reg; reg++) |
| 4573 | mask |= 1 << reg; |
| 4574 | } |
| 4575 | } |
| 4576 | while (skip_past_comma (&input_line_pointer) != FAIL); |
| 4577 | |
| 4578 | skip_past_char (&input_line_pointer, '}'); |
| 4579 | |
| 4580 | demand_empty_rest_of_line (); |
| 4581 | |
| 4582 | /* Generate any deferred opcodes because we're going to be looking at |
| 4583 | the list. */ |
| 4584 | flush_pending_unwind (); |
| 4585 | |
| 4586 | for (reg = 0; reg < 16; reg++) |
| 4587 | { |
| 4588 | if (mask & (1 << reg)) |
| 4589 | unwind.frame_size += 4; |
| 4590 | } |
| 4591 | op = 0xc700 | mask; |
| 4592 | add_unwind_opcode (op, 2); |
| 4593 | return; |
| 4594 | error: |
| 4595 | ignore_rest_of_line (); |
| 4596 | } |
| 4597 | |
| 4598 | |
| 4599 | /* Parse an unwind_save directive. |
| 4600 | If the argument is non-zero, this is a .vsave directive. */ |
| 4601 | |
| 4602 | static void |
| 4603 | s_arm_unwind_save (int arch_v6) |
| 4604 | { |
| 4605 | char *peek; |
| 4606 | struct reg_entry *reg; |
| 4607 | bfd_boolean had_brace = FALSE; |
| 4608 | |
| 4609 | if (!unwind.proc_start) |
| 4610 | as_bad (MISSING_FNSTART); |
| 4611 | |
| 4612 | /* Figure out what sort of save we have. */ |
| 4613 | peek = input_line_pointer; |
| 4614 | |
| 4615 | if (*peek == '{') |
| 4616 | { |
| 4617 | had_brace = TRUE; |
| 4618 | peek++; |
| 4619 | } |
| 4620 | |
| 4621 | reg = arm_reg_parse_multi (&peek); |
| 4622 | |
| 4623 | if (!reg) |
| 4624 | { |
| 4625 | as_bad (_("register expected")); |
| 4626 | ignore_rest_of_line (); |
| 4627 | return; |
| 4628 | } |
| 4629 | |
| 4630 | switch (reg->type) |
| 4631 | { |
| 4632 | case REG_TYPE_FN: |
| 4633 | if (had_brace) |
| 4634 | { |
| 4635 | as_bad (_("FPA .unwind_save does not take a register list")); |
| 4636 | ignore_rest_of_line (); |
| 4637 | return; |
| 4638 | } |
| 4639 | input_line_pointer = peek; |
| 4640 | s_arm_unwind_save_fpa (reg->number); |
| 4641 | return; |
| 4642 | |
| 4643 | case REG_TYPE_RN: |
| 4644 | s_arm_unwind_save_core (); |
| 4645 | return; |
| 4646 | |
| 4647 | case REG_TYPE_VFD: |
| 4648 | if (arch_v6) |
| 4649 | s_arm_unwind_save_vfp_armv6 (); |
| 4650 | else |
| 4651 | s_arm_unwind_save_vfp (); |
| 4652 | return; |
| 4653 | |
| 4654 | case REG_TYPE_MMXWR: |
| 4655 | s_arm_unwind_save_mmxwr (); |
| 4656 | return; |
| 4657 | |
| 4658 | case REG_TYPE_MMXWCG: |
| 4659 | s_arm_unwind_save_mmxwcg (); |
| 4660 | return; |
| 4661 | |
| 4662 | default: |
| 4663 | as_bad (_(".unwind_save does not support this kind of register")); |
| 4664 | ignore_rest_of_line (); |
| 4665 | } |
| 4666 | } |
| 4667 | |
| 4668 | |
| 4669 | /* Parse an unwind_movsp directive. */ |
| 4670 | |
| 4671 | static void |
| 4672 | s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) |
| 4673 | { |
| 4674 | int reg; |
| 4675 | valueT op; |
| 4676 | int offset; |
| 4677 | |
| 4678 | if (!unwind.proc_start) |
| 4679 | as_bad (MISSING_FNSTART); |
| 4680 | |
| 4681 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
| 4682 | if (reg == FAIL) |
| 4683 | { |
| 4684 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN])); |
| 4685 | ignore_rest_of_line (); |
| 4686 | return; |
| 4687 | } |
| 4688 | |
| 4689 | /* Optional constant. */ |
| 4690 | if (skip_past_comma (&input_line_pointer) != FAIL) |
| 4691 | { |
| 4692 | if (immediate_for_directive (&offset) == FAIL) |
| 4693 | return; |
| 4694 | } |
| 4695 | else |
| 4696 | offset = 0; |
| 4697 | |
| 4698 | demand_empty_rest_of_line (); |
| 4699 | |
| 4700 | if (reg == REG_SP || reg == REG_PC) |
| 4701 | { |
| 4702 | as_bad (_("SP and PC not permitted in .unwind_movsp directive")); |
| 4703 | return; |
| 4704 | } |
| 4705 | |
| 4706 | if (unwind.fp_reg != REG_SP) |
| 4707 | as_bad (_("unexpected .unwind_movsp directive")); |
| 4708 | |
| 4709 | /* Generate opcode to restore the value. */ |
| 4710 | op = 0x90 | reg; |
| 4711 | add_unwind_opcode (op, 1); |
| 4712 | |
| 4713 | /* Record the information for later. */ |
| 4714 | unwind.fp_reg = reg; |
| 4715 | unwind.fp_offset = unwind.frame_size - offset; |
| 4716 | unwind.sp_restored = 1; |
| 4717 | } |
| 4718 | |
| 4719 | /* Parse an unwind_pad directive. */ |
| 4720 | |
| 4721 | static void |
| 4722 | s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) |
| 4723 | { |
| 4724 | int offset; |
| 4725 | |
| 4726 | if (!unwind.proc_start) |
| 4727 | as_bad (MISSING_FNSTART); |
| 4728 | |
| 4729 | if (immediate_for_directive (&offset) == FAIL) |
| 4730 | return; |
| 4731 | |
| 4732 | if (offset & 3) |
| 4733 | { |
| 4734 | as_bad (_("stack increment must be multiple of 4")); |
| 4735 | ignore_rest_of_line (); |
| 4736 | return; |
| 4737 | } |
| 4738 | |
| 4739 | /* Don't generate any opcodes, just record the details for later. */ |
| 4740 | unwind.frame_size += offset; |
| 4741 | unwind.pending_offset += offset; |
| 4742 | |
| 4743 | demand_empty_rest_of_line (); |
| 4744 | } |
| 4745 | |
| 4746 | /* Parse an unwind_setfp directive. */ |
| 4747 | |
| 4748 | static void |
| 4749 | s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) |
| 4750 | { |
| 4751 | int sp_reg; |
| 4752 | int fp_reg; |
| 4753 | int offset; |
| 4754 | |
| 4755 | if (!unwind.proc_start) |
| 4756 | as_bad (MISSING_FNSTART); |
| 4757 | |
| 4758 | fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
| 4759 | if (skip_past_comma (&input_line_pointer) == FAIL) |
| 4760 | sp_reg = FAIL; |
| 4761 | else |
| 4762 | sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
| 4763 | |
| 4764 | if (fp_reg == FAIL || sp_reg == FAIL) |
| 4765 | { |
| 4766 | as_bad (_("expected <reg>, <reg>")); |
| 4767 | ignore_rest_of_line (); |
| 4768 | return; |
| 4769 | } |
| 4770 | |
| 4771 | /* Optional constant. */ |
| 4772 | if (skip_past_comma (&input_line_pointer) != FAIL) |
| 4773 | { |
| 4774 | if (immediate_for_directive (&offset) == FAIL) |
| 4775 | return; |
| 4776 | } |
| 4777 | else |
| 4778 | offset = 0; |
| 4779 | |
| 4780 | demand_empty_rest_of_line (); |
| 4781 | |
| 4782 | if (sp_reg != REG_SP && sp_reg != unwind.fp_reg) |
| 4783 | { |
| 4784 | as_bad (_("register must be either sp or set by a previous" |
| 4785 | "unwind_movsp directive")); |
| 4786 | return; |
| 4787 | } |
| 4788 | |
| 4789 | /* Don't generate any opcodes, just record the information for later. */ |
| 4790 | unwind.fp_reg = fp_reg; |
| 4791 | unwind.fp_used = 1; |
| 4792 | if (sp_reg == REG_SP) |
| 4793 | unwind.fp_offset = unwind.frame_size - offset; |
| 4794 | else |
| 4795 | unwind.fp_offset -= offset; |
| 4796 | } |
| 4797 | |
| 4798 | /* Parse an unwind_raw directive. */ |
| 4799 | |
| 4800 | static void |
| 4801 | s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) |
| 4802 | { |
| 4803 | expressionS exp; |
| 4804 | /* This is an arbitrary limit. */ |
| 4805 | unsigned char op[16]; |
| 4806 | int count; |
| 4807 | |
| 4808 | if (!unwind.proc_start) |
| 4809 | as_bad (MISSING_FNSTART); |
| 4810 | |
| 4811 | expression (&exp); |
| 4812 | if (exp.X_op == O_constant |
| 4813 | && skip_past_comma (&input_line_pointer) != FAIL) |
| 4814 | { |
| 4815 | unwind.frame_size += exp.X_add_number; |
| 4816 | expression (&exp); |
| 4817 | } |
| 4818 | else |
| 4819 | exp.X_op = O_illegal; |
| 4820 | |
| 4821 | if (exp.X_op != O_constant) |
| 4822 | { |
| 4823 | as_bad (_("expected <offset>, <opcode>")); |
| 4824 | ignore_rest_of_line (); |
| 4825 | return; |
| 4826 | } |
| 4827 | |
| 4828 | count = 0; |
| 4829 | |
| 4830 | /* Parse the opcode. */ |
| 4831 | for (;;) |
| 4832 | { |
| 4833 | if (count >= 16) |
| 4834 | { |
| 4835 | as_bad (_("unwind opcode too long")); |
| 4836 | ignore_rest_of_line (); |
| 4837 | } |
| 4838 | if (exp.X_op != O_constant || exp.X_add_number & ~0xff) |
| 4839 | { |
| 4840 | as_bad (_("invalid unwind opcode")); |
| 4841 | ignore_rest_of_line (); |
| 4842 | return; |
| 4843 | } |
| 4844 | op[count++] = exp.X_add_number; |
| 4845 | |
| 4846 | /* Parse the next byte. */ |
| 4847 | if (skip_past_comma (&input_line_pointer) == FAIL) |
| 4848 | break; |
| 4849 | |
| 4850 | expression (&exp); |
| 4851 | } |
| 4852 | |
| 4853 | /* Add the opcode bytes in reverse order. */ |
| 4854 | while (count--) |
| 4855 | add_unwind_opcode (op[count], 1); |
| 4856 | |
| 4857 | demand_empty_rest_of_line (); |
| 4858 | } |
| 4859 | |
| 4860 | |
| 4861 | /* Parse a .eabi_attribute directive. */ |
| 4862 | |
| 4863 | static void |
| 4864 | s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) |
| 4865 | { |
| 4866 | int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC); |
| 4867 | |
| 4868 | if (tag >= 0 && tag < NUM_KNOWN_OBJ_ATTRIBUTES) |
| 4869 | attributes_set_explicitly[tag] = 1; |
| 4870 | } |
| 4871 | |
| 4872 | /* Emit a tls fix for the symbol. */ |
| 4873 | |
| 4874 | static void |
| 4875 | s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED) |
| 4876 | { |
| 4877 | char *p; |
| 4878 | expressionS exp; |
| 4879 | #ifdef md_flush_pending_output |
| 4880 | md_flush_pending_output (); |
| 4881 | #endif |
| 4882 | |
| 4883 | #ifdef md_cons_align |
| 4884 | md_cons_align (4); |
| 4885 | #endif |
| 4886 | |
| 4887 | /* Since we're just labelling the code, there's no need to define a |
| 4888 | mapping symbol. */ |
| 4889 | expression (&exp); |
| 4890 | p = obstack_next_free (&frchain_now->frch_obstack); |
| 4891 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0, |
| 4892 | thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ |
| 4893 | : BFD_RELOC_ARM_TLS_DESCSEQ); |
| 4894 | } |
| 4895 | #endif /* OBJ_ELF */ |
| 4896 | |
| 4897 | static void s_arm_arch (int); |
| 4898 | static void s_arm_object_arch (int); |
| 4899 | static void s_arm_cpu (int); |
| 4900 | static void s_arm_fpu (int); |
| 4901 | static void s_arm_arch_extension (int); |
| 4902 | |
| 4903 | #ifdef TE_PE |
| 4904 | |
| 4905 | static void |
| 4906 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
| 4907 | { |
| 4908 | expressionS exp; |
| 4909 | |
| 4910 | do |
| 4911 | { |
| 4912 | expression (&exp); |
| 4913 | if (exp.X_op == O_symbol) |
| 4914 | exp.X_op = O_secrel; |
| 4915 | |
| 4916 | emit_expr (&exp, 4); |
| 4917 | } |
| 4918 | while (*input_line_pointer++ == ','); |
| 4919 | |
| 4920 | input_line_pointer--; |
| 4921 | demand_empty_rest_of_line (); |
| 4922 | } |
| 4923 | #endif /* TE_PE */ |
| 4924 | |
| 4925 | /* This table describes all the machine specific pseudo-ops the assembler |
| 4926 | has to support. The fields are: |
| 4927 | pseudo-op name without dot |
| 4928 | function to call to execute this pseudo-op |
| 4929 | Integer arg to pass to the function. */ |
| 4930 | |
| 4931 | const pseudo_typeS md_pseudo_table[] = |
| 4932 | { |
| 4933 | /* Never called because '.req' does not start a line. */ |
| 4934 | { "req", s_req, 0 }, |
| 4935 | /* Following two are likewise never called. */ |
| 4936 | { "dn", s_dn, 0 }, |
| 4937 | { "qn", s_qn, 0 }, |
| 4938 | { "unreq", s_unreq, 0 }, |
| 4939 | { "bss", s_bss, 0 }, |
| 4940 | { "align", s_align_ptwo, 2 }, |
| 4941 | { "arm", s_arm, 0 }, |
| 4942 | { "thumb", s_thumb, 0 }, |
| 4943 | { "code", s_code, 0 }, |
| 4944 | { "force_thumb", s_force_thumb, 0 }, |
| 4945 | { "thumb_func", s_thumb_func, 0 }, |
| 4946 | { "thumb_set", s_thumb_set, 0 }, |
| 4947 | { "even", s_even, 0 }, |
| 4948 | { "ltorg", s_ltorg, 0 }, |
| 4949 | { "pool", s_ltorg, 0 }, |
| 4950 | { "syntax", s_syntax, 0 }, |
| 4951 | { "cpu", s_arm_cpu, 0 }, |
| 4952 | { "arch", s_arm_arch, 0 }, |
| 4953 | { "object_arch", s_arm_object_arch, 0 }, |
| 4954 | { "fpu", s_arm_fpu, 0 }, |
| 4955 | { "arch_extension", s_arm_arch_extension, 0 }, |
| 4956 | #ifdef OBJ_ELF |
| 4957 | { "word", s_arm_elf_cons, 4 }, |
| 4958 | { "long", s_arm_elf_cons, 4 }, |
| 4959 | { "inst.n", s_arm_elf_inst, 2 }, |
| 4960 | { "inst.w", s_arm_elf_inst, 4 }, |
| 4961 | { "inst", s_arm_elf_inst, 0 }, |
| 4962 | { "rel31", s_arm_rel31, 0 }, |
| 4963 | { "fnstart", s_arm_unwind_fnstart, 0 }, |
| 4964 | { "fnend", s_arm_unwind_fnend, 0 }, |
| 4965 | { "cantunwind", s_arm_unwind_cantunwind, 0 }, |
| 4966 | { "personality", s_arm_unwind_personality, 0 }, |
| 4967 | { "personalityindex", s_arm_unwind_personalityindex, 0 }, |
| 4968 | { "handlerdata", s_arm_unwind_handlerdata, 0 }, |
| 4969 | { "save", s_arm_unwind_save, 0 }, |
| 4970 | { "vsave", s_arm_unwind_save, 1 }, |
| 4971 | { "movsp", s_arm_unwind_movsp, 0 }, |
| 4972 | { "pad", s_arm_unwind_pad, 0 }, |
| 4973 | { "setfp", s_arm_unwind_setfp, 0 }, |
| 4974 | { "unwind_raw", s_arm_unwind_raw, 0 }, |
| 4975 | { "eabi_attribute", s_arm_eabi_attribute, 0 }, |
| 4976 | { "tlsdescseq", s_arm_tls_descseq, 0 }, |
| 4977 | #else |
| 4978 | { "word", cons, 4}, |
| 4979 | |
| 4980 | /* These are used for dwarf. */ |
| 4981 | {"2byte", cons, 2}, |
| 4982 | {"4byte", cons, 4}, |
| 4983 | {"8byte", cons, 8}, |
| 4984 | /* These are used for dwarf2. */ |
| 4985 | { "file", dwarf2_directive_file, 0 }, |
| 4986 | { "loc", dwarf2_directive_loc, 0 }, |
| 4987 | { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 }, |
| 4988 | #endif |
| 4989 | { "extend", float_cons, 'x' }, |
| 4990 | { "ldouble", float_cons, 'x' }, |
| 4991 | { "packed", float_cons, 'p' }, |
| 4992 | #ifdef TE_PE |
| 4993 | {"secrel32", pe_directive_secrel, 0}, |
| 4994 | #endif |
| 4995 | |
| 4996 | /* These are for compatibility with CodeComposer Studio. */ |
| 4997 | {"ref", s_ccs_ref, 0}, |
| 4998 | {"def", s_ccs_def, 0}, |
| 4999 | {"asmfunc", s_ccs_asmfunc, 0}, |
| 5000 | {"endasmfunc", s_ccs_endasmfunc, 0}, |
| 5001 | |
| 5002 | { 0, 0, 0 } |
| 5003 | }; |
| 5004 | \f |
| 5005 | /* Parser functions used exclusively in instruction operands. */ |
| 5006 | |
| 5007 | /* Generic immediate-value read function for use in insn parsing. |
| 5008 | STR points to the beginning of the immediate (the leading #); |
| 5009 | VAL receives the value; if the value is outside [MIN, MAX] |
| 5010 | issue an error. PREFIX_OPT is true if the immediate prefix is |
| 5011 | optional. */ |
| 5012 | |
| 5013 | static int |
| 5014 | parse_immediate (char **str, int *val, int min, int max, |
| 5015 | bfd_boolean prefix_opt) |
| 5016 | { |
| 5017 | expressionS exp; |
| 5018 | |
| 5019 | my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); |
| 5020 | if (exp.X_op != O_constant) |
| 5021 | { |
| 5022 | inst.error = _("constant expression required"); |
| 5023 | return FAIL; |
| 5024 | } |
| 5025 | |
| 5026 | if (exp.X_add_number < min || exp.X_add_number > max) |
| 5027 | { |
| 5028 | inst.error = _("immediate value out of range"); |
| 5029 | return FAIL; |
| 5030 | } |
| 5031 | |
| 5032 | *val = exp.X_add_number; |
| 5033 | return SUCCESS; |
| 5034 | } |
| 5035 | |
| 5036 | /* Less-generic immediate-value read function with the possibility of loading a |
| 5037 | big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate |
| 5038 | instructions. Puts the result directly in inst.operands[i]. */ |
| 5039 | |
| 5040 | static int |
| 5041 | parse_big_immediate (char **str, int i, expressionS *in_exp, |
| 5042 | bfd_boolean allow_symbol_p) |
| 5043 | { |
| 5044 | expressionS exp; |
| 5045 | expressionS *exp_p = in_exp ? in_exp : &exp; |
| 5046 | char *ptr = *str; |
| 5047 | |
| 5048 | my_get_expression (exp_p, &ptr, GE_OPT_PREFIX_BIG); |
| 5049 | |
| 5050 | if (exp_p->X_op == O_constant) |
| 5051 | { |
| 5052 | inst.operands[i].imm = exp_p->X_add_number & 0xffffffff; |
| 5053 | /* If we're on a 64-bit host, then a 64-bit number can be returned using |
| 5054 | O_constant. We have to be careful not to break compilation for |
| 5055 | 32-bit X_add_number, though. */ |
| 5056 | if ((exp_p->X_add_number & ~(offsetT)(0xffffffffU)) != 0) |
| 5057 | { |
| 5058 | /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */ |
| 5059 | inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16) |
| 5060 | & 0xffffffff); |
| 5061 | inst.operands[i].regisimm = 1; |
| 5062 | } |
| 5063 | } |
| 5064 | else if (exp_p->X_op == O_big |
| 5065 | && LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 32) |
| 5066 | { |
| 5067 | unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; |
| 5068 | |
| 5069 | /* Bignums have their least significant bits in |
| 5070 | generic_bignum[0]. Make sure we put 32 bits in imm and |
| 5071 | 32 bits in reg, in a (hopefully) portable way. */ |
| 5072 | gas_assert (parts != 0); |
| 5073 | |
| 5074 | /* Make sure that the number is not too big. |
| 5075 | PR 11972: Bignums can now be sign-extended to the |
| 5076 | size of a .octa so check that the out of range bits |
| 5077 | are all zero or all one. */ |
| 5078 | if (LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 64) |
| 5079 | { |
| 5080 | LITTLENUM_TYPE m = -1; |
| 5081 | |
| 5082 | if (generic_bignum[parts * 2] != 0 |
| 5083 | && generic_bignum[parts * 2] != m) |
| 5084 | return FAIL; |
| 5085 | |
| 5086 | for (j = parts * 2 + 1; j < (unsigned) exp_p->X_add_number; j++) |
| 5087 | if (generic_bignum[j] != generic_bignum[j-1]) |
| 5088 | return FAIL; |
| 5089 | } |
| 5090 | |
| 5091 | inst.operands[i].imm = 0; |
| 5092 | for (j = 0; j < parts; j++, idx++) |
| 5093 | inst.operands[i].imm |= generic_bignum[idx] |
| 5094 | << (LITTLENUM_NUMBER_OF_BITS * j); |
| 5095 | inst.operands[i].reg = 0; |
| 5096 | for (j = 0; j < parts; j++, idx++) |
| 5097 | inst.operands[i].reg |= generic_bignum[idx] |
| 5098 | << (LITTLENUM_NUMBER_OF_BITS * j); |
| 5099 | inst.operands[i].regisimm = 1; |
| 5100 | } |
| 5101 | else if (!(exp_p->X_op == O_symbol && allow_symbol_p)) |
| 5102 | return FAIL; |
| 5103 | |
| 5104 | *str = ptr; |
| 5105 | |
| 5106 | return SUCCESS; |
| 5107 | } |
| 5108 | |
| 5109 | /* Returns the pseudo-register number of an FPA immediate constant, |
| 5110 | or FAIL if there isn't a valid constant here. */ |
| 5111 | |
| 5112 | static int |
| 5113 | parse_fpa_immediate (char ** str) |
| 5114 | { |
| 5115 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
| 5116 | char * save_in; |
| 5117 | expressionS exp; |
| 5118 | int i; |
| 5119 | int j; |
| 5120 | |
| 5121 | /* First try and match exact strings, this is to guarantee |
| 5122 | that some formats will work even for cross assembly. */ |
| 5123 | |
| 5124 | for (i = 0; fp_const[i]; i++) |
| 5125 | { |
| 5126 | if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) |
| 5127 | { |
| 5128 | char *start = *str; |
| 5129 | |
| 5130 | *str += strlen (fp_const[i]); |
| 5131 | if (is_end_of_line[(unsigned char) **str]) |
| 5132 | return i + 8; |
| 5133 | *str = start; |
| 5134 | } |
| 5135 | } |
| 5136 | |
| 5137 | /* Just because we didn't get a match doesn't mean that the constant |
| 5138 | isn't valid, just that it is in a format that we don't |
| 5139 | automatically recognize. Try parsing it with the standard |
| 5140 | expression routines. */ |
| 5141 | |
| 5142 | memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); |
| 5143 | |
| 5144 | /* Look for a raw floating point number. */ |
| 5145 | if ((save_in = atof_ieee (*str, 'x', words)) != NULL |
| 5146 | && is_end_of_line[(unsigned char) *save_in]) |
| 5147 | { |
| 5148 | for (i = 0; i < NUM_FLOAT_VALS; i++) |
| 5149 | { |
| 5150 | for (j = 0; j < MAX_LITTLENUMS; j++) |
| 5151 | { |
| 5152 | if (words[j] != fp_values[i][j]) |
| 5153 | break; |
| 5154 | } |
| 5155 | |
| 5156 | if (j == MAX_LITTLENUMS) |
| 5157 | { |
| 5158 | *str = save_in; |
| 5159 | return i + 8; |
| 5160 | } |
| 5161 | } |
| 5162 | } |
| 5163 | |
| 5164 | /* Try and parse a more complex expression, this will probably fail |
| 5165 | unless the code uses a floating point prefix (eg "0f"). */ |
| 5166 | save_in = input_line_pointer; |
| 5167 | input_line_pointer = *str; |
| 5168 | if (expression (&exp) == absolute_section |
| 5169 | && exp.X_op == O_big |
| 5170 | && exp.X_add_number < 0) |
| 5171 | { |
| 5172 | /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. |
| 5173 | Ditto for 15. */ |
| 5174 | #define X_PRECISION 5 |
| 5175 | #define E_PRECISION 15L |
| 5176 | if (gen_to_words (words, X_PRECISION, E_PRECISION) == 0) |
| 5177 | { |
| 5178 | for (i = 0; i < NUM_FLOAT_VALS; i++) |
| 5179 | { |
| 5180 | for (j = 0; j < MAX_LITTLENUMS; j++) |
| 5181 | { |
| 5182 | if (words[j] != fp_values[i][j]) |
| 5183 | break; |
| 5184 | } |
| 5185 | |
| 5186 | if (j == MAX_LITTLENUMS) |
| 5187 | { |
| 5188 | *str = input_line_pointer; |
| 5189 | input_line_pointer = save_in; |
| 5190 | return i + 8; |
| 5191 | } |
| 5192 | } |
| 5193 | } |
| 5194 | } |
| 5195 | |
| 5196 | *str = input_line_pointer; |
| 5197 | input_line_pointer = save_in; |
| 5198 | inst.error = _("invalid FPA immediate expression"); |
| 5199 | return FAIL; |
| 5200 | } |
| 5201 | |
| 5202 | /* Returns 1 if a number has "quarter-precision" float format |
| 5203 | 0baBbbbbbc defgh000 00000000 00000000. */ |
| 5204 | |
| 5205 | static int |
| 5206 | is_quarter_float (unsigned imm) |
| 5207 | { |
| 5208 | int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; |
| 5209 | return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; |
| 5210 | } |
| 5211 | |
| 5212 | |
| 5213 | /* Detect the presence of a floating point or integer zero constant, |
| 5214 | i.e. #0.0 or #0. */ |
| 5215 | |
| 5216 | static bfd_boolean |
| 5217 | parse_ifimm_zero (char **in) |
| 5218 | { |
| 5219 | int error_code; |
| 5220 | |
| 5221 | if (!is_immediate_prefix (**in)) |
| 5222 | { |
| 5223 | /* In unified syntax, all prefixes are optional. */ |
| 5224 | if (!unified_syntax) |
| 5225 | return FALSE; |
| 5226 | } |
| 5227 | else |
| 5228 | ++*in; |
| 5229 | |
| 5230 | /* Accept #0x0 as a synonym for #0. */ |
| 5231 | if (strncmp (*in, "0x", 2) == 0) |
| 5232 | { |
| 5233 | int val; |
| 5234 | if (parse_immediate (in, &val, 0, 0, TRUE) == FAIL) |
| 5235 | return FALSE; |
| 5236 | return TRUE; |
| 5237 | } |
| 5238 | |
| 5239 | error_code = atof_generic (in, ".", EXP_CHARS, |
| 5240 | &generic_floating_point_number); |
| 5241 | |
| 5242 | if (!error_code |
| 5243 | && generic_floating_point_number.sign == '+' |
| 5244 | && (generic_floating_point_number.low |
| 5245 | > generic_floating_point_number.leader)) |
| 5246 | return TRUE; |
| 5247 | |
| 5248 | return FALSE; |
| 5249 | } |
| 5250 | |
| 5251 | /* Parse an 8-bit "quarter-precision" floating point number of the form: |
| 5252 | 0baBbbbbbc defgh000 00000000 00000000. |
| 5253 | The zero and minus-zero cases need special handling, since they can't be |
| 5254 | encoded in the "quarter-precision" float format, but can nonetheless be |
| 5255 | loaded as integer constants. */ |
| 5256 | |
| 5257 | static unsigned |
| 5258 | parse_qfloat_immediate (char **ccp, int *immed) |
| 5259 | { |
| 5260 | char *str = *ccp; |
| 5261 | char *fpnum; |
| 5262 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
| 5263 | int found_fpchar = 0; |
| 5264 | |
| 5265 | skip_past_char (&str, '#'); |
| 5266 | |
| 5267 | /* We must not accidentally parse an integer as a floating-point number. Make |
| 5268 | sure that the value we parse is not an integer by checking for special |
| 5269 | characters '.' or 'e'. |
| 5270 | FIXME: This is a horrible hack, but doing better is tricky because type |
| 5271 | information isn't in a very usable state at parse time. */ |
| 5272 | fpnum = str; |
| 5273 | skip_whitespace (fpnum); |
| 5274 | |
| 5275 | if (strncmp (fpnum, "0x", 2) == 0) |
| 5276 | return FAIL; |
| 5277 | else |
| 5278 | { |
| 5279 | for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) |
| 5280 | if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') |
| 5281 | { |
| 5282 | found_fpchar = 1; |
| 5283 | break; |
| 5284 | } |
| 5285 | |
| 5286 | if (!found_fpchar) |
| 5287 | return FAIL; |
| 5288 | } |
| 5289 | |
| 5290 | if ((str = atof_ieee (str, 's', words)) != NULL) |
| 5291 | { |
| 5292 | unsigned fpword = 0; |
| 5293 | int i; |
| 5294 | |
| 5295 | /* Our FP word must be 32 bits (single-precision FP). */ |
| 5296 | for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) |
| 5297 | { |
| 5298 | fpword <<= LITTLENUM_NUMBER_OF_BITS; |
| 5299 | fpword |= words[i]; |
| 5300 | } |
| 5301 | |
| 5302 | if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0) |
| 5303 | *immed = fpword; |
| 5304 | else |
| 5305 | return FAIL; |
| 5306 | |
| 5307 | *ccp = str; |
| 5308 | |
| 5309 | return SUCCESS; |
| 5310 | } |
| 5311 | |
| 5312 | return FAIL; |
| 5313 | } |
| 5314 | |
| 5315 | /* Shift operands. */ |
| 5316 | enum shift_kind |
| 5317 | { |
| 5318 | SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX, SHIFT_UXTW |
| 5319 | }; |
| 5320 | |
| 5321 | struct asm_shift_name |
| 5322 | { |
| 5323 | const char *name; |
| 5324 | enum shift_kind kind; |
| 5325 | }; |
| 5326 | |
| 5327 | /* Third argument to parse_shift. */ |
| 5328 | enum parse_shift_mode |
| 5329 | { |
| 5330 | NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ |
| 5331 | SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ |
| 5332 | SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ |
| 5333 | SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ |
| 5334 | SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ |
| 5335 | SHIFT_UXTW_IMMEDIATE /* Shift must be UXTW immediate. */ |
| 5336 | }; |
| 5337 | |
| 5338 | /* Parse a <shift> specifier on an ARM data processing instruction. |
| 5339 | This has three forms: |
| 5340 | |
| 5341 | (LSL|LSR|ASL|ASR|ROR) Rs |
| 5342 | (LSL|LSR|ASL|ASR|ROR) #imm |
| 5343 | RRX |
| 5344 | |
| 5345 | Note that ASL is assimilated to LSL in the instruction encoding, and |
| 5346 | RRX to ROR #0 (which cannot be written as such). */ |
| 5347 | |
| 5348 | static int |
| 5349 | parse_shift (char **str, int i, enum parse_shift_mode mode) |
| 5350 | { |
| 5351 | const struct asm_shift_name *shift_name; |
| 5352 | enum shift_kind shift; |
| 5353 | char *s = *str; |
| 5354 | char *p = s; |
| 5355 | int reg; |
| 5356 | |
| 5357 | for (p = *str; ISALPHA (*p); p++) |
| 5358 | ; |
| 5359 | |
| 5360 | if (p == *str) |
| 5361 | { |
| 5362 | inst.error = _("shift expression expected"); |
| 5363 | return FAIL; |
| 5364 | } |
| 5365 | |
| 5366 | shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str, |
| 5367 | p - *str); |
| 5368 | |
| 5369 | if (shift_name == NULL) |
| 5370 | { |
| 5371 | inst.error = _("shift expression expected"); |
| 5372 | return FAIL; |
| 5373 | } |
| 5374 | |
| 5375 | shift = shift_name->kind; |
| 5376 | |
| 5377 | switch (mode) |
| 5378 | { |
| 5379 | case NO_SHIFT_RESTRICT: |
| 5380 | case SHIFT_IMMEDIATE: |
| 5381 | if (shift == SHIFT_UXTW) |
| 5382 | { |
| 5383 | inst.error = _("'UXTW' not allowed here"); |
| 5384 | return FAIL; |
| 5385 | } |
| 5386 | break; |
| 5387 | |
| 5388 | case SHIFT_LSL_OR_ASR_IMMEDIATE: |
| 5389 | if (shift != SHIFT_LSL && shift != SHIFT_ASR) |
| 5390 | { |
| 5391 | inst.error = _("'LSL' or 'ASR' required"); |
| 5392 | return FAIL; |
| 5393 | } |
| 5394 | break; |
| 5395 | |
| 5396 | case SHIFT_LSL_IMMEDIATE: |
| 5397 | if (shift != SHIFT_LSL) |
| 5398 | { |
| 5399 | inst.error = _("'LSL' required"); |
| 5400 | return FAIL; |
| 5401 | } |
| 5402 | break; |
| 5403 | |
| 5404 | case SHIFT_ASR_IMMEDIATE: |
| 5405 | if (shift != SHIFT_ASR) |
| 5406 | { |
| 5407 | inst.error = _("'ASR' required"); |
| 5408 | return FAIL; |
| 5409 | } |
| 5410 | break; |
| 5411 | case SHIFT_UXTW_IMMEDIATE: |
| 5412 | if (shift != SHIFT_UXTW) |
| 5413 | { |
| 5414 | inst.error = _("'UXTW' required"); |
| 5415 | return FAIL; |
| 5416 | } |
| 5417 | break; |
| 5418 | |
| 5419 | default: abort (); |
| 5420 | } |
| 5421 | |
| 5422 | if (shift != SHIFT_RRX) |
| 5423 | { |
| 5424 | /* Whitespace can appear here if the next thing is a bare digit. */ |
| 5425 | skip_whitespace (p); |
| 5426 | |
| 5427 | if (mode == NO_SHIFT_RESTRICT |
| 5428 | && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
| 5429 | { |
| 5430 | inst.operands[i].imm = reg; |
| 5431 | inst.operands[i].immisreg = 1; |
| 5432 | } |
| 5433 | else if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX)) |
| 5434 | return FAIL; |
| 5435 | } |
| 5436 | inst.operands[i].shift_kind = shift; |
| 5437 | inst.operands[i].shifted = 1; |
| 5438 | *str = p; |
| 5439 | return SUCCESS; |
| 5440 | } |
| 5441 | |
| 5442 | /* Parse a <shifter_operand> for an ARM data processing instruction: |
| 5443 | |
| 5444 | #<immediate> |
| 5445 | #<immediate>, <rotate> |
| 5446 | <Rm> |
| 5447 | <Rm>, <shift> |
| 5448 | |
| 5449 | where <shift> is defined by parse_shift above, and <rotate> is a |
| 5450 | multiple of 2 between 0 and 30. Validation of immediate operands |
| 5451 | is deferred to md_apply_fix. */ |
| 5452 | |
| 5453 | static int |
| 5454 | parse_shifter_operand (char **str, int i) |
| 5455 | { |
| 5456 | int value; |
| 5457 | expressionS exp; |
| 5458 | |
| 5459 | if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) |
| 5460 | { |
| 5461 | inst.operands[i].reg = value; |
| 5462 | inst.operands[i].isreg = 1; |
| 5463 | |
| 5464 | /* parse_shift will override this if appropriate */ |
| 5465 | inst.relocs[0].exp.X_op = O_constant; |
| 5466 | inst.relocs[0].exp.X_add_number = 0; |
| 5467 | |
| 5468 | if (skip_past_comma (str) == FAIL) |
| 5469 | return SUCCESS; |
| 5470 | |
| 5471 | /* Shift operation on register. */ |
| 5472 | return parse_shift (str, i, NO_SHIFT_RESTRICT); |
| 5473 | } |
| 5474 | |
| 5475 | if (my_get_expression (&inst.relocs[0].exp, str, GE_IMM_PREFIX)) |
| 5476 | return FAIL; |
| 5477 | |
| 5478 | if (skip_past_comma (str) == SUCCESS) |
| 5479 | { |
| 5480 | /* #x, y -- ie explicit rotation by Y. */ |
| 5481 | if (my_get_expression (&exp, str, GE_NO_PREFIX)) |
| 5482 | return FAIL; |
| 5483 | |
| 5484 | if (exp.X_op != O_constant || inst.relocs[0].exp.X_op != O_constant) |
| 5485 | { |
| 5486 | inst.error = _("constant expression expected"); |
| 5487 | return FAIL; |
| 5488 | } |
| 5489 | |
| 5490 | value = exp.X_add_number; |
| 5491 | if (value < 0 || value > 30 || value % 2 != 0) |
| 5492 | { |
| 5493 | inst.error = _("invalid rotation"); |
| 5494 | return FAIL; |
| 5495 | } |
| 5496 | if (inst.relocs[0].exp.X_add_number < 0 |
| 5497 | || inst.relocs[0].exp.X_add_number > 255) |
| 5498 | { |
| 5499 | inst.error = _("invalid constant"); |
| 5500 | return FAIL; |
| 5501 | } |
| 5502 | |
| 5503 | /* Encode as specified. */ |
| 5504 | inst.operands[i].imm = inst.relocs[0].exp.X_add_number | value << 7; |
| 5505 | return SUCCESS; |
| 5506 | } |
| 5507 | |
| 5508 | inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE; |
| 5509 | inst.relocs[0].pc_rel = 0; |
| 5510 | return SUCCESS; |
| 5511 | } |
| 5512 | |
| 5513 | /* Group relocation information. Each entry in the table contains the |
| 5514 | textual name of the relocation as may appear in assembler source |
| 5515 | and must end with a colon. |
| 5516 | Along with this textual name are the relocation codes to be used if |
| 5517 | the corresponding instruction is an ALU instruction (ADD or SUB only), |
| 5518 | an LDR, an LDRS, or an LDC. */ |
| 5519 | |
| 5520 | struct group_reloc_table_entry |
| 5521 | { |
| 5522 | const char *name; |
| 5523 | int alu_code; |
| 5524 | int ldr_code; |
| 5525 | int ldrs_code; |
| 5526 | int ldc_code; |
| 5527 | }; |
| 5528 | |
| 5529 | typedef enum |
| 5530 | { |
| 5531 | /* Varieties of non-ALU group relocation. */ |
| 5532 | |
| 5533 | GROUP_LDR, |
| 5534 | GROUP_LDRS, |
| 5535 | GROUP_LDC, |
| 5536 | GROUP_MVE |
| 5537 | } group_reloc_type; |
| 5538 | |
| 5539 | static struct group_reloc_table_entry group_reloc_table[] = |
| 5540 | { /* Program counter relative: */ |
| 5541 | { "pc_g0_nc", |
| 5542 | BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ |
| 5543 | 0, /* LDR */ |
| 5544 | 0, /* LDRS */ |
| 5545 | 0 }, /* LDC */ |
| 5546 | { "pc_g0", |
| 5547 | BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ |
| 5548 | BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ |
| 5549 | BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ |
| 5550 | BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ |
| 5551 | { "pc_g1_nc", |
| 5552 | BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ |
| 5553 | 0, /* LDR */ |
| 5554 | 0, /* LDRS */ |
| 5555 | 0 }, /* LDC */ |
| 5556 | { "pc_g1", |
| 5557 | BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ |
| 5558 | BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ |
| 5559 | BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ |
| 5560 | BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ |
| 5561 | { "pc_g2", |
| 5562 | BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ |
| 5563 | BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ |
| 5564 | BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ |
| 5565 | BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ |
| 5566 | /* Section base relative */ |
| 5567 | { "sb_g0_nc", |
| 5568 | BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ |
| 5569 | 0, /* LDR */ |
| 5570 | 0, /* LDRS */ |
| 5571 | 0 }, /* LDC */ |
| 5572 | { "sb_g0", |
| 5573 | BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ |
| 5574 | BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ |
| 5575 | BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ |
| 5576 | BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ |
| 5577 | { "sb_g1_nc", |
| 5578 | BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ |
| 5579 | 0, /* LDR */ |
| 5580 | 0, /* LDRS */ |
| 5581 | 0 }, /* LDC */ |
| 5582 | { "sb_g1", |
| 5583 | BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ |
| 5584 | BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ |
| 5585 | BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ |
| 5586 | BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ |
| 5587 | { "sb_g2", |
| 5588 | BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ |
| 5589 | BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ |
| 5590 | BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ |
| 5591 | BFD_RELOC_ARM_LDC_SB_G2 }, /* LDC */ |
| 5592 | /* Absolute thumb alu relocations. */ |
| 5593 | { "lower0_7", |
| 5594 | BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC,/* ALU. */ |
| 5595 | 0, /* LDR. */ |
| 5596 | 0, /* LDRS. */ |
| 5597 | 0 }, /* LDC. */ |
| 5598 | { "lower8_15", |
| 5599 | BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC,/* ALU. */ |
| 5600 | 0, /* LDR. */ |
| 5601 | 0, /* LDRS. */ |
| 5602 | 0 }, /* LDC. */ |
| 5603 | { "upper0_7", |
| 5604 | BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC,/* ALU. */ |
| 5605 | 0, /* LDR. */ |
| 5606 | 0, /* LDRS. */ |
| 5607 | 0 }, /* LDC. */ |
| 5608 | { "upper8_15", |
| 5609 | BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC,/* ALU. */ |
| 5610 | 0, /* LDR. */ |
| 5611 | 0, /* LDRS. */ |
| 5612 | 0 } }; /* LDC. */ |
| 5613 | |
| 5614 | /* Given the address of a pointer pointing to the textual name of a group |
| 5615 | relocation as may appear in assembler source, attempt to find its details |
| 5616 | in group_reloc_table. The pointer will be updated to the character after |
| 5617 | the trailing colon. On failure, FAIL will be returned; SUCCESS |
| 5618 | otherwise. On success, *entry will be updated to point at the relevant |
| 5619 | group_reloc_table entry. */ |
| 5620 | |
| 5621 | static int |
| 5622 | find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) |
| 5623 | { |
| 5624 | unsigned int i; |
| 5625 | for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) |
| 5626 | { |
| 5627 | int length = strlen (group_reloc_table[i].name); |
| 5628 | |
| 5629 | if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 |
| 5630 | && (*str)[length] == ':') |
| 5631 | { |
| 5632 | *out = &group_reloc_table[i]; |
| 5633 | *str += (length + 1); |
| 5634 | return SUCCESS; |
| 5635 | } |
| 5636 | } |
| 5637 | |
| 5638 | return FAIL; |
| 5639 | } |
| 5640 | |
| 5641 | /* Parse a <shifter_operand> for an ARM data processing instruction |
| 5642 | (as for parse_shifter_operand) where group relocations are allowed: |
| 5643 | |
| 5644 | #<immediate> |
| 5645 | #<immediate>, <rotate> |
| 5646 | #:<group_reloc>:<expression> |
| 5647 | <Rm> |
| 5648 | <Rm>, <shift> |
| 5649 | |
| 5650 | where <group_reloc> is one of the strings defined in group_reloc_table. |
| 5651 | The hashes are optional. |
| 5652 | |
| 5653 | Everything else is as for parse_shifter_operand. */ |
| 5654 | |
| 5655 | static parse_operand_result |
| 5656 | parse_shifter_operand_group_reloc (char **str, int i) |
| 5657 | { |
| 5658 | /* Determine if we have the sequence of characters #: or just : |
| 5659 | coming next. If we do, then we check for a group relocation. |
| 5660 | If we don't, punt the whole lot to parse_shifter_operand. */ |
| 5661 | |
| 5662 | if (((*str)[0] == '#' && (*str)[1] == ':') |
| 5663 | || (*str)[0] == ':') |
| 5664 | { |
| 5665 | struct group_reloc_table_entry *entry; |
| 5666 | |
| 5667 | if ((*str)[0] == '#') |
| 5668 | (*str) += 2; |
| 5669 | else |
| 5670 | (*str)++; |
| 5671 | |
| 5672 | /* Try to parse a group relocation. Anything else is an error. */ |
| 5673 | if (find_group_reloc_table_entry (str, &entry) == FAIL) |
| 5674 | { |
| 5675 | inst.error = _("unknown group relocation"); |
| 5676 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; |
| 5677 | } |
| 5678 | |
| 5679 | /* We now have the group relocation table entry corresponding to |
| 5680 | the name in the assembler source. Next, we parse the expression. */ |
| 5681 | if (my_get_expression (&inst.relocs[0].exp, str, GE_NO_PREFIX)) |
| 5682 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; |
| 5683 | |
| 5684 | /* Record the relocation type (always the ALU variant here). */ |
| 5685 | inst.relocs[0].type = (bfd_reloc_code_real_type) entry->alu_code; |
| 5686 | gas_assert (inst.relocs[0].type != 0); |
| 5687 | |
| 5688 | return PARSE_OPERAND_SUCCESS; |
| 5689 | } |
| 5690 | else |
| 5691 | return parse_shifter_operand (str, i) == SUCCESS |
| 5692 | ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; |
| 5693 | |
| 5694 | /* Never reached. */ |
| 5695 | } |
| 5696 | |
| 5697 | /* Parse a Neon alignment expression. Information is written to |
| 5698 | inst.operands[i]. We assume the initial ':' has been skipped. |
| 5699 | |
| 5700 | align .imm = align << 8, .immisalign=1, .preind=0 */ |
| 5701 | static parse_operand_result |
| 5702 | parse_neon_alignment (char **str, int i) |
| 5703 | { |
| 5704 | char *p = *str; |
| 5705 | expressionS exp; |
| 5706 | |
| 5707 | my_get_expression (&exp, &p, GE_NO_PREFIX); |
| 5708 | |
| 5709 | if (exp.X_op != O_constant) |
| 5710 | { |
| 5711 | inst.error = _("alignment must be constant"); |
| 5712 | return PARSE_OPERAND_FAIL; |
| 5713 | } |
| 5714 | |
| 5715 | inst.operands[i].imm = exp.X_add_number << 8; |
| 5716 | inst.operands[i].immisalign = 1; |
| 5717 | /* Alignments are not pre-indexes. */ |
| 5718 | inst.operands[i].preind = 0; |
| 5719 | |
| 5720 | *str = p; |
| 5721 | return PARSE_OPERAND_SUCCESS; |
| 5722 | } |
| 5723 | |
| 5724 | /* Parse all forms of an ARM address expression. Information is written |
| 5725 | to inst.operands[i] and/or inst.relocs[0]. |
| 5726 | |
| 5727 | Preindexed addressing (.preind=1): |
| 5728 | |
| 5729 | [Rn, #offset] .reg=Rn .relocs[0].exp=offset |
| 5730 | [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 |
| 5731 | [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 |
| 5732 | .shift_kind=shift .relocs[0].exp=shift_imm |
| 5733 | |
| 5734 | These three may have a trailing ! which causes .writeback to be set also. |
| 5735 | |
| 5736 | Postindexed addressing (.postind=1, .writeback=1): |
| 5737 | |
| 5738 | [Rn], #offset .reg=Rn .relocs[0].exp=offset |
| 5739 | [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 |
| 5740 | [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 |
| 5741 | .shift_kind=shift .relocs[0].exp=shift_imm |
| 5742 | |
| 5743 | Unindexed addressing (.preind=0, .postind=0): |
| 5744 | |
| 5745 | [Rn], {option} .reg=Rn .imm=option .immisreg=0 |
| 5746 | |
| 5747 | Other: |
| 5748 | |
| 5749 | [Rn]{!} shorthand for [Rn,#0]{!} |
| 5750 | =immediate .isreg=0 .relocs[0].exp=immediate |
| 5751 | label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label |
| 5752 | |
| 5753 | It is the caller's responsibility to check for addressing modes not |
| 5754 | supported by the instruction, and to set inst.relocs[0].type. */ |
| 5755 | |
| 5756 | static parse_operand_result |
| 5757 | parse_address_main (char **str, int i, int group_relocations, |
| 5758 | group_reloc_type group_type) |
| 5759 | { |
| 5760 | char *p = *str; |
| 5761 | int reg; |
| 5762 | |
| 5763 | if (skip_past_char (&p, '[') == FAIL) |
| 5764 | { |
| 5765 | if (skip_past_char (&p, '=') == FAIL) |
| 5766 | { |
| 5767 | /* Bare address - translate to PC-relative offset. */ |
| 5768 | inst.relocs[0].pc_rel = 1; |
| 5769 | inst.operands[i].reg = REG_PC; |
| 5770 | inst.operands[i].isreg = 1; |
| 5771 | inst.operands[i].preind = 1; |
| 5772 | |
| 5773 | if (my_get_expression (&inst.relocs[0].exp, &p, GE_OPT_PREFIX_BIG)) |
| 5774 | return PARSE_OPERAND_FAIL; |
| 5775 | } |
| 5776 | else if (parse_big_immediate (&p, i, &inst.relocs[0].exp, |
| 5777 | /*allow_symbol_p=*/TRUE)) |
| 5778 | return PARSE_OPERAND_FAIL; |
| 5779 | |
| 5780 | *str = p; |
| 5781 | return PARSE_OPERAND_SUCCESS; |
| 5782 | } |
| 5783 | |
| 5784 | /* PR gas/14887: Allow for whitespace after the opening bracket. */ |
| 5785 | skip_whitespace (p); |
| 5786 | |
| 5787 | if (group_type == GROUP_MVE) |
| 5788 | { |
| 5789 | enum arm_reg_type rtype = REG_TYPE_MQ; |
| 5790 | struct neon_type_el et; |
| 5791 | if ((reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL) |
| 5792 | { |
| 5793 | inst.operands[i].isquad = 1; |
| 5794 | } |
| 5795 | else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
| 5796 | { |
| 5797 | inst.error = BAD_ADDR_MODE; |
| 5798 | return PARSE_OPERAND_FAIL; |
| 5799 | } |
| 5800 | } |
| 5801 | else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
| 5802 | { |
| 5803 | if (group_type == GROUP_MVE) |
| 5804 | inst.error = BAD_ADDR_MODE; |
| 5805 | else |
| 5806 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); |
| 5807 | return PARSE_OPERAND_FAIL; |
| 5808 | } |
| 5809 | inst.operands[i].reg = reg; |
| 5810 | inst.operands[i].isreg = 1; |
| 5811 | |
| 5812 | if (skip_past_comma (&p) == SUCCESS) |
| 5813 | { |
| 5814 | inst.operands[i].preind = 1; |
| 5815 | |
| 5816 | if (*p == '+') p++; |
| 5817 | else if (*p == '-') p++, inst.operands[i].negative = 1; |
| 5818 | |
| 5819 | enum arm_reg_type rtype = REG_TYPE_MQ; |
| 5820 | struct neon_type_el et; |
| 5821 | if (group_type == GROUP_MVE |
| 5822 | && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL) |
| 5823 | { |
| 5824 | inst.operands[i].immisreg = 2; |
| 5825 | inst.operands[i].imm = reg; |
| 5826 | |
| 5827 | if (skip_past_comma (&p) == SUCCESS) |
| 5828 | { |
| 5829 | if (parse_shift (&p, i, SHIFT_UXTW_IMMEDIATE) == SUCCESS) |
| 5830 | { |
| 5831 | inst.operands[i].imm |= inst.relocs[0].exp.X_add_number << 5; |
| 5832 | inst.relocs[0].exp.X_add_number = 0; |
| 5833 | } |
| 5834 | else |
| 5835 | return PARSE_OPERAND_FAIL; |
| 5836 | } |
| 5837 | } |
| 5838 | else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
| 5839 | { |
| 5840 | inst.operands[i].imm = reg; |
| 5841 | inst.operands[i].immisreg = 1; |
| 5842 | |
| 5843 | if (skip_past_comma (&p) == SUCCESS) |
| 5844 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) |
| 5845 | return PARSE_OPERAND_FAIL; |
| 5846 | } |
| 5847 | else if (skip_past_char (&p, ':') == SUCCESS) |
| 5848 | { |
| 5849 | /* FIXME: '@' should be used here, but it's filtered out by generic |
| 5850 | code before we get to see it here. This may be subject to |
| 5851 | change. */ |
| 5852 | parse_operand_result result = parse_neon_alignment (&p, i); |
| 5853 | |
| 5854 | if (result != PARSE_OPERAND_SUCCESS) |
| 5855 | return result; |
| 5856 | } |
| 5857 | else |
| 5858 | { |
| 5859 | if (inst.operands[i].negative) |
| 5860 | { |
| 5861 | inst.operands[i].negative = 0; |
| 5862 | p--; |
| 5863 | } |
| 5864 | |
| 5865 | if (group_relocations |
| 5866 | && ((*p == '#' && *(p + 1) == ':') || *p == ':')) |
| 5867 | { |
| 5868 | struct group_reloc_table_entry *entry; |
| 5869 | |
| 5870 | /* Skip over the #: or : sequence. */ |
| 5871 | if (*p == '#') |
| 5872 | p += 2; |
| 5873 | else |
| 5874 | p++; |
| 5875 | |
| 5876 | /* Try to parse a group relocation. Anything else is an |
| 5877 | error. */ |
| 5878 | if (find_group_reloc_table_entry (&p, &entry) == FAIL) |
| 5879 | { |
| 5880 | inst.error = _("unknown group relocation"); |
| 5881 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; |
| 5882 | } |
| 5883 | |
| 5884 | /* We now have the group relocation table entry corresponding to |
| 5885 | the name in the assembler source. Next, we parse the |
| 5886 | expression. */ |
| 5887 | if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX)) |
| 5888 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; |
| 5889 | |
| 5890 | /* Record the relocation type. */ |
| 5891 | switch (group_type) |
| 5892 | { |
| 5893 | case GROUP_LDR: |
| 5894 | inst.relocs[0].type |
| 5895 | = (bfd_reloc_code_real_type) entry->ldr_code; |
| 5896 | break; |
| 5897 | |
| 5898 | case GROUP_LDRS: |
| 5899 | inst.relocs[0].type |
| 5900 | = (bfd_reloc_code_real_type) entry->ldrs_code; |
| 5901 | break; |
| 5902 | |
| 5903 | case GROUP_LDC: |
| 5904 | inst.relocs[0].type |
| 5905 | = (bfd_reloc_code_real_type) entry->ldc_code; |
| 5906 | break; |
| 5907 | |
| 5908 | default: |
| 5909 | gas_assert (0); |
| 5910 | } |
| 5911 | |
| 5912 | if (inst.relocs[0].type == 0) |
| 5913 | { |
| 5914 | inst.error = _("this group relocation is not allowed on this instruction"); |
| 5915 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; |
| 5916 | } |
| 5917 | } |
| 5918 | else |
| 5919 | { |
| 5920 | char *q = p; |
| 5921 | |
| 5922 | if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX)) |
| 5923 | return PARSE_OPERAND_FAIL; |
| 5924 | /* If the offset is 0, find out if it's a +0 or -0. */ |
| 5925 | if (inst.relocs[0].exp.X_op == O_constant |
| 5926 | && inst.relocs[0].exp.X_add_number == 0) |
| 5927 | { |
| 5928 | skip_whitespace (q); |
| 5929 | if (*q == '#') |
| 5930 | { |
| 5931 | q++; |
| 5932 | skip_whitespace (q); |
| 5933 | } |
| 5934 | if (*q == '-') |
| 5935 | inst.operands[i].negative = 1; |
| 5936 | } |
| 5937 | } |
| 5938 | } |
| 5939 | } |
| 5940 | else if (skip_past_char (&p, ':') == SUCCESS) |
| 5941 | { |
| 5942 | /* FIXME: '@' should be used here, but it's filtered out by generic code |
| 5943 | before we get to see it here. This may be subject to change. */ |
| 5944 | parse_operand_result result = parse_neon_alignment (&p, i); |
| 5945 | |
| 5946 | if (result != PARSE_OPERAND_SUCCESS) |
| 5947 | return result; |
| 5948 | } |
| 5949 | |
| 5950 | if (skip_past_char (&p, ']') == FAIL) |
| 5951 | { |
| 5952 | inst.error = _("']' expected"); |
| 5953 | return PARSE_OPERAND_FAIL; |
| 5954 | } |
| 5955 | |
| 5956 | if (skip_past_char (&p, '!') == SUCCESS) |
| 5957 | inst.operands[i].writeback = 1; |
| 5958 | |
| 5959 | else if (skip_past_comma (&p) == SUCCESS) |
| 5960 | { |
| 5961 | if (skip_past_char (&p, '{') == SUCCESS) |
| 5962 | { |
| 5963 | /* [Rn], {expr} - unindexed, with option */ |
| 5964 | if (parse_immediate (&p, &inst.operands[i].imm, |
| 5965 | 0, 255, TRUE) == FAIL) |
| 5966 | return PARSE_OPERAND_FAIL; |
| 5967 | |
| 5968 | if (skip_past_char (&p, '}') == FAIL) |
| 5969 | { |
| 5970 | inst.error = _("'}' expected at end of 'option' field"); |
| 5971 | return PARSE_OPERAND_FAIL; |
| 5972 | } |
| 5973 | if (inst.operands[i].preind) |
| 5974 | { |
| 5975 | inst.error = _("cannot combine index with option"); |
| 5976 | return PARSE_OPERAND_FAIL; |
| 5977 | } |
| 5978 | *str = p; |
| 5979 | return PARSE_OPERAND_SUCCESS; |
| 5980 | } |
| 5981 | else |
| 5982 | { |
| 5983 | inst.operands[i].postind = 1; |
| 5984 | inst.operands[i].writeback = 1; |
| 5985 | |
| 5986 | if (inst.operands[i].preind) |
| 5987 | { |
| 5988 | inst.error = _("cannot combine pre- and post-indexing"); |
| 5989 | return PARSE_OPERAND_FAIL; |
| 5990 | } |
| 5991 | |
| 5992 | if (*p == '+') p++; |
| 5993 | else if (*p == '-') p++, inst.operands[i].negative = 1; |
| 5994 | |
| 5995 | enum arm_reg_type rtype = REG_TYPE_MQ; |
| 5996 | struct neon_type_el et; |
| 5997 | if (group_type == GROUP_MVE |
| 5998 | && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL) |
| 5999 | { |
| 6000 | inst.operands[i].immisreg = 2; |
| 6001 | inst.operands[i].imm = reg; |
| 6002 | } |
| 6003 | else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
| 6004 | { |
| 6005 | /* We might be using the immediate for alignment already. If we |
| 6006 | are, OR the register number into the low-order bits. */ |
| 6007 | if (inst.operands[i].immisalign) |
| 6008 | inst.operands[i].imm |= reg; |
| 6009 | else |
| 6010 | inst.operands[i].imm = reg; |
| 6011 | inst.operands[i].immisreg = 1; |
| 6012 | |
| 6013 | if (skip_past_comma (&p) == SUCCESS) |
| 6014 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) |
| 6015 | return PARSE_OPERAND_FAIL; |
| 6016 | } |
| 6017 | else |
| 6018 | { |
| 6019 | char *q = p; |
| 6020 | |
| 6021 | if (inst.operands[i].negative) |
| 6022 | { |
| 6023 | inst.operands[i].negative = 0; |
| 6024 | p--; |
| 6025 | } |
| 6026 | if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX)) |
| 6027 | return PARSE_OPERAND_FAIL; |
| 6028 | /* If the offset is 0, find out if it's a +0 or -0. */ |
| 6029 | if (inst.relocs[0].exp.X_op == O_constant |
| 6030 | && inst.relocs[0].exp.X_add_number == 0) |
| 6031 | { |
| 6032 | skip_whitespace (q); |
| 6033 | if (*q == '#') |
| 6034 | { |
| 6035 | q++; |
| 6036 | skip_whitespace (q); |
| 6037 | } |
| 6038 | if (*q == '-') |
| 6039 | inst.operands[i].negative = 1; |
| 6040 | } |
| 6041 | } |
| 6042 | } |
| 6043 | } |
| 6044 | |
| 6045 | /* If at this point neither .preind nor .postind is set, we have a |
| 6046 | bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ |
| 6047 | if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) |
| 6048 | { |
| 6049 | inst.operands[i].preind = 1; |
| 6050 | inst.relocs[0].exp.X_op = O_constant; |
| 6051 | inst.relocs[0].exp.X_add_number = 0; |
| 6052 | } |
| 6053 | *str = p; |
| 6054 | return PARSE_OPERAND_SUCCESS; |
| 6055 | } |
| 6056 | |
| 6057 | static int |
| 6058 | parse_address (char **str, int i) |
| 6059 | { |
| 6060 | return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS |
| 6061 | ? SUCCESS : FAIL; |
| 6062 | } |
| 6063 | |
| 6064 | static parse_operand_result |
| 6065 | parse_address_group_reloc (char **str, int i, group_reloc_type type) |
| 6066 | { |
| 6067 | return parse_address_main (str, i, 1, type); |
| 6068 | } |
| 6069 | |
| 6070 | /* Parse an operand for a MOVW or MOVT instruction. */ |
| 6071 | static int |
| 6072 | parse_half (char **str) |
| 6073 | { |
| 6074 | char * p; |
| 6075 | |
| 6076 | p = *str; |
| 6077 | skip_past_char (&p, '#'); |
| 6078 | if (strncasecmp (p, ":lower16:", 9) == 0) |
| 6079 | inst.relocs[0].type = BFD_RELOC_ARM_MOVW; |
| 6080 | else if (strncasecmp (p, ":upper16:", 9) == 0) |
| 6081 | inst.relocs[0].type = BFD_RELOC_ARM_MOVT; |
| 6082 | |
| 6083 | if (inst.relocs[0].type != BFD_RELOC_UNUSED) |
| 6084 | { |
| 6085 | p += 9; |
| 6086 | skip_whitespace (p); |
| 6087 | } |
| 6088 | |
| 6089 | if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX)) |
| 6090 | return FAIL; |
| 6091 | |
| 6092 | if (inst.relocs[0].type == BFD_RELOC_UNUSED) |
| 6093 | { |
| 6094 | if (inst.relocs[0].exp.X_op != O_constant) |
| 6095 | { |
| 6096 | inst.error = _("constant expression expected"); |
| 6097 | return FAIL; |
| 6098 | } |
| 6099 | if (inst.relocs[0].exp.X_add_number < 0 |
| 6100 | || inst.relocs[0].exp.X_add_number > 0xffff) |
| 6101 | { |
| 6102 | inst.error = _("immediate value out of range"); |
| 6103 | return FAIL; |
| 6104 | } |
| 6105 | } |
| 6106 | *str = p; |
| 6107 | return SUCCESS; |
| 6108 | } |
| 6109 | |
| 6110 | /* Miscellaneous. */ |
| 6111 | |
| 6112 | /* Parse a PSR flag operand. The value returned is FAIL on syntax error, |
| 6113 | or a bitmask suitable to be or-ed into the ARM msr instruction. */ |
| 6114 | static int |
| 6115 | parse_psr (char **str, bfd_boolean lhs) |
| 6116 | { |
| 6117 | char *p; |
| 6118 | unsigned long psr_field; |
| 6119 | const struct asm_psr *psr; |
| 6120 | char *start; |
| 6121 | bfd_boolean is_apsr = FALSE; |
| 6122 | bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m); |
| 6123 | |
| 6124 | /* PR gas/12698: If the user has specified -march=all then m_profile will |
| 6125 | be TRUE, but we want to ignore it in this case as we are building for any |
| 6126 | CPU type, including non-m variants. */ |
| 6127 | if (ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any)) |
| 6128 | m_profile = FALSE; |
| 6129 | |
| 6130 | /* CPSR's and SPSR's can now be lowercase. This is just a convenience |
| 6131 | feature for ease of use and backwards compatibility. */ |
| 6132 | p = *str; |
| 6133 | if (strncasecmp (p, "SPSR", 4) == 0) |
| 6134 | { |
| 6135 | if (m_profile) |
| 6136 | goto unsupported_psr; |
| 6137 | |
| 6138 | psr_field = SPSR_BIT; |
| 6139 | } |
| 6140 | else if (strncasecmp (p, "CPSR", 4) == 0) |
| 6141 | { |
| 6142 | if (m_profile) |
| 6143 | goto unsupported_psr; |
| 6144 | |
| 6145 | psr_field = 0; |
| 6146 | } |
| 6147 | else if (strncasecmp (p, "APSR", 4) == 0) |
| 6148 | { |
| 6149 | /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A |
| 6150 | and ARMv7-R architecture CPUs. */ |
| 6151 | is_apsr = TRUE; |
| 6152 | psr_field = 0; |
| 6153 | } |
| 6154 | else if (m_profile) |
| 6155 | { |
| 6156 | start = p; |
| 6157 | do |
| 6158 | p++; |
| 6159 | while (ISALNUM (*p) || *p == '_'); |
| 6160 | |
| 6161 | if (strncasecmp (start, "iapsr", 5) == 0 |
| 6162 | || strncasecmp (start, "eapsr", 5) == 0 |
| 6163 | || strncasecmp (start, "xpsr", 4) == 0 |
| 6164 | || strncasecmp (start, "psr", 3) == 0) |
| 6165 | p = start + strcspn (start, "rR") + 1; |
| 6166 | |
| 6167 | psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start, |
| 6168 | p - start); |
| 6169 | |
| 6170 | if (!psr) |
| 6171 | return FAIL; |
| 6172 | |
| 6173 | /* If APSR is being written, a bitfield may be specified. Note that |
| 6174 | APSR itself is handled above. */ |
| 6175 | if (psr->field <= 3) |
| 6176 | { |
| 6177 | psr_field = psr->field; |
| 6178 | is_apsr = TRUE; |
| 6179 | goto check_suffix; |
| 6180 | } |
| 6181 | |
| 6182 | *str = p; |
| 6183 | /* M-profile MSR instructions have the mask field set to "10", except |
| 6184 | *PSR variants which modify APSR, which may use a different mask (and |
| 6185 | have been handled already). Do that by setting the PSR_f field |
| 6186 | here. */ |
| 6187 | return psr->field | (lhs ? PSR_f : 0); |
| 6188 | } |
| 6189 | else |
| 6190 | goto unsupported_psr; |
| 6191 | |
| 6192 | p += 4; |
| 6193 | check_suffix: |
| 6194 | if (*p == '_') |
| 6195 | { |
| 6196 | /* A suffix follows. */ |
| 6197 | p++; |
| 6198 | start = p; |
| 6199 | |
| 6200 | do |
| 6201 | p++; |
| 6202 | while (ISALNUM (*p) || *p == '_'); |
| 6203 | |
| 6204 | if (is_apsr) |
| 6205 | { |
| 6206 | /* APSR uses a notation for bits, rather than fields. */ |
| 6207 | unsigned int nzcvq_bits = 0; |
| 6208 | unsigned int g_bit = 0; |
| 6209 | char *bit; |
| 6210 | |
| 6211 | for (bit = start; bit != p; bit++) |
| 6212 | { |
| 6213 | switch (TOLOWER (*bit)) |
| 6214 | { |
| 6215 | case 'n': |
| 6216 | nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01; |
| 6217 | break; |
| 6218 | |
| 6219 | case 'z': |
| 6220 | nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02; |
| 6221 | break; |
| 6222 | |
| 6223 | case 'c': |
| 6224 | nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04; |
| 6225 | break; |
| 6226 | |
| 6227 | case 'v': |
| 6228 | nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08; |
| 6229 | break; |
| 6230 | |
| 6231 | case 'q': |
| 6232 | nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10; |
| 6233 | break; |
| 6234 | |
| 6235 | case 'g': |
| 6236 | g_bit |= (g_bit & 0x1) ? 0x2 : 0x1; |
| 6237 | break; |
| 6238 | |
| 6239 | default: |
| 6240 | inst.error = _("unexpected bit specified after APSR"); |
| 6241 | return FAIL; |
| 6242 | } |
| 6243 | } |
| 6244 | |
| 6245 | if (nzcvq_bits == 0x1f) |
| 6246 | psr_field |= PSR_f; |
| 6247 | |
| 6248 | if (g_bit == 0x1) |
| 6249 | { |
| 6250 | if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)) |
| 6251 | { |
| 6252 | inst.error = _("selected processor does not " |
| 6253 | "support DSP extension"); |
| 6254 | return FAIL; |
| 6255 | } |
| 6256 | |
| 6257 | psr_field |= PSR_s; |
| 6258 | } |
| 6259 | |
| 6260 | if ((nzcvq_bits & 0x20) != 0 |
| 6261 | || (nzcvq_bits != 0x1f && nzcvq_bits != 0) |
| 6262 | || (g_bit & 0x2) != 0) |
| 6263 | { |
| 6264 | inst.error = _("bad bitmask specified after APSR"); |
| 6265 | return FAIL; |
| 6266 | } |
| 6267 | } |
| 6268 | else |
| 6269 | { |
| 6270 | psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start, |
| 6271 | p - start); |
| 6272 | if (!psr) |
| 6273 | goto error; |
| 6274 | |
| 6275 | psr_field |= psr->field; |
| 6276 | } |
| 6277 | } |
| 6278 | else |
| 6279 | { |
| 6280 | if (ISALNUM (*p)) |
| 6281 | goto error; /* Garbage after "[CS]PSR". */ |
| 6282 | |
| 6283 | /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This |
| 6284 | is deprecated, but allow it anyway. */ |
| 6285 | if (is_apsr && lhs) |
| 6286 | { |
| 6287 | psr_field |= PSR_f; |
| 6288 | as_tsktsk (_("writing to APSR without specifying a bitmask is " |
| 6289 | "deprecated")); |
| 6290 | } |
| 6291 | else if (!m_profile) |
| 6292 | /* These bits are never right for M-profile devices: don't set them |
| 6293 | (only code paths which read/write APSR reach here). */ |
| 6294 | psr_field |= (PSR_c | PSR_f); |
| 6295 | } |
| 6296 | *str = p; |
| 6297 | return psr_field; |
| 6298 | |
| 6299 | unsupported_psr: |
| 6300 | inst.error = _("selected processor does not support requested special " |
| 6301 | "purpose register"); |
| 6302 | return FAIL; |
| 6303 | |
| 6304 | error: |
| 6305 | inst.error = _("flag for {c}psr instruction expected"); |
| 6306 | return FAIL; |
| 6307 | } |
| 6308 | |
| 6309 | static int |
| 6310 | parse_sys_vldr_vstr (char **str) |
| 6311 | { |
| 6312 | unsigned i; |
| 6313 | int val = FAIL; |
| 6314 | struct { |
| 6315 | const char *name; |
| 6316 | int regl; |
| 6317 | int regh; |
| 6318 | } sysregs[] = { |
| 6319 | {"FPSCR", 0x1, 0x0}, |
| 6320 | {"FPSCR_nzcvqc", 0x2, 0x0}, |
| 6321 | {"VPR", 0x4, 0x1}, |
| 6322 | {"P0", 0x5, 0x1}, |
| 6323 | {"FPCXTNS", 0x6, 0x1}, |
| 6324 | {"FPCXTS", 0x7, 0x1} |
| 6325 | }; |
| 6326 | char *op_end = strchr (*str, ','); |
| 6327 | size_t op_strlen = op_end - *str; |
| 6328 | |
| 6329 | for (i = 0; i < sizeof (sysregs) / sizeof (sysregs[0]); i++) |
| 6330 | { |
| 6331 | if (!strncmp (*str, sysregs[i].name, op_strlen)) |
| 6332 | { |
| 6333 | val = sysregs[i].regl | (sysregs[i].regh << 3); |
| 6334 | *str = op_end; |
| 6335 | break; |
| 6336 | } |
| 6337 | } |
| 6338 | |
| 6339 | return val; |
| 6340 | } |
| 6341 | |
| 6342 | /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a |
| 6343 | value suitable for splatting into the AIF field of the instruction. */ |
| 6344 | |
| 6345 | static int |
| 6346 | parse_cps_flags (char **str) |
| 6347 | { |
| 6348 | int val = 0; |
| 6349 | int saw_a_flag = 0; |
| 6350 | char *s = *str; |
| 6351 | |
| 6352 | for (;;) |
| 6353 | switch (*s++) |
| 6354 | { |
| 6355 | case '\0': case ',': |
| 6356 | goto done; |
| 6357 | |
| 6358 | case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; |
| 6359 | case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; |
| 6360 | case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; |
| 6361 | |
| 6362 | default: |
| 6363 | inst.error = _("unrecognized CPS flag"); |
| 6364 | return FAIL; |
| 6365 | } |
| 6366 | |
| 6367 | done: |
| 6368 | if (saw_a_flag == 0) |
| 6369 | { |
| 6370 | inst.error = _("missing CPS flags"); |
| 6371 | return FAIL; |
| 6372 | } |
| 6373 | |
| 6374 | *str = s - 1; |
| 6375 | return val; |
| 6376 | } |
| 6377 | |
| 6378 | /* Parse an endian specifier ("BE" or "LE", case insensitive); |
| 6379 | returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ |
| 6380 | |
| 6381 | static int |
| 6382 | parse_endian_specifier (char **str) |
| 6383 | { |
| 6384 | int little_endian; |
| 6385 | char *s = *str; |
| 6386 | |
| 6387 | if (strncasecmp (s, "BE", 2)) |
| 6388 | little_endian = 0; |
| 6389 | else if (strncasecmp (s, "LE", 2)) |
| 6390 | little_endian = 1; |
| 6391 | else |
| 6392 | { |
| 6393 | inst.error = _("valid endian specifiers are be or le"); |
| 6394 | return FAIL; |
| 6395 | } |
| 6396 | |
| 6397 | if (ISALNUM (s[2]) || s[2] == '_') |
| 6398 | { |
| 6399 | inst.error = _("valid endian specifiers are be or le"); |
| 6400 | return FAIL; |
| 6401 | } |
| 6402 | |
| 6403 | *str = s + 2; |
| 6404 | return little_endian; |
| 6405 | } |
| 6406 | |
| 6407 | /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a |
| 6408 | value suitable for poking into the rotate field of an sxt or sxta |
| 6409 | instruction, or FAIL on error. */ |
| 6410 | |
| 6411 | static int |
| 6412 | parse_ror (char **str) |
| 6413 | { |
| 6414 | int rot; |
| 6415 | char *s = *str; |
| 6416 | |
| 6417 | if (strncasecmp (s, "ROR", 3) == 0) |
| 6418 | s += 3; |
| 6419 | else |
| 6420 | { |
| 6421 | inst.error = _("missing rotation field after comma"); |
| 6422 | return FAIL; |
| 6423 | } |
| 6424 | |
| 6425 | if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) |
| 6426 | return FAIL; |
| 6427 | |
| 6428 | switch (rot) |
| 6429 | { |
| 6430 | case 0: *str = s; return 0x0; |
| 6431 | case 8: *str = s; return 0x1; |
| 6432 | case 16: *str = s; return 0x2; |
| 6433 | case 24: *str = s; return 0x3; |
| 6434 | |
| 6435 | default: |
| 6436 | inst.error = _("rotation can only be 0, 8, 16, or 24"); |
| 6437 | return FAIL; |
| 6438 | } |
| 6439 | } |
| 6440 | |
| 6441 | /* Parse a conditional code (from conds[] below). The value returned is in the |
| 6442 | range 0 .. 14, or FAIL. */ |
| 6443 | static int |
| 6444 | parse_cond (char **str) |
| 6445 | { |
| 6446 | char *q; |
| 6447 | const struct asm_cond *c; |
| 6448 | int n; |
| 6449 | /* Condition codes are always 2 characters, so matching up to |
| 6450 | 3 characters is sufficient. */ |
| 6451 | char cond[3]; |
| 6452 | |
| 6453 | q = *str; |
| 6454 | n = 0; |
| 6455 | while (ISALPHA (*q) && n < 3) |
| 6456 | { |
| 6457 | cond[n] = TOLOWER (*q); |
| 6458 | q++; |
| 6459 | n++; |
| 6460 | } |
| 6461 | |
| 6462 | c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n); |
| 6463 | if (!c) |
| 6464 | { |
| 6465 | inst.error = _("condition required"); |
| 6466 | return FAIL; |
| 6467 | } |
| 6468 | |
| 6469 | *str = q; |
| 6470 | return c->value; |
| 6471 | } |
| 6472 | |
| 6473 | /* Parse an option for a barrier instruction. Returns the encoding for the |
| 6474 | option, or FAIL. */ |
| 6475 | static int |
| 6476 | parse_barrier (char **str) |
| 6477 | { |
| 6478 | char *p, *q; |
| 6479 | const struct asm_barrier_opt *o; |
| 6480 | |
| 6481 | p = q = *str; |
| 6482 | while (ISALPHA (*q)) |
| 6483 | q++; |
| 6484 | |
| 6485 | o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p, |
| 6486 | q - p); |
| 6487 | if (!o) |
| 6488 | return FAIL; |
| 6489 | |
| 6490 | if (!mark_feature_used (&o->arch)) |
| 6491 | return FAIL; |
| 6492 | |
| 6493 | *str = q; |
| 6494 | return o->value; |
| 6495 | } |
| 6496 | |
| 6497 | /* Parse the operands of a table branch instruction. Similar to a memory |
| 6498 | operand. */ |
| 6499 | static int |
| 6500 | parse_tb (char **str) |
| 6501 | { |
| 6502 | char * p = *str; |
| 6503 | int reg; |
| 6504 | |
| 6505 | if (skip_past_char (&p, '[') == FAIL) |
| 6506 | { |
| 6507 | inst.error = _("'[' expected"); |
| 6508 | return FAIL; |
| 6509 | } |
| 6510 | |
| 6511 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
| 6512 | { |
| 6513 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); |
| 6514 | return FAIL; |
| 6515 | } |
| 6516 | inst.operands[0].reg = reg; |
| 6517 | |
| 6518 | if (skip_past_comma (&p) == FAIL) |
| 6519 | { |
| 6520 | inst.error = _("',' expected"); |
| 6521 | return FAIL; |
| 6522 | } |
| 6523 | |
| 6524 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
| 6525 | { |
| 6526 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); |
| 6527 | return FAIL; |
| 6528 | } |
| 6529 | inst.operands[0].imm = reg; |
| 6530 | |
| 6531 | if (skip_past_comma (&p) == SUCCESS) |
| 6532 | { |
| 6533 | if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) |
| 6534 | return FAIL; |
| 6535 | if (inst.relocs[0].exp.X_add_number != 1) |
| 6536 | { |
| 6537 | inst.error = _("invalid shift"); |
| 6538 | return FAIL; |
| 6539 | } |
| 6540 | inst.operands[0].shifted = 1; |
| 6541 | } |
| 6542 | |
| 6543 | if (skip_past_char (&p, ']') == FAIL) |
| 6544 | { |
| 6545 | inst.error = _("']' expected"); |
| 6546 | return FAIL; |
| 6547 | } |
| 6548 | *str = p; |
| 6549 | return SUCCESS; |
| 6550 | } |
| 6551 | |
| 6552 | /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more |
| 6553 | information on the types the operands can take and how they are encoded. |
| 6554 | Up to four operands may be read; this function handles setting the |
| 6555 | ".present" field for each read operand itself. |
| 6556 | Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, |
| 6557 | else returns FAIL. */ |
| 6558 | |
| 6559 | static int |
| 6560 | parse_neon_mov (char **str, int *which_operand) |
| 6561 | { |
| 6562 | int i = *which_operand, val; |
| 6563 | enum arm_reg_type rtype; |
| 6564 | char *ptr = *str; |
| 6565 | struct neon_type_el optype; |
| 6566 | |
| 6567 | if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL) |
| 6568 | { |
| 6569 | /* Cases 17 or 19. */ |
| 6570 | inst.operands[i].reg = val; |
| 6571 | inst.operands[i].isvec = 1; |
| 6572 | inst.operands[i].isscalar = 2; |
| 6573 | inst.operands[i].vectype = optype; |
| 6574 | inst.operands[i++].present = 1; |
| 6575 | |
| 6576 | if (skip_past_comma (&ptr) == FAIL) |
| 6577 | goto wanted_comma; |
| 6578 | |
| 6579 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
| 6580 | { |
| 6581 | /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */ |
| 6582 | inst.operands[i].reg = val; |
| 6583 | inst.operands[i].isreg = 1; |
| 6584 | inst.operands[i].present = 1; |
| 6585 | } |
| 6586 | else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL) |
| 6587 | { |
| 6588 | /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */ |
| 6589 | inst.operands[i].reg = val; |
| 6590 | inst.operands[i].isvec = 1; |
| 6591 | inst.operands[i].isscalar = 2; |
| 6592 | inst.operands[i].vectype = optype; |
| 6593 | inst.operands[i++].present = 1; |
| 6594 | |
| 6595 | if (skip_past_comma (&ptr) == FAIL) |
| 6596 | goto wanted_comma; |
| 6597 | |
| 6598 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
| 6599 | goto wanted_arm; |
| 6600 | |
| 6601 | inst.operands[i].reg = val; |
| 6602 | inst.operands[i].isreg = 1; |
| 6603 | inst.operands[i++].present = 1; |
| 6604 | |
| 6605 | if (skip_past_comma (&ptr) == FAIL) |
| 6606 | goto wanted_comma; |
| 6607 | |
| 6608 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
| 6609 | goto wanted_arm; |
| 6610 | |
| 6611 | inst.operands[i].reg = val; |
| 6612 | inst.operands[i].isreg = 1; |
| 6613 | inst.operands[i].present = 1; |
| 6614 | } |
| 6615 | else |
| 6616 | { |
| 6617 | first_error (_("expected ARM or MVE vector register")); |
| 6618 | return FAIL; |
| 6619 | } |
| 6620 | } |
| 6621 | else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_VFD)) != FAIL) |
| 6622 | { |
| 6623 | /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ |
| 6624 | inst.operands[i].reg = val; |
| 6625 | inst.operands[i].isscalar = 1; |
| 6626 | inst.operands[i].vectype = optype; |
| 6627 | inst.operands[i++].present = 1; |
| 6628 | |
| 6629 | if (skip_past_comma (&ptr) == FAIL) |
| 6630 | goto wanted_comma; |
| 6631 | |
| 6632 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
| 6633 | goto wanted_arm; |
| 6634 | |
| 6635 | inst.operands[i].reg = val; |
| 6636 | inst.operands[i].isreg = 1; |
| 6637 | inst.operands[i].present = 1; |
| 6638 | } |
| 6639 | else if (((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) |
| 6640 | != FAIL) |
| 6641 | || ((val = arm_typed_reg_parse (&ptr, REG_TYPE_MQ, &rtype, &optype)) |
| 6642 | != FAIL)) |
| 6643 | { |
| 6644 | /* Cases 0, 1, 2, 3, 5 (D only). */ |
| 6645 | if (skip_past_comma (&ptr) == FAIL) |
| 6646 | goto wanted_comma; |
| 6647 | |
| 6648 | inst.operands[i].reg = val; |
| 6649 | inst.operands[i].isreg = 1; |
| 6650 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); |
| 6651 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
| 6652 | inst.operands[i].isvec = 1; |
| 6653 | inst.operands[i].vectype = optype; |
| 6654 | inst.operands[i++].present = 1; |
| 6655 | |
| 6656 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
| 6657 | { |
| 6658 | /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. |
| 6659 | Case 13: VMOV <Sd>, <Rm> */ |
| 6660 | inst.operands[i].reg = val; |
| 6661 | inst.operands[i].isreg = 1; |
| 6662 | inst.operands[i].present = 1; |
| 6663 | |
| 6664 | if (rtype == REG_TYPE_NQ) |
| 6665 | { |
| 6666 | first_error (_("can't use Neon quad register here")); |
| 6667 | return FAIL; |
| 6668 | } |
| 6669 | else if (rtype != REG_TYPE_VFS) |
| 6670 | { |
| 6671 | i++; |
| 6672 | if (skip_past_comma (&ptr) == FAIL) |
| 6673 | goto wanted_comma; |
| 6674 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
| 6675 | goto wanted_arm; |
| 6676 | inst.operands[i].reg = val; |
| 6677 | inst.operands[i].isreg = 1; |
| 6678 | inst.operands[i].present = 1; |
| 6679 | } |
| 6680 | } |
| 6681 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, |
| 6682 | &optype)) != FAIL) |
| 6683 | { |
| 6684 | /* Case 0: VMOV<c><q> <Qd>, <Qm> |
| 6685 | Case 1: VMOV<c><q> <Dd>, <Dm> |
| 6686 | Case 8: VMOV.F32 <Sd>, <Sm> |
| 6687 | Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */ |
| 6688 | |
| 6689 | inst.operands[i].reg = val; |
| 6690 | inst.operands[i].isreg = 1; |
| 6691 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); |
| 6692 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
| 6693 | inst.operands[i].isvec = 1; |
| 6694 | inst.operands[i].vectype = optype; |
| 6695 | inst.operands[i].present = 1; |
| 6696 | |
| 6697 | if (skip_past_comma (&ptr) == SUCCESS) |
| 6698 | { |
| 6699 | /* Case 15. */ |
| 6700 | i++; |
| 6701 | |
| 6702 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
| 6703 | goto wanted_arm; |
| 6704 | |
| 6705 | inst.operands[i].reg = val; |
| 6706 | inst.operands[i].isreg = 1; |
| 6707 | inst.operands[i++].present = 1; |
| 6708 | |
| 6709 | if (skip_past_comma (&ptr) == FAIL) |
| 6710 | goto wanted_comma; |
| 6711 | |
| 6712 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
| 6713 | goto wanted_arm; |
| 6714 | |
| 6715 | inst.operands[i].reg = val; |
| 6716 | inst.operands[i].isreg = 1; |
| 6717 | inst.operands[i].present = 1; |
| 6718 | } |
| 6719 | } |
| 6720 | else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) |
| 6721 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm> |
| 6722 | Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm> |
| 6723 | Case 10: VMOV.F32 <Sd>, #<imm> |
| 6724 | Case 11: VMOV.F64 <Dd>, #<imm> */ |
| 6725 | inst.operands[i].immisfloat = 1; |
| 6726 | else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/FALSE) |
| 6727 | == SUCCESS) |
| 6728 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm> |
| 6729 | Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */ |
| 6730 | ; |
| 6731 | else |
| 6732 | { |
| 6733 | first_error (_("expected <Rm> or <Dm> or <Qm> operand")); |
| 6734 | return FAIL; |
| 6735 | } |
| 6736 | } |
| 6737 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
| 6738 | { |
| 6739 | /* Cases 6, 7, 16, 18. */ |
| 6740 | inst.operands[i].reg = val; |
| 6741 | inst.operands[i].isreg = 1; |
| 6742 | inst.operands[i++].present = 1; |
| 6743 | |
| 6744 | if (skip_past_comma (&ptr) == FAIL) |
| 6745 | goto wanted_comma; |
| 6746 | |
| 6747 | if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL) |
| 6748 | { |
| 6749 | /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */ |
| 6750 | inst.operands[i].reg = val; |
| 6751 | inst.operands[i].isscalar = 2; |
| 6752 | inst.operands[i].present = 1; |
| 6753 | inst.operands[i].vectype = optype; |
| 6754 | } |
| 6755 | else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_VFD)) != FAIL) |
| 6756 | { |
| 6757 | /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ |
| 6758 | inst.operands[i].reg = val; |
| 6759 | inst.operands[i].isscalar = 1; |
| 6760 | inst.operands[i].present = 1; |
| 6761 | inst.operands[i].vectype = optype; |
| 6762 | } |
| 6763 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
| 6764 | { |
| 6765 | inst.operands[i].reg = val; |
| 6766 | inst.operands[i].isreg = 1; |
| 6767 | inst.operands[i++].present = 1; |
| 6768 | |
| 6769 | if (skip_past_comma (&ptr) == FAIL) |
| 6770 | goto wanted_comma; |
| 6771 | |
| 6772 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) |
| 6773 | != FAIL) |
| 6774 | { |
| 6775 | /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ |
| 6776 | |
| 6777 | inst.operands[i].reg = val; |
| 6778 | inst.operands[i].isreg = 1; |
| 6779 | inst.operands[i].isvec = 1; |
| 6780 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
| 6781 | inst.operands[i].vectype = optype; |
| 6782 | inst.operands[i].present = 1; |
| 6783 | |
| 6784 | if (rtype == REG_TYPE_VFS) |
| 6785 | { |
| 6786 | /* Case 14. */ |
| 6787 | i++; |
| 6788 | if (skip_past_comma (&ptr) == FAIL) |
| 6789 | goto wanted_comma; |
| 6790 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, |
| 6791 | &optype)) == FAIL) |
| 6792 | { |
| 6793 | first_error (_(reg_expected_msgs[REG_TYPE_VFS])); |
| 6794 | return FAIL; |
| 6795 | } |
| 6796 | inst.operands[i].reg = val; |
| 6797 | inst.operands[i].isreg = 1; |
| 6798 | inst.operands[i].isvec = 1; |
| 6799 | inst.operands[i].issingle = 1; |
| 6800 | inst.operands[i].vectype = optype; |
| 6801 | inst.operands[i].present = 1; |
| 6802 | } |
| 6803 | } |
| 6804 | else |
| 6805 | { |
| 6806 | if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) |
| 6807 | != FAIL) |
| 6808 | { |
| 6809 | /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */ |
| 6810 | inst.operands[i].reg = val; |
| 6811 | inst.operands[i].isvec = 1; |
| 6812 | inst.operands[i].isscalar = 2; |
| 6813 | inst.operands[i].vectype = optype; |
| 6814 | inst.operands[i++].present = 1; |
| 6815 | |
| 6816 | if (skip_past_comma (&ptr) == FAIL) |
| 6817 | goto wanted_comma; |
| 6818 | |
| 6819 | if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) |
| 6820 | == FAIL) |
| 6821 | { |
| 6822 | first_error (_(reg_expected_msgs[REG_TYPE_MQ])); |
| 6823 | return FAIL; |
| 6824 | } |
| 6825 | inst.operands[i].reg = val; |
| 6826 | inst.operands[i].isvec = 1; |
| 6827 | inst.operands[i].isscalar = 2; |
| 6828 | inst.operands[i].vectype = optype; |
| 6829 | inst.operands[i].present = 1; |
| 6830 | } |
| 6831 | else |
| 6832 | { |
| 6833 | first_error (_("VFP single, double or MVE vector register" |
| 6834 | " expected")); |
| 6835 | return FAIL; |
| 6836 | } |
| 6837 | } |
| 6838 | } |
| 6839 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) |
| 6840 | != FAIL) |
| 6841 | { |
| 6842 | /* Case 13. */ |
| 6843 | inst.operands[i].reg = val; |
| 6844 | inst.operands[i].isreg = 1; |
| 6845 | inst.operands[i].isvec = 1; |
| 6846 | inst.operands[i].issingle = 1; |
| 6847 | inst.operands[i].vectype = optype; |
| 6848 | inst.operands[i].present = 1; |
| 6849 | } |
| 6850 | } |
| 6851 | else |
| 6852 | { |
| 6853 | first_error (_("parse error")); |
| 6854 | return FAIL; |
| 6855 | } |
| 6856 | |
| 6857 | /* Successfully parsed the operands. Update args. */ |
| 6858 | *which_operand = i; |
| 6859 | *str = ptr; |
| 6860 | return SUCCESS; |
| 6861 | |
| 6862 | wanted_comma: |
| 6863 | first_error (_("expected comma")); |
| 6864 | return FAIL; |
| 6865 | |
| 6866 | wanted_arm: |
| 6867 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
| 6868 | return FAIL; |
| 6869 | } |
| 6870 | |
| 6871 | /* Use this macro when the operand constraints are different |
| 6872 | for ARM and THUMB (e.g. ldrd). */ |
| 6873 | #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \ |
| 6874 | ((arm_operand) | ((thumb_operand) << 16)) |
| 6875 | |
| 6876 | /* Matcher codes for parse_operands. */ |
| 6877 | enum operand_parse_code |
| 6878 | { |
| 6879 | OP_stop, /* end of line */ |
| 6880 | |
| 6881 | OP_RR, /* ARM register */ |
| 6882 | OP_RRnpc, /* ARM register, not r15 */ |
| 6883 | OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */ |
| 6884 | OP_RRnpcb, /* ARM register, not r15, in square brackets */ |
| 6885 | OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback, |
| 6886 | optional trailing ! */ |
| 6887 | OP_RRw, /* ARM register, not r15, optional trailing ! */ |
| 6888 | OP_RCP, /* Coprocessor number */ |
| 6889 | OP_RCN, /* Coprocessor register */ |
| 6890 | OP_RF, /* FPA register */ |
| 6891 | OP_RVS, /* VFP single precision register */ |
| 6892 | OP_RVD, /* VFP double precision register (0..15) */ |
| 6893 | OP_RND, /* Neon double precision register (0..31) */ |
| 6894 | OP_RNDMQ, /* Neon double precision (0..31) or MVE vector register. */ |
| 6895 | OP_RNDMQR, /* Neon double precision (0..31), MVE vector or ARM register. |
| 6896 | */ |
| 6897 | OP_RNQ, /* Neon quad precision register */ |
| 6898 | OP_RNQMQ, /* Neon quad or MVE vector register. */ |
| 6899 | OP_RVSD, /* VFP single or double precision register */ |
| 6900 | OP_RVSD_COND, /* VFP single, double precision register or condition code. */ |
| 6901 | OP_RVSDMQ, /* VFP single, double precision or MVE vector register. */ |
| 6902 | OP_RNSD, /* Neon single or double precision register */ |
| 6903 | OP_RNDQ, /* Neon double or quad precision register */ |
| 6904 | OP_RNDQMQ, /* Neon double, quad or MVE vector register. */ |
| 6905 | OP_RNDQMQR, /* Neon double, quad, MVE vector or ARM register. */ |
| 6906 | OP_RNSDQ, /* Neon single, double or quad precision register */ |
| 6907 | OP_RNSC, /* Neon scalar D[X] */ |
| 6908 | OP_RVC, /* VFP control register */ |
| 6909 | OP_RMF, /* Maverick F register */ |
| 6910 | OP_RMD, /* Maverick D register */ |
| 6911 | OP_RMFX, /* Maverick FX register */ |
| 6912 | OP_RMDX, /* Maverick DX register */ |
| 6913 | OP_RMAX, /* Maverick AX register */ |
| 6914 | OP_RMDS, /* Maverick DSPSC register */ |
| 6915 | OP_RIWR, /* iWMMXt wR register */ |
| 6916 | OP_RIWC, /* iWMMXt wC register */ |
| 6917 | OP_RIWG, /* iWMMXt wCG register */ |
| 6918 | OP_RXA, /* XScale accumulator register */ |
| 6919 | |
| 6920 | OP_RNSDQMQ, /* Neon single, double or quad register or MVE vector register |
| 6921 | */ |
| 6922 | OP_RNSDQMQR, /* Neon single, double or quad register, MVE vector register or |
| 6923 | GPR (no SP/SP) */ |
| 6924 | OP_RMQ, /* MVE vector register. */ |
| 6925 | OP_RMQRZ, /* MVE vector or ARM register including ZR. */ |
| 6926 | OP_RMQRR, /* MVE vector or ARM register. */ |
| 6927 | |
| 6928 | /* New operands for Armv8.1-M Mainline. */ |
| 6929 | OP_LR, /* ARM LR register */ |
| 6930 | OP_RRe, /* ARM register, only even numbered. */ |
| 6931 | OP_RRo, /* ARM register, only odd numbered, not r13 or r15. */ |
| 6932 | OP_RRnpcsp_I32, /* ARM register (no BadReg) or literal 1 .. 32 */ |
| 6933 | |
| 6934 | OP_REGLST, /* ARM register list */ |
| 6935 | OP_CLRMLST, /* CLRM register list */ |
| 6936 | OP_VRSLST, /* VFP single-precision register list */ |
| 6937 | OP_VRDLST, /* VFP double-precision register list */ |
| 6938 | OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ |
| 6939 | OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ |
| 6940 | OP_NSTRLST, /* Neon element/structure list */ |
| 6941 | OP_VRSDVLST, /* VFP single or double-precision register list and VPR */ |
| 6942 | OP_MSTRLST2, /* MVE vector list with two elements. */ |
| 6943 | OP_MSTRLST4, /* MVE vector list with four elements. */ |
| 6944 | |
| 6945 | OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ |
| 6946 | OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ |
| 6947 | OP_RSVD_FI0, /* VFP S or D reg, or floating point immediate zero. */ |
| 6948 | OP_RSVDMQ_FI0, /* VFP S, D, MVE vector register or floating point immediate |
| 6949 | zero. */ |
| 6950 | OP_RR_RNSC, /* ARM reg or Neon scalar. */ |
| 6951 | OP_RNSD_RNSC, /* Neon S or D reg, or Neon scalar. */ |
| 6952 | OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ |
| 6953 | OP_RNSDQ_RNSC_MQ, /* Vector S, D or Q reg, Neon scalar or MVE vector register. |
| 6954 | */ |
| 6955 | OP_RNSDQ_RNSC_MQ_RR, /* Vector S, D or Q reg, or MVE vector reg , or Neon |
| 6956 | scalar, or ARM register. */ |
| 6957 | OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ |
| 6958 | OP_RNDQ_RNSC_RR, /* Neon D or Q reg, Neon scalar, or ARM register. */ |
| 6959 | OP_RNDQMQ_RNSC_RR, /* Neon D or Q reg, Neon scalar, MVE vector or ARM |
| 6960 | register. */ |
| 6961 | OP_RNDQMQ_RNSC, /* Neon D, Q or MVE vector reg, or Neon scalar. */ |
| 6962 | OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ |
| 6963 | OP_VMOV, /* Neon VMOV operands. */ |
| 6964 | OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */ |
| 6965 | /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */ |
| 6966 | OP_RNDQMQ_Ibig, |
| 6967 | OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ |
| 6968 | OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */ |
| 6969 | OP_VLDR, /* VLDR operand. */ |
| 6970 | |
| 6971 | OP_I0, /* immediate zero */ |
| 6972 | OP_I7, /* immediate value 0 .. 7 */ |
| 6973 | OP_I15, /* 0 .. 15 */ |
| 6974 | OP_I16, /* 1 .. 16 */ |
| 6975 | OP_I16z, /* 0 .. 16 */ |
| 6976 | OP_I31, /* 0 .. 31 */ |
| 6977 | OP_I31w, /* 0 .. 31, optional trailing ! */ |
| 6978 | OP_I32, /* 1 .. 32 */ |
| 6979 | OP_I32z, /* 0 .. 32 */ |
| 6980 | OP_I63, /* 0 .. 63 */ |
| 6981 | OP_I63s, /* -64 .. 63 */ |
| 6982 | OP_I64, /* 1 .. 64 */ |
| 6983 | OP_I64z, /* 0 .. 64 */ |
| 6984 | OP_I255, /* 0 .. 255 */ |
| 6985 | |
| 6986 | OP_I4b, /* immediate, prefix optional, 1 .. 4 */ |
| 6987 | OP_I7b, /* 0 .. 7 */ |
| 6988 | OP_I15b, /* 0 .. 15 */ |
| 6989 | OP_I31b, /* 0 .. 31 */ |
| 6990 | |
| 6991 | OP_SH, /* shifter operand */ |
| 6992 | OP_SHG, /* shifter operand with possible group relocation */ |
| 6993 | OP_ADDR, /* Memory address expression (any mode) */ |
| 6994 | OP_ADDRMVE, /* Memory address expression for MVE's VSTR/VLDR. */ |
| 6995 | OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ |
| 6996 | OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ |
| 6997 | OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ |
| 6998 | OP_EXP, /* arbitrary expression */ |
| 6999 | OP_EXPi, /* same, with optional immediate prefix */ |
| 7000 | OP_EXPr, /* same, with optional relocation suffix */ |
| 7001 | OP_EXPs, /* same, with optional non-first operand relocation suffix */ |
| 7002 | OP_HALF, /* 0 .. 65535 or low/high reloc. */ |
| 7003 | OP_IROT1, /* VCADD rotate immediate: 90, 270. */ |
| 7004 | OP_IROT2, /* VCMLA rotate immediate: 0, 90, 180, 270. */ |
| 7005 | |
| 7006 | OP_CPSF, /* CPS flags */ |
| 7007 | OP_ENDI, /* Endianness specifier */ |
| 7008 | OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */ |
| 7009 | OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */ |
| 7010 | OP_COND, /* conditional code */ |
| 7011 | OP_TB, /* Table branch. */ |
| 7012 | |
| 7013 | OP_APSR_RR, /* ARM register or "APSR_nzcv". */ |
| 7014 | |
| 7015 | OP_RRnpc_I0, /* ARM register or literal 0 */ |
| 7016 | OP_RR_EXr, /* ARM register or expression with opt. reloc stuff. */ |
| 7017 | OP_RR_EXi, /* ARM register or expression with imm prefix */ |
| 7018 | OP_RF_IF, /* FPA register or immediate */ |
| 7019 | OP_RIWR_RIWC, /* iWMMXt R or C reg */ |
| 7020 | OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ |
| 7021 | |
| 7022 | /* Optional operands. */ |
| 7023 | OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ |
| 7024 | OP_oI31b, /* 0 .. 31 */ |
| 7025 | OP_oI32b, /* 1 .. 32 */ |
| 7026 | OP_oI32z, /* 0 .. 32 */ |
| 7027 | OP_oIffffb, /* 0 .. 65535 */ |
| 7028 | OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ |
| 7029 | |
| 7030 | OP_oRR, /* ARM register */ |
| 7031 | OP_oLR, /* ARM LR register */ |
| 7032 | OP_oRRnpc, /* ARM register, not the PC */ |
| 7033 | OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */ |
| 7034 | OP_oRRw, /* ARM register, not r15, optional trailing ! */ |
| 7035 | OP_oRND, /* Optional Neon double precision register */ |
| 7036 | OP_oRNQ, /* Optional Neon quad precision register */ |
| 7037 | OP_oRNDQMQ, /* Optional Neon double, quad or MVE vector register. */ |
| 7038 | OP_oRNDQ, /* Optional Neon double or quad precision register */ |
| 7039 | OP_oRNSDQ, /* Optional single, double or quad precision vector register */ |
| 7040 | OP_oRNSDQMQ, /* Optional single, double or quad register or MVE vector |
| 7041 | register. */ |
| 7042 | OP_oSHll, /* LSL immediate */ |
| 7043 | OP_oSHar, /* ASR immediate */ |
| 7044 | OP_oSHllar, /* LSL or ASR immediate */ |
| 7045 | OP_oROR, /* ROR 0/8/16/24 */ |
| 7046 | OP_oBARRIER_I15, /* Option argument for a barrier instruction. */ |
| 7047 | |
| 7048 | OP_oRMQRZ, /* optional MVE vector or ARM register including ZR. */ |
| 7049 | |
| 7050 | /* Some pre-defined mixed (ARM/THUMB) operands. */ |
| 7051 | OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp), |
| 7052 | OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp), |
| 7053 | OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp), |
| 7054 | |
| 7055 | OP_FIRST_OPTIONAL = OP_oI7b |
| 7056 | }; |
| 7057 | |
| 7058 | /* Generic instruction operand parser. This does no encoding and no |
| 7059 | semantic validation; it merely squirrels values away in the inst |
| 7060 | structure. Returns SUCCESS or FAIL depending on whether the |
| 7061 | specified grammar matched. */ |
| 7062 | static int |
| 7063 | parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) |
| 7064 | { |
| 7065 | unsigned const int *upat = pattern; |
| 7066 | char *backtrack_pos = 0; |
| 7067 | const char *backtrack_error = 0; |
| 7068 | int i, val = 0, backtrack_index = 0; |
| 7069 | enum arm_reg_type rtype; |
| 7070 | parse_operand_result result; |
| 7071 | unsigned int op_parse_code; |
| 7072 | bfd_boolean partial_match; |
| 7073 | |
| 7074 | #define po_char_or_fail(chr) \ |
| 7075 | do \ |
| 7076 | { \ |
| 7077 | if (skip_past_char (&str, chr) == FAIL) \ |
| 7078 | goto bad_args; \ |
| 7079 | } \ |
| 7080 | while (0) |
| 7081 | |
| 7082 | #define po_reg_or_fail(regtype) \ |
| 7083 | do \ |
| 7084 | { \ |
| 7085 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ |
| 7086 | & inst.operands[i].vectype); \ |
| 7087 | if (val == FAIL) \ |
| 7088 | { \ |
| 7089 | first_error (_(reg_expected_msgs[regtype])); \ |
| 7090 | goto failure; \ |
| 7091 | } \ |
| 7092 | inst.operands[i].reg = val; \ |
| 7093 | inst.operands[i].isreg = 1; \ |
| 7094 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ |
| 7095 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ |
| 7096 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ |
| 7097 | || rtype == REG_TYPE_VFD \ |
| 7098 | || rtype == REG_TYPE_NQ); \ |
| 7099 | inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \ |
| 7100 | } \ |
| 7101 | while (0) |
| 7102 | |
| 7103 | #define po_reg_or_goto(regtype, label) \ |
| 7104 | do \ |
| 7105 | { \ |
| 7106 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ |
| 7107 | & inst.operands[i].vectype); \ |
| 7108 | if (val == FAIL) \ |
| 7109 | goto label; \ |
| 7110 | \ |
| 7111 | inst.operands[i].reg = val; \ |
| 7112 | inst.operands[i].isreg = 1; \ |
| 7113 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ |
| 7114 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ |
| 7115 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ |
| 7116 | || rtype == REG_TYPE_VFD \ |
| 7117 | || rtype == REG_TYPE_NQ); \ |
| 7118 | inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \ |
| 7119 | } \ |
| 7120 | while (0) |
| 7121 | |
| 7122 | #define po_imm_or_fail(min, max, popt) \ |
| 7123 | do \ |
| 7124 | { \ |
| 7125 | if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ |
| 7126 | goto failure; \ |
| 7127 | inst.operands[i].imm = val; \ |
| 7128 | } \ |
| 7129 | while (0) |
| 7130 | |
| 7131 | #define po_scalar_or_goto(elsz, label, reg_type) \ |
| 7132 | do \ |
| 7133 | { \ |
| 7134 | val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \ |
| 7135 | reg_type); \ |
| 7136 | if (val == FAIL) \ |
| 7137 | goto label; \ |
| 7138 | inst.operands[i].reg = val; \ |
| 7139 | inst.operands[i].isscalar = 1; \ |
| 7140 | } \ |
| 7141 | while (0) |
| 7142 | |
| 7143 | #define po_misc_or_fail(expr) \ |
| 7144 | do \ |
| 7145 | { \ |
| 7146 | if (expr) \ |
| 7147 | goto failure; \ |
| 7148 | } \ |
| 7149 | while (0) |
| 7150 | |
| 7151 | #define po_misc_or_fail_no_backtrack(expr) \ |
| 7152 | do \ |
| 7153 | { \ |
| 7154 | result = expr; \ |
| 7155 | if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \ |
| 7156 | backtrack_pos = 0; \ |
| 7157 | if (result != PARSE_OPERAND_SUCCESS) \ |
| 7158 | goto failure; \ |
| 7159 | } \ |
| 7160 | while (0) |
| 7161 | |
| 7162 | #define po_barrier_or_imm(str) \ |
| 7163 | do \ |
| 7164 | { \ |
| 7165 | val = parse_barrier (&str); \ |
| 7166 | if (val == FAIL && ! ISALPHA (*str)) \ |
| 7167 | goto immediate; \ |
| 7168 | if (val == FAIL \ |
| 7169 | /* ISB can only take SY as an option. */ \ |
| 7170 | || ((inst.instruction & 0xf0) == 0x60 \ |
| 7171 | && val != 0xf)) \ |
| 7172 | { \ |
| 7173 | inst.error = _("invalid barrier type"); \ |
| 7174 | backtrack_pos = 0; \ |
| 7175 | goto failure; \ |
| 7176 | } \ |
| 7177 | } \ |
| 7178 | while (0) |
| 7179 | |
| 7180 | skip_whitespace (str); |
| 7181 | |
| 7182 | for (i = 0; upat[i] != OP_stop; i++) |
| 7183 | { |
| 7184 | op_parse_code = upat[i]; |
| 7185 | if (op_parse_code >= 1<<16) |
| 7186 | op_parse_code = thumb ? (op_parse_code >> 16) |
| 7187 | : (op_parse_code & ((1<<16)-1)); |
| 7188 | |
| 7189 | if (op_parse_code >= OP_FIRST_OPTIONAL) |
| 7190 | { |
| 7191 | /* Remember where we are in case we need to backtrack. */ |
| 7192 | backtrack_pos = str; |
| 7193 | backtrack_error = inst.error; |
| 7194 | backtrack_index = i; |
| 7195 | } |
| 7196 | |
| 7197 | if (i > 0 && (i > 1 || inst.operands[0].present)) |
| 7198 | po_char_or_fail (','); |
| 7199 | |
| 7200 | switch (op_parse_code) |
| 7201 | { |
| 7202 | /* Registers */ |
| 7203 | case OP_oRRnpc: |
| 7204 | case OP_oRRnpcsp: |
| 7205 | case OP_RRnpc: |
| 7206 | case OP_RRnpcsp: |
| 7207 | case OP_oRR: |
| 7208 | case OP_RRe: |
| 7209 | case OP_RRo: |
| 7210 | case OP_LR: |
| 7211 | case OP_oLR: |
| 7212 | case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; |
| 7213 | case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; |
| 7214 | case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; |
| 7215 | case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; |
| 7216 | case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; |
| 7217 | case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; |
| 7218 | case OP_oRND: |
| 7219 | case OP_RNDMQR: |
| 7220 | po_reg_or_goto (REG_TYPE_RN, try_rndmq); |
| 7221 | break; |
| 7222 | try_rndmq: |
| 7223 | case OP_RNDMQ: |
| 7224 | po_reg_or_goto (REG_TYPE_MQ, try_rnd); |
| 7225 | break; |
| 7226 | try_rnd: |
| 7227 | case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; |
| 7228 | case OP_RVC: |
| 7229 | po_reg_or_goto (REG_TYPE_VFC, coproc_reg); |
| 7230 | break; |
| 7231 | /* Also accept generic coprocessor regs for unknown registers. */ |
| 7232 | coproc_reg: |
| 7233 | po_reg_or_fail (REG_TYPE_CN); |
| 7234 | break; |
| 7235 | case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; |
| 7236 | case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; |
| 7237 | case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; |
| 7238 | case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; |
| 7239 | case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; |
| 7240 | case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; |
| 7241 | case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; |
| 7242 | case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; |
| 7243 | case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; |
| 7244 | case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; |
| 7245 | case OP_oRNQ: |
| 7246 | case OP_RNQMQ: |
| 7247 | po_reg_or_goto (REG_TYPE_MQ, try_nq); |
| 7248 | break; |
| 7249 | try_nq: |
| 7250 | case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; |
| 7251 | case OP_RNSD: po_reg_or_fail (REG_TYPE_NSD); break; |
| 7252 | case OP_RNDQMQR: |
| 7253 | po_reg_or_goto (REG_TYPE_RN, try_rndqmq); |
| 7254 | break; |
| 7255 | try_rndqmq: |
| 7256 | case OP_oRNDQMQ: |
| 7257 | case OP_RNDQMQ: |
| 7258 | po_reg_or_goto (REG_TYPE_MQ, try_rndq); |
| 7259 | break; |
| 7260 | try_rndq: |
| 7261 | case OP_oRNDQ: |
| 7262 | case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; |
| 7263 | case OP_RVSDMQ: |
| 7264 | po_reg_or_goto (REG_TYPE_MQ, try_rvsd); |
| 7265 | break; |
| 7266 | try_rvsd: |
| 7267 | case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; |
| 7268 | case OP_RVSD_COND: |
| 7269 | po_reg_or_goto (REG_TYPE_VFSD, try_cond); |
| 7270 | break; |
| 7271 | case OP_oRNSDQ: |
| 7272 | case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; |
| 7273 | case OP_RNSDQMQR: |
| 7274 | po_reg_or_goto (REG_TYPE_RN, try_mq); |
| 7275 | break; |
| 7276 | try_mq: |
| 7277 | case OP_oRNSDQMQ: |
| 7278 | case OP_RNSDQMQ: |
| 7279 | po_reg_or_goto (REG_TYPE_MQ, try_nsdq2); |
| 7280 | break; |
| 7281 | try_nsdq2: |
| 7282 | po_reg_or_fail (REG_TYPE_NSDQ); |
| 7283 | inst.error = 0; |
| 7284 | break; |
| 7285 | case OP_RMQRR: |
| 7286 | po_reg_or_goto (REG_TYPE_RN, try_rmq); |
| 7287 | break; |
| 7288 | try_rmq: |
| 7289 | case OP_RMQ: |
| 7290 | po_reg_or_fail (REG_TYPE_MQ); |
| 7291 | break; |
| 7292 | /* Neon scalar. Using an element size of 8 means that some invalid |
| 7293 | scalars are accepted here, so deal with those in later code. */ |
| 7294 | case OP_RNSC: po_scalar_or_goto (8, failure, REG_TYPE_VFD); break; |
| 7295 | |
| 7296 | case OP_RNDQ_I0: |
| 7297 | { |
| 7298 | po_reg_or_goto (REG_TYPE_NDQ, try_imm0); |
| 7299 | break; |
| 7300 | try_imm0: |
| 7301 | po_imm_or_fail (0, 0, TRUE); |
| 7302 | } |
| 7303 | break; |
| 7304 | |
| 7305 | case OP_RVSD_I0: |
| 7306 | po_reg_or_goto (REG_TYPE_VFSD, try_imm0); |
| 7307 | break; |
| 7308 | |
| 7309 | case OP_RSVDMQ_FI0: |
| 7310 | po_reg_or_goto (REG_TYPE_MQ, try_rsvd_fi0); |
| 7311 | break; |
| 7312 | try_rsvd_fi0: |
| 7313 | case OP_RSVD_FI0: |
| 7314 | { |
| 7315 | po_reg_or_goto (REG_TYPE_VFSD, try_ifimm0); |
| 7316 | break; |
| 7317 | try_ifimm0: |
| 7318 | if (parse_ifimm_zero (&str)) |
| 7319 | inst.operands[i].imm = 0; |
| 7320 | else |
| 7321 | { |
| 7322 | inst.error |
| 7323 | = _("only floating point zero is allowed as immediate value"); |
| 7324 | goto failure; |
| 7325 | } |
| 7326 | } |
| 7327 | break; |
| 7328 | |
| 7329 | case OP_RR_RNSC: |
| 7330 | { |
| 7331 | po_scalar_or_goto (8, try_rr, REG_TYPE_VFD); |
| 7332 | break; |
| 7333 | try_rr: |
| 7334 | po_reg_or_fail (REG_TYPE_RN); |
| 7335 | } |
| 7336 | break; |
| 7337 | |
| 7338 | case OP_RNSDQ_RNSC_MQ_RR: |
| 7339 | po_reg_or_goto (REG_TYPE_RN, try_rnsdq_rnsc_mq); |
| 7340 | break; |
| 7341 | try_rnsdq_rnsc_mq: |
| 7342 | case OP_RNSDQ_RNSC_MQ: |
| 7343 | po_reg_or_goto (REG_TYPE_MQ, try_rnsdq_rnsc); |
| 7344 | break; |
| 7345 | try_rnsdq_rnsc: |
| 7346 | case OP_RNSDQ_RNSC: |
| 7347 | { |
| 7348 | po_scalar_or_goto (8, try_nsdq, REG_TYPE_VFD); |
| 7349 | inst.error = 0; |
| 7350 | break; |
| 7351 | try_nsdq: |
| 7352 | po_reg_or_fail (REG_TYPE_NSDQ); |
| 7353 | inst.error = 0; |
| 7354 | } |
| 7355 | break; |
| 7356 | |
| 7357 | case OP_RNSD_RNSC: |
| 7358 | { |
| 7359 | po_scalar_or_goto (8, try_s_scalar, REG_TYPE_VFD); |
| 7360 | break; |
| 7361 | try_s_scalar: |
| 7362 | po_scalar_or_goto (4, try_nsd, REG_TYPE_VFS); |
| 7363 | break; |
| 7364 | try_nsd: |
| 7365 | po_reg_or_fail (REG_TYPE_NSD); |
| 7366 | } |
| 7367 | break; |
| 7368 | |
| 7369 | case OP_RNDQMQ_RNSC_RR: |
| 7370 | po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc_rr); |
| 7371 | break; |
| 7372 | try_rndq_rnsc_rr: |
| 7373 | case OP_RNDQ_RNSC_RR: |
| 7374 | po_reg_or_goto (REG_TYPE_RN, try_rndq_rnsc); |
| 7375 | break; |
| 7376 | case OP_RNDQMQ_RNSC: |
| 7377 | po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc); |
| 7378 | break; |
| 7379 | try_rndq_rnsc: |
| 7380 | case OP_RNDQ_RNSC: |
| 7381 | { |
| 7382 | po_scalar_or_goto (8, try_ndq, REG_TYPE_VFD); |
| 7383 | break; |
| 7384 | try_ndq: |
| 7385 | po_reg_or_fail (REG_TYPE_NDQ); |
| 7386 | } |
| 7387 | break; |
| 7388 | |
| 7389 | case OP_RND_RNSC: |
| 7390 | { |
| 7391 | po_scalar_or_goto (8, try_vfd, REG_TYPE_VFD); |
| 7392 | break; |
| 7393 | try_vfd: |
| 7394 | po_reg_or_fail (REG_TYPE_VFD); |
| 7395 | } |
| 7396 | break; |
| 7397 | |
| 7398 | case OP_VMOV: |
| 7399 | /* WARNING: parse_neon_mov can move the operand counter, i. If we're |
| 7400 | not careful then bad things might happen. */ |
| 7401 | po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); |
| 7402 | break; |
| 7403 | |
| 7404 | case OP_RNDQMQ_Ibig: |
| 7405 | po_reg_or_goto (REG_TYPE_MQ, try_rndq_ibig); |
| 7406 | break; |
| 7407 | try_rndq_ibig: |
| 7408 | case OP_RNDQ_Ibig: |
| 7409 | { |
| 7410 | po_reg_or_goto (REG_TYPE_NDQ, try_immbig); |
| 7411 | break; |
| 7412 | try_immbig: |
| 7413 | /* There's a possibility of getting a 64-bit immediate here, so |
| 7414 | we need special handling. */ |
| 7415 | if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/FALSE) |
| 7416 | == FAIL) |
| 7417 | { |
| 7418 | inst.error = _("immediate value is out of range"); |
| 7419 | goto failure; |
| 7420 | } |
| 7421 | } |
| 7422 | break; |
| 7423 | |
| 7424 | case OP_RNDQ_I63b: |
| 7425 | { |
| 7426 | po_reg_or_goto (REG_TYPE_NDQ, try_shimm); |
| 7427 | break; |
| 7428 | try_shimm: |
| 7429 | po_imm_or_fail (0, 63, TRUE); |
| 7430 | } |
| 7431 | break; |
| 7432 | |
| 7433 | case OP_RRnpcb: |
| 7434 | po_char_or_fail ('['); |
| 7435 | po_reg_or_fail (REG_TYPE_RN); |
| 7436 | po_char_or_fail (']'); |
| 7437 | break; |
| 7438 | |
| 7439 | case OP_RRnpctw: |
| 7440 | case OP_RRw: |
| 7441 | case OP_oRRw: |
| 7442 | po_reg_or_fail (REG_TYPE_RN); |
| 7443 | if (skip_past_char (&str, '!') == SUCCESS) |
| 7444 | inst.operands[i].writeback = 1; |
| 7445 | break; |
| 7446 | |
| 7447 | /* Immediates */ |
| 7448 | case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; |
| 7449 | case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; |
| 7450 | case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; |
| 7451 | case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; |
| 7452 | case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; |
| 7453 | case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; |
| 7454 | case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; |
| 7455 | case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; |
| 7456 | case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; |
| 7457 | case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; |
| 7458 | case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; |
| 7459 | case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; |
| 7460 | |
| 7461 | case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; |
| 7462 | case OP_oI7b: |
| 7463 | case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; |
| 7464 | case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; |
| 7465 | case OP_oI31b: |
| 7466 | case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; |
| 7467 | case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; |
| 7468 | case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break; |
| 7469 | case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; |
| 7470 | |
| 7471 | /* Immediate variants */ |
| 7472 | case OP_oI255c: |
| 7473 | po_char_or_fail ('{'); |
| 7474 | po_imm_or_fail (0, 255, TRUE); |
| 7475 | po_char_or_fail ('}'); |
| 7476 | break; |
| 7477 | |
| 7478 | case OP_I31w: |
| 7479 | /* The expression parser chokes on a trailing !, so we have |
| 7480 | to find it first and zap it. */ |
| 7481 | { |
| 7482 | char *s = str; |
| 7483 | while (*s && *s != ',') |
| 7484 | s++; |
| 7485 | if (s[-1] == '!') |
| 7486 | { |
| 7487 | s[-1] = '\0'; |
| 7488 | inst.operands[i].writeback = 1; |
| 7489 | } |
| 7490 | po_imm_or_fail (0, 31, TRUE); |
| 7491 | if (str == s - 1) |
| 7492 | str = s; |
| 7493 | } |
| 7494 | break; |
| 7495 | |
| 7496 | /* Expressions */ |
| 7497 | case OP_EXPi: EXPi: |
| 7498 | po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str, |
| 7499 | GE_OPT_PREFIX)); |
| 7500 | break; |
| 7501 | |
| 7502 | case OP_EXP: |
| 7503 | po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str, |
| 7504 | GE_NO_PREFIX)); |
| 7505 | break; |
| 7506 | |
| 7507 | case OP_EXPr: EXPr: |
| 7508 | po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str, |
| 7509 | GE_NO_PREFIX)); |
| 7510 | if (inst.relocs[0].exp.X_op == O_symbol) |
| 7511 | { |
| 7512 | val = parse_reloc (&str); |
| 7513 | if (val == -1) |
| 7514 | { |
| 7515 | inst.error = _("unrecognized relocation suffix"); |
| 7516 | goto failure; |
| 7517 | } |
| 7518 | else if (val != BFD_RELOC_UNUSED) |
| 7519 | { |
| 7520 | inst.operands[i].imm = val; |
| 7521 | inst.operands[i].hasreloc = 1; |
| 7522 | } |
| 7523 | } |
| 7524 | break; |
| 7525 | |
| 7526 | case OP_EXPs: |
| 7527 | po_misc_or_fail (my_get_expression (&inst.relocs[i].exp, &str, |
| 7528 | GE_NO_PREFIX)); |
| 7529 | if (inst.relocs[i].exp.X_op == O_symbol) |
| 7530 | { |
| 7531 | inst.operands[i].hasreloc = 1; |
| 7532 | } |
| 7533 | else if (inst.relocs[i].exp.X_op == O_constant) |
| 7534 | { |
| 7535 | inst.operands[i].imm = inst.relocs[i].exp.X_add_number; |
| 7536 | inst.operands[i].hasreloc = 0; |
| 7537 | } |
| 7538 | break; |
| 7539 | |
| 7540 | /* Operand for MOVW or MOVT. */ |
| 7541 | case OP_HALF: |
| 7542 | po_misc_or_fail (parse_half (&str)); |
| 7543 | break; |
| 7544 | |
| 7545 | /* Register or expression. */ |
| 7546 | case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; |
| 7547 | case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; |
| 7548 | |
| 7549 | /* Register or immediate. */ |
| 7550 | case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; |
| 7551 | I0: po_imm_or_fail (0, 0, FALSE); break; |
| 7552 | |
| 7553 | case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; |
| 7554 | IF: |
| 7555 | if (!is_immediate_prefix (*str)) |
| 7556 | goto bad_args; |
| 7557 | str++; |
| 7558 | val = parse_fpa_immediate (&str); |
| 7559 | if (val == FAIL) |
| 7560 | goto failure; |
| 7561 | /* FPA immediates are encoded as registers 8-15. |
| 7562 | parse_fpa_immediate has already applied the offset. */ |
| 7563 | inst.operands[i].reg = val; |
| 7564 | inst.operands[i].isreg = 1; |
| 7565 | break; |
| 7566 | |
| 7567 | case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break; |
| 7568 | I32z: po_imm_or_fail (0, 32, FALSE); break; |
| 7569 | |
| 7570 | /* Two kinds of register. */ |
| 7571 | case OP_RIWR_RIWC: |
| 7572 | { |
| 7573 | struct reg_entry *rege = arm_reg_parse_multi (&str); |
| 7574 | if (!rege |
| 7575 | || (rege->type != REG_TYPE_MMXWR |
| 7576 | && rege->type != REG_TYPE_MMXWC |
| 7577 | && rege->type != REG_TYPE_MMXWCG)) |
| 7578 | { |
| 7579 | inst.error = _("iWMMXt data or control register expected"); |
| 7580 | goto failure; |
| 7581 | } |
| 7582 | inst.operands[i].reg = rege->number; |
| 7583 | inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); |
| 7584 | } |
| 7585 | break; |
| 7586 | |
| 7587 | case OP_RIWC_RIWG: |
| 7588 | { |
| 7589 | struct reg_entry *rege = arm_reg_parse_multi (&str); |
| 7590 | if (!rege |
| 7591 | || (rege->type != REG_TYPE_MMXWC |
| 7592 | && rege->type != REG_TYPE_MMXWCG)) |
| 7593 | { |
| 7594 | inst.error = _("iWMMXt control register expected"); |
| 7595 | goto failure; |
| 7596 | } |
| 7597 | inst.operands[i].reg = rege->number; |
| 7598 | inst.operands[i].isreg = 1; |
| 7599 | } |
| 7600 | break; |
| 7601 | |
| 7602 | /* Misc */ |
| 7603 | case OP_CPSF: val = parse_cps_flags (&str); break; |
| 7604 | case OP_ENDI: val = parse_endian_specifier (&str); break; |
| 7605 | case OP_oROR: val = parse_ror (&str); break; |
| 7606 | try_cond: |
| 7607 | case OP_COND: val = parse_cond (&str); break; |
| 7608 | case OP_oBARRIER_I15: |
| 7609 | po_barrier_or_imm (str); break; |
| 7610 | immediate: |
| 7611 | if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL) |
| 7612 | goto failure; |
| 7613 | break; |
| 7614 | |
| 7615 | case OP_wPSR: |
| 7616 | case OP_rPSR: |
| 7617 | po_reg_or_goto (REG_TYPE_RNB, try_psr); |
| 7618 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt)) |
| 7619 | { |
| 7620 | inst.error = _("Banked registers are not available with this " |
| 7621 | "architecture."); |
| 7622 | goto failure; |
| 7623 | } |
| 7624 | break; |
| 7625 | try_psr: |
| 7626 | val = parse_psr (&str, op_parse_code == OP_wPSR); |
| 7627 | break; |
| 7628 | |
| 7629 | case OP_VLDR: |
| 7630 | po_reg_or_goto (REG_TYPE_VFSD, try_sysreg); |
| 7631 | break; |
| 7632 | try_sysreg: |
| 7633 | val = parse_sys_vldr_vstr (&str); |
| 7634 | break; |
| 7635 | |
| 7636 | case OP_APSR_RR: |
| 7637 | po_reg_or_goto (REG_TYPE_RN, try_apsr); |
| 7638 | break; |
| 7639 | try_apsr: |
| 7640 | /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS |
| 7641 | instruction). */ |
| 7642 | if (strncasecmp (str, "APSR_", 5) == 0) |
| 7643 | { |
| 7644 | unsigned found = 0; |
| 7645 | str += 5; |
| 7646 | while (found < 15) |
| 7647 | switch (*str++) |
| 7648 | { |
| 7649 | case 'c': found = (found & 1) ? 16 : found | 1; break; |
| 7650 | case 'n': found = (found & 2) ? 16 : found | 2; break; |
| 7651 | case 'z': found = (found & 4) ? 16 : found | 4; break; |
| 7652 | case 'v': found = (found & 8) ? 16 : found | 8; break; |
| 7653 | default: found = 16; |
| 7654 | } |
| 7655 | if (found != 15) |
| 7656 | goto failure; |
| 7657 | inst.operands[i].isvec = 1; |
| 7658 | /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */ |
| 7659 | inst.operands[i].reg = REG_PC; |
| 7660 | } |
| 7661 | else |
| 7662 | goto failure; |
| 7663 | break; |
| 7664 | |
| 7665 | case OP_TB: |
| 7666 | po_misc_or_fail (parse_tb (&str)); |
| 7667 | break; |
| 7668 | |
| 7669 | /* Register lists. */ |
| 7670 | case OP_REGLST: |
| 7671 | val = parse_reg_list (&str, REGLIST_RN); |
| 7672 | if (*str == '^') |
| 7673 | { |
| 7674 | inst.operands[i].writeback = 1; |
| 7675 | str++; |
| 7676 | } |
| 7677 | break; |
| 7678 | |
| 7679 | case OP_CLRMLST: |
| 7680 | val = parse_reg_list (&str, REGLIST_CLRM); |
| 7681 | break; |
| 7682 | |
| 7683 | case OP_VRSLST: |
| 7684 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S, |
| 7685 | &partial_match); |
| 7686 | break; |
| 7687 | |
| 7688 | case OP_VRDLST: |
| 7689 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D, |
| 7690 | &partial_match); |
| 7691 | break; |
| 7692 | |
| 7693 | case OP_VRSDLST: |
| 7694 | /* Allow Q registers too. */ |
| 7695 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, |
| 7696 | REGLIST_NEON_D, &partial_match); |
| 7697 | if (val == FAIL) |
| 7698 | { |
| 7699 | inst.error = NULL; |
| 7700 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, |
| 7701 | REGLIST_VFP_S, &partial_match); |
| 7702 | inst.operands[i].issingle = 1; |
| 7703 | } |
| 7704 | break; |
| 7705 | |
| 7706 | case OP_VRSDVLST: |
| 7707 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, |
| 7708 | REGLIST_VFP_D_VPR, &partial_match); |
| 7709 | if (val == FAIL && !partial_match) |
| 7710 | { |
| 7711 | inst.error = NULL; |
| 7712 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, |
| 7713 | REGLIST_VFP_S_VPR, &partial_match); |
| 7714 | inst.operands[i].issingle = 1; |
| 7715 | } |
| 7716 | break; |
| 7717 | |
| 7718 | case OP_NRDLST: |
| 7719 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, |
| 7720 | REGLIST_NEON_D, &partial_match); |
| 7721 | break; |
| 7722 | |
| 7723 | case OP_MSTRLST4: |
| 7724 | case OP_MSTRLST2: |
| 7725 | val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, |
| 7726 | 1, &inst.operands[i].vectype); |
| 7727 | if (val != (((op_parse_code == OP_MSTRLST2) ? 3 : 7) << 5 | 0xe)) |
| 7728 | goto failure; |
| 7729 | break; |
| 7730 | case OP_NSTRLST: |
| 7731 | val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, |
| 7732 | 0, &inst.operands[i].vectype); |
| 7733 | break; |
| 7734 | |
| 7735 | /* Addressing modes */ |
| 7736 | case OP_ADDRMVE: |
| 7737 | po_misc_or_fail (parse_address_group_reloc (&str, i, GROUP_MVE)); |
| 7738 | break; |
| 7739 | |
| 7740 | case OP_ADDR: |
| 7741 | po_misc_or_fail (parse_address (&str, i)); |
| 7742 | break; |
| 7743 | |
| 7744 | case OP_ADDRGLDR: |
| 7745 | po_misc_or_fail_no_backtrack ( |
| 7746 | parse_address_group_reloc (&str, i, GROUP_LDR)); |
| 7747 | break; |
| 7748 | |
| 7749 | case OP_ADDRGLDRS: |
| 7750 | po_misc_or_fail_no_backtrack ( |
| 7751 | parse_address_group_reloc (&str, i, GROUP_LDRS)); |
| 7752 | break; |
| 7753 | |
| 7754 | case OP_ADDRGLDC: |
| 7755 | po_misc_or_fail_no_backtrack ( |
| 7756 | parse_address_group_reloc (&str, i, GROUP_LDC)); |
| 7757 | break; |
| 7758 | |
| 7759 | case OP_SH: |
| 7760 | po_misc_or_fail (parse_shifter_operand (&str, i)); |
| 7761 | break; |
| 7762 | |
| 7763 | case OP_SHG: |
| 7764 | po_misc_or_fail_no_backtrack ( |
| 7765 | parse_shifter_operand_group_reloc (&str, i)); |
| 7766 | break; |
| 7767 | |
| 7768 | case OP_oSHll: |
| 7769 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); |
| 7770 | break; |
| 7771 | |
| 7772 | case OP_oSHar: |
| 7773 | po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); |
| 7774 | break; |
| 7775 | |
| 7776 | case OP_oSHllar: |
| 7777 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); |
| 7778 | break; |
| 7779 | |
| 7780 | case OP_RMQRZ: |
| 7781 | case OP_oRMQRZ: |
| 7782 | po_reg_or_goto (REG_TYPE_MQ, try_rr_zr); |
| 7783 | break; |
| 7784 | try_rr_zr: |
| 7785 | po_reg_or_goto (REG_TYPE_RN, ZR); |
| 7786 | break; |
| 7787 | ZR: |
| 7788 | po_reg_or_fail (REG_TYPE_ZR); |
| 7789 | break; |
| 7790 | |
| 7791 | default: |
| 7792 | as_fatal (_("unhandled operand code %d"), op_parse_code); |
| 7793 | } |
| 7794 | |
| 7795 | /* Various value-based sanity checks and shared operations. We |
| 7796 | do not signal immediate failures for the register constraints; |
| 7797 | this allows a syntax error to take precedence. */ |
| 7798 | switch (op_parse_code) |
| 7799 | { |
| 7800 | case OP_oRRnpc: |
| 7801 | case OP_RRnpc: |
| 7802 | case OP_RRnpcb: |
| 7803 | case OP_RRw: |
| 7804 | case OP_oRRw: |
| 7805 | case OP_RRnpc_I0: |
| 7806 | if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) |
| 7807 | inst.error = BAD_PC; |
| 7808 | break; |
| 7809 | |
| 7810 | case OP_oRRnpcsp: |
| 7811 | case OP_RRnpcsp: |
| 7812 | if (inst.operands[i].isreg) |
| 7813 | { |
| 7814 | if (inst.operands[i].reg == REG_PC) |
| 7815 | inst.error = BAD_PC; |
| 7816 | else if (inst.operands[i].reg == REG_SP |
| 7817 | /* The restriction on Rd/Rt/Rt2 on Thumb mode has been |
| 7818 | relaxed since ARMv8-A. */ |
| 7819 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) |
| 7820 | { |
| 7821 | gas_assert (thumb); |
| 7822 | inst.error = BAD_SP; |
| 7823 | } |
| 7824 | } |
| 7825 | break; |
| 7826 | |
| 7827 | case OP_RRnpctw: |
| 7828 | if (inst.operands[i].isreg |
| 7829 | && inst.operands[i].reg == REG_PC |
| 7830 | && (inst.operands[i].writeback || thumb)) |
| 7831 | inst.error = BAD_PC; |
| 7832 | break; |
| 7833 | |
| 7834 | case OP_RVSD_COND: |
| 7835 | case OP_VLDR: |
| 7836 | if (inst.operands[i].isreg) |
| 7837 | break; |
| 7838 | /* fall through. */ |
| 7839 | |
| 7840 | case OP_CPSF: |
| 7841 | case OP_ENDI: |
| 7842 | case OP_oROR: |
| 7843 | case OP_wPSR: |
| 7844 | case OP_rPSR: |
| 7845 | case OP_COND: |
| 7846 | case OP_oBARRIER_I15: |
| 7847 | case OP_REGLST: |
| 7848 | case OP_CLRMLST: |
| 7849 | case OP_VRSLST: |
| 7850 | case OP_VRDLST: |
| 7851 | case OP_VRSDLST: |
| 7852 | case OP_VRSDVLST: |
| 7853 | case OP_NRDLST: |
| 7854 | case OP_NSTRLST: |
| 7855 | case OP_MSTRLST2: |
| 7856 | case OP_MSTRLST4: |
| 7857 | if (val == FAIL) |
| 7858 | goto failure; |
| 7859 | inst.operands[i].imm = val; |
| 7860 | break; |
| 7861 | |
| 7862 | case OP_LR: |
| 7863 | case OP_oLR: |
| 7864 | if (inst.operands[i].reg != REG_LR) |
| 7865 | inst.error = _("operand must be LR register"); |
| 7866 | break; |
| 7867 | |
| 7868 | case OP_RMQRZ: |
| 7869 | case OP_oRMQRZ: |
| 7870 | if (!inst.operands[i].iszr && inst.operands[i].reg == REG_PC) |
| 7871 | inst.error = BAD_PC; |
| 7872 | break; |
| 7873 | |
| 7874 | case OP_RRe: |
| 7875 | if (inst.operands[i].isreg |
| 7876 | && (inst.operands[i].reg & 0x00000001) != 0) |
| 7877 | inst.error = BAD_ODD; |
| 7878 | break; |
| 7879 | |
| 7880 | case OP_RRo: |
| 7881 | if (inst.operands[i].isreg) |
| 7882 | { |
| 7883 | if ((inst.operands[i].reg & 0x00000001) != 1) |
| 7884 | inst.error = BAD_EVEN; |
| 7885 | else if (inst.operands[i].reg == REG_SP) |
| 7886 | as_tsktsk (MVE_BAD_SP); |
| 7887 | else if (inst.operands[i].reg == REG_PC) |
| 7888 | inst.error = BAD_PC; |
| 7889 | } |
| 7890 | break; |
| 7891 | |
| 7892 | default: |
| 7893 | break; |
| 7894 | } |
| 7895 | |
| 7896 | /* If we get here, this operand was successfully parsed. */ |
| 7897 | inst.operands[i].present = 1; |
| 7898 | continue; |
| 7899 | |
| 7900 | bad_args: |
| 7901 | inst.error = BAD_ARGS; |
| 7902 | |
| 7903 | failure: |
| 7904 | if (!backtrack_pos) |
| 7905 | { |
| 7906 | /* The parse routine should already have set inst.error, but set a |
| 7907 | default here just in case. */ |
| 7908 | if (!inst.error) |
| 7909 | inst.error = BAD_SYNTAX; |
| 7910 | return FAIL; |
| 7911 | } |
| 7912 | |
| 7913 | /* Do not backtrack over a trailing optional argument that |
| 7914 | absorbed some text. We will only fail again, with the |
| 7915 | 'garbage following instruction' error message, which is |
| 7916 | probably less helpful than the current one. */ |
| 7917 | if (backtrack_index == i && backtrack_pos != str |
| 7918 | && upat[i+1] == OP_stop) |
| 7919 | { |
| 7920 | if (!inst.error) |
| 7921 | inst.error = BAD_SYNTAX; |
| 7922 | return FAIL; |
| 7923 | } |
| 7924 | |
| 7925 | /* Try again, skipping the optional argument at backtrack_pos. */ |
| 7926 | str = backtrack_pos; |
| 7927 | inst.error = backtrack_error; |
| 7928 | inst.operands[backtrack_index].present = 0; |
| 7929 | i = backtrack_index; |
| 7930 | backtrack_pos = 0; |
| 7931 | } |
| 7932 | |
| 7933 | /* Check that we have parsed all the arguments. */ |
| 7934 | if (*str != '\0' && !inst.error) |
| 7935 | inst.error = _("garbage following instruction"); |
| 7936 | |
| 7937 | return inst.error ? FAIL : SUCCESS; |
| 7938 | } |
| 7939 | |
| 7940 | #undef po_char_or_fail |
| 7941 | #undef po_reg_or_fail |
| 7942 | #undef po_reg_or_goto |
| 7943 | #undef po_imm_or_fail |
| 7944 | #undef po_scalar_or_fail |
| 7945 | #undef po_barrier_or_imm |
| 7946 | |
| 7947 | /* Shorthand macro for instruction encoding functions issuing errors. */ |
| 7948 | #define constraint(expr, err) \ |
| 7949 | do \ |
| 7950 | { \ |
| 7951 | if (expr) \ |
| 7952 | { \ |
| 7953 | inst.error = err; \ |
| 7954 | return; \ |
| 7955 | } \ |
| 7956 | } \ |
| 7957 | while (0) |
| 7958 | |
| 7959 | /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2 |
| 7960 | instructions are unpredictable if these registers are used. This |
| 7961 | is the BadReg predicate in ARM's Thumb-2 documentation. |
| 7962 | |
| 7963 | Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few |
| 7964 | places, while the restriction on REG_SP was relaxed since ARMv8-A. */ |
| 7965 | #define reject_bad_reg(reg) \ |
| 7966 | do \ |
| 7967 | if (reg == REG_PC) \ |
| 7968 | { \ |
| 7969 | inst.error = BAD_PC; \ |
| 7970 | return; \ |
| 7971 | } \ |
| 7972 | else if (reg == REG_SP \ |
| 7973 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \ |
| 7974 | { \ |
| 7975 | inst.error = BAD_SP; \ |
| 7976 | return; \ |
| 7977 | } \ |
| 7978 | while (0) |
| 7979 | |
| 7980 | /* If REG is R13 (the stack pointer), warn that its use is |
| 7981 | deprecated. */ |
| 7982 | #define warn_deprecated_sp(reg) \ |
| 7983 | do \ |
| 7984 | if (warn_on_deprecated && reg == REG_SP) \ |
| 7985 | as_tsktsk (_("use of r13 is deprecated")); \ |
| 7986 | while (0) |
| 7987 | |
| 7988 | /* Functions for operand encoding. ARM, then Thumb. */ |
| 7989 | |
| 7990 | #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31)) |
| 7991 | |
| 7992 | /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding. |
| 7993 | |
| 7994 | The only binary encoding difference is the Coprocessor number. Coprocessor |
| 7995 | 9 is used for half-precision calculations or conversions. The format of the |
| 7996 | instruction is the same as the equivalent Coprocessor 10 instruction that |
| 7997 | exists for Single-Precision operation. */ |
| 7998 | |
| 7999 | static void |
| 8000 | do_scalar_fp16_v82_encode (void) |
| 8001 | { |
| 8002 | if (inst.cond < COND_ALWAYS) |
| 8003 | as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional," |
| 8004 | " the behaviour is UNPREDICTABLE")); |
| 8005 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16), |
| 8006 | _(BAD_FP16)); |
| 8007 | |
| 8008 | inst.instruction = (inst.instruction & 0xfffff0ff) | 0x900; |
| 8009 | mark_feature_used (&arm_ext_fp16); |
| 8010 | } |
| 8011 | |
| 8012 | /* If VAL can be encoded in the immediate field of an ARM instruction, |
| 8013 | return the encoded form. Otherwise, return FAIL. */ |
| 8014 | |
| 8015 | static unsigned int |
| 8016 | encode_arm_immediate (unsigned int val) |
| 8017 | { |
| 8018 | unsigned int a, i; |
| 8019 | |
| 8020 | if (val <= 0xff) |
| 8021 | return val; |
| 8022 | |
| 8023 | for (i = 2; i < 32; i += 2) |
| 8024 | if ((a = rotate_left (val, i)) <= 0xff) |
| 8025 | return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ |
| 8026 | |
| 8027 | return FAIL; |
| 8028 | } |
| 8029 | |
| 8030 | /* If VAL can be encoded in the immediate field of a Thumb32 instruction, |
| 8031 | return the encoded form. Otherwise, return FAIL. */ |
| 8032 | static unsigned int |
| 8033 | encode_thumb32_immediate (unsigned int val) |
| 8034 | { |
| 8035 | unsigned int a, i; |
| 8036 | |
| 8037 | if (val <= 0xff) |
| 8038 | return val; |
| 8039 | |
| 8040 | for (i = 1; i <= 24; i++) |
| 8041 | { |
| 8042 | a = val >> i; |
| 8043 | if ((val & ~(0xff << i)) == 0) |
| 8044 | return ((val >> i) & 0x7f) | ((32 - i) << 7); |
| 8045 | } |
| 8046 | |
| 8047 | a = val & 0xff; |
| 8048 | if (val == ((a << 16) | a)) |
| 8049 | return 0x100 | a; |
| 8050 | if (val == ((a << 24) | (a << 16) | (a << 8) | a)) |
| 8051 | return 0x300 | a; |
| 8052 | |
| 8053 | a = val & 0xff00; |
| 8054 | if (val == ((a << 16) | a)) |
| 8055 | return 0x200 | (a >> 8); |
| 8056 | |
| 8057 | return FAIL; |
| 8058 | } |
| 8059 | /* Encode a VFP SP or DP register number into inst.instruction. */ |
| 8060 | |
| 8061 | static void |
| 8062 | encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) |
| 8063 | { |
| 8064 | if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) |
| 8065 | && reg > 15) |
| 8066 | { |
| 8067 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) |
| 8068 | { |
| 8069 | if (thumb_mode) |
| 8070 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
| 8071 | fpu_vfp_ext_d32); |
| 8072 | else |
| 8073 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, |
| 8074 | fpu_vfp_ext_d32); |
| 8075 | } |
| 8076 | else |
| 8077 | { |
| 8078 | first_error (_("D register out of range for selected VFP version")); |
| 8079 | return; |
| 8080 | } |
| 8081 | } |
| 8082 | |
| 8083 | switch (pos) |
| 8084 | { |
| 8085 | case VFP_REG_Sd: |
| 8086 | inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); |
| 8087 | break; |
| 8088 | |
| 8089 | case VFP_REG_Sn: |
| 8090 | inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); |
| 8091 | break; |
| 8092 | |
| 8093 | case VFP_REG_Sm: |
| 8094 | inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); |
| 8095 | break; |
| 8096 | |
| 8097 | case VFP_REG_Dd: |
| 8098 | inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); |
| 8099 | break; |
| 8100 | |
| 8101 | case VFP_REG_Dn: |
| 8102 | inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); |
| 8103 | break; |
| 8104 | |
| 8105 | case VFP_REG_Dm: |
| 8106 | inst.instruction |= (reg & 15) | ((reg >> 4) << 5); |
| 8107 | break; |
| 8108 | |
| 8109 | default: |
| 8110 | abort (); |
| 8111 | } |
| 8112 | } |
| 8113 | |
| 8114 | /* Encode a <shift> in an ARM-format instruction. The immediate, |
| 8115 | if any, is handled by md_apply_fix. */ |
| 8116 | static void |
| 8117 | encode_arm_shift (int i) |
| 8118 | { |
| 8119 | /* register-shifted register. */ |
| 8120 | if (inst.operands[i].immisreg) |
| 8121 | { |
| 8122 | int op_index; |
| 8123 | for (op_index = 0; op_index <= i; ++op_index) |
| 8124 | { |
| 8125 | /* Check the operand only when it's presented. In pre-UAL syntax, |
| 8126 | if the destination register is the same as the first operand, two |
| 8127 | register form of the instruction can be used. */ |
| 8128 | if (inst.operands[op_index].present && inst.operands[op_index].isreg |
| 8129 | && inst.operands[op_index].reg == REG_PC) |
| 8130 | as_warn (UNPRED_REG ("r15")); |
| 8131 | } |
| 8132 | |
| 8133 | if (inst.operands[i].imm == REG_PC) |
| 8134 | as_warn (UNPRED_REG ("r15")); |
| 8135 | } |
| 8136 | |
| 8137 | if (inst.operands[i].shift_kind == SHIFT_RRX) |
| 8138 | inst.instruction |= SHIFT_ROR << 5; |
| 8139 | else |
| 8140 | { |
| 8141 | inst.instruction |= inst.operands[i].shift_kind << 5; |
| 8142 | if (inst.operands[i].immisreg) |
| 8143 | { |
| 8144 | inst.instruction |= SHIFT_BY_REG; |
| 8145 | inst.instruction |= inst.operands[i].imm << 8; |
| 8146 | } |
| 8147 | else |
| 8148 | inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM; |
| 8149 | } |
| 8150 | } |
| 8151 | |
| 8152 | static void |
| 8153 | encode_arm_shifter_operand (int i) |
| 8154 | { |
| 8155 | if (inst.operands[i].isreg) |
| 8156 | { |
| 8157 | inst.instruction |= inst.operands[i].reg; |
| 8158 | encode_arm_shift (i); |
| 8159 | } |
| 8160 | else |
| 8161 | { |
| 8162 | inst.instruction |= INST_IMMEDIATE; |
| 8163 | if (inst.relocs[0].type != BFD_RELOC_ARM_IMMEDIATE) |
| 8164 | inst.instruction |= inst.operands[i].imm; |
| 8165 | } |
| 8166 | } |
| 8167 | |
| 8168 | /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ |
| 8169 | static void |
| 8170 | encode_arm_addr_mode_common (int i, bfd_boolean is_t) |
| 8171 | { |
| 8172 | /* PR 14260: |
| 8173 | Generate an error if the operand is not a register. */ |
| 8174 | constraint (!inst.operands[i].isreg, |
| 8175 | _("Instruction does not support =N addresses")); |
| 8176 | |
| 8177 | inst.instruction |= inst.operands[i].reg << 16; |
| 8178 | |
| 8179 | if (inst.operands[i].preind) |
| 8180 | { |
| 8181 | if (is_t) |
| 8182 | { |
| 8183 | inst.error = _("instruction does not accept preindexed addressing"); |
| 8184 | return; |
| 8185 | } |
| 8186 | inst.instruction |= PRE_INDEX; |
| 8187 | if (inst.operands[i].writeback) |
| 8188 | inst.instruction |= WRITE_BACK; |
| 8189 | |
| 8190 | } |
| 8191 | else if (inst.operands[i].postind) |
| 8192 | { |
| 8193 | gas_assert (inst.operands[i].writeback); |
| 8194 | if (is_t) |
| 8195 | inst.instruction |= WRITE_BACK; |
| 8196 | } |
| 8197 | else /* unindexed - only for coprocessor */ |
| 8198 | { |
| 8199 | inst.error = _("instruction does not accept unindexed addressing"); |
| 8200 | return; |
| 8201 | } |
| 8202 | |
| 8203 | if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) |
| 8204 | && (((inst.instruction & 0x000f0000) >> 16) |
| 8205 | == ((inst.instruction & 0x0000f000) >> 12))) |
| 8206 | as_warn ((inst.instruction & LOAD_BIT) |
| 8207 | ? _("destination register same as write-back base") |
| 8208 | : _("source register same as write-back base")); |
| 8209 | } |
| 8210 | |
| 8211 | /* inst.operands[i] was set up by parse_address. Encode it into an |
| 8212 | ARM-format mode 2 load or store instruction. If is_t is true, |
| 8213 | reject forms that cannot be used with a T instruction (i.e. not |
| 8214 | post-indexed). */ |
| 8215 | static void |
| 8216 | encode_arm_addr_mode_2 (int i, bfd_boolean is_t) |
| 8217 | { |
| 8218 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
| 8219 | |
| 8220 | encode_arm_addr_mode_common (i, is_t); |
| 8221 | |
| 8222 | if (inst.operands[i].immisreg) |
| 8223 | { |
| 8224 | constraint ((inst.operands[i].imm == REG_PC |
| 8225 | || (is_pc && inst.operands[i].writeback)), |
| 8226 | BAD_PC_ADDRESSING); |
| 8227 | inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ |
| 8228 | inst.instruction |= inst.operands[i].imm; |
| 8229 | if (!inst.operands[i].negative) |
| 8230 | inst.instruction |= INDEX_UP; |
| 8231 | if (inst.operands[i].shifted) |
| 8232 | { |
| 8233 | if (inst.operands[i].shift_kind == SHIFT_RRX) |
| 8234 | inst.instruction |= SHIFT_ROR << 5; |
| 8235 | else |
| 8236 | { |
| 8237 | inst.instruction |= inst.operands[i].shift_kind << 5; |
| 8238 | inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM; |
| 8239 | } |
| 8240 | } |
| 8241 | } |
| 8242 | else /* immediate offset in inst.relocs[0] */ |
| 8243 | { |
| 8244 | if (is_pc && !inst.relocs[0].pc_rel) |
| 8245 | { |
| 8246 | const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0); |
| 8247 | |
| 8248 | /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt |
| 8249 | cannot use PC in addressing. |
| 8250 | PC cannot be used in writeback addressing, either. */ |
| 8251 | constraint ((is_t || inst.operands[i].writeback), |
| 8252 | BAD_PC_ADDRESSING); |
| 8253 | |
| 8254 | /* Use of PC in str is deprecated for ARMv7. */ |
| 8255 | if (warn_on_deprecated |
| 8256 | && !is_load |
| 8257 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7)) |
| 8258 | as_tsktsk (_("use of PC in this instruction is deprecated")); |
| 8259 | } |
| 8260 | |
| 8261 | if (inst.relocs[0].type == BFD_RELOC_UNUSED) |
| 8262 | { |
| 8263 | /* Prefer + for zero encoded value. */ |
| 8264 | if (!inst.operands[i].negative) |
| 8265 | inst.instruction |= INDEX_UP; |
| 8266 | inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM; |
| 8267 | } |
| 8268 | } |
| 8269 | } |
| 8270 | |
| 8271 | /* inst.operands[i] was set up by parse_address. Encode it into an |
| 8272 | ARM-format mode 3 load or store instruction. Reject forms that |
| 8273 | cannot be used with such instructions. If is_t is true, reject |
| 8274 | forms that cannot be used with a T instruction (i.e. not |
| 8275 | post-indexed). */ |
| 8276 | static void |
| 8277 | encode_arm_addr_mode_3 (int i, bfd_boolean is_t) |
| 8278 | { |
| 8279 | if (inst.operands[i].immisreg && inst.operands[i].shifted) |
| 8280 | { |
| 8281 | inst.error = _("instruction does not accept scaled register index"); |
| 8282 | return; |
| 8283 | } |
| 8284 | |
| 8285 | encode_arm_addr_mode_common (i, is_t); |
| 8286 | |
| 8287 | if (inst.operands[i].immisreg) |
| 8288 | { |
| 8289 | constraint ((inst.operands[i].imm == REG_PC |
| 8290 | || (is_t && inst.operands[i].reg == REG_PC)), |
| 8291 | BAD_PC_ADDRESSING); |
| 8292 | constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback, |
| 8293 | BAD_PC_WRITEBACK); |
| 8294 | inst.instruction |= inst.operands[i].imm; |
| 8295 | if (!inst.operands[i].negative) |
| 8296 | inst.instruction |= INDEX_UP; |
| 8297 | } |
| 8298 | else /* immediate offset in inst.relocs[0] */ |
| 8299 | { |
| 8300 | constraint ((inst.operands[i].reg == REG_PC && !inst.relocs[0].pc_rel |
| 8301 | && inst.operands[i].writeback), |
| 8302 | BAD_PC_WRITEBACK); |
| 8303 | inst.instruction |= HWOFFSET_IMM; |
| 8304 | if (inst.relocs[0].type == BFD_RELOC_UNUSED) |
| 8305 | { |
| 8306 | /* Prefer + for zero encoded value. */ |
| 8307 | if (!inst.operands[i].negative) |
| 8308 | inst.instruction |= INDEX_UP; |
| 8309 | |
| 8310 | inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM8; |
| 8311 | } |
| 8312 | } |
| 8313 | } |
| 8314 | |
| 8315 | /* Write immediate bits [7:0] to the following locations: |
| 8316 | |
| 8317 | |28/24|23 19|18 16|15 4|3 0| |
| 8318 | | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| |
| 8319 | |
| 8320 | This function is used by VMOV/VMVN/VORR/VBIC. */ |
| 8321 | |
| 8322 | static void |
| 8323 | neon_write_immbits (unsigned immbits) |
| 8324 | { |
| 8325 | inst.instruction |= immbits & 0xf; |
| 8326 | inst.instruction |= ((immbits >> 4) & 0x7) << 16; |
| 8327 | inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24); |
| 8328 | } |
| 8329 | |
| 8330 | /* Invert low-order SIZE bits of XHI:XLO. */ |
| 8331 | |
| 8332 | static void |
| 8333 | neon_invert_size (unsigned *xlo, unsigned *xhi, int size) |
| 8334 | { |
| 8335 | unsigned immlo = xlo ? *xlo : 0; |
| 8336 | unsigned immhi = xhi ? *xhi : 0; |
| 8337 | |
| 8338 | switch (size) |
| 8339 | { |
| 8340 | case 8: |
| 8341 | immlo = (~immlo) & 0xff; |
| 8342 | break; |
| 8343 | |
| 8344 | case 16: |
| 8345 | immlo = (~immlo) & 0xffff; |
| 8346 | break; |
| 8347 | |
| 8348 | case 64: |
| 8349 | immhi = (~immhi) & 0xffffffff; |
| 8350 | /* fall through. */ |
| 8351 | |
| 8352 | case 32: |
| 8353 | immlo = (~immlo) & 0xffffffff; |
| 8354 | break; |
| 8355 | |
| 8356 | default: |
| 8357 | abort (); |
| 8358 | } |
| 8359 | |
| 8360 | if (xlo) |
| 8361 | *xlo = immlo; |
| 8362 | |
| 8363 | if (xhi) |
| 8364 | *xhi = immhi; |
| 8365 | } |
| 8366 | |
| 8367 | /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits |
| 8368 | A, B, C, D. */ |
| 8369 | |
| 8370 | static int |
| 8371 | neon_bits_same_in_bytes (unsigned imm) |
| 8372 | { |
| 8373 | return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) |
| 8374 | && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) |
| 8375 | && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) |
| 8376 | && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); |
| 8377 | } |
| 8378 | |
| 8379 | /* For immediate of above form, return 0bABCD. */ |
| 8380 | |
| 8381 | static unsigned |
| 8382 | neon_squash_bits (unsigned imm) |
| 8383 | { |
| 8384 | return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) |
| 8385 | | ((imm & 0x01000000) >> 21); |
| 8386 | } |
| 8387 | |
| 8388 | /* Compress quarter-float representation to 0b...000 abcdefgh. */ |
| 8389 | |
| 8390 | static unsigned |
| 8391 | neon_qfloat_bits (unsigned imm) |
| 8392 | { |
| 8393 | return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); |
| 8394 | } |
| 8395 | |
| 8396 | /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into |
| 8397 | the instruction. *OP is passed as the initial value of the op field, and |
| 8398 | may be set to a different value depending on the constant (i.e. |
| 8399 | "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not |
| 8400 | MVN). If the immediate looks like a repeated pattern then also |
| 8401 | try smaller element sizes. */ |
| 8402 | |
| 8403 | static int |
| 8404 | neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, |
| 8405 | unsigned *immbits, int *op, int size, |
| 8406 | enum neon_el_type type) |
| 8407 | { |
| 8408 | /* Only permit float immediates (including 0.0/-0.0) if the operand type is |
| 8409 | float. */ |
| 8410 | if (type == NT_float && !float_p) |
| 8411 | return FAIL; |
| 8412 | |
| 8413 | if (type == NT_float && is_quarter_float (immlo) && immhi == 0) |
| 8414 | { |
| 8415 | if (size != 32 || *op == 1) |
| 8416 | return FAIL; |
| 8417 | *immbits = neon_qfloat_bits (immlo); |
| 8418 | return 0xf; |
| 8419 | } |
| 8420 | |
| 8421 | if (size == 64) |
| 8422 | { |
| 8423 | if (neon_bits_same_in_bytes (immhi) |
| 8424 | && neon_bits_same_in_bytes (immlo)) |
| 8425 | { |
| 8426 | if (*op == 1) |
| 8427 | return FAIL; |
| 8428 | *immbits = (neon_squash_bits (immhi) << 4) |
| 8429 | | neon_squash_bits (immlo); |
| 8430 | *op = 1; |
| 8431 | return 0xe; |
| 8432 | } |
| 8433 | |
| 8434 | if (immhi != immlo) |
| 8435 | return FAIL; |
| 8436 | } |
| 8437 | |
| 8438 | if (size >= 32) |
| 8439 | { |
| 8440 | if (immlo == (immlo & 0x000000ff)) |
| 8441 | { |
| 8442 | *immbits = immlo; |
| 8443 | return 0x0; |
| 8444 | } |
| 8445 | else if (immlo == (immlo & 0x0000ff00)) |
| 8446 | { |
| 8447 | *immbits = immlo >> 8; |
| 8448 | return 0x2; |
| 8449 | } |
| 8450 | else if (immlo == (immlo & 0x00ff0000)) |
| 8451 | { |
| 8452 | *immbits = immlo >> 16; |
| 8453 | return 0x4; |
| 8454 | } |
| 8455 | else if (immlo == (immlo & 0xff000000)) |
| 8456 | { |
| 8457 | *immbits = immlo >> 24; |
| 8458 | return 0x6; |
| 8459 | } |
| 8460 | else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) |
| 8461 | { |
| 8462 | *immbits = (immlo >> 8) & 0xff; |
| 8463 | return 0xc; |
| 8464 | } |
| 8465 | else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) |
| 8466 | { |
| 8467 | *immbits = (immlo >> 16) & 0xff; |
| 8468 | return 0xd; |
| 8469 | } |
| 8470 | |
| 8471 | if ((immlo & 0xffff) != (immlo >> 16)) |
| 8472 | return FAIL; |
| 8473 | immlo &= 0xffff; |
| 8474 | } |
| 8475 | |
| 8476 | if (size >= 16) |
| 8477 | { |
| 8478 | if (immlo == (immlo & 0x000000ff)) |
| 8479 | { |
| 8480 | *immbits = immlo; |
| 8481 | return 0x8; |
| 8482 | } |
| 8483 | else if (immlo == (immlo & 0x0000ff00)) |
| 8484 | { |
| 8485 | *immbits = immlo >> 8; |
| 8486 | return 0xa; |
| 8487 | } |
| 8488 | |
| 8489 | if ((immlo & 0xff) != (immlo >> 8)) |
| 8490 | return FAIL; |
| 8491 | immlo &= 0xff; |
| 8492 | } |
| 8493 | |
| 8494 | if (immlo == (immlo & 0x000000ff)) |
| 8495 | { |
| 8496 | /* Don't allow MVN with 8-bit immediate. */ |
| 8497 | if (*op == 1) |
| 8498 | return FAIL; |
| 8499 | *immbits = immlo; |
| 8500 | return 0xe; |
| 8501 | } |
| 8502 | |
| 8503 | return FAIL; |
| 8504 | } |
| 8505 | |
| 8506 | #if defined BFD_HOST_64_BIT |
| 8507 | /* Returns TRUE if double precision value V may be cast |
| 8508 | to single precision without loss of accuracy. */ |
| 8509 | |
| 8510 | static bfd_boolean |
| 8511 | is_double_a_single (bfd_int64_t v) |
| 8512 | { |
| 8513 | int exp = (int)((v >> 52) & 0x7FF); |
| 8514 | bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL); |
| 8515 | |
| 8516 | return (exp == 0 || exp == 0x7FF |
| 8517 | || (exp >= 1023 - 126 && exp <= 1023 + 127)) |
| 8518 | && (mantissa & 0x1FFFFFFFl) == 0; |
| 8519 | } |
| 8520 | |
| 8521 | /* Returns a double precision value casted to single precision |
| 8522 | (ignoring the least significant bits in exponent and mantissa). */ |
| 8523 | |
| 8524 | static int |
| 8525 | double_to_single (bfd_int64_t v) |
| 8526 | { |
| 8527 | int sign = (int) ((v >> 63) & 1l); |
| 8528 | int exp = (int) ((v >> 52) & 0x7FF); |
| 8529 | bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL); |
| 8530 | |
| 8531 | if (exp == 0x7FF) |
| 8532 | exp = 0xFF; |
| 8533 | else |
| 8534 | { |
| 8535 | exp = exp - 1023 + 127; |
| 8536 | if (exp >= 0xFF) |
| 8537 | { |
| 8538 | /* Infinity. */ |
| 8539 | exp = 0x7F; |
| 8540 | mantissa = 0; |
| 8541 | } |
| 8542 | else if (exp < 0) |
| 8543 | { |
| 8544 | /* No denormalized numbers. */ |
| 8545 | exp = 0; |
| 8546 | mantissa = 0; |
| 8547 | } |
| 8548 | } |
| 8549 | mantissa >>= 29; |
| 8550 | return (sign << 31) | (exp << 23) | mantissa; |
| 8551 | } |
| 8552 | #endif /* BFD_HOST_64_BIT */ |
| 8553 | |
| 8554 | enum lit_type |
| 8555 | { |
| 8556 | CONST_THUMB, |
| 8557 | CONST_ARM, |
| 8558 | CONST_VEC |
| 8559 | }; |
| 8560 | |
| 8561 | static void do_vfp_nsyn_opcode (const char *); |
| 8562 | |
| 8563 | /* inst.relocs[0].exp describes an "=expr" load pseudo-operation. |
| 8564 | Determine whether it can be performed with a move instruction; if |
| 8565 | it can, convert inst.instruction to that move instruction and |
| 8566 | return TRUE; if it can't, convert inst.instruction to a literal-pool |
| 8567 | load and return FALSE. If this is not a valid thing to do in the |
| 8568 | current context, set inst.error and return TRUE. |
| 8569 | |
| 8570 | inst.operands[i] describes the destination register. */ |
| 8571 | |
| 8572 | static bfd_boolean |
| 8573 | move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3) |
| 8574 | { |
| 8575 | unsigned long tbit; |
| 8576 | bfd_boolean thumb_p = (t == CONST_THUMB); |
| 8577 | bfd_boolean arm_p = (t == CONST_ARM); |
| 8578 | |
| 8579 | if (thumb_p) |
| 8580 | tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; |
| 8581 | else |
| 8582 | tbit = LOAD_BIT; |
| 8583 | |
| 8584 | if ((inst.instruction & tbit) == 0) |
| 8585 | { |
| 8586 | inst.error = _("invalid pseudo operation"); |
| 8587 | return TRUE; |
| 8588 | } |
| 8589 | |
| 8590 | if (inst.relocs[0].exp.X_op != O_constant |
| 8591 | && inst.relocs[0].exp.X_op != O_symbol |
| 8592 | && inst.relocs[0].exp.X_op != O_big) |
| 8593 | { |
| 8594 | inst.error = _("constant expression expected"); |
| 8595 | return TRUE; |
| 8596 | } |
| 8597 | |
| 8598 | if (inst.relocs[0].exp.X_op == O_constant |
| 8599 | || inst.relocs[0].exp.X_op == O_big) |
| 8600 | { |
| 8601 | #if defined BFD_HOST_64_BIT |
| 8602 | bfd_int64_t v; |
| 8603 | #else |
| 8604 | offsetT v; |
| 8605 | #endif |
| 8606 | if (inst.relocs[0].exp.X_op == O_big) |
| 8607 | { |
| 8608 | LITTLENUM_TYPE w[X_PRECISION]; |
| 8609 | LITTLENUM_TYPE * l; |
| 8610 | |
| 8611 | if (inst.relocs[0].exp.X_add_number == -1) |
| 8612 | { |
| 8613 | gen_to_words (w, X_PRECISION, E_PRECISION); |
| 8614 | l = w; |
| 8615 | /* FIXME: Should we check words w[2..5] ? */ |
| 8616 | } |
| 8617 | else |
| 8618 | l = generic_bignum; |
| 8619 | |
| 8620 | #if defined BFD_HOST_64_BIT |
| 8621 | v = |
| 8622 | ((((((((bfd_int64_t) l[3] & LITTLENUM_MASK) |
| 8623 | << LITTLENUM_NUMBER_OF_BITS) |
| 8624 | | ((bfd_int64_t) l[2] & LITTLENUM_MASK)) |
| 8625 | << LITTLENUM_NUMBER_OF_BITS) |
| 8626 | | ((bfd_int64_t) l[1] & LITTLENUM_MASK)) |
| 8627 | << LITTLENUM_NUMBER_OF_BITS) |
| 8628 | | ((bfd_int64_t) l[0] & LITTLENUM_MASK)); |
| 8629 | #else |
| 8630 | v = ((l[1] & LITTLENUM_MASK) << LITTLENUM_NUMBER_OF_BITS) |
| 8631 | | (l[0] & LITTLENUM_MASK); |
| 8632 | #endif |
| 8633 | } |
| 8634 | else |
| 8635 | v = inst.relocs[0].exp.X_add_number; |
| 8636 | |
| 8637 | if (!inst.operands[i].issingle) |
| 8638 | { |
| 8639 | if (thumb_p) |
| 8640 | { |
| 8641 | /* LDR should not use lead in a flag-setting instruction being |
| 8642 | chosen so we do not check whether movs can be used. */ |
| 8643 | |
| 8644 | if ((ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2) |
| 8645 | || ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m)) |
| 8646 | && inst.operands[i].reg != 13 |
| 8647 | && inst.operands[i].reg != 15) |
| 8648 | { |
| 8649 | /* Check if on thumb2 it can be done with a mov.w, mvn or |
| 8650 | movw instruction. */ |
| 8651 | unsigned int newimm; |
| 8652 | bfd_boolean isNegated; |
| 8653 | |
| 8654 | newimm = encode_thumb32_immediate (v); |
| 8655 | if (newimm != (unsigned int) FAIL) |
| 8656 | isNegated = FALSE; |
| 8657 | else |
| 8658 | { |
| 8659 | newimm = encode_thumb32_immediate (~v); |
| 8660 | if (newimm != (unsigned int) FAIL) |
| 8661 | isNegated = TRUE; |
| 8662 | } |
| 8663 | |
| 8664 | /* The number can be loaded with a mov.w or mvn |
| 8665 | instruction. */ |
| 8666 | if (newimm != (unsigned int) FAIL |
| 8667 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)) |
| 8668 | { |
| 8669 | inst.instruction = (0xf04f0000 /* MOV.W. */ |
| 8670 | | (inst.operands[i].reg << 8)); |
| 8671 | /* Change to MOVN. */ |
| 8672 | inst.instruction |= (isNegated ? 0x200000 : 0); |
| 8673 | inst.instruction |= (newimm & 0x800) << 15; |
| 8674 | inst.instruction |= (newimm & 0x700) << 4; |
| 8675 | inst.instruction |= (newimm & 0x0ff); |
| 8676 | return TRUE; |
| 8677 | } |
| 8678 | /* The number can be loaded with a movw instruction. */ |
| 8679 | else if ((v & ~0xFFFF) == 0 |
| 8680 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m)) |
| 8681 | { |
| 8682 | int imm = v & 0xFFFF; |
| 8683 | |
| 8684 | inst.instruction = 0xf2400000; /* MOVW. */ |
| 8685 | inst.instruction |= (inst.operands[i].reg << 8); |
| 8686 | inst.instruction |= (imm & 0xf000) << 4; |
| 8687 | inst.instruction |= (imm & 0x0800) << 15; |
| 8688 | inst.instruction |= (imm & 0x0700) << 4; |
| 8689 | inst.instruction |= (imm & 0x00ff); |
| 8690 | return TRUE; |
| 8691 | } |
| 8692 | } |
| 8693 | } |
| 8694 | else if (arm_p) |
| 8695 | { |
| 8696 | int value = encode_arm_immediate (v); |
| 8697 | |
| 8698 | if (value != FAIL) |
| 8699 | { |
| 8700 | /* This can be done with a mov instruction. */ |
| 8701 | inst.instruction &= LITERAL_MASK; |
| 8702 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); |
| 8703 | inst.instruction |= value & 0xfff; |
| 8704 | return TRUE; |
| 8705 | } |
| 8706 | |
| 8707 | value = encode_arm_immediate (~ v); |
| 8708 | if (value != FAIL) |
| 8709 | { |
| 8710 | /* This can be done with a mvn instruction. */ |
| 8711 | inst.instruction &= LITERAL_MASK; |
| 8712 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); |
| 8713 | inst.instruction |= value & 0xfff; |
| 8714 | return TRUE; |
| 8715 | } |
| 8716 | } |
| 8717 | else if (t == CONST_VEC && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) |
| 8718 | { |
| 8719 | int op = 0; |
| 8720 | unsigned immbits = 0; |
| 8721 | unsigned immlo = inst.operands[1].imm; |
| 8722 | unsigned immhi = inst.operands[1].regisimm |
| 8723 | ? inst.operands[1].reg |
| 8724 | : inst.relocs[0].exp.X_unsigned |
| 8725 | ? 0 |
| 8726 | : ((bfd_int64_t)((int) immlo)) >> 32; |
| 8727 | int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits, |
| 8728 | &op, 64, NT_invtype); |
| 8729 | |
| 8730 | if (cmode == FAIL) |
| 8731 | { |
| 8732 | neon_invert_size (&immlo, &immhi, 64); |
| 8733 | op = !op; |
| 8734 | cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits, |
| 8735 | &op, 64, NT_invtype); |
| 8736 | } |
| 8737 | |
| 8738 | if (cmode != FAIL) |
| 8739 | { |
| 8740 | inst.instruction = (inst.instruction & VLDR_VMOV_SAME) |
| 8741 | | (1 << 23) |
| 8742 | | (cmode << 8) |
| 8743 | | (op << 5) |
| 8744 | | (1 << 4); |
| 8745 | |
| 8746 | /* Fill other bits in vmov encoding for both thumb and arm. */ |
| 8747 | if (thumb_mode) |
| 8748 | inst.instruction |= (0x7U << 29) | (0xF << 24); |
| 8749 | else |
| 8750 | inst.instruction |= (0xFU << 28) | (0x1 << 25); |
| 8751 | neon_write_immbits (immbits); |
| 8752 | return TRUE; |
| 8753 | } |
| 8754 | } |
| 8755 | } |
| 8756 | |
| 8757 | if (t == CONST_VEC) |
| 8758 | { |
| 8759 | /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */ |
| 8760 | if (inst.operands[i].issingle |
| 8761 | && is_quarter_float (inst.operands[1].imm) |
| 8762 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3xd)) |
| 8763 | { |
| 8764 | inst.operands[1].imm = |
| 8765 | neon_qfloat_bits (v); |
| 8766 | do_vfp_nsyn_opcode ("fconsts"); |
| 8767 | return TRUE; |
| 8768 | } |
| 8769 | |
| 8770 | /* If our host does not support a 64-bit type then we cannot perform |
| 8771 | the following optimization. This mean that there will be a |
| 8772 | discrepancy between the output produced by an assembler built for |
| 8773 | a 32-bit-only host and the output produced from a 64-bit host, but |
| 8774 | this cannot be helped. */ |
| 8775 | #if defined BFD_HOST_64_BIT |
| 8776 | else if (!inst.operands[1].issingle |
| 8777 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3)) |
| 8778 | { |
| 8779 | if (is_double_a_single (v) |
| 8780 | && is_quarter_float (double_to_single (v))) |
| 8781 | { |
| 8782 | inst.operands[1].imm = |
| 8783 | neon_qfloat_bits (double_to_single (v)); |
| 8784 | do_vfp_nsyn_opcode ("fconstd"); |
| 8785 | return TRUE; |
| 8786 | } |
| 8787 | } |
| 8788 | #endif |
| 8789 | } |
| 8790 | } |
| 8791 | |
| 8792 | if (add_to_lit_pool ((!inst.operands[i].isvec |
| 8793 | || inst.operands[i].issingle) ? 4 : 8) == FAIL) |
| 8794 | return TRUE; |
| 8795 | |
| 8796 | inst.operands[1].reg = REG_PC; |
| 8797 | inst.operands[1].isreg = 1; |
| 8798 | inst.operands[1].preind = 1; |
| 8799 | inst.relocs[0].pc_rel = 1; |
| 8800 | inst.relocs[0].type = (thumb_p |
| 8801 | ? BFD_RELOC_ARM_THUMB_OFFSET |
| 8802 | : (mode_3 |
| 8803 | ? BFD_RELOC_ARM_HWLITERAL |
| 8804 | : BFD_RELOC_ARM_LITERAL)); |
| 8805 | return FALSE; |
| 8806 | } |
| 8807 | |
| 8808 | /* inst.operands[i] was set up by parse_address. Encode it into an |
| 8809 | ARM-format instruction. Reject all forms which cannot be encoded |
| 8810 | into a coprocessor load/store instruction. If wb_ok is false, |
| 8811 | reject use of writeback; if unind_ok is false, reject use of |
| 8812 | unindexed addressing. If reloc_override is not 0, use it instead |
| 8813 | of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one |
| 8814 | (in which case it is preserved). */ |
| 8815 | |
| 8816 | static int |
| 8817 | encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) |
| 8818 | { |
| 8819 | if (!inst.operands[i].isreg) |
| 8820 | { |
| 8821 | /* PR 18256 */ |
| 8822 | if (! inst.operands[0].isvec) |
| 8823 | { |
| 8824 | inst.error = _("invalid co-processor operand"); |
| 8825 | return FAIL; |
| 8826 | } |
| 8827 | if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE)) |
| 8828 | return SUCCESS; |
| 8829 | } |
| 8830 | |
| 8831 | inst.instruction |= inst.operands[i].reg << 16; |
| 8832 | |
| 8833 | gas_assert (!(inst.operands[i].preind && inst.operands[i].postind)); |
| 8834 | |
| 8835 | if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ |
| 8836 | { |
| 8837 | gas_assert (!inst.operands[i].writeback); |
| 8838 | if (!unind_ok) |
| 8839 | { |
| 8840 | inst.error = _("instruction does not support unindexed addressing"); |
| 8841 | return FAIL; |
| 8842 | } |
| 8843 | inst.instruction |= inst.operands[i].imm; |
| 8844 | inst.instruction |= INDEX_UP; |
| 8845 | return SUCCESS; |
| 8846 | } |
| 8847 | |
| 8848 | if (inst.operands[i].preind) |
| 8849 | inst.instruction |= PRE_INDEX; |
| 8850 | |
| 8851 | if (inst.operands[i].writeback) |
| 8852 | { |
| 8853 | if (inst.operands[i].reg == REG_PC) |
| 8854 | { |
| 8855 | inst.error = _("pc may not be used with write-back"); |
| 8856 | return FAIL; |
| 8857 | } |
| 8858 | if (!wb_ok) |
| 8859 | { |
| 8860 | inst.error = _("instruction does not support writeback"); |
| 8861 | return FAIL; |
| 8862 | } |
| 8863 | inst.instruction |= WRITE_BACK; |
| 8864 | } |
| 8865 | |
| 8866 | if (reloc_override) |
| 8867 | inst.relocs[0].type = (bfd_reloc_code_real_type) reloc_override; |
| 8868 | else if ((inst.relocs[0].type < BFD_RELOC_ARM_ALU_PC_G0_NC |
| 8869 | || inst.relocs[0].type > BFD_RELOC_ARM_LDC_SB_G2) |
| 8870 | && inst.relocs[0].type != BFD_RELOC_ARM_LDR_PC_G0) |
| 8871 | { |
| 8872 | if (thumb_mode) |
| 8873 | inst.relocs[0].type = BFD_RELOC_ARM_T32_CP_OFF_IMM; |
| 8874 | else |
| 8875 | inst.relocs[0].type = BFD_RELOC_ARM_CP_OFF_IMM; |
| 8876 | } |
| 8877 | |
| 8878 | /* Prefer + for zero encoded value. */ |
| 8879 | if (!inst.operands[i].negative) |
| 8880 | inst.instruction |= INDEX_UP; |
| 8881 | |
| 8882 | return SUCCESS; |
| 8883 | } |
| 8884 | |
| 8885 | /* Functions for instruction encoding, sorted by sub-architecture. |
| 8886 | First some generics; their names are taken from the conventional |
| 8887 | bit positions for register arguments in ARM format instructions. */ |
| 8888 | |
| 8889 | static void |
| 8890 | do_noargs (void) |
| 8891 | { |
| 8892 | } |
| 8893 | |
| 8894 | static void |
| 8895 | do_rd (void) |
| 8896 | { |
| 8897 | inst.instruction |= inst.operands[0].reg << 12; |
| 8898 | } |
| 8899 | |
| 8900 | static void |
| 8901 | do_rn (void) |
| 8902 | { |
| 8903 | inst.instruction |= inst.operands[0].reg << 16; |
| 8904 | } |
| 8905 | |
| 8906 | static void |
| 8907 | do_rd_rm (void) |
| 8908 | { |
| 8909 | inst.instruction |= inst.operands[0].reg << 12; |
| 8910 | inst.instruction |= inst.operands[1].reg; |
| 8911 | } |
| 8912 | |
| 8913 | static void |
| 8914 | do_rm_rn (void) |
| 8915 | { |
| 8916 | inst.instruction |= inst.operands[0].reg; |
| 8917 | inst.instruction |= inst.operands[1].reg << 16; |
| 8918 | } |
| 8919 | |
| 8920 | static void |
| 8921 | do_rd_rn (void) |
| 8922 | { |
| 8923 | inst.instruction |= inst.operands[0].reg << 12; |
| 8924 | inst.instruction |= inst.operands[1].reg << 16; |
| 8925 | } |
| 8926 | |
| 8927 | static void |
| 8928 | do_rn_rd (void) |
| 8929 | { |
| 8930 | inst.instruction |= inst.operands[0].reg << 16; |
| 8931 | inst.instruction |= inst.operands[1].reg << 12; |
| 8932 | } |
| 8933 | |
| 8934 | static void |
| 8935 | do_tt (void) |
| 8936 | { |
| 8937 | inst.instruction |= inst.operands[0].reg << 8; |
| 8938 | inst.instruction |= inst.operands[1].reg << 16; |
| 8939 | } |
| 8940 | |
| 8941 | static bfd_boolean |
| 8942 | check_obsolete (const arm_feature_set *feature, const char *msg) |
| 8943 | { |
| 8944 | if (ARM_CPU_IS_ANY (cpu_variant)) |
| 8945 | { |
| 8946 | as_tsktsk ("%s", msg); |
| 8947 | return TRUE; |
| 8948 | } |
| 8949 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature)) |
| 8950 | { |
| 8951 | as_bad ("%s", msg); |
| 8952 | return TRUE; |
| 8953 | } |
| 8954 | |
| 8955 | return FALSE; |
| 8956 | } |
| 8957 | |
| 8958 | static void |
| 8959 | do_rd_rm_rn (void) |
| 8960 | { |
| 8961 | unsigned Rn = inst.operands[2].reg; |
| 8962 | /* Enforce restrictions on SWP instruction. */ |
| 8963 | if ((inst.instruction & 0x0fbfffff) == 0x01000090) |
| 8964 | { |
| 8965 | constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, |
| 8966 | _("Rn must not overlap other operands")); |
| 8967 | |
| 8968 | /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7. |
| 8969 | */ |
| 8970 | if (!check_obsolete (&arm_ext_v8, |
| 8971 | _("swp{b} use is obsoleted for ARMv8 and later")) |
| 8972 | && warn_on_deprecated |
| 8973 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6)) |
| 8974 | as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7")); |
| 8975 | } |
| 8976 | |
| 8977 | inst.instruction |= inst.operands[0].reg << 12; |
| 8978 | inst.instruction |= inst.operands[1].reg; |
| 8979 | inst.instruction |= Rn << 16; |
| 8980 | } |
| 8981 | |
| 8982 | static void |
| 8983 | do_rd_rn_rm (void) |
| 8984 | { |
| 8985 | inst.instruction |= inst.operands[0].reg << 12; |
| 8986 | inst.instruction |= inst.operands[1].reg << 16; |
| 8987 | inst.instruction |= inst.operands[2].reg; |
| 8988 | } |
| 8989 | |
| 8990 | static void |
| 8991 | do_rm_rd_rn (void) |
| 8992 | { |
| 8993 | constraint ((inst.operands[2].reg == REG_PC), BAD_PC); |
| 8994 | constraint (((inst.relocs[0].exp.X_op != O_constant |
| 8995 | && inst.relocs[0].exp.X_op != O_illegal) |
| 8996 | || inst.relocs[0].exp.X_add_number != 0), |
| 8997 | BAD_ADDR_MODE); |
| 8998 | inst.instruction |= inst.operands[0].reg; |
| 8999 | inst.instruction |= inst.operands[1].reg << 12; |
| 9000 | inst.instruction |= inst.operands[2].reg << 16; |
| 9001 | } |
| 9002 | |
| 9003 | static void |
| 9004 | do_imm0 (void) |
| 9005 | { |
| 9006 | inst.instruction |= inst.operands[0].imm; |
| 9007 | } |
| 9008 | |
| 9009 | static void |
| 9010 | do_rd_cpaddr (void) |
| 9011 | { |
| 9012 | inst.instruction |= inst.operands[0].reg << 12; |
| 9013 | encode_arm_cp_address (1, TRUE, TRUE, 0); |
| 9014 | } |
| 9015 | |
| 9016 | /* ARM instructions, in alphabetical order by function name (except |
| 9017 | that wrapper functions appear immediately after the function they |
| 9018 | wrap). */ |
| 9019 | |
| 9020 | /* This is a pseudo-op of the form "adr rd, label" to be converted |
| 9021 | into a relative address of the form "add rd, pc, #label-.-8". */ |
| 9022 | |
| 9023 | static void |
| 9024 | do_adr (void) |
| 9025 | { |
| 9026 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ |
| 9027 | |
| 9028 | /* Frag hacking will turn this into a sub instruction if the offset turns |
| 9029 | out to be negative. */ |
| 9030 | inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE; |
| 9031 | inst.relocs[0].pc_rel = 1; |
| 9032 | inst.relocs[0].exp.X_add_number -= 8; |
| 9033 | |
| 9034 | if (support_interwork |
| 9035 | && inst.relocs[0].exp.X_op == O_symbol |
| 9036 | && inst.relocs[0].exp.X_add_symbol != NULL |
| 9037 | && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol) |
| 9038 | && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol)) |
| 9039 | inst.relocs[0].exp.X_add_number |= 1; |
| 9040 | } |
| 9041 | |
| 9042 | /* This is a pseudo-op of the form "adrl rd, label" to be converted |
| 9043 | into a relative address of the form: |
| 9044 | add rd, pc, #low(label-.-8)" |
| 9045 | add rd, rd, #high(label-.-8)" */ |
| 9046 | |
| 9047 | static void |
| 9048 | do_adrl (void) |
| 9049 | { |
| 9050 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ |
| 9051 | |
| 9052 | /* Frag hacking will turn this into a sub instruction if the offset turns |
| 9053 | out to be negative. */ |
| 9054 | inst.relocs[0].type = BFD_RELOC_ARM_ADRL_IMMEDIATE; |
| 9055 | inst.relocs[0].pc_rel = 1; |
| 9056 | inst.size = INSN_SIZE * 2; |
| 9057 | inst.relocs[0].exp.X_add_number -= 8; |
| 9058 | |
| 9059 | if (support_interwork |
| 9060 | && inst.relocs[0].exp.X_op == O_symbol |
| 9061 | && inst.relocs[0].exp.X_add_symbol != NULL |
| 9062 | && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol) |
| 9063 | && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol)) |
| 9064 | inst.relocs[0].exp.X_add_number |= 1; |
| 9065 | } |
| 9066 | |
| 9067 | static void |
| 9068 | do_arit (void) |
| 9069 | { |
| 9070 | constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC |
| 9071 | && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC , |
| 9072 | THUMB1_RELOC_ONLY); |
| 9073 | if (!inst.operands[1].present) |
| 9074 | inst.operands[1].reg = inst.operands[0].reg; |
| 9075 | inst.instruction |= inst.operands[0].reg << 12; |
| 9076 | inst.instruction |= inst.operands[1].reg << 16; |
| 9077 | encode_arm_shifter_operand (2); |
| 9078 | } |
| 9079 | |
| 9080 | static void |
| 9081 | do_barrier (void) |
| 9082 | { |
| 9083 | if (inst.operands[0].present) |
| 9084 | inst.instruction |= inst.operands[0].imm; |
| 9085 | else |
| 9086 | inst.instruction |= 0xf; |
| 9087 | } |
| 9088 | |
| 9089 | static void |
| 9090 | do_bfc (void) |
| 9091 | { |
| 9092 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; |
| 9093 | constraint (msb > 32, _("bit-field extends past end of register")); |
| 9094 | /* The instruction encoding stores the LSB and MSB, |
| 9095 | not the LSB and width. */ |
| 9096 | inst.instruction |= inst.operands[0].reg << 12; |
| 9097 | inst.instruction |= inst.operands[1].imm << 7; |
| 9098 | inst.instruction |= (msb - 1) << 16; |
| 9099 | } |
| 9100 | |
| 9101 | static void |
| 9102 | do_bfi (void) |
| 9103 | { |
| 9104 | unsigned int msb; |
| 9105 | |
| 9106 | /* #0 in second position is alternative syntax for bfc, which is |
| 9107 | the same instruction but with REG_PC in the Rm field. */ |
| 9108 | if (!inst.operands[1].isreg) |
| 9109 | inst.operands[1].reg = REG_PC; |
| 9110 | |
| 9111 | msb = inst.operands[2].imm + inst.operands[3].imm; |
| 9112 | constraint (msb > 32, _("bit-field extends past end of register")); |
| 9113 | /* The instruction encoding stores the LSB and MSB, |
| 9114 | not the LSB and width. */ |
| 9115 | inst.instruction |= inst.operands[0].reg << 12; |
| 9116 | inst.instruction |= inst.operands[1].reg; |
| 9117 | inst.instruction |= inst.operands[2].imm << 7; |
| 9118 | inst.instruction |= (msb - 1) << 16; |
| 9119 | } |
| 9120 | |
| 9121 | static void |
| 9122 | do_bfx (void) |
| 9123 | { |
| 9124 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
| 9125 | _("bit-field extends past end of register")); |
| 9126 | inst.instruction |= inst.operands[0].reg << 12; |
| 9127 | inst.instruction |= inst.operands[1].reg; |
| 9128 | inst.instruction |= inst.operands[2].imm << 7; |
| 9129 | inst.instruction |= (inst.operands[3].imm - 1) << 16; |
| 9130 | } |
| 9131 | |
| 9132 | /* ARM V5 breakpoint instruction (argument parse) |
| 9133 | BKPT <16 bit unsigned immediate> |
| 9134 | Instruction is not conditional. |
| 9135 | The bit pattern given in insns[] has the COND_ALWAYS condition, |
| 9136 | and it is an error if the caller tried to override that. */ |
| 9137 | |
| 9138 | static void |
| 9139 | do_bkpt (void) |
| 9140 | { |
| 9141 | /* Top 12 of 16 bits to bits 19:8. */ |
| 9142 | inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; |
| 9143 | |
| 9144 | /* Bottom 4 of 16 bits to bits 3:0. */ |
| 9145 | inst.instruction |= inst.operands[0].imm & 0xf; |
| 9146 | } |
| 9147 | |
| 9148 | static void |
| 9149 | encode_branch (int default_reloc) |
| 9150 | { |
| 9151 | if (inst.operands[0].hasreloc) |
| 9152 | { |
| 9153 | constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32 |
| 9154 | && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL, |
| 9155 | _("the only valid suffixes here are '(plt)' and '(tlscall)'")); |
| 9156 | inst.relocs[0].type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32 |
| 9157 | ? BFD_RELOC_ARM_PLT32 |
| 9158 | : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL; |
| 9159 | } |
| 9160 | else |
| 9161 | inst.relocs[0].type = (bfd_reloc_code_real_type) default_reloc; |
| 9162 | inst.relocs[0].pc_rel = 1; |
| 9163 | } |
| 9164 | |
| 9165 | static void |
| 9166 | do_branch (void) |
| 9167 | { |
| 9168 | #ifdef OBJ_ELF |
| 9169 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) |
| 9170 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); |
| 9171 | else |
| 9172 | #endif |
| 9173 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); |
| 9174 | } |
| 9175 | |
| 9176 | static void |
| 9177 | do_bl (void) |
| 9178 | { |
| 9179 | #ifdef OBJ_ELF |
| 9180 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) |
| 9181 | { |
| 9182 | if (inst.cond == COND_ALWAYS) |
| 9183 | encode_branch (BFD_RELOC_ARM_PCREL_CALL); |
| 9184 | else |
| 9185 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); |
| 9186 | } |
| 9187 | else |
| 9188 | #endif |
| 9189 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); |
| 9190 | } |
| 9191 | |
| 9192 | /* ARM V5 branch-link-exchange instruction (argument parse) |
| 9193 | BLX <target_addr> ie BLX(1) |
| 9194 | BLX{<condition>} <Rm> ie BLX(2) |
| 9195 | Unfortunately, there are two different opcodes for this mnemonic. |
| 9196 | So, the insns[].value is not used, and the code here zaps values |
| 9197 | into inst.instruction. |
| 9198 | Also, the <target_addr> can be 25 bits, hence has its own reloc. */ |
| 9199 | |
| 9200 | static void |
| 9201 | do_blx (void) |
| 9202 | { |
| 9203 | if (inst.operands[0].isreg) |
| 9204 | { |
| 9205 | /* Arg is a register; the opcode provided by insns[] is correct. |
| 9206 | It is not illegal to do "blx pc", just useless. */ |
| 9207 | if (inst.operands[0].reg == REG_PC) |
| 9208 | as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); |
| 9209 | |
| 9210 | inst.instruction |= inst.operands[0].reg; |
| 9211 | } |
| 9212 | else |
| 9213 | { |
| 9214 | /* Arg is an address; this instruction cannot be executed |
| 9215 | conditionally, and the opcode must be adjusted. |
| 9216 | We retain the BFD_RELOC_ARM_PCREL_BLX till the very end |
| 9217 | where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */ |
| 9218 | constraint (inst.cond != COND_ALWAYS, BAD_COND); |
| 9219 | inst.instruction = 0xfa000000; |
| 9220 | encode_branch (BFD_RELOC_ARM_PCREL_BLX); |
| 9221 | } |
| 9222 | } |
| 9223 | |
| 9224 | static void |
| 9225 | do_bx (void) |
| 9226 | { |
| 9227 | bfd_boolean want_reloc; |
| 9228 | |
| 9229 | if (inst.operands[0].reg == REG_PC) |
| 9230 | as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); |
| 9231 | |
| 9232 | inst.instruction |= inst.operands[0].reg; |
| 9233 | /* Output R_ARM_V4BX relocations if is an EABI object that looks like |
| 9234 | it is for ARMv4t or earlier. */ |
| 9235 | want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5); |
| 9236 | if (!ARM_FEATURE_ZERO (selected_object_arch) |
| 9237 | && !ARM_CPU_HAS_FEATURE (selected_object_arch, arm_ext_v5)) |
| 9238 | want_reloc = TRUE; |
| 9239 | |
| 9240 | #ifdef OBJ_ELF |
| 9241 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
| 9242 | #endif |
| 9243 | want_reloc = FALSE; |
| 9244 | |
| 9245 | if (want_reloc) |
| 9246 | inst.relocs[0].type = BFD_RELOC_ARM_V4BX; |
| 9247 | } |
| 9248 | |
| 9249 | |
| 9250 | /* ARM v5TEJ. Jump to Jazelle code. */ |
| 9251 | |
| 9252 | static void |
| 9253 | do_bxj (void) |
| 9254 | { |
| 9255 | if (inst.operands[0].reg == REG_PC) |
| 9256 | as_tsktsk (_("use of r15 in bxj is not really useful")); |
| 9257 | |
| 9258 | inst.instruction |= inst.operands[0].reg; |
| 9259 | } |
| 9260 | |
| 9261 | /* Co-processor data operation: |
| 9262 | CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} |
| 9263 | CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ |
| 9264 | static void |
| 9265 | do_cdp (void) |
| 9266 | { |
| 9267 | inst.instruction |= inst.operands[0].reg << 8; |
| 9268 | inst.instruction |= inst.operands[1].imm << 20; |
| 9269 | inst.instruction |= inst.operands[2].reg << 12; |
| 9270 | inst.instruction |= inst.operands[3].reg << 16; |
| 9271 | inst.instruction |= inst.operands[4].reg; |
| 9272 | inst.instruction |= inst.operands[5].imm << 5; |
| 9273 | } |
| 9274 | |
| 9275 | static void |
| 9276 | do_cmp (void) |
| 9277 | { |
| 9278 | inst.instruction |= inst.operands[0].reg << 16; |
| 9279 | encode_arm_shifter_operand (1); |
| 9280 | } |
| 9281 | |
| 9282 | /* Transfer between coprocessor and ARM registers. |
| 9283 | MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} |
| 9284 | MRC2 |
| 9285 | MCR{cond} |
| 9286 | MCR2 |
| 9287 | |
| 9288 | No special properties. */ |
| 9289 | |
| 9290 | struct deprecated_coproc_regs_s |
| 9291 | { |
| 9292 | unsigned cp; |
| 9293 | int opc1; |
| 9294 | unsigned crn; |
| 9295 | unsigned crm; |
| 9296 | int opc2; |
| 9297 | arm_feature_set deprecated; |
| 9298 | arm_feature_set obsoleted; |
| 9299 | const char *dep_msg; |
| 9300 | const char *obs_msg; |
| 9301 | }; |
| 9302 | |
| 9303 | #define DEPR_ACCESS_V8 \ |
| 9304 | N_("This coprocessor register access is deprecated in ARMv8") |
| 9305 | |
| 9306 | /* Table of all deprecated coprocessor registers. */ |
| 9307 | static struct deprecated_coproc_regs_s deprecated_coproc_regs[] = |
| 9308 | { |
| 9309 | {15, 0, 7, 10, 5, /* CP15DMB. */ |
| 9310 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
| 9311 | DEPR_ACCESS_V8, NULL}, |
| 9312 | {15, 0, 7, 10, 4, /* CP15DSB. */ |
| 9313 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
| 9314 | DEPR_ACCESS_V8, NULL}, |
| 9315 | {15, 0, 7, 5, 4, /* CP15ISB. */ |
| 9316 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
| 9317 | DEPR_ACCESS_V8, NULL}, |
| 9318 | {14, 6, 1, 0, 0, /* TEEHBR. */ |
| 9319 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
| 9320 | DEPR_ACCESS_V8, NULL}, |
| 9321 | {14, 6, 0, 0, 0, /* TEECR. */ |
| 9322 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
| 9323 | DEPR_ACCESS_V8, NULL}, |
| 9324 | }; |
| 9325 | |
| 9326 | #undef DEPR_ACCESS_V8 |
| 9327 | |
| 9328 | static const size_t deprecated_coproc_reg_count = |
| 9329 | sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]); |
| 9330 | |
| 9331 | static void |
| 9332 | do_co_reg (void) |
| 9333 | { |
| 9334 | unsigned Rd; |
| 9335 | size_t i; |
| 9336 | |
| 9337 | Rd = inst.operands[2].reg; |
| 9338 | if (thumb_mode) |
| 9339 | { |
| 9340 | if (inst.instruction == 0xee000010 |
| 9341 | || inst.instruction == 0xfe000010) |
| 9342 | /* MCR, MCR2 */ |
| 9343 | reject_bad_reg (Rd); |
| 9344 | else if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) |
| 9345 | /* MRC, MRC2 */ |
| 9346 | constraint (Rd == REG_SP, BAD_SP); |
| 9347 | } |
| 9348 | else |
| 9349 | { |
| 9350 | /* MCR */ |
| 9351 | if (inst.instruction == 0xe000010) |
| 9352 | constraint (Rd == REG_PC, BAD_PC); |
| 9353 | } |
| 9354 | |
| 9355 | for (i = 0; i < deprecated_coproc_reg_count; ++i) |
| 9356 | { |
| 9357 | const struct deprecated_coproc_regs_s *r = |
| 9358 | deprecated_coproc_regs + i; |
| 9359 | |
| 9360 | if (inst.operands[0].reg == r->cp |
| 9361 | && inst.operands[1].imm == r->opc1 |
| 9362 | && inst.operands[3].reg == r->crn |
| 9363 | && inst.operands[4].reg == r->crm |
| 9364 | && inst.operands[5].imm == r->opc2) |
| 9365 | { |
| 9366 | if (! ARM_CPU_IS_ANY (cpu_variant) |
| 9367 | && warn_on_deprecated |
| 9368 | && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated)) |
| 9369 | as_tsktsk ("%s", r->dep_msg); |
| 9370 | } |
| 9371 | } |
| 9372 | |
| 9373 | inst.instruction |= inst.operands[0].reg << 8; |
| 9374 | inst.instruction |= inst.operands[1].imm << 21; |
| 9375 | inst.instruction |= Rd << 12; |
| 9376 | inst.instruction |= inst.operands[3].reg << 16; |
| 9377 | inst.instruction |= inst.operands[4].reg; |
| 9378 | inst.instruction |= inst.operands[5].imm << 5; |
| 9379 | } |
| 9380 | |
| 9381 | /* Transfer between coprocessor register and pair of ARM registers. |
| 9382 | MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. |
| 9383 | MCRR2 |
| 9384 | MRRC{cond} |
| 9385 | MRRC2 |
| 9386 | |
| 9387 | Two XScale instructions are special cases of these: |
| 9388 | |
| 9389 | MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 |
| 9390 | MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 |
| 9391 | |
| 9392 | Result unpredictable if Rd or Rn is R15. */ |
| 9393 | |
| 9394 | static void |
| 9395 | do_co_reg2c (void) |
| 9396 | { |
| 9397 | unsigned Rd, Rn; |
| 9398 | |
| 9399 | Rd = inst.operands[2].reg; |
| 9400 | Rn = inst.operands[3].reg; |
| 9401 | |
| 9402 | if (thumb_mode) |
| 9403 | { |
| 9404 | reject_bad_reg (Rd); |
| 9405 | reject_bad_reg (Rn); |
| 9406 | } |
| 9407 | else |
| 9408 | { |
| 9409 | constraint (Rd == REG_PC, BAD_PC); |
| 9410 | constraint (Rn == REG_PC, BAD_PC); |
| 9411 | } |
| 9412 | |
| 9413 | /* Only check the MRRC{2} variants. */ |
| 9414 | if ((inst.instruction & 0x0FF00000) == 0x0C500000) |
| 9415 | { |
| 9416 | /* If Rd == Rn, error that the operation is |
| 9417 | unpredictable (example MRRC p3,#1,r1,r1,c4). */ |
| 9418 | constraint (Rd == Rn, BAD_OVERLAP); |
| 9419 | } |
| 9420 | |
| 9421 | inst.instruction |= inst.operands[0].reg << 8; |
| 9422 | inst.instruction |= inst.operands[1].imm << 4; |
| 9423 | inst.instruction |= Rd << 12; |
| 9424 | inst.instruction |= Rn << 16; |
| 9425 | inst.instruction |= inst.operands[4].reg; |
| 9426 | } |
| 9427 | |
| 9428 | static void |
| 9429 | do_cpsi (void) |
| 9430 | { |
| 9431 | inst.instruction |= inst.operands[0].imm << 6; |
| 9432 | if (inst.operands[1].present) |
| 9433 | { |
| 9434 | inst.instruction |= CPSI_MMOD; |
| 9435 | inst.instruction |= inst.operands[1].imm; |
| 9436 | } |
| 9437 | } |
| 9438 | |
| 9439 | static void |
| 9440 | do_dbg (void) |
| 9441 | { |
| 9442 | inst.instruction |= inst.operands[0].imm; |
| 9443 | } |
| 9444 | |
| 9445 | static void |
| 9446 | do_div (void) |
| 9447 | { |
| 9448 | unsigned Rd, Rn, Rm; |
| 9449 | |
| 9450 | Rd = inst.operands[0].reg; |
| 9451 | Rn = (inst.operands[1].present |
| 9452 | ? inst.operands[1].reg : Rd); |
| 9453 | Rm = inst.operands[2].reg; |
| 9454 | |
| 9455 | constraint ((Rd == REG_PC), BAD_PC); |
| 9456 | constraint ((Rn == REG_PC), BAD_PC); |
| 9457 | constraint ((Rm == REG_PC), BAD_PC); |
| 9458 | |
| 9459 | inst.instruction |= Rd << 16; |
| 9460 | inst.instruction |= Rn << 0; |
| 9461 | inst.instruction |= Rm << 8; |
| 9462 | } |
| 9463 | |
| 9464 | static void |
| 9465 | do_it (void) |
| 9466 | { |
| 9467 | /* There is no IT instruction in ARM mode. We |
| 9468 | process it to do the validation as if in |
| 9469 | thumb mode, just in case the code gets |
| 9470 | assembled for thumb using the unified syntax. */ |
| 9471 | |
| 9472 | inst.size = 0; |
| 9473 | if (unified_syntax) |
| 9474 | { |
| 9475 | set_pred_insn_type (IT_INSN); |
| 9476 | now_pred.mask = (inst.instruction & 0xf) | 0x10; |
| 9477 | now_pred.cc = inst.operands[0].imm; |
| 9478 | } |
| 9479 | } |
| 9480 | |
| 9481 | /* If there is only one register in the register list, |
| 9482 | then return its register number. Otherwise return -1. */ |
| 9483 | static int |
| 9484 | only_one_reg_in_list (int range) |
| 9485 | { |
| 9486 | int i = ffs (range) - 1; |
| 9487 | return (i > 15 || range != (1 << i)) ? -1 : i; |
| 9488 | } |
| 9489 | |
| 9490 | static void |
| 9491 | encode_ldmstm(int from_push_pop_mnem) |
| 9492 | { |
| 9493 | int base_reg = inst.operands[0].reg; |
| 9494 | int range = inst.operands[1].imm; |
| 9495 | int one_reg; |
| 9496 | |
| 9497 | inst.instruction |= base_reg << 16; |
| 9498 | inst.instruction |= range; |
| 9499 | |
| 9500 | if (inst.operands[1].writeback) |
| 9501 | inst.instruction |= LDM_TYPE_2_OR_3; |
| 9502 | |
| 9503 | if (inst.operands[0].writeback) |
| 9504 | { |
| 9505 | inst.instruction |= WRITE_BACK; |
| 9506 | /* Check for unpredictable uses of writeback. */ |
| 9507 | if (inst.instruction & LOAD_BIT) |
| 9508 | { |
| 9509 | /* Not allowed in LDM type 2. */ |
| 9510 | if ((inst.instruction & LDM_TYPE_2_OR_3) |
| 9511 | && ((range & (1 << REG_PC)) == 0)) |
| 9512 | as_warn (_("writeback of base register is UNPREDICTABLE")); |
| 9513 | /* Only allowed if base reg not in list for other types. */ |
| 9514 | else if (range & (1 << base_reg)) |
| 9515 | as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); |
| 9516 | } |
| 9517 | else /* STM. */ |
| 9518 | { |
| 9519 | /* Not allowed for type 2. */ |
| 9520 | if (inst.instruction & LDM_TYPE_2_OR_3) |
| 9521 | as_warn (_("writeback of base register is UNPREDICTABLE")); |
| 9522 | /* Only allowed if base reg not in list, or first in list. */ |
| 9523 | else if ((range & (1 << base_reg)) |
| 9524 | && (range & ((1 << base_reg) - 1))) |
| 9525 | as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); |
| 9526 | } |
| 9527 | } |
| 9528 | |
| 9529 | /* If PUSH/POP has only one register, then use the A2 encoding. */ |
| 9530 | one_reg = only_one_reg_in_list (range); |
| 9531 | if (from_push_pop_mnem && one_reg >= 0) |
| 9532 | { |
| 9533 | int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH; |
| 9534 | |
| 9535 | if (is_push && one_reg == 13 /* SP */) |
| 9536 | /* PR 22483: The A2 encoding cannot be used when |
| 9537 | pushing the stack pointer as this is UNPREDICTABLE. */ |
| 9538 | return; |
| 9539 | |
| 9540 | inst.instruction &= A_COND_MASK; |
| 9541 | inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP; |
| 9542 | inst.instruction |= one_reg << 12; |
| 9543 | } |
| 9544 | } |
| 9545 | |
| 9546 | static void |
| 9547 | do_ldmstm (void) |
| 9548 | { |
| 9549 | encode_ldmstm (/*from_push_pop_mnem=*/FALSE); |
| 9550 | } |
| 9551 | |
| 9552 | /* ARMv5TE load-consecutive (argument parse) |
| 9553 | Mode is like LDRH. |
| 9554 | |
| 9555 | LDRccD R, mode |
| 9556 | STRccD R, mode. */ |
| 9557 | |
| 9558 | static void |
| 9559 | do_ldrd (void) |
| 9560 | { |
| 9561 | constraint (inst.operands[0].reg % 2 != 0, |
| 9562 | _("first transfer register must be even")); |
| 9563 | constraint (inst.operands[1].present |
| 9564 | && inst.operands[1].reg != inst.operands[0].reg + 1, |
| 9565 | _("can only transfer two consecutive registers")); |
| 9566 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); |
| 9567 | constraint (!inst.operands[2].isreg, _("'[' expected")); |
| 9568 | |
| 9569 | if (!inst.operands[1].present) |
| 9570 | inst.operands[1].reg = inst.operands[0].reg + 1; |
| 9571 | |
| 9572 | /* encode_arm_addr_mode_3 will diagnose overlap between the base |
| 9573 | register and the first register written; we have to diagnose |
| 9574 | overlap between the base and the second register written here. */ |
| 9575 | |
| 9576 | if (inst.operands[2].reg == inst.operands[1].reg |
| 9577 | && (inst.operands[2].writeback || inst.operands[2].postind)) |
| 9578 | as_warn (_("base register written back, and overlaps " |
| 9579 | "second transfer register")); |
| 9580 | |
| 9581 | if (!(inst.instruction & V4_STR_BIT)) |
| 9582 | { |
| 9583 | /* For an index-register load, the index register must not overlap the |
| 9584 | destination (even if not write-back). */ |
| 9585 | if (inst.operands[2].immisreg |
| 9586 | && ((unsigned) inst.operands[2].imm == inst.operands[0].reg |
| 9587 | || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) |
| 9588 | as_warn (_("index register overlaps transfer register")); |
| 9589 | } |
| 9590 | inst.instruction |= inst.operands[0].reg << 12; |
| 9591 | encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); |
| 9592 | } |
| 9593 | |
| 9594 | static void |
| 9595 | do_ldrex (void) |
| 9596 | { |
| 9597 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind |
| 9598 | || inst.operands[1].postind || inst.operands[1].writeback |
| 9599 | || inst.operands[1].immisreg || inst.operands[1].shifted |
| 9600 | || inst.operands[1].negative |
| 9601 | /* This can arise if the programmer has written |
| 9602 | strex rN, rM, foo |
| 9603 | or if they have mistakenly used a register name as the last |
| 9604 | operand, eg: |
| 9605 | strex rN, rM, rX |
| 9606 | It is very difficult to distinguish between these two cases |
| 9607 | because "rX" might actually be a label. ie the register |
| 9608 | name has been occluded by a symbol of the same name. So we |
| 9609 | just generate a general 'bad addressing mode' type error |
| 9610 | message and leave it up to the programmer to discover the |
| 9611 | true cause and fix their mistake. */ |
| 9612 | || (inst.operands[1].reg == REG_PC), |
| 9613 | BAD_ADDR_MODE); |
| 9614 | |
| 9615 | constraint (inst.relocs[0].exp.X_op != O_constant |
| 9616 | || inst.relocs[0].exp.X_add_number != 0, |
| 9617 | _("offset must be zero in ARM encoding")); |
| 9618 | |
| 9619 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
| 9620 | |
| 9621 | inst.instruction |= inst.operands[0].reg << 12; |
| 9622 | inst.instruction |= inst.operands[1].reg << 16; |
| 9623 | inst.relocs[0].type = BFD_RELOC_UNUSED; |
| 9624 | } |
| 9625 | |
| 9626 | static void |
| 9627 | do_ldrexd (void) |
| 9628 | { |
| 9629 | constraint (inst.operands[0].reg % 2 != 0, |
| 9630 | _("even register required")); |
| 9631 | constraint (inst.operands[1].present |
| 9632 | && inst.operands[1].reg != inst.operands[0].reg + 1, |
| 9633 | _("can only load two consecutive registers")); |
| 9634 | /* If op 1 were present and equal to PC, this function wouldn't |
| 9635 | have been called in the first place. */ |
| 9636 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); |
| 9637 | |
| 9638 | inst.instruction |= inst.operands[0].reg << 12; |
| 9639 | inst.instruction |= inst.operands[2].reg << 16; |
| 9640 | } |
| 9641 | |
| 9642 | /* In both ARM and thumb state 'ldr pc, #imm' with an immediate |
| 9643 | which is not a multiple of four is UNPREDICTABLE. */ |
| 9644 | static void |
| 9645 | check_ldr_r15_aligned (void) |
| 9646 | { |
| 9647 | constraint (!(inst.operands[1].immisreg) |
| 9648 | && (inst.operands[0].reg == REG_PC |
| 9649 | && inst.operands[1].reg == REG_PC |
| 9650 | && (inst.relocs[0].exp.X_add_number & 0x3)), |
| 9651 | _("ldr to register 15 must be 4-byte aligned")); |
| 9652 | } |
| 9653 | |
| 9654 | static void |
| 9655 | do_ldst (void) |
| 9656 | { |
| 9657 | inst.instruction |= inst.operands[0].reg << 12; |
| 9658 | if (!inst.operands[1].isreg) |
| 9659 | if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/FALSE)) |
| 9660 | return; |
| 9661 | encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); |
| 9662 | check_ldr_r15_aligned (); |
| 9663 | } |
| 9664 | |
| 9665 | static void |
| 9666 | do_ldstt (void) |
| 9667 | { |
| 9668 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
| 9669 | reject [Rn,...]. */ |
| 9670 | if (inst.operands[1].preind) |
| 9671 | { |
| 9672 | constraint (inst.relocs[0].exp.X_op != O_constant |
| 9673 | || inst.relocs[0].exp.X_add_number != 0, |
| 9674 | _("this instruction requires a post-indexed address")); |
| 9675 | |
| 9676 | inst.operands[1].preind = 0; |
| 9677 | inst.operands[1].postind = 1; |
| 9678 | inst.operands[1].writeback = 1; |
| 9679 | } |
| 9680 | inst.instruction |= inst.operands[0].reg << 12; |
| 9681 | encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); |
| 9682 | } |
| 9683 | |
| 9684 | /* Halfword and signed-byte load/store operations. */ |
| 9685 | |
| 9686 | static void |
| 9687 | do_ldstv4 (void) |
| 9688 | { |
| 9689 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
| 9690 | inst.instruction |= inst.operands[0].reg << 12; |
| 9691 | if (!inst.operands[1].isreg) |
| 9692 | if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/TRUE)) |
| 9693 | return; |
| 9694 | encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); |
| 9695 | } |
| 9696 | |
| 9697 | static void |
| 9698 | do_ldsttv4 (void) |
| 9699 | { |
| 9700 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
| 9701 | reject [Rn,...]. */ |
| 9702 | if (inst.operands[1].preind) |
| 9703 | { |
| 9704 | constraint (inst.relocs[0].exp.X_op != O_constant |
| 9705 | || inst.relocs[0].exp.X_add_number != 0, |
| 9706 | _("this instruction requires a post-indexed address")); |
| 9707 | |
| 9708 | inst.operands[1].preind = 0; |
| 9709 | inst.operands[1].postind = 1; |
| 9710 | inst.operands[1].writeback = 1; |
| 9711 | } |
| 9712 | inst.instruction |= inst.operands[0].reg << 12; |
| 9713 | encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); |
| 9714 | } |
| 9715 | |
| 9716 | /* Co-processor register load/store. |
| 9717 | Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ |
| 9718 | static void |
| 9719 | do_lstc (void) |
| 9720 | { |
| 9721 | inst.instruction |= inst.operands[0].reg << 8; |
| 9722 | inst.instruction |= inst.operands[1].reg << 12; |
| 9723 | encode_arm_cp_address (2, TRUE, TRUE, 0); |
| 9724 | } |
| 9725 | |
| 9726 | static void |
| 9727 | do_mlas (void) |
| 9728 | { |
| 9729 | /* This restriction does not apply to mls (nor to mla in v6 or later). */ |
| 9730 | if (inst.operands[0].reg == inst.operands[1].reg |
| 9731 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6) |
| 9732 | && !(inst.instruction & 0x00400000)) |
| 9733 | as_tsktsk (_("Rd and Rm should be different in mla")); |
| 9734 | |
| 9735 | inst.instruction |= inst.operands[0].reg << 16; |
| 9736 | inst.instruction |= inst.operands[1].reg; |
| 9737 | inst.instruction |= inst.operands[2].reg << 8; |
| 9738 | inst.instruction |= inst.operands[3].reg << 12; |
| 9739 | } |
| 9740 | |
| 9741 | static void |
| 9742 | do_mov (void) |
| 9743 | { |
| 9744 | constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC |
| 9745 | && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC , |
| 9746 | THUMB1_RELOC_ONLY); |
| 9747 | inst.instruction |= inst.operands[0].reg << 12; |
| 9748 | encode_arm_shifter_operand (1); |
| 9749 | } |
| 9750 | |
| 9751 | /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ |
| 9752 | static void |
| 9753 | do_mov16 (void) |
| 9754 | { |
| 9755 | bfd_vma imm; |
| 9756 | bfd_boolean top; |
| 9757 | |
| 9758 | top = (inst.instruction & 0x00400000) != 0; |
| 9759 | constraint (top && inst.relocs[0].type == BFD_RELOC_ARM_MOVW, |
| 9760 | _(":lower16: not allowed in this instruction")); |
| 9761 | constraint (!top && inst.relocs[0].type == BFD_RELOC_ARM_MOVT, |
| 9762 | _(":upper16: not allowed in this instruction")); |
| 9763 | inst.instruction |= inst.operands[0].reg << 12; |
| 9764 | if (inst.relocs[0].type == BFD_RELOC_UNUSED) |
| 9765 | { |
| 9766 | imm = inst.relocs[0].exp.X_add_number; |
| 9767 | /* The value is in two pieces: 0:11, 16:19. */ |
| 9768 | inst.instruction |= (imm & 0x00000fff); |
| 9769 | inst.instruction |= (imm & 0x0000f000) << 4; |
| 9770 | } |
| 9771 | } |
| 9772 | |
| 9773 | static int |
| 9774 | do_vfp_nsyn_mrs (void) |
| 9775 | { |
| 9776 | if (inst.operands[0].isvec) |
| 9777 | { |
| 9778 | if (inst.operands[1].reg != 1) |
| 9779 | first_error (_("operand 1 must be FPSCR")); |
| 9780 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); |
| 9781 | memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); |
| 9782 | do_vfp_nsyn_opcode ("fmstat"); |
| 9783 | } |
| 9784 | else if (inst.operands[1].isvec) |
| 9785 | do_vfp_nsyn_opcode ("fmrx"); |
| 9786 | else |
| 9787 | return FAIL; |
| 9788 | |
| 9789 | return SUCCESS; |
| 9790 | } |
| 9791 | |
| 9792 | static int |
| 9793 | do_vfp_nsyn_msr (void) |
| 9794 | { |
| 9795 | if (inst.operands[0].isvec) |
| 9796 | do_vfp_nsyn_opcode ("fmxr"); |
| 9797 | else |
| 9798 | return FAIL; |
| 9799 | |
| 9800 | return SUCCESS; |
| 9801 | } |
| 9802 | |
| 9803 | static void |
| 9804 | do_vmrs (void) |
| 9805 | { |
| 9806 | unsigned Rt = inst.operands[0].reg; |
| 9807 | |
| 9808 | if (thumb_mode && Rt == REG_SP) |
| 9809 | { |
| 9810 | inst.error = BAD_SP; |
| 9811 | return; |
| 9812 | } |
| 9813 | |
| 9814 | /* MVFR2 is only valid at ARMv8-A. */ |
| 9815 | if (inst.operands[1].reg == 5) |
| 9816 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), |
| 9817 | _(BAD_FPU)); |
| 9818 | |
| 9819 | /* APSR_ sets isvec. All other refs to PC are illegal. */ |
| 9820 | if (!inst.operands[0].isvec && Rt == REG_PC) |
| 9821 | { |
| 9822 | inst.error = BAD_PC; |
| 9823 | return; |
| 9824 | } |
| 9825 | |
| 9826 | /* If we get through parsing the register name, we just insert the number |
| 9827 | generated into the instruction without further validation. */ |
| 9828 | inst.instruction |= (inst.operands[1].reg << 16); |
| 9829 | inst.instruction |= (Rt << 12); |
| 9830 | } |
| 9831 | |
| 9832 | static void |
| 9833 | do_vmsr (void) |
| 9834 | { |
| 9835 | unsigned Rt = inst.operands[1].reg; |
| 9836 | |
| 9837 | if (thumb_mode) |
| 9838 | reject_bad_reg (Rt); |
| 9839 | else if (Rt == REG_PC) |
| 9840 | { |
| 9841 | inst.error = BAD_PC; |
| 9842 | return; |
| 9843 | } |
| 9844 | |
| 9845 | /* MVFR2 is only valid for ARMv8-A. */ |
| 9846 | if (inst.operands[0].reg == 5) |
| 9847 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), |
| 9848 | _(BAD_FPU)); |
| 9849 | |
| 9850 | /* If we get through parsing the register name, we just insert the number |
| 9851 | generated into the instruction without further validation. */ |
| 9852 | inst.instruction |= (inst.operands[0].reg << 16); |
| 9853 | inst.instruction |= (Rt << 12); |
| 9854 | } |
| 9855 | |
| 9856 | static void |
| 9857 | do_mrs (void) |
| 9858 | { |
| 9859 | unsigned br; |
| 9860 | |
| 9861 | if (do_vfp_nsyn_mrs () == SUCCESS) |
| 9862 | return; |
| 9863 | |
| 9864 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
| 9865 | inst.instruction |= inst.operands[0].reg << 12; |
| 9866 | |
| 9867 | if (inst.operands[1].isreg) |
| 9868 | { |
| 9869 | br = inst.operands[1].reg; |
| 9870 | if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf0000)) |
| 9871 | as_bad (_("bad register for mrs")); |
| 9872 | } |
| 9873 | else |
| 9874 | { |
| 9875 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ |
| 9876 | constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) |
| 9877 | != (PSR_c|PSR_f), |
| 9878 | _("'APSR', 'CPSR' or 'SPSR' expected")); |
| 9879 | br = (15<<16) | (inst.operands[1].imm & SPSR_BIT); |
| 9880 | } |
| 9881 | |
| 9882 | inst.instruction |= br; |
| 9883 | } |
| 9884 | |
| 9885 | /* Two possible forms: |
| 9886 | "{C|S}PSR_<field>, Rm", |
| 9887 | "{C|S}PSR_f, #expression". */ |
| 9888 | |
| 9889 | static void |
| 9890 | do_msr (void) |
| 9891 | { |
| 9892 | if (do_vfp_nsyn_msr () == SUCCESS) |
| 9893 | return; |
| 9894 | |
| 9895 | inst.instruction |= inst.operands[0].imm; |
| 9896 | if (inst.operands[1].isreg) |
| 9897 | inst.instruction |= inst.operands[1].reg; |
| 9898 | else |
| 9899 | { |
| 9900 | inst.instruction |= INST_IMMEDIATE; |
| 9901 | inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE; |
| 9902 | inst.relocs[0].pc_rel = 0; |
| 9903 | } |
| 9904 | } |
| 9905 | |
| 9906 | static void |
| 9907 | do_mul (void) |
| 9908 | { |
| 9909 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
| 9910 | |
| 9911 | if (!inst.operands[2].present) |
| 9912 | inst.operands[2].reg = inst.operands[0].reg; |
| 9913 | inst.instruction |= inst.operands[0].reg << 16; |
| 9914 | inst.instruction |= inst.operands[1].reg; |
| 9915 | inst.instruction |= inst.operands[2].reg << 8; |
| 9916 | |
| 9917 | if (inst.operands[0].reg == inst.operands[1].reg |
| 9918 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) |
| 9919 | as_tsktsk (_("Rd and Rm should be different in mul")); |
| 9920 | } |
| 9921 | |
| 9922 | /* Long Multiply Parser |
| 9923 | UMULL RdLo, RdHi, Rm, Rs |
| 9924 | SMULL RdLo, RdHi, Rm, Rs |
| 9925 | UMLAL RdLo, RdHi, Rm, Rs |
| 9926 | SMLAL RdLo, RdHi, Rm, Rs. */ |
| 9927 | |
| 9928 | static void |
| 9929 | do_mull (void) |
| 9930 | { |
| 9931 | inst.instruction |= inst.operands[0].reg << 12; |
| 9932 | inst.instruction |= inst.operands[1].reg << 16; |
| 9933 | inst.instruction |= inst.operands[2].reg; |
| 9934 | inst.instruction |= inst.operands[3].reg << 8; |
| 9935 | |
| 9936 | /* rdhi and rdlo must be different. */ |
| 9937 | if (inst.operands[0].reg == inst.operands[1].reg) |
| 9938 | as_tsktsk (_("rdhi and rdlo must be different")); |
| 9939 | |
| 9940 | /* rdhi, rdlo and rm must all be different before armv6. */ |
| 9941 | if ((inst.operands[0].reg == inst.operands[2].reg |
| 9942 | || inst.operands[1].reg == inst.operands[2].reg) |
| 9943 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) |
| 9944 | as_tsktsk (_("rdhi, rdlo and rm must all be different")); |
| 9945 | } |
| 9946 | |
| 9947 | static void |
| 9948 | do_nop (void) |
| 9949 | { |
| 9950 | if (inst.operands[0].present |
| 9951 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k)) |
| 9952 | { |
| 9953 | /* Architectural NOP hints are CPSR sets with no bits selected. */ |
| 9954 | inst.instruction &= 0xf0000000; |
| 9955 | inst.instruction |= 0x0320f000; |
| 9956 | if (inst.operands[0].present) |
| 9957 | inst.instruction |= inst.operands[0].imm; |
| 9958 | } |
| 9959 | } |
| 9960 | |
| 9961 | /* ARM V6 Pack Halfword Bottom Top instruction (argument parse). |
| 9962 | PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} |
| 9963 | Condition defaults to COND_ALWAYS. |
| 9964 | Error if Rd, Rn or Rm are R15. */ |
| 9965 | |
| 9966 | static void |
| 9967 | do_pkhbt (void) |
| 9968 | { |
| 9969 | inst.instruction |= inst.operands[0].reg << 12; |
| 9970 | inst.instruction |= inst.operands[1].reg << 16; |
| 9971 | inst.instruction |= inst.operands[2].reg; |
| 9972 | if (inst.operands[3].present) |
| 9973 | encode_arm_shift (3); |
| 9974 | } |
| 9975 | |
| 9976 | /* ARM V6 PKHTB (Argument Parse). */ |
| 9977 | |
| 9978 | static void |
| 9979 | do_pkhtb (void) |
| 9980 | { |
| 9981 | if (!inst.operands[3].present) |
| 9982 | { |
| 9983 | /* If the shift specifier is omitted, turn the instruction |
| 9984 | into pkhbt rd, rm, rn. */ |
| 9985 | inst.instruction &= 0xfff00010; |
| 9986 | inst.instruction |= inst.operands[0].reg << 12; |
| 9987 | inst.instruction |= inst.operands[1].reg; |
| 9988 | inst.instruction |= inst.operands[2].reg << 16; |
| 9989 | } |
| 9990 | else |
| 9991 | { |
| 9992 | inst.instruction |= inst.operands[0].reg << 12; |
| 9993 | inst.instruction |= inst.operands[1].reg << 16; |
| 9994 | inst.instruction |= inst.operands[2].reg; |
| 9995 | encode_arm_shift (3); |
| 9996 | } |
| 9997 | } |
| 9998 | |
| 9999 | /* ARMv5TE: Preload-Cache |
| 10000 | MP Extensions: Preload for write |
| 10001 | |
| 10002 | PLD(W) <addr_mode> |
| 10003 | |
| 10004 | Syntactically, like LDR with B=1, W=0, L=1. */ |
| 10005 | |
| 10006 | static void |
| 10007 | do_pld (void) |
| 10008 | { |
| 10009 | constraint (!inst.operands[0].isreg, |
| 10010 | _("'[' expected after PLD mnemonic")); |
| 10011 | constraint (inst.operands[0].postind, |
| 10012 | _("post-indexed expression used in preload instruction")); |
| 10013 | constraint (inst.operands[0].writeback, |
| 10014 | _("writeback used in preload instruction")); |
| 10015 | constraint (!inst.operands[0].preind, |
| 10016 | _("unindexed addressing used in preload instruction")); |
| 10017 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); |
| 10018 | } |
| 10019 | |
| 10020 | /* ARMv7: PLI <addr_mode> */ |
| 10021 | static void |
| 10022 | do_pli (void) |
| 10023 | { |
| 10024 | constraint (!inst.operands[0].isreg, |
| 10025 | _("'[' expected after PLI mnemonic")); |
| 10026 | constraint (inst.operands[0].postind, |
| 10027 | _("post-indexed expression used in preload instruction")); |
| 10028 | constraint (inst.operands[0].writeback, |
| 10029 | _("writeback used in preload instruction")); |
| 10030 | constraint (!inst.operands[0].preind, |
| 10031 | _("unindexed addressing used in preload instruction")); |
| 10032 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); |
| 10033 | inst.instruction &= ~PRE_INDEX; |
| 10034 | } |
| 10035 | |
| 10036 | static void |
| 10037 | do_push_pop (void) |
| 10038 | { |
| 10039 | constraint (inst.operands[0].writeback, |
| 10040 | _("push/pop do not support {reglist}^")); |
| 10041 | inst.operands[1] = inst.operands[0]; |
| 10042 | memset (&inst.operands[0], 0, sizeof inst.operands[0]); |
| 10043 | inst.operands[0].isreg = 1; |
| 10044 | inst.operands[0].writeback = 1; |
| 10045 | inst.operands[0].reg = REG_SP; |
| 10046 | encode_ldmstm (/*from_push_pop_mnem=*/TRUE); |
| 10047 | } |
| 10048 | |
| 10049 | /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the |
| 10050 | word at the specified address and the following word |
| 10051 | respectively. |
| 10052 | Unconditionally executed. |
| 10053 | Error if Rn is R15. */ |
| 10054 | |
| 10055 | static void |
| 10056 | do_rfe (void) |
| 10057 | { |
| 10058 | inst.instruction |= inst.operands[0].reg << 16; |
| 10059 | if (inst.operands[0].writeback) |
| 10060 | inst.instruction |= WRITE_BACK; |
| 10061 | } |
| 10062 | |
| 10063 | /* ARM V6 ssat (argument parse). */ |
| 10064 | |
| 10065 | static void |
| 10066 | do_ssat (void) |
| 10067 | { |
| 10068 | inst.instruction |= inst.operands[0].reg << 12; |
| 10069 | inst.instruction |= (inst.operands[1].imm - 1) << 16; |
| 10070 | inst.instruction |= inst.operands[2].reg; |
| 10071 | |
| 10072 | if (inst.operands[3].present) |
| 10073 | encode_arm_shift (3); |
| 10074 | } |
| 10075 | |
| 10076 | /* ARM V6 usat (argument parse). */ |
| 10077 | |
| 10078 | static void |
| 10079 | do_usat (void) |
| 10080 | { |
| 10081 | inst.instruction |= inst.operands[0].reg << 12; |
| 10082 | inst.instruction |= inst.operands[1].imm << 16; |
| 10083 | inst.instruction |= inst.operands[2].reg; |
| 10084 | |
| 10085 | if (inst.operands[3].present) |
| 10086 | encode_arm_shift (3); |
| 10087 | } |
| 10088 | |
| 10089 | /* ARM V6 ssat16 (argument parse). */ |
| 10090 | |
| 10091 | static void |
| 10092 | do_ssat16 (void) |
| 10093 | { |
| 10094 | inst.instruction |= inst.operands[0].reg << 12; |
| 10095 | inst.instruction |= ((inst.operands[1].imm - 1) << 16); |
| 10096 | inst.instruction |= inst.operands[2].reg; |
| 10097 | } |
| 10098 | |
| 10099 | static void |
| 10100 | do_usat16 (void) |
| 10101 | { |
| 10102 | inst.instruction |= inst.operands[0].reg << 12; |
| 10103 | inst.instruction |= inst.operands[1].imm << 16; |
| 10104 | inst.instruction |= inst.operands[2].reg; |
| 10105 | } |
| 10106 | |
| 10107 | /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while |
| 10108 | preserving the other bits. |
| 10109 | |
| 10110 | setend <endian_specifier>, where <endian_specifier> is either |
| 10111 | BE or LE. */ |
| 10112 | |
| 10113 | static void |
| 10114 | do_setend (void) |
| 10115 | { |
| 10116 | if (warn_on_deprecated |
| 10117 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) |
| 10118 | as_tsktsk (_("setend use is deprecated for ARMv8")); |
| 10119 | |
| 10120 | if (inst.operands[0].imm) |
| 10121 | inst.instruction |= 0x200; |
| 10122 | } |
| 10123 | |
| 10124 | static void |
| 10125 | do_shift (void) |
| 10126 | { |
| 10127 | unsigned int Rm = (inst.operands[1].present |
| 10128 | ? inst.operands[1].reg |
| 10129 | : inst.operands[0].reg); |
| 10130 | |
| 10131 | inst.instruction |= inst.operands[0].reg << 12; |
| 10132 | inst.instruction |= Rm; |
| 10133 | if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ |
| 10134 | { |
| 10135 | inst.instruction |= inst.operands[2].reg << 8; |
| 10136 | inst.instruction |= SHIFT_BY_REG; |
| 10137 | /* PR 12854: Error on extraneous shifts. */ |
| 10138 | constraint (inst.operands[2].shifted, |
| 10139 | _("extraneous shift as part of operand to shift insn")); |
| 10140 | } |
| 10141 | else |
| 10142 | inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM; |
| 10143 | } |
| 10144 | |
| 10145 | static void |
| 10146 | do_smc (void) |
| 10147 | { |
| 10148 | inst.relocs[0].type = BFD_RELOC_ARM_SMC; |
| 10149 | inst.relocs[0].pc_rel = 0; |
| 10150 | } |
| 10151 | |
| 10152 | static void |
| 10153 | do_hvc (void) |
| 10154 | { |
| 10155 | inst.relocs[0].type = BFD_RELOC_ARM_HVC; |
| 10156 | inst.relocs[0].pc_rel = 0; |
| 10157 | } |
| 10158 | |
| 10159 | static void |
| 10160 | do_swi (void) |
| 10161 | { |
| 10162 | inst.relocs[0].type = BFD_RELOC_ARM_SWI; |
| 10163 | inst.relocs[0].pc_rel = 0; |
| 10164 | } |
| 10165 | |
| 10166 | static void |
| 10167 | do_setpan (void) |
| 10168 | { |
| 10169 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan), |
| 10170 | _("selected processor does not support SETPAN instruction")); |
| 10171 | |
| 10172 | inst.instruction |= ((inst.operands[0].imm & 1) << 9); |
| 10173 | } |
| 10174 | |
| 10175 | static void |
| 10176 | do_t_setpan (void) |
| 10177 | { |
| 10178 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan), |
| 10179 | _("selected processor does not support SETPAN instruction")); |
| 10180 | |
| 10181 | inst.instruction |= (inst.operands[0].imm << 3); |
| 10182 | } |
| 10183 | |
| 10184 | /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) |
| 10185 | SMLAxy{cond} Rd,Rm,Rs,Rn |
| 10186 | SMLAWy{cond} Rd,Rm,Rs,Rn |
| 10187 | Error if any register is R15. */ |
| 10188 | |
| 10189 | static void |
| 10190 | do_smla (void) |
| 10191 | { |
| 10192 | inst.instruction |= inst.operands[0].reg << 16; |
| 10193 | inst.instruction |= inst.operands[1].reg; |
| 10194 | inst.instruction |= inst.operands[2].reg << 8; |
| 10195 | inst.instruction |= inst.operands[3].reg << 12; |
| 10196 | } |
| 10197 | |
| 10198 | /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) |
| 10199 | SMLALxy{cond} Rdlo,Rdhi,Rm,Rs |
| 10200 | Error if any register is R15. |
| 10201 | Warning if Rdlo == Rdhi. */ |
| 10202 | |
| 10203 | static void |
| 10204 | do_smlal (void) |
| 10205 | { |
| 10206 | inst.instruction |= inst.operands[0].reg << 12; |
| 10207 | inst.instruction |= inst.operands[1].reg << 16; |
| 10208 | inst.instruction |= inst.operands[2].reg; |
| 10209 | inst.instruction |= inst.operands[3].reg << 8; |
| 10210 | |
| 10211 | if (inst.operands[0].reg == inst.operands[1].reg) |
| 10212 | as_tsktsk (_("rdhi and rdlo must be different")); |
| 10213 | } |
| 10214 | |
| 10215 | /* ARM V5E (El Segundo) signed-multiply (argument parse) |
| 10216 | SMULxy{cond} Rd,Rm,Rs |
| 10217 | Error if any register is R15. */ |
| 10218 | |
| 10219 | static void |
| 10220 | do_smul (void) |
| 10221 | { |
| 10222 | inst.instruction |= inst.operands[0].reg << 16; |
| 10223 | inst.instruction |= inst.operands[1].reg; |
| 10224 | inst.instruction |= inst.operands[2].reg << 8; |
| 10225 | } |
| 10226 | |
| 10227 | /* ARM V6 srs (argument parse). The variable fields in the encoding are |
| 10228 | the same for both ARM and Thumb-2. */ |
| 10229 | |
| 10230 | static void |
| 10231 | do_srs (void) |
| 10232 | { |
| 10233 | int reg; |
| 10234 | |
| 10235 | if (inst.operands[0].present) |
| 10236 | { |
| 10237 | reg = inst.operands[0].reg; |
| 10238 | constraint (reg != REG_SP, _("SRS base register must be r13")); |
| 10239 | } |
| 10240 | else |
| 10241 | reg = REG_SP; |
| 10242 | |
| 10243 | inst.instruction |= reg << 16; |
| 10244 | inst.instruction |= inst.operands[1].imm; |
| 10245 | if (inst.operands[0].writeback || inst.operands[1].writeback) |
| 10246 | inst.instruction |= WRITE_BACK; |
| 10247 | } |
| 10248 | |
| 10249 | /* ARM V6 strex (argument parse). */ |
| 10250 | |
| 10251 | static void |
| 10252 | do_strex (void) |
| 10253 | { |
| 10254 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind |
| 10255 | || inst.operands[2].postind || inst.operands[2].writeback |
| 10256 | || inst.operands[2].immisreg || inst.operands[2].shifted |
| 10257 | || inst.operands[2].negative |
| 10258 | /* See comment in do_ldrex(). */ |
| 10259 | || (inst.operands[2].reg == REG_PC), |
| 10260 | BAD_ADDR_MODE); |
| 10261 | |
| 10262 | constraint (inst.operands[0].reg == inst.operands[1].reg |
| 10263 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); |
| 10264 | |
| 10265 | constraint (inst.relocs[0].exp.X_op != O_constant |
| 10266 | || inst.relocs[0].exp.X_add_number != 0, |
| 10267 | _("offset must be zero in ARM encoding")); |
| 10268 | |
| 10269 | inst.instruction |= inst.operands[0].reg << 12; |
| 10270 | inst.instruction |= inst.operands[1].reg; |
| 10271 | inst.instruction |= inst.operands[2].reg << 16; |
| 10272 | inst.relocs[0].type = BFD_RELOC_UNUSED; |
| 10273 | } |
| 10274 | |
| 10275 | static void |
| 10276 | do_t_strexbh (void) |
| 10277 | { |
| 10278 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind |
| 10279 | || inst.operands[2].postind || inst.operands[2].writeback |
| 10280 | || inst.operands[2].immisreg || inst.operands[2].shifted |
| 10281 | || inst.operands[2].negative, |
| 10282 | BAD_ADDR_MODE); |
| 10283 | |
| 10284 | constraint (inst.operands[0].reg == inst.operands[1].reg |
| 10285 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); |
| 10286 | |
| 10287 | do_rm_rd_rn (); |
| 10288 | } |
| 10289 | |
| 10290 | static void |
| 10291 | do_strexd (void) |
| 10292 | { |
| 10293 | constraint (inst.operands[1].reg % 2 != 0, |
| 10294 | _("even register required")); |
| 10295 | constraint (inst.operands[2].present |
| 10296 | && inst.operands[2].reg != inst.operands[1].reg + 1, |
| 10297 | _("can only store two consecutive registers")); |
| 10298 | /* If op 2 were present and equal to PC, this function wouldn't |
| 10299 | have been called in the first place. */ |
| 10300 | constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); |
| 10301 | |
| 10302 | constraint (inst.operands[0].reg == inst.operands[1].reg |
| 10303 | || inst.operands[0].reg == inst.operands[1].reg + 1 |
| 10304 | || inst.operands[0].reg == inst.operands[3].reg, |
| 10305 | BAD_OVERLAP); |
| 10306 | |
| 10307 | inst.instruction |= inst.operands[0].reg << 12; |
| 10308 | inst.instruction |= inst.operands[1].reg; |
| 10309 | inst.instruction |= inst.operands[3].reg << 16; |
| 10310 | } |
| 10311 | |
| 10312 | /* ARM V8 STRL. */ |
| 10313 | static void |
| 10314 | do_stlex (void) |
| 10315 | { |
| 10316 | constraint (inst.operands[0].reg == inst.operands[1].reg |
| 10317 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); |
| 10318 | |
| 10319 | do_rd_rm_rn (); |
| 10320 | } |
| 10321 | |
| 10322 | static void |
| 10323 | do_t_stlex (void) |
| 10324 | { |
| 10325 | constraint (inst.operands[0].reg == inst.operands[1].reg |
| 10326 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); |
| 10327 | |
| 10328 | do_rm_rd_rn (); |
| 10329 | } |
| 10330 | |
| 10331 | /* ARM V6 SXTAH extracts a 16-bit value from a register, sign |
| 10332 | extends it to 32-bits, and adds the result to a value in another |
| 10333 | register. You can specify a rotation by 0, 8, 16, or 24 bits |
| 10334 | before extracting the 16-bit value. |
| 10335 | SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} |
| 10336 | Condition defaults to COND_ALWAYS. |
| 10337 | Error if any register uses R15. */ |
| 10338 | |
| 10339 | static void |
| 10340 | do_sxtah (void) |
| 10341 | { |
| 10342 | inst.instruction |= inst.operands[0].reg << 12; |
| 10343 | inst.instruction |= inst.operands[1].reg << 16; |
| 10344 | inst.instruction |= inst.operands[2].reg; |
| 10345 | inst.instruction |= inst.operands[3].imm << 10; |
| 10346 | } |
| 10347 | |
| 10348 | /* ARM V6 SXTH. |
| 10349 | |
| 10350 | SXTH {<cond>} <Rd>, <Rm>{, <rotation>} |
| 10351 | Condition defaults to COND_ALWAYS. |
| 10352 | Error if any register uses R15. */ |
| 10353 | |
| 10354 | static void |
| 10355 | do_sxth (void) |
| 10356 | { |
| 10357 | inst.instruction |= inst.operands[0].reg << 12; |
| 10358 | inst.instruction |= inst.operands[1].reg; |
| 10359 | inst.instruction |= inst.operands[2].imm << 10; |
| 10360 | } |
| 10361 | \f |
| 10362 | /* VFP instructions. In a logical order: SP variant first, monad |
| 10363 | before dyad, arithmetic then move then load/store. */ |
| 10364 | |
| 10365 | static void |
| 10366 | do_vfp_sp_monadic (void) |
| 10367 | { |
| 10368 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd) |
| 10369 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), |
| 10370 | _(BAD_FPU)); |
| 10371 | |
| 10372 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
| 10373 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); |
| 10374 | } |
| 10375 | |
| 10376 | static void |
| 10377 | do_vfp_sp_dyadic (void) |
| 10378 | { |
| 10379 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
| 10380 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); |
| 10381 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); |
| 10382 | } |
| 10383 | |
| 10384 | static void |
| 10385 | do_vfp_sp_compare_z (void) |
| 10386 | { |
| 10387 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
| 10388 | } |
| 10389 | |
| 10390 | static void |
| 10391 | do_vfp_dp_sp_cvt (void) |
| 10392 | { |
| 10393 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
| 10394 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); |
| 10395 | } |
| 10396 | |
| 10397 | static void |
| 10398 | do_vfp_sp_dp_cvt (void) |
| 10399 | { |
| 10400 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
| 10401 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); |
| 10402 | } |
| 10403 | |
| 10404 | static void |
| 10405 | do_vfp_reg_from_sp (void) |
| 10406 | { |
| 10407 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd) |
| 10408 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), |
| 10409 | _(BAD_FPU)); |
| 10410 | |
| 10411 | inst.instruction |= inst.operands[0].reg << 12; |
| 10412 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); |
| 10413 | } |
| 10414 | |
| 10415 | static void |
| 10416 | do_vfp_reg2_from_sp2 (void) |
| 10417 | { |
| 10418 | constraint (inst.operands[2].imm != 2, |
| 10419 | _("only two consecutive VFP SP registers allowed here")); |
| 10420 | inst.instruction |= inst.operands[0].reg << 12; |
| 10421 | inst.instruction |= inst.operands[1].reg << 16; |
| 10422 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); |
| 10423 | } |
| 10424 | |
| 10425 | static void |
| 10426 | do_vfp_sp_from_reg (void) |
| 10427 | { |
| 10428 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd) |
| 10429 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), |
| 10430 | _(BAD_FPU)); |
| 10431 | |
| 10432 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); |
| 10433 | inst.instruction |= inst.operands[1].reg << 12; |
| 10434 | } |
| 10435 | |
| 10436 | static void |
| 10437 | do_vfp_sp2_from_reg2 (void) |
| 10438 | { |
| 10439 | constraint (inst.operands[0].imm != 2, |
| 10440 | _("only two consecutive VFP SP registers allowed here")); |
| 10441 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); |
| 10442 | inst.instruction |= inst.operands[1].reg << 12; |
| 10443 | inst.instruction |= inst.operands[2].reg << 16; |
| 10444 | } |
| 10445 | |
| 10446 | static void |
| 10447 | do_vfp_sp_ldst (void) |
| 10448 | { |
| 10449 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
| 10450 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
| 10451 | } |
| 10452 | |
| 10453 | static void |
| 10454 | do_vfp_dp_ldst (void) |
| 10455 | { |
| 10456 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
| 10457 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
| 10458 | } |
| 10459 | |
| 10460 | |
| 10461 | static void |
| 10462 | vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) |
| 10463 | { |
| 10464 | if (inst.operands[0].writeback) |
| 10465 | inst.instruction |= WRITE_BACK; |
| 10466 | else |
| 10467 | constraint (ldstm_type != VFP_LDSTMIA, |
| 10468 | _("this addressing mode requires base-register writeback")); |
| 10469 | inst.instruction |= inst.operands[0].reg << 16; |
| 10470 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); |
| 10471 | inst.instruction |= inst.operands[1].imm; |
| 10472 | } |
| 10473 | |
| 10474 | static void |
| 10475 | vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) |
| 10476 | { |
| 10477 | int count; |
| 10478 | |
| 10479 | if (inst.operands[0].writeback) |
| 10480 | inst.instruction |= WRITE_BACK; |
| 10481 | else |
| 10482 | constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, |
| 10483 | _("this addressing mode requires base-register writeback")); |
| 10484 | |
| 10485 | inst.instruction |= inst.operands[0].reg << 16; |
| 10486 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); |
| 10487 | |
| 10488 | count = inst.operands[1].imm << 1; |
| 10489 | if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) |
| 10490 | count += 1; |
| 10491 | |
| 10492 | inst.instruction |= count; |
| 10493 | } |
| 10494 | |
| 10495 | static void |
| 10496 | do_vfp_sp_ldstmia (void) |
| 10497 | { |
| 10498 | vfp_sp_ldstm (VFP_LDSTMIA); |
| 10499 | } |
| 10500 | |
| 10501 | static void |
| 10502 | do_vfp_sp_ldstmdb (void) |
| 10503 | { |
| 10504 | vfp_sp_ldstm (VFP_LDSTMDB); |
| 10505 | } |
| 10506 | |
| 10507 | static void |
| 10508 | do_vfp_dp_ldstmia (void) |
| 10509 | { |
| 10510 | vfp_dp_ldstm (VFP_LDSTMIA); |
| 10511 | } |
| 10512 | |
| 10513 | static void |
| 10514 | do_vfp_dp_ldstmdb (void) |
| 10515 | { |
| 10516 | vfp_dp_ldstm (VFP_LDSTMDB); |
| 10517 | } |
| 10518 | |
| 10519 | static void |
| 10520 | do_vfp_xp_ldstmia (void) |
| 10521 | { |
| 10522 | vfp_dp_ldstm (VFP_LDSTMIAX); |
| 10523 | } |
| 10524 | |
| 10525 | static void |
| 10526 | do_vfp_xp_ldstmdb (void) |
| 10527 | { |
| 10528 | vfp_dp_ldstm (VFP_LDSTMDBX); |
| 10529 | } |
| 10530 | |
| 10531 | static void |
| 10532 | do_vfp_dp_rd_rm (void) |
| 10533 | { |
| 10534 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1) |
| 10535 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), |
| 10536 | _(BAD_FPU)); |
| 10537 | |
| 10538 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
| 10539 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); |
| 10540 | } |
| 10541 | |
| 10542 | static void |
| 10543 | do_vfp_dp_rn_rd (void) |
| 10544 | { |
| 10545 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); |
| 10546 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); |
| 10547 | } |
| 10548 | |
| 10549 | static void |
| 10550 | do_vfp_dp_rd_rn (void) |
| 10551 | { |
| 10552 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
| 10553 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); |
| 10554 | } |
| 10555 | |
| 10556 | static void |
| 10557 | do_vfp_dp_rd_rn_rm (void) |
| 10558 | { |
| 10559 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2) |
| 10560 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), |
| 10561 | _(BAD_FPU)); |
| 10562 | |
| 10563 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
| 10564 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); |
| 10565 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); |
| 10566 | } |
| 10567 | |
| 10568 | static void |
| 10569 | do_vfp_dp_rd (void) |
| 10570 | { |
| 10571 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
| 10572 | } |
| 10573 | |
| 10574 | static void |
| 10575 | do_vfp_dp_rm_rd_rn (void) |
| 10576 | { |
| 10577 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2) |
| 10578 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), |
| 10579 | _(BAD_FPU)); |
| 10580 | |
| 10581 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); |
| 10582 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); |
| 10583 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); |
| 10584 | } |
| 10585 | |
| 10586 | /* VFPv3 instructions. */ |
| 10587 | static void |
| 10588 | do_vfp_sp_const (void) |
| 10589 | { |
| 10590 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
| 10591 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
| 10592 | inst.instruction |= (inst.operands[1].imm & 0x0f); |
| 10593 | } |
| 10594 | |
| 10595 | static void |
| 10596 | do_vfp_dp_const (void) |
| 10597 | { |
| 10598 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
| 10599 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
| 10600 | inst.instruction |= (inst.operands[1].imm & 0x0f); |
| 10601 | } |
| 10602 | |
| 10603 | static void |
| 10604 | vfp_conv (int srcsize) |
| 10605 | { |
| 10606 | int immbits = srcsize - inst.operands[1].imm; |
| 10607 | |
| 10608 | if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize)) |
| 10609 | { |
| 10610 | /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16. |
| 10611 | i.e. immbits must be in range 0 - 16. */ |
| 10612 | inst.error = _("immediate value out of range, expected range [0, 16]"); |
| 10613 | return; |
| 10614 | } |
| 10615 | else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize)) |
| 10616 | { |
| 10617 | /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32. |
| 10618 | i.e. immbits must be in range 0 - 31. */ |
| 10619 | inst.error = _("immediate value out of range, expected range [1, 32]"); |
| 10620 | return; |
| 10621 | } |
| 10622 | |
| 10623 | inst.instruction |= (immbits & 1) << 5; |
| 10624 | inst.instruction |= (immbits >> 1); |
| 10625 | } |
| 10626 | |
| 10627 | static void |
| 10628 | do_vfp_sp_conv_16 (void) |
| 10629 | { |
| 10630 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
| 10631 | vfp_conv (16); |
| 10632 | } |
| 10633 | |
| 10634 | static void |
| 10635 | do_vfp_dp_conv_16 (void) |
| 10636 | { |
| 10637 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
| 10638 | vfp_conv (16); |
| 10639 | } |
| 10640 | |
| 10641 | static void |
| 10642 | do_vfp_sp_conv_32 (void) |
| 10643 | { |
| 10644 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
| 10645 | vfp_conv (32); |
| 10646 | } |
| 10647 | |
| 10648 | static void |
| 10649 | do_vfp_dp_conv_32 (void) |
| 10650 | { |
| 10651 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
| 10652 | vfp_conv (32); |
| 10653 | } |
| 10654 | \f |
| 10655 | /* FPA instructions. Also in a logical order. */ |
| 10656 | |
| 10657 | static void |
| 10658 | do_fpa_cmp (void) |
| 10659 | { |
| 10660 | inst.instruction |= inst.operands[0].reg << 16; |
| 10661 | inst.instruction |= inst.operands[1].reg; |
| 10662 | } |
| 10663 | |
| 10664 | static void |
| 10665 | do_fpa_ldmstm (void) |
| 10666 | { |
| 10667 | inst.instruction |= inst.operands[0].reg << 12; |
| 10668 | switch (inst.operands[1].imm) |
| 10669 | { |
| 10670 | case 1: inst.instruction |= CP_T_X; break; |
| 10671 | case 2: inst.instruction |= CP_T_Y; break; |
| 10672 | case 3: inst.instruction |= CP_T_Y | CP_T_X; break; |
| 10673 | case 4: break; |
| 10674 | default: abort (); |
| 10675 | } |
| 10676 | |
| 10677 | if (inst.instruction & (PRE_INDEX | INDEX_UP)) |
| 10678 | { |
| 10679 | /* The instruction specified "ea" or "fd", so we can only accept |
| 10680 | [Rn]{!}. The instruction does not really support stacking or |
| 10681 | unstacking, so we have to emulate these by setting appropriate |
| 10682 | bits and offsets. */ |
| 10683 | constraint (inst.relocs[0].exp.X_op != O_constant |
| 10684 | || inst.relocs[0].exp.X_add_number != 0, |
| 10685 | _("this instruction does not support indexing")); |
| 10686 | |
| 10687 | if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) |
| 10688 | inst.relocs[0].exp.X_add_number = 12 * inst.operands[1].imm; |
| 10689 | |
| 10690 | if (!(inst.instruction & INDEX_UP)) |
| 10691 | inst.relocs[0].exp.X_add_number = -inst.relocs[0].exp.X_add_number; |
| 10692 | |
| 10693 | if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) |
| 10694 | { |
| 10695 | inst.operands[2].preind = 0; |
| 10696 | inst.operands[2].postind = 1; |
| 10697 | } |
| 10698 | } |
| 10699 | |
| 10700 | encode_arm_cp_address (2, TRUE, TRUE, 0); |
| 10701 | } |
| 10702 | \f |
| 10703 | /* iWMMXt instructions: strictly in alphabetical order. */ |
| 10704 | |
| 10705 | static void |
| 10706 | do_iwmmxt_tandorc (void) |
| 10707 | { |
| 10708 | constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); |
| 10709 | } |
| 10710 | |
| 10711 | static void |
| 10712 | do_iwmmxt_textrc (void) |
| 10713 | { |
| 10714 | inst.instruction |= inst.operands[0].reg << 12; |
| 10715 | inst.instruction |= inst.operands[1].imm; |
| 10716 | } |
| 10717 | |
| 10718 | static void |
| 10719 | do_iwmmxt_textrm (void) |
| 10720 | { |
| 10721 | inst.instruction |= inst.operands[0].reg << 12; |
| 10722 | inst.instruction |= inst.operands[1].reg << 16; |
| 10723 | inst.instruction |= inst.operands[2].imm; |
| 10724 | } |
| 10725 | |
| 10726 | static void |
| 10727 | do_iwmmxt_tinsr (void) |
| 10728 | { |
| 10729 | inst.instruction |= inst.operands[0].reg << 16; |
| 10730 | inst.instruction |= inst.operands[1].reg << 12; |
| 10731 | inst.instruction |= inst.operands[2].imm; |
| 10732 | } |
| 10733 | |
| 10734 | static void |
| 10735 | do_iwmmxt_tmia (void) |
| 10736 | { |
| 10737 | inst.instruction |= inst.operands[0].reg << 5; |
| 10738 | inst.instruction |= inst.operands[1].reg; |
| 10739 | inst.instruction |= inst.operands[2].reg << 12; |
| 10740 | } |
| 10741 | |
| 10742 | static void |
| 10743 | do_iwmmxt_waligni (void) |
| 10744 | { |
| 10745 | inst.instruction |= inst.operands[0].reg << 12; |
| 10746 | inst.instruction |= inst.operands[1].reg << 16; |
| 10747 | inst.instruction |= inst.operands[2].reg; |
| 10748 | inst.instruction |= inst.operands[3].imm << 20; |
| 10749 | } |
| 10750 | |
| 10751 | static void |
| 10752 | do_iwmmxt_wmerge (void) |
| 10753 | { |
| 10754 | inst.instruction |= inst.operands[0].reg << 12; |
| 10755 | inst.instruction |= inst.operands[1].reg << 16; |
| 10756 | inst.instruction |= inst.operands[2].reg; |
| 10757 | inst.instruction |= inst.operands[3].imm << 21; |
| 10758 | } |
| 10759 | |
| 10760 | static void |
| 10761 | do_iwmmxt_wmov (void) |
| 10762 | { |
| 10763 | /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ |
| 10764 | inst.instruction |= inst.operands[0].reg << 12; |
| 10765 | inst.instruction |= inst.operands[1].reg << 16; |
| 10766 | inst.instruction |= inst.operands[1].reg; |
| 10767 | } |
| 10768 | |
| 10769 | static void |
| 10770 | do_iwmmxt_wldstbh (void) |
| 10771 | { |
| 10772 | int reloc; |
| 10773 | inst.instruction |= inst.operands[0].reg << 12; |
| 10774 | if (thumb_mode) |
| 10775 | reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; |
| 10776 | else |
| 10777 | reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; |
| 10778 | encode_arm_cp_address (1, TRUE, FALSE, reloc); |
| 10779 | } |
| 10780 | |
| 10781 | static void |
| 10782 | do_iwmmxt_wldstw (void) |
| 10783 | { |
| 10784 | /* RIWR_RIWC clears .isreg for a control register. */ |
| 10785 | if (!inst.operands[0].isreg) |
| 10786 | { |
| 10787 | constraint (inst.cond != COND_ALWAYS, BAD_COND); |
| 10788 | inst.instruction |= 0xf0000000; |
| 10789 | } |
| 10790 | |
| 10791 | inst.instruction |= inst.operands[0].reg << 12; |
| 10792 | encode_arm_cp_address (1, TRUE, TRUE, 0); |
| 10793 | } |
| 10794 | |
| 10795 | static void |
| 10796 | do_iwmmxt_wldstd (void) |
| 10797 | { |
| 10798 | inst.instruction |= inst.operands[0].reg << 12; |
| 10799 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2) |
| 10800 | && inst.operands[1].immisreg) |
| 10801 | { |
| 10802 | inst.instruction &= ~0x1a000ff; |
| 10803 | inst.instruction |= (0xfU << 28); |
| 10804 | if (inst.operands[1].preind) |
| 10805 | inst.instruction |= PRE_INDEX; |
| 10806 | if (!inst.operands[1].negative) |
| 10807 | inst.instruction |= INDEX_UP; |
| 10808 | if (inst.operands[1].writeback) |
| 10809 | inst.instruction |= WRITE_BACK; |
| 10810 | inst.instruction |= inst.operands[1].reg << 16; |
| 10811 | inst.instruction |= inst.relocs[0].exp.X_add_number << 4; |
| 10812 | inst.instruction |= inst.operands[1].imm; |
| 10813 | } |
| 10814 | else |
| 10815 | encode_arm_cp_address (1, TRUE, FALSE, 0); |
| 10816 | } |
| 10817 | |
| 10818 | static void |
| 10819 | do_iwmmxt_wshufh (void) |
| 10820 | { |
| 10821 | inst.instruction |= inst.operands[0].reg << 12; |
| 10822 | inst.instruction |= inst.operands[1].reg << 16; |
| 10823 | inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); |
| 10824 | inst.instruction |= (inst.operands[2].imm & 0x0f); |
| 10825 | } |
| 10826 | |
| 10827 | static void |
| 10828 | do_iwmmxt_wzero (void) |
| 10829 | { |
| 10830 | /* WZERO reg is an alias for WANDN reg, reg, reg. */ |
| 10831 | inst.instruction |= inst.operands[0].reg; |
| 10832 | inst.instruction |= inst.operands[0].reg << 12; |
| 10833 | inst.instruction |= inst.operands[0].reg << 16; |
| 10834 | } |
| 10835 | |
| 10836 | static void |
| 10837 | do_iwmmxt_wrwrwr_or_imm5 (void) |
| 10838 | { |
| 10839 | if (inst.operands[2].isreg) |
| 10840 | do_rd_rn_rm (); |
| 10841 | else { |
| 10842 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), |
| 10843 | _("immediate operand requires iWMMXt2")); |
| 10844 | do_rd_rn (); |
| 10845 | if (inst.operands[2].imm == 0) |
| 10846 | { |
| 10847 | switch ((inst.instruction >> 20) & 0xf) |
| 10848 | { |
| 10849 | case 4: |
| 10850 | case 5: |
| 10851 | case 6: |
| 10852 | case 7: |
| 10853 | /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */ |
| 10854 | inst.operands[2].imm = 16; |
| 10855 | inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20); |
| 10856 | break; |
| 10857 | case 8: |
| 10858 | case 9: |
| 10859 | case 10: |
| 10860 | case 11: |
| 10861 | /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */ |
| 10862 | inst.operands[2].imm = 32; |
| 10863 | inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20); |
| 10864 | break; |
| 10865 | case 12: |
| 10866 | case 13: |
| 10867 | case 14: |
| 10868 | case 15: |
| 10869 | { |
| 10870 | /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */ |
| 10871 | unsigned long wrn; |
| 10872 | wrn = (inst.instruction >> 16) & 0xf; |
| 10873 | inst.instruction &= 0xff0fff0f; |
| 10874 | inst.instruction |= wrn; |
| 10875 | /* Bail out here; the instruction is now assembled. */ |
| 10876 | return; |
| 10877 | } |
| 10878 | } |
| 10879 | } |
| 10880 | /* Map 32 -> 0, etc. */ |
| 10881 | inst.operands[2].imm &= 0x1f; |
| 10882 | inst.instruction |= (0xfU << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf); |
| 10883 | } |
| 10884 | } |
| 10885 | \f |
| 10886 | /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register |
| 10887 | operations first, then control, shift, and load/store. */ |
| 10888 | |
| 10889 | /* Insns like "foo X,Y,Z". */ |
| 10890 | |
| 10891 | static void |
| 10892 | do_mav_triple (void) |
| 10893 | { |
| 10894 | inst.instruction |= inst.operands[0].reg << 16; |
| 10895 | inst.instruction |= inst.operands[1].reg; |
| 10896 | inst.instruction |= inst.operands[2].reg << 12; |
| 10897 | } |
| 10898 | |
| 10899 | /* Insns like "foo W,X,Y,Z". |
| 10900 | where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ |
| 10901 | |
| 10902 | static void |
| 10903 | do_mav_quad (void) |
| 10904 | { |
| 10905 | inst.instruction |= inst.operands[0].reg << 5; |
| 10906 | inst.instruction |= inst.operands[1].reg << 12; |
| 10907 | inst.instruction |= inst.operands[2].reg << 16; |
| 10908 | inst.instruction |= inst.operands[3].reg; |
| 10909 | } |
| 10910 | |
| 10911 | /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ |
| 10912 | static void |
| 10913 | do_mav_dspsc (void) |
| 10914 | { |
| 10915 | inst.instruction |= inst.operands[1].reg << 12; |
| 10916 | } |
| 10917 | |
| 10918 | /* Maverick shift immediate instructions. |
| 10919 | cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. |
| 10920 | cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ |
| 10921 | |
| 10922 | static void |
| 10923 | do_mav_shift (void) |
| 10924 | { |
| 10925 | int imm = inst.operands[2].imm; |
| 10926 | |
| 10927 | inst.instruction |= inst.operands[0].reg << 12; |
| 10928 | inst.instruction |= inst.operands[1].reg << 16; |
| 10929 | |
| 10930 | /* Bits 0-3 of the insn should have bits 0-3 of the immediate. |
| 10931 | Bits 5-7 of the insn should have bits 4-6 of the immediate. |
| 10932 | Bit 4 should be 0. */ |
| 10933 | imm = (imm & 0xf) | ((imm & 0x70) << 1); |
| 10934 | |
| 10935 | inst.instruction |= imm; |
| 10936 | } |
| 10937 | \f |
| 10938 | /* XScale instructions. Also sorted arithmetic before move. */ |
| 10939 | |
| 10940 | /* Xscale multiply-accumulate (argument parse) |
| 10941 | MIAcc acc0,Rm,Rs |
| 10942 | MIAPHcc acc0,Rm,Rs |
| 10943 | MIAxycc acc0,Rm,Rs. */ |
| 10944 | |
| 10945 | static void |
| 10946 | do_xsc_mia (void) |
| 10947 | { |
| 10948 | inst.instruction |= inst.operands[1].reg; |
| 10949 | inst.instruction |= inst.operands[2].reg << 12; |
| 10950 | } |
| 10951 | |
| 10952 | /* Xscale move-accumulator-register (argument parse) |
| 10953 | |
| 10954 | MARcc acc0,RdLo,RdHi. */ |
| 10955 | |
| 10956 | static void |
| 10957 | do_xsc_mar (void) |
| 10958 | { |
| 10959 | inst.instruction |= inst.operands[1].reg << 12; |
| 10960 | inst.instruction |= inst.operands[2].reg << 16; |
| 10961 | } |
| 10962 | |
| 10963 | /* Xscale move-register-accumulator (argument parse) |
| 10964 | |
| 10965 | MRAcc RdLo,RdHi,acc0. */ |
| 10966 | |
| 10967 | static void |
| 10968 | do_xsc_mra (void) |
| 10969 | { |
| 10970 | constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); |
| 10971 | inst.instruction |= inst.operands[0].reg << 12; |
| 10972 | inst.instruction |= inst.operands[1].reg << 16; |
| 10973 | } |
| 10974 | \f |
| 10975 | /* Encoding functions relevant only to Thumb. */ |
| 10976 | |
| 10977 | /* inst.operands[i] is a shifted-register operand; encode |
| 10978 | it into inst.instruction in the format used by Thumb32. */ |
| 10979 | |
| 10980 | static void |
| 10981 | encode_thumb32_shifted_operand (int i) |
| 10982 | { |
| 10983 | unsigned int value = inst.relocs[0].exp.X_add_number; |
| 10984 | unsigned int shift = inst.operands[i].shift_kind; |
| 10985 | |
| 10986 | constraint (inst.operands[i].immisreg, |
| 10987 | _("shift by register not allowed in thumb mode")); |
| 10988 | inst.instruction |= inst.operands[i].reg; |
| 10989 | if (shift == SHIFT_RRX) |
| 10990 | inst.instruction |= SHIFT_ROR << 4; |
| 10991 | else |
| 10992 | { |
| 10993 | constraint (inst.relocs[0].exp.X_op != O_constant, |
| 10994 | _("expression too complex")); |
| 10995 | |
| 10996 | constraint (value > 32 |
| 10997 | || (value == 32 && (shift == SHIFT_LSL |
| 10998 | || shift == SHIFT_ROR)), |
| 10999 | _("shift expression is too large")); |
| 11000 | |
| 11001 | if (value == 0) |
| 11002 | shift = SHIFT_LSL; |
| 11003 | else if (value == 32) |
| 11004 | value = 0; |
| 11005 | |
| 11006 | inst.instruction |= shift << 4; |
| 11007 | inst.instruction |= (value & 0x1c) << 10; |
| 11008 | inst.instruction |= (value & 0x03) << 6; |
| 11009 | } |
| 11010 | } |
| 11011 | |
| 11012 | |
| 11013 | /* inst.operands[i] was set up by parse_address. Encode it into a |
| 11014 | Thumb32 format load or store instruction. Reject forms that cannot |
| 11015 | be used with such instructions. If is_t is true, reject forms that |
| 11016 | cannot be used with a T instruction; if is_d is true, reject forms |
| 11017 | that cannot be used with a D instruction. If it is a store insn, |
| 11018 | reject PC in Rn. */ |
| 11019 | |
| 11020 | static void |
| 11021 | encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) |
| 11022 | { |
| 11023 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
| 11024 | |
| 11025 | constraint (!inst.operands[i].isreg, |
| 11026 | _("Instruction does not support =N addresses")); |
| 11027 | |
| 11028 | inst.instruction |= inst.operands[i].reg << 16; |
| 11029 | if (inst.operands[i].immisreg) |
| 11030 | { |
| 11031 | constraint (is_pc, BAD_PC_ADDRESSING); |
| 11032 | constraint (is_t || is_d, _("cannot use register index with this instruction")); |
| 11033 | constraint (inst.operands[i].negative, |
| 11034 | _("Thumb does not support negative register indexing")); |
| 11035 | constraint (inst.operands[i].postind, |
| 11036 | _("Thumb does not support register post-indexing")); |
| 11037 | constraint (inst.operands[i].writeback, |
| 11038 | _("Thumb does not support register indexing with writeback")); |
| 11039 | constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, |
| 11040 | _("Thumb supports only LSL in shifted register indexing")); |
| 11041 | |
| 11042 | inst.instruction |= inst.operands[i].imm; |
| 11043 | if (inst.operands[i].shifted) |
| 11044 | { |
| 11045 | constraint (inst.relocs[0].exp.X_op != O_constant, |
| 11046 | _("expression too complex")); |
| 11047 | constraint (inst.relocs[0].exp.X_add_number < 0 |
| 11048 | || inst.relocs[0].exp.X_add_number > 3, |
| 11049 | _("shift out of range")); |
| 11050 | inst.instruction |= inst.relocs[0].exp.X_add_number << 4; |
| 11051 | } |
| 11052 | inst.relocs[0].type = BFD_RELOC_UNUSED; |
| 11053 | } |
| 11054 | else if (inst.operands[i].preind) |
| 11055 | { |
| 11056 | constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK); |
| 11057 | constraint (is_t && inst.operands[i].writeback, |
| 11058 | _("cannot use writeback with this instruction")); |
| 11059 | constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0), |
| 11060 | BAD_PC_ADDRESSING); |
| 11061 | |
| 11062 | if (is_d) |
| 11063 | { |
| 11064 | inst.instruction |= 0x01000000; |
| 11065 | if (inst.operands[i].writeback) |
| 11066 | inst.instruction |= 0x00200000; |
| 11067 | } |
| 11068 | else |
| 11069 | { |
| 11070 | inst.instruction |= 0x00000c00; |
| 11071 | if (inst.operands[i].writeback) |
| 11072 | inst.instruction |= 0x00000100; |
| 11073 | } |
| 11074 | inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
| 11075 | } |
| 11076 | else if (inst.operands[i].postind) |
| 11077 | { |
| 11078 | gas_assert (inst.operands[i].writeback); |
| 11079 | constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); |
| 11080 | constraint (is_t, _("cannot use post-indexing with this instruction")); |
| 11081 | |
| 11082 | if (is_d) |
| 11083 | inst.instruction |= 0x00200000; |
| 11084 | else |
| 11085 | inst.instruction |= 0x00000900; |
| 11086 | inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
| 11087 | } |
| 11088 | else /* unindexed - only for coprocessor */ |
| 11089 | inst.error = _("instruction does not accept unindexed addressing"); |
| 11090 | } |
| 11091 | |
| 11092 | /* Table of Thumb instructions which exist in both 16- and 32-bit |
| 11093 | encodings (the latter only in post-V6T2 cores). The index is the |
| 11094 | value used in the insns table below. When there is more than one |
| 11095 | possible 16-bit encoding for the instruction, this table always |
| 11096 | holds variant (1). |
| 11097 | Also contains several pseudo-instructions used during relaxation. */ |
| 11098 | #define T16_32_TAB \ |
| 11099 | X(_adc, 4140, eb400000), \ |
| 11100 | X(_adcs, 4140, eb500000), \ |
| 11101 | X(_add, 1c00, eb000000), \ |
| 11102 | X(_adds, 1c00, eb100000), \ |
| 11103 | X(_addi, 0000, f1000000), \ |
| 11104 | X(_addis, 0000, f1100000), \ |
| 11105 | X(_add_pc,000f, f20f0000), \ |
| 11106 | X(_add_sp,000d, f10d0000), \ |
| 11107 | X(_adr, 000f, f20f0000), \ |
| 11108 | X(_and, 4000, ea000000), \ |
| 11109 | X(_ands, 4000, ea100000), \ |
| 11110 | X(_asr, 1000, fa40f000), \ |
| 11111 | X(_asrs, 1000, fa50f000), \ |
| 11112 | X(_b, e000, f000b000), \ |
| 11113 | X(_bcond, d000, f0008000), \ |
| 11114 | X(_bf, 0000, f040e001), \ |
| 11115 | X(_bfcsel,0000, f000e001), \ |
| 11116 | X(_bfx, 0000, f060e001), \ |
| 11117 | X(_bfl, 0000, f000c001), \ |
| 11118 | X(_bflx, 0000, f070e001), \ |
| 11119 | X(_bic, 4380, ea200000), \ |
| 11120 | X(_bics, 4380, ea300000), \ |
| 11121 | X(_cmn, 42c0, eb100f00), \ |
| 11122 | X(_cmp, 2800, ebb00f00), \ |
| 11123 | X(_cpsie, b660, f3af8400), \ |
| 11124 | X(_cpsid, b670, f3af8600), \ |
| 11125 | X(_cpy, 4600, ea4f0000), \ |
| 11126 | X(_dec_sp,80dd, f1ad0d00), \ |
| 11127 | X(_dls, 0000, f040e001), \ |
| 11128 | X(_eor, 4040, ea800000), \ |
| 11129 | X(_eors, 4040, ea900000), \ |
| 11130 | X(_inc_sp,00dd, f10d0d00), \ |
| 11131 | X(_ldmia, c800, e8900000), \ |
| 11132 | X(_ldr, 6800, f8500000), \ |
| 11133 | X(_ldrb, 7800, f8100000), \ |
| 11134 | X(_ldrh, 8800, f8300000), \ |
| 11135 | X(_ldrsb, 5600, f9100000), \ |
| 11136 | X(_ldrsh, 5e00, f9300000), \ |
| 11137 | X(_ldr_pc,4800, f85f0000), \ |
| 11138 | X(_ldr_pc2,4800, f85f0000), \ |
| 11139 | X(_ldr_sp,9800, f85d0000), \ |
| 11140 | X(_le, 0000, f00fc001), \ |
| 11141 | X(_lsl, 0000, fa00f000), \ |
| 11142 | X(_lsls, 0000, fa10f000), \ |
| 11143 | X(_lsr, 0800, fa20f000), \ |
| 11144 | X(_lsrs, 0800, fa30f000), \ |
| 11145 | X(_mov, 2000, ea4f0000), \ |
| 11146 | X(_movs, 2000, ea5f0000), \ |
| 11147 | X(_mul, 4340, fb00f000), \ |
| 11148 | X(_muls, 4340, ffffffff), /* no 32b muls */ \ |
| 11149 | X(_mvn, 43c0, ea6f0000), \ |
| 11150 | X(_mvns, 43c0, ea7f0000), \ |
| 11151 | X(_neg, 4240, f1c00000), /* rsb #0 */ \ |
| 11152 | X(_negs, 4240, f1d00000), /* rsbs #0 */ \ |
| 11153 | X(_orr, 4300, ea400000), \ |
| 11154 | X(_orrs, 4300, ea500000), \ |
| 11155 | X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \ |
| 11156 | X(_push, b400, e92d0000), /* stmdb sp!,... */ \ |
| 11157 | X(_rev, ba00, fa90f080), \ |
| 11158 | X(_rev16, ba40, fa90f090), \ |
| 11159 | X(_revsh, bac0, fa90f0b0), \ |
| 11160 | X(_ror, 41c0, fa60f000), \ |
| 11161 | X(_rors, 41c0, fa70f000), \ |
| 11162 | X(_sbc, 4180, eb600000), \ |
| 11163 | X(_sbcs, 4180, eb700000), \ |
| 11164 | X(_stmia, c000, e8800000), \ |
| 11165 | X(_str, 6000, f8400000), \ |
| 11166 | X(_strb, 7000, f8000000), \ |
| 11167 | X(_strh, 8000, f8200000), \ |
| 11168 | X(_str_sp,9000, f84d0000), \ |
| 11169 | X(_sub, 1e00, eba00000), \ |
| 11170 | X(_subs, 1e00, ebb00000), \ |
| 11171 | X(_subi, 8000, f1a00000), \ |
| 11172 | X(_subis, 8000, f1b00000), \ |
| 11173 | X(_sxtb, b240, fa4ff080), \ |
| 11174 | X(_sxth, b200, fa0ff080), \ |
| 11175 | X(_tst, 4200, ea100f00), \ |
| 11176 | X(_uxtb, b2c0, fa5ff080), \ |
| 11177 | X(_uxth, b280, fa1ff080), \ |
| 11178 | X(_nop, bf00, f3af8000), \ |
| 11179 | X(_yield, bf10, f3af8001), \ |
| 11180 | X(_wfe, bf20, f3af8002), \ |
| 11181 | X(_wfi, bf30, f3af8003), \ |
| 11182 | X(_wls, 0000, f040c001), \ |
| 11183 | X(_sev, bf40, f3af8004), \ |
| 11184 | X(_sevl, bf50, f3af8005), \ |
| 11185 | X(_udf, de00, f7f0a000) |
| 11186 | |
| 11187 | /* To catch errors in encoding functions, the codes are all offset by |
| 11188 | 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined |
| 11189 | as 16-bit instructions. */ |
| 11190 | #define X(a,b,c) T_MNEM##a |
| 11191 | enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; |
| 11192 | #undef X |
| 11193 | |
| 11194 | #define X(a,b,c) 0x##b |
| 11195 | static const unsigned short thumb_op16[] = { T16_32_TAB }; |
| 11196 | #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) |
| 11197 | #undef X |
| 11198 | |
| 11199 | #define X(a,b,c) 0x##c |
| 11200 | static const unsigned int thumb_op32[] = { T16_32_TAB }; |
| 11201 | #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) |
| 11202 | #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) |
| 11203 | #undef X |
| 11204 | #undef T16_32_TAB |
| 11205 | |
| 11206 | /* Thumb instruction encoders, in alphabetical order. */ |
| 11207 | |
| 11208 | /* ADDW or SUBW. */ |
| 11209 | |
| 11210 | static void |
| 11211 | do_t_add_sub_w (void) |
| 11212 | { |
| 11213 | int Rd, Rn; |
| 11214 | |
| 11215 | Rd = inst.operands[0].reg; |
| 11216 | Rn = inst.operands[1].reg; |
| 11217 | |
| 11218 | /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this |
| 11219 | is the SP-{plus,minus}-immediate form of the instruction. */ |
| 11220 | if (Rn == REG_SP) |
| 11221 | constraint (Rd == REG_PC, BAD_PC); |
| 11222 | else |
| 11223 | reject_bad_reg (Rd); |
| 11224 | |
| 11225 | inst.instruction |= (Rn << 16) | (Rd << 8); |
| 11226 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12; |
| 11227 | } |
| 11228 | |
| 11229 | /* Parse an add or subtract instruction. We get here with inst.instruction |
| 11230 | equaling any of THUMB_OPCODE_add, adds, sub, or subs. */ |
| 11231 | |
| 11232 | static void |
| 11233 | do_t_add_sub (void) |
| 11234 | { |
| 11235 | int Rd, Rs, Rn; |
| 11236 | |
| 11237 | Rd = inst.operands[0].reg; |
| 11238 | Rs = (inst.operands[1].present |
| 11239 | ? inst.operands[1].reg /* Rd, Rs, foo */ |
| 11240 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ |
| 11241 | |
| 11242 | if (Rd == REG_PC) |
| 11243 | set_pred_insn_type_last (); |
| 11244 | |
| 11245 | if (unified_syntax) |
| 11246 | { |
| 11247 | bfd_boolean flags; |
| 11248 | bfd_boolean narrow; |
| 11249 | int opcode; |
| 11250 | |
| 11251 | flags = (inst.instruction == T_MNEM_adds |
| 11252 | || inst.instruction == T_MNEM_subs); |
| 11253 | if (flags) |
| 11254 | narrow = !in_pred_block (); |
| 11255 | else |
| 11256 | narrow = in_pred_block (); |
| 11257 | if (!inst.operands[2].isreg) |
| 11258 | { |
| 11259 | int add; |
| 11260 | |
| 11261 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) |
| 11262 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); |
| 11263 | |
| 11264 | add = (inst.instruction == T_MNEM_add |
| 11265 | || inst.instruction == T_MNEM_adds); |
| 11266 | opcode = 0; |
| 11267 | if (inst.size_req != 4) |
| 11268 | { |
| 11269 | /* Attempt to use a narrow opcode, with relaxation if |
| 11270 | appropriate. */ |
| 11271 | if (Rd == REG_SP && Rs == REG_SP && !flags) |
| 11272 | opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; |
| 11273 | else if (Rd <= 7 && Rs == REG_SP && add && !flags) |
| 11274 | opcode = T_MNEM_add_sp; |
| 11275 | else if (Rd <= 7 && Rs == REG_PC && add && !flags) |
| 11276 | opcode = T_MNEM_add_pc; |
| 11277 | else if (Rd <= 7 && Rs <= 7 && narrow) |
| 11278 | { |
| 11279 | if (flags) |
| 11280 | opcode = add ? T_MNEM_addis : T_MNEM_subis; |
| 11281 | else |
| 11282 | opcode = add ? T_MNEM_addi : T_MNEM_subi; |
| 11283 | } |
| 11284 | if (opcode) |
| 11285 | { |
| 11286 | inst.instruction = THUMB_OP16(opcode); |
| 11287 | inst.instruction |= (Rd << 4) | Rs; |
| 11288 | if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC |
| 11289 | || (inst.relocs[0].type |
| 11290 | > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)) |
| 11291 | { |
| 11292 | if (inst.size_req == 2) |
| 11293 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD; |
| 11294 | else |
| 11295 | inst.relax = opcode; |
| 11296 | } |
| 11297 | } |
| 11298 | else |
| 11299 | constraint (inst.size_req == 2, BAD_HIREG); |
| 11300 | } |
| 11301 | if (inst.size_req == 4 |
| 11302 | || (inst.size_req != 2 && !opcode)) |
| 11303 | { |
| 11304 | constraint ((inst.relocs[0].type |
| 11305 | >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC) |
| 11306 | && (inst.relocs[0].type |
| 11307 | <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) , |
| 11308 | THUMB1_RELOC_ONLY); |
| 11309 | if (Rd == REG_PC) |
| 11310 | { |
| 11311 | constraint (add, BAD_PC); |
| 11312 | constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, |
| 11313 | _("only SUBS PC, LR, #const allowed")); |
| 11314 | constraint (inst.relocs[0].exp.X_op != O_constant, |
| 11315 | _("expression too complex")); |
| 11316 | constraint (inst.relocs[0].exp.X_add_number < 0 |
| 11317 | || inst.relocs[0].exp.X_add_number > 0xff, |
| 11318 | _("immediate value out of range")); |
| 11319 | inst.instruction = T2_SUBS_PC_LR |
| 11320 | | inst.relocs[0].exp.X_add_number; |
| 11321 | inst.relocs[0].type = BFD_RELOC_UNUSED; |
| 11322 | return; |
| 11323 | } |
| 11324 | else if (Rs == REG_PC) |
| 11325 | { |
| 11326 | /* Always use addw/subw. */ |
| 11327 | inst.instruction = add ? 0xf20f0000 : 0xf2af0000; |
| 11328 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12; |
| 11329 | } |
| 11330 | else |
| 11331 | { |
| 11332 | inst.instruction = THUMB_OP32 (inst.instruction); |
| 11333 | inst.instruction = (inst.instruction & 0xe1ffffff) |
| 11334 | | 0x10000000; |
| 11335 | if (flags) |
| 11336 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE; |
| 11337 | else |
| 11338 | inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_IMM; |
| 11339 | } |
| 11340 | inst.instruction |= Rd << 8; |
| 11341 | inst.instruction |= Rs << 16; |
| 11342 | } |
| 11343 | } |
| 11344 | else |
| 11345 | { |
| 11346 | unsigned int value = inst.relocs[0].exp.X_add_number; |
| 11347 | unsigned int shift = inst.operands[2].shift_kind; |
| 11348 | |
| 11349 | Rn = inst.operands[2].reg; |
| 11350 | /* See if we can do this with a 16-bit instruction. */ |
| 11351 | if (!inst.operands[2].shifted && inst.size_req != 4) |
| 11352 | { |
| 11353 | if (Rd > 7 || Rs > 7 || Rn > 7) |
| 11354 | narrow = FALSE; |
| 11355 | |
| 11356 | if (narrow) |
| 11357 | { |
| 11358 | inst.instruction = ((inst.instruction == T_MNEM_adds |
| 11359 | || inst.instruction == T_MNEM_add) |
| 11360 | ? T_OPCODE_ADD_R3 |
| 11361 | : T_OPCODE_SUB_R3); |
| 11362 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); |
| 11363 | return; |
| 11364 | } |
| 11365 | |
| 11366 | if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn)) |
| 11367 | { |
| 11368 | /* Thumb-1 cores (except v6-M) require at least one high |
| 11369 | register in a narrow non flag setting add. */ |
| 11370 | if (Rd > 7 || Rn > 7 |
| 11371 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2) |
| 11372 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr)) |
| 11373 | { |
| 11374 | if (Rd == Rn) |
| 11375 | { |
| 11376 | Rn = Rs; |
| 11377 | Rs = Rd; |
| 11378 | } |
| 11379 | inst.instruction = T_OPCODE_ADD_HI; |
| 11380 | inst.instruction |= (Rd & 8) << 4; |
| 11381 | inst.instruction |= (Rd & 7); |
| 11382 | inst.instruction |= Rn << 3; |
| 11383 | return; |
| 11384 | } |
| 11385 | } |
| 11386 | } |
| 11387 | |
| 11388 | constraint (Rd == REG_PC, BAD_PC); |
| 11389 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) |
| 11390 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); |
| 11391 | constraint (Rs == REG_PC, BAD_PC); |
| 11392 | reject_bad_reg (Rn); |
| 11393 | |
| 11394 | /* If we get here, it can't be done in 16 bits. */ |
| 11395 | constraint (inst.operands[2].shifted && inst.operands[2].immisreg, |
| 11396 | _("shift must be constant")); |
| 11397 | inst.instruction = THUMB_OP32 (inst.instruction); |
| 11398 | inst.instruction |= Rd << 8; |
| 11399 | inst.instruction |= Rs << 16; |
| 11400 | constraint (Rd == REG_SP && Rs == REG_SP && value > 3, |
| 11401 | _("shift value over 3 not allowed in thumb mode")); |
| 11402 | constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL, |
| 11403 | _("only LSL shift allowed in thumb mode")); |
| 11404 | encode_thumb32_shifted_operand (2); |
| 11405 | } |
| 11406 | } |
| 11407 | else |
| 11408 | { |
| 11409 | constraint (inst.instruction == T_MNEM_adds |
| 11410 | || inst.instruction == T_MNEM_subs, |
| 11411 | BAD_THUMB32); |
| 11412 | |
| 11413 | if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ |
| 11414 | { |
| 11415 | constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) |
| 11416 | || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), |
| 11417 | BAD_HIREG); |
| 11418 | |
| 11419 | inst.instruction = (inst.instruction == T_MNEM_add |
| 11420 | ? 0x0000 : 0x8000); |
| 11421 | inst.instruction |= (Rd << 4) | Rs; |
| 11422 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD; |
| 11423 | return; |
| 11424 | } |
| 11425 | |
| 11426 | Rn = inst.operands[2].reg; |
| 11427 | constraint (inst.operands[2].shifted, _("unshifted register required")); |
| 11428 | |
| 11429 | /* We now have Rd, Rs, and Rn set to registers. */ |
| 11430 | if (Rd > 7 || Rs > 7 || Rn > 7) |
| 11431 | { |
| 11432 | /* Can't do this for SUB. */ |
| 11433 | constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); |
| 11434 | inst.instruction = T_OPCODE_ADD_HI; |
| 11435 | inst.instruction |= (Rd & 8) << 4; |
| 11436 | inst.instruction |= (Rd & 7); |
| 11437 | if (Rs == Rd) |
| 11438 | inst.instruction |= Rn << 3; |
| 11439 | else if (Rn == Rd) |
| 11440 | inst.instruction |= Rs << 3; |
| 11441 | else |
| 11442 | constraint (1, _("dest must overlap one source register")); |
| 11443 | } |
| 11444 | else |
| 11445 | { |
| 11446 | inst.instruction = (inst.instruction == T_MNEM_add |
| 11447 | ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); |
| 11448 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); |
| 11449 | } |
| 11450 | } |
| 11451 | } |
| 11452 | |
| 11453 | static void |
| 11454 | do_t_adr (void) |
| 11455 | { |
| 11456 | unsigned Rd; |
| 11457 | |
| 11458 | Rd = inst.operands[0].reg; |
| 11459 | reject_bad_reg (Rd); |
| 11460 | |
| 11461 | if (unified_syntax && inst.size_req == 0 && Rd <= 7) |
| 11462 | { |
| 11463 | /* Defer to section relaxation. */ |
| 11464 | inst.relax = inst.instruction; |
| 11465 | inst.instruction = THUMB_OP16 (inst.instruction); |
| 11466 | inst.instruction |= Rd << 4; |
| 11467 | } |
| 11468 | else if (unified_syntax && inst.size_req != 2) |
| 11469 | { |
| 11470 | /* Generate a 32-bit opcode. */ |
| 11471 | inst.instruction = THUMB_OP32 (inst.instruction); |
| 11472 | inst.instruction |= Rd << 8; |
| 11473 | inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_PC12; |
| 11474 | inst.relocs[0].pc_rel = 1; |
| 11475 | } |
| 11476 | else |
| 11477 | { |
| 11478 | /* Generate a 16-bit opcode. */ |
| 11479 | inst.instruction = THUMB_OP16 (inst.instruction); |
| 11480 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD; |
| 11481 | inst.relocs[0].exp.X_add_number -= 4; /* PC relative adjust. */ |
| 11482 | inst.relocs[0].pc_rel = 1; |
| 11483 | inst.instruction |= Rd << 4; |
| 11484 | } |
| 11485 | |
| 11486 | if (inst.relocs[0].exp.X_op == O_symbol |
| 11487 | && inst.relocs[0].exp.X_add_symbol != NULL |
| 11488 | && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol) |
| 11489 | && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol)) |
| 11490 | inst.relocs[0].exp.X_add_number += 1; |
| 11491 | } |
| 11492 | |
| 11493 | /* Arithmetic instructions for which there is just one 16-bit |
| 11494 | instruction encoding, and it allows only two low registers. |
| 11495 | For maximal compatibility with ARM syntax, we allow three register |
| 11496 | operands even when Thumb-32 instructions are not available, as long |
| 11497 | as the first two are identical. For instance, both "sbc r0,r1" and |
| 11498 | "sbc r0,r0,r1" are allowed. */ |
| 11499 | static void |
| 11500 | do_t_arit3 (void) |
| 11501 | { |
| 11502 | int Rd, Rs, Rn; |
| 11503 | |
| 11504 | Rd = inst.operands[0].reg; |
| 11505 | Rs = (inst.operands[1].present |
| 11506 | ? inst.operands[1].reg /* Rd, Rs, foo */ |
| 11507 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ |
| 11508 | Rn = inst.operands[2].reg; |
| 11509 | |
| 11510 | reject_bad_reg (Rd); |
| 11511 | reject_bad_reg (Rs); |
| 11512 | if (inst.operands[2].isreg) |
| 11513 | reject_bad_reg (Rn); |
| 11514 | |
| 11515 | if (unified_syntax) |
| 11516 | { |
| 11517 | if (!inst.operands[2].isreg) |
| 11518 | { |
| 11519 | /* For an immediate, we always generate a 32-bit opcode; |
| 11520 | section relaxation will shrink it later if possible. */ |
| 11521 | inst.instruction = THUMB_OP32 (inst.instruction); |
| 11522 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; |
| 11523 | inst.instruction |= Rd << 8; |
| 11524 | inst.instruction |= Rs << 16; |
| 11525 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE; |
| 11526 | } |
| 11527 | else |
| 11528 | { |
| 11529 | bfd_boolean narrow; |
| 11530 | |
| 11531 | /* See if we can do this with a 16-bit instruction. */ |
| 11532 | if (THUMB_SETS_FLAGS (inst.instruction)) |
| 11533 | narrow = !in_pred_block (); |
| 11534 | else |
| 11535 | narrow = in_pred_block (); |
| 11536 | |
| 11537 | if (Rd > 7 || Rn > 7 || Rs > 7) |
| 11538 | narrow = FALSE; |
| 11539 | if (inst.operands[2].shifted) |
| 11540 | narrow = FALSE; |
| 11541 | if (inst.size_req == 4) |
| 11542 | narrow = FALSE; |
| 11543 | |
| 11544 | if (narrow |
| 11545 | && Rd == Rs) |
| 11546 | { |
| 11547 | inst.instruction = THUMB_OP16 (inst.instruction); |
| 11548 | inst.instruction |= Rd; |
| 11549 | inst.instruction |= Rn << 3; |
| 11550 | return; |
| 11551 | } |
| 11552 | |
| 11553 | /* If we get here, it can't be done in 16 bits. */ |
| 11554 | constraint (inst.operands[2].shifted |
| 11555 | && inst.operands[2].immisreg, |
| 11556 | _("shift must be constant")); |
| 11557 | inst.instruction = THUMB_OP32 (inst.instruction); |
| 11558 | inst.instruction |= Rd << 8; |
| 11559 | inst.instruction |= Rs << 16; |
| 11560 | encode_thumb32_shifted_operand (2); |
| 11561 | } |
| 11562 | } |
| 11563 | else |
| 11564 | { |
| 11565 | /* On its face this is a lie - the instruction does set the |
| 11566 | flags. However, the only supported mnemonic in this mode |
| 11567 | says it doesn't. */ |
| 11568 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); |
| 11569 | |
| 11570 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
| 11571 | _("unshifted register required")); |
| 11572 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); |
| 11573 | constraint (Rd != Rs, |
| 11574 | _("dest and source1 must be the same register")); |
| 11575 | |
| 11576 | inst.instruction = THUMB_OP16 (inst.instruction); |
| 11577 | inst.instruction |= Rd; |
| 11578 | inst.instruction |= Rn << 3; |
| 11579 | } |
| 11580 | } |
| 11581 | |
| 11582 | /* Similarly, but for instructions where the arithmetic operation is |
| 11583 | commutative, so we can allow either of them to be different from |
| 11584 | the destination operand in a 16-bit instruction. For instance, all |
| 11585 | three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are |
| 11586 | accepted. */ |
| 11587 | static void |
| 11588 | do_t_arit3c (void) |
| 11589 | { |
| 11590 | int Rd, Rs, Rn; |
| 11591 | |
| 11592 | Rd = inst.operands[0].reg; |
| 11593 | Rs = (inst.operands[1].present |
| 11594 | ? inst.operands[1].reg /* Rd, Rs, foo */ |
| 11595 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ |
| 11596 | Rn = inst.operands[2].reg; |
| 11597 | |
| 11598 | reject_bad_reg (Rd); |
| 11599 | reject_bad_reg (Rs); |
| 11600 | if (inst.operands[2].isreg) |
| 11601 | reject_bad_reg (Rn); |
| 11602 | |
| 11603 | if (unified_syntax) |
| 11604 | { |
| 11605 | if (!inst.operands[2].isreg) |
| 11606 | { |
| 11607 | /* For an immediate, we always generate a 32-bit opcode; |
| 11608 | section relaxation will shrink it later if possible. */ |
| 11609 | inst.instruction = THUMB_OP32 (inst.instruction); |
| 11610 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; |
| 11611 | inst.instruction |= Rd << 8; |
| 11612 | inst.instruction |= Rs << 16; |
| 11613 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE; |
| 11614 | } |
| 11615 | else |
| 11616 | { |
| 11617 | bfd_boolean narrow; |
| 11618 | |
| 11619 | /* See if we can do this with a 16-bit instruction. */ |
| 11620 | if (THUMB_SETS_FLAGS (inst.instruction)) |
| 11621 | narrow = !in_pred_block (); |
| 11622 | else |
| 11623 | narrow = in_pred_block (); |
| 11624 | |
| 11625 | if (Rd > 7 || Rn > 7 || Rs > 7) |
| 11626 | narrow = FALSE; |
| 11627 | if (inst.operands[2].shifted) |
| 11628 | narrow = FALSE; |
| 11629 | if (inst.size_req == 4) |
| 11630 | narrow = FALSE; |
| 11631 | |
| 11632 | if (narrow) |
| 11633 | { |
| 11634 | if (Rd == Rs) |
| 11635 | { |
| 11636 | inst.instruction = THUMB_OP16 (inst.instruction); |
| 11637 | inst.instruction |= Rd; |
| 11638 | inst.instruction |= Rn << 3; |
| 11639 | return; |
| 11640 | } |
| 11641 | if (Rd == Rn) |
| 11642 | { |
| 11643 | inst.instruction = THUMB_OP16 (inst.instruction); |
| 11644 | inst.instruction |= Rd; |
| 11645 | inst.instruction |= Rs << 3; |
| 11646 | return; |
| 11647 | } |
| 11648 | } |
| 11649 | |
| 11650 | /* If we get here, it can't be done in 16 bits. */ |
| 11651 | constraint (inst.operands[2].shifted |
| 11652 | && inst.operands[2].immisreg, |
| 11653 | _("shift must be constant")); |
| 11654 | inst.instruction = THUMB_OP32 (inst.instruction); |
| 11655 | inst.instruction |= Rd << 8; |
| 11656 | inst.instruction |= Rs << 16; |
| 11657 | encode_thumb32_shifted_operand (2); |
| 11658 | } |
| 11659 | } |
| 11660 | else |
| 11661 | { |
| 11662 | /* On its face this is a lie - the instruction does set the |
| 11663 | flags. However, the only supported mnemonic in this mode |
| 11664 | says it doesn't. */ |
| 11665 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); |
| 11666 | |
| 11667 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
| 11668 | _("unshifted register required")); |
| 11669 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); |
| 11670 | |
| 11671 | inst.instruction = THUMB_OP16 (inst.instruction); |
| 11672 | inst.instruction |= Rd; |
| 11673 | |
| 11674 | if (Rd == Rs) |
| 11675 | inst.instruction |= Rn << 3; |
| 11676 | else if (Rd == Rn) |
| 11677 | inst.instruction |= Rs << 3; |
| 11678 | else |
| 11679 | constraint (1, _("dest must overlap one source register")); |
| 11680 | } |
| 11681 | } |
| 11682 | |
| 11683 | static void |
| 11684 | do_t_bfc (void) |
| 11685 | { |
| 11686 | unsigned Rd; |
| 11687 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; |
| 11688 | constraint (msb > 32, _("bit-field extends past end of register")); |
| 11689 | /* The instruction encoding stores the LSB and MSB, |
| 11690 | not the LSB and width. */ |
| 11691 | Rd = inst.operands[0].reg; |
| 11692 | reject_bad_reg (Rd); |
| 11693 | inst.instruction |= Rd << 8; |
| 11694 | inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; |
| 11695 | inst.instruction |= (inst.operands[1].imm & 0x03) << 6; |
| 11696 | inst.instruction |= msb - 1; |
| 11697 | } |
| 11698 | |
| 11699 | static void |
| 11700 | do_t_bfi (void) |
| 11701 | { |
| 11702 | int Rd, Rn; |
| 11703 | unsigned int msb; |
| 11704 | |
| 11705 | Rd = inst.operands[0].reg; |
| 11706 | reject_bad_reg (Rd); |
| 11707 | |
| 11708 | /* #0 in second position is alternative syntax for bfc, which is |
| 11709 | the same instruction but with REG_PC in the Rm field. */ |
| 11710 | if (!inst.operands[1].isreg) |
| 11711 | Rn = REG_PC; |
| 11712 | else |
| 11713 | { |
| 11714 | Rn = inst.operands[1].reg; |
| 11715 | reject_bad_reg (Rn); |
| 11716 | } |
| 11717 | |
| 11718 | msb = inst.operands[2].imm + inst.operands[3].imm; |
| 11719 | constraint (msb > 32, _("bit-field extends past end of register")); |
| 11720 | /* The instruction encoding stores the LSB and MSB, |
| 11721 | not the LSB and width. */ |
| 11722 | inst.instruction |= Rd << 8; |
| 11723 | inst.instruction |= Rn << 16; |
| 11724 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
| 11725 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; |
| 11726 | inst.instruction |= msb - 1; |
| 11727 | } |
| 11728 | |
| 11729 | static void |
| 11730 | do_t_bfx (void) |
| 11731 | { |
| 11732 | unsigned Rd, Rn; |
| 11733 | |
| 11734 | Rd = inst.operands[0].reg; |
| 11735 | Rn = inst.operands[1].reg; |
| 11736 | |
| 11737 | reject_bad_reg (Rd); |
| 11738 | reject_bad_reg (Rn); |
| 11739 | |
| 11740 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
| 11741 | _("bit-field extends past end of register")); |
| 11742 | inst.instruction |= Rd << 8; |
| 11743 | inst.instruction |= Rn << 16; |
| 11744 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
| 11745 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; |
| 11746 | inst.instruction |= inst.operands[3].imm - 1; |
| 11747 | } |
| 11748 | |
| 11749 | /* ARM V5 Thumb BLX (argument parse) |
| 11750 | BLX <target_addr> which is BLX(1) |
| 11751 | BLX <Rm> which is BLX(2) |
| 11752 | Unfortunately, there are two different opcodes for this mnemonic. |
| 11753 | So, the insns[].value is not used, and the code here zaps values |
| 11754 | into inst.instruction. |
| 11755 | |
| 11756 | ??? How to take advantage of the additional two bits of displacement |
| 11757 | available in Thumb32 mode? Need new relocation? */ |
| 11758 | |
| 11759 | static void |
| 11760 | do_t_blx (void) |
| 11761 | { |
| 11762 | set_pred_insn_type_last (); |
| 11763 | |
| 11764 | if (inst.operands[0].isreg) |
| 11765 | { |
| 11766 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
| 11767 | /* We have a register, so this is BLX(2). */ |
| 11768 | inst.instruction |= inst.operands[0].reg << 3; |
| 11769 | } |
| 11770 | else |
| 11771 | { |
| 11772 | /* No register. This must be BLX(1). */ |
| 11773 | inst.instruction = 0xf000e800; |
| 11774 | encode_branch (BFD_RELOC_THUMB_PCREL_BLX); |
| 11775 | } |
| 11776 | } |
| 11777 | |
| 11778 | static void |
| 11779 | do_t_branch (void) |
| 11780 | { |
| 11781 | int opcode; |
| 11782 | int cond; |
| 11783 | bfd_reloc_code_real_type reloc; |
| 11784 | |
| 11785 | cond = inst.cond; |
| 11786 | set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); |
| 11787 | |
| 11788 | if (in_pred_block ()) |
| 11789 | { |
| 11790 | /* Conditional branches inside IT blocks are encoded as unconditional |
| 11791 | branches. */ |
| 11792 | cond = COND_ALWAYS; |
| 11793 | } |
| 11794 | else |
| 11795 | cond = inst.cond; |
| 11796 | |
| 11797 | if (cond != COND_ALWAYS) |
| 11798 | opcode = T_MNEM_bcond; |
| 11799 | else |
| 11800 | opcode = inst.instruction; |
| 11801 | |
| 11802 | if (unified_syntax |
| 11803 | && (inst.size_req == 4 |
| 11804 | || (inst.size_req != 2 |
| 11805 | && (inst.operands[0].hasreloc |
| 11806 | || inst.relocs[0].exp.X_op == O_constant)))) |
| 11807 | { |
| 11808 | inst.instruction = THUMB_OP32(opcode); |
| 11809 | if (cond == COND_ALWAYS) |
| 11810 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH25; |
| 11811 | else |
| 11812 | { |
| 11813 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2), |
| 11814 | _("selected architecture does not support " |
| 11815 | "wide conditional branch instruction")); |
| 11816 | |
| 11817 | gas_assert (cond != 0xF); |
| 11818 | inst.instruction |= cond << 22; |
| 11819 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH20; |
| 11820 | } |
| 11821 | } |
| 11822 | else |
| 11823 | { |
| 11824 | inst.instruction = THUMB_OP16(opcode); |
| 11825 | if (cond == COND_ALWAYS) |
| 11826 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH12; |
| 11827 | else |
| 11828 | { |
| 11829 | inst.instruction |= cond << 8; |
| 11830 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH9; |
| 11831 | } |
| 11832 | /* Allow section relaxation. */ |
| 11833 | if (unified_syntax && inst.size_req != 2) |
| 11834 | inst.relax = opcode; |
| 11835 | } |
| 11836 | inst.relocs[0].type = reloc; |
| 11837 | inst.relocs[0].pc_rel = 1; |
| 11838 | } |
| 11839 | |
| 11840 | /* Actually do the work for Thumb state bkpt and hlt. The only difference |
| 11841 | between the two is the maximum immediate allowed - which is passed in |
| 11842 | RANGE. */ |
| 11843 | static void |
| 11844 | do_t_bkpt_hlt1 (int range) |
| 11845 | { |
| 11846 | constraint (inst.cond != COND_ALWAYS, |
| 11847 | _("instruction is always unconditional")); |
| 11848 | if (inst.operands[0].present) |
| 11849 | { |
| 11850 | constraint (inst.operands[0].imm > range, |
| 11851 | _("immediate value out of range")); |
| 11852 | inst.instruction |= inst.operands[0].imm; |
| 11853 | } |
| 11854 | |
| 11855 | set_pred_insn_type (NEUTRAL_IT_INSN); |
| 11856 | } |
| 11857 | |
| 11858 | static void |
| 11859 | do_t_hlt (void) |
| 11860 | { |
| 11861 | do_t_bkpt_hlt1 (63); |
| 11862 | } |
| 11863 | |
| 11864 | static void |
| 11865 | do_t_bkpt (void) |
| 11866 | { |
| 11867 | do_t_bkpt_hlt1 (255); |
| 11868 | } |
| 11869 | |
| 11870 | static void |
| 11871 | do_t_branch23 (void) |
| 11872 | { |
| 11873 | set_pred_insn_type_last (); |
| 11874 | encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23); |
| 11875 | |
| 11876 | /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in |
| 11877 | this file. We used to simply ignore the PLT reloc type here -- |
| 11878 | the branch encoding is now needed to deal with TLSCALL relocs. |
| 11879 | So if we see a PLT reloc now, put it back to how it used to be to |
| 11880 | keep the preexisting behaviour. */ |
| 11881 | if (inst.relocs[0].type == BFD_RELOC_ARM_PLT32) |
| 11882 | inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH23; |
| 11883 | |
| 11884 | #if defined(OBJ_COFF) |
| 11885 | /* If the destination of the branch is a defined symbol which does not have |
| 11886 | the THUMB_FUNC attribute, then we must be calling a function which has |
| 11887 | the (interfacearm) attribute. We look for the Thumb entry point to that |
| 11888 | function and change the branch to refer to that function instead. */ |
| 11889 | if ( inst.relocs[0].exp.X_op == O_symbol |
| 11890 | && inst.relocs[0].exp.X_add_symbol != NULL |
| 11891 | && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol) |
| 11892 | && ! THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol)) |
| 11893 | inst.relocs[0].exp.X_add_symbol |
| 11894 | = find_real_start (inst.relocs[0].exp.X_add_symbol); |
| 11895 | #endif |
| 11896 | } |
| 11897 | |
| 11898 | static void |
| 11899 | do_t_bx (void) |
| 11900 | { |
| 11901 | set_pred_insn_type_last (); |
| 11902 | inst.instruction |= inst.operands[0].reg << 3; |
| 11903 | /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc |
| 11904 | should cause the alignment to be checked once it is known. This is |
| 11905 | because BX PC only works if the instruction is word aligned. */ |
| 11906 | } |
| 11907 | |
| 11908 | static void |
| 11909 | do_t_bxj (void) |
| 11910 | { |
| 11911 | int Rm; |
| 11912 | |
| 11913 | set_pred_insn_type_last (); |
| 11914 | Rm = inst.operands[0].reg; |
| 11915 | reject_bad_reg (Rm); |
| 11916 | inst.instruction |= Rm << 16; |
| 11917 | } |
| 11918 | |
| 11919 | static void |
| 11920 | do_t_clz (void) |
| 11921 | { |
| 11922 | unsigned Rd; |
| 11923 | unsigned Rm; |
| 11924 | |
| 11925 | Rd = inst.operands[0].reg; |
| 11926 | Rm = inst.operands[1].reg; |
| 11927 | |
| 11928 | reject_bad_reg (Rd); |
| 11929 | reject_bad_reg (Rm); |
| 11930 | |
| 11931 | inst.instruction |= Rd << 8; |
| 11932 | inst.instruction |= Rm << 16; |
| 11933 | inst.instruction |= Rm; |
| 11934 | } |
| 11935 | |
| 11936 | static void |
| 11937 | do_t_csdb (void) |
| 11938 | { |
| 11939 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
| 11940 | } |
| 11941 | |
| 11942 | static void |
| 11943 | do_t_cps (void) |
| 11944 | { |
| 11945 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
| 11946 | inst.instruction |= inst.operands[0].imm; |
| 11947 | } |
| 11948 | |
| 11949 | static void |
| 11950 | do_t_cpsi (void) |
| 11951 | { |
| 11952 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
| 11953 | if (unified_syntax |
| 11954 | && (inst.operands[1].present || inst.size_req == 4) |
| 11955 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) |
| 11956 | { |
| 11957 | unsigned int imod = (inst.instruction & 0x0030) >> 4; |
| 11958 | inst.instruction = 0xf3af8000; |
| 11959 | inst.instruction |= imod << 9; |
| 11960 | inst.instruction |= inst.operands[0].imm << 5; |
| 11961 | if (inst.operands[1].present) |
| 11962 | inst.instruction |= 0x100 | inst.operands[1].imm; |
| 11963 | } |
| 11964 | else |
| 11965 | { |
| 11966 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) |
| 11967 | && (inst.operands[0].imm & 4), |
| 11968 | _("selected processor does not support 'A' form " |
| 11969 | "of this instruction")); |
| 11970 | constraint (inst.operands[1].present || inst.size_req == 4, |
| 11971 | _("Thumb does not support the 2-argument " |
| 11972 | "form of this instruction")); |
| 11973 | inst.instruction |= inst.operands[0].imm; |
| 11974 | } |
| 11975 | } |
| 11976 | |
| 11977 | /* THUMB CPY instruction (argument parse). */ |
| 11978 | |
| 11979 | static void |
| 11980 | do_t_cpy (void) |
| 11981 | { |
| 11982 | if (inst.size_req == 4) |
| 11983 | { |
| 11984 | inst.instruction = THUMB_OP32 (T_MNEM_mov); |
| 11985 | inst.instruction |= inst.operands[0].reg << 8; |
| 11986 | inst.instruction |= inst.operands[1].reg; |
| 11987 | } |
| 11988 | else |
| 11989 | { |
| 11990 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; |
| 11991 | inst.instruction |= (inst.operands[0].reg & 0x7); |
| 11992 | inst.instruction |= inst.operands[1].reg << 3; |
| 11993 | } |
| 11994 | } |
| 11995 | |
| 11996 | static void |
| 11997 | do_t_cbz (void) |
| 11998 | { |
| 11999 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
| 12000 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
| 12001 | inst.instruction |= inst.operands[0].reg; |
| 12002 | inst.relocs[0].pc_rel = 1; |
| 12003 | inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH7; |
| 12004 | } |
| 12005 | |
| 12006 | static void |
| 12007 | do_t_dbg (void) |
| 12008 | { |
| 12009 | inst.instruction |= inst.operands[0].imm; |
| 12010 | } |
| 12011 | |
| 12012 | static void |
| 12013 | do_t_div (void) |
| 12014 | { |
| 12015 | unsigned Rd, Rn, Rm; |
| 12016 | |
| 12017 | Rd = inst.operands[0].reg; |
| 12018 | Rn = (inst.operands[1].present |
| 12019 | ? inst.operands[1].reg : Rd); |
| 12020 | Rm = inst.operands[2].reg; |
| 12021 | |
| 12022 | reject_bad_reg (Rd); |
| 12023 | reject_bad_reg (Rn); |
| 12024 | reject_bad_reg (Rm); |
| 12025 | |
| 12026 | inst.instruction |= Rd << 8; |
| 12027 | inst.instruction |= Rn << 16; |
| 12028 | inst.instruction |= Rm; |
| 12029 | } |
| 12030 | |
| 12031 | static void |
| 12032 | do_t_hint (void) |
| 12033 | { |
| 12034 | if (unified_syntax && inst.size_req == 4) |
| 12035 | inst.instruction = THUMB_OP32 (inst.instruction); |
| 12036 | else |
| 12037 | inst.instruction = THUMB_OP16 (inst.instruction); |
| 12038 | } |
| 12039 | |
| 12040 | static void |
| 12041 | do_t_it (void) |
| 12042 | { |
| 12043 | unsigned int cond = inst.operands[0].imm; |
| 12044 | |
| 12045 | set_pred_insn_type (IT_INSN); |
| 12046 | now_pred.mask = (inst.instruction & 0xf) | 0x10; |
| 12047 | now_pred.cc = cond; |
| 12048 | now_pred.warn_deprecated = FALSE; |
| 12049 | now_pred.type = SCALAR_PRED; |
| 12050 | |
| 12051 | /* If the condition is a negative condition, invert the mask. */ |
| 12052 | if ((cond & 0x1) == 0x0) |
| 12053 | { |
| 12054 | unsigned int mask = inst.instruction & 0x000f; |
| 12055 | |
| 12056 | if ((mask & 0x7) == 0) |
| 12057 | { |
| 12058 | /* No conversion needed. */ |
| 12059 | now_pred.block_length = 1; |
| 12060 | } |
| 12061 | else if ((mask & 0x3) == 0) |
| 12062 | { |
| 12063 | mask ^= 0x8; |
| 12064 | now_pred.block_length = 2; |
| 12065 | } |
| 12066 | else if ((mask & 0x1) == 0) |
| 12067 | { |
| 12068 | mask ^= 0xC; |
| 12069 | now_pred.block_length = 3; |
| 12070 | } |
| 12071 | else |
| 12072 | { |
| 12073 | mask ^= 0xE; |
| 12074 | now_pred.block_length = 4; |
| 12075 | } |
| 12076 | |
| 12077 | inst.instruction &= 0xfff0; |
| 12078 | inst.instruction |= mask; |
| 12079 | } |
| 12080 | |
| 12081 | inst.instruction |= cond << 4; |
| 12082 | } |
| 12083 | |
| 12084 | /* Helper function used for both push/pop and ldm/stm. */ |
| 12085 | static void |
| 12086 | encode_thumb2_multi (bfd_boolean do_io, int base, unsigned mask, |
| 12087 | bfd_boolean writeback) |
| 12088 | { |
| 12089 | bfd_boolean load, store; |
| 12090 | |
| 12091 | gas_assert (base != -1 || !do_io); |
| 12092 | load = do_io && ((inst.instruction & (1 << 20)) != 0); |
| 12093 | store = do_io && !load; |
| 12094 | |
| 12095 | if (mask & (1 << 13)) |
| 12096 | inst.error = _("SP not allowed in register list"); |
| 12097 | |
| 12098 | if (do_io && (mask & (1 << base)) != 0 |
| 12099 | && writeback) |
| 12100 | inst.error = _("having the base register in the register list when " |
| 12101 | "using write back is UNPREDICTABLE"); |
| 12102 | |
| 12103 | if (load) |
| 12104 | { |
| 12105 | if (mask & (1 << 15)) |
| 12106 | { |
| 12107 | if (mask & (1 << 14)) |
| 12108 | inst.error = _("LR and PC should not both be in register list"); |
| 12109 | else |
| 12110 | set_pred_insn_type_last (); |
| 12111 | } |
| 12112 | } |
| 12113 | else if (store) |
| 12114 | { |
| 12115 | if (mask & (1 << 15)) |
| 12116 | inst.error = _("PC not allowed in register list"); |
| 12117 | } |
| 12118 | |
| 12119 | if (do_io && ((mask & (mask - 1)) == 0)) |
| 12120 | { |
| 12121 | /* Single register transfers implemented as str/ldr. */ |
| 12122 | if (writeback) |
| 12123 | { |
| 12124 | if (inst.instruction & (1 << 23)) |
| 12125 | inst.instruction = 0x00000b04; /* ia! -> [base], #4 */ |
| 12126 | else |
| 12127 | inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */ |
| 12128 | } |
| 12129 | else |
| 12130 | { |
| 12131 | if (inst.instruction & (1 << 23)) |
| 12132 | inst.instruction = 0x00800000; /* ia -> [base] */ |
| 12133 | else |
| 12134 | inst.instruction = 0x00000c04; /* db -> [base, #-4] */ |
| 12135 | } |
| 12136 | |
| 12137 | inst.instruction |= 0xf8400000; |
| 12138 | if (load) |
| 12139 | inst.instruction |= 0x00100000; |
| 12140 | |
| 12141 | mask = ffs (mask) - 1; |
| 12142 | mask <<= 12; |
| 12143 | } |
| 12144 | else if (writeback) |
| 12145 | inst.instruction |= WRITE_BACK; |
| 12146 | |
| 12147 | inst.instruction |= mask; |
| 12148 | if (do_io) |
| 12149 | inst.instruction |= base << 16; |
| 12150 | } |
| 12151 | |
| 12152 | static void |
| 12153 | do_t_ldmstm (void) |
| 12154 | { |
| 12155 | /* This really doesn't seem worth it. */ |
| 12156 | constraint (inst.relocs[0].type != BFD_RELOC_UNUSED, |
| 12157 | _("expression too complex")); |
| 12158 | constraint (inst.operands[1].writeback, |
| 12159 | _("Thumb load/store multiple does not support {reglist}^")); |
| 12160 | |
| 12161 | if (unified_syntax) |
| 12162 | { |
| 12163 | bfd_boolean narrow; |
| 12164 | unsigned mask; |
| 12165 | |
| 12166 | narrow = FALSE; |
| 12167 | /* See if we can use a 16-bit instruction. */ |
| 12168 | if (inst.instruction < 0xffff /* not ldmdb/stmdb */ |
| 12169 | && inst.size_req != 4 |
| 12170 | && !(inst.operands[1].imm & ~0xff)) |
| 12171 | { |
| 12172 | mask = 1 << inst.operands[0].reg; |
| 12173 | |
| 12174 | if (inst.operands[0].reg <= 7) |
| 12175 | { |
| 12176 | if (inst.instruction == T_MNEM_stmia |
| 12177 | ? inst.operands[0].writeback |
| 12178 | : (inst.operands[0].writeback |
| 12179 | == !(inst.operands[1].imm & mask))) |
| 12180 | { |
| 12181 | if (inst.instruction == T_MNEM_stmia |
| 12182 | && (inst.operands[1].imm & mask) |
| 12183 | && (inst.operands[1].imm & (mask - 1))) |
| 12184 | as_warn (_("value stored for r%d is UNKNOWN"), |
| 12185 | inst.operands[0].reg); |
| 12186 | |
| 12187 | inst.instruction = THUMB_OP16 (inst.instruction); |
| 12188 | inst.instruction |= inst.operands[0].reg << 8; |
| 12189 | inst.instruction |= inst.operands[1].imm; |
| 12190 | narrow = TRUE; |
| 12191 | } |
| 12192 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) |
| 12193 | { |
| 12194 | /* This means 1 register in reg list one of 3 situations: |
| 12195 | 1. Instruction is stmia, but without writeback. |
| 12196 | 2. lmdia without writeback, but with Rn not in |
| 12197 | reglist. |
| 12198 | 3. ldmia with writeback, but with Rn in reglist. |
| 12199 | Case 3 is UNPREDICTABLE behaviour, so we handle |
| 12200 | case 1 and 2 which can be converted into a 16-bit |
| 12201 | str or ldr. The SP cases are handled below. */ |
| 12202 | unsigned long opcode; |
| 12203 | /* First, record an error for Case 3. */ |
| 12204 | if (inst.operands[1].imm & mask |
| 12205 | && inst.operands[0].writeback) |
| 12206 | inst.error = |
| 12207 | _("having the base register in the register list when " |
| 12208 | "using write back is UNPREDICTABLE"); |
| 12209 | |
| 12210 | opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str |
| 12211 | : T_MNEM_ldr); |
| 12212 | inst.instruction = THUMB_OP16 (opcode); |
| 12213 | inst.instruction |= inst.operands[0].reg << 3; |
| 12214 | inst.instruction |= (ffs (inst.operands[1].imm)-1); |
| 12215 | narrow = TRUE; |
| 12216 | } |
| 12217 | } |
| 12218 | else if (inst.operands[0] .reg == REG_SP) |
| 12219 | { |
| 12220 | if (inst.operands[0].writeback) |
| 12221 | { |
| 12222 | inst.instruction = |
| 12223 | THUMB_OP16 (inst.instruction == T_MNEM_stmia |
| 12224 | ? T_MNEM_push : T_MNEM_pop); |
| 12225 | inst.instruction |= inst.operands[1].imm; |
| 12226 | narrow = TRUE; |
| 12227 | } |
| 12228 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) |
| 12229 | { |
| 12230 | inst.instruction = |
| 12231 | THUMB_OP16 (inst.instruction == T_MNEM_stmia |
| 12232 | ? T_MNEM_str_sp : T_MNEM_ldr_sp); |
| 12233 | inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8); |
| 12234 | narrow = TRUE; |
| 12235 | } |
| 12236 | } |
| 12237 | } |
| 12238 | |
| 12239 | if (!narrow) |
| 12240 | { |
| 12241 | if (inst.instruction < 0xffff) |
| 12242 | inst.instruction = THUMB_OP32 (inst.instruction); |
| 12243 | |
| 12244 | encode_thumb2_multi (TRUE /* do_io */, inst.operands[0].reg, |
| 12245 | inst.operands[1].imm, |
| 12246 | inst.operands[0].writeback); |
| 12247 | } |
| 12248 | } |
| 12249 | else |
| 12250 | { |
| 12251 | constraint (inst.operands[0].reg > 7 |
| 12252 | || (inst.operands[1].imm & ~0xff), BAD_HIREG); |
| 12253 | constraint (inst.instruction != T_MNEM_ldmia |
| 12254 | && inst.instruction != T_MNEM_stmia, |
| 12255 | _("Thumb-2 instruction only valid in unified syntax")); |
| 12256 | if (inst.instruction == T_MNEM_stmia) |
| 12257 | { |
| 12258 | if (!inst.operands[0].writeback) |
| 12259 | as_warn (_("this instruction will write back the base register")); |
| 12260 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) |
| 12261 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) |
| 12262 | as_warn (_("value stored for r%d is UNKNOWN"), |
| 12263 | inst.operands[0].reg); |
| 12264 | } |
| 12265 | else |
| 12266 | { |
| 12267 | if (!inst.operands[0].writeback |
| 12268 | && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) |
| 12269 | as_warn (_("this instruction will write back the base register")); |
| 12270 | else if (inst.operands[0].writeback |
| 12271 | && (inst.operands[1].imm & (1 << inst.operands[0].reg))) |
| 12272 | as_warn (_("this instruction will not write back the base register")); |
| 12273 | } |
| 12274 | |
| 12275 | inst.instruction = THUMB_OP16 (inst.instruction); |
| 12276 | inst.instruction |= inst.operands[0].reg << 8; |
| 12277 | inst.instruction |= inst.operands[1].imm; |
| 12278 | } |
| 12279 | } |
| 12280 | |
| 12281 | static void |
| 12282 | do_t_ldrex (void) |
| 12283 | { |
| 12284 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind |
| 12285 | || inst.operands[1].postind || inst.operands[1].writeback |
| 12286 | || inst.operands[1].immisreg || inst.operands[1].shifted |
| 12287 | || inst.operands[1].negative, |
| 12288 | BAD_ADDR_MODE); |
| 12289 | |
| 12290 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
| 12291 | |
| 12292 | inst.instruction |= inst.operands[0].reg << 12; |
| 12293 | inst.instruction |= inst.operands[1].reg << 16; |
| 12294 | inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8; |
| 12295 | } |
| 12296 | |
| 12297 | static void |
| 12298 | do_t_ldrexd (void) |
| 12299 | { |
| 12300 | if (!inst.operands[1].present) |
| 12301 | { |
| 12302 | constraint (inst.operands[0].reg == REG_LR, |
| 12303 | _("r14 not allowed as first register " |
| 12304 | "when second register is omitted")); |
| 12305 | inst.operands[1].reg = inst.operands[0].reg + 1; |
| 12306 | } |
| 12307 | constraint (inst.operands[0].reg == inst.operands[1].reg, |
| 12308 | BAD_OVERLAP); |
| 12309 | |
| 12310 | inst.instruction |= inst.operands[0].reg << 12; |
| 12311 | inst.instruction |= inst.operands[1].reg << 8; |
| 12312 | inst.instruction |= inst.operands[2].reg << 16; |
| 12313 | } |
| 12314 | |
| 12315 | static void |
| 12316 | do_t_ldst (void) |
| 12317 | { |
| 12318 | unsigned long opcode; |
| 12319 | int Rn; |
| 12320 | |
| 12321 | if (inst.operands[0].isreg |
| 12322 | && !inst.operands[0].preind |
| 12323 | && inst.operands[0].reg == REG_PC) |
| 12324 | set_pred_insn_type_last (); |
| 12325 | |
| 12326 | opcode = inst.instruction; |
| 12327 | if (unified_syntax) |
| 12328 | { |
| 12329 | if (!inst.operands[1].isreg) |
| 12330 | { |
| 12331 | if (opcode <= 0xffff) |
| 12332 | inst.instruction = THUMB_OP32 (opcode); |
| 12333 | if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE)) |
| 12334 | return; |
| 12335 | } |
| 12336 | if (inst.operands[1].isreg |
| 12337 | && !inst.operands[1].writeback |
| 12338 | && !inst.operands[1].shifted && !inst.operands[1].postind |
| 12339 | && !inst.operands[1].negative && inst.operands[0].reg <= 7 |
| 12340 | && opcode <= 0xffff |
| 12341 | && inst.size_req != 4) |
| 12342 | { |
| 12343 | /* Insn may have a 16-bit form. */ |
| 12344 | Rn = inst.operands[1].reg; |
| 12345 | if (inst.operands[1].immisreg) |
| 12346 | { |
| 12347 | inst.instruction = THUMB_OP16 (opcode); |
| 12348 | /* [Rn, Rik] */ |
| 12349 | if (Rn <= 7 && inst.operands[1].imm <= 7) |
| 12350 | goto op16; |
| 12351 | else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str) |
| 12352 | reject_bad_reg (inst.operands[1].imm); |
| 12353 | } |
| 12354 | else if ((Rn <= 7 && opcode != T_MNEM_ldrsh |
| 12355 | && opcode != T_MNEM_ldrsb) |
| 12356 | || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) |
| 12357 | || (Rn == REG_SP && opcode == T_MNEM_str)) |
| 12358 | { |
| 12359 | /* [Rn, #const] */ |
| 12360 | if (Rn > 7) |
| 12361 | { |
| 12362 | if (Rn == REG_PC) |
| 12363 | { |
| 12364 | if (inst.relocs[0].pc_rel) |
| 12365 | opcode = T_MNEM_ldr_pc2; |
| 12366 | else |
| 12367 | opcode = T_MNEM_ldr_pc; |
| 12368 | } |
| 12369 | else |
| 12370 | { |
| 12371 | if (opcode == T_MNEM_ldr) |
| 12372 | opcode = T_MNEM_ldr_sp; |
| 12373 | else |
| 12374 | opcode = T_MNEM_str_sp; |
| 12375 | } |
| 12376 | inst.instruction = inst.operands[0].reg << 8; |
| 12377 | } |
| 12378 | else |
| 12379 | { |
| 12380 | inst.instruction = inst.operands[0].reg; |
| 12381 | inst.instruction |= inst.operands[1].reg << 3; |
| 12382 | } |
| 12383 | inst.instruction |= THUMB_OP16 (opcode); |
| 12384 | if (inst.size_req == 2) |
| 12385 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET; |
| 12386 | else |
| 12387 | inst.relax = opcode; |
| 12388 | return; |
| 12389 | } |
| 12390 | } |
| 12391 | /* Definitely a 32-bit variant. */ |
| 12392 | |
| 12393 | /* Warning for Erratum 752419. */ |
| 12394 | if (opcode == T_MNEM_ldr |
| 12395 | && inst.operands[0].reg == REG_SP |
| 12396 | && inst.operands[1].writeback == 1 |
| 12397 | && !inst.operands[1].immisreg) |
| 12398 | { |
| 12399 | if (no_cpu_selected () |
| 12400 | || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7) |
| 12401 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a) |
| 12402 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r))) |
| 12403 | as_warn (_("This instruction may be unpredictable " |
| 12404 | "if executed on M-profile cores " |
| 12405 | "with interrupts enabled.")); |
| 12406 | } |
| 12407 | |
| 12408 | /* Do some validations regarding addressing modes. */ |
| 12409 | if (inst.operands[1].immisreg) |
| 12410 | reject_bad_reg (inst.operands[1].imm); |
| 12411 | |
| 12412 | constraint (inst.operands[1].writeback == 1 |
| 12413 | && inst.operands[0].reg == inst.operands[1].reg, |
| 12414 | BAD_OVERLAP); |
| 12415 | |
| 12416 | inst.instruction = THUMB_OP32 (opcode); |
| 12417 | inst.instruction |= inst.operands[0].reg << 12; |
| 12418 | encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); |
| 12419 | check_ldr_r15_aligned (); |
| 12420 | return; |
| 12421 | } |
| 12422 | |
| 12423 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
| 12424 | |
| 12425 | if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) |
| 12426 | { |
| 12427 | /* Only [Rn,Rm] is acceptable. */ |
| 12428 | constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); |
| 12429 | constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg |
| 12430 | || inst.operands[1].postind || inst.operands[1].shifted |
| 12431 | || inst.operands[1].negative, |
| 12432 | _("Thumb does not support this addressing mode")); |
| 12433 | inst.instruction = THUMB_OP16 (inst.instruction); |
| 12434 | goto op16; |
| 12435 | } |
| 12436 | |
| 12437 | inst.instruction = THUMB_OP16 (inst.instruction); |
| 12438 | if (!inst.operands[1].isreg) |
| 12439 | if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE)) |
| 12440 | return; |
| 12441 | |
| 12442 | constraint (!inst.operands[1].preind |
| 12443 | || inst.operands[1].shifted |
| 12444 | || inst.operands[1].writeback, |
| 12445 | _("Thumb does not support this addressing mode")); |
| 12446 | if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) |
| 12447 | { |
| 12448 | constraint (inst.instruction & 0x0600, |
| 12449 | _("byte or halfword not valid for base register")); |
| 12450 | constraint (inst.operands[1].reg == REG_PC |
| 12451 | && !(inst.instruction & THUMB_LOAD_BIT), |
| 12452 | _("r15 based store not allowed")); |
| 12453 | constraint (inst.operands[1].immisreg, |
| 12454 | _("invalid base register for register offset")); |
| 12455 | |
| 12456 | if (inst.operands[1].reg == REG_PC) |
| 12457 | inst.instruction = T_OPCODE_LDR_PC; |
| 12458 | else if (inst.instruction & THUMB_LOAD_BIT) |
| 12459 | inst.instruction = T_OPCODE_LDR_SP; |
| 12460 | else |
| 12461 | inst.instruction = T_OPCODE_STR_SP; |
| 12462 | |
| 12463 | inst.instruction |= inst.operands[0].reg << 8; |
| 12464 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET; |
| 12465 | return; |
| 12466 | } |
| 12467 | |
| 12468 | constraint (inst.operands[1].reg > 7, BAD_HIREG); |
| 12469 | if (!inst.operands[1].immisreg) |
| 12470 | { |
| 12471 | /* Immediate offset. */ |
| 12472 | inst.instruction |= inst.operands[0].reg; |
| 12473 | inst.instruction |= inst.operands[1].reg << 3; |
| 12474 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET; |
| 12475 | return; |
| 12476 | } |
| 12477 | |
| 12478 | /* Register offset. */ |
| 12479 | constraint (inst.operands[1].imm > 7, BAD_HIREG); |
| 12480 | constraint (inst.operands[1].negative, |
| 12481 | _("Thumb does not support this addressing mode")); |
| 12482 | |
| 12483 | op16: |
| 12484 | switch (inst.instruction) |
| 12485 | { |
| 12486 | case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; |
| 12487 | case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; |
| 12488 | case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; |
| 12489 | case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; |
| 12490 | case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; |
| 12491 | case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; |
| 12492 | case 0x5600 /* ldrsb */: |
| 12493 | case 0x5e00 /* ldrsh */: break; |
| 12494 | default: abort (); |
| 12495 | } |
| 12496 | |
| 12497 | inst.instruction |= inst.operands[0].reg; |
| 12498 | inst.instruction |= inst.operands[1].reg << 3; |
| 12499 | inst.instruction |= inst.operands[1].imm << 6; |
| 12500 | } |
| 12501 | |
| 12502 | static void |
| 12503 | do_t_ldstd (void) |
| 12504 | { |
| 12505 | if (!inst.operands[1].present) |
| 12506 | { |
| 12507 | inst.operands[1].reg = inst.operands[0].reg + 1; |
| 12508 | constraint (inst.operands[0].reg == REG_LR, |
| 12509 | _("r14 not allowed here")); |
| 12510 | constraint (inst.operands[0].reg == REG_R12, |
| 12511 | _("r12 not allowed here")); |
| 12512 | } |
| 12513 | |
| 12514 | if (inst.operands[2].writeback |
| 12515 | && (inst.operands[0].reg == inst.operands[2].reg |
| 12516 | || inst.operands[1].reg == inst.operands[2].reg)) |
| 12517 | as_warn (_("base register written back, and overlaps " |
| 12518 | "one of transfer registers")); |
| 12519 | |
| 12520 | inst.instruction |= inst.operands[0].reg << 12; |
| 12521 | inst.instruction |= inst.operands[1].reg << 8; |
| 12522 | encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); |
| 12523 | } |
| 12524 | |
| 12525 | static void |
| 12526 | do_t_ldstt (void) |
| 12527 | { |
| 12528 | inst.instruction |= inst.operands[0].reg << 12; |
| 12529 | encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); |
| 12530 | } |
| 12531 | |
| 12532 | static void |
| 12533 | do_t_mla (void) |
| 12534 | { |
| 12535 | unsigned Rd, Rn, Rm, Ra; |
| 12536 | |
| 12537 | Rd = inst.operands[0].reg; |
| 12538 | Rn = inst.operands[1].reg; |
| 12539 | Rm = inst.operands[2].reg; |
| 12540 | Ra = inst.operands[3].reg; |
| 12541 | |
| 12542 | reject_bad_reg (Rd); |
| 12543 | reject_bad_reg (Rn); |
| 12544 | reject_bad_reg (Rm); |
| 12545 | reject_bad_reg (Ra); |
| 12546 | |
| 12547 | inst.instruction |= Rd << 8; |
| 12548 | inst.instruction |= Rn << 16; |
| 12549 | inst.instruction |= Rm; |
| 12550 | inst.instruction |= Ra << 12; |
| 12551 | } |
| 12552 | |
| 12553 | static void |
| 12554 | do_t_mlal (void) |
| 12555 | { |
| 12556 | unsigned RdLo, RdHi, Rn, Rm; |
| 12557 | |
| 12558 | RdLo = inst.operands[0].reg; |
| 12559 | RdHi = inst.operands[1].reg; |
| 12560 | Rn = inst.operands[2].reg; |
| 12561 | Rm = inst.operands[3].reg; |
| 12562 | |
| 12563 | reject_bad_reg (RdLo); |
| 12564 | reject_bad_reg (RdHi); |
| 12565 | reject_bad_reg (Rn); |
| 12566 | reject_bad_reg (Rm); |
| 12567 | |
| 12568 | inst.instruction |= RdLo << 12; |
| 12569 | inst.instruction |= RdHi << 8; |
| 12570 | inst.instruction |= Rn << 16; |
| 12571 | inst.instruction |= Rm; |
| 12572 | } |
| 12573 | |
| 12574 | static void |
| 12575 | do_t_mov_cmp (void) |
| 12576 | { |
| 12577 | unsigned Rn, Rm; |
| 12578 | |
| 12579 | Rn = inst.operands[0].reg; |
| 12580 | Rm = inst.operands[1].reg; |
| 12581 | |
| 12582 | if (Rn == REG_PC) |
| 12583 | set_pred_insn_type_last (); |
| 12584 | |
| 12585 | if (unified_syntax) |
| 12586 | { |
| 12587 | int r0off = (inst.instruction == T_MNEM_mov |
| 12588 | || inst.instruction == T_MNEM_movs) ? 8 : 16; |
| 12589 | unsigned long opcode; |
| 12590 | bfd_boolean narrow; |
| 12591 | bfd_boolean low_regs; |
| 12592 | |
| 12593 | low_regs = (Rn <= 7 && Rm <= 7); |
| 12594 | opcode = inst.instruction; |
| 12595 | if (in_pred_block ()) |
| 12596 | narrow = opcode != T_MNEM_movs; |
| 12597 | else |
| 12598 | narrow = opcode != T_MNEM_movs || low_regs; |
| 12599 | if (inst.size_req == 4 |
| 12600 | || inst.operands[1].shifted) |
| 12601 | narrow = FALSE; |
| 12602 | |
| 12603 | /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ |
| 12604 | if (opcode == T_MNEM_movs && inst.operands[1].isreg |
| 12605 | && !inst.operands[1].shifted |
| 12606 | && Rn == REG_PC |
| 12607 | && Rm == REG_LR) |
| 12608 | { |
| 12609 | inst.instruction = T2_SUBS_PC_LR; |
| 12610 | return; |
| 12611 | } |
| 12612 | |
| 12613 | if (opcode == T_MNEM_cmp) |
| 12614 | { |
| 12615 | constraint (Rn == REG_PC, BAD_PC); |
| 12616 | if (narrow) |
| 12617 | { |
| 12618 | /* In the Thumb-2 ISA, use of R13 as Rm is deprecated, |
| 12619 | but valid. */ |
| 12620 | warn_deprecated_sp (Rm); |
| 12621 | /* R15 was documented as a valid choice for Rm in ARMv6, |
| 12622 | but as UNPREDICTABLE in ARMv7. ARM's proprietary |
| 12623 | tools reject R15, so we do too. */ |
| 12624 | constraint (Rm == REG_PC, BAD_PC); |
| 12625 | } |
| 12626 | else |
| 12627 | reject_bad_reg (Rm); |
| 12628 | } |
| 12629 | else if (opcode == T_MNEM_mov |
| 12630 | || opcode == T_MNEM_movs) |
| 12631 | { |
| 12632 | if (inst.operands[1].isreg) |
| 12633 | { |
| 12634 | if (opcode == T_MNEM_movs) |
| 12635 | { |
| 12636 | reject_bad_reg (Rn); |
| 12637 | reject_bad_reg (Rm); |
| 12638 | } |
| 12639 | else if (narrow) |
| 12640 | { |
| 12641 | /* This is mov.n. */ |
| 12642 | if ((Rn == REG_SP || Rn == REG_PC) |
| 12643 | && (Rm == REG_SP || Rm == REG_PC)) |
| 12644 | { |
| 12645 | as_tsktsk (_("Use of r%u as a source register is " |
| 12646 | "deprecated when r%u is the destination " |
| 12647 | "register."), Rm, Rn); |
| 12648 | } |
| 12649 | } |
| 12650 | else |
| 12651 | { |
| 12652 | /* This is mov.w. */ |
| 12653 | constraint (Rn == REG_PC, BAD_PC); |
| 12654 | constraint (Rm == REG_PC, BAD_PC); |
| 12655 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) |
| 12656 | constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP); |
| 12657 | } |
| 12658 | } |
| 12659 | else |
| 12660 | reject_bad_reg (Rn); |
| 12661 | } |
| 12662 | |
| 12663 | if (!inst.operands[1].isreg) |
| 12664 | { |
| 12665 | /* Immediate operand. */ |
| 12666 | if (!in_pred_block () && opcode == T_MNEM_mov) |
| 12667 | narrow = 0; |
| 12668 | if (low_regs && narrow) |
| 12669 | { |
| 12670 | inst.instruction = THUMB_OP16 (opcode); |
| 12671 | inst.instruction |= Rn << 8; |
| 12672 | if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC |
| 12673 | || inst.relocs[0].type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) |
| 12674 | { |
| 12675 | if (inst.size_req == 2) |
| 12676 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM; |
| 12677 | else |
| 12678 | inst.relax = opcode; |
| 12679 | } |
| 12680 | } |
| 12681 | else |
| 12682 | { |
| 12683 | constraint ((inst.relocs[0].type |
| 12684 | >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC) |
| 12685 | && (inst.relocs[0].type |
| 12686 | <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) , |
| 12687 | THUMB1_RELOC_ONLY); |
| 12688 | |
| 12689 | inst.instruction = THUMB_OP32 (inst.instruction); |
| 12690 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; |
| 12691 | inst.instruction |= Rn << r0off; |
| 12692 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE; |
| 12693 | } |
| 12694 | } |
| 12695 | else if (inst.operands[1].shifted && inst.operands[1].immisreg |
| 12696 | && (inst.instruction == T_MNEM_mov |
| 12697 | || inst.instruction == T_MNEM_movs)) |
| 12698 | { |
| 12699 | /* Register shifts are encoded as separate shift instructions. */ |
| 12700 | bfd_boolean flags = (inst.instruction == T_MNEM_movs); |
| 12701 | |
| 12702 | if (in_pred_block ()) |
| 12703 | narrow = !flags; |
| 12704 | else |
| 12705 | narrow = flags; |
| 12706 | |
| 12707 | if (inst.size_req == 4) |
| 12708 | narrow = FALSE; |
| 12709 | |
| 12710 | if (!low_regs || inst.operands[1].imm > 7) |
| 12711 | narrow = FALSE; |
| 12712 | |
| 12713 | if (Rn != Rm) |
| 12714 | narrow = FALSE; |
| 12715 | |
| 12716 | switch (inst.operands[1].shift_kind) |
| 12717 | { |
| 12718 | case SHIFT_LSL: |
| 12719 | opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl); |
| 12720 | break; |
| 12721 | case SHIFT_ASR: |
| 12722 | opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr); |
| 12723 | break; |
| 12724 | case SHIFT_LSR: |
| 12725 | opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr); |
| 12726 | break; |
| 12727 | case SHIFT_ROR: |
| 12728 | opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror); |
| 12729 | break; |
| 12730 | default: |
| 12731 | abort (); |
| 12732 | } |
| 12733 | |
| 12734 | inst.instruction = opcode; |
| 12735 | if (narrow) |
| 12736 | { |
| 12737 | inst.instruction |= Rn; |
| 12738 | inst.instruction |= inst.operands[1].imm << 3; |
| 12739 | } |
| 12740 | else |
| 12741 | { |
| 12742 | if (flags) |
| 12743 | inst.instruction |= CONDS_BIT; |
| 12744 | |
| 12745 | inst.instruction |= Rn << 8; |
| 12746 | inst.instruction |= Rm << 16; |
| 12747 | inst.instruction |= inst.operands[1].imm; |
| 12748 | } |
| 12749 | } |
| 12750 | else if (!narrow) |
| 12751 | { |
| 12752 | /* Some mov with immediate shift have narrow variants. |
| 12753 | Register shifts are handled above. */ |
| 12754 | if (low_regs && inst.operands[1].shifted |
| 12755 | && (inst.instruction == T_MNEM_mov |
| 12756 | || inst.instruction == T_MNEM_movs)) |
| 12757 | { |
| 12758 | if (in_pred_block ()) |
| 12759 | narrow = (inst.instruction == T_MNEM_mov); |
| 12760 | else |
| 12761 | narrow = (inst.instruction == T_MNEM_movs); |
| 12762 | } |
| 12763 | |
| 12764 | if (narrow) |
| 12765 | { |
| 12766 | switch (inst.operands[1].shift_kind) |
| 12767 | { |
| 12768 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; |
| 12769 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; |
| 12770 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; |
| 12771 | default: narrow = FALSE; break; |
| 12772 | } |
| 12773 | } |
| 12774 | |
| 12775 | if (narrow) |
| 12776 | { |
| 12777 | inst.instruction |= Rn; |
| 12778 | inst.instruction |= Rm << 3; |
| 12779 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT; |
| 12780 | } |
| 12781 | else |
| 12782 | { |
| 12783 | inst.instruction = THUMB_OP32 (inst.instruction); |
| 12784 | inst.instruction |= Rn << r0off; |
| 12785 | encode_thumb32_shifted_operand (1); |
| 12786 | } |
| 12787 | } |
| 12788 | else |
| 12789 | switch (inst.instruction) |
| 12790 | { |
| 12791 | case T_MNEM_mov: |
| 12792 | /* In v4t or v5t a move of two lowregs produces unpredictable |
| 12793 | results. Don't allow this. */ |
| 12794 | if (low_regs) |
| 12795 | { |
| 12796 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6), |
| 12797 | "MOV Rd, Rs with two low registers is not " |
| 12798 | "permitted on this architecture"); |
| 12799 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
| 12800 | arm_ext_v6); |
| 12801 | } |
| 12802 | |
| 12803 | inst.instruction = T_OPCODE_MOV_HR; |
| 12804 | inst.instruction |= (Rn & 0x8) << 4; |
| 12805 | inst.instruction |= (Rn & 0x7); |
| 12806 | inst.instruction |= Rm << 3; |
| 12807 | break; |
| 12808 | |
| 12809 | case T_MNEM_movs: |
| 12810 | /* We know we have low registers at this point. |
| 12811 | Generate LSLS Rd, Rs, #0. */ |
| 12812 | inst.instruction = T_OPCODE_LSL_I; |
| 12813 | inst.instruction |= Rn; |
| 12814 | inst.instruction |= Rm << 3; |
| 12815 | break; |
| 12816 | |
| 12817 | case T_MNEM_cmp: |
| 12818 | if (low_regs) |
| 12819 | { |
| 12820 | inst.instruction = T_OPCODE_CMP_LR; |
| 12821 | inst.instruction |= Rn; |
| 12822 | inst.instruction |= Rm << 3; |
| 12823 | } |
| 12824 | else |
| 12825 | { |
| 12826 | inst.instruction = T_OPCODE_CMP_HR; |
| 12827 | inst.instruction |= (Rn & 0x8) << 4; |
| 12828 | inst.instruction |= (Rn & 0x7); |
| 12829 | inst.instruction |= Rm << 3; |
| 12830 | } |
| 12831 | break; |
| 12832 | } |
| 12833 | return; |
| 12834 | } |
| 12835 | |
| 12836 | inst.instruction = THUMB_OP16 (inst.instruction); |
| 12837 | |
| 12838 | /* PR 10443: Do not silently ignore shifted operands. */ |
| 12839 | constraint (inst.operands[1].shifted, |
| 12840 | _("shifts in CMP/MOV instructions are only supported in unified syntax")); |
| 12841 | |
| 12842 | if (inst.operands[1].isreg) |
| 12843 | { |
| 12844 | if (Rn < 8 && Rm < 8) |
| 12845 | { |
| 12846 | /* A move of two lowregs is encoded as ADD Rd, Rs, #0 |
| 12847 | since a MOV instruction produces unpredictable results. */ |
| 12848 | if (inst.instruction == T_OPCODE_MOV_I8) |
| 12849 | inst.instruction = T_OPCODE_ADD_I3; |
| 12850 | else |
| 12851 | inst.instruction = T_OPCODE_CMP_LR; |
| 12852 | |
| 12853 | inst.instruction |= Rn; |
| 12854 | inst.instruction |= Rm << 3; |
| 12855 | } |
| 12856 | else |
| 12857 | { |
| 12858 | if (inst.instruction == T_OPCODE_MOV_I8) |
| 12859 | inst.instruction = T_OPCODE_MOV_HR; |
| 12860 | else |
| 12861 | inst.instruction = T_OPCODE_CMP_HR; |
| 12862 | do_t_cpy (); |
| 12863 | } |
| 12864 | } |
| 12865 | else |
| 12866 | { |
| 12867 | constraint (Rn > 7, |
| 12868 | _("only lo regs allowed with immediate")); |
| 12869 | inst.instruction |= Rn << 8; |
| 12870 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM; |
| 12871 | } |
| 12872 | } |
| 12873 | |
| 12874 | static void |
| 12875 | do_t_mov16 (void) |
| 12876 | { |
| 12877 | unsigned Rd; |
| 12878 | bfd_vma imm; |
| 12879 | bfd_boolean top; |
| 12880 | |
| 12881 | top = (inst.instruction & 0x00800000) != 0; |
| 12882 | if (inst.relocs[0].type == BFD_RELOC_ARM_MOVW) |
| 12883 | { |
| 12884 | constraint (top, _(":lower16: not allowed in this instruction")); |
| 12885 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVW; |
| 12886 | } |
| 12887 | else if (inst.relocs[0].type == BFD_RELOC_ARM_MOVT) |
| 12888 | { |
| 12889 | constraint (!top, _(":upper16: not allowed in this instruction")); |
| 12890 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVT; |
| 12891 | } |
| 12892 | |
| 12893 | Rd = inst.operands[0].reg; |
| 12894 | reject_bad_reg (Rd); |
| 12895 | |
| 12896 | inst.instruction |= Rd << 8; |
| 12897 | if (inst.relocs[0].type == BFD_RELOC_UNUSED) |
| 12898 | { |
| 12899 | imm = inst.relocs[0].exp.X_add_number; |
| 12900 | inst.instruction |= (imm & 0xf000) << 4; |
| 12901 | inst.instruction |= (imm & 0x0800) << 15; |
| 12902 | inst.instruction |= (imm & 0x0700) << 4; |
| 12903 | inst.instruction |= (imm & 0x00ff); |
| 12904 | } |
| 12905 | } |
| 12906 | |
| 12907 | static void |
| 12908 | do_t_mvn_tst (void) |
| 12909 | { |
| 12910 | unsigned Rn, Rm; |
| 12911 | |
| 12912 | Rn = inst.operands[0].reg; |
| 12913 | Rm = inst.operands[1].reg; |
| 12914 | |
| 12915 | if (inst.instruction == T_MNEM_cmp |
| 12916 | || inst.instruction == T_MNEM_cmn) |
| 12917 | constraint (Rn == REG_PC, BAD_PC); |
| 12918 | else |
| 12919 | reject_bad_reg (Rn); |
| 12920 | reject_bad_reg (Rm); |
| 12921 | |
| 12922 | if (unified_syntax) |
| 12923 | { |
| 12924 | int r0off = (inst.instruction == T_MNEM_mvn |
| 12925 | || inst.instruction == T_MNEM_mvns) ? 8 : 16; |
| 12926 | bfd_boolean narrow; |
| 12927 | |
| 12928 | if (inst.size_req == 4 |
| 12929 | || inst.instruction > 0xffff |
| 12930 | || inst.operands[1].shifted |
| 12931 | || Rn > 7 || Rm > 7) |
| 12932 | narrow = FALSE; |
| 12933 | else if (inst.instruction == T_MNEM_cmn |
| 12934 | || inst.instruction == T_MNEM_tst) |
| 12935 | narrow = TRUE; |
| 12936 | else if (THUMB_SETS_FLAGS (inst.instruction)) |
| 12937 | narrow = !in_pred_block (); |
| 12938 | else |
| 12939 | narrow = in_pred_block (); |
| 12940 | |
| 12941 | if (!inst.operands[1].isreg) |
| 12942 | { |
| 12943 | /* For an immediate, we always generate a 32-bit opcode; |
| 12944 | section relaxation will shrink it later if possible. */ |
| 12945 | if (inst.instruction < 0xffff) |
| 12946 | inst.instruction = THUMB_OP32 (inst.instruction); |
| 12947 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; |
| 12948 | inst.instruction |= Rn << r0off; |
| 12949 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE; |
| 12950 | } |
| 12951 | else |
| 12952 | { |
| 12953 | /* See if we can do this with a 16-bit instruction. */ |
| 12954 | if (narrow) |
| 12955 | { |
| 12956 | inst.instruction = THUMB_OP16 (inst.instruction); |
| 12957 | inst.instruction |= Rn; |
| 12958 | inst.instruction |= Rm << 3; |
| 12959 | } |
| 12960 | else |
| 12961 | { |
| 12962 | constraint (inst.operands[1].shifted |
| 12963 | && inst.operands[1].immisreg, |
| 12964 | _("shift must be constant")); |
| 12965 | if (inst.instruction < 0xffff) |
| 12966 | inst.instruction = THUMB_OP32 (inst.instruction); |
| 12967 | inst.instruction |= Rn << r0off; |
| 12968 | encode_thumb32_shifted_operand (1); |
| 12969 | } |
| 12970 | } |
| 12971 | } |
| 12972 | else |
| 12973 | { |
| 12974 | constraint (inst.instruction > 0xffff |
| 12975 | || inst.instruction == T_MNEM_mvns, BAD_THUMB32); |
| 12976 | constraint (!inst.operands[1].isreg || inst.operands[1].shifted, |
| 12977 | _("unshifted register required")); |
| 12978 | constraint (Rn > 7 || Rm > 7, |
| 12979 | BAD_HIREG); |
| 12980 | |
| 12981 | inst.instruction = THUMB_OP16 (inst.instruction); |
| 12982 | inst.instruction |= Rn; |
| 12983 | inst.instruction |= Rm << 3; |
| 12984 | } |
| 12985 | } |
| 12986 | |
| 12987 | static void |
| 12988 | do_t_mrs (void) |
| 12989 | { |
| 12990 | unsigned Rd; |
| 12991 | |
| 12992 | if (do_vfp_nsyn_mrs () == SUCCESS) |
| 12993 | return; |
| 12994 | |
| 12995 | Rd = inst.operands[0].reg; |
| 12996 | reject_bad_reg (Rd); |
| 12997 | inst.instruction |= Rd << 8; |
| 12998 | |
| 12999 | if (inst.operands[1].isreg) |
| 13000 | { |
| 13001 | unsigned br = inst.operands[1].reg; |
| 13002 | if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000)) |
| 13003 | as_bad (_("bad register for mrs")); |
| 13004 | |
| 13005 | inst.instruction |= br & (0xf << 16); |
| 13006 | inst.instruction |= (br & 0x300) >> 4; |
| 13007 | inst.instruction |= (br & SPSR_BIT) >> 2; |
| 13008 | } |
| 13009 | else |
| 13010 | { |
| 13011 | int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
| 13012 | |
| 13013 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
| 13014 | { |
| 13015 | /* PR gas/12698: The constraint is only applied for m_profile. |
| 13016 | If the user has specified -march=all, we want to ignore it as |
| 13017 | we are building for any CPU type, including non-m variants. */ |
| 13018 | bfd_boolean m_profile = |
| 13019 | !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any); |
| 13020 | constraint ((flags != 0) && m_profile, _("selected processor does " |
| 13021 | "not support requested special purpose register")); |
| 13022 | } |
| 13023 | else |
| 13024 | /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile |
| 13025 | devices). */ |
| 13026 | constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), |
| 13027 | _("'APSR', 'CPSR' or 'SPSR' expected")); |
| 13028 | |
| 13029 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
| 13030 | inst.instruction |= inst.operands[1].imm & 0xff; |
| 13031 | inst.instruction |= 0xf0000; |
| 13032 | } |
| 13033 | } |
| 13034 | |
| 13035 | static void |
| 13036 | do_t_msr (void) |
| 13037 | { |
| 13038 | int flags; |
| 13039 | unsigned Rn; |
| 13040 | |
| 13041 | if (do_vfp_nsyn_msr () == SUCCESS) |
| 13042 | return; |
| 13043 | |
| 13044 | constraint (!inst.operands[1].isreg, |
| 13045 | _("Thumb encoding does not support an immediate here")); |
| 13046 | |
| 13047 | if (inst.operands[0].isreg) |
| 13048 | flags = (int)(inst.operands[0].reg); |
| 13049 | else |
| 13050 | flags = inst.operands[0].imm; |
| 13051 | |
| 13052 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
| 13053 | { |
| 13054 | int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
| 13055 | |
| 13056 | /* PR gas/12698: The constraint is only applied for m_profile. |
| 13057 | If the user has specified -march=all, we want to ignore it as |
| 13058 | we are building for any CPU type, including non-m variants. */ |
| 13059 | bfd_boolean m_profile = |
| 13060 | !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any); |
| 13061 | constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) |
| 13062 | && (bits & ~(PSR_s | PSR_f)) != 0) |
| 13063 | || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) |
| 13064 | && bits != PSR_f)) && m_profile, |
| 13065 | _("selected processor does not support requested special " |
| 13066 | "purpose register")); |
| 13067 | } |
| 13068 | else |
| 13069 | constraint ((flags & 0xff) != 0, _("selected processor does not support " |
| 13070 | "requested special purpose register")); |
| 13071 | |
| 13072 | Rn = inst.operands[1].reg; |
| 13073 | reject_bad_reg (Rn); |
| 13074 | |
| 13075 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
| 13076 | inst.instruction |= (flags & 0xf0000) >> 8; |
| 13077 | inst.instruction |= (flags & 0x300) >> 4; |
| 13078 | inst.instruction |= (flags & 0xff); |
| 13079 | inst.instruction |= Rn << 16; |
| 13080 | } |
| 13081 | |
| 13082 | static void |
| 13083 | do_t_mul (void) |
| 13084 | { |
| 13085 | bfd_boolean narrow; |
| 13086 | unsigned Rd, Rn, Rm; |
| 13087 | |
| 13088 | if (!inst.operands[2].present) |
| 13089 | inst.operands[2].reg = inst.operands[0].reg; |
| 13090 | |
| 13091 | Rd = inst.operands[0].reg; |
| 13092 | Rn = inst.operands[1].reg; |
| 13093 | Rm = inst.operands[2].reg; |
| 13094 | |
| 13095 | if (unified_syntax) |
| 13096 | { |
| 13097 | if (inst.size_req == 4 |
| 13098 | || (Rd != Rn |
| 13099 | && Rd != Rm) |
| 13100 | || Rn > 7 |
| 13101 | || Rm > 7) |
| 13102 | narrow = FALSE; |
| 13103 | else if (inst.instruction == T_MNEM_muls) |
| 13104 | narrow = !in_pred_block (); |
| 13105 | else |
| 13106 | narrow = in_pred_block (); |
| 13107 | } |
| 13108 | else |
| 13109 | { |
| 13110 | constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32); |
| 13111 | constraint (Rn > 7 || Rm > 7, |
| 13112 | BAD_HIREG); |
| 13113 | narrow = TRUE; |
| 13114 | } |
| 13115 | |
| 13116 | if (narrow) |
| 13117 | { |
| 13118 | /* 16-bit MULS/Conditional MUL. */ |
| 13119 | inst.instruction = THUMB_OP16 (inst.instruction); |
| 13120 | inst.instruction |= Rd; |
| 13121 | |
| 13122 | if (Rd == Rn) |
| 13123 | inst.instruction |= Rm << 3; |
| 13124 | else if (Rd == Rm) |
| 13125 | inst.instruction |= Rn << 3; |
| 13126 | else |
| 13127 | constraint (1, _("dest must overlap one source register")); |
| 13128 | } |
| 13129 | else |
| 13130 | { |
| 13131 | constraint (inst.instruction != T_MNEM_mul, |
| 13132 | _("Thumb-2 MUL must not set flags")); |
| 13133 | /* 32-bit MUL. */ |
| 13134 | inst.instruction = THUMB_OP32 (inst.instruction); |
| 13135 | inst.instruction |= Rd << 8; |
| 13136 | inst.instruction |= Rn << 16; |
| 13137 | inst.instruction |= Rm << 0; |
| 13138 | |
| 13139 | reject_bad_reg (Rd); |
| 13140 | reject_bad_reg (Rn); |
| 13141 | reject_bad_reg (Rm); |
| 13142 | } |
| 13143 | } |
| 13144 | |
| 13145 | static void |
| 13146 | do_t_mull (void) |
| 13147 | { |
| 13148 | unsigned RdLo, RdHi, Rn, Rm; |
| 13149 | |
| 13150 | RdLo = inst.operands[0].reg; |
| 13151 | RdHi = inst.operands[1].reg; |
| 13152 | Rn = inst.operands[2].reg; |
| 13153 | Rm = inst.operands[3].reg; |
| 13154 | |
| 13155 | reject_bad_reg (RdLo); |
| 13156 | reject_bad_reg (RdHi); |
| 13157 | reject_bad_reg (Rn); |
| 13158 | reject_bad_reg (Rm); |
| 13159 | |
| 13160 | inst.instruction |= RdLo << 12; |
| 13161 | inst.instruction |= RdHi << 8; |
| 13162 | inst.instruction |= Rn << 16; |
| 13163 | inst.instruction |= Rm; |
| 13164 | |
| 13165 | if (RdLo == RdHi) |
| 13166 | as_tsktsk (_("rdhi and rdlo must be different")); |
| 13167 | } |
| 13168 | |
| 13169 | static void |
| 13170 | do_t_nop (void) |
| 13171 | { |
| 13172 | set_pred_insn_type (NEUTRAL_IT_INSN); |
| 13173 | |
| 13174 | if (unified_syntax) |
| 13175 | { |
| 13176 | if (inst.size_req == 4 || inst.operands[0].imm > 15) |
| 13177 | { |
| 13178 | inst.instruction = THUMB_OP32 (inst.instruction); |
| 13179 | inst.instruction |= inst.operands[0].imm; |
| 13180 | } |
| 13181 | else |
| 13182 | { |
| 13183 | /* PR9722: Check for Thumb2 availability before |
| 13184 | generating a thumb2 nop instruction. */ |
| 13185 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) |
| 13186 | { |
| 13187 | inst.instruction = THUMB_OP16 (inst.instruction); |
| 13188 | inst.instruction |= inst.operands[0].imm << 4; |
| 13189 | } |
| 13190 | else |
| 13191 | inst.instruction = 0x46c0; |
| 13192 | } |
| 13193 | } |
| 13194 | else |
| 13195 | { |
| 13196 | constraint (inst.operands[0].present, |
| 13197 | _("Thumb does not support NOP with hints")); |
| 13198 | inst.instruction = 0x46c0; |
| 13199 | } |
| 13200 | } |
| 13201 | |
| 13202 | static void |
| 13203 | do_t_neg (void) |
| 13204 | { |
| 13205 | if (unified_syntax) |
| 13206 | { |
| 13207 | bfd_boolean narrow; |
| 13208 | |
| 13209 | if (THUMB_SETS_FLAGS (inst.instruction)) |
| 13210 | narrow = !in_pred_block (); |
| 13211 | else |
| 13212 | narrow = in_pred_block (); |
| 13213 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
| 13214 | narrow = FALSE; |
| 13215 | if (inst.size_req == 4) |
| 13216 | narrow = FALSE; |
| 13217 | |
| 13218 | if (!narrow) |
| 13219 | { |
| 13220 | inst.instruction = THUMB_OP32 (inst.instruction); |
| 13221 | inst.instruction |= inst.operands[0].reg << 8; |
| 13222 | inst.instruction |= inst.operands[1].reg << 16; |
| 13223 | } |
| 13224 | else |
| 13225 | { |
| 13226 | inst.instruction = THUMB_OP16 (inst.instruction); |
| 13227 | inst.instruction |= inst.operands[0].reg; |
| 13228 | inst.instruction |= inst.operands[1].reg << 3; |
| 13229 | } |
| 13230 | } |
| 13231 | else |
| 13232 | { |
| 13233 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, |
| 13234 | BAD_HIREG); |
| 13235 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); |
| 13236 | |
| 13237 | inst.instruction = THUMB_OP16 (inst.instruction); |
| 13238 | inst.instruction |= inst.operands[0].reg; |
| 13239 | inst.instruction |= inst.operands[1].reg << 3; |
| 13240 | } |
| 13241 | } |
| 13242 | |
| 13243 | static void |
| 13244 | do_t_orn (void) |
| 13245 | { |
| 13246 | unsigned Rd, Rn; |
| 13247 | |
| 13248 | Rd = inst.operands[0].reg; |
| 13249 | Rn = inst.operands[1].present ? inst.operands[1].reg : Rd; |
| 13250 | |
| 13251 | reject_bad_reg (Rd); |
| 13252 | /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */ |
| 13253 | reject_bad_reg (Rn); |
| 13254 | |
| 13255 | inst.instruction |= Rd << 8; |
| 13256 | inst.instruction |= Rn << 16; |
| 13257 | |
| 13258 | if (!inst.operands[2].isreg) |
| 13259 | { |
| 13260 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; |
| 13261 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE; |
| 13262 | } |
| 13263 | else |
| 13264 | { |
| 13265 | unsigned Rm; |
| 13266 | |
| 13267 | Rm = inst.operands[2].reg; |
| 13268 | reject_bad_reg (Rm); |
| 13269 | |
| 13270 | constraint (inst.operands[2].shifted |
| 13271 | && inst.operands[2].immisreg, |
| 13272 | _("shift must be constant")); |
| 13273 | encode_thumb32_shifted_operand (2); |
| 13274 | } |
| 13275 | } |
| 13276 | |
| 13277 | static void |
| 13278 | do_t_pkhbt (void) |
| 13279 | { |
| 13280 | unsigned Rd, Rn, Rm; |
| 13281 | |
| 13282 | Rd = inst.operands[0].reg; |
| 13283 | Rn = inst.operands[1].reg; |
| 13284 | Rm = inst.operands[2].reg; |
| 13285 | |
| 13286 | reject_bad_reg (Rd); |
| 13287 | reject_bad_reg (Rn); |
| 13288 | reject_bad_reg (Rm); |
| 13289 | |
| 13290 | inst.instruction |= Rd << 8; |
| 13291 | inst.instruction |= Rn << 16; |
| 13292 | inst.instruction |= Rm; |
| 13293 | if (inst.operands[3].present) |
| 13294 | { |
| 13295 | unsigned int val = inst.relocs[0].exp.X_add_number; |
| 13296 | constraint (inst.relocs[0].exp.X_op != O_constant, |
| 13297 | _("expression too complex")); |
| 13298 | inst.instruction |= (val & 0x1c) << 10; |
| 13299 | inst.instruction |= (val & 0x03) << 6; |
| 13300 | } |
| 13301 | } |
| 13302 | |
| 13303 | static void |
| 13304 | do_t_pkhtb (void) |
| 13305 | { |
| 13306 | if (!inst.operands[3].present) |
| 13307 | { |
| 13308 | unsigned Rtmp; |
| 13309 | |
| 13310 | inst.instruction &= ~0x00000020; |
| 13311 | |
| 13312 | /* PR 10168. Swap the Rm and Rn registers. */ |
| 13313 | Rtmp = inst.operands[1].reg; |
| 13314 | inst.operands[1].reg = inst.operands[2].reg; |
| 13315 | inst.operands[2].reg = Rtmp; |
| 13316 | } |
| 13317 | do_t_pkhbt (); |
| 13318 | } |
| 13319 | |
| 13320 | static void |
| 13321 | do_t_pld (void) |
| 13322 | { |
| 13323 | if (inst.operands[0].immisreg) |
| 13324 | reject_bad_reg (inst.operands[0].imm); |
| 13325 | |
| 13326 | encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); |
| 13327 | } |
| 13328 | |
| 13329 | static void |
| 13330 | do_t_push_pop (void) |
| 13331 | { |
| 13332 | unsigned mask; |
| 13333 | |
| 13334 | constraint (inst.operands[0].writeback, |
| 13335 | _("push/pop do not support {reglist}^")); |
| 13336 | constraint (inst.relocs[0].type != BFD_RELOC_UNUSED, |
| 13337 | _("expression too complex")); |
| 13338 | |
| 13339 | mask = inst.operands[0].imm; |
| 13340 | if (inst.size_req != 4 && (mask & ~0xff) == 0) |
| 13341 | inst.instruction = THUMB_OP16 (inst.instruction) | mask; |
| 13342 | else if (inst.size_req != 4 |
| 13343 | && (mask & ~0xff) == (1U << (inst.instruction == T_MNEM_push |
| 13344 | ? REG_LR : REG_PC))) |
| 13345 | { |
| 13346 | inst.instruction = THUMB_OP16 (inst.instruction); |
| 13347 | inst.instruction |= THUMB_PP_PC_LR; |
| 13348 | inst.instruction |= mask & 0xff; |
| 13349 | } |
| 13350 | else if (unified_syntax) |
| 13351 | { |
| 13352 | inst.instruction = THUMB_OP32 (inst.instruction); |
| 13353 | encode_thumb2_multi (TRUE /* do_io */, 13, mask, TRUE); |
| 13354 | } |
| 13355 | else |
| 13356 | { |
| 13357 | inst.error = _("invalid register list to push/pop instruction"); |
| 13358 | return; |
| 13359 | } |
| 13360 | } |
| 13361 | |
| 13362 | static void |
| 13363 | do_t_clrm (void) |
| 13364 | { |
| 13365 | if (unified_syntax) |
| 13366 | encode_thumb2_multi (FALSE /* do_io */, -1, inst.operands[0].imm, FALSE); |
| 13367 | else |
| 13368 | { |
| 13369 | inst.error = _("invalid register list to push/pop instruction"); |
| 13370 | return; |
| 13371 | } |
| 13372 | } |
| 13373 | |
| 13374 | static void |
| 13375 | do_t_vscclrm (void) |
| 13376 | { |
| 13377 | if (inst.operands[0].issingle) |
| 13378 | { |
| 13379 | inst.instruction |= (inst.operands[0].reg & 0x1) << 22; |
| 13380 | inst.instruction |= (inst.operands[0].reg & 0x1e) << 11; |
| 13381 | inst.instruction |= inst.operands[0].imm; |
| 13382 | } |
| 13383 | else |
| 13384 | { |
| 13385 | inst.instruction |= (inst.operands[0].reg & 0x10) << 18; |
| 13386 | inst.instruction |= (inst.operands[0].reg & 0xf) << 12; |
| 13387 | inst.instruction |= 1 << 8; |
| 13388 | inst.instruction |= inst.operands[0].imm << 1; |
| 13389 | } |
| 13390 | } |
| 13391 | |
| 13392 | static void |
| 13393 | do_t_rbit (void) |
| 13394 | { |
| 13395 | unsigned Rd, Rm; |
| 13396 | |
| 13397 | Rd = inst.operands[0].reg; |
| 13398 | Rm = inst.operands[1].reg; |
| 13399 | |
| 13400 | reject_bad_reg (Rd); |
| 13401 | reject_bad_reg (Rm); |
| 13402 | |
| 13403 | inst.instruction |= Rd << 8; |
| 13404 | inst.instruction |= Rm << 16; |
| 13405 | inst.instruction |= Rm; |
| 13406 | } |
| 13407 | |
| 13408 | static void |
| 13409 | do_t_rev (void) |
| 13410 | { |
| 13411 | unsigned Rd, Rm; |
| 13412 | |
| 13413 | Rd = inst.operands[0].reg; |
| 13414 | Rm = inst.operands[1].reg; |
| 13415 | |
| 13416 | reject_bad_reg (Rd); |
| 13417 | reject_bad_reg (Rm); |
| 13418 | |
| 13419 | if (Rd <= 7 && Rm <= 7 |
| 13420 | && inst.size_req != 4) |
| 13421 | { |
| 13422 | inst.instruction = THUMB_OP16 (inst.instruction); |
| 13423 | inst.instruction |= Rd; |
| 13424 | inst.instruction |= Rm << 3; |
| 13425 | } |
| 13426 | else if (unified_syntax) |
| 13427 | { |
| 13428 | inst.instruction = THUMB_OP32 (inst.instruction); |
| 13429 | inst.instruction |= Rd << 8; |
| 13430 | inst.instruction |= Rm << 16; |
| 13431 | inst.instruction |= Rm; |
| 13432 | } |
| 13433 | else |
| 13434 | inst.error = BAD_HIREG; |
| 13435 | } |
| 13436 | |
| 13437 | static void |
| 13438 | do_t_rrx (void) |
| 13439 | { |
| 13440 | unsigned Rd, Rm; |
| 13441 | |
| 13442 | Rd = inst.operands[0].reg; |
| 13443 | Rm = inst.operands[1].reg; |
| 13444 | |
| 13445 | reject_bad_reg (Rd); |
| 13446 | reject_bad_reg (Rm); |
| 13447 | |
| 13448 | inst.instruction |= Rd << 8; |
| 13449 | inst.instruction |= Rm; |
| 13450 | } |
| 13451 | |
| 13452 | static void |
| 13453 | do_t_rsb (void) |
| 13454 | { |
| 13455 | unsigned Rd, Rs; |
| 13456 | |
| 13457 | Rd = inst.operands[0].reg; |
| 13458 | Rs = (inst.operands[1].present |
| 13459 | ? inst.operands[1].reg /* Rd, Rs, foo */ |
| 13460 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ |
| 13461 | |
| 13462 | reject_bad_reg (Rd); |
| 13463 | reject_bad_reg (Rs); |
| 13464 | if (inst.operands[2].isreg) |
| 13465 | reject_bad_reg (inst.operands[2].reg); |
| 13466 | |
| 13467 | inst.instruction |= Rd << 8; |
| 13468 | inst.instruction |= Rs << 16; |
| 13469 | if (!inst.operands[2].isreg) |
| 13470 | { |
| 13471 | bfd_boolean narrow; |
| 13472 | |
| 13473 | if ((inst.instruction & 0x00100000) != 0) |
| 13474 | narrow = !in_pred_block (); |
| 13475 | else |
| 13476 | narrow = in_pred_block (); |
| 13477 | |
| 13478 | if (Rd > 7 || Rs > 7) |
| 13479 | narrow = FALSE; |
| 13480 | |
| 13481 | if (inst.size_req == 4 || !unified_syntax) |
| 13482 | narrow = FALSE; |
| 13483 | |
| 13484 | if (inst.relocs[0].exp.X_op != O_constant |
| 13485 | || inst.relocs[0].exp.X_add_number != 0) |
| 13486 | narrow = FALSE; |
| 13487 | |
| 13488 | /* Turn rsb #0 into 16-bit neg. We should probably do this via |
| 13489 | relaxation, but it doesn't seem worth the hassle. */ |
| 13490 | if (narrow) |
| 13491 | { |
| 13492 | inst.relocs[0].type = BFD_RELOC_UNUSED; |
| 13493 | inst.instruction = THUMB_OP16 (T_MNEM_negs); |
| 13494 | inst.instruction |= Rs << 3; |
| 13495 | inst.instruction |= Rd; |
| 13496 | } |
| 13497 | else |
| 13498 | { |
| 13499 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; |
| 13500 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE; |
| 13501 | } |
| 13502 | } |
| 13503 | else |
| 13504 | encode_thumb32_shifted_operand (2); |
| 13505 | } |
| 13506 | |
| 13507 | static void |
| 13508 | do_t_setend (void) |
| 13509 | { |
| 13510 | if (warn_on_deprecated |
| 13511 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) |
| 13512 | as_tsktsk (_("setend use is deprecated for ARMv8")); |
| 13513 | |
| 13514 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
| 13515 | if (inst.operands[0].imm) |
| 13516 | inst.instruction |= 0x8; |
| 13517 | } |
| 13518 | |
| 13519 | static void |
| 13520 | do_t_shift (void) |
| 13521 | { |
| 13522 | if (!inst.operands[1].present) |
| 13523 | inst.operands[1].reg = inst.operands[0].reg; |
| 13524 | |
| 13525 | if (unified_syntax) |
| 13526 | { |
| 13527 | bfd_boolean narrow; |
| 13528 | int shift_kind; |
| 13529 | |
| 13530 | switch (inst.instruction) |
| 13531 | { |
| 13532 | case T_MNEM_asr: |
| 13533 | case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; |
| 13534 | case T_MNEM_lsl: |
| 13535 | case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; |
| 13536 | case T_MNEM_lsr: |
| 13537 | case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; |
| 13538 | case T_MNEM_ror: |
| 13539 | case T_MNEM_rors: shift_kind = SHIFT_ROR; break; |
| 13540 | default: abort (); |
| 13541 | } |
| 13542 | |
| 13543 | if (THUMB_SETS_FLAGS (inst.instruction)) |
| 13544 | narrow = !in_pred_block (); |
| 13545 | else |
| 13546 | narrow = in_pred_block (); |
| 13547 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
| 13548 | narrow = FALSE; |
| 13549 | if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) |
| 13550 | narrow = FALSE; |
| 13551 | if (inst.operands[2].isreg |
| 13552 | && (inst.operands[1].reg != inst.operands[0].reg |
| 13553 | || inst.operands[2].reg > 7)) |
| 13554 | narrow = FALSE; |
| 13555 | if (inst.size_req == 4) |
| 13556 | narrow = FALSE; |
| 13557 | |
| 13558 | reject_bad_reg (inst.operands[0].reg); |
| 13559 | reject_bad_reg (inst.operands[1].reg); |
| 13560 | |
| 13561 | if (!narrow) |
| 13562 | { |
| 13563 | if (inst.operands[2].isreg) |
| 13564 | { |
| 13565 | reject_bad_reg (inst.operands[2].reg); |
| 13566 | inst.instruction = THUMB_OP32 (inst.instruction); |
| 13567 | inst.instruction |= inst.operands[0].reg << 8; |
| 13568 | inst.instruction |= inst.operands[1].reg << 16; |
| 13569 | inst.instruction |= inst.operands[2].reg; |
| 13570 | |
| 13571 | /* PR 12854: Error on extraneous shifts. */ |
| 13572 | constraint (inst.operands[2].shifted, |
| 13573 | _("extraneous shift as part of operand to shift insn")); |
| 13574 | } |
| 13575 | else |
| 13576 | { |
| 13577 | inst.operands[1].shifted = 1; |
| 13578 | inst.operands[1].shift_kind = shift_kind; |
| 13579 | inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) |
| 13580 | ? T_MNEM_movs : T_MNEM_mov); |
| 13581 | inst.instruction |= inst.operands[0].reg << 8; |
| 13582 | encode_thumb32_shifted_operand (1); |
| 13583 | /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ |
| 13584 | inst.relocs[0].type = BFD_RELOC_UNUSED; |
| 13585 | } |
| 13586 | } |
| 13587 | else |
| 13588 | { |
| 13589 | if (inst.operands[2].isreg) |
| 13590 | { |
| 13591 | switch (shift_kind) |
| 13592 | { |
| 13593 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; |
| 13594 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; |
| 13595 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; |
| 13596 | case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; |
| 13597 | default: abort (); |
| 13598 | } |
| 13599 | |
| 13600 | inst.instruction |= inst.operands[0].reg; |
| 13601 | inst.instruction |= inst.operands[2].reg << 3; |
| 13602 | |
| 13603 | /* PR 12854: Error on extraneous shifts. */ |
| 13604 | constraint (inst.operands[2].shifted, |
| 13605 | _("extraneous shift as part of operand to shift insn")); |
| 13606 | } |
| 13607 | else |
| 13608 | { |
| 13609 | switch (shift_kind) |
| 13610 | { |
| 13611 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; |
| 13612 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; |
| 13613 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; |
| 13614 | default: abort (); |
| 13615 | } |
| 13616 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT; |
| 13617 | inst.instruction |= inst.operands[0].reg; |
| 13618 | inst.instruction |= inst.operands[1].reg << 3; |
| 13619 | } |
| 13620 | } |
| 13621 | } |
| 13622 | else |
| 13623 | { |
| 13624 | constraint (inst.operands[0].reg > 7 |
| 13625 | || inst.operands[1].reg > 7, BAD_HIREG); |
| 13626 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); |
| 13627 | |
| 13628 | if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ |
| 13629 | { |
| 13630 | constraint (inst.operands[2].reg > 7, BAD_HIREG); |
| 13631 | constraint (inst.operands[0].reg != inst.operands[1].reg, |
| 13632 | _("source1 and dest must be same register")); |
| 13633 | |
| 13634 | switch (inst.instruction) |
| 13635 | { |
| 13636 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; |
| 13637 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; |
| 13638 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; |
| 13639 | case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; |
| 13640 | default: abort (); |
| 13641 | } |
| 13642 | |
| 13643 | inst.instruction |= inst.operands[0].reg; |
| 13644 | inst.instruction |= inst.operands[2].reg << 3; |
| 13645 | |
| 13646 | /* PR 12854: Error on extraneous shifts. */ |
| 13647 | constraint (inst.operands[2].shifted, |
| 13648 | _("extraneous shift as part of operand to shift insn")); |
| 13649 | } |
| 13650 | else |
| 13651 | { |
| 13652 | switch (inst.instruction) |
| 13653 | { |
| 13654 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; |
| 13655 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; |
| 13656 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; |
| 13657 | case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; |
| 13658 | default: abort (); |
| 13659 | } |
| 13660 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT; |
| 13661 | inst.instruction |= inst.operands[0].reg; |
| 13662 | inst.instruction |= inst.operands[1].reg << 3; |
| 13663 | } |
| 13664 | } |
| 13665 | } |
| 13666 | |
| 13667 | static void |
| 13668 | do_t_simd (void) |
| 13669 | { |
| 13670 | unsigned Rd, Rn, Rm; |
| 13671 | |
| 13672 | Rd = inst.operands[0].reg; |
| 13673 | Rn = inst.operands[1].reg; |
| 13674 | Rm = inst.operands[2].reg; |
| 13675 | |
| 13676 | reject_bad_reg (Rd); |
| 13677 | reject_bad_reg (Rn); |
| 13678 | reject_bad_reg (Rm); |
| 13679 | |
| 13680 | inst.instruction |= Rd << 8; |
| 13681 | inst.instruction |= Rn << 16; |
| 13682 | inst.instruction |= Rm; |
| 13683 | } |
| 13684 | |
| 13685 | static void |
| 13686 | do_t_simd2 (void) |
| 13687 | { |
| 13688 | unsigned Rd, Rn, Rm; |
| 13689 | |
| 13690 | Rd = inst.operands[0].reg; |
| 13691 | Rm = inst.operands[1].reg; |
| 13692 | Rn = inst.operands[2].reg; |
| 13693 | |
| 13694 | reject_bad_reg (Rd); |
| 13695 | reject_bad_reg (Rn); |
| 13696 | reject_bad_reg (Rm); |
| 13697 | |
| 13698 | inst.instruction |= Rd << 8; |
| 13699 | inst.instruction |= Rn << 16; |
| 13700 | inst.instruction |= Rm; |
| 13701 | } |
| 13702 | |
| 13703 | static void |
| 13704 | do_t_smc (void) |
| 13705 | { |
| 13706 | unsigned int value = inst.relocs[0].exp.X_add_number; |
| 13707 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a), |
| 13708 | _("SMC is not permitted on this architecture")); |
| 13709 | constraint (inst.relocs[0].exp.X_op != O_constant, |
| 13710 | _("expression too complex")); |
| 13711 | inst.relocs[0].type = BFD_RELOC_UNUSED; |
| 13712 | inst.instruction |= (value & 0xf000) >> 12; |
| 13713 | inst.instruction |= (value & 0x0ff0); |
| 13714 | inst.instruction |= (value & 0x000f) << 16; |
| 13715 | /* PR gas/15623: SMC instructions must be last in an IT block. */ |
| 13716 | set_pred_insn_type_last (); |
| 13717 | } |
| 13718 | |
| 13719 | static void |
| 13720 | do_t_hvc (void) |
| 13721 | { |
| 13722 | unsigned int value = inst.relocs[0].exp.X_add_number; |
| 13723 | |
| 13724 | inst.relocs[0].type = BFD_RELOC_UNUSED; |
| 13725 | inst.instruction |= (value & 0x0fff); |
| 13726 | inst.instruction |= (value & 0xf000) << 4; |
| 13727 | } |
| 13728 | |
| 13729 | static void |
| 13730 | do_t_ssat_usat (int bias) |
| 13731 | { |
| 13732 | unsigned Rd, Rn; |
| 13733 | |
| 13734 | Rd = inst.operands[0].reg; |
| 13735 | Rn = inst.operands[2].reg; |
| 13736 | |
| 13737 | reject_bad_reg (Rd); |
| 13738 | reject_bad_reg (Rn); |
| 13739 | |
| 13740 | inst.instruction |= Rd << 8; |
| 13741 | inst.instruction |= inst.operands[1].imm - bias; |
| 13742 | inst.instruction |= Rn << 16; |
| 13743 | |
| 13744 | if (inst.operands[3].present) |
| 13745 | { |
| 13746 | offsetT shift_amount = inst.relocs[0].exp.X_add_number; |
| 13747 | |
| 13748 | inst.relocs[0].type = BFD_RELOC_UNUSED; |
| 13749 | |
| 13750 | constraint (inst.relocs[0].exp.X_op != O_constant, |
| 13751 | _("expression too complex")); |
| 13752 | |
| 13753 | if (shift_amount != 0) |
| 13754 | { |
| 13755 | constraint (shift_amount > 31, |
| 13756 | _("shift expression is too large")); |
| 13757 | |
| 13758 | if (inst.operands[3].shift_kind == SHIFT_ASR) |
| 13759 | inst.instruction |= 0x00200000; /* sh bit. */ |
| 13760 | |
| 13761 | inst.instruction |= (shift_amount & 0x1c) << 10; |
| 13762 | inst.instruction |= (shift_amount & 0x03) << 6; |
| 13763 | } |
| 13764 | } |
| 13765 | } |
| 13766 | |
| 13767 | static void |
| 13768 | do_t_ssat (void) |
| 13769 | { |
| 13770 | do_t_ssat_usat (1); |
| 13771 | } |
| 13772 | |
| 13773 | static void |
| 13774 | do_t_ssat16 (void) |
| 13775 | { |
| 13776 | unsigned Rd, Rn; |
| 13777 | |
| 13778 | Rd = inst.operands[0].reg; |
| 13779 | Rn = inst.operands[2].reg; |
| 13780 | |
| 13781 | reject_bad_reg (Rd); |
| 13782 | reject_bad_reg (Rn); |
| 13783 | |
| 13784 | inst.instruction |= Rd << 8; |
| 13785 | inst.instruction |= inst.operands[1].imm - 1; |
| 13786 | inst.instruction |= Rn << 16; |
| 13787 | } |
| 13788 | |
| 13789 | static void |
| 13790 | do_t_strex (void) |
| 13791 | { |
| 13792 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind |
| 13793 | || inst.operands[2].postind || inst.operands[2].writeback |
| 13794 | || inst.operands[2].immisreg || inst.operands[2].shifted |
| 13795 | || inst.operands[2].negative, |
| 13796 | BAD_ADDR_MODE); |
| 13797 | |
| 13798 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
| 13799 | |
| 13800 | inst.instruction |= inst.operands[0].reg << 8; |
| 13801 | inst.instruction |= inst.operands[1].reg << 12; |
| 13802 | inst.instruction |= inst.operands[2].reg << 16; |
| 13803 | inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8; |
| 13804 | } |
| 13805 | |
| 13806 | static void |
| 13807 | do_t_strexd (void) |
| 13808 | { |
| 13809 | if (!inst.operands[2].present) |
| 13810 | inst.operands[2].reg = inst.operands[1].reg + 1; |
| 13811 | |
| 13812 | constraint (inst.operands[0].reg == inst.operands[1].reg |
| 13813 | || inst.operands[0].reg == inst.operands[2].reg |
| 13814 | || inst.operands[0].reg == inst.operands[3].reg, |
| 13815 | BAD_OVERLAP); |
| 13816 | |
| 13817 | inst.instruction |= inst.operands[0].reg; |
| 13818 | inst.instruction |= inst.operands[1].reg << 12; |
| 13819 | inst.instruction |= inst.operands[2].reg << 8; |
| 13820 | inst.instruction |= inst.operands[3].reg << 16; |
| 13821 | } |
| 13822 | |
| 13823 | static void |
| 13824 | do_t_sxtah (void) |
| 13825 | { |
| 13826 | unsigned Rd, Rn, Rm; |
| 13827 | |
| 13828 | Rd = inst.operands[0].reg; |
| 13829 | Rn = inst.operands[1].reg; |
| 13830 | Rm = inst.operands[2].reg; |
| 13831 | |
| 13832 | reject_bad_reg (Rd); |
| 13833 | reject_bad_reg (Rn); |
| 13834 | reject_bad_reg (Rm); |
| 13835 | |
| 13836 | inst.instruction |= Rd << 8; |
| 13837 | inst.instruction |= Rn << 16; |
| 13838 | inst.instruction |= Rm; |
| 13839 | inst.instruction |= inst.operands[3].imm << 4; |
| 13840 | } |
| 13841 | |
| 13842 | static void |
| 13843 | do_t_sxth (void) |
| 13844 | { |
| 13845 | unsigned Rd, Rm; |
| 13846 | |
| 13847 | Rd = inst.operands[0].reg; |
| 13848 | Rm = inst.operands[1].reg; |
| 13849 | |
| 13850 | reject_bad_reg (Rd); |
| 13851 | reject_bad_reg (Rm); |
| 13852 | |
| 13853 | if (inst.instruction <= 0xffff |
| 13854 | && inst.size_req != 4 |
| 13855 | && Rd <= 7 && Rm <= 7 |
| 13856 | && (!inst.operands[2].present || inst.operands[2].imm == 0)) |
| 13857 | { |
| 13858 | inst.instruction = THUMB_OP16 (inst.instruction); |
| 13859 | inst.instruction |= Rd; |
| 13860 | inst.instruction |= Rm << 3; |
| 13861 | } |
| 13862 | else if (unified_syntax) |
| 13863 | { |
| 13864 | if (inst.instruction <= 0xffff) |
| 13865 | inst.instruction = THUMB_OP32 (inst.instruction); |
| 13866 | inst.instruction |= Rd << 8; |
| 13867 | inst.instruction |= Rm; |
| 13868 | inst.instruction |= inst.operands[2].imm << 4; |
| 13869 | } |
| 13870 | else |
| 13871 | { |
| 13872 | constraint (inst.operands[2].present && inst.operands[2].imm != 0, |
| 13873 | _("Thumb encoding does not support rotation")); |
| 13874 | constraint (1, BAD_HIREG); |
| 13875 | } |
| 13876 | } |
| 13877 | |
| 13878 | static void |
| 13879 | do_t_swi (void) |
| 13880 | { |
| 13881 | inst.relocs[0].type = BFD_RELOC_ARM_SWI; |
| 13882 | } |
| 13883 | |
| 13884 | static void |
| 13885 | do_t_tb (void) |
| 13886 | { |
| 13887 | unsigned Rn, Rm; |
| 13888 | int half; |
| 13889 | |
| 13890 | half = (inst.instruction & 0x10) != 0; |
| 13891 | set_pred_insn_type_last (); |
| 13892 | constraint (inst.operands[0].immisreg, |
| 13893 | _("instruction requires register index")); |
| 13894 | |
| 13895 | Rn = inst.operands[0].reg; |
| 13896 | Rm = inst.operands[0].imm; |
| 13897 | |
| 13898 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) |
| 13899 | constraint (Rn == REG_SP, BAD_SP); |
| 13900 | reject_bad_reg (Rm); |
| 13901 | |
| 13902 | constraint (!half && inst.operands[0].shifted, |
| 13903 | _("instruction does not allow shifted index")); |
| 13904 | inst.instruction |= (Rn << 16) | Rm; |
| 13905 | } |
| 13906 | |
| 13907 | static void |
| 13908 | do_t_udf (void) |
| 13909 | { |
| 13910 | if (!inst.operands[0].present) |
| 13911 | inst.operands[0].imm = 0; |
| 13912 | |
| 13913 | if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4) |
| 13914 | { |
| 13915 | constraint (inst.size_req == 2, |
| 13916 | _("immediate value out of range")); |
| 13917 | inst.instruction = THUMB_OP32 (inst.instruction); |
| 13918 | inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4; |
| 13919 | inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0; |
| 13920 | } |
| 13921 | else |
| 13922 | { |
| 13923 | inst.instruction = THUMB_OP16 (inst.instruction); |
| 13924 | inst.instruction |= inst.operands[0].imm; |
| 13925 | } |
| 13926 | |
| 13927 | set_pred_insn_type (NEUTRAL_IT_INSN); |
| 13928 | } |
| 13929 | |
| 13930 | |
| 13931 | static void |
| 13932 | do_t_usat (void) |
| 13933 | { |
| 13934 | do_t_ssat_usat (0); |
| 13935 | } |
| 13936 | |
| 13937 | static void |
| 13938 | do_t_usat16 (void) |
| 13939 | { |
| 13940 | unsigned Rd, Rn; |
| 13941 | |
| 13942 | Rd = inst.operands[0].reg; |
| 13943 | Rn = inst.operands[2].reg; |
| 13944 | |
| 13945 | reject_bad_reg (Rd); |
| 13946 | reject_bad_reg (Rn); |
| 13947 | |
| 13948 | inst.instruction |= Rd << 8; |
| 13949 | inst.instruction |= inst.operands[1].imm; |
| 13950 | inst.instruction |= Rn << 16; |
| 13951 | } |
| 13952 | |
| 13953 | /* Checking the range of the branch offset (VAL) with NBITS bits |
| 13954 | and IS_SIGNED signedness. Also checks the LSB to be 0. */ |
| 13955 | static int |
| 13956 | v8_1_branch_value_check (int val, int nbits, int is_signed) |
| 13957 | { |
| 13958 | gas_assert (nbits > 0 && nbits <= 32); |
| 13959 | if (is_signed) |
| 13960 | { |
| 13961 | int cmp = (1 << (nbits - 1)); |
| 13962 | if ((val < -cmp) || (val >= cmp) || (val & 0x01)) |
| 13963 | return FAIL; |
| 13964 | } |
| 13965 | else |
| 13966 | { |
| 13967 | if ((val <= 0) || (val >= (1 << nbits)) || (val & 0x1)) |
| 13968 | return FAIL; |
| 13969 | } |
| 13970 | return SUCCESS; |
| 13971 | } |
| 13972 | |
| 13973 | /* For branches in Armv8.1-M Mainline. */ |
| 13974 | static void |
| 13975 | do_t_branch_future (void) |
| 13976 | { |
| 13977 | unsigned long insn = inst.instruction; |
| 13978 | |
| 13979 | inst.instruction = THUMB_OP32 (inst.instruction); |
| 13980 | if (inst.operands[0].hasreloc == 0) |
| 13981 | { |
| 13982 | if (v8_1_branch_value_check (inst.operands[0].imm, 5, FALSE) == FAIL) |
| 13983 | as_bad (BAD_BRANCH_OFF); |
| 13984 | |
| 13985 | inst.instruction |= ((inst.operands[0].imm & 0x1f) >> 1) << 23; |
| 13986 | } |
| 13987 | else |
| 13988 | { |
| 13989 | inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH5; |
| 13990 | inst.relocs[0].pc_rel = 1; |
| 13991 | } |
| 13992 | |
| 13993 | switch (insn) |
| 13994 | { |
| 13995 | case T_MNEM_bf: |
| 13996 | if (inst.operands[1].hasreloc == 0) |
| 13997 | { |
| 13998 | int val = inst.operands[1].imm; |
| 13999 | if (v8_1_branch_value_check (inst.operands[1].imm, 17, TRUE) == FAIL) |
| 14000 | as_bad (BAD_BRANCH_OFF); |
| 14001 | |
| 14002 | int immA = (val & 0x0001f000) >> 12; |
| 14003 | int immB = (val & 0x00000ffc) >> 2; |
| 14004 | int immC = (val & 0x00000002) >> 1; |
| 14005 | inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11); |
| 14006 | } |
| 14007 | else |
| 14008 | { |
| 14009 | inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF17; |
| 14010 | inst.relocs[1].pc_rel = 1; |
| 14011 | } |
| 14012 | break; |
| 14013 | |
| 14014 | case T_MNEM_bfl: |
| 14015 | if (inst.operands[1].hasreloc == 0) |
| 14016 | { |
| 14017 | int val = inst.operands[1].imm; |
| 14018 | if (v8_1_branch_value_check (inst.operands[1].imm, 19, TRUE) == FAIL) |
| 14019 | as_bad (BAD_BRANCH_OFF); |
| 14020 | |
| 14021 | int immA = (val & 0x0007f000) >> 12; |
| 14022 | int immB = (val & 0x00000ffc) >> 2; |
| 14023 | int immC = (val & 0x00000002) >> 1; |
| 14024 | inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11); |
| 14025 | } |
| 14026 | else |
| 14027 | { |
| 14028 | inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF19; |
| 14029 | inst.relocs[1].pc_rel = 1; |
| 14030 | } |
| 14031 | break; |
| 14032 | |
| 14033 | case T_MNEM_bfcsel: |
| 14034 | /* Operand 1. */ |
| 14035 | if (inst.operands[1].hasreloc == 0) |
| 14036 | { |
| 14037 | int val = inst.operands[1].imm; |
| 14038 | int immA = (val & 0x00001000) >> 12; |
| 14039 | int immB = (val & 0x00000ffc) >> 2; |
| 14040 | int immC = (val & 0x00000002) >> 1; |
| 14041 | inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11); |
| 14042 | } |
| 14043 | else |
| 14044 | { |
| 14045 | inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF13; |
| 14046 | inst.relocs[1].pc_rel = 1; |
| 14047 | } |
| 14048 | |
| 14049 | /* Operand 2. */ |
| 14050 | if (inst.operands[2].hasreloc == 0) |
| 14051 | { |
| 14052 | constraint ((inst.operands[0].hasreloc != 0), BAD_ARGS); |
| 14053 | int val2 = inst.operands[2].imm; |
| 14054 | int val0 = inst.operands[0].imm & 0x1f; |
| 14055 | int diff = val2 - val0; |
| 14056 | if (diff == 4) |
| 14057 | inst.instruction |= 1 << 17; /* T bit. */ |
| 14058 | else if (diff != 2) |
| 14059 | as_bad (_("out of range label-relative fixup value")); |
| 14060 | } |
| 14061 | else |
| 14062 | { |
| 14063 | constraint ((inst.operands[0].hasreloc == 0), BAD_ARGS); |
| 14064 | inst.relocs[2].type = BFD_RELOC_THUMB_PCREL_BFCSEL; |
| 14065 | inst.relocs[2].pc_rel = 1; |
| 14066 | } |
| 14067 | |
| 14068 | /* Operand 3. */ |
| 14069 | constraint (inst.cond != COND_ALWAYS, BAD_COND); |
| 14070 | inst.instruction |= (inst.operands[3].imm & 0xf) << 18; |
| 14071 | break; |
| 14072 | |
| 14073 | case T_MNEM_bfx: |
| 14074 | case T_MNEM_bflx: |
| 14075 | inst.instruction |= inst.operands[1].reg << 16; |
| 14076 | break; |
| 14077 | |
| 14078 | default: abort (); |
| 14079 | } |
| 14080 | } |
| 14081 | |
| 14082 | /* Helper function for do_t_loloop to handle relocations. */ |
| 14083 | static void |
| 14084 | v8_1_loop_reloc (int is_le) |
| 14085 | { |
| 14086 | if (inst.relocs[0].exp.X_op == O_constant) |
| 14087 | { |
| 14088 | int value = inst.relocs[0].exp.X_add_number; |
| 14089 | value = (is_le) ? -value : value; |
| 14090 | |
| 14091 | if (v8_1_branch_value_check (value, 12, FALSE) == FAIL) |
| 14092 | as_bad (BAD_BRANCH_OFF); |
| 14093 | |
| 14094 | int imml, immh; |
| 14095 | |
| 14096 | immh = (value & 0x00000ffc) >> 2; |
| 14097 | imml = (value & 0x00000002) >> 1; |
| 14098 | |
| 14099 | inst.instruction |= (imml << 11) | (immh << 1); |
| 14100 | } |
| 14101 | else |
| 14102 | { |
| 14103 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_LOOP12; |
| 14104 | inst.relocs[0].pc_rel = 1; |
| 14105 | } |
| 14106 | } |
| 14107 | |
| 14108 | /* To handle the Scalar Low Overhead Loop instructions |
| 14109 | in Armv8.1-M Mainline. */ |
| 14110 | static void |
| 14111 | do_t_loloop (void) |
| 14112 | { |
| 14113 | unsigned long insn = inst.instruction; |
| 14114 | |
| 14115 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
| 14116 | inst.instruction = THUMB_OP32 (inst.instruction); |
| 14117 | |
| 14118 | switch (insn) |
| 14119 | { |
| 14120 | case T_MNEM_le: |
| 14121 | /* le <label>. */ |
| 14122 | if (!inst.operands[0].present) |
| 14123 | inst.instruction |= 1 << 21; |
| 14124 | |
| 14125 | v8_1_loop_reloc (TRUE); |
| 14126 | break; |
| 14127 | |
| 14128 | case T_MNEM_wls: |
| 14129 | v8_1_loop_reloc (FALSE); |
| 14130 | /* Fall through. */ |
| 14131 | case T_MNEM_dls: |
| 14132 | constraint (inst.operands[1].isreg != 1, BAD_ARGS); |
| 14133 | inst.instruction |= (inst.operands[1].reg << 16); |
| 14134 | break; |
| 14135 | |
| 14136 | default: abort(); |
| 14137 | } |
| 14138 | } |
| 14139 | |
| 14140 | /* MVE instruction encoder helpers. */ |
| 14141 | #define M_MNEM_vabav 0xee800f01 |
| 14142 | #define M_MNEM_vmladav 0xeef00e00 |
| 14143 | #define M_MNEM_vmladava 0xeef00e20 |
| 14144 | #define M_MNEM_vmladavx 0xeef01e00 |
| 14145 | #define M_MNEM_vmladavax 0xeef01e20 |
| 14146 | #define M_MNEM_vmlsdav 0xeef00e01 |
| 14147 | #define M_MNEM_vmlsdava 0xeef00e21 |
| 14148 | #define M_MNEM_vmlsdavx 0xeef01e01 |
| 14149 | #define M_MNEM_vmlsdavax 0xeef01e21 |
| 14150 | #define M_MNEM_vmullt 0xee011e00 |
| 14151 | #define M_MNEM_vmullb 0xee010e00 |
| 14152 | #define M_MNEM_vst20 0xfc801e00 |
| 14153 | #define M_MNEM_vst21 0xfc801e20 |
| 14154 | #define M_MNEM_vst40 0xfc801e01 |
| 14155 | #define M_MNEM_vst41 0xfc801e21 |
| 14156 | #define M_MNEM_vst42 0xfc801e41 |
| 14157 | #define M_MNEM_vst43 0xfc801e61 |
| 14158 | #define M_MNEM_vld20 0xfc901e00 |
| 14159 | #define M_MNEM_vld21 0xfc901e20 |
| 14160 | #define M_MNEM_vld40 0xfc901e01 |
| 14161 | #define M_MNEM_vld41 0xfc901e21 |
| 14162 | #define M_MNEM_vld42 0xfc901e41 |
| 14163 | #define M_MNEM_vld43 0xfc901e61 |
| 14164 | #define M_MNEM_vstrb 0xec000e00 |
| 14165 | #define M_MNEM_vstrh 0xec000e10 |
| 14166 | #define M_MNEM_vstrw 0xec000e40 |
| 14167 | #define M_MNEM_vstrd 0xec000e50 |
| 14168 | #define M_MNEM_vldrb 0xec100e00 |
| 14169 | #define M_MNEM_vldrh 0xec100e10 |
| 14170 | #define M_MNEM_vldrw 0xec100e40 |
| 14171 | #define M_MNEM_vldrd 0xec100e50 |
| 14172 | #define M_MNEM_vmovlt 0xeea01f40 |
| 14173 | #define M_MNEM_vmovlb 0xeea00f40 |
| 14174 | #define M_MNEM_vmovnt 0xfe311e81 |
| 14175 | #define M_MNEM_vmovnb 0xfe310e81 |
| 14176 | #define M_MNEM_vadc 0xee300f00 |
| 14177 | #define M_MNEM_vadci 0xee301f00 |
| 14178 | #define M_MNEM_vbrsr 0xfe011e60 |
| 14179 | #define M_MNEM_vaddlv 0xee890f00 |
| 14180 | #define M_MNEM_vaddlva 0xee890f20 |
| 14181 | #define M_MNEM_vaddv 0xeef10f00 |
| 14182 | #define M_MNEM_vaddva 0xeef10f20 |
| 14183 | #define M_MNEM_vddup 0xee011f6e |
| 14184 | #define M_MNEM_vdwdup 0xee011f60 |
| 14185 | #define M_MNEM_vidup 0xee010f6e |
| 14186 | #define M_MNEM_viwdup 0xee010f60 |
| 14187 | #define M_MNEM_vmaxv 0xeee20f00 |
| 14188 | #define M_MNEM_vmaxav 0xeee00f00 |
| 14189 | #define M_MNEM_vminv 0xeee20f80 |
| 14190 | #define M_MNEM_vminav 0xeee00f80 |
| 14191 | #define M_MNEM_vmlaldav 0xee800e00 |
| 14192 | #define M_MNEM_vmlaldava 0xee800e20 |
| 14193 | #define M_MNEM_vmlaldavx 0xee801e00 |
| 14194 | #define M_MNEM_vmlaldavax 0xee801e20 |
| 14195 | #define M_MNEM_vmlsldav 0xee800e01 |
| 14196 | #define M_MNEM_vmlsldava 0xee800e21 |
| 14197 | #define M_MNEM_vmlsldavx 0xee801e01 |
| 14198 | #define M_MNEM_vmlsldavax 0xee801e21 |
| 14199 | #define M_MNEM_vrmlaldavhx 0xee801f00 |
| 14200 | #define M_MNEM_vrmlaldavhax 0xee801f20 |
| 14201 | #define M_MNEM_vrmlsldavh 0xfe800e01 |
| 14202 | #define M_MNEM_vrmlsldavha 0xfe800e21 |
| 14203 | #define M_MNEM_vrmlsldavhx 0xfe801e01 |
| 14204 | #define M_MNEM_vrmlsldavhax 0xfe801e21 |
| 14205 | #define M_MNEM_vqmovnt 0xee331e01 |
| 14206 | #define M_MNEM_vqmovnb 0xee330e01 |
| 14207 | #define M_MNEM_vqmovunt 0xee311e81 |
| 14208 | #define M_MNEM_vqmovunb 0xee310e81 |
| 14209 | |
| 14210 | /* Neon instruction encoder helpers. */ |
| 14211 | |
| 14212 | /* Encodings for the different types for various Neon opcodes. */ |
| 14213 | |
| 14214 | /* An "invalid" code for the following tables. */ |
| 14215 | #define N_INV -1u |
| 14216 | |
| 14217 | struct neon_tab_entry |
| 14218 | { |
| 14219 | unsigned integer; |
| 14220 | unsigned float_or_poly; |
| 14221 | unsigned scalar_or_imm; |
| 14222 | }; |
| 14223 | |
| 14224 | /* Map overloaded Neon opcodes to their respective encodings. */ |
| 14225 | #define NEON_ENC_TAB \ |
| 14226 | X(vabd, 0x0000700, 0x1200d00, N_INV), \ |
| 14227 | X(vabdl, 0x0800700, N_INV, N_INV), \ |
| 14228 | X(vmax, 0x0000600, 0x0000f00, N_INV), \ |
| 14229 | X(vmin, 0x0000610, 0x0200f00, N_INV), \ |
| 14230 | X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ |
| 14231 | X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ |
| 14232 | X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ |
| 14233 | X(vadd, 0x0000800, 0x0000d00, N_INV), \ |
| 14234 | X(vaddl, 0x0800000, N_INV, N_INV), \ |
| 14235 | X(vsub, 0x1000800, 0x0200d00, N_INV), \ |
| 14236 | X(vsubl, 0x0800200, N_INV, N_INV), \ |
| 14237 | X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ |
| 14238 | X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ |
| 14239 | X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ |
| 14240 | /* Register variants of the following two instructions are encoded as |
| 14241 | vcge / vcgt with the operands reversed. */ \ |
| 14242 | X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \ |
| 14243 | X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \ |
| 14244 | X(vfma, N_INV, 0x0000c10, N_INV), \ |
| 14245 | X(vfms, N_INV, 0x0200c10, N_INV), \ |
| 14246 | X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ |
| 14247 | X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ |
| 14248 | X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ |
| 14249 | X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ |
| 14250 | X(vmlal, 0x0800800, N_INV, 0x0800240), \ |
| 14251 | X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ |
| 14252 | X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ |
| 14253 | X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ |
| 14254 | X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ |
| 14255 | X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ |
| 14256 | X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ |
| 14257 | X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \ |
| 14258 | X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \ |
| 14259 | X(vshl, 0x0000400, N_INV, 0x0800510), \ |
| 14260 | X(vqshl, 0x0000410, N_INV, 0x0800710), \ |
| 14261 | X(vand, 0x0000110, N_INV, 0x0800030), \ |
| 14262 | X(vbic, 0x0100110, N_INV, 0x0800030), \ |
| 14263 | X(veor, 0x1000110, N_INV, N_INV), \ |
| 14264 | X(vorn, 0x0300110, N_INV, 0x0800010), \ |
| 14265 | X(vorr, 0x0200110, N_INV, 0x0800010), \ |
| 14266 | X(vmvn, 0x1b00580, N_INV, 0x0800030), \ |
| 14267 | X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ |
| 14268 | X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ |
| 14269 | X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ |
| 14270 | X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ |
| 14271 | X(vst1, 0x0000000, 0x0800000, N_INV), \ |
| 14272 | X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ |
| 14273 | X(vst2, 0x0000100, 0x0800100, N_INV), \ |
| 14274 | X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ |
| 14275 | X(vst3, 0x0000200, 0x0800200, N_INV), \ |
| 14276 | X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ |
| 14277 | X(vst4, 0x0000300, 0x0800300, N_INV), \ |
| 14278 | X(vmovn, 0x1b20200, N_INV, N_INV), \ |
| 14279 | X(vtrn, 0x1b20080, N_INV, N_INV), \ |
| 14280 | X(vqmovn, 0x1b20200, N_INV, N_INV), \ |
| 14281 | X(vqmovun, 0x1b20240, N_INV, N_INV), \ |
| 14282 | X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ |
| 14283 | X(vnmla, 0xe100a40, 0xe100b40, N_INV), \ |
| 14284 | X(vnmls, 0xe100a00, 0xe100b00, N_INV), \ |
| 14285 | X(vfnma, 0xe900a40, 0xe900b40, N_INV), \ |
| 14286 | X(vfnms, 0xe900a00, 0xe900b00, N_INV), \ |
| 14287 | X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ |
| 14288 | X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ |
| 14289 | X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ |
| 14290 | X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \ |
| 14291 | X(vseleq, 0xe000a00, N_INV, N_INV), \ |
| 14292 | X(vselvs, 0xe100a00, N_INV, N_INV), \ |
| 14293 | X(vselge, 0xe200a00, N_INV, N_INV), \ |
| 14294 | X(vselgt, 0xe300a00, N_INV, N_INV), \ |
| 14295 | X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \ |
| 14296 | X(vminnm, 0xe800a40, 0x3200f10, N_INV), \ |
| 14297 | X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \ |
| 14298 | X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \ |
| 14299 | X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \ |
| 14300 | X(aes, 0x3b00300, N_INV, N_INV), \ |
| 14301 | X(sha3op, 0x2000c00, N_INV, N_INV), \ |
| 14302 | X(sha1h, 0x3b902c0, N_INV, N_INV), \ |
| 14303 | X(sha2op, 0x3ba0380, N_INV, N_INV) |
| 14304 | |
| 14305 | enum neon_opc |
| 14306 | { |
| 14307 | #define X(OPC,I,F,S) N_MNEM_##OPC |
| 14308 | NEON_ENC_TAB |
| 14309 | #undef X |
| 14310 | }; |
| 14311 | |
| 14312 | static const struct neon_tab_entry neon_enc_tab[] = |
| 14313 | { |
| 14314 | #define X(OPC,I,F,S) { (I), (F), (S) } |
| 14315 | NEON_ENC_TAB |
| 14316 | #undef X |
| 14317 | }; |
| 14318 | |
| 14319 | /* Do not use these macros; instead, use NEON_ENCODE defined below. */ |
| 14320 | #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) |
| 14321 | #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) |
| 14322 | #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) |
| 14323 | #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) |
| 14324 | #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) |
| 14325 | #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) |
| 14326 | #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) |
| 14327 | #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) |
| 14328 | #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) |
| 14329 | #define NEON_ENC_SINGLE_(X) \ |
| 14330 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) |
| 14331 | #define NEON_ENC_DOUBLE_(X) \ |
| 14332 | ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) |
| 14333 | #define NEON_ENC_FPV8_(X) \ |
| 14334 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000)) |
| 14335 | |
| 14336 | #define NEON_ENCODE(type, inst) \ |
| 14337 | do \ |
| 14338 | { \ |
| 14339 | inst.instruction = NEON_ENC_##type##_ (inst.instruction); \ |
| 14340 | inst.is_neon = 1; \ |
| 14341 | } \ |
| 14342 | while (0) |
| 14343 | |
| 14344 | #define check_neon_suffixes \ |
| 14345 | do \ |
| 14346 | { \ |
| 14347 | if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \ |
| 14348 | { \ |
| 14349 | as_bad (_("invalid neon suffix for non neon instruction")); \ |
| 14350 | return; \ |
| 14351 | } \ |
| 14352 | } \ |
| 14353 | while (0) |
| 14354 | |
| 14355 | /* Define shapes for instruction operands. The following mnemonic characters |
| 14356 | are used in this table: |
| 14357 | |
| 14358 | F - VFP S<n> register |
| 14359 | D - Neon D<n> register |
| 14360 | Q - Neon Q<n> register |
| 14361 | I - Immediate |
| 14362 | S - Scalar |
| 14363 | R - ARM register |
| 14364 | L - D<n> register list |
| 14365 | |
| 14366 | This table is used to generate various data: |
| 14367 | - enumerations of the form NS_DDR to be used as arguments to |
| 14368 | neon_select_shape. |
| 14369 | - a table classifying shapes into single, double, quad, mixed. |
| 14370 | - a table used to drive neon_select_shape. */ |
| 14371 | |
| 14372 | #define NEON_SHAPE_DEF \ |
| 14373 | X(4, (R, R, Q, Q), QUAD), \ |
| 14374 | X(4, (Q, R, R, I), QUAD), \ |
| 14375 | X(4, (R, R, S, S), QUAD), \ |
| 14376 | X(4, (S, S, R, R), QUAD), \ |
| 14377 | X(3, (Q, R, I), QUAD), \ |
| 14378 | X(3, (I, Q, Q), QUAD), \ |
| 14379 | X(3, (I, Q, R), QUAD), \ |
| 14380 | X(3, (R, Q, Q), QUAD), \ |
| 14381 | X(3, (D, D, D), DOUBLE), \ |
| 14382 | X(3, (Q, Q, Q), QUAD), \ |
| 14383 | X(3, (D, D, I), DOUBLE), \ |
| 14384 | X(3, (Q, Q, I), QUAD), \ |
| 14385 | X(3, (D, D, S), DOUBLE), \ |
| 14386 | X(3, (Q, Q, S), QUAD), \ |
| 14387 | X(3, (Q, Q, R), QUAD), \ |
| 14388 | X(3, (R, R, Q), QUAD), \ |
| 14389 | X(2, (R, Q), QUAD), \ |
| 14390 | X(2, (D, D), DOUBLE), \ |
| 14391 | X(2, (Q, Q), QUAD), \ |
| 14392 | X(2, (D, S), DOUBLE), \ |
| 14393 | X(2, (Q, S), QUAD), \ |
| 14394 | X(2, (D, R), DOUBLE), \ |
| 14395 | X(2, (Q, R), QUAD), \ |
| 14396 | X(2, (D, I), DOUBLE), \ |
| 14397 | X(2, (Q, I), QUAD), \ |
| 14398 | X(3, (D, L, D), DOUBLE), \ |
| 14399 | X(2, (D, Q), MIXED), \ |
| 14400 | X(2, (Q, D), MIXED), \ |
| 14401 | X(3, (D, Q, I), MIXED), \ |
| 14402 | X(3, (Q, D, I), MIXED), \ |
| 14403 | X(3, (Q, D, D), MIXED), \ |
| 14404 | X(3, (D, Q, Q), MIXED), \ |
| 14405 | X(3, (Q, Q, D), MIXED), \ |
| 14406 | X(3, (Q, D, S), MIXED), \ |
| 14407 | X(3, (D, Q, S), MIXED), \ |
| 14408 | X(4, (D, D, D, I), DOUBLE), \ |
| 14409 | X(4, (Q, Q, Q, I), QUAD), \ |
| 14410 | X(4, (D, D, S, I), DOUBLE), \ |
| 14411 | X(4, (Q, Q, S, I), QUAD), \ |
| 14412 | X(2, (F, F), SINGLE), \ |
| 14413 | X(3, (F, F, F), SINGLE), \ |
| 14414 | X(2, (F, I), SINGLE), \ |
| 14415 | X(2, (F, D), MIXED), \ |
| 14416 | X(2, (D, F), MIXED), \ |
| 14417 | X(3, (F, F, I), MIXED), \ |
| 14418 | X(4, (R, R, F, F), SINGLE), \ |
| 14419 | X(4, (F, F, R, R), SINGLE), \ |
| 14420 | X(3, (D, R, R), DOUBLE), \ |
| 14421 | X(3, (R, R, D), DOUBLE), \ |
| 14422 | X(2, (S, R), SINGLE), \ |
| 14423 | X(2, (R, S), SINGLE), \ |
| 14424 | X(2, (F, R), SINGLE), \ |
| 14425 | X(2, (R, F), SINGLE), \ |
| 14426 | /* Half float shape supported so far. */\ |
| 14427 | X (2, (H, D), MIXED), \ |
| 14428 | X (2, (D, H), MIXED), \ |
| 14429 | X (2, (H, F), MIXED), \ |
| 14430 | X (2, (F, H), MIXED), \ |
| 14431 | X (2, (H, H), HALF), \ |
| 14432 | X (2, (H, R), HALF), \ |
| 14433 | X (2, (R, H), HALF), \ |
| 14434 | X (2, (H, I), HALF), \ |
| 14435 | X (3, (H, H, H), HALF), \ |
| 14436 | X (3, (H, F, I), MIXED), \ |
| 14437 | X (3, (F, H, I), MIXED), \ |
| 14438 | X (3, (D, H, H), MIXED), \ |
| 14439 | X (3, (D, H, S), MIXED) |
| 14440 | |
| 14441 | #define S2(A,B) NS_##A##B |
| 14442 | #define S3(A,B,C) NS_##A##B##C |
| 14443 | #define S4(A,B,C,D) NS_##A##B##C##D |
| 14444 | |
| 14445 | #define X(N, L, C) S##N L |
| 14446 | |
| 14447 | enum neon_shape |
| 14448 | { |
| 14449 | NEON_SHAPE_DEF, |
| 14450 | NS_NULL |
| 14451 | }; |
| 14452 | |
| 14453 | #undef X |
| 14454 | #undef S2 |
| 14455 | #undef S3 |
| 14456 | #undef S4 |
| 14457 | |
| 14458 | enum neon_shape_class |
| 14459 | { |
| 14460 | SC_HALF, |
| 14461 | SC_SINGLE, |
| 14462 | SC_DOUBLE, |
| 14463 | SC_QUAD, |
| 14464 | SC_MIXED |
| 14465 | }; |
| 14466 | |
| 14467 | #define X(N, L, C) SC_##C |
| 14468 | |
| 14469 | static enum neon_shape_class neon_shape_class[] = |
| 14470 | { |
| 14471 | NEON_SHAPE_DEF |
| 14472 | }; |
| 14473 | |
| 14474 | #undef X |
| 14475 | |
| 14476 | enum neon_shape_el |
| 14477 | { |
| 14478 | SE_H, |
| 14479 | SE_F, |
| 14480 | SE_D, |
| 14481 | SE_Q, |
| 14482 | SE_I, |
| 14483 | SE_S, |
| 14484 | SE_R, |
| 14485 | SE_L |
| 14486 | }; |
| 14487 | |
| 14488 | /* Register widths of above. */ |
| 14489 | static unsigned neon_shape_el_size[] = |
| 14490 | { |
| 14491 | 16, |
| 14492 | 32, |
| 14493 | 64, |
| 14494 | 128, |
| 14495 | 0, |
| 14496 | 32, |
| 14497 | 32, |
| 14498 | 0 |
| 14499 | }; |
| 14500 | |
| 14501 | struct neon_shape_info |
| 14502 | { |
| 14503 | unsigned els; |
| 14504 | enum neon_shape_el el[NEON_MAX_TYPE_ELS]; |
| 14505 | }; |
| 14506 | |
| 14507 | #define S2(A,B) { SE_##A, SE_##B } |
| 14508 | #define S3(A,B,C) { SE_##A, SE_##B, SE_##C } |
| 14509 | #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } |
| 14510 | |
| 14511 | #define X(N, L, C) { N, S##N L } |
| 14512 | |
| 14513 | static struct neon_shape_info neon_shape_tab[] = |
| 14514 | { |
| 14515 | NEON_SHAPE_DEF |
| 14516 | }; |
| 14517 | |
| 14518 | #undef X |
| 14519 | #undef S2 |
| 14520 | #undef S3 |
| 14521 | #undef S4 |
| 14522 | |
| 14523 | /* Bit masks used in type checking given instructions. |
| 14524 | 'N_EQK' means the type must be the same as (or based on in some way) the key |
| 14525 | type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is |
| 14526 | set, various other bits can be set as well in order to modify the meaning of |
| 14527 | the type constraint. */ |
| 14528 | |
| 14529 | enum neon_type_mask |
| 14530 | { |
| 14531 | N_S8 = 0x0000001, |
| 14532 | N_S16 = 0x0000002, |
| 14533 | N_S32 = 0x0000004, |
| 14534 | N_S64 = 0x0000008, |
| 14535 | N_U8 = 0x0000010, |
| 14536 | N_U16 = 0x0000020, |
| 14537 | N_U32 = 0x0000040, |
| 14538 | N_U64 = 0x0000080, |
| 14539 | N_I8 = 0x0000100, |
| 14540 | N_I16 = 0x0000200, |
| 14541 | N_I32 = 0x0000400, |
| 14542 | N_I64 = 0x0000800, |
| 14543 | N_8 = 0x0001000, |
| 14544 | N_16 = 0x0002000, |
| 14545 | N_32 = 0x0004000, |
| 14546 | N_64 = 0x0008000, |
| 14547 | N_P8 = 0x0010000, |
| 14548 | N_P16 = 0x0020000, |
| 14549 | N_F16 = 0x0040000, |
| 14550 | N_F32 = 0x0080000, |
| 14551 | N_F64 = 0x0100000, |
| 14552 | N_P64 = 0x0200000, |
| 14553 | N_KEY = 0x1000000, /* Key element (main type specifier). */ |
| 14554 | N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */ |
| 14555 | N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */ |
| 14556 | N_UNT = 0x8000000, /* Must be explicitly untyped. */ |
| 14557 | N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */ |
| 14558 | N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */ |
| 14559 | N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */ |
| 14560 | N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */ |
| 14561 | N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */ |
| 14562 | N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */ |
| 14563 | N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */ |
| 14564 | N_UTYP = 0, |
| 14565 | N_MAX_NONSPECIAL = N_P64 |
| 14566 | }; |
| 14567 | |
| 14568 | #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) |
| 14569 | |
| 14570 | #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) |
| 14571 | #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) |
| 14572 | #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) |
| 14573 | #define N_S_32 (N_S8 | N_S16 | N_S32) |
| 14574 | #define N_F_16_32 (N_F16 | N_F32) |
| 14575 | #define N_SUF_32 (N_SU_32 | N_F_16_32) |
| 14576 | #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) |
| 14577 | #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32) |
| 14578 | #define N_F_ALL (N_F16 | N_F32 | N_F64) |
| 14579 | #define N_I_MVE (N_I8 | N_I16 | N_I32) |
| 14580 | #define N_F_MVE (N_F16 | N_F32) |
| 14581 | #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) |
| 14582 | |
| 14583 | /* Pass this as the first type argument to neon_check_type to ignore types |
| 14584 | altogether. */ |
| 14585 | #define N_IGNORE_TYPE (N_KEY | N_EQK) |
| 14586 | |
| 14587 | /* Select a "shape" for the current instruction (describing register types or |
| 14588 | sizes) from a list of alternatives. Return NS_NULL if the current instruction |
| 14589 | doesn't fit. For non-polymorphic shapes, checking is usually done as a |
| 14590 | function of operand parsing, so this function doesn't need to be called. |
| 14591 | Shapes should be listed in order of decreasing length. */ |
| 14592 | |
| 14593 | static enum neon_shape |
| 14594 | neon_select_shape (enum neon_shape shape, ...) |
| 14595 | { |
| 14596 | va_list ap; |
| 14597 | enum neon_shape first_shape = shape; |
| 14598 | |
| 14599 | /* Fix missing optional operands. FIXME: we don't know at this point how |
| 14600 | many arguments we should have, so this makes the assumption that we have |
| 14601 | > 1. This is true of all current Neon opcodes, I think, but may not be |
| 14602 | true in the future. */ |
| 14603 | if (!inst.operands[1].present) |
| 14604 | inst.operands[1] = inst.operands[0]; |
| 14605 | |
| 14606 | va_start (ap, shape); |
| 14607 | |
| 14608 | for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int)) |
| 14609 | { |
| 14610 | unsigned j; |
| 14611 | int matches = 1; |
| 14612 | |
| 14613 | for (j = 0; j < neon_shape_tab[shape].els; j++) |
| 14614 | { |
| 14615 | if (!inst.operands[j].present) |
| 14616 | { |
| 14617 | matches = 0; |
| 14618 | break; |
| 14619 | } |
| 14620 | |
| 14621 | switch (neon_shape_tab[shape].el[j]) |
| 14622 | { |
| 14623 | /* If a .f16, .16, .u16, .s16 type specifier is given over |
| 14624 | a VFP single precision register operand, it's essentially |
| 14625 | means only half of the register is used. |
| 14626 | |
| 14627 | If the type specifier is given after the mnemonics, the |
| 14628 | information is stored in inst.vectype. If the type specifier |
| 14629 | is given after register operand, the information is stored |
| 14630 | in inst.operands[].vectype. |
| 14631 | |
| 14632 | When there is only one type specifier, and all the register |
| 14633 | operands are the same type of hardware register, the type |
| 14634 | specifier applies to all register operands. |
| 14635 | |
| 14636 | If no type specifier is given, the shape is inferred from |
| 14637 | operand information. |
| 14638 | |
| 14639 | for example: |
| 14640 | vadd.f16 s0, s1, s2: NS_HHH |
| 14641 | vabs.f16 s0, s1: NS_HH |
| 14642 | vmov.f16 s0, r1: NS_HR |
| 14643 | vmov.f16 r0, s1: NS_RH |
| 14644 | vcvt.f16 r0, s1: NS_RH |
| 14645 | vcvt.f16.s32 s2, s2, #29: NS_HFI |
| 14646 | vcvt.f16.s32 s2, s2: NS_HF |
| 14647 | */ |
| 14648 | case SE_H: |
| 14649 | if (!(inst.operands[j].isreg |
| 14650 | && inst.operands[j].isvec |
| 14651 | && inst.operands[j].issingle |
| 14652 | && !inst.operands[j].isquad |
| 14653 | && ((inst.vectype.elems == 1 |
| 14654 | && inst.vectype.el[0].size == 16) |
| 14655 | || (inst.vectype.elems > 1 |
| 14656 | && inst.vectype.el[j].size == 16) |
| 14657 | || (inst.vectype.elems == 0 |
| 14658 | && inst.operands[j].vectype.type != NT_invtype |
| 14659 | && inst.operands[j].vectype.size == 16)))) |
| 14660 | matches = 0; |
| 14661 | break; |
| 14662 | |
| 14663 | case SE_F: |
| 14664 | if (!(inst.operands[j].isreg |
| 14665 | && inst.operands[j].isvec |
| 14666 | && inst.operands[j].issingle |
| 14667 | && !inst.operands[j].isquad |
| 14668 | && ((inst.vectype.elems == 1 && inst.vectype.el[0].size == 32) |
| 14669 | || (inst.vectype.elems > 1 && inst.vectype.el[j].size == 32) |
| 14670 | || (inst.vectype.elems == 0 |
| 14671 | && (inst.operands[j].vectype.size == 32 |
| 14672 | || inst.operands[j].vectype.type == NT_invtype))))) |
| 14673 | matches = 0; |
| 14674 | break; |
| 14675 | |
| 14676 | case SE_D: |
| 14677 | if (!(inst.operands[j].isreg |
| 14678 | && inst.operands[j].isvec |
| 14679 | && !inst.operands[j].isquad |
| 14680 | && !inst.operands[j].issingle)) |
| 14681 | matches = 0; |
| 14682 | break; |
| 14683 | |
| 14684 | case SE_R: |
| 14685 | if (!(inst.operands[j].isreg |
| 14686 | && !inst.operands[j].isvec)) |
| 14687 | matches = 0; |
| 14688 | break; |
| 14689 | |
| 14690 | case SE_Q: |
| 14691 | if (!(inst.operands[j].isreg |
| 14692 | && inst.operands[j].isvec |
| 14693 | && inst.operands[j].isquad |
| 14694 | && !inst.operands[j].issingle)) |
| 14695 | matches = 0; |
| 14696 | break; |
| 14697 | |
| 14698 | case SE_I: |
| 14699 | if (!(!inst.operands[j].isreg |
| 14700 | && !inst.operands[j].isscalar)) |
| 14701 | matches = 0; |
| 14702 | break; |
| 14703 | |
| 14704 | case SE_S: |
| 14705 | if (!(!inst.operands[j].isreg |
| 14706 | && inst.operands[j].isscalar)) |
| 14707 | matches = 0; |
| 14708 | break; |
| 14709 | |
| 14710 | case SE_L: |
| 14711 | break; |
| 14712 | } |
| 14713 | if (!matches) |
| 14714 | break; |
| 14715 | } |
| 14716 | if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present)) |
| 14717 | /* We've matched all the entries in the shape table, and we don't |
| 14718 | have any left over operands which have not been matched. */ |
| 14719 | break; |
| 14720 | } |
| 14721 | |
| 14722 | va_end (ap); |
| 14723 | |
| 14724 | if (shape == NS_NULL && first_shape != NS_NULL) |
| 14725 | first_error (_("invalid instruction shape")); |
| 14726 | |
| 14727 | return shape; |
| 14728 | } |
| 14729 | |
| 14730 | /* True if SHAPE is predominantly a quadword operation (most of the time, this |
| 14731 | means the Q bit should be set). */ |
| 14732 | |
| 14733 | static int |
| 14734 | neon_quad (enum neon_shape shape) |
| 14735 | { |
| 14736 | return neon_shape_class[shape] == SC_QUAD; |
| 14737 | } |
| 14738 | |
| 14739 | static void |
| 14740 | neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, |
| 14741 | unsigned *g_size) |
| 14742 | { |
| 14743 | /* Allow modification to be made to types which are constrained to be |
| 14744 | based on the key element, based on bits set alongside N_EQK. */ |
| 14745 | if ((typebits & N_EQK) != 0) |
| 14746 | { |
| 14747 | if ((typebits & N_HLF) != 0) |
| 14748 | *g_size /= 2; |
| 14749 | else if ((typebits & N_DBL) != 0) |
| 14750 | *g_size *= 2; |
| 14751 | if ((typebits & N_SGN) != 0) |
| 14752 | *g_type = NT_signed; |
| 14753 | else if ((typebits & N_UNS) != 0) |
| 14754 | *g_type = NT_unsigned; |
| 14755 | else if ((typebits & N_INT) != 0) |
| 14756 | *g_type = NT_integer; |
| 14757 | else if ((typebits & N_FLT) != 0) |
| 14758 | *g_type = NT_float; |
| 14759 | else if ((typebits & N_SIZ) != 0) |
| 14760 | *g_type = NT_untyped; |
| 14761 | } |
| 14762 | } |
| 14763 | |
| 14764 | /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" |
| 14765 | operand type, i.e. the single type specified in a Neon instruction when it |
| 14766 | is the only one given. */ |
| 14767 | |
| 14768 | static struct neon_type_el |
| 14769 | neon_type_promote (struct neon_type_el *key, unsigned thisarg) |
| 14770 | { |
| 14771 | struct neon_type_el dest = *key; |
| 14772 | |
| 14773 | gas_assert ((thisarg & N_EQK) != 0); |
| 14774 | |
| 14775 | neon_modify_type_size (thisarg, &dest.type, &dest.size); |
| 14776 | |
| 14777 | return dest; |
| 14778 | } |
| 14779 | |
| 14780 | /* Convert Neon type and size into compact bitmask representation. */ |
| 14781 | |
| 14782 | static enum neon_type_mask |
| 14783 | type_chk_of_el_type (enum neon_el_type type, unsigned size) |
| 14784 | { |
| 14785 | switch (type) |
| 14786 | { |
| 14787 | case NT_untyped: |
| 14788 | switch (size) |
| 14789 | { |
| 14790 | case 8: return N_8; |
| 14791 | case 16: return N_16; |
| 14792 | case 32: return N_32; |
| 14793 | case 64: return N_64; |
| 14794 | default: ; |
| 14795 | } |
| 14796 | break; |
| 14797 | |
| 14798 | case NT_integer: |
| 14799 | switch (size) |
| 14800 | { |
| 14801 | case 8: return N_I8; |
| 14802 | case 16: return N_I16; |
| 14803 | case 32: return N_I32; |
| 14804 | case 64: return N_I64; |
| 14805 | default: ; |
| 14806 | } |
| 14807 | break; |
| 14808 | |
| 14809 | case NT_float: |
| 14810 | switch (size) |
| 14811 | { |
| 14812 | case 16: return N_F16; |
| 14813 | case 32: return N_F32; |
| 14814 | case 64: return N_F64; |
| 14815 | default: ; |
| 14816 | } |
| 14817 | break; |
| 14818 | |
| 14819 | case NT_poly: |
| 14820 | switch (size) |
| 14821 | { |
| 14822 | case 8: return N_P8; |
| 14823 | case 16: return N_P16; |
| 14824 | case 64: return N_P64; |
| 14825 | default: ; |
| 14826 | } |
| 14827 | break; |
| 14828 | |
| 14829 | case NT_signed: |
| 14830 | switch (size) |
| 14831 | { |
| 14832 | case 8: return N_S8; |
| 14833 | case 16: return N_S16; |
| 14834 | case 32: return N_S32; |
| 14835 | case 64: return N_S64; |
| 14836 | default: ; |
| 14837 | } |
| 14838 | break; |
| 14839 | |
| 14840 | case NT_unsigned: |
| 14841 | switch (size) |
| 14842 | { |
| 14843 | case 8: return N_U8; |
| 14844 | case 16: return N_U16; |
| 14845 | case 32: return N_U32; |
| 14846 | case 64: return N_U64; |
| 14847 | default: ; |
| 14848 | } |
| 14849 | break; |
| 14850 | |
| 14851 | default: ; |
| 14852 | } |
| 14853 | |
| 14854 | return N_UTYP; |
| 14855 | } |
| 14856 | |
| 14857 | /* Convert compact Neon bitmask type representation to a type and size. Only |
| 14858 | handles the case where a single bit is set in the mask. */ |
| 14859 | |
| 14860 | static int |
| 14861 | el_type_of_type_chk (enum neon_el_type *type, unsigned *size, |
| 14862 | enum neon_type_mask mask) |
| 14863 | { |
| 14864 | if ((mask & N_EQK) != 0) |
| 14865 | return FAIL; |
| 14866 | |
| 14867 | if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) |
| 14868 | *size = 8; |
| 14869 | else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0) |
| 14870 | *size = 16; |
| 14871 | else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) |
| 14872 | *size = 32; |
| 14873 | else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0) |
| 14874 | *size = 64; |
| 14875 | else |
| 14876 | return FAIL; |
| 14877 | |
| 14878 | if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) |
| 14879 | *type = NT_signed; |
| 14880 | else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) |
| 14881 | *type = NT_unsigned; |
| 14882 | else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) |
| 14883 | *type = NT_integer; |
| 14884 | else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) |
| 14885 | *type = NT_untyped; |
| 14886 | else if ((mask & (N_P8 | N_P16 | N_P64)) != 0) |
| 14887 | *type = NT_poly; |
| 14888 | else if ((mask & (N_F_ALL)) != 0) |
| 14889 | *type = NT_float; |
| 14890 | else |
| 14891 | return FAIL; |
| 14892 | |
| 14893 | return SUCCESS; |
| 14894 | } |
| 14895 | |
| 14896 | /* Modify a bitmask of allowed types. This is only needed for type |
| 14897 | relaxation. */ |
| 14898 | |
| 14899 | static unsigned |
| 14900 | modify_types_allowed (unsigned allowed, unsigned mods) |
| 14901 | { |
| 14902 | unsigned size; |
| 14903 | enum neon_el_type type; |
| 14904 | unsigned destmask; |
| 14905 | int i; |
| 14906 | |
| 14907 | destmask = 0; |
| 14908 | |
| 14909 | for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) |
| 14910 | { |
| 14911 | if (el_type_of_type_chk (&type, &size, |
| 14912 | (enum neon_type_mask) (allowed & i)) == SUCCESS) |
| 14913 | { |
| 14914 | neon_modify_type_size (mods, &type, &size); |
| 14915 | destmask |= type_chk_of_el_type (type, size); |
| 14916 | } |
| 14917 | } |
| 14918 | |
| 14919 | return destmask; |
| 14920 | } |
| 14921 | |
| 14922 | /* Check type and return type classification. |
| 14923 | The manual states (paraphrase): If one datatype is given, it indicates the |
| 14924 | type given in: |
| 14925 | - the second operand, if there is one |
| 14926 | - the operand, if there is no second operand |
| 14927 | - the result, if there are no operands. |
| 14928 | This isn't quite good enough though, so we use a concept of a "key" datatype |
| 14929 | which is set on a per-instruction basis, which is the one which matters when |
| 14930 | only one data type is written. |
| 14931 | Note: this function has side-effects (e.g. filling in missing operands). All |
| 14932 | Neon instructions should call it before performing bit encoding. */ |
| 14933 | |
| 14934 | static struct neon_type_el |
| 14935 | neon_check_type (unsigned els, enum neon_shape ns, ...) |
| 14936 | { |
| 14937 | va_list ap; |
| 14938 | unsigned i, pass, key_el = 0; |
| 14939 | unsigned types[NEON_MAX_TYPE_ELS]; |
| 14940 | enum neon_el_type k_type = NT_invtype; |
| 14941 | unsigned k_size = -1u; |
| 14942 | struct neon_type_el badtype = {NT_invtype, -1}; |
| 14943 | unsigned key_allowed = 0; |
| 14944 | |
| 14945 | /* Optional registers in Neon instructions are always (not) in operand 1. |
| 14946 | Fill in the missing operand here, if it was omitted. */ |
| 14947 | if (els > 1 && !inst.operands[1].present) |
| 14948 | inst.operands[1] = inst.operands[0]; |
| 14949 | |
| 14950 | /* Suck up all the varargs. */ |
| 14951 | va_start (ap, ns); |
| 14952 | for (i = 0; i < els; i++) |
| 14953 | { |
| 14954 | unsigned thisarg = va_arg (ap, unsigned); |
| 14955 | if (thisarg == N_IGNORE_TYPE) |
| 14956 | { |
| 14957 | va_end (ap); |
| 14958 | return badtype; |
| 14959 | } |
| 14960 | types[i] = thisarg; |
| 14961 | if ((thisarg & N_KEY) != 0) |
| 14962 | key_el = i; |
| 14963 | } |
| 14964 | va_end (ap); |
| 14965 | |
| 14966 | if (inst.vectype.elems > 0) |
| 14967 | for (i = 0; i < els; i++) |
| 14968 | if (inst.operands[i].vectype.type != NT_invtype) |
| 14969 | { |
| 14970 | first_error (_("types specified in both the mnemonic and operands")); |
| 14971 | return badtype; |
| 14972 | } |
| 14973 | |
| 14974 | /* Duplicate inst.vectype elements here as necessary. |
| 14975 | FIXME: No idea if this is exactly the same as the ARM assembler, |
| 14976 | particularly when an insn takes one register and one non-register |
| 14977 | operand. */ |
| 14978 | if (inst.vectype.elems == 1 && els > 1) |
| 14979 | { |
| 14980 | unsigned j; |
| 14981 | inst.vectype.elems = els; |
| 14982 | inst.vectype.el[key_el] = inst.vectype.el[0]; |
| 14983 | for (j = 0; j < els; j++) |
| 14984 | if (j != key_el) |
| 14985 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], |
| 14986 | types[j]); |
| 14987 | } |
| 14988 | else if (inst.vectype.elems == 0 && els > 0) |
| 14989 | { |
| 14990 | unsigned j; |
| 14991 | /* No types were given after the mnemonic, so look for types specified |
| 14992 | after each operand. We allow some flexibility here; as long as the |
| 14993 | "key" operand has a type, we can infer the others. */ |
| 14994 | for (j = 0; j < els; j++) |
| 14995 | if (inst.operands[j].vectype.type != NT_invtype) |
| 14996 | inst.vectype.el[j] = inst.operands[j].vectype; |
| 14997 | |
| 14998 | if (inst.operands[key_el].vectype.type != NT_invtype) |
| 14999 | { |
| 15000 | for (j = 0; j < els; j++) |
| 15001 | if (inst.operands[j].vectype.type == NT_invtype) |
| 15002 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], |
| 15003 | types[j]); |
| 15004 | } |
| 15005 | else |
| 15006 | { |
| 15007 | first_error (_("operand types can't be inferred")); |
| 15008 | return badtype; |
| 15009 | } |
| 15010 | } |
| 15011 | else if (inst.vectype.elems != els) |
| 15012 | { |
| 15013 | first_error (_("type specifier has the wrong number of parts")); |
| 15014 | return badtype; |
| 15015 | } |
| 15016 | |
| 15017 | for (pass = 0; pass < 2; pass++) |
| 15018 | { |
| 15019 | for (i = 0; i < els; i++) |
| 15020 | { |
| 15021 | unsigned thisarg = types[i]; |
| 15022 | unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) |
| 15023 | ? modify_types_allowed (key_allowed, thisarg) : thisarg; |
| 15024 | enum neon_el_type g_type = inst.vectype.el[i].type; |
| 15025 | unsigned g_size = inst.vectype.el[i].size; |
| 15026 | |
| 15027 | /* Decay more-specific signed & unsigned types to sign-insensitive |
| 15028 | integer types if sign-specific variants are unavailable. */ |
| 15029 | if ((g_type == NT_signed || g_type == NT_unsigned) |
| 15030 | && (types_allowed & N_SU_ALL) == 0) |
| 15031 | g_type = NT_integer; |
| 15032 | |
| 15033 | /* If only untyped args are allowed, decay any more specific types to |
| 15034 | them. Some instructions only care about signs for some element |
| 15035 | sizes, so handle that properly. */ |
| 15036 | if (((types_allowed & N_UNT) == 0) |
| 15037 | && ((g_size == 8 && (types_allowed & N_8) != 0) |
| 15038 | || (g_size == 16 && (types_allowed & N_16) != 0) |
| 15039 | || (g_size == 32 && (types_allowed & N_32) != 0) |
| 15040 | || (g_size == 64 && (types_allowed & N_64) != 0))) |
| 15041 | g_type = NT_untyped; |
| 15042 | |
| 15043 | if (pass == 0) |
| 15044 | { |
| 15045 | if ((thisarg & N_KEY) != 0) |
| 15046 | { |
| 15047 | k_type = g_type; |
| 15048 | k_size = g_size; |
| 15049 | key_allowed = thisarg & ~N_KEY; |
| 15050 | |
| 15051 | /* Check architecture constraint on FP16 extension. */ |
| 15052 | if (k_size == 16 |
| 15053 | && k_type == NT_float |
| 15054 | && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16)) |
| 15055 | { |
| 15056 | inst.error = _(BAD_FP16); |
| 15057 | return badtype; |
| 15058 | } |
| 15059 | } |
| 15060 | } |
| 15061 | else |
| 15062 | { |
| 15063 | if ((thisarg & N_VFP) != 0) |
| 15064 | { |
| 15065 | enum neon_shape_el regshape; |
| 15066 | unsigned regwidth, match; |
| 15067 | |
| 15068 | /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */ |
| 15069 | if (ns == NS_NULL) |
| 15070 | { |
| 15071 | first_error (_("invalid instruction shape")); |
| 15072 | return badtype; |
| 15073 | } |
| 15074 | regshape = neon_shape_tab[ns].el[i]; |
| 15075 | regwidth = neon_shape_el_size[regshape]; |
| 15076 | |
| 15077 | /* In VFP mode, operands must match register widths. If we |
| 15078 | have a key operand, use its width, else use the width of |
| 15079 | the current operand. */ |
| 15080 | if (k_size != -1u) |
| 15081 | match = k_size; |
| 15082 | else |
| 15083 | match = g_size; |
| 15084 | |
| 15085 | /* FP16 will use a single precision register. */ |
| 15086 | if (regwidth == 32 && match == 16) |
| 15087 | { |
| 15088 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16)) |
| 15089 | match = regwidth; |
| 15090 | else |
| 15091 | { |
| 15092 | inst.error = _(BAD_FP16); |
| 15093 | return badtype; |
| 15094 | } |
| 15095 | } |
| 15096 | |
| 15097 | if (regwidth != match) |
| 15098 | { |
| 15099 | first_error (_("operand size must match register width")); |
| 15100 | return badtype; |
| 15101 | } |
| 15102 | } |
| 15103 | |
| 15104 | if ((thisarg & N_EQK) == 0) |
| 15105 | { |
| 15106 | unsigned given_type = type_chk_of_el_type (g_type, g_size); |
| 15107 | |
| 15108 | if ((given_type & types_allowed) == 0) |
| 15109 | { |
| 15110 | first_error (BAD_SIMD_TYPE); |
| 15111 | return badtype; |
| 15112 | } |
| 15113 | } |
| 15114 | else |
| 15115 | { |
| 15116 | enum neon_el_type mod_k_type = k_type; |
| 15117 | unsigned mod_k_size = k_size; |
| 15118 | neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); |
| 15119 | if (g_type != mod_k_type || g_size != mod_k_size) |
| 15120 | { |
| 15121 | first_error (_("inconsistent types in Neon instruction")); |
| 15122 | return badtype; |
| 15123 | } |
| 15124 | } |
| 15125 | } |
| 15126 | } |
| 15127 | } |
| 15128 | |
| 15129 | return inst.vectype.el[key_el]; |
| 15130 | } |
| 15131 | |
| 15132 | /* Neon-style VFP instruction forwarding. */ |
| 15133 | |
| 15134 | /* Thumb VFP instructions have 0xE in the condition field. */ |
| 15135 | |
| 15136 | static void |
| 15137 | do_vfp_cond_or_thumb (void) |
| 15138 | { |
| 15139 | inst.is_neon = 1; |
| 15140 | |
| 15141 | if (thumb_mode) |
| 15142 | inst.instruction |= 0xe0000000; |
| 15143 | else |
| 15144 | inst.instruction |= inst.cond << 28; |
| 15145 | } |
| 15146 | |
| 15147 | /* Look up and encode a simple mnemonic, for use as a helper function for the |
| 15148 | Neon-style VFP syntax. This avoids duplication of bits of the insns table, |
| 15149 | etc. It is assumed that operand parsing has already been done, and that the |
| 15150 | operands are in the form expected by the given opcode (this isn't necessarily |
| 15151 | the same as the form in which they were parsed, hence some massaging must |
| 15152 | take place before this function is called). |
| 15153 | Checks current arch version against that in the looked-up opcode. */ |
| 15154 | |
| 15155 | static void |
| 15156 | do_vfp_nsyn_opcode (const char *opname) |
| 15157 | { |
| 15158 | const struct asm_opcode *opcode; |
| 15159 | |
| 15160 | opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname); |
| 15161 | |
| 15162 | if (!opcode) |
| 15163 | abort (); |
| 15164 | |
| 15165 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, |
| 15166 | thumb_mode ? *opcode->tvariant : *opcode->avariant), |
| 15167 | _(BAD_FPU)); |
| 15168 | |
| 15169 | inst.is_neon = 1; |
| 15170 | |
| 15171 | if (thumb_mode) |
| 15172 | { |
| 15173 | inst.instruction = opcode->tvalue; |
| 15174 | opcode->tencode (); |
| 15175 | } |
| 15176 | else |
| 15177 | { |
| 15178 | inst.instruction = (inst.cond << 28) | opcode->avalue; |
| 15179 | opcode->aencode (); |
| 15180 | } |
| 15181 | } |
| 15182 | |
| 15183 | static void |
| 15184 | do_vfp_nsyn_add_sub (enum neon_shape rs) |
| 15185 | { |
| 15186 | int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; |
| 15187 | |
| 15188 | if (rs == NS_FFF || rs == NS_HHH) |
| 15189 | { |
| 15190 | if (is_add) |
| 15191 | do_vfp_nsyn_opcode ("fadds"); |
| 15192 | else |
| 15193 | do_vfp_nsyn_opcode ("fsubs"); |
| 15194 | |
| 15195 | /* ARMv8.2 fp16 instruction. */ |
| 15196 | if (rs == NS_HHH) |
| 15197 | do_scalar_fp16_v82_encode (); |
| 15198 | } |
| 15199 | else |
| 15200 | { |
| 15201 | if (is_add) |
| 15202 | do_vfp_nsyn_opcode ("faddd"); |
| 15203 | else |
| 15204 | do_vfp_nsyn_opcode ("fsubd"); |
| 15205 | } |
| 15206 | } |
| 15207 | |
| 15208 | /* Check operand types to see if this is a VFP instruction, and if so call |
| 15209 | PFN (). */ |
| 15210 | |
| 15211 | static int |
| 15212 | try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) |
| 15213 | { |
| 15214 | enum neon_shape rs; |
| 15215 | struct neon_type_el et; |
| 15216 | |
| 15217 | switch (args) |
| 15218 | { |
| 15219 | case 2: |
| 15220 | rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL); |
| 15221 | et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP); |
| 15222 | break; |
| 15223 | |
| 15224 | case 3: |
| 15225 | rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL); |
| 15226 | et = neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, |
| 15227 | N_F_ALL | N_KEY | N_VFP); |
| 15228 | break; |
| 15229 | |
| 15230 | default: |
| 15231 | abort (); |
| 15232 | } |
| 15233 | |
| 15234 | if (et.type != NT_invtype) |
| 15235 | { |
| 15236 | pfn (rs); |
| 15237 | return SUCCESS; |
| 15238 | } |
| 15239 | |
| 15240 | inst.error = NULL; |
| 15241 | return FAIL; |
| 15242 | } |
| 15243 | |
| 15244 | static void |
| 15245 | do_vfp_nsyn_mla_mls (enum neon_shape rs) |
| 15246 | { |
| 15247 | int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; |
| 15248 | |
| 15249 | if (rs == NS_FFF || rs == NS_HHH) |
| 15250 | { |
| 15251 | if (is_mla) |
| 15252 | do_vfp_nsyn_opcode ("fmacs"); |
| 15253 | else |
| 15254 | do_vfp_nsyn_opcode ("fnmacs"); |
| 15255 | |
| 15256 | /* ARMv8.2 fp16 instruction. */ |
| 15257 | if (rs == NS_HHH) |
| 15258 | do_scalar_fp16_v82_encode (); |
| 15259 | } |
| 15260 | else |
| 15261 | { |
| 15262 | if (is_mla) |
| 15263 | do_vfp_nsyn_opcode ("fmacd"); |
| 15264 | else |
| 15265 | do_vfp_nsyn_opcode ("fnmacd"); |
| 15266 | } |
| 15267 | } |
| 15268 | |
| 15269 | static void |
| 15270 | do_vfp_nsyn_fma_fms (enum neon_shape rs) |
| 15271 | { |
| 15272 | int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma; |
| 15273 | |
| 15274 | if (rs == NS_FFF || rs == NS_HHH) |
| 15275 | { |
| 15276 | if (is_fma) |
| 15277 | do_vfp_nsyn_opcode ("ffmas"); |
| 15278 | else |
| 15279 | do_vfp_nsyn_opcode ("ffnmas"); |
| 15280 | |
| 15281 | /* ARMv8.2 fp16 instruction. */ |
| 15282 | if (rs == NS_HHH) |
| 15283 | do_scalar_fp16_v82_encode (); |
| 15284 | } |
| 15285 | else |
| 15286 | { |
| 15287 | if (is_fma) |
| 15288 | do_vfp_nsyn_opcode ("ffmad"); |
| 15289 | else |
| 15290 | do_vfp_nsyn_opcode ("ffnmad"); |
| 15291 | } |
| 15292 | } |
| 15293 | |
| 15294 | static void |
| 15295 | do_vfp_nsyn_mul (enum neon_shape rs) |
| 15296 | { |
| 15297 | if (rs == NS_FFF || rs == NS_HHH) |
| 15298 | { |
| 15299 | do_vfp_nsyn_opcode ("fmuls"); |
| 15300 | |
| 15301 | /* ARMv8.2 fp16 instruction. */ |
| 15302 | if (rs == NS_HHH) |
| 15303 | do_scalar_fp16_v82_encode (); |
| 15304 | } |
| 15305 | else |
| 15306 | do_vfp_nsyn_opcode ("fmuld"); |
| 15307 | } |
| 15308 | |
| 15309 | static void |
| 15310 | do_vfp_nsyn_abs_neg (enum neon_shape rs) |
| 15311 | { |
| 15312 | int is_neg = (inst.instruction & 0x80) != 0; |
| 15313 | neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_VFP | N_KEY); |
| 15314 | |
| 15315 | if (rs == NS_FF || rs == NS_HH) |
| 15316 | { |
| 15317 | if (is_neg) |
| 15318 | do_vfp_nsyn_opcode ("fnegs"); |
| 15319 | else |
| 15320 | do_vfp_nsyn_opcode ("fabss"); |
| 15321 | |
| 15322 | /* ARMv8.2 fp16 instruction. */ |
| 15323 | if (rs == NS_HH) |
| 15324 | do_scalar_fp16_v82_encode (); |
| 15325 | } |
| 15326 | else |
| 15327 | { |
| 15328 | if (is_neg) |
| 15329 | do_vfp_nsyn_opcode ("fnegd"); |
| 15330 | else |
| 15331 | do_vfp_nsyn_opcode ("fabsd"); |
| 15332 | } |
| 15333 | } |
| 15334 | |
| 15335 | /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision |
| 15336 | insns belong to Neon, and are handled elsewhere. */ |
| 15337 | |
| 15338 | static void |
| 15339 | do_vfp_nsyn_ldm_stm (int is_dbmode) |
| 15340 | { |
| 15341 | int is_ldm = (inst.instruction & (1 << 20)) != 0; |
| 15342 | if (is_ldm) |
| 15343 | { |
| 15344 | if (is_dbmode) |
| 15345 | do_vfp_nsyn_opcode ("fldmdbs"); |
| 15346 | else |
| 15347 | do_vfp_nsyn_opcode ("fldmias"); |
| 15348 | } |
| 15349 | else |
| 15350 | { |
| 15351 | if (is_dbmode) |
| 15352 | do_vfp_nsyn_opcode ("fstmdbs"); |
| 15353 | else |
| 15354 | do_vfp_nsyn_opcode ("fstmias"); |
| 15355 | } |
| 15356 | } |
| 15357 | |
| 15358 | static void |
| 15359 | do_vfp_nsyn_sqrt (void) |
| 15360 | { |
| 15361 | enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL); |
| 15362 | neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP); |
| 15363 | |
| 15364 | if (rs == NS_FF || rs == NS_HH) |
| 15365 | { |
| 15366 | do_vfp_nsyn_opcode ("fsqrts"); |
| 15367 | |
| 15368 | /* ARMv8.2 fp16 instruction. */ |
| 15369 | if (rs == NS_HH) |
| 15370 | do_scalar_fp16_v82_encode (); |
| 15371 | } |
| 15372 | else |
| 15373 | do_vfp_nsyn_opcode ("fsqrtd"); |
| 15374 | } |
| 15375 | |
| 15376 | static void |
| 15377 | do_vfp_nsyn_div (void) |
| 15378 | { |
| 15379 | enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL); |
| 15380 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, |
| 15381 | N_F_ALL | N_KEY | N_VFP); |
| 15382 | |
| 15383 | if (rs == NS_FFF || rs == NS_HHH) |
| 15384 | { |
| 15385 | do_vfp_nsyn_opcode ("fdivs"); |
| 15386 | |
| 15387 | /* ARMv8.2 fp16 instruction. */ |
| 15388 | if (rs == NS_HHH) |
| 15389 | do_scalar_fp16_v82_encode (); |
| 15390 | } |
| 15391 | else |
| 15392 | do_vfp_nsyn_opcode ("fdivd"); |
| 15393 | } |
| 15394 | |
| 15395 | static void |
| 15396 | do_vfp_nsyn_nmul (void) |
| 15397 | { |
| 15398 | enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL); |
| 15399 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, |
| 15400 | N_F_ALL | N_KEY | N_VFP); |
| 15401 | |
| 15402 | if (rs == NS_FFF || rs == NS_HHH) |
| 15403 | { |
| 15404 | NEON_ENCODE (SINGLE, inst); |
| 15405 | do_vfp_sp_dyadic (); |
| 15406 | |
| 15407 | /* ARMv8.2 fp16 instruction. */ |
| 15408 | if (rs == NS_HHH) |
| 15409 | do_scalar_fp16_v82_encode (); |
| 15410 | } |
| 15411 | else |
| 15412 | { |
| 15413 | NEON_ENCODE (DOUBLE, inst); |
| 15414 | do_vfp_dp_rd_rn_rm (); |
| 15415 | } |
| 15416 | do_vfp_cond_or_thumb (); |
| 15417 | |
| 15418 | } |
| 15419 | |
| 15420 | /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 |
| 15421 | (0, 1, 2, 3). */ |
| 15422 | |
| 15423 | static unsigned |
| 15424 | neon_logbits (unsigned x) |
| 15425 | { |
| 15426 | return ffs (x) - 4; |
| 15427 | } |
| 15428 | |
| 15429 | #define LOW4(R) ((R) & 0xf) |
| 15430 | #define HI1(R) (((R) >> 4) & 1) |
| 15431 | |
| 15432 | static unsigned |
| 15433 | mve_get_vcmp_vpt_cond (struct neon_type_el et) |
| 15434 | { |
| 15435 | switch (et.type) |
| 15436 | { |
| 15437 | default: |
| 15438 | first_error (BAD_EL_TYPE); |
| 15439 | return 0; |
| 15440 | case NT_float: |
| 15441 | switch (inst.operands[0].imm) |
| 15442 | { |
| 15443 | default: |
| 15444 | first_error (_("invalid condition")); |
| 15445 | return 0; |
| 15446 | case 0x0: |
| 15447 | /* eq. */ |
| 15448 | return 0; |
| 15449 | case 0x1: |
| 15450 | /* ne. */ |
| 15451 | return 1; |
| 15452 | case 0xa: |
| 15453 | /* ge/ */ |
| 15454 | return 4; |
| 15455 | case 0xb: |
| 15456 | /* lt. */ |
| 15457 | return 5; |
| 15458 | case 0xc: |
| 15459 | /* gt. */ |
| 15460 | return 6; |
| 15461 | case 0xd: |
| 15462 | /* le. */ |
| 15463 | return 7; |
| 15464 | } |
| 15465 | case NT_integer: |
| 15466 | /* only accept eq and ne. */ |
| 15467 | if (inst.operands[0].imm > 1) |
| 15468 | { |
| 15469 | first_error (_("invalid condition")); |
| 15470 | return 0; |
| 15471 | } |
| 15472 | return inst.operands[0].imm; |
| 15473 | case NT_unsigned: |
| 15474 | if (inst.operands[0].imm == 0x2) |
| 15475 | return 2; |
| 15476 | else if (inst.operands[0].imm == 0x8) |
| 15477 | return 3; |
| 15478 | else |
| 15479 | { |
| 15480 | first_error (_("invalid condition")); |
| 15481 | return 0; |
| 15482 | } |
| 15483 | case NT_signed: |
| 15484 | switch (inst.operands[0].imm) |
| 15485 | { |
| 15486 | default: |
| 15487 | first_error (_("invalid condition")); |
| 15488 | return 0; |
| 15489 | case 0xa: |
| 15490 | /* ge. */ |
| 15491 | return 4; |
| 15492 | case 0xb: |
| 15493 | /* lt. */ |
| 15494 | return 5; |
| 15495 | case 0xc: |
| 15496 | /* gt. */ |
| 15497 | return 6; |
| 15498 | case 0xd: |
| 15499 | /* le. */ |
| 15500 | return 7; |
| 15501 | } |
| 15502 | } |
| 15503 | /* Should be unreachable. */ |
| 15504 | abort (); |
| 15505 | } |
| 15506 | |
| 15507 | static void |
| 15508 | do_mve_vpt (void) |
| 15509 | { |
| 15510 | /* We are dealing with a vector predicated block. */ |
| 15511 | if (inst.operands[0].present) |
| 15512 | { |
| 15513 | enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL); |
| 15514 | struct neon_type_el et |
| 15515 | = neon_check_type (3, rs, N_EQK, N_KEY | N_F_MVE | N_I_MVE | N_SU_32, |
| 15516 | N_EQK); |
| 15517 | |
| 15518 | unsigned fcond = mve_get_vcmp_vpt_cond (et); |
| 15519 | |
| 15520 | constraint (inst.operands[1].reg > 14, MVE_BAD_QREG); |
| 15521 | |
| 15522 | if (et.type == NT_invtype) |
| 15523 | return; |
| 15524 | |
| 15525 | if (et.type == NT_float) |
| 15526 | { |
| 15527 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext), |
| 15528 | BAD_FPU); |
| 15529 | constraint (et.size != 16 && et.size != 32, BAD_EL_TYPE); |
| 15530 | inst.instruction |= (et.size == 16) << 28; |
| 15531 | inst.instruction |= 0x3 << 20; |
| 15532 | } |
| 15533 | else |
| 15534 | { |
| 15535 | constraint (et.size != 8 && et.size != 16 && et.size != 32, |
| 15536 | BAD_EL_TYPE); |
| 15537 | inst.instruction |= 1 << 28; |
| 15538 | inst.instruction |= neon_logbits (et.size) << 20; |
| 15539 | } |
| 15540 | |
| 15541 | if (inst.operands[2].isquad) |
| 15542 | { |
| 15543 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; |
| 15544 | inst.instruction |= LOW4 (inst.operands[2].reg); |
| 15545 | inst.instruction |= (fcond & 0x2) >> 1; |
| 15546 | } |
| 15547 | else |
| 15548 | { |
| 15549 | if (inst.operands[2].reg == REG_SP) |
| 15550 | as_tsktsk (MVE_BAD_SP); |
| 15551 | inst.instruction |= 1 << 6; |
| 15552 | inst.instruction |= (fcond & 0x2) << 4; |
| 15553 | inst.instruction |= inst.operands[2].reg; |
| 15554 | } |
| 15555 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; |
| 15556 | inst.instruction |= (fcond & 0x4) << 10; |
| 15557 | inst.instruction |= (fcond & 0x1) << 7; |
| 15558 | |
| 15559 | } |
| 15560 | set_pred_insn_type (VPT_INSN); |
| 15561 | now_pred.cc = 0; |
| 15562 | now_pred.mask = ((inst.instruction & 0x00400000) >> 19) |
| 15563 | | ((inst.instruction & 0xe000) >> 13); |
| 15564 | now_pred.warn_deprecated = FALSE; |
| 15565 | now_pred.type = VECTOR_PRED; |
| 15566 | inst.is_neon = 1; |
| 15567 | } |
| 15568 | |
| 15569 | static void |
| 15570 | do_mve_vcmp (void) |
| 15571 | { |
| 15572 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); |
| 15573 | if (!inst.operands[1].isreg || !inst.operands[1].isquad) |
| 15574 | first_error (_(reg_expected_msgs[REG_TYPE_MQ])); |
| 15575 | if (!inst.operands[2].present) |
| 15576 | first_error (_("MVE vector or ARM register expected")); |
| 15577 | constraint (inst.operands[1].reg > 14, MVE_BAD_QREG); |
| 15578 | |
| 15579 | /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */ |
| 15580 | if ((inst.instruction & 0xffffffff) == N_MNEM_vcmpe |
| 15581 | && inst.operands[1].isquad) |
| 15582 | { |
| 15583 | inst.instruction = N_MNEM_vcmp; |
| 15584 | inst.cond = 0x10; |
| 15585 | } |
| 15586 | |
| 15587 | if (inst.cond > COND_ALWAYS) |
| 15588 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 15589 | else |
| 15590 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 15591 | |
| 15592 | enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL); |
| 15593 | struct neon_type_el et |
| 15594 | = neon_check_type (3, rs, N_EQK, N_KEY | N_F_MVE | N_I_MVE | N_SU_32, |
| 15595 | N_EQK); |
| 15596 | |
| 15597 | constraint (rs == NS_IQR && inst.operands[2].reg == REG_PC |
| 15598 | && !inst.operands[2].iszr, BAD_PC); |
| 15599 | |
| 15600 | unsigned fcond = mve_get_vcmp_vpt_cond (et); |
| 15601 | |
| 15602 | inst.instruction = 0xee010f00; |
| 15603 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; |
| 15604 | inst.instruction |= (fcond & 0x4) << 10; |
| 15605 | inst.instruction |= (fcond & 0x1) << 7; |
| 15606 | if (et.type == NT_float) |
| 15607 | { |
| 15608 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext), |
| 15609 | BAD_FPU); |
| 15610 | inst.instruction |= (et.size == 16) << 28; |
| 15611 | inst.instruction |= 0x3 << 20; |
| 15612 | } |
| 15613 | else |
| 15614 | { |
| 15615 | inst.instruction |= 1 << 28; |
| 15616 | inst.instruction |= neon_logbits (et.size) << 20; |
| 15617 | } |
| 15618 | if (inst.operands[2].isquad) |
| 15619 | { |
| 15620 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; |
| 15621 | inst.instruction |= (fcond & 0x2) >> 1; |
| 15622 | inst.instruction |= LOW4 (inst.operands[2].reg); |
| 15623 | } |
| 15624 | else |
| 15625 | { |
| 15626 | if (inst.operands[2].reg == REG_SP) |
| 15627 | as_tsktsk (MVE_BAD_SP); |
| 15628 | inst.instruction |= 1 << 6; |
| 15629 | inst.instruction |= (fcond & 0x2) << 4; |
| 15630 | inst.instruction |= inst.operands[2].reg; |
| 15631 | } |
| 15632 | |
| 15633 | inst.is_neon = 1; |
| 15634 | return; |
| 15635 | } |
| 15636 | |
| 15637 | static void |
| 15638 | do_mve_vmaxa_vmina (void) |
| 15639 | { |
| 15640 | if (inst.cond > COND_ALWAYS) |
| 15641 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 15642 | else |
| 15643 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 15644 | |
| 15645 | enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL); |
| 15646 | struct neon_type_el et |
| 15647 | = neon_check_type (2, rs, N_EQK, N_KEY | N_S8 | N_S16 | N_S32); |
| 15648 | |
| 15649 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 15650 | inst.instruction |= neon_logbits (et.size) << 18; |
| 15651 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 15652 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; |
| 15653 | inst.instruction |= LOW4 (inst.operands[1].reg); |
| 15654 | inst.is_neon = 1; |
| 15655 | } |
| 15656 | |
| 15657 | static void |
| 15658 | do_mve_vfmas (void) |
| 15659 | { |
| 15660 | enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); |
| 15661 | struct neon_type_el et |
| 15662 | = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK, N_EQK); |
| 15663 | |
| 15664 | if (inst.cond > COND_ALWAYS) |
| 15665 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 15666 | else |
| 15667 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 15668 | |
| 15669 | if (inst.operands[2].reg == REG_SP) |
| 15670 | as_tsktsk (MVE_BAD_SP); |
| 15671 | else if (inst.operands[2].reg == REG_PC) |
| 15672 | as_tsktsk (MVE_BAD_PC); |
| 15673 | |
| 15674 | inst.instruction |= (et.size == 16) << 28; |
| 15675 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 15676 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; |
| 15677 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 15678 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; |
| 15679 | inst.instruction |= inst.operands[2].reg; |
| 15680 | inst.is_neon = 1; |
| 15681 | } |
| 15682 | |
| 15683 | static void |
| 15684 | do_mve_viddup (void) |
| 15685 | { |
| 15686 | if (inst.cond > COND_ALWAYS) |
| 15687 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 15688 | else |
| 15689 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 15690 | |
| 15691 | unsigned imm = inst.relocs[0].exp.X_add_number; |
| 15692 | constraint (imm != 1 && imm != 2 && imm != 4 && imm != 8, |
| 15693 | _("immediate must be either 1, 2, 4 or 8")); |
| 15694 | |
| 15695 | enum neon_shape rs; |
| 15696 | struct neon_type_el et; |
| 15697 | unsigned Rm; |
| 15698 | if (inst.instruction == M_MNEM_vddup || inst.instruction == M_MNEM_vidup) |
| 15699 | { |
| 15700 | rs = neon_select_shape (NS_QRI, NS_NULL); |
| 15701 | et = neon_check_type (2, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK); |
| 15702 | Rm = 7; |
| 15703 | } |
| 15704 | else |
| 15705 | { |
| 15706 | constraint ((inst.operands[2].reg % 2) != 1, BAD_EVEN); |
| 15707 | if (inst.operands[2].reg == REG_SP) |
| 15708 | as_tsktsk (MVE_BAD_SP); |
| 15709 | else if (inst.operands[2].reg == REG_PC) |
| 15710 | first_error (BAD_PC); |
| 15711 | |
| 15712 | rs = neon_select_shape (NS_QRRI, NS_NULL); |
| 15713 | et = neon_check_type (3, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK, N_EQK); |
| 15714 | Rm = inst.operands[2].reg >> 1; |
| 15715 | } |
| 15716 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 15717 | inst.instruction |= neon_logbits (et.size) << 20; |
| 15718 | inst.instruction |= inst.operands[1].reg << 16; |
| 15719 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 15720 | inst.instruction |= (imm > 2) << 7; |
| 15721 | inst.instruction |= Rm << 1; |
| 15722 | inst.instruction |= (imm == 2 || imm == 8); |
| 15723 | inst.is_neon = 1; |
| 15724 | } |
| 15725 | |
| 15726 | static void |
| 15727 | do_mve_vmlas (void) |
| 15728 | { |
| 15729 | enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); |
| 15730 | struct neon_type_el et |
| 15731 | = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY); |
| 15732 | |
| 15733 | if (inst.operands[2].reg == REG_PC) |
| 15734 | as_tsktsk (MVE_BAD_PC); |
| 15735 | else if (inst.operands[2].reg == REG_SP) |
| 15736 | as_tsktsk (MVE_BAD_SP); |
| 15737 | |
| 15738 | if (inst.cond > COND_ALWAYS) |
| 15739 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 15740 | else |
| 15741 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 15742 | |
| 15743 | inst.instruction |= (et.type == NT_unsigned) << 28; |
| 15744 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 15745 | inst.instruction |= neon_logbits (et.size) << 20; |
| 15746 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; |
| 15747 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 15748 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; |
| 15749 | inst.instruction |= inst.operands[2].reg; |
| 15750 | inst.is_neon = 1; |
| 15751 | } |
| 15752 | |
| 15753 | static void |
| 15754 | do_mve_vqmovn (void) |
| 15755 | { |
| 15756 | struct neon_type_el et; |
| 15757 | if (inst.instruction == M_MNEM_vqmovnt |
| 15758 | || inst.instruction == M_MNEM_vqmovnb) |
| 15759 | et = neon_check_type (2, NS_QQ, N_EQK, |
| 15760 | N_U16 | N_U32 | N_S16 | N_S32 | N_KEY); |
| 15761 | else |
| 15762 | et = neon_check_type (2, NS_QQ, N_EQK, N_S16 | N_S32 | N_KEY); |
| 15763 | |
| 15764 | if (inst.cond > COND_ALWAYS) |
| 15765 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 15766 | else |
| 15767 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 15768 | |
| 15769 | inst.instruction |= (et.type == NT_unsigned) << 28; |
| 15770 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 15771 | inst.instruction |= (et.size == 32) << 18; |
| 15772 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 15773 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; |
| 15774 | inst.instruction |= LOW4 (inst.operands[1].reg); |
| 15775 | inst.is_neon = 1; |
| 15776 | } |
| 15777 | |
| 15778 | static void |
| 15779 | do_mve_vpsel (void) |
| 15780 | { |
| 15781 | neon_select_shape (NS_QQQ, NS_NULL); |
| 15782 | |
| 15783 | if (inst.cond > COND_ALWAYS) |
| 15784 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 15785 | else |
| 15786 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 15787 | |
| 15788 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 15789 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; |
| 15790 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 15791 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; |
| 15792 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; |
| 15793 | inst.instruction |= LOW4 (inst.operands[2].reg); |
| 15794 | inst.is_neon = 1; |
| 15795 | } |
| 15796 | |
| 15797 | static void |
| 15798 | do_mve_vpnot (void) |
| 15799 | { |
| 15800 | if (inst.cond > COND_ALWAYS) |
| 15801 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 15802 | else |
| 15803 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 15804 | } |
| 15805 | |
| 15806 | static void |
| 15807 | do_mve_vmaxnma_vminnma (void) |
| 15808 | { |
| 15809 | enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL); |
| 15810 | struct neon_type_el et |
| 15811 | = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY); |
| 15812 | |
| 15813 | if (inst.cond > COND_ALWAYS) |
| 15814 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 15815 | else |
| 15816 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 15817 | |
| 15818 | inst.instruction |= (et.size == 16) << 28; |
| 15819 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 15820 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 15821 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; |
| 15822 | inst.instruction |= LOW4 (inst.operands[1].reg); |
| 15823 | inst.is_neon = 1; |
| 15824 | } |
| 15825 | |
| 15826 | static void |
| 15827 | do_mve_vcmul (void) |
| 15828 | { |
| 15829 | enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL); |
| 15830 | struct neon_type_el et |
| 15831 | = neon_check_type (3, rs, N_EQK, N_EQK, N_F_MVE | N_KEY); |
| 15832 | |
| 15833 | if (inst.cond > COND_ALWAYS) |
| 15834 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 15835 | else |
| 15836 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 15837 | |
| 15838 | unsigned rot = inst.relocs[0].exp.X_add_number; |
| 15839 | constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270, |
| 15840 | _("immediate out of range")); |
| 15841 | |
| 15842 | if (et.size == 32 && (inst.operands[0].reg == inst.operands[1].reg |
| 15843 | || inst.operands[0].reg == inst.operands[2].reg)) |
| 15844 | as_tsktsk (BAD_MVE_SRCDEST); |
| 15845 | |
| 15846 | inst.instruction |= (et.size == 32) << 28; |
| 15847 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 15848 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; |
| 15849 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 15850 | inst.instruction |= (rot > 90) << 12; |
| 15851 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; |
| 15852 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; |
| 15853 | inst.instruction |= LOW4 (inst.operands[2].reg); |
| 15854 | inst.instruction |= (rot == 90 || rot == 270); |
| 15855 | inst.is_neon = 1; |
| 15856 | } |
| 15857 | |
| 15858 | static void |
| 15859 | do_vfp_nsyn_cmp (void) |
| 15860 | { |
| 15861 | enum neon_shape rs; |
| 15862 | if (!inst.operands[0].isreg) |
| 15863 | { |
| 15864 | do_mve_vcmp (); |
| 15865 | return; |
| 15866 | } |
| 15867 | else |
| 15868 | { |
| 15869 | constraint (inst.operands[2].present, BAD_SYNTAX); |
| 15870 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd), |
| 15871 | BAD_FPU); |
| 15872 | } |
| 15873 | |
| 15874 | if (inst.operands[1].isreg) |
| 15875 | { |
| 15876 | rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL); |
| 15877 | neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP); |
| 15878 | |
| 15879 | if (rs == NS_FF || rs == NS_HH) |
| 15880 | { |
| 15881 | NEON_ENCODE (SINGLE, inst); |
| 15882 | do_vfp_sp_monadic (); |
| 15883 | } |
| 15884 | else |
| 15885 | { |
| 15886 | NEON_ENCODE (DOUBLE, inst); |
| 15887 | do_vfp_dp_rd_rm (); |
| 15888 | } |
| 15889 | } |
| 15890 | else |
| 15891 | { |
| 15892 | rs = neon_select_shape (NS_HI, NS_FI, NS_DI, NS_NULL); |
| 15893 | neon_check_type (2, rs, N_F_ALL | N_KEY | N_VFP, N_EQK); |
| 15894 | |
| 15895 | switch (inst.instruction & 0x0fffffff) |
| 15896 | { |
| 15897 | case N_MNEM_vcmp: |
| 15898 | inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; |
| 15899 | break; |
| 15900 | case N_MNEM_vcmpe: |
| 15901 | inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; |
| 15902 | break; |
| 15903 | default: |
| 15904 | abort (); |
| 15905 | } |
| 15906 | |
| 15907 | if (rs == NS_FI || rs == NS_HI) |
| 15908 | { |
| 15909 | NEON_ENCODE (SINGLE, inst); |
| 15910 | do_vfp_sp_compare_z (); |
| 15911 | } |
| 15912 | else |
| 15913 | { |
| 15914 | NEON_ENCODE (DOUBLE, inst); |
| 15915 | do_vfp_dp_rd (); |
| 15916 | } |
| 15917 | } |
| 15918 | do_vfp_cond_or_thumb (); |
| 15919 | |
| 15920 | /* ARMv8.2 fp16 instruction. */ |
| 15921 | if (rs == NS_HI || rs == NS_HH) |
| 15922 | do_scalar_fp16_v82_encode (); |
| 15923 | } |
| 15924 | |
| 15925 | static void |
| 15926 | nsyn_insert_sp (void) |
| 15927 | { |
| 15928 | inst.operands[1] = inst.operands[0]; |
| 15929 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); |
| 15930 | inst.operands[0].reg = REG_SP; |
| 15931 | inst.operands[0].isreg = 1; |
| 15932 | inst.operands[0].writeback = 1; |
| 15933 | inst.operands[0].present = 1; |
| 15934 | } |
| 15935 | |
| 15936 | static void |
| 15937 | do_vfp_nsyn_push (void) |
| 15938 | { |
| 15939 | nsyn_insert_sp (); |
| 15940 | |
| 15941 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, |
| 15942 | _("register list must contain at least 1 and at most 16 " |
| 15943 | "registers")); |
| 15944 | |
| 15945 | if (inst.operands[1].issingle) |
| 15946 | do_vfp_nsyn_opcode ("fstmdbs"); |
| 15947 | else |
| 15948 | do_vfp_nsyn_opcode ("fstmdbd"); |
| 15949 | } |
| 15950 | |
| 15951 | static void |
| 15952 | do_vfp_nsyn_pop (void) |
| 15953 | { |
| 15954 | nsyn_insert_sp (); |
| 15955 | |
| 15956 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, |
| 15957 | _("register list must contain at least 1 and at most 16 " |
| 15958 | "registers")); |
| 15959 | |
| 15960 | if (inst.operands[1].issingle) |
| 15961 | do_vfp_nsyn_opcode ("fldmias"); |
| 15962 | else |
| 15963 | do_vfp_nsyn_opcode ("fldmiad"); |
| 15964 | } |
| 15965 | |
| 15966 | /* Fix up Neon data-processing instructions, ORing in the correct bits for |
| 15967 | ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ |
| 15968 | |
| 15969 | static void |
| 15970 | neon_dp_fixup (struct arm_it* insn) |
| 15971 | { |
| 15972 | unsigned int i = insn->instruction; |
| 15973 | insn->is_neon = 1; |
| 15974 | |
| 15975 | if (thumb_mode) |
| 15976 | { |
| 15977 | /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ |
| 15978 | if (i & (1 << 24)) |
| 15979 | i |= 1 << 28; |
| 15980 | |
| 15981 | i &= ~(1 << 24); |
| 15982 | |
| 15983 | i |= 0xef000000; |
| 15984 | } |
| 15985 | else |
| 15986 | i |= 0xf2000000; |
| 15987 | |
| 15988 | insn->instruction = i; |
| 15989 | } |
| 15990 | |
| 15991 | static void |
| 15992 | mve_encode_qqr (int size, int U, int fp) |
| 15993 | { |
| 15994 | if (inst.operands[2].reg == REG_SP) |
| 15995 | as_tsktsk (MVE_BAD_SP); |
| 15996 | else if (inst.operands[2].reg == REG_PC) |
| 15997 | as_tsktsk (MVE_BAD_PC); |
| 15998 | |
| 15999 | if (fp) |
| 16000 | { |
| 16001 | /* vadd. */ |
| 16002 | if (((unsigned)inst.instruction) == 0xd00) |
| 16003 | inst.instruction = 0xee300f40; |
| 16004 | /* vsub. */ |
| 16005 | else if (((unsigned)inst.instruction) == 0x200d00) |
| 16006 | inst.instruction = 0xee301f40; |
| 16007 | /* vmul. */ |
| 16008 | else if (((unsigned)inst.instruction) == 0x1000d10) |
| 16009 | inst.instruction = 0xee310e60; |
| 16010 | |
| 16011 | /* Setting size which is 1 for F16 and 0 for F32. */ |
| 16012 | inst.instruction |= (size == 16) << 28; |
| 16013 | } |
| 16014 | else |
| 16015 | { |
| 16016 | /* vadd. */ |
| 16017 | if (((unsigned)inst.instruction) == 0x800) |
| 16018 | inst.instruction = 0xee010f40; |
| 16019 | /* vsub. */ |
| 16020 | else if (((unsigned)inst.instruction) == 0x1000800) |
| 16021 | inst.instruction = 0xee011f40; |
| 16022 | /* vhadd. */ |
| 16023 | else if (((unsigned)inst.instruction) == 0) |
| 16024 | inst.instruction = 0xee000f40; |
| 16025 | /* vhsub. */ |
| 16026 | else if (((unsigned)inst.instruction) == 0x200) |
| 16027 | inst.instruction = 0xee001f40; |
| 16028 | /* vmla. */ |
| 16029 | else if (((unsigned)inst.instruction) == 0x900) |
| 16030 | inst.instruction = 0xee010e40; |
| 16031 | /* vmul. */ |
| 16032 | else if (((unsigned)inst.instruction) == 0x910) |
| 16033 | inst.instruction = 0xee011e60; |
| 16034 | /* vqadd. */ |
| 16035 | else if (((unsigned)inst.instruction) == 0x10) |
| 16036 | inst.instruction = 0xee000f60; |
| 16037 | /* vqsub. */ |
| 16038 | else if (((unsigned)inst.instruction) == 0x210) |
| 16039 | inst.instruction = 0xee001f60; |
| 16040 | /* vqrdmlah. */ |
| 16041 | else if (((unsigned)inst.instruction) == 0x3000b10) |
| 16042 | inst.instruction = 0xee000e40; |
| 16043 | /* vqdmulh. */ |
| 16044 | else if (((unsigned)inst.instruction) == 0x0000b00) |
| 16045 | inst.instruction = 0xee010e60; |
| 16046 | /* vqrdmulh. */ |
| 16047 | else if (((unsigned)inst.instruction) == 0x1000b00) |
| 16048 | inst.instruction = 0xfe010e60; |
| 16049 | |
| 16050 | /* Set U-bit. */ |
| 16051 | inst.instruction |= U << 28; |
| 16052 | |
| 16053 | /* Setting bits for size. */ |
| 16054 | inst.instruction |= neon_logbits (size) << 20; |
| 16055 | } |
| 16056 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 16057 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 16058 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; |
| 16059 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; |
| 16060 | inst.instruction |= inst.operands[2].reg; |
| 16061 | inst.is_neon = 1; |
| 16062 | } |
| 16063 | |
| 16064 | static void |
| 16065 | mve_encode_rqq (unsigned bit28, unsigned size) |
| 16066 | { |
| 16067 | inst.instruction |= bit28 << 28; |
| 16068 | inst.instruction |= neon_logbits (size) << 20; |
| 16069 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; |
| 16070 | inst.instruction |= inst.operands[0].reg << 12; |
| 16071 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; |
| 16072 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; |
| 16073 | inst.instruction |= LOW4 (inst.operands[2].reg); |
| 16074 | inst.is_neon = 1; |
| 16075 | } |
| 16076 | |
| 16077 | static void |
| 16078 | mve_encode_qqq (int ubit, int size) |
| 16079 | { |
| 16080 | |
| 16081 | inst.instruction |= (ubit != 0) << 28; |
| 16082 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 16083 | inst.instruction |= neon_logbits (size) << 20; |
| 16084 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; |
| 16085 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 16086 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; |
| 16087 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; |
| 16088 | inst.instruction |= LOW4 (inst.operands[2].reg); |
| 16089 | |
| 16090 | inst.is_neon = 1; |
| 16091 | } |
| 16092 | |
| 16093 | static void |
| 16094 | mve_encode_rq (unsigned bit28, unsigned size) |
| 16095 | { |
| 16096 | inst.instruction |= bit28 << 28; |
| 16097 | inst.instruction |= neon_logbits (size) << 18; |
| 16098 | inst.instruction |= inst.operands[0].reg << 12; |
| 16099 | inst.instruction |= LOW4 (inst.operands[1].reg); |
| 16100 | inst.is_neon = 1; |
| 16101 | } |
| 16102 | |
| 16103 | static void |
| 16104 | mve_encode_rrqq (unsigned U, unsigned size) |
| 16105 | { |
| 16106 | constraint (inst.operands[3].reg > 14, MVE_BAD_QREG); |
| 16107 | |
| 16108 | inst.instruction |= U << 28; |
| 16109 | inst.instruction |= (inst.operands[1].reg >> 1) << 20; |
| 16110 | inst.instruction |= LOW4 (inst.operands[2].reg) << 16; |
| 16111 | inst.instruction |= (size == 32) << 16; |
| 16112 | inst.instruction |= inst.operands[0].reg << 12; |
| 16113 | inst.instruction |= HI1 (inst.operands[2].reg) << 7; |
| 16114 | inst.instruction |= inst.operands[3].reg; |
| 16115 | inst.is_neon = 1; |
| 16116 | } |
| 16117 | |
| 16118 | /* Encode insns with bit pattern: |
| 16119 | |
| 16120 | |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| |
| 16121 | | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | |
| 16122 | |
| 16123 | SIZE is passed in bits. -1 means size field isn't changed, in case it has a |
| 16124 | different meaning for some instruction. */ |
| 16125 | |
| 16126 | static void |
| 16127 | neon_three_same (int isquad, int ubit, int size) |
| 16128 | { |
| 16129 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 16130 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 16131 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; |
| 16132 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; |
| 16133 | inst.instruction |= LOW4 (inst.operands[2].reg); |
| 16134 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; |
| 16135 | inst.instruction |= (isquad != 0) << 6; |
| 16136 | inst.instruction |= (ubit != 0) << 24; |
| 16137 | if (size != -1) |
| 16138 | inst.instruction |= neon_logbits (size) << 20; |
| 16139 | |
| 16140 | neon_dp_fixup (&inst); |
| 16141 | } |
| 16142 | |
| 16143 | /* Encode instructions of the form: |
| 16144 | |
| 16145 | |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| |
| 16146 | | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | |
| 16147 | |
| 16148 | Don't write size if SIZE == -1. */ |
| 16149 | |
| 16150 | static void |
| 16151 | neon_two_same (int qbit, int ubit, int size) |
| 16152 | { |
| 16153 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 16154 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 16155 | inst.instruction |= LOW4 (inst.operands[1].reg); |
| 16156 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; |
| 16157 | inst.instruction |= (qbit != 0) << 6; |
| 16158 | inst.instruction |= (ubit != 0) << 24; |
| 16159 | |
| 16160 | if (size != -1) |
| 16161 | inst.instruction |= neon_logbits (size) << 18; |
| 16162 | |
| 16163 | neon_dp_fixup (&inst); |
| 16164 | } |
| 16165 | |
| 16166 | enum vfp_or_neon_is_neon_bits |
| 16167 | { |
| 16168 | NEON_CHECK_CC = 1, |
| 16169 | NEON_CHECK_ARCH = 2, |
| 16170 | NEON_CHECK_ARCH8 = 4 |
| 16171 | }; |
| 16172 | |
| 16173 | /* Call this function if an instruction which may have belonged to the VFP or |
| 16174 | Neon instruction sets, but turned out to be a Neon instruction (due to the |
| 16175 | operand types involved, etc.). We have to check and/or fix-up a couple of |
| 16176 | things: |
| 16177 | |
| 16178 | - Make sure the user hasn't attempted to make a Neon instruction |
| 16179 | conditional. |
| 16180 | - Alter the value in the condition code field if necessary. |
| 16181 | - Make sure that the arch supports Neon instructions. |
| 16182 | |
| 16183 | Which of these operations take place depends on bits from enum |
| 16184 | vfp_or_neon_is_neon_bits. |
| 16185 | |
| 16186 | WARNING: This function has side effects! If NEON_CHECK_CC is used and the |
| 16187 | current instruction's condition is COND_ALWAYS, the condition field is |
| 16188 | changed to inst.uncond_value. This is necessary because instructions shared |
| 16189 | between VFP and Neon may be conditional for the VFP variants only, and the |
| 16190 | unconditional Neon version must have, e.g., 0xF in the condition field. */ |
| 16191 | |
| 16192 | static int |
| 16193 | vfp_or_neon_is_neon (unsigned check) |
| 16194 | { |
| 16195 | /* Conditions are always legal in Thumb mode (IT blocks). */ |
| 16196 | if (!thumb_mode && (check & NEON_CHECK_CC)) |
| 16197 | { |
| 16198 | if (inst.cond != COND_ALWAYS) |
| 16199 | { |
| 16200 | first_error (_(BAD_COND)); |
| 16201 | return FAIL; |
| 16202 | } |
| 16203 | if (inst.uncond_value != -1) |
| 16204 | inst.instruction |= inst.uncond_value << 28; |
| 16205 | } |
| 16206 | |
| 16207 | |
| 16208 | if (((check & NEON_CHECK_ARCH) && !mark_feature_used (&fpu_neon_ext_v1)) |
| 16209 | || ((check & NEON_CHECK_ARCH8) |
| 16210 | && !mark_feature_used (&fpu_neon_ext_armv8))) |
| 16211 | { |
| 16212 | first_error (_(BAD_FPU)); |
| 16213 | return FAIL; |
| 16214 | } |
| 16215 | |
| 16216 | return SUCCESS; |
| 16217 | } |
| 16218 | |
| 16219 | static int |
| 16220 | check_simd_pred_availability (int fp, unsigned check) |
| 16221 | { |
| 16222 | if (inst.cond > COND_ALWAYS) |
| 16223 | { |
| 16224 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 16225 | { |
| 16226 | inst.error = BAD_FPU; |
| 16227 | return 1; |
| 16228 | } |
| 16229 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 16230 | } |
| 16231 | else if (inst.cond < COND_ALWAYS) |
| 16232 | { |
| 16233 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 16234 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 16235 | else if (vfp_or_neon_is_neon (check) == FAIL) |
| 16236 | return 2; |
| 16237 | } |
| 16238 | else |
| 16239 | { |
| 16240 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, fp ? mve_fp_ext : mve_ext) |
| 16241 | && vfp_or_neon_is_neon (check) == FAIL) |
| 16242 | return 3; |
| 16243 | |
| 16244 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 16245 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 16246 | } |
| 16247 | return 0; |
| 16248 | } |
| 16249 | |
| 16250 | /* Neon instruction encoders, in approximate order of appearance. */ |
| 16251 | |
| 16252 | static void |
| 16253 | do_neon_dyadic_i_su (void) |
| 16254 | { |
| 16255 | if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
| 16256 | return; |
| 16257 | |
| 16258 | enum neon_shape rs; |
| 16259 | struct neon_type_el et; |
| 16260 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 16261 | rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL); |
| 16262 | else |
| 16263 | rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
| 16264 | |
| 16265 | et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_32 | N_KEY); |
| 16266 | |
| 16267 | |
| 16268 | if (rs != NS_QQR) |
| 16269 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
| 16270 | else |
| 16271 | mve_encode_qqr (et.size, et.type == NT_unsigned, 0); |
| 16272 | } |
| 16273 | |
| 16274 | static void |
| 16275 | do_neon_dyadic_i64_su (void) |
| 16276 | { |
| 16277 | if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH)) |
| 16278 | return; |
| 16279 | enum neon_shape rs; |
| 16280 | struct neon_type_el et; |
| 16281 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 16282 | { |
| 16283 | rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL); |
| 16284 | et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY); |
| 16285 | } |
| 16286 | else |
| 16287 | { |
| 16288 | rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
| 16289 | et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_ALL | N_KEY); |
| 16290 | } |
| 16291 | if (rs == NS_QQR) |
| 16292 | mve_encode_qqr (et.size, et.type == NT_unsigned, 0); |
| 16293 | else |
| 16294 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
| 16295 | } |
| 16296 | |
| 16297 | static void |
| 16298 | neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, |
| 16299 | unsigned immbits) |
| 16300 | { |
| 16301 | unsigned size = et.size >> 3; |
| 16302 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 16303 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 16304 | inst.instruction |= LOW4 (inst.operands[1].reg); |
| 16305 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; |
| 16306 | inst.instruction |= (isquad != 0) << 6; |
| 16307 | inst.instruction |= immbits << 16; |
| 16308 | inst.instruction |= (size >> 3) << 7; |
| 16309 | inst.instruction |= (size & 0x7) << 19; |
| 16310 | if (write_ubit) |
| 16311 | inst.instruction |= (uval != 0) << 24; |
| 16312 | |
| 16313 | neon_dp_fixup (&inst); |
| 16314 | } |
| 16315 | |
| 16316 | static void |
| 16317 | do_neon_shl_imm (void) |
| 16318 | { |
| 16319 | if (!inst.operands[2].isreg) |
| 16320 | { |
| 16321 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
| 16322 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); |
| 16323 | int imm = inst.operands[2].imm; |
| 16324 | |
| 16325 | constraint (imm < 0 || (unsigned)imm >= et.size, |
| 16326 | _("immediate out of range for shift")); |
| 16327 | NEON_ENCODE (IMMED, inst); |
| 16328 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
| 16329 | } |
| 16330 | else |
| 16331 | { |
| 16332 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
| 16333 | struct neon_type_el et = neon_check_type (3, rs, |
| 16334 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); |
| 16335 | unsigned int tmp; |
| 16336 | |
| 16337 | /* VSHL/VQSHL 3-register variants have syntax such as: |
| 16338 | vshl.xx Dd, Dm, Dn |
| 16339 | whereas other 3-register operations encoded by neon_three_same have |
| 16340 | syntax like: |
| 16341 | vadd.xx Dd, Dn, Dm |
| 16342 | (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg |
| 16343 | here. */ |
| 16344 | tmp = inst.operands[2].reg; |
| 16345 | inst.operands[2].reg = inst.operands[1].reg; |
| 16346 | inst.operands[1].reg = tmp; |
| 16347 | NEON_ENCODE (INTEGER, inst); |
| 16348 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
| 16349 | } |
| 16350 | } |
| 16351 | |
| 16352 | static void |
| 16353 | do_neon_qshl_imm (void) |
| 16354 | { |
| 16355 | if (!inst.operands[2].isreg) |
| 16356 | { |
| 16357 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
| 16358 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
| 16359 | int imm = inst.operands[2].imm; |
| 16360 | |
| 16361 | constraint (imm < 0 || (unsigned)imm >= et.size, |
| 16362 | _("immediate out of range for shift")); |
| 16363 | NEON_ENCODE (IMMED, inst); |
| 16364 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, imm); |
| 16365 | } |
| 16366 | else |
| 16367 | { |
| 16368 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
| 16369 | struct neon_type_el et = neon_check_type (3, rs, |
| 16370 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); |
| 16371 | unsigned int tmp; |
| 16372 | |
| 16373 | /* See note in do_neon_shl_imm. */ |
| 16374 | tmp = inst.operands[2].reg; |
| 16375 | inst.operands[2].reg = inst.operands[1].reg; |
| 16376 | inst.operands[1].reg = tmp; |
| 16377 | NEON_ENCODE (INTEGER, inst); |
| 16378 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
| 16379 | } |
| 16380 | } |
| 16381 | |
| 16382 | static void |
| 16383 | do_neon_rshl (void) |
| 16384 | { |
| 16385 | if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
| 16386 | return; |
| 16387 | |
| 16388 | enum neon_shape rs; |
| 16389 | struct neon_type_el et; |
| 16390 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 16391 | { |
| 16392 | rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL); |
| 16393 | et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY); |
| 16394 | } |
| 16395 | else |
| 16396 | { |
| 16397 | rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
| 16398 | et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_ALL | N_KEY); |
| 16399 | } |
| 16400 | |
| 16401 | unsigned int tmp; |
| 16402 | |
| 16403 | if (rs == NS_QQR) |
| 16404 | { |
| 16405 | if (inst.operands[2].reg == REG_PC) |
| 16406 | as_tsktsk (MVE_BAD_PC); |
| 16407 | else if (inst.operands[2].reg == REG_SP) |
| 16408 | as_tsktsk (MVE_BAD_SP); |
| 16409 | |
| 16410 | constraint (inst.operands[0].reg != inst.operands[1].reg, |
| 16411 | _("invalid instruction shape")); |
| 16412 | |
| 16413 | if (inst.instruction == 0x0000510) |
| 16414 | /* We are dealing with vqrshl. */ |
| 16415 | inst.instruction = 0xee331ee0; |
| 16416 | else |
| 16417 | /* We are dealing with vrshl. */ |
| 16418 | inst.instruction = 0xee331e60; |
| 16419 | |
| 16420 | inst.instruction |= (et.type == NT_unsigned) << 28; |
| 16421 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 16422 | inst.instruction |= neon_logbits (et.size) << 18; |
| 16423 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 16424 | inst.instruction |= inst.operands[2].reg; |
| 16425 | inst.is_neon = 1; |
| 16426 | } |
| 16427 | else |
| 16428 | { |
| 16429 | tmp = inst.operands[2].reg; |
| 16430 | inst.operands[2].reg = inst.operands[1].reg; |
| 16431 | inst.operands[1].reg = tmp; |
| 16432 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
| 16433 | } |
| 16434 | } |
| 16435 | |
| 16436 | static int |
| 16437 | neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) |
| 16438 | { |
| 16439 | /* Handle .I8 pseudo-instructions. */ |
| 16440 | if (size == 8) |
| 16441 | { |
| 16442 | /* Unfortunately, this will make everything apart from zero out-of-range. |
| 16443 | FIXME is this the intended semantics? There doesn't seem much point in |
| 16444 | accepting .I8 if so. */ |
| 16445 | immediate |= immediate << 8; |
| 16446 | size = 16; |
| 16447 | } |
| 16448 | |
| 16449 | if (size >= 32) |
| 16450 | { |
| 16451 | if (immediate == (immediate & 0x000000ff)) |
| 16452 | { |
| 16453 | *immbits = immediate; |
| 16454 | return 0x1; |
| 16455 | } |
| 16456 | else if (immediate == (immediate & 0x0000ff00)) |
| 16457 | { |
| 16458 | *immbits = immediate >> 8; |
| 16459 | return 0x3; |
| 16460 | } |
| 16461 | else if (immediate == (immediate & 0x00ff0000)) |
| 16462 | { |
| 16463 | *immbits = immediate >> 16; |
| 16464 | return 0x5; |
| 16465 | } |
| 16466 | else if (immediate == (immediate & 0xff000000)) |
| 16467 | { |
| 16468 | *immbits = immediate >> 24; |
| 16469 | return 0x7; |
| 16470 | } |
| 16471 | if ((immediate & 0xffff) != (immediate >> 16)) |
| 16472 | goto bad_immediate; |
| 16473 | immediate &= 0xffff; |
| 16474 | } |
| 16475 | |
| 16476 | if (immediate == (immediate & 0x000000ff)) |
| 16477 | { |
| 16478 | *immbits = immediate; |
| 16479 | return 0x9; |
| 16480 | } |
| 16481 | else if (immediate == (immediate & 0x0000ff00)) |
| 16482 | { |
| 16483 | *immbits = immediate >> 8; |
| 16484 | return 0xb; |
| 16485 | } |
| 16486 | |
| 16487 | bad_immediate: |
| 16488 | first_error (_("immediate value out of range")); |
| 16489 | return FAIL; |
| 16490 | } |
| 16491 | |
| 16492 | static void |
| 16493 | do_neon_logic (void) |
| 16494 | { |
| 16495 | if (inst.operands[2].present && inst.operands[2].isreg) |
| 16496 | { |
| 16497 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
| 16498 | if (rs == NS_QQQ |
| 16499 | && check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC) |
| 16500 | == FAIL) |
| 16501 | return; |
| 16502 | else if (rs != NS_QQQ |
| 16503 | && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) |
| 16504 | first_error (BAD_FPU); |
| 16505 | |
| 16506 | neon_check_type (3, rs, N_IGNORE_TYPE); |
| 16507 | /* U bit and size field were set as part of the bitmask. */ |
| 16508 | NEON_ENCODE (INTEGER, inst); |
| 16509 | neon_three_same (neon_quad (rs), 0, -1); |
| 16510 | } |
| 16511 | else |
| 16512 | { |
| 16513 | const int three_ops_form = (inst.operands[2].present |
| 16514 | && !inst.operands[2].isreg); |
| 16515 | const int immoperand = (three_ops_form ? 2 : 1); |
| 16516 | enum neon_shape rs = (three_ops_form |
| 16517 | ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL) |
| 16518 | : neon_select_shape (NS_DI, NS_QI, NS_NULL)); |
| 16519 | /* Because neon_select_shape makes the second operand a copy of the first |
| 16520 | if the second operand is not present. */ |
| 16521 | if (rs == NS_QQI |
| 16522 | && check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC) |
| 16523 | == FAIL) |
| 16524 | return; |
| 16525 | else if (rs != NS_QQI |
| 16526 | && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) |
| 16527 | first_error (BAD_FPU); |
| 16528 | |
| 16529 | struct neon_type_el et; |
| 16530 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 16531 | et = neon_check_type (2, rs, N_I32 | N_I16 | N_KEY, N_EQK); |
| 16532 | else |
| 16533 | et = neon_check_type (2, rs, N_I8 | N_I16 | N_I32 | N_I64 | N_F32 |
| 16534 | | N_KEY, N_EQK); |
| 16535 | |
| 16536 | if (et.type == NT_invtype) |
| 16537 | return; |
| 16538 | enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff; |
| 16539 | unsigned immbits; |
| 16540 | int cmode; |
| 16541 | |
| 16542 | |
| 16543 | if (three_ops_form) |
| 16544 | constraint (inst.operands[0].reg != inst.operands[1].reg, |
| 16545 | _("first and second operands shall be the same register")); |
| 16546 | |
| 16547 | NEON_ENCODE (IMMED, inst); |
| 16548 | |
| 16549 | immbits = inst.operands[immoperand].imm; |
| 16550 | if (et.size == 64) |
| 16551 | { |
| 16552 | /* .i64 is a pseudo-op, so the immediate must be a repeating |
| 16553 | pattern. */ |
| 16554 | if (immbits != (inst.operands[immoperand].regisimm ? |
| 16555 | inst.operands[immoperand].reg : 0)) |
| 16556 | { |
| 16557 | /* Set immbits to an invalid constant. */ |
| 16558 | immbits = 0xdeadbeef; |
| 16559 | } |
| 16560 | } |
| 16561 | |
| 16562 | switch (opcode) |
| 16563 | { |
| 16564 | case N_MNEM_vbic: |
| 16565 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); |
| 16566 | break; |
| 16567 | |
| 16568 | case N_MNEM_vorr: |
| 16569 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); |
| 16570 | break; |
| 16571 | |
| 16572 | case N_MNEM_vand: |
| 16573 | /* Pseudo-instruction for VBIC. */ |
| 16574 | neon_invert_size (&immbits, 0, et.size); |
| 16575 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); |
| 16576 | break; |
| 16577 | |
| 16578 | case N_MNEM_vorn: |
| 16579 | /* Pseudo-instruction for VORR. */ |
| 16580 | neon_invert_size (&immbits, 0, et.size); |
| 16581 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); |
| 16582 | break; |
| 16583 | |
| 16584 | default: |
| 16585 | abort (); |
| 16586 | } |
| 16587 | |
| 16588 | if (cmode == FAIL) |
| 16589 | return; |
| 16590 | |
| 16591 | inst.instruction |= neon_quad (rs) << 6; |
| 16592 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 16593 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 16594 | inst.instruction |= cmode << 8; |
| 16595 | neon_write_immbits (immbits); |
| 16596 | |
| 16597 | neon_dp_fixup (&inst); |
| 16598 | } |
| 16599 | } |
| 16600 | |
| 16601 | static void |
| 16602 | do_neon_bitfield (void) |
| 16603 | { |
| 16604 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
| 16605 | neon_check_type (3, rs, N_IGNORE_TYPE); |
| 16606 | neon_three_same (neon_quad (rs), 0, -1); |
| 16607 | } |
| 16608 | |
| 16609 | static void |
| 16610 | neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, |
| 16611 | unsigned destbits) |
| 16612 | { |
| 16613 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL); |
| 16614 | struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, |
| 16615 | types | N_KEY); |
| 16616 | if (et.type == NT_float) |
| 16617 | { |
| 16618 | NEON_ENCODE (FLOAT, inst); |
| 16619 | if (rs == NS_QQR) |
| 16620 | mve_encode_qqr (et.size, 0, 1); |
| 16621 | else |
| 16622 | neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1); |
| 16623 | } |
| 16624 | else |
| 16625 | { |
| 16626 | NEON_ENCODE (INTEGER, inst); |
| 16627 | if (rs == NS_QQR) |
| 16628 | mve_encode_qqr (et.size, et.type == ubit_meaning, 0); |
| 16629 | else |
| 16630 | neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); |
| 16631 | } |
| 16632 | } |
| 16633 | |
| 16634 | |
| 16635 | static void |
| 16636 | do_neon_dyadic_if_su_d (void) |
| 16637 | { |
| 16638 | /* This version only allow D registers, but that constraint is enforced during |
| 16639 | operand parsing so we don't need to do anything extra here. */ |
| 16640 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
| 16641 | } |
| 16642 | |
| 16643 | static void |
| 16644 | do_neon_dyadic_if_i_d (void) |
| 16645 | { |
| 16646 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
| 16647 | affected if we specify unsigned args. */ |
| 16648 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); |
| 16649 | } |
| 16650 | |
| 16651 | static void |
| 16652 | do_mve_vstr_vldr_QI (int size, int elsize, int load) |
| 16653 | { |
| 16654 | constraint (size < 32, BAD_ADDR_MODE); |
| 16655 | constraint (size != elsize, BAD_EL_TYPE); |
| 16656 | constraint (inst.operands[1].immisreg, BAD_ADDR_MODE); |
| 16657 | constraint (!inst.operands[1].preind, BAD_ADDR_MODE); |
| 16658 | constraint (load && inst.operands[0].reg == inst.operands[1].reg, |
| 16659 | _("destination register and offset register may not be the" |
| 16660 | " same")); |
| 16661 | |
| 16662 | int imm = inst.relocs[0].exp.X_add_number; |
| 16663 | int add = 1; |
| 16664 | if (imm < 0) |
| 16665 | { |
| 16666 | add = 0; |
| 16667 | imm = -imm; |
| 16668 | } |
| 16669 | constraint ((imm % (size / 8) != 0) |
| 16670 | || imm > (0x7f << neon_logbits (size)), |
| 16671 | (size == 32) ? _("immediate must be a multiple of 4 in the" |
| 16672 | " range of +/-[0,508]") |
| 16673 | : _("immediate must be a multiple of 8 in the" |
| 16674 | " range of +/-[0,1016]")); |
| 16675 | inst.instruction |= 0x11 << 24; |
| 16676 | inst.instruction |= add << 23; |
| 16677 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 16678 | inst.instruction |= inst.operands[1].writeback << 21; |
| 16679 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; |
| 16680 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 16681 | inst.instruction |= 1 << 12; |
| 16682 | inst.instruction |= (size == 64) << 8; |
| 16683 | inst.instruction &= 0xffffff00; |
| 16684 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; |
| 16685 | inst.instruction |= imm >> neon_logbits (size); |
| 16686 | } |
| 16687 | |
| 16688 | static void |
| 16689 | do_mve_vstr_vldr_RQ (int size, int elsize, int load) |
| 16690 | { |
| 16691 | unsigned os = inst.operands[1].imm >> 5; |
| 16692 | constraint (os != 0 && size == 8, |
| 16693 | _("can not shift offsets when accessing less than half-word")); |
| 16694 | constraint (os && os != neon_logbits (size), |
| 16695 | _("shift immediate must be 1, 2 or 3 for half-word, word" |
| 16696 | " or double-word accesses respectively")); |
| 16697 | if (inst.operands[1].reg == REG_PC) |
| 16698 | as_tsktsk (MVE_BAD_PC); |
| 16699 | |
| 16700 | switch (size) |
| 16701 | { |
| 16702 | case 8: |
| 16703 | constraint (elsize >= 64, BAD_EL_TYPE); |
| 16704 | break; |
| 16705 | case 16: |
| 16706 | constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE); |
| 16707 | break; |
| 16708 | case 32: |
| 16709 | case 64: |
| 16710 | constraint (elsize != size, BAD_EL_TYPE); |
| 16711 | break; |
| 16712 | default: |
| 16713 | break; |
| 16714 | } |
| 16715 | constraint (inst.operands[1].writeback || !inst.operands[1].preind, |
| 16716 | BAD_ADDR_MODE); |
| 16717 | if (load) |
| 16718 | { |
| 16719 | constraint (inst.operands[0].reg == (inst.operands[1].imm & 0x1f), |
| 16720 | _("destination register and offset register may not be" |
| 16721 | " the same")); |
| 16722 | constraint (size == elsize && inst.vectype.el[0].type != NT_unsigned, |
| 16723 | BAD_EL_TYPE); |
| 16724 | constraint (inst.vectype.el[0].type != NT_unsigned |
| 16725 | && inst.vectype.el[0].type != NT_signed, BAD_EL_TYPE); |
| 16726 | inst.instruction |= (inst.vectype.el[0].type == NT_unsigned) << 28; |
| 16727 | } |
| 16728 | else |
| 16729 | { |
| 16730 | constraint (inst.vectype.el[0].type != NT_untyped, BAD_EL_TYPE); |
| 16731 | } |
| 16732 | |
| 16733 | inst.instruction |= 1 << 23; |
| 16734 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 16735 | inst.instruction |= inst.operands[1].reg << 16; |
| 16736 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 16737 | inst.instruction |= neon_logbits (elsize) << 7; |
| 16738 | inst.instruction |= HI1 (inst.operands[1].imm) << 5; |
| 16739 | inst.instruction |= LOW4 (inst.operands[1].imm); |
| 16740 | inst.instruction |= !!os; |
| 16741 | } |
| 16742 | |
| 16743 | static void |
| 16744 | do_mve_vstr_vldr_RI (int size, int elsize, int load) |
| 16745 | { |
| 16746 | enum neon_el_type type = inst.vectype.el[0].type; |
| 16747 | |
| 16748 | constraint (size >= 64, BAD_ADDR_MODE); |
| 16749 | switch (size) |
| 16750 | { |
| 16751 | case 16: |
| 16752 | constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE); |
| 16753 | break; |
| 16754 | case 32: |
| 16755 | constraint (elsize != size, BAD_EL_TYPE); |
| 16756 | break; |
| 16757 | default: |
| 16758 | break; |
| 16759 | } |
| 16760 | if (load) |
| 16761 | { |
| 16762 | constraint (elsize != size && type != NT_unsigned |
| 16763 | && type != NT_signed, BAD_EL_TYPE); |
| 16764 | } |
| 16765 | else |
| 16766 | { |
| 16767 | constraint (elsize != size && type != NT_untyped, BAD_EL_TYPE); |
| 16768 | } |
| 16769 | |
| 16770 | int imm = inst.relocs[0].exp.X_add_number; |
| 16771 | int add = 1; |
| 16772 | if (imm < 0) |
| 16773 | { |
| 16774 | add = 0; |
| 16775 | imm = -imm; |
| 16776 | } |
| 16777 | |
| 16778 | if ((imm % (size / 8) != 0) || imm > (0x7f << neon_logbits (size))) |
| 16779 | { |
| 16780 | switch (size) |
| 16781 | { |
| 16782 | case 8: |
| 16783 | constraint (1, _("immediate must be in the range of +/-[0,127]")); |
| 16784 | break; |
| 16785 | case 16: |
| 16786 | constraint (1, _("immediate must be a multiple of 2 in the" |
| 16787 | " range of +/-[0,254]")); |
| 16788 | break; |
| 16789 | case 32: |
| 16790 | constraint (1, _("immediate must be a multiple of 4 in the" |
| 16791 | " range of +/-[0,508]")); |
| 16792 | break; |
| 16793 | } |
| 16794 | } |
| 16795 | |
| 16796 | if (size != elsize) |
| 16797 | { |
| 16798 | constraint (inst.operands[1].reg > 7, BAD_HIREG); |
| 16799 | constraint (inst.operands[0].reg > 14, |
| 16800 | _("MVE vector register in the range [Q0..Q7] expected")); |
| 16801 | inst.instruction |= (load && type == NT_unsigned) << 28; |
| 16802 | inst.instruction |= (size == 16) << 19; |
| 16803 | inst.instruction |= neon_logbits (elsize) << 7; |
| 16804 | } |
| 16805 | else |
| 16806 | { |
| 16807 | if (inst.operands[1].reg == REG_PC) |
| 16808 | as_tsktsk (MVE_BAD_PC); |
| 16809 | else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback) |
| 16810 | as_tsktsk (MVE_BAD_SP); |
| 16811 | inst.instruction |= 1 << 12; |
| 16812 | inst.instruction |= neon_logbits (size) << 7; |
| 16813 | } |
| 16814 | inst.instruction |= inst.operands[1].preind << 24; |
| 16815 | inst.instruction |= add << 23; |
| 16816 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 16817 | inst.instruction |= inst.operands[1].writeback << 21; |
| 16818 | inst.instruction |= inst.operands[1].reg << 16; |
| 16819 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 16820 | inst.instruction &= 0xffffff80; |
| 16821 | inst.instruction |= imm >> neon_logbits (size); |
| 16822 | |
| 16823 | } |
| 16824 | |
| 16825 | static void |
| 16826 | do_mve_vstr_vldr (void) |
| 16827 | { |
| 16828 | unsigned size; |
| 16829 | int load = 0; |
| 16830 | |
| 16831 | if (inst.cond > COND_ALWAYS) |
| 16832 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 16833 | else |
| 16834 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 16835 | |
| 16836 | switch (inst.instruction) |
| 16837 | { |
| 16838 | default: |
| 16839 | gas_assert (0); |
| 16840 | break; |
| 16841 | case M_MNEM_vldrb: |
| 16842 | load = 1; |
| 16843 | /* fall through. */ |
| 16844 | case M_MNEM_vstrb: |
| 16845 | size = 8; |
| 16846 | break; |
| 16847 | case M_MNEM_vldrh: |
| 16848 | load = 1; |
| 16849 | /* fall through. */ |
| 16850 | case M_MNEM_vstrh: |
| 16851 | size = 16; |
| 16852 | break; |
| 16853 | case M_MNEM_vldrw: |
| 16854 | load = 1; |
| 16855 | /* fall through. */ |
| 16856 | case M_MNEM_vstrw: |
| 16857 | size = 32; |
| 16858 | break; |
| 16859 | case M_MNEM_vldrd: |
| 16860 | load = 1; |
| 16861 | /* fall through. */ |
| 16862 | case M_MNEM_vstrd: |
| 16863 | size = 64; |
| 16864 | break; |
| 16865 | } |
| 16866 | unsigned elsize = inst.vectype.el[0].size; |
| 16867 | |
| 16868 | if (inst.operands[1].isquad) |
| 16869 | { |
| 16870 | /* We are dealing with [Q, imm]{!} cases. */ |
| 16871 | do_mve_vstr_vldr_QI (size, elsize, load); |
| 16872 | } |
| 16873 | else |
| 16874 | { |
| 16875 | if (inst.operands[1].immisreg == 2) |
| 16876 | { |
| 16877 | /* We are dealing with [R, Q, {UXTW #os}] cases. */ |
| 16878 | do_mve_vstr_vldr_RQ (size, elsize, load); |
| 16879 | } |
| 16880 | else if (!inst.operands[1].immisreg) |
| 16881 | { |
| 16882 | /* We are dealing with [R, Imm]{!}/[R], Imm cases. */ |
| 16883 | do_mve_vstr_vldr_RI (size, elsize, load); |
| 16884 | } |
| 16885 | else |
| 16886 | constraint (1, BAD_ADDR_MODE); |
| 16887 | } |
| 16888 | |
| 16889 | inst.is_neon = 1; |
| 16890 | } |
| 16891 | |
| 16892 | static void |
| 16893 | do_mve_vst_vld (void) |
| 16894 | { |
| 16895 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 16896 | return; |
| 16897 | |
| 16898 | constraint (!inst.operands[1].preind || inst.relocs[0].exp.X_add_symbol != 0 |
| 16899 | || inst.relocs[0].exp.X_add_number != 0 |
| 16900 | || inst.operands[1].immisreg != 0, |
| 16901 | BAD_ADDR_MODE); |
| 16902 | constraint (inst.vectype.el[0].size > 32, BAD_EL_TYPE); |
| 16903 | if (inst.operands[1].reg == REG_PC) |
| 16904 | as_tsktsk (MVE_BAD_PC); |
| 16905 | else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback) |
| 16906 | as_tsktsk (MVE_BAD_SP); |
| 16907 | |
| 16908 | |
| 16909 | /* These instructions are one of the "exceptions" mentioned in |
| 16910 | handle_pred_state. They are MVE instructions that are not VPT compatible |
| 16911 | and do not accept a VPT code, thus appending such a code is a syntax |
| 16912 | error. */ |
| 16913 | if (inst.cond > COND_ALWAYS) |
| 16914 | first_error (BAD_SYNTAX); |
| 16915 | /* If we append a scalar condition code we can set this to |
| 16916 | MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */ |
| 16917 | else if (inst.cond < COND_ALWAYS) |
| 16918 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 16919 | else |
| 16920 | inst.pred_insn_type = MVE_UNPREDICABLE_INSN; |
| 16921 | |
| 16922 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 16923 | inst.instruction |= inst.operands[1].writeback << 21; |
| 16924 | inst.instruction |= inst.operands[1].reg << 16; |
| 16925 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 16926 | inst.instruction |= neon_logbits (inst.vectype.el[0].size) << 7; |
| 16927 | inst.is_neon = 1; |
| 16928 | } |
| 16929 | |
| 16930 | static void |
| 16931 | do_mve_vaddlv (void) |
| 16932 | { |
| 16933 | enum neon_shape rs = neon_select_shape (NS_RRQ, NS_NULL); |
| 16934 | struct neon_type_el et |
| 16935 | = neon_check_type (3, rs, N_EQK, N_EQK, N_S32 | N_U32 | N_KEY); |
| 16936 | |
| 16937 | if (et.type == NT_invtype) |
| 16938 | first_error (BAD_EL_TYPE); |
| 16939 | |
| 16940 | if (inst.cond > COND_ALWAYS) |
| 16941 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 16942 | else |
| 16943 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 16944 | |
| 16945 | constraint (inst.operands[1].reg > 14, MVE_BAD_QREG); |
| 16946 | |
| 16947 | inst.instruction |= (et.type == NT_unsigned) << 28; |
| 16948 | inst.instruction |= inst.operands[1].reg << 19; |
| 16949 | inst.instruction |= inst.operands[0].reg << 12; |
| 16950 | inst.instruction |= inst.operands[2].reg; |
| 16951 | inst.is_neon = 1; |
| 16952 | } |
| 16953 | |
| 16954 | static void |
| 16955 | do_neon_dyadic_if_su (void) |
| 16956 | { |
| 16957 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL); |
| 16958 | struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK, |
| 16959 | N_SUF_32 | N_KEY); |
| 16960 | |
| 16961 | constraint ((inst.instruction == ((unsigned) N_MNEM_vmax) |
| 16962 | || inst.instruction == ((unsigned) N_MNEM_vmin)) |
| 16963 | && et.type == NT_float |
| 16964 | && !ARM_CPU_HAS_FEATURE (cpu_variant,fpu_neon_ext_v1), BAD_FPU); |
| 16965 | |
| 16966 | if (check_simd_pred_availability (et.type == NT_float, |
| 16967 | NEON_CHECK_ARCH | NEON_CHECK_CC)) |
| 16968 | return; |
| 16969 | |
| 16970 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
| 16971 | } |
| 16972 | |
| 16973 | static void |
| 16974 | do_neon_addsub_if_i (void) |
| 16975 | { |
| 16976 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd) |
| 16977 | && try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) |
| 16978 | return; |
| 16979 | |
| 16980 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL); |
| 16981 | struct neon_type_el et = neon_check_type (3, rs, N_EQK, |
| 16982 | N_EQK, N_IF_32 | N_I64 | N_KEY); |
| 16983 | |
| 16984 | constraint (rs == NS_QQR && et.size == 64, BAD_FPU); |
| 16985 | /* If we are parsing Q registers and the element types match MVE, which NEON |
| 16986 | also supports, then we must check whether this is an instruction that can |
| 16987 | be used by both MVE/NEON. This distinction can be made based on whether |
| 16988 | they are predicated or not. */ |
| 16989 | if ((rs == NS_QQQ || rs == NS_QQR) && et.size != 64) |
| 16990 | { |
| 16991 | if (check_simd_pred_availability (et.type == NT_float, |
| 16992 | NEON_CHECK_ARCH | NEON_CHECK_CC)) |
| 16993 | return; |
| 16994 | } |
| 16995 | else |
| 16996 | { |
| 16997 | /* If they are either in a D register or are using an unsupported. */ |
| 16998 | if (rs != NS_QQR |
| 16999 | && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
| 17000 | return; |
| 17001 | } |
| 17002 | |
| 17003 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
| 17004 | affected if we specify unsigned args. */ |
| 17005 | neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); |
| 17006 | } |
| 17007 | |
| 17008 | /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the |
| 17009 | result to be: |
| 17010 | V<op> A,B (A is operand 0, B is operand 2) |
| 17011 | to mean: |
| 17012 | V<op> A,B,A |
| 17013 | not: |
| 17014 | V<op> A,B,B |
| 17015 | so handle that case specially. */ |
| 17016 | |
| 17017 | static void |
| 17018 | neon_exchange_operands (void) |
| 17019 | { |
| 17020 | if (inst.operands[1].present) |
| 17021 | { |
| 17022 | void *scratch = xmalloc (sizeof (inst.operands[0])); |
| 17023 | |
| 17024 | /* Swap operands[1] and operands[2]. */ |
| 17025 | memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); |
| 17026 | inst.operands[1] = inst.operands[2]; |
| 17027 | memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); |
| 17028 | free (scratch); |
| 17029 | } |
| 17030 | else |
| 17031 | { |
| 17032 | inst.operands[1] = inst.operands[2]; |
| 17033 | inst.operands[2] = inst.operands[0]; |
| 17034 | } |
| 17035 | } |
| 17036 | |
| 17037 | static void |
| 17038 | neon_compare (unsigned regtypes, unsigned immtypes, int invert) |
| 17039 | { |
| 17040 | if (inst.operands[2].isreg) |
| 17041 | { |
| 17042 | if (invert) |
| 17043 | neon_exchange_operands (); |
| 17044 | neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); |
| 17045 | } |
| 17046 | else |
| 17047 | { |
| 17048 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
| 17049 | struct neon_type_el et = neon_check_type (2, rs, |
| 17050 | N_EQK | N_SIZ, immtypes | N_KEY); |
| 17051 | |
| 17052 | NEON_ENCODE (IMMED, inst); |
| 17053 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 17054 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 17055 | inst.instruction |= LOW4 (inst.operands[1].reg); |
| 17056 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; |
| 17057 | inst.instruction |= neon_quad (rs) << 6; |
| 17058 | inst.instruction |= (et.type == NT_float) << 10; |
| 17059 | inst.instruction |= neon_logbits (et.size) << 18; |
| 17060 | |
| 17061 | neon_dp_fixup (&inst); |
| 17062 | } |
| 17063 | } |
| 17064 | |
| 17065 | static void |
| 17066 | do_neon_cmp (void) |
| 17067 | { |
| 17068 | neon_compare (N_SUF_32, N_S_32 | N_F_16_32, FALSE); |
| 17069 | } |
| 17070 | |
| 17071 | static void |
| 17072 | do_neon_cmp_inv (void) |
| 17073 | { |
| 17074 | neon_compare (N_SUF_32, N_S_32 | N_F_16_32, TRUE); |
| 17075 | } |
| 17076 | |
| 17077 | static void |
| 17078 | do_neon_ceq (void) |
| 17079 | { |
| 17080 | neon_compare (N_IF_32, N_IF_32, FALSE); |
| 17081 | } |
| 17082 | |
| 17083 | /* For multiply instructions, we have the possibility of 16-bit or 32-bit |
| 17084 | scalars, which are encoded in 5 bits, M : Rm. |
| 17085 | For 16-bit scalars, the register is encoded in Rm[2:0] and the index in |
| 17086 | M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the |
| 17087 | index in M. |
| 17088 | |
| 17089 | Dot Product instructions are similar to multiply instructions except elsize |
| 17090 | should always be 32. |
| 17091 | |
| 17092 | This function translates SCALAR, which is GAS's internal encoding of indexed |
| 17093 | scalar register, to raw encoding. There is also register and index range |
| 17094 | check based on ELSIZE. */ |
| 17095 | |
| 17096 | static unsigned |
| 17097 | neon_scalar_for_mul (unsigned scalar, unsigned elsize) |
| 17098 | { |
| 17099 | unsigned regno = NEON_SCALAR_REG (scalar); |
| 17100 | unsigned elno = NEON_SCALAR_INDEX (scalar); |
| 17101 | |
| 17102 | switch (elsize) |
| 17103 | { |
| 17104 | case 16: |
| 17105 | if (regno > 7 || elno > 3) |
| 17106 | goto bad_scalar; |
| 17107 | return regno | (elno << 3); |
| 17108 | |
| 17109 | case 32: |
| 17110 | if (regno > 15 || elno > 1) |
| 17111 | goto bad_scalar; |
| 17112 | return regno | (elno << 4); |
| 17113 | |
| 17114 | default: |
| 17115 | bad_scalar: |
| 17116 | first_error (_("scalar out of range for multiply instruction")); |
| 17117 | } |
| 17118 | |
| 17119 | return 0; |
| 17120 | } |
| 17121 | |
| 17122 | /* Encode multiply / multiply-accumulate scalar instructions. */ |
| 17123 | |
| 17124 | static void |
| 17125 | neon_mul_mac (struct neon_type_el et, int ubit) |
| 17126 | { |
| 17127 | unsigned scalar; |
| 17128 | |
| 17129 | /* Give a more helpful error message if we have an invalid type. */ |
| 17130 | if (et.type == NT_invtype) |
| 17131 | return; |
| 17132 | |
| 17133 | scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); |
| 17134 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 17135 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 17136 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; |
| 17137 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; |
| 17138 | inst.instruction |= LOW4 (scalar); |
| 17139 | inst.instruction |= HI1 (scalar) << 5; |
| 17140 | inst.instruction |= (et.type == NT_float) << 8; |
| 17141 | inst.instruction |= neon_logbits (et.size) << 20; |
| 17142 | inst.instruction |= (ubit != 0) << 24; |
| 17143 | |
| 17144 | neon_dp_fixup (&inst); |
| 17145 | } |
| 17146 | |
| 17147 | static void |
| 17148 | do_neon_mac_maybe_scalar (void) |
| 17149 | { |
| 17150 | if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) |
| 17151 | return; |
| 17152 | |
| 17153 | if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH)) |
| 17154 | return; |
| 17155 | |
| 17156 | if (inst.operands[2].isscalar) |
| 17157 | { |
| 17158 | constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); |
| 17159 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
| 17160 | struct neon_type_el et = neon_check_type (3, rs, |
| 17161 | N_EQK, N_EQK, N_I16 | N_I32 | N_F_16_32 | N_KEY); |
| 17162 | NEON_ENCODE (SCALAR, inst); |
| 17163 | neon_mul_mac (et, neon_quad (rs)); |
| 17164 | } |
| 17165 | else if (!inst.operands[2].isvec) |
| 17166 | { |
| 17167 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); |
| 17168 | |
| 17169 | enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); |
| 17170 | neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY); |
| 17171 | |
| 17172 | neon_dyadic_misc (NT_unsigned, N_SU_MVE, 0); |
| 17173 | } |
| 17174 | else |
| 17175 | { |
| 17176 | constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); |
| 17177 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
| 17178 | affected if we specify unsigned args. */ |
| 17179 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); |
| 17180 | } |
| 17181 | } |
| 17182 | |
| 17183 | static void |
| 17184 | do_neon_fmac (void) |
| 17185 | { |
| 17186 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_fma) |
| 17187 | && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS) |
| 17188 | return; |
| 17189 | |
| 17190 | if (check_simd_pred_availability (1, NEON_CHECK_CC | NEON_CHECK_ARCH)) |
| 17191 | return; |
| 17192 | |
| 17193 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)) |
| 17194 | { |
| 17195 | enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL); |
| 17196 | struct neon_type_el et = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK, |
| 17197 | N_EQK); |
| 17198 | |
| 17199 | if (rs == NS_QQR) |
| 17200 | { |
| 17201 | if (inst.operands[2].reg == REG_SP) |
| 17202 | as_tsktsk (MVE_BAD_SP); |
| 17203 | else if (inst.operands[2].reg == REG_PC) |
| 17204 | as_tsktsk (MVE_BAD_PC); |
| 17205 | |
| 17206 | inst.instruction = 0xee310e40; |
| 17207 | inst.instruction |= (et.size == 16) << 28; |
| 17208 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 17209 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; |
| 17210 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 17211 | inst.instruction |= HI1 (inst.operands[1].reg) << 6; |
| 17212 | inst.instruction |= inst.operands[2].reg; |
| 17213 | inst.is_neon = 1; |
| 17214 | return; |
| 17215 | } |
| 17216 | } |
| 17217 | else |
| 17218 | { |
| 17219 | constraint (!inst.operands[2].isvec, BAD_FPU); |
| 17220 | } |
| 17221 | |
| 17222 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); |
| 17223 | } |
| 17224 | |
| 17225 | static void |
| 17226 | do_neon_tst (void) |
| 17227 | { |
| 17228 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
| 17229 | struct neon_type_el et = neon_check_type (3, rs, |
| 17230 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); |
| 17231 | neon_three_same (neon_quad (rs), 0, et.size); |
| 17232 | } |
| 17233 | |
| 17234 | /* VMUL with 3 registers allows the P8 type. The scalar version supports the |
| 17235 | same types as the MAC equivalents. The polynomial type for this instruction |
| 17236 | is encoded the same as the integer type. */ |
| 17237 | |
| 17238 | static void |
| 17239 | do_neon_mul (void) |
| 17240 | { |
| 17241 | if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) |
| 17242 | return; |
| 17243 | |
| 17244 | if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH)) |
| 17245 | return; |
| 17246 | |
| 17247 | if (inst.operands[2].isscalar) |
| 17248 | { |
| 17249 | constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); |
| 17250 | do_neon_mac_maybe_scalar (); |
| 17251 | } |
| 17252 | else |
| 17253 | { |
| 17254 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 17255 | { |
| 17256 | enum neon_shape rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL); |
| 17257 | struct neon_type_el et |
| 17258 | = neon_check_type (3, rs, N_EQK, N_EQK, N_I_MVE | N_F_MVE | N_KEY); |
| 17259 | if (et.type == NT_float) |
| 17260 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext), |
| 17261 | BAD_FPU); |
| 17262 | |
| 17263 | neon_dyadic_misc (NT_float, N_I_MVE | N_F_MVE, 0); |
| 17264 | } |
| 17265 | else |
| 17266 | { |
| 17267 | constraint (!inst.operands[2].isvec, BAD_FPU); |
| 17268 | neon_dyadic_misc (NT_poly, |
| 17269 | N_I8 | N_I16 | N_I32 | N_F16 | N_F32 | N_P8, 0); |
| 17270 | } |
| 17271 | } |
| 17272 | } |
| 17273 | |
| 17274 | static void |
| 17275 | do_neon_qdmulh (void) |
| 17276 | { |
| 17277 | if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
| 17278 | return; |
| 17279 | |
| 17280 | if (inst.operands[2].isscalar) |
| 17281 | { |
| 17282 | constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); |
| 17283 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
| 17284 | struct neon_type_el et = neon_check_type (3, rs, |
| 17285 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); |
| 17286 | NEON_ENCODE (SCALAR, inst); |
| 17287 | neon_mul_mac (et, neon_quad (rs)); |
| 17288 | } |
| 17289 | else |
| 17290 | { |
| 17291 | enum neon_shape rs; |
| 17292 | struct neon_type_el et; |
| 17293 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 17294 | { |
| 17295 | rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL); |
| 17296 | et = neon_check_type (3, rs, |
| 17297 | N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); |
| 17298 | } |
| 17299 | else |
| 17300 | { |
| 17301 | rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
| 17302 | et = neon_check_type (3, rs, |
| 17303 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); |
| 17304 | } |
| 17305 | |
| 17306 | NEON_ENCODE (INTEGER, inst); |
| 17307 | if (rs == NS_QQR) |
| 17308 | mve_encode_qqr (et.size, 0, 0); |
| 17309 | else |
| 17310 | /* The U bit (rounding) comes from bit mask. */ |
| 17311 | neon_three_same (neon_quad (rs), 0, et.size); |
| 17312 | } |
| 17313 | } |
| 17314 | |
| 17315 | static void |
| 17316 | do_mve_vaddv (void) |
| 17317 | { |
| 17318 | enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL); |
| 17319 | struct neon_type_el et |
| 17320 | = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); |
| 17321 | |
| 17322 | if (et.type == NT_invtype) |
| 17323 | first_error (BAD_EL_TYPE); |
| 17324 | |
| 17325 | if (inst.cond > COND_ALWAYS) |
| 17326 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 17327 | else |
| 17328 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 17329 | |
| 17330 | constraint (inst.operands[1].reg > 14, MVE_BAD_QREG); |
| 17331 | |
| 17332 | mve_encode_rq (et.type == NT_unsigned, et.size); |
| 17333 | } |
| 17334 | |
| 17335 | static void |
| 17336 | do_mve_vhcadd (void) |
| 17337 | { |
| 17338 | enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL); |
| 17339 | struct neon_type_el et |
| 17340 | = neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); |
| 17341 | |
| 17342 | if (inst.cond > COND_ALWAYS) |
| 17343 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 17344 | else |
| 17345 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 17346 | |
| 17347 | unsigned rot = inst.relocs[0].exp.X_add_number; |
| 17348 | constraint (rot != 90 && rot != 270, _("immediate out of range")); |
| 17349 | |
| 17350 | if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg) |
| 17351 | as_tsktsk (_("Warning: 32-bit element size and same first and third " |
| 17352 | "operand makes instruction UNPREDICTABLE")); |
| 17353 | |
| 17354 | mve_encode_qqq (0, et.size); |
| 17355 | inst.instruction |= (rot == 270) << 12; |
| 17356 | inst.is_neon = 1; |
| 17357 | } |
| 17358 | |
| 17359 | static void |
| 17360 | do_mve_vqdmull (void) |
| 17361 | { |
| 17362 | enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL); |
| 17363 | struct neon_type_el et |
| 17364 | = neon_check_type (3, rs, N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); |
| 17365 | |
| 17366 | if (et.size == 32 |
| 17367 | && (inst.operands[0].reg == inst.operands[1].reg |
| 17368 | || (rs == NS_QQQ && inst.operands[0].reg == inst.operands[2].reg))) |
| 17369 | as_tsktsk (BAD_MVE_SRCDEST); |
| 17370 | |
| 17371 | if (inst.cond > COND_ALWAYS) |
| 17372 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 17373 | else |
| 17374 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 17375 | |
| 17376 | if (rs == NS_QQQ) |
| 17377 | { |
| 17378 | mve_encode_qqq (et.size == 32, 64); |
| 17379 | inst.instruction |= 1; |
| 17380 | } |
| 17381 | else |
| 17382 | { |
| 17383 | mve_encode_qqr (64, et.size == 32, 0); |
| 17384 | inst.instruction |= 0x3 << 5; |
| 17385 | } |
| 17386 | } |
| 17387 | |
| 17388 | static void |
| 17389 | do_mve_vadc (void) |
| 17390 | { |
| 17391 | enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL); |
| 17392 | struct neon_type_el et |
| 17393 | = neon_check_type (3, rs, N_KEY | N_I32, N_EQK, N_EQK); |
| 17394 | |
| 17395 | if (et.type == NT_invtype) |
| 17396 | first_error (BAD_EL_TYPE); |
| 17397 | |
| 17398 | if (inst.cond > COND_ALWAYS) |
| 17399 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 17400 | else |
| 17401 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 17402 | |
| 17403 | mve_encode_qqq (0, 64); |
| 17404 | } |
| 17405 | |
| 17406 | static void |
| 17407 | do_mve_vbrsr (void) |
| 17408 | { |
| 17409 | enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); |
| 17410 | struct neon_type_el et |
| 17411 | = neon_check_type (3, rs, N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); |
| 17412 | |
| 17413 | if (inst.cond > COND_ALWAYS) |
| 17414 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 17415 | else |
| 17416 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 17417 | |
| 17418 | mve_encode_qqr (et.size, 0, 0); |
| 17419 | } |
| 17420 | |
| 17421 | static void |
| 17422 | do_mve_vsbc (void) |
| 17423 | { |
| 17424 | neon_check_type (3, NS_QQQ, N_EQK, N_EQK, N_I32 | N_KEY); |
| 17425 | |
| 17426 | if (inst.cond > COND_ALWAYS) |
| 17427 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 17428 | else |
| 17429 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 17430 | |
| 17431 | mve_encode_qqq (1, 64); |
| 17432 | } |
| 17433 | |
| 17434 | static void |
| 17435 | do_mve_vmulh (void) |
| 17436 | { |
| 17437 | enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL); |
| 17438 | struct neon_type_el et |
| 17439 | = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY); |
| 17440 | |
| 17441 | if (inst.cond > COND_ALWAYS) |
| 17442 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 17443 | else |
| 17444 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 17445 | |
| 17446 | mve_encode_qqq (et.type == NT_unsigned, et.size); |
| 17447 | } |
| 17448 | |
| 17449 | static void |
| 17450 | do_mve_vqdmlah (void) |
| 17451 | { |
| 17452 | enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); |
| 17453 | struct neon_type_el et |
| 17454 | = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY); |
| 17455 | |
| 17456 | if (inst.cond > COND_ALWAYS) |
| 17457 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 17458 | else |
| 17459 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 17460 | |
| 17461 | mve_encode_qqr (et.size, et.type == NT_unsigned, 0); |
| 17462 | } |
| 17463 | |
| 17464 | static void |
| 17465 | do_mve_vqdmladh (void) |
| 17466 | { |
| 17467 | enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL); |
| 17468 | struct neon_type_el et |
| 17469 | = neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); |
| 17470 | |
| 17471 | if (inst.cond > COND_ALWAYS) |
| 17472 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 17473 | else |
| 17474 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 17475 | |
| 17476 | if (et.size == 32 |
| 17477 | && (inst.operands[0].reg == inst.operands[1].reg |
| 17478 | || inst.operands[0].reg == inst.operands[2].reg)) |
| 17479 | as_tsktsk (BAD_MVE_SRCDEST); |
| 17480 | |
| 17481 | mve_encode_qqq (0, et.size); |
| 17482 | } |
| 17483 | |
| 17484 | |
| 17485 | static void |
| 17486 | do_mve_vmull (void) |
| 17487 | { |
| 17488 | |
| 17489 | enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_DDS, |
| 17490 | NS_QQS, NS_QQQ, NS_QQR, NS_NULL); |
| 17491 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) |
| 17492 | && inst.cond == COND_ALWAYS |
| 17493 | && ((unsigned)inst.instruction) == M_MNEM_vmullt) |
| 17494 | { |
| 17495 | if (rs == NS_QQQ) |
| 17496 | { |
| 17497 | |
| 17498 | struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK, |
| 17499 | N_SUF_32 | N_F64 | N_P8 |
| 17500 | | N_P16 | N_I_MVE | N_KEY); |
| 17501 | if (((et.type == NT_poly) && et.size == 8 |
| 17502 | && ARM_CPU_IS_ANY (cpu_variant)) |
| 17503 | || (et.type == NT_integer) || (et.type == NT_float)) |
| 17504 | goto neon_vmul; |
| 17505 | } |
| 17506 | else |
| 17507 | goto neon_vmul; |
| 17508 | } |
| 17509 | |
| 17510 | constraint (rs != NS_QQQ, BAD_FPU); |
| 17511 | struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK, |
| 17512 | N_SU_32 | N_P8 | N_P16 | N_KEY); |
| 17513 | |
| 17514 | /* We are dealing with MVE's vmullt. */ |
| 17515 | if (et.size == 32 |
| 17516 | && (inst.operands[0].reg == inst.operands[1].reg |
| 17517 | || inst.operands[0].reg == inst.operands[2].reg)) |
| 17518 | as_tsktsk (BAD_MVE_SRCDEST); |
| 17519 | |
| 17520 | if (inst.cond > COND_ALWAYS) |
| 17521 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 17522 | else |
| 17523 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 17524 | |
| 17525 | if (et.type == NT_poly) |
| 17526 | mve_encode_qqq (neon_logbits (et.size), 64); |
| 17527 | else |
| 17528 | mve_encode_qqq (et.type == NT_unsigned, et.size); |
| 17529 | |
| 17530 | return; |
| 17531 | |
| 17532 | neon_vmul: |
| 17533 | inst.instruction = N_MNEM_vmul; |
| 17534 | inst.cond = 0xb; |
| 17535 | if (thumb_mode) |
| 17536 | inst.pred_insn_type = INSIDE_IT_INSN; |
| 17537 | do_neon_mul (); |
| 17538 | } |
| 17539 | |
| 17540 | static void |
| 17541 | do_mve_vabav (void) |
| 17542 | { |
| 17543 | enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL); |
| 17544 | |
| 17545 | if (rs == NS_NULL) |
| 17546 | return; |
| 17547 | |
| 17548 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 17549 | return; |
| 17550 | |
| 17551 | struct neon_type_el et = neon_check_type (2, NS_NULL, N_EQK, N_KEY | N_S8 |
| 17552 | | N_S16 | N_S32 | N_U8 | N_U16 |
| 17553 | | N_U32); |
| 17554 | |
| 17555 | if (inst.cond > COND_ALWAYS) |
| 17556 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 17557 | else |
| 17558 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 17559 | |
| 17560 | mve_encode_rqq (et.type == NT_unsigned, et.size); |
| 17561 | } |
| 17562 | |
| 17563 | static void |
| 17564 | do_mve_vmladav (void) |
| 17565 | { |
| 17566 | enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL); |
| 17567 | struct neon_type_el et = neon_check_type (3, rs, |
| 17568 | N_EQK, N_EQK, N_SU_MVE | N_KEY); |
| 17569 | |
| 17570 | if (et.type == NT_unsigned |
| 17571 | && (inst.instruction == M_MNEM_vmladavx |
| 17572 | || inst.instruction == M_MNEM_vmladavax |
| 17573 | || inst.instruction == M_MNEM_vmlsdav |
| 17574 | || inst.instruction == M_MNEM_vmlsdava |
| 17575 | || inst.instruction == M_MNEM_vmlsdavx |
| 17576 | || inst.instruction == M_MNEM_vmlsdavax)) |
| 17577 | first_error (BAD_SIMD_TYPE); |
| 17578 | |
| 17579 | constraint (inst.operands[2].reg > 14, |
| 17580 | _("MVE vector register in the range [Q0..Q7] expected")); |
| 17581 | |
| 17582 | if (inst.cond > COND_ALWAYS) |
| 17583 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 17584 | else |
| 17585 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 17586 | |
| 17587 | if (inst.instruction == M_MNEM_vmlsdav |
| 17588 | || inst.instruction == M_MNEM_vmlsdava |
| 17589 | || inst.instruction == M_MNEM_vmlsdavx |
| 17590 | || inst.instruction == M_MNEM_vmlsdavax) |
| 17591 | inst.instruction |= (et.size == 8) << 28; |
| 17592 | else |
| 17593 | inst.instruction |= (et.size == 8) << 8; |
| 17594 | |
| 17595 | mve_encode_rqq (et.type == NT_unsigned, 64); |
| 17596 | inst.instruction |= (et.size == 32) << 16; |
| 17597 | } |
| 17598 | |
| 17599 | static void |
| 17600 | do_mve_vmlaldav (void) |
| 17601 | { |
| 17602 | enum neon_shape rs = neon_select_shape (NS_RRQQ, NS_NULL); |
| 17603 | struct neon_type_el et |
| 17604 | = neon_check_type (4, rs, N_EQK, N_EQK, N_EQK, |
| 17605 | N_S16 | N_S32 | N_U16 | N_U32 | N_KEY); |
| 17606 | |
| 17607 | if (et.type == NT_unsigned |
| 17608 | && (inst.instruction == M_MNEM_vmlsldav |
| 17609 | || inst.instruction == M_MNEM_vmlsldava |
| 17610 | || inst.instruction == M_MNEM_vmlsldavx |
| 17611 | || inst.instruction == M_MNEM_vmlsldavax)) |
| 17612 | first_error (BAD_SIMD_TYPE); |
| 17613 | |
| 17614 | if (inst.cond > COND_ALWAYS) |
| 17615 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 17616 | else |
| 17617 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 17618 | |
| 17619 | mve_encode_rrqq (et.type == NT_unsigned, et.size); |
| 17620 | } |
| 17621 | |
| 17622 | static void |
| 17623 | do_mve_vrmlaldavh (void) |
| 17624 | { |
| 17625 | struct neon_type_el et; |
| 17626 | if (inst.instruction == M_MNEM_vrmlsldavh |
| 17627 | || inst.instruction == M_MNEM_vrmlsldavha |
| 17628 | || inst.instruction == M_MNEM_vrmlsldavhx |
| 17629 | || inst.instruction == M_MNEM_vrmlsldavhax) |
| 17630 | { |
| 17631 | et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY); |
| 17632 | if (inst.operands[1].reg == REG_SP) |
| 17633 | as_tsktsk (MVE_BAD_SP); |
| 17634 | } |
| 17635 | else |
| 17636 | { |
| 17637 | if (inst.instruction == M_MNEM_vrmlaldavhx |
| 17638 | || inst.instruction == M_MNEM_vrmlaldavhax) |
| 17639 | et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY); |
| 17640 | else |
| 17641 | et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, |
| 17642 | N_U32 | N_S32 | N_KEY); |
| 17643 | /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias |
| 17644 | with vmax/min instructions, making the use of SP in assembly really |
| 17645 | nonsensical, so instead of issuing a warning like we do for other uses |
| 17646 | of SP for the odd register operand we error out. */ |
| 17647 | constraint (inst.operands[1].reg == REG_SP, BAD_SP); |
| 17648 | } |
| 17649 | |
| 17650 | /* Make sure we still check the second operand is an odd one and that PC is |
| 17651 | disallowed. This because we are parsing for any GPR operand, to be able |
| 17652 | to distinguish between giving a warning or an error for SP as described |
| 17653 | above. */ |
| 17654 | constraint ((inst.operands[1].reg % 2) != 1, BAD_EVEN); |
| 17655 | constraint (inst.operands[1].reg == REG_PC, BAD_PC); |
| 17656 | |
| 17657 | if (inst.cond > COND_ALWAYS) |
| 17658 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 17659 | else |
| 17660 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 17661 | |
| 17662 | mve_encode_rrqq (et.type == NT_unsigned, 0); |
| 17663 | } |
| 17664 | |
| 17665 | |
| 17666 | static void |
| 17667 | do_mve_vmaxnmv (void) |
| 17668 | { |
| 17669 | enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL); |
| 17670 | struct neon_type_el et |
| 17671 | = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY); |
| 17672 | |
| 17673 | if (inst.cond > COND_ALWAYS) |
| 17674 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 17675 | else |
| 17676 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 17677 | |
| 17678 | if (inst.operands[0].reg == REG_SP) |
| 17679 | as_tsktsk (MVE_BAD_SP); |
| 17680 | else if (inst.operands[0].reg == REG_PC) |
| 17681 | as_tsktsk (MVE_BAD_PC); |
| 17682 | |
| 17683 | mve_encode_rq (et.size == 16, 64); |
| 17684 | } |
| 17685 | |
| 17686 | static void |
| 17687 | do_mve_vmaxv (void) |
| 17688 | { |
| 17689 | enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL); |
| 17690 | struct neon_type_el et; |
| 17691 | |
| 17692 | if (inst.instruction == M_MNEM_vmaxv || inst.instruction == M_MNEM_vminv) |
| 17693 | et = neon_check_type (2, rs, N_EQK, N_SU_MVE | N_KEY); |
| 17694 | else |
| 17695 | et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); |
| 17696 | |
| 17697 | if (inst.cond > COND_ALWAYS) |
| 17698 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 17699 | else |
| 17700 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 17701 | |
| 17702 | if (inst.operands[0].reg == REG_SP) |
| 17703 | as_tsktsk (MVE_BAD_SP); |
| 17704 | else if (inst.operands[0].reg == REG_PC) |
| 17705 | as_tsktsk (MVE_BAD_PC); |
| 17706 | |
| 17707 | mve_encode_rq (et.type == NT_unsigned, et.size); |
| 17708 | } |
| 17709 | |
| 17710 | |
| 17711 | static void |
| 17712 | do_neon_qrdmlah (void) |
| 17713 | { |
| 17714 | if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
| 17715 | return; |
| 17716 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 17717 | { |
| 17718 | /* Check we're on the correct architecture. */ |
| 17719 | if (!mark_feature_used (&fpu_neon_ext_armv8)) |
| 17720 | inst.error |
| 17721 | = _("instruction form not available on this architecture."); |
| 17722 | else if (!mark_feature_used (&fpu_neon_ext_v8_1)) |
| 17723 | { |
| 17724 | as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD.")); |
| 17725 | record_feature_use (&fpu_neon_ext_v8_1); |
| 17726 | } |
| 17727 | if (inst.operands[2].isscalar) |
| 17728 | { |
| 17729 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
| 17730 | struct neon_type_el et = neon_check_type (3, rs, |
| 17731 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); |
| 17732 | NEON_ENCODE (SCALAR, inst); |
| 17733 | neon_mul_mac (et, neon_quad (rs)); |
| 17734 | } |
| 17735 | else |
| 17736 | { |
| 17737 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
| 17738 | struct neon_type_el et = neon_check_type (3, rs, |
| 17739 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); |
| 17740 | NEON_ENCODE (INTEGER, inst); |
| 17741 | /* The U bit (rounding) comes from bit mask. */ |
| 17742 | neon_three_same (neon_quad (rs), 0, et.size); |
| 17743 | } |
| 17744 | } |
| 17745 | else |
| 17746 | { |
| 17747 | enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); |
| 17748 | struct neon_type_el et |
| 17749 | = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY); |
| 17750 | |
| 17751 | NEON_ENCODE (INTEGER, inst); |
| 17752 | mve_encode_qqr (et.size, et.type == NT_unsigned, 0); |
| 17753 | } |
| 17754 | } |
| 17755 | |
| 17756 | static void |
| 17757 | do_neon_fcmp_absolute (void) |
| 17758 | { |
| 17759 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
| 17760 | struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK, |
| 17761 | N_F_16_32 | N_KEY); |
| 17762 | /* Size field comes from bit mask. */ |
| 17763 | neon_three_same (neon_quad (rs), 1, et.size == 16 ? (int) et.size : -1); |
| 17764 | } |
| 17765 | |
| 17766 | static void |
| 17767 | do_neon_fcmp_absolute_inv (void) |
| 17768 | { |
| 17769 | neon_exchange_operands (); |
| 17770 | do_neon_fcmp_absolute (); |
| 17771 | } |
| 17772 | |
| 17773 | static void |
| 17774 | do_neon_step (void) |
| 17775 | { |
| 17776 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
| 17777 | struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK, |
| 17778 | N_F_16_32 | N_KEY); |
| 17779 | neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1); |
| 17780 | } |
| 17781 | |
| 17782 | static void |
| 17783 | do_neon_abs_neg (void) |
| 17784 | { |
| 17785 | enum neon_shape rs; |
| 17786 | struct neon_type_el et; |
| 17787 | |
| 17788 | if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) |
| 17789 | return; |
| 17790 | |
| 17791 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
| 17792 | et = neon_check_type (2, rs, N_EQK, N_S_32 | N_F_16_32 | N_KEY); |
| 17793 | |
| 17794 | if (check_simd_pred_availability (et.type == NT_float, |
| 17795 | NEON_CHECK_ARCH | NEON_CHECK_CC)) |
| 17796 | return; |
| 17797 | |
| 17798 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 17799 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 17800 | inst.instruction |= LOW4 (inst.operands[1].reg); |
| 17801 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; |
| 17802 | inst.instruction |= neon_quad (rs) << 6; |
| 17803 | inst.instruction |= (et.type == NT_float) << 10; |
| 17804 | inst.instruction |= neon_logbits (et.size) << 18; |
| 17805 | |
| 17806 | neon_dp_fixup (&inst); |
| 17807 | } |
| 17808 | |
| 17809 | static void |
| 17810 | do_neon_sli (void) |
| 17811 | { |
| 17812 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
| 17813 | struct neon_type_el et = neon_check_type (2, rs, |
| 17814 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); |
| 17815 | int imm = inst.operands[2].imm; |
| 17816 | constraint (imm < 0 || (unsigned)imm >= et.size, |
| 17817 | _("immediate out of range for insert")); |
| 17818 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
| 17819 | } |
| 17820 | |
| 17821 | static void |
| 17822 | do_neon_sri (void) |
| 17823 | { |
| 17824 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
| 17825 | struct neon_type_el et = neon_check_type (2, rs, |
| 17826 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); |
| 17827 | int imm = inst.operands[2].imm; |
| 17828 | constraint (imm < 1 || (unsigned)imm > et.size, |
| 17829 | _("immediate out of range for insert")); |
| 17830 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); |
| 17831 | } |
| 17832 | |
| 17833 | static void |
| 17834 | do_neon_qshlu_imm (void) |
| 17835 | { |
| 17836 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
| 17837 | struct neon_type_el et = neon_check_type (2, rs, |
| 17838 | N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); |
| 17839 | int imm = inst.operands[2].imm; |
| 17840 | constraint (imm < 0 || (unsigned)imm >= et.size, |
| 17841 | _("immediate out of range for shift")); |
| 17842 | /* Only encodes the 'U present' variant of the instruction. |
| 17843 | In this case, signed types have OP (bit 8) set to 0. |
| 17844 | Unsigned types have OP set to 1. */ |
| 17845 | inst.instruction |= (et.type == NT_unsigned) << 8; |
| 17846 | /* The rest of the bits are the same as other immediate shifts. */ |
| 17847 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
| 17848 | } |
| 17849 | |
| 17850 | static void |
| 17851 | do_neon_qmovn (void) |
| 17852 | { |
| 17853 | struct neon_type_el et = neon_check_type (2, NS_DQ, |
| 17854 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); |
| 17855 | /* Saturating move where operands can be signed or unsigned, and the |
| 17856 | destination has the same signedness. */ |
| 17857 | NEON_ENCODE (INTEGER, inst); |
| 17858 | if (et.type == NT_unsigned) |
| 17859 | inst.instruction |= 0xc0; |
| 17860 | else |
| 17861 | inst.instruction |= 0x80; |
| 17862 | neon_two_same (0, 1, et.size / 2); |
| 17863 | } |
| 17864 | |
| 17865 | static void |
| 17866 | do_neon_qmovun (void) |
| 17867 | { |
| 17868 | struct neon_type_el et = neon_check_type (2, NS_DQ, |
| 17869 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); |
| 17870 | /* Saturating move with unsigned results. Operands must be signed. */ |
| 17871 | NEON_ENCODE (INTEGER, inst); |
| 17872 | neon_two_same (0, 1, et.size / 2); |
| 17873 | } |
| 17874 | |
| 17875 | static void |
| 17876 | do_neon_rshift_sat_narrow (void) |
| 17877 | { |
| 17878 | /* FIXME: Types for narrowing. If operands are signed, results can be signed |
| 17879 | or unsigned. If operands are unsigned, results must also be unsigned. */ |
| 17880 | struct neon_type_el et = neon_check_type (2, NS_DQI, |
| 17881 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); |
| 17882 | int imm = inst.operands[2].imm; |
| 17883 | /* This gets the bounds check, size encoding and immediate bits calculation |
| 17884 | right. */ |
| 17885 | et.size /= 2; |
| 17886 | |
| 17887 | /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for |
| 17888 | VQMOVN.I<size> <Dd>, <Qm>. */ |
| 17889 | if (imm == 0) |
| 17890 | { |
| 17891 | inst.operands[2].present = 0; |
| 17892 | inst.instruction = N_MNEM_vqmovn; |
| 17893 | do_neon_qmovn (); |
| 17894 | return; |
| 17895 | } |
| 17896 | |
| 17897 | constraint (imm < 1 || (unsigned)imm > et.size, |
| 17898 | _("immediate out of range")); |
| 17899 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); |
| 17900 | } |
| 17901 | |
| 17902 | static void |
| 17903 | do_neon_rshift_sat_narrow_u (void) |
| 17904 | { |
| 17905 | /* FIXME: Types for narrowing. If operands are signed, results can be signed |
| 17906 | or unsigned. If operands are unsigned, results must also be unsigned. */ |
| 17907 | struct neon_type_el et = neon_check_type (2, NS_DQI, |
| 17908 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); |
| 17909 | int imm = inst.operands[2].imm; |
| 17910 | /* This gets the bounds check, size encoding and immediate bits calculation |
| 17911 | right. */ |
| 17912 | et.size /= 2; |
| 17913 | |
| 17914 | /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for |
| 17915 | VQMOVUN.I<size> <Dd>, <Qm>. */ |
| 17916 | if (imm == 0) |
| 17917 | { |
| 17918 | inst.operands[2].present = 0; |
| 17919 | inst.instruction = N_MNEM_vqmovun; |
| 17920 | do_neon_qmovun (); |
| 17921 | return; |
| 17922 | } |
| 17923 | |
| 17924 | constraint (imm < 1 || (unsigned)imm > et.size, |
| 17925 | _("immediate out of range")); |
| 17926 | /* FIXME: The manual is kind of unclear about what value U should have in |
| 17927 | VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it |
| 17928 | must be 1. */ |
| 17929 | neon_imm_shift (TRUE, 1, 0, et, et.size - imm); |
| 17930 | } |
| 17931 | |
| 17932 | static void |
| 17933 | do_neon_movn (void) |
| 17934 | { |
| 17935 | struct neon_type_el et = neon_check_type (2, NS_DQ, |
| 17936 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); |
| 17937 | NEON_ENCODE (INTEGER, inst); |
| 17938 | neon_two_same (0, 1, et.size / 2); |
| 17939 | } |
| 17940 | |
| 17941 | static void |
| 17942 | do_neon_rshift_narrow (void) |
| 17943 | { |
| 17944 | struct neon_type_el et = neon_check_type (2, NS_DQI, |
| 17945 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); |
| 17946 | int imm = inst.operands[2].imm; |
| 17947 | /* This gets the bounds check, size encoding and immediate bits calculation |
| 17948 | right. */ |
| 17949 | et.size /= 2; |
| 17950 | |
| 17951 | /* If immediate is zero then we are a pseudo-instruction for |
| 17952 | VMOVN.I<size> <Dd>, <Qm> */ |
| 17953 | if (imm == 0) |
| 17954 | { |
| 17955 | inst.operands[2].present = 0; |
| 17956 | inst.instruction = N_MNEM_vmovn; |
| 17957 | do_neon_movn (); |
| 17958 | return; |
| 17959 | } |
| 17960 | |
| 17961 | constraint (imm < 1 || (unsigned)imm > et.size, |
| 17962 | _("immediate out of range for narrowing operation")); |
| 17963 | neon_imm_shift (FALSE, 0, 0, et, et.size - imm); |
| 17964 | } |
| 17965 | |
| 17966 | static void |
| 17967 | do_neon_shll (void) |
| 17968 | { |
| 17969 | /* FIXME: Type checking when lengthening. */ |
| 17970 | struct neon_type_el et = neon_check_type (2, NS_QDI, |
| 17971 | N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); |
| 17972 | unsigned imm = inst.operands[2].imm; |
| 17973 | |
| 17974 | if (imm == et.size) |
| 17975 | { |
| 17976 | /* Maximum shift variant. */ |
| 17977 | NEON_ENCODE (INTEGER, inst); |
| 17978 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 17979 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 17980 | inst.instruction |= LOW4 (inst.operands[1].reg); |
| 17981 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; |
| 17982 | inst.instruction |= neon_logbits (et.size) << 18; |
| 17983 | |
| 17984 | neon_dp_fixup (&inst); |
| 17985 | } |
| 17986 | else |
| 17987 | { |
| 17988 | /* A more-specific type check for non-max versions. */ |
| 17989 | et = neon_check_type (2, NS_QDI, |
| 17990 | N_EQK | N_DBL, N_SU_32 | N_KEY); |
| 17991 | NEON_ENCODE (IMMED, inst); |
| 17992 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); |
| 17993 | } |
| 17994 | } |
| 17995 | |
| 17996 | /* Check the various types for the VCVT instruction, and return which version |
| 17997 | the current instruction is. */ |
| 17998 | |
| 17999 | #define CVT_FLAVOUR_VAR \ |
| 18000 | CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \ |
| 18001 | CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \ |
| 18002 | CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \ |
| 18003 | CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \ |
| 18004 | /* Half-precision conversions. */ \ |
| 18005 | CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \ |
| 18006 | CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \ |
| 18007 | CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \ |
| 18008 | CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \ |
| 18009 | CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \ |
| 18010 | CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \ |
| 18011 | /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \ |
| 18012 | Compared with single/double precision variants, only the co-processor \ |
| 18013 | field is different, so the encoding flow is reused here. */ \ |
| 18014 | CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \ |
| 18015 | CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \ |
| 18016 | CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\ |
| 18017 | CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\ |
| 18018 | /* VFP instructions. */ \ |
| 18019 | CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \ |
| 18020 | CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \ |
| 18021 | CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \ |
| 18022 | CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \ |
| 18023 | CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \ |
| 18024 | CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \ |
| 18025 | /* VFP instructions with bitshift. */ \ |
| 18026 | CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \ |
| 18027 | CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \ |
| 18028 | CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \ |
| 18029 | CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \ |
| 18030 | CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \ |
| 18031 | CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \ |
| 18032 | CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \ |
| 18033 | CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL) |
| 18034 | |
| 18035 | #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \ |
| 18036 | neon_cvt_flavour_##C, |
| 18037 | |
| 18038 | /* The different types of conversions we can do. */ |
| 18039 | enum neon_cvt_flavour |
| 18040 | { |
| 18041 | CVT_FLAVOUR_VAR |
| 18042 | neon_cvt_flavour_invalid, |
| 18043 | neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64 |
| 18044 | }; |
| 18045 | |
| 18046 | #undef CVT_VAR |
| 18047 | |
| 18048 | static enum neon_cvt_flavour |
| 18049 | get_neon_cvt_flavour (enum neon_shape rs) |
| 18050 | { |
| 18051 | #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \ |
| 18052 | et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \ |
| 18053 | if (et.type != NT_invtype) \ |
| 18054 | { \ |
| 18055 | inst.error = NULL; \ |
| 18056 | return (neon_cvt_flavour_##C); \ |
| 18057 | } |
| 18058 | |
| 18059 | struct neon_type_el et; |
| 18060 | unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF |
| 18061 | || rs == NS_FF) ? N_VFP : 0; |
| 18062 | /* The instruction versions which take an immediate take one register |
| 18063 | argument, which is extended to the width of the full register. Thus the |
| 18064 | "source" and "destination" registers must have the same width. Hack that |
| 18065 | here by making the size equal to the key (wider, in this case) operand. */ |
| 18066 | unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; |
| 18067 | |
| 18068 | CVT_FLAVOUR_VAR; |
| 18069 | |
| 18070 | return neon_cvt_flavour_invalid; |
| 18071 | #undef CVT_VAR |
| 18072 | } |
| 18073 | |
| 18074 | enum neon_cvt_mode |
| 18075 | { |
| 18076 | neon_cvt_mode_a, |
| 18077 | neon_cvt_mode_n, |
| 18078 | neon_cvt_mode_p, |
| 18079 | neon_cvt_mode_m, |
| 18080 | neon_cvt_mode_z, |
| 18081 | neon_cvt_mode_x, |
| 18082 | neon_cvt_mode_r |
| 18083 | }; |
| 18084 | |
| 18085 | /* Neon-syntax VFP conversions. */ |
| 18086 | |
| 18087 | static void |
| 18088 | do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour) |
| 18089 | { |
| 18090 | const char *opname = 0; |
| 18091 | |
| 18092 | if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI |
| 18093 | || rs == NS_FHI || rs == NS_HFI) |
| 18094 | { |
| 18095 | /* Conversions with immediate bitshift. */ |
| 18096 | const char *enc[] = |
| 18097 | { |
| 18098 | #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN, |
| 18099 | CVT_FLAVOUR_VAR |
| 18100 | NULL |
| 18101 | #undef CVT_VAR |
| 18102 | }; |
| 18103 | |
| 18104 | if (flavour < (int) ARRAY_SIZE (enc)) |
| 18105 | { |
| 18106 | opname = enc[flavour]; |
| 18107 | constraint (inst.operands[0].reg != inst.operands[1].reg, |
| 18108 | _("operands 0 and 1 must be the same register")); |
| 18109 | inst.operands[1] = inst.operands[2]; |
| 18110 | memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); |
| 18111 | } |
| 18112 | } |
| 18113 | else |
| 18114 | { |
| 18115 | /* Conversions without bitshift. */ |
| 18116 | const char *enc[] = |
| 18117 | { |
| 18118 | #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN, |
| 18119 | CVT_FLAVOUR_VAR |
| 18120 | NULL |
| 18121 | #undef CVT_VAR |
| 18122 | }; |
| 18123 | |
| 18124 | if (flavour < (int) ARRAY_SIZE (enc)) |
| 18125 | opname = enc[flavour]; |
| 18126 | } |
| 18127 | |
| 18128 | if (opname) |
| 18129 | do_vfp_nsyn_opcode (opname); |
| 18130 | |
| 18131 | /* ARMv8.2 fp16 VCVT instruction. */ |
| 18132 | if (flavour == neon_cvt_flavour_s32_f16 |
| 18133 | || flavour == neon_cvt_flavour_u32_f16 |
| 18134 | || flavour == neon_cvt_flavour_f16_u32 |
| 18135 | || flavour == neon_cvt_flavour_f16_s32) |
| 18136 | do_scalar_fp16_v82_encode (); |
| 18137 | } |
| 18138 | |
| 18139 | static void |
| 18140 | do_vfp_nsyn_cvtz (void) |
| 18141 | { |
| 18142 | enum neon_shape rs = neon_select_shape (NS_FH, NS_FF, NS_FD, NS_NULL); |
| 18143 | enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs); |
| 18144 | const char *enc[] = |
| 18145 | { |
| 18146 | #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN, |
| 18147 | CVT_FLAVOUR_VAR |
| 18148 | NULL |
| 18149 | #undef CVT_VAR |
| 18150 | }; |
| 18151 | |
| 18152 | if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) |
| 18153 | do_vfp_nsyn_opcode (enc[flavour]); |
| 18154 | } |
| 18155 | |
| 18156 | static void |
| 18157 | do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour, |
| 18158 | enum neon_cvt_mode mode) |
| 18159 | { |
| 18160 | int sz, op; |
| 18161 | int rm; |
| 18162 | |
| 18163 | /* Targets like FPv5-SP-D16 don't support FP v8 instructions with |
| 18164 | D register operands. */ |
| 18165 | if (flavour == neon_cvt_flavour_s32_f64 |
| 18166 | || flavour == neon_cvt_flavour_u32_f64) |
| 18167 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), |
| 18168 | _(BAD_FPU)); |
| 18169 | |
| 18170 | if (flavour == neon_cvt_flavour_s32_f16 |
| 18171 | || flavour == neon_cvt_flavour_u32_f16) |
| 18172 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16), |
| 18173 | _(BAD_FP16)); |
| 18174 | |
| 18175 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
| 18176 | |
| 18177 | switch (flavour) |
| 18178 | { |
| 18179 | case neon_cvt_flavour_s32_f64: |
| 18180 | sz = 1; |
| 18181 | op = 1; |
| 18182 | break; |
| 18183 | case neon_cvt_flavour_s32_f32: |
| 18184 | sz = 0; |
| 18185 | op = 1; |
| 18186 | break; |
| 18187 | case neon_cvt_flavour_s32_f16: |
| 18188 | sz = 0; |
| 18189 | op = 1; |
| 18190 | break; |
| 18191 | case neon_cvt_flavour_u32_f64: |
| 18192 | sz = 1; |
| 18193 | op = 0; |
| 18194 | break; |
| 18195 | case neon_cvt_flavour_u32_f32: |
| 18196 | sz = 0; |
| 18197 | op = 0; |
| 18198 | break; |
| 18199 | case neon_cvt_flavour_u32_f16: |
| 18200 | sz = 0; |
| 18201 | op = 0; |
| 18202 | break; |
| 18203 | default: |
| 18204 | first_error (_("invalid instruction shape")); |
| 18205 | return; |
| 18206 | } |
| 18207 | |
| 18208 | switch (mode) |
| 18209 | { |
| 18210 | case neon_cvt_mode_a: rm = 0; break; |
| 18211 | case neon_cvt_mode_n: rm = 1; break; |
| 18212 | case neon_cvt_mode_p: rm = 2; break; |
| 18213 | case neon_cvt_mode_m: rm = 3; break; |
| 18214 | default: first_error (_("invalid rounding mode")); return; |
| 18215 | } |
| 18216 | |
| 18217 | NEON_ENCODE (FPV8, inst); |
| 18218 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
| 18219 | encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm); |
| 18220 | inst.instruction |= sz << 8; |
| 18221 | |
| 18222 | /* ARMv8.2 fp16 VCVT instruction. */ |
| 18223 | if (flavour == neon_cvt_flavour_s32_f16 |
| 18224 | ||flavour == neon_cvt_flavour_u32_f16) |
| 18225 | do_scalar_fp16_v82_encode (); |
| 18226 | inst.instruction |= op << 7; |
| 18227 | inst.instruction |= rm << 16; |
| 18228 | inst.instruction |= 0xf0000000; |
| 18229 | inst.is_neon = TRUE; |
| 18230 | } |
| 18231 | |
| 18232 | static void |
| 18233 | do_neon_cvt_1 (enum neon_cvt_mode mode) |
| 18234 | { |
| 18235 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, |
| 18236 | NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, |
| 18237 | NS_FH, NS_HF, NS_FHI, NS_HFI, |
| 18238 | NS_NULL); |
| 18239 | enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs); |
| 18240 | |
| 18241 | if (flavour == neon_cvt_flavour_invalid) |
| 18242 | return; |
| 18243 | |
| 18244 | /* PR11109: Handle round-to-zero for VCVT conversions. */ |
| 18245 | if (mode == neon_cvt_mode_z |
| 18246 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2) |
| 18247 | && (flavour == neon_cvt_flavour_s16_f16 |
| 18248 | || flavour == neon_cvt_flavour_u16_f16 |
| 18249 | || flavour == neon_cvt_flavour_s32_f32 |
| 18250 | || flavour == neon_cvt_flavour_u32_f32 |
| 18251 | || flavour == neon_cvt_flavour_s32_f64 |
| 18252 | || flavour == neon_cvt_flavour_u32_f64) |
| 18253 | && (rs == NS_FD || rs == NS_FF)) |
| 18254 | { |
| 18255 | do_vfp_nsyn_cvtz (); |
| 18256 | return; |
| 18257 | } |
| 18258 | |
| 18259 | /* ARMv8.2 fp16 VCVT conversions. */ |
| 18260 | if (mode == neon_cvt_mode_z |
| 18261 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16) |
| 18262 | && (flavour == neon_cvt_flavour_s32_f16 |
| 18263 | || flavour == neon_cvt_flavour_u32_f16) |
| 18264 | && (rs == NS_FH)) |
| 18265 | { |
| 18266 | do_vfp_nsyn_cvtz (); |
| 18267 | do_scalar_fp16_v82_encode (); |
| 18268 | return; |
| 18269 | } |
| 18270 | |
| 18271 | /* VFP rather than Neon conversions. */ |
| 18272 | if (flavour >= neon_cvt_flavour_first_fp) |
| 18273 | { |
| 18274 | if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z) |
| 18275 | do_vfp_nsyn_cvt (rs, flavour); |
| 18276 | else |
| 18277 | do_vfp_nsyn_cvt_fpv8 (flavour, mode); |
| 18278 | |
| 18279 | return; |
| 18280 | } |
| 18281 | |
| 18282 | switch (rs) |
| 18283 | { |
| 18284 | case NS_QQI: |
| 18285 | if (mode == neon_cvt_mode_z |
| 18286 | && (flavour == neon_cvt_flavour_f16_s16 |
| 18287 | || flavour == neon_cvt_flavour_f16_u16 |
| 18288 | || flavour == neon_cvt_flavour_s16_f16 |
| 18289 | || flavour == neon_cvt_flavour_u16_f16 |
| 18290 | || flavour == neon_cvt_flavour_f32_u32 |
| 18291 | || flavour == neon_cvt_flavour_f32_s32 |
| 18292 | || flavour == neon_cvt_flavour_s32_f32 |
| 18293 | || flavour == neon_cvt_flavour_u32_f32)) |
| 18294 | { |
| 18295 | if (check_simd_pred_availability (1, NEON_CHECK_CC | NEON_CHECK_ARCH)) |
| 18296 | return; |
| 18297 | } |
| 18298 | else if (mode == neon_cvt_mode_n) |
| 18299 | { |
| 18300 | /* We are dealing with vcvt with the 'ne' condition. */ |
| 18301 | inst.cond = 0x1; |
| 18302 | inst.instruction = N_MNEM_vcvt; |
| 18303 | do_neon_cvt_1 (neon_cvt_mode_z); |
| 18304 | return; |
| 18305 | } |
| 18306 | /* fall through. */ |
| 18307 | case NS_DDI: |
| 18308 | { |
| 18309 | unsigned immbits; |
| 18310 | unsigned enctab[] = {0x0000100, 0x1000100, 0x0, 0x1000000, |
| 18311 | 0x0000100, 0x1000100, 0x0, 0x1000000}; |
| 18312 | |
| 18313 | if ((rs != NS_QQI || !ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)) |
| 18314 | && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
| 18315 | return; |
| 18316 | |
| 18317 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)) |
| 18318 | { |
| 18319 | constraint (inst.operands[2].present && inst.operands[2].imm == 0, |
| 18320 | _("immediate value out of range")); |
| 18321 | switch (flavour) |
| 18322 | { |
| 18323 | case neon_cvt_flavour_f16_s16: |
| 18324 | case neon_cvt_flavour_f16_u16: |
| 18325 | case neon_cvt_flavour_s16_f16: |
| 18326 | case neon_cvt_flavour_u16_f16: |
| 18327 | constraint (inst.operands[2].imm > 16, |
| 18328 | _("immediate value out of range")); |
| 18329 | break; |
| 18330 | case neon_cvt_flavour_f32_u32: |
| 18331 | case neon_cvt_flavour_f32_s32: |
| 18332 | case neon_cvt_flavour_s32_f32: |
| 18333 | case neon_cvt_flavour_u32_f32: |
| 18334 | constraint (inst.operands[2].imm > 32, |
| 18335 | _("immediate value out of range")); |
| 18336 | break; |
| 18337 | default: |
| 18338 | inst.error = BAD_FPU; |
| 18339 | return; |
| 18340 | } |
| 18341 | } |
| 18342 | |
| 18343 | /* Fixed-point conversion with #0 immediate is encoded as an |
| 18344 | integer conversion. */ |
| 18345 | if (inst.operands[2].present && inst.operands[2].imm == 0) |
| 18346 | goto int_encode; |
| 18347 | NEON_ENCODE (IMMED, inst); |
| 18348 | if (flavour != neon_cvt_flavour_invalid) |
| 18349 | inst.instruction |= enctab[flavour]; |
| 18350 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 18351 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 18352 | inst.instruction |= LOW4 (inst.operands[1].reg); |
| 18353 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; |
| 18354 | inst.instruction |= neon_quad (rs) << 6; |
| 18355 | inst.instruction |= 1 << 21; |
| 18356 | if (flavour < neon_cvt_flavour_s16_f16) |
| 18357 | { |
| 18358 | inst.instruction |= 1 << 21; |
| 18359 | immbits = 32 - inst.operands[2].imm; |
| 18360 | inst.instruction |= immbits << 16; |
| 18361 | } |
| 18362 | else |
| 18363 | { |
| 18364 | inst.instruction |= 3 << 20; |
| 18365 | immbits = 16 - inst.operands[2].imm; |
| 18366 | inst.instruction |= immbits << 16; |
| 18367 | inst.instruction &= ~(1 << 9); |
| 18368 | } |
| 18369 | |
| 18370 | neon_dp_fixup (&inst); |
| 18371 | } |
| 18372 | break; |
| 18373 | |
| 18374 | case NS_QQ: |
| 18375 | if ((mode == neon_cvt_mode_a || mode == neon_cvt_mode_n |
| 18376 | || mode == neon_cvt_mode_m || mode == neon_cvt_mode_p) |
| 18377 | && (flavour == neon_cvt_flavour_s16_f16 |
| 18378 | || flavour == neon_cvt_flavour_u16_f16 |
| 18379 | || flavour == neon_cvt_flavour_s32_f32 |
| 18380 | || flavour == neon_cvt_flavour_u32_f32)) |
| 18381 | { |
| 18382 | if (check_simd_pred_availability (1, |
| 18383 | NEON_CHECK_CC | NEON_CHECK_ARCH8)) |
| 18384 | return; |
| 18385 | } |
| 18386 | else if (mode == neon_cvt_mode_z |
| 18387 | && (flavour == neon_cvt_flavour_f16_s16 |
| 18388 | || flavour == neon_cvt_flavour_f16_u16 |
| 18389 | || flavour == neon_cvt_flavour_s16_f16 |
| 18390 | || flavour == neon_cvt_flavour_u16_f16 |
| 18391 | || flavour == neon_cvt_flavour_f32_u32 |
| 18392 | || flavour == neon_cvt_flavour_f32_s32 |
| 18393 | || flavour == neon_cvt_flavour_s32_f32 |
| 18394 | || flavour == neon_cvt_flavour_u32_f32)) |
| 18395 | { |
| 18396 | if (check_simd_pred_availability (1, |
| 18397 | NEON_CHECK_CC | NEON_CHECK_ARCH)) |
| 18398 | return; |
| 18399 | } |
| 18400 | /* fall through. */ |
| 18401 | case NS_DD: |
| 18402 | if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z) |
| 18403 | { |
| 18404 | |
| 18405 | NEON_ENCODE (FLOAT, inst); |
| 18406 | if (check_simd_pred_availability (1, |
| 18407 | NEON_CHECK_CC | NEON_CHECK_ARCH8)) |
| 18408 | return; |
| 18409 | |
| 18410 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 18411 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 18412 | inst.instruction |= LOW4 (inst.operands[1].reg); |
| 18413 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; |
| 18414 | inst.instruction |= neon_quad (rs) << 6; |
| 18415 | inst.instruction |= (flavour == neon_cvt_flavour_u16_f16 |
| 18416 | || flavour == neon_cvt_flavour_u32_f32) << 7; |
| 18417 | inst.instruction |= mode << 8; |
| 18418 | if (flavour == neon_cvt_flavour_u16_f16 |
| 18419 | || flavour == neon_cvt_flavour_s16_f16) |
| 18420 | /* Mask off the original size bits and reencode them. */ |
| 18421 | inst.instruction = ((inst.instruction & 0xfff3ffff) | (1 << 18)); |
| 18422 | |
| 18423 | if (thumb_mode) |
| 18424 | inst.instruction |= 0xfc000000; |
| 18425 | else |
| 18426 | inst.instruction |= 0xf0000000; |
| 18427 | } |
| 18428 | else |
| 18429 | { |
| 18430 | int_encode: |
| 18431 | { |
| 18432 | unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080, |
| 18433 | 0x100, 0x180, 0x0, 0x080}; |
| 18434 | |
| 18435 | NEON_ENCODE (INTEGER, inst); |
| 18436 | |
| 18437 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)) |
| 18438 | { |
| 18439 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
| 18440 | return; |
| 18441 | } |
| 18442 | |
| 18443 | if (flavour != neon_cvt_flavour_invalid) |
| 18444 | inst.instruction |= enctab[flavour]; |
| 18445 | |
| 18446 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 18447 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 18448 | inst.instruction |= LOW4 (inst.operands[1].reg); |
| 18449 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; |
| 18450 | inst.instruction |= neon_quad (rs) << 6; |
| 18451 | if (flavour >= neon_cvt_flavour_s16_f16 |
| 18452 | && flavour <= neon_cvt_flavour_f16_u16) |
| 18453 | /* Half precision. */ |
| 18454 | inst.instruction |= 1 << 18; |
| 18455 | else |
| 18456 | inst.instruction |= 2 << 18; |
| 18457 | |
| 18458 | neon_dp_fixup (&inst); |
| 18459 | } |
| 18460 | } |
| 18461 | break; |
| 18462 | |
| 18463 | /* Half-precision conversions for Advanced SIMD -- neon. */ |
| 18464 | case NS_QD: |
| 18465 | case NS_DQ: |
| 18466 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
| 18467 | return; |
| 18468 | |
| 18469 | if ((rs == NS_DQ) |
| 18470 | && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32)) |
| 18471 | { |
| 18472 | as_bad (_("operand size must match register width")); |
| 18473 | break; |
| 18474 | } |
| 18475 | |
| 18476 | if ((rs == NS_QD) |
| 18477 | && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16))) |
| 18478 | { |
| 18479 | as_bad (_("operand size must match register width")); |
| 18480 | break; |
| 18481 | } |
| 18482 | |
| 18483 | if (rs == NS_DQ) |
| 18484 | inst.instruction = 0x3b60600; |
| 18485 | else |
| 18486 | inst.instruction = 0x3b60700; |
| 18487 | |
| 18488 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 18489 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 18490 | inst.instruction |= LOW4 (inst.operands[1].reg); |
| 18491 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; |
| 18492 | neon_dp_fixup (&inst); |
| 18493 | break; |
| 18494 | |
| 18495 | default: |
| 18496 | /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ |
| 18497 | if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z) |
| 18498 | do_vfp_nsyn_cvt (rs, flavour); |
| 18499 | else |
| 18500 | do_vfp_nsyn_cvt_fpv8 (flavour, mode); |
| 18501 | } |
| 18502 | } |
| 18503 | |
| 18504 | static void |
| 18505 | do_neon_cvtr (void) |
| 18506 | { |
| 18507 | do_neon_cvt_1 (neon_cvt_mode_x); |
| 18508 | } |
| 18509 | |
| 18510 | static void |
| 18511 | do_neon_cvt (void) |
| 18512 | { |
| 18513 | do_neon_cvt_1 (neon_cvt_mode_z); |
| 18514 | } |
| 18515 | |
| 18516 | static void |
| 18517 | do_neon_cvta (void) |
| 18518 | { |
| 18519 | do_neon_cvt_1 (neon_cvt_mode_a); |
| 18520 | } |
| 18521 | |
| 18522 | static void |
| 18523 | do_neon_cvtn (void) |
| 18524 | { |
| 18525 | do_neon_cvt_1 (neon_cvt_mode_n); |
| 18526 | } |
| 18527 | |
| 18528 | static void |
| 18529 | do_neon_cvtp (void) |
| 18530 | { |
| 18531 | do_neon_cvt_1 (neon_cvt_mode_p); |
| 18532 | } |
| 18533 | |
| 18534 | static void |
| 18535 | do_neon_cvtm (void) |
| 18536 | { |
| 18537 | do_neon_cvt_1 (neon_cvt_mode_m); |
| 18538 | } |
| 18539 | |
| 18540 | static void |
| 18541 | do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double) |
| 18542 | { |
| 18543 | if (is_double) |
| 18544 | mark_feature_used (&fpu_vfp_ext_armv8); |
| 18545 | |
| 18546 | encode_arm_vfp_reg (inst.operands[0].reg, |
| 18547 | (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd); |
| 18548 | encode_arm_vfp_reg (inst.operands[1].reg, |
| 18549 | (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm); |
| 18550 | inst.instruction |= to ? 0x10000 : 0; |
| 18551 | inst.instruction |= t ? 0x80 : 0; |
| 18552 | inst.instruction |= is_double ? 0x100 : 0; |
| 18553 | do_vfp_cond_or_thumb (); |
| 18554 | } |
| 18555 | |
| 18556 | static void |
| 18557 | do_neon_cvttb_1 (bfd_boolean t) |
| 18558 | { |
| 18559 | enum neon_shape rs = neon_select_shape (NS_HF, NS_HD, NS_FH, NS_FF, NS_FD, |
| 18560 | NS_DF, NS_DH, NS_QQ, NS_QQI, NS_NULL); |
| 18561 | |
| 18562 | if (rs == NS_NULL) |
| 18563 | return; |
| 18564 | else if (rs == NS_QQ || rs == NS_QQI) |
| 18565 | { |
| 18566 | int single_to_half = 0; |
| 18567 | if (check_simd_pred_availability (1, NEON_CHECK_ARCH)) |
| 18568 | return; |
| 18569 | |
| 18570 | enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs); |
| 18571 | |
| 18572 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) |
| 18573 | && (flavour == neon_cvt_flavour_u16_f16 |
| 18574 | || flavour == neon_cvt_flavour_s16_f16 |
| 18575 | || flavour == neon_cvt_flavour_f16_s16 |
| 18576 | || flavour == neon_cvt_flavour_f16_u16 |
| 18577 | || flavour == neon_cvt_flavour_u32_f32 |
| 18578 | || flavour == neon_cvt_flavour_s32_f32 |
| 18579 | || flavour == neon_cvt_flavour_f32_s32 |
| 18580 | || flavour == neon_cvt_flavour_f32_u32)) |
| 18581 | { |
| 18582 | inst.cond = 0xf; |
| 18583 | inst.instruction = N_MNEM_vcvt; |
| 18584 | set_pred_insn_type (INSIDE_VPT_INSN); |
| 18585 | do_neon_cvt_1 (neon_cvt_mode_z); |
| 18586 | return; |
| 18587 | } |
| 18588 | else if (rs == NS_QQ && flavour == neon_cvt_flavour_f32_f16) |
| 18589 | single_to_half = 1; |
| 18590 | else if (rs == NS_QQ && flavour != neon_cvt_flavour_f16_f32) |
| 18591 | { |
| 18592 | first_error (BAD_FPU); |
| 18593 | return; |
| 18594 | } |
| 18595 | |
| 18596 | inst.instruction = 0xee3f0e01; |
| 18597 | inst.instruction |= single_to_half << 28; |
| 18598 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 18599 | inst.instruction |= LOW4 (inst.operands[0].reg) << 13; |
| 18600 | inst.instruction |= t << 12; |
| 18601 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; |
| 18602 | inst.instruction |= LOW4 (inst.operands[1].reg) << 1; |
| 18603 | inst.is_neon = 1; |
| 18604 | } |
| 18605 | else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype) |
| 18606 | { |
| 18607 | inst.error = NULL; |
| 18608 | do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE); |
| 18609 | } |
| 18610 | else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype) |
| 18611 | { |
| 18612 | inst.error = NULL; |
| 18613 | do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE); |
| 18614 | } |
| 18615 | else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype) |
| 18616 | { |
| 18617 | /* The VCVTB and VCVTT instructions with D-register operands |
| 18618 | don't work for SP only targets. */ |
| 18619 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), |
| 18620 | _(BAD_FPU)); |
| 18621 | |
| 18622 | inst.error = NULL; |
| 18623 | do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE); |
| 18624 | } |
| 18625 | else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype) |
| 18626 | { |
| 18627 | /* The VCVTB and VCVTT instructions with D-register operands |
| 18628 | don't work for SP only targets. */ |
| 18629 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), |
| 18630 | _(BAD_FPU)); |
| 18631 | |
| 18632 | inst.error = NULL; |
| 18633 | do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE); |
| 18634 | } |
| 18635 | else |
| 18636 | return; |
| 18637 | } |
| 18638 | |
| 18639 | static void |
| 18640 | do_neon_cvtb (void) |
| 18641 | { |
| 18642 | do_neon_cvttb_1 (FALSE); |
| 18643 | } |
| 18644 | |
| 18645 | |
| 18646 | static void |
| 18647 | do_neon_cvtt (void) |
| 18648 | { |
| 18649 | do_neon_cvttb_1 (TRUE); |
| 18650 | } |
| 18651 | |
| 18652 | static void |
| 18653 | neon_move_immediate (void) |
| 18654 | { |
| 18655 | enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); |
| 18656 | struct neon_type_el et = neon_check_type (2, rs, |
| 18657 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); |
| 18658 | unsigned immlo, immhi = 0, immbits; |
| 18659 | int op, cmode, float_p; |
| 18660 | |
| 18661 | constraint (et.type == NT_invtype, |
| 18662 | _("operand size must be specified for immediate VMOV")); |
| 18663 | |
| 18664 | /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ |
| 18665 | op = (inst.instruction & (1 << 5)) != 0; |
| 18666 | |
| 18667 | immlo = inst.operands[1].imm; |
| 18668 | if (inst.operands[1].regisimm) |
| 18669 | immhi = inst.operands[1].reg; |
| 18670 | |
| 18671 | constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, |
| 18672 | _("immediate has bits set outside the operand size")); |
| 18673 | |
| 18674 | float_p = inst.operands[1].immisfloat; |
| 18675 | |
| 18676 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op, |
| 18677 | et.size, et.type)) == FAIL) |
| 18678 | { |
| 18679 | /* Invert relevant bits only. */ |
| 18680 | neon_invert_size (&immlo, &immhi, et.size); |
| 18681 | /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable |
| 18682 | with one or the other; those cases are caught by |
| 18683 | neon_cmode_for_move_imm. */ |
| 18684 | op = !op; |
| 18685 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, |
| 18686 | &op, et.size, et.type)) == FAIL) |
| 18687 | { |
| 18688 | first_error (_("immediate out of range")); |
| 18689 | return; |
| 18690 | } |
| 18691 | } |
| 18692 | |
| 18693 | inst.instruction &= ~(1 << 5); |
| 18694 | inst.instruction |= op << 5; |
| 18695 | |
| 18696 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 18697 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 18698 | inst.instruction |= neon_quad (rs) << 6; |
| 18699 | inst.instruction |= cmode << 8; |
| 18700 | |
| 18701 | neon_write_immbits (immbits); |
| 18702 | } |
| 18703 | |
| 18704 | static void |
| 18705 | do_neon_mvn (void) |
| 18706 | { |
| 18707 | if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH)) |
| 18708 | return; |
| 18709 | |
| 18710 | if (inst.operands[1].isreg) |
| 18711 | { |
| 18712 | enum neon_shape rs; |
| 18713 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 18714 | rs = neon_select_shape (NS_QQ, NS_NULL); |
| 18715 | else |
| 18716 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
| 18717 | |
| 18718 | NEON_ENCODE (INTEGER, inst); |
| 18719 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 18720 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 18721 | inst.instruction |= LOW4 (inst.operands[1].reg); |
| 18722 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; |
| 18723 | inst.instruction |= neon_quad (rs) << 6; |
| 18724 | } |
| 18725 | else |
| 18726 | { |
| 18727 | NEON_ENCODE (IMMED, inst); |
| 18728 | neon_move_immediate (); |
| 18729 | } |
| 18730 | |
| 18731 | neon_dp_fixup (&inst); |
| 18732 | |
| 18733 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 18734 | { |
| 18735 | constraint (!inst.operands[1].isreg && !inst.operands[0].isquad, BAD_FPU); |
| 18736 | constraint ((inst.instruction & 0xd00) == 0xd00, |
| 18737 | _("immediate value out of range")); |
| 18738 | } |
| 18739 | } |
| 18740 | |
| 18741 | /* Encode instructions of form: |
| 18742 | |
| 18743 | |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| |
| 18744 | | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */ |
| 18745 | |
| 18746 | static void |
| 18747 | neon_mixed_length (struct neon_type_el et, unsigned size) |
| 18748 | { |
| 18749 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 18750 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 18751 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; |
| 18752 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; |
| 18753 | inst.instruction |= LOW4 (inst.operands[2].reg); |
| 18754 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; |
| 18755 | inst.instruction |= (et.type == NT_unsigned) << 24; |
| 18756 | inst.instruction |= neon_logbits (size) << 20; |
| 18757 | |
| 18758 | neon_dp_fixup (&inst); |
| 18759 | } |
| 18760 | |
| 18761 | static void |
| 18762 | do_neon_dyadic_long (void) |
| 18763 | { |
| 18764 | enum neon_shape rs = neon_select_shape (NS_QDD, NS_QQQ, NS_QQR, NS_NULL); |
| 18765 | if (rs == NS_QDD) |
| 18766 | { |
| 18767 | if (vfp_or_neon_is_neon (NEON_CHECK_ARCH | NEON_CHECK_CC) == FAIL) |
| 18768 | return; |
| 18769 | |
| 18770 | NEON_ENCODE (INTEGER, inst); |
| 18771 | /* FIXME: Type checking for lengthening op. */ |
| 18772 | struct neon_type_el et = neon_check_type (3, NS_QDD, |
| 18773 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); |
| 18774 | neon_mixed_length (et, et.size); |
| 18775 | } |
| 18776 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) |
| 18777 | && (inst.cond == 0xf || inst.cond == 0x10)) |
| 18778 | { |
| 18779 | /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd |
| 18780 | in an IT block with le/lt conditions. */ |
| 18781 | |
| 18782 | if (inst.cond == 0xf) |
| 18783 | inst.cond = 0xb; |
| 18784 | else if (inst.cond == 0x10) |
| 18785 | inst.cond = 0xd; |
| 18786 | |
| 18787 | inst.pred_insn_type = INSIDE_IT_INSN; |
| 18788 | |
| 18789 | if (inst.instruction == N_MNEM_vaddl) |
| 18790 | { |
| 18791 | inst.instruction = N_MNEM_vadd; |
| 18792 | do_neon_addsub_if_i (); |
| 18793 | } |
| 18794 | else if (inst.instruction == N_MNEM_vsubl) |
| 18795 | { |
| 18796 | inst.instruction = N_MNEM_vsub; |
| 18797 | do_neon_addsub_if_i (); |
| 18798 | } |
| 18799 | else if (inst.instruction == N_MNEM_vabdl) |
| 18800 | { |
| 18801 | inst.instruction = N_MNEM_vabd; |
| 18802 | do_neon_dyadic_if_su (); |
| 18803 | } |
| 18804 | } |
| 18805 | else |
| 18806 | first_error (BAD_FPU); |
| 18807 | } |
| 18808 | |
| 18809 | static void |
| 18810 | do_neon_abal (void) |
| 18811 | { |
| 18812 | struct neon_type_el et = neon_check_type (3, NS_QDD, |
| 18813 | N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); |
| 18814 | neon_mixed_length (et, et.size); |
| 18815 | } |
| 18816 | |
| 18817 | static void |
| 18818 | neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) |
| 18819 | { |
| 18820 | if (inst.operands[2].isscalar) |
| 18821 | { |
| 18822 | struct neon_type_el et = neon_check_type (3, NS_QDS, |
| 18823 | N_EQK | N_DBL, N_EQK, regtypes | N_KEY); |
| 18824 | NEON_ENCODE (SCALAR, inst); |
| 18825 | neon_mul_mac (et, et.type == NT_unsigned); |
| 18826 | } |
| 18827 | else |
| 18828 | { |
| 18829 | struct neon_type_el et = neon_check_type (3, NS_QDD, |
| 18830 | N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); |
| 18831 | NEON_ENCODE (INTEGER, inst); |
| 18832 | neon_mixed_length (et, et.size); |
| 18833 | } |
| 18834 | } |
| 18835 | |
| 18836 | static void |
| 18837 | do_neon_mac_maybe_scalar_long (void) |
| 18838 | { |
| 18839 | neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); |
| 18840 | } |
| 18841 | |
| 18842 | /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's |
| 18843 | internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */ |
| 18844 | |
| 18845 | static unsigned |
| 18846 | neon_scalar_for_fmac_fp16_long (unsigned scalar, unsigned quad_p) |
| 18847 | { |
| 18848 | unsigned regno = NEON_SCALAR_REG (scalar); |
| 18849 | unsigned elno = NEON_SCALAR_INDEX (scalar); |
| 18850 | |
| 18851 | if (quad_p) |
| 18852 | { |
| 18853 | if (regno > 7 || elno > 3) |
| 18854 | goto bad_scalar; |
| 18855 | |
| 18856 | return ((regno & 0x7) |
| 18857 | | ((elno & 0x1) << 3) |
| 18858 | | (((elno >> 1) & 0x1) << 5)); |
| 18859 | } |
| 18860 | else |
| 18861 | { |
| 18862 | if (regno > 15 || elno > 1) |
| 18863 | goto bad_scalar; |
| 18864 | |
| 18865 | return (((regno & 0x1) << 5) |
| 18866 | | ((regno >> 1) & 0x7) |
| 18867 | | ((elno & 0x1) << 3)); |
| 18868 | } |
| 18869 | |
| 18870 | bad_scalar: |
| 18871 | first_error (_("scalar out of range for multiply instruction")); |
| 18872 | return 0; |
| 18873 | } |
| 18874 | |
| 18875 | static void |
| 18876 | do_neon_fmac_maybe_scalar_long (int subtype) |
| 18877 | { |
| 18878 | enum neon_shape rs; |
| 18879 | int high8; |
| 18880 | /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size" |
| 18881 | field (bits[21:20]) has different meaning. For scalar index variant, it's |
| 18882 | used to differentiate add and subtract, otherwise it's with fixed value |
| 18883 | 0x2. */ |
| 18884 | int size = -1; |
| 18885 | |
| 18886 | if (inst.cond != COND_ALWAYS) |
| 18887 | as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the " |
| 18888 | "behaviour is UNPREDICTABLE")); |
| 18889 | |
| 18890 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16_fml), |
| 18891 | _(BAD_FP16)); |
| 18892 | |
| 18893 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8), |
| 18894 | _(BAD_FPU)); |
| 18895 | |
| 18896 | /* vfmal/vfmsl are in three-same D/Q register format or the third operand can |
| 18897 | be a scalar index register. */ |
| 18898 | if (inst.operands[2].isscalar) |
| 18899 | { |
| 18900 | high8 = 0xfe000000; |
| 18901 | if (subtype) |
| 18902 | size = 16; |
| 18903 | rs = neon_select_shape (NS_DHS, NS_QDS, NS_NULL); |
| 18904 | } |
| 18905 | else |
| 18906 | { |
| 18907 | high8 = 0xfc000000; |
| 18908 | size = 32; |
| 18909 | if (subtype) |
| 18910 | inst.instruction |= (0x1 << 23); |
| 18911 | rs = neon_select_shape (NS_DHH, NS_QDD, NS_NULL); |
| 18912 | } |
| 18913 | |
| 18914 | neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16); |
| 18915 | |
| 18916 | /* "opcode" from template has included "ubit", so simply pass 0 here. Also, |
| 18917 | the "S" bit in size field has been reused to differentiate vfmal and vfmsl, |
| 18918 | so we simply pass -1 as size. */ |
| 18919 | unsigned quad_p = (rs == NS_QDD || rs == NS_QDS); |
| 18920 | neon_three_same (quad_p, 0, size); |
| 18921 | |
| 18922 | /* Undo neon_dp_fixup. Redo the high eight bits. */ |
| 18923 | inst.instruction &= 0x00ffffff; |
| 18924 | inst.instruction |= high8; |
| 18925 | |
| 18926 | #define LOW1(R) ((R) & 0x1) |
| 18927 | #define HI4(R) (((R) >> 1) & 0xf) |
| 18928 | /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on |
| 18929 | whether the instruction is in Q form and whether Vm is a scalar indexed |
| 18930 | operand. */ |
| 18931 | if (inst.operands[2].isscalar) |
| 18932 | { |
| 18933 | unsigned rm |
| 18934 | = neon_scalar_for_fmac_fp16_long (inst.operands[2].reg, quad_p); |
| 18935 | inst.instruction &= 0xffffffd0; |
| 18936 | inst.instruction |= rm; |
| 18937 | |
| 18938 | if (!quad_p) |
| 18939 | { |
| 18940 | /* Redo Rn as well. */ |
| 18941 | inst.instruction &= 0xfff0ff7f; |
| 18942 | inst.instruction |= HI4 (inst.operands[1].reg) << 16; |
| 18943 | inst.instruction |= LOW1 (inst.operands[1].reg) << 7; |
| 18944 | } |
| 18945 | } |
| 18946 | else if (!quad_p) |
| 18947 | { |
| 18948 | /* Redo Rn and Rm. */ |
| 18949 | inst.instruction &= 0xfff0ff50; |
| 18950 | inst.instruction |= HI4 (inst.operands[1].reg) << 16; |
| 18951 | inst.instruction |= LOW1 (inst.operands[1].reg) << 7; |
| 18952 | inst.instruction |= HI4 (inst.operands[2].reg); |
| 18953 | inst.instruction |= LOW1 (inst.operands[2].reg) << 5; |
| 18954 | } |
| 18955 | } |
| 18956 | |
| 18957 | static void |
| 18958 | do_neon_vfmal (void) |
| 18959 | { |
| 18960 | return do_neon_fmac_maybe_scalar_long (0); |
| 18961 | } |
| 18962 | |
| 18963 | static void |
| 18964 | do_neon_vfmsl (void) |
| 18965 | { |
| 18966 | return do_neon_fmac_maybe_scalar_long (1); |
| 18967 | } |
| 18968 | |
| 18969 | static void |
| 18970 | do_neon_dyadic_wide (void) |
| 18971 | { |
| 18972 | struct neon_type_el et = neon_check_type (3, NS_QQD, |
| 18973 | N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); |
| 18974 | neon_mixed_length (et, et.size); |
| 18975 | } |
| 18976 | |
| 18977 | static void |
| 18978 | do_neon_dyadic_narrow (void) |
| 18979 | { |
| 18980 | struct neon_type_el et = neon_check_type (3, NS_QDD, |
| 18981 | N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); |
| 18982 | /* Operand sign is unimportant, and the U bit is part of the opcode, |
| 18983 | so force the operand type to integer. */ |
| 18984 | et.type = NT_integer; |
| 18985 | neon_mixed_length (et, et.size / 2); |
| 18986 | } |
| 18987 | |
| 18988 | static void |
| 18989 | do_neon_mul_sat_scalar_long (void) |
| 18990 | { |
| 18991 | neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); |
| 18992 | } |
| 18993 | |
| 18994 | static void |
| 18995 | do_neon_vmull (void) |
| 18996 | { |
| 18997 | if (inst.operands[2].isscalar) |
| 18998 | do_neon_mac_maybe_scalar_long (); |
| 18999 | else |
| 19000 | { |
| 19001 | struct neon_type_el et = neon_check_type (3, NS_QDD, |
| 19002 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY); |
| 19003 | |
| 19004 | if (et.type == NT_poly) |
| 19005 | NEON_ENCODE (POLY, inst); |
| 19006 | else |
| 19007 | NEON_ENCODE (INTEGER, inst); |
| 19008 | |
| 19009 | /* For polynomial encoding the U bit must be zero, and the size must |
| 19010 | be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non |
| 19011 | obviously, as 0b10). */ |
| 19012 | if (et.size == 64) |
| 19013 | { |
| 19014 | /* Check we're on the correct architecture. */ |
| 19015 | if (!mark_feature_used (&fpu_crypto_ext_armv8)) |
| 19016 | inst.error = |
| 19017 | _("Instruction form not available on this architecture."); |
| 19018 | |
| 19019 | et.size = 32; |
| 19020 | } |
| 19021 | |
| 19022 | neon_mixed_length (et, et.size); |
| 19023 | } |
| 19024 | } |
| 19025 | |
| 19026 | static void |
| 19027 | do_neon_ext (void) |
| 19028 | { |
| 19029 | enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); |
| 19030 | struct neon_type_el et = neon_check_type (3, rs, |
| 19031 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); |
| 19032 | unsigned imm = (inst.operands[3].imm * et.size) / 8; |
| 19033 | |
| 19034 | constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8), |
| 19035 | _("shift out of range")); |
| 19036 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 19037 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 19038 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; |
| 19039 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; |
| 19040 | inst.instruction |= LOW4 (inst.operands[2].reg); |
| 19041 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; |
| 19042 | inst.instruction |= neon_quad (rs) << 6; |
| 19043 | inst.instruction |= imm << 8; |
| 19044 | |
| 19045 | neon_dp_fixup (&inst); |
| 19046 | } |
| 19047 | |
| 19048 | static void |
| 19049 | do_neon_rev (void) |
| 19050 | { |
| 19051 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
| 19052 | struct neon_type_el et = neon_check_type (2, rs, |
| 19053 | N_EQK, N_8 | N_16 | N_32 | N_KEY); |
| 19054 | unsigned op = (inst.instruction >> 7) & 3; |
| 19055 | /* N (width of reversed regions) is encoded as part of the bitmask. We |
| 19056 | extract it here to check the elements to be reversed are smaller. |
| 19057 | Otherwise we'd get a reserved instruction. */ |
| 19058 | unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; |
| 19059 | gas_assert (elsize != 0); |
| 19060 | constraint (et.size >= elsize, |
| 19061 | _("elements must be smaller than reversal region")); |
| 19062 | neon_two_same (neon_quad (rs), 1, et.size); |
| 19063 | } |
| 19064 | |
| 19065 | static void |
| 19066 | do_neon_dup (void) |
| 19067 | { |
| 19068 | if (inst.operands[1].isscalar) |
| 19069 | { |
| 19070 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1), |
| 19071 | BAD_FPU); |
| 19072 | enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); |
| 19073 | struct neon_type_el et = neon_check_type (2, rs, |
| 19074 | N_EQK, N_8 | N_16 | N_32 | N_KEY); |
| 19075 | unsigned sizebits = et.size >> 3; |
| 19076 | unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); |
| 19077 | int logsize = neon_logbits (et.size); |
| 19078 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; |
| 19079 | |
| 19080 | if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) |
| 19081 | return; |
| 19082 | |
| 19083 | NEON_ENCODE (SCALAR, inst); |
| 19084 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 19085 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 19086 | inst.instruction |= LOW4 (dm); |
| 19087 | inst.instruction |= HI1 (dm) << 5; |
| 19088 | inst.instruction |= neon_quad (rs) << 6; |
| 19089 | inst.instruction |= x << 17; |
| 19090 | inst.instruction |= sizebits << 16; |
| 19091 | |
| 19092 | neon_dp_fixup (&inst); |
| 19093 | } |
| 19094 | else |
| 19095 | { |
| 19096 | enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); |
| 19097 | struct neon_type_el et = neon_check_type (2, rs, |
| 19098 | N_8 | N_16 | N_32 | N_KEY, N_EQK); |
| 19099 | if (rs == NS_QR) |
| 19100 | { |
| 19101 | if (check_simd_pred_availability (0, NEON_CHECK_ARCH)) |
| 19102 | return; |
| 19103 | } |
| 19104 | else |
| 19105 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1), |
| 19106 | BAD_FPU); |
| 19107 | |
| 19108 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 19109 | { |
| 19110 | if (inst.operands[1].reg == REG_SP) |
| 19111 | as_tsktsk (MVE_BAD_SP); |
| 19112 | else if (inst.operands[1].reg == REG_PC) |
| 19113 | as_tsktsk (MVE_BAD_PC); |
| 19114 | } |
| 19115 | |
| 19116 | /* Duplicate ARM register to lanes of vector. */ |
| 19117 | NEON_ENCODE (ARMREG, inst); |
| 19118 | switch (et.size) |
| 19119 | { |
| 19120 | case 8: inst.instruction |= 0x400000; break; |
| 19121 | case 16: inst.instruction |= 0x000020; break; |
| 19122 | case 32: inst.instruction |= 0x000000; break; |
| 19123 | default: break; |
| 19124 | } |
| 19125 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; |
| 19126 | inst.instruction |= LOW4 (inst.operands[0].reg) << 16; |
| 19127 | inst.instruction |= HI1 (inst.operands[0].reg) << 7; |
| 19128 | inst.instruction |= neon_quad (rs) << 21; |
| 19129 | /* The encoding for this instruction is identical for the ARM and Thumb |
| 19130 | variants, except for the condition field. */ |
| 19131 | do_vfp_cond_or_thumb (); |
| 19132 | } |
| 19133 | } |
| 19134 | |
| 19135 | static void |
| 19136 | do_mve_mov (int toQ) |
| 19137 | { |
| 19138 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 19139 | return; |
| 19140 | if (inst.cond > COND_ALWAYS) |
| 19141 | inst.pred_insn_type = MVE_UNPREDICABLE_INSN; |
| 19142 | |
| 19143 | unsigned Rt = 0, Rt2 = 1, Q0 = 2, Q1 = 3; |
| 19144 | if (toQ) |
| 19145 | { |
| 19146 | Q0 = 0; |
| 19147 | Q1 = 1; |
| 19148 | Rt = 2; |
| 19149 | Rt2 = 3; |
| 19150 | } |
| 19151 | |
| 19152 | constraint (inst.operands[Q0].reg != inst.operands[Q1].reg + 2, |
| 19153 | _("Index one must be [2,3] and index two must be two less than" |
| 19154 | " index one.")); |
| 19155 | constraint (inst.operands[Rt].reg == inst.operands[Rt2].reg, |
| 19156 | _("General purpose registers may not be the same")); |
| 19157 | constraint (inst.operands[Rt].reg == REG_SP |
| 19158 | || inst.operands[Rt2].reg == REG_SP, |
| 19159 | BAD_SP); |
| 19160 | constraint (inst.operands[Rt].reg == REG_PC |
| 19161 | || inst.operands[Rt2].reg == REG_PC, |
| 19162 | BAD_PC); |
| 19163 | |
| 19164 | inst.instruction = 0xec000f00; |
| 19165 | inst.instruction |= HI1 (inst.operands[Q1].reg / 32) << 23; |
| 19166 | inst.instruction |= !!toQ << 20; |
| 19167 | inst.instruction |= inst.operands[Rt2].reg << 16; |
| 19168 | inst.instruction |= LOW4 (inst.operands[Q1].reg / 32) << 13; |
| 19169 | inst.instruction |= (inst.operands[Q1].reg % 4) << 4; |
| 19170 | inst.instruction |= inst.operands[Rt].reg; |
| 19171 | } |
| 19172 | |
| 19173 | static void |
| 19174 | do_mve_movn (void) |
| 19175 | { |
| 19176 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 19177 | return; |
| 19178 | |
| 19179 | if (inst.cond > COND_ALWAYS) |
| 19180 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 19181 | else |
| 19182 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; |
| 19183 | |
| 19184 | struct neon_type_el et = neon_check_type (2, NS_QQ, N_EQK, N_I16 | N_I32 |
| 19185 | | N_KEY); |
| 19186 | |
| 19187 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 19188 | inst.instruction |= (neon_logbits (et.size) - 1) << 18; |
| 19189 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 19190 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; |
| 19191 | inst.instruction |= LOW4 (inst.operands[1].reg); |
| 19192 | inst.is_neon = 1; |
| 19193 | |
| 19194 | } |
| 19195 | |
| 19196 | /* VMOV has particularly many variations. It can be one of: |
| 19197 | 0. VMOV<c><q> <Qd>, <Qm> |
| 19198 | 1. VMOV<c><q> <Dd>, <Dm> |
| 19199 | (Register operations, which are VORR with Rm = Rn.) |
| 19200 | 2. VMOV<c><q>.<dt> <Qd>, #<imm> |
| 19201 | 3. VMOV<c><q>.<dt> <Dd>, #<imm> |
| 19202 | (Immediate loads.) |
| 19203 | 4. VMOV<c><q>.<size> <Dn[x]>, <Rd> |
| 19204 | (ARM register to scalar.) |
| 19205 | 5. VMOV<c><q> <Dm>, <Rd>, <Rn> |
| 19206 | (Two ARM registers to vector.) |
| 19207 | 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]> |
| 19208 | (Scalar to ARM register.) |
| 19209 | 7. VMOV<c><q> <Rd>, <Rn>, <Dm> |
| 19210 | (Vector to two ARM registers.) |
| 19211 | 8. VMOV.F32 <Sd>, <Sm> |
| 19212 | 9. VMOV.F64 <Dd>, <Dm> |
| 19213 | (VFP register moves.) |
| 19214 | 10. VMOV.F32 <Sd>, #imm |
| 19215 | 11. VMOV.F64 <Dd>, #imm |
| 19216 | (VFP float immediate load.) |
| 19217 | 12. VMOV <Rd>, <Sm> |
| 19218 | (VFP single to ARM reg.) |
| 19219 | 13. VMOV <Sd>, <Rm> |
| 19220 | (ARM reg to VFP single.) |
| 19221 | 14. VMOV <Rd>, <Re>, <Sn>, <Sm> |
| 19222 | (Two ARM regs to two VFP singles.) |
| 19223 | 15. VMOV <Sd>, <Se>, <Rn>, <Rm> |
| 19224 | (Two VFP singles to two ARM regs.) |
| 19225 | 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> |
| 19226 | 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> |
| 19227 | 18. VMOV<c>.<dt> <Rt>, <Qn[idx]> |
| 19228 | 19. VMOV<c>.<dt> <Qd[idx]>, <Rt> |
| 19229 | |
| 19230 | These cases can be disambiguated using neon_select_shape, except cases 1/9 |
| 19231 | and 3/11 which depend on the operand type too. |
| 19232 | |
| 19233 | All the encoded bits are hardcoded by this function. |
| 19234 | |
| 19235 | Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). |
| 19236 | Cases 5, 7 may be used with VFPv2 and above. |
| 19237 | |
| 19238 | FIXME: Some of the checking may be a bit sloppy (in a couple of cases you |
| 19239 | can specify a type where it doesn't make sense to, and is ignored). */ |
| 19240 | |
| 19241 | static void |
| 19242 | do_neon_mov (void) |
| 19243 | { |
| 19244 | enum neon_shape rs = neon_select_shape (NS_RRSS, NS_SSRR, NS_RRFF, NS_FFRR, |
| 19245 | NS_DRR, NS_RRD, NS_QQ, NS_DD, NS_QI, |
| 19246 | NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, |
| 19247 | NS_RF, NS_FR, NS_HR, NS_RH, NS_HI, |
| 19248 | NS_NULL); |
| 19249 | struct neon_type_el et; |
| 19250 | const char *ldconst = 0; |
| 19251 | |
| 19252 | switch (rs) |
| 19253 | { |
| 19254 | case NS_DD: /* case 1/9. */ |
| 19255 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); |
| 19256 | /* It is not an error here if no type is given. */ |
| 19257 | inst.error = NULL; |
| 19258 | if (et.type == NT_float && et.size == 64) |
| 19259 | { |
| 19260 | do_vfp_nsyn_opcode ("fcpyd"); |
| 19261 | break; |
| 19262 | } |
| 19263 | /* fall through. */ |
| 19264 | |
| 19265 | case NS_QQ: /* case 0/1. */ |
| 19266 | { |
| 19267 | if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH)) |
| 19268 | return; |
| 19269 | /* The architecture manual I have doesn't explicitly state which |
| 19270 | value the U bit should have for register->register moves, but |
| 19271 | the equivalent VORR instruction has U = 0, so do that. */ |
| 19272 | inst.instruction = 0x0200110; |
| 19273 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 19274 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 19275 | inst.instruction |= LOW4 (inst.operands[1].reg); |
| 19276 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; |
| 19277 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; |
| 19278 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; |
| 19279 | inst.instruction |= neon_quad (rs) << 6; |
| 19280 | |
| 19281 | neon_dp_fixup (&inst); |
| 19282 | } |
| 19283 | break; |
| 19284 | |
| 19285 | case NS_DI: /* case 3/11. */ |
| 19286 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); |
| 19287 | inst.error = NULL; |
| 19288 | if (et.type == NT_float && et.size == 64) |
| 19289 | { |
| 19290 | /* case 11 (fconstd). */ |
| 19291 | ldconst = "fconstd"; |
| 19292 | goto encode_fconstd; |
| 19293 | } |
| 19294 | /* fall through. */ |
| 19295 | |
| 19296 | case NS_QI: /* case 2/3. */ |
| 19297 | if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH)) |
| 19298 | return; |
| 19299 | inst.instruction = 0x0800010; |
| 19300 | neon_move_immediate (); |
| 19301 | neon_dp_fixup (&inst); |
| 19302 | break; |
| 19303 | |
| 19304 | case NS_SR: /* case 4. */ |
| 19305 | { |
| 19306 | unsigned bcdebits = 0; |
| 19307 | int logsize; |
| 19308 | unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); |
| 19309 | unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); |
| 19310 | |
| 19311 | /* .<size> is optional here, defaulting to .32. */ |
| 19312 | if (inst.vectype.elems == 0 |
| 19313 | && inst.operands[0].vectype.type == NT_invtype |
| 19314 | && inst.operands[1].vectype.type == NT_invtype) |
| 19315 | { |
| 19316 | inst.vectype.el[0].type = NT_untyped; |
| 19317 | inst.vectype.el[0].size = 32; |
| 19318 | inst.vectype.elems = 1; |
| 19319 | } |
| 19320 | |
| 19321 | et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK); |
| 19322 | logsize = neon_logbits (et.size); |
| 19323 | |
| 19324 | if (et.size != 32) |
| 19325 | { |
| 19326 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) |
| 19327 | && vfp_or_neon_is_neon (NEON_CHECK_ARCH) == FAIL) |
| 19328 | return; |
| 19329 | } |
| 19330 | else |
| 19331 | { |
| 19332 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1) |
| 19333 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), |
| 19334 | _(BAD_FPU)); |
| 19335 | } |
| 19336 | |
| 19337 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 19338 | { |
| 19339 | if (inst.operands[1].reg == REG_SP) |
| 19340 | as_tsktsk (MVE_BAD_SP); |
| 19341 | else if (inst.operands[1].reg == REG_PC) |
| 19342 | as_tsktsk (MVE_BAD_PC); |
| 19343 | } |
| 19344 | unsigned size = inst.operands[0].isscalar == 1 ? 64 : 128; |
| 19345 | |
| 19346 | constraint (et.type == NT_invtype, _("bad type for scalar")); |
| 19347 | constraint (x >= size / et.size, _("scalar index out of range")); |
| 19348 | |
| 19349 | |
| 19350 | switch (et.size) |
| 19351 | { |
| 19352 | case 8: bcdebits = 0x8; break; |
| 19353 | case 16: bcdebits = 0x1; break; |
| 19354 | case 32: bcdebits = 0x0; break; |
| 19355 | default: ; |
| 19356 | } |
| 19357 | |
| 19358 | bcdebits |= (x & ((1 << (3-logsize)) - 1)) << logsize; |
| 19359 | |
| 19360 | inst.instruction = 0xe000b10; |
| 19361 | do_vfp_cond_or_thumb (); |
| 19362 | inst.instruction |= LOW4 (dn) << 16; |
| 19363 | inst.instruction |= HI1 (dn) << 7; |
| 19364 | inst.instruction |= inst.operands[1].reg << 12; |
| 19365 | inst.instruction |= (bcdebits & 3) << 5; |
| 19366 | inst.instruction |= ((bcdebits >> 2) & 3) << 21; |
| 19367 | inst.instruction |= (x >> (3-logsize)) << 16; |
| 19368 | } |
| 19369 | break; |
| 19370 | |
| 19371 | case NS_DRR: /* case 5 (fmdrr). */ |
| 19372 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2) |
| 19373 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), |
| 19374 | _(BAD_FPU)); |
| 19375 | |
| 19376 | inst.instruction = 0xc400b10; |
| 19377 | do_vfp_cond_or_thumb (); |
| 19378 | inst.instruction |= LOW4 (inst.operands[0].reg); |
| 19379 | inst.instruction |= HI1 (inst.operands[0].reg) << 5; |
| 19380 | inst.instruction |= inst.operands[1].reg << 12; |
| 19381 | inst.instruction |= inst.operands[2].reg << 16; |
| 19382 | break; |
| 19383 | |
| 19384 | case NS_RS: /* case 6. */ |
| 19385 | { |
| 19386 | unsigned logsize; |
| 19387 | unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); |
| 19388 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); |
| 19389 | unsigned abcdebits = 0; |
| 19390 | |
| 19391 | /* .<dt> is optional here, defaulting to .32. */ |
| 19392 | if (inst.vectype.elems == 0 |
| 19393 | && inst.operands[0].vectype.type == NT_invtype |
| 19394 | && inst.operands[1].vectype.type == NT_invtype) |
| 19395 | { |
| 19396 | inst.vectype.el[0].type = NT_untyped; |
| 19397 | inst.vectype.el[0].size = 32; |
| 19398 | inst.vectype.elems = 1; |
| 19399 | } |
| 19400 | |
| 19401 | et = neon_check_type (2, NS_NULL, |
| 19402 | N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); |
| 19403 | logsize = neon_logbits (et.size); |
| 19404 | |
| 19405 | if (et.size != 32) |
| 19406 | { |
| 19407 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) |
| 19408 | && vfp_or_neon_is_neon (NEON_CHECK_CC |
| 19409 | | NEON_CHECK_ARCH) == FAIL) |
| 19410 | return; |
| 19411 | } |
| 19412 | else |
| 19413 | { |
| 19414 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1) |
| 19415 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), |
| 19416 | _(BAD_FPU)); |
| 19417 | } |
| 19418 | |
| 19419 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 19420 | { |
| 19421 | if (inst.operands[0].reg == REG_SP) |
| 19422 | as_tsktsk (MVE_BAD_SP); |
| 19423 | else if (inst.operands[0].reg == REG_PC) |
| 19424 | as_tsktsk (MVE_BAD_PC); |
| 19425 | } |
| 19426 | |
| 19427 | unsigned size = inst.operands[1].isscalar == 1 ? 64 : 128; |
| 19428 | |
| 19429 | constraint (et.type == NT_invtype, _("bad type for scalar")); |
| 19430 | constraint (x >= size / et.size, _("scalar index out of range")); |
| 19431 | |
| 19432 | switch (et.size) |
| 19433 | { |
| 19434 | case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; |
| 19435 | case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; |
| 19436 | case 32: abcdebits = 0x00; break; |
| 19437 | default: ; |
| 19438 | } |
| 19439 | |
| 19440 | abcdebits |= (x & ((1 << (3-logsize)) - 1)) << logsize; |
| 19441 | inst.instruction = 0xe100b10; |
| 19442 | do_vfp_cond_or_thumb (); |
| 19443 | inst.instruction |= LOW4 (dn) << 16; |
| 19444 | inst.instruction |= HI1 (dn) << 7; |
| 19445 | inst.instruction |= inst.operands[0].reg << 12; |
| 19446 | inst.instruction |= (abcdebits & 3) << 5; |
| 19447 | inst.instruction |= (abcdebits >> 2) << 21; |
| 19448 | inst.instruction |= (x >> (3-logsize)) << 16; |
| 19449 | } |
| 19450 | break; |
| 19451 | |
| 19452 | case NS_RRD: /* case 7 (fmrrd). */ |
| 19453 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2) |
| 19454 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), |
| 19455 | _(BAD_FPU)); |
| 19456 | |
| 19457 | inst.instruction = 0xc500b10; |
| 19458 | do_vfp_cond_or_thumb (); |
| 19459 | inst.instruction |= inst.operands[0].reg << 12; |
| 19460 | inst.instruction |= inst.operands[1].reg << 16; |
| 19461 | inst.instruction |= LOW4 (inst.operands[2].reg); |
| 19462 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; |
| 19463 | break; |
| 19464 | |
| 19465 | case NS_FF: /* case 8 (fcpys). */ |
| 19466 | do_vfp_nsyn_opcode ("fcpys"); |
| 19467 | break; |
| 19468 | |
| 19469 | case NS_HI: |
| 19470 | case NS_FI: /* case 10 (fconsts). */ |
| 19471 | ldconst = "fconsts"; |
| 19472 | encode_fconstd: |
| 19473 | if (!inst.operands[1].immisfloat) |
| 19474 | { |
| 19475 | unsigned new_imm; |
| 19476 | /* Immediate has to fit in 8 bits so float is enough. */ |
| 19477 | float imm = (float) inst.operands[1].imm; |
| 19478 | memcpy (&new_imm, &imm, sizeof (float)); |
| 19479 | /* But the assembly may have been written to provide an integer |
| 19480 | bit pattern that equates to a float, so check that the |
| 19481 | conversion has worked. */ |
| 19482 | if (is_quarter_float (new_imm)) |
| 19483 | { |
| 19484 | if (is_quarter_float (inst.operands[1].imm)) |
| 19485 | as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)")); |
| 19486 | |
| 19487 | inst.operands[1].imm = new_imm; |
| 19488 | inst.operands[1].immisfloat = 1; |
| 19489 | } |
| 19490 | } |
| 19491 | |
| 19492 | if (is_quarter_float (inst.operands[1].imm)) |
| 19493 | { |
| 19494 | inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); |
| 19495 | do_vfp_nsyn_opcode (ldconst); |
| 19496 | |
| 19497 | /* ARMv8.2 fp16 vmov.f16 instruction. */ |
| 19498 | if (rs == NS_HI) |
| 19499 | do_scalar_fp16_v82_encode (); |
| 19500 | } |
| 19501 | else |
| 19502 | first_error (_("immediate out of range")); |
| 19503 | break; |
| 19504 | |
| 19505 | case NS_RH: |
| 19506 | case NS_RF: /* case 12 (fmrs). */ |
| 19507 | do_vfp_nsyn_opcode ("fmrs"); |
| 19508 | /* ARMv8.2 fp16 vmov.f16 instruction. */ |
| 19509 | if (rs == NS_RH) |
| 19510 | do_scalar_fp16_v82_encode (); |
| 19511 | break; |
| 19512 | |
| 19513 | case NS_HR: |
| 19514 | case NS_FR: /* case 13 (fmsr). */ |
| 19515 | do_vfp_nsyn_opcode ("fmsr"); |
| 19516 | /* ARMv8.2 fp16 vmov.f16 instruction. */ |
| 19517 | if (rs == NS_HR) |
| 19518 | do_scalar_fp16_v82_encode (); |
| 19519 | break; |
| 19520 | |
| 19521 | case NS_RRSS: |
| 19522 | do_mve_mov (0); |
| 19523 | break; |
| 19524 | case NS_SSRR: |
| 19525 | do_mve_mov (1); |
| 19526 | break; |
| 19527 | |
| 19528 | /* The encoders for the fmrrs and fmsrr instructions expect three operands |
| 19529 | (one of which is a list), but we have parsed four. Do some fiddling to |
| 19530 | make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 |
| 19531 | expect. */ |
| 19532 | case NS_RRFF: /* case 14 (fmrrs). */ |
| 19533 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2) |
| 19534 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), |
| 19535 | _(BAD_FPU)); |
| 19536 | constraint (inst.operands[3].reg != inst.operands[2].reg + 1, |
| 19537 | _("VFP registers must be adjacent")); |
| 19538 | inst.operands[2].imm = 2; |
| 19539 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); |
| 19540 | do_vfp_nsyn_opcode ("fmrrs"); |
| 19541 | break; |
| 19542 | |
| 19543 | case NS_FFRR: /* case 15 (fmsrr). */ |
| 19544 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2) |
| 19545 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), |
| 19546 | _(BAD_FPU)); |
| 19547 | constraint (inst.operands[1].reg != inst.operands[0].reg + 1, |
| 19548 | _("VFP registers must be adjacent")); |
| 19549 | inst.operands[1] = inst.operands[2]; |
| 19550 | inst.operands[2] = inst.operands[3]; |
| 19551 | inst.operands[0].imm = 2; |
| 19552 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); |
| 19553 | do_vfp_nsyn_opcode ("fmsrr"); |
| 19554 | break; |
| 19555 | |
| 19556 | case NS_NULL: |
| 19557 | /* neon_select_shape has determined that the instruction |
| 19558 | shape is wrong and has already set the error message. */ |
| 19559 | break; |
| 19560 | |
| 19561 | default: |
| 19562 | abort (); |
| 19563 | } |
| 19564 | } |
| 19565 | |
| 19566 | static void |
| 19567 | do_mve_movl (void) |
| 19568 | { |
| 19569 | if (!(inst.operands[0].present && inst.operands[0].isquad |
| 19570 | && inst.operands[1].present && inst.operands[1].isquad |
| 19571 | && !inst.operands[2].present)) |
| 19572 | { |
| 19573 | inst.instruction = 0; |
| 19574 | inst.cond = 0xb; |
| 19575 | if (thumb_mode) |
| 19576 | set_pred_insn_type (INSIDE_IT_INSN); |
| 19577 | do_neon_mov (); |
| 19578 | return; |
| 19579 | } |
| 19580 | |
| 19581 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 19582 | return; |
| 19583 | |
| 19584 | if (inst.cond != COND_ALWAYS) |
| 19585 | inst.pred_insn_type = INSIDE_VPT_INSN; |
| 19586 | |
| 19587 | struct neon_type_el et = neon_check_type (2, NS_QQ, N_EQK, N_S8 | N_U8 |
| 19588 | | N_S16 | N_U16 | N_KEY); |
| 19589 | |
| 19590 | inst.instruction |= (et.type == NT_unsigned) << 28; |
| 19591 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 19592 | inst.instruction |= (neon_logbits (et.size) + 1) << 19; |
| 19593 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 19594 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; |
| 19595 | inst.instruction |= LOW4 (inst.operands[1].reg); |
| 19596 | inst.is_neon = 1; |
| 19597 | } |
| 19598 | |
| 19599 | static void |
| 19600 | do_neon_rshift_round_imm (void) |
| 19601 | { |
| 19602 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
| 19603 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
| 19604 | int imm = inst.operands[2].imm; |
| 19605 | |
| 19606 | /* imm == 0 case is encoded as VMOV for V{R}SHR. */ |
| 19607 | if (imm == 0) |
| 19608 | { |
| 19609 | inst.operands[2].present = 0; |
| 19610 | do_neon_mov (); |
| 19611 | return; |
| 19612 | } |
| 19613 | |
| 19614 | constraint (imm < 1 || (unsigned)imm > et.size, |
| 19615 | _("immediate out of range for shift")); |
| 19616 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
| 19617 | et.size - imm); |
| 19618 | } |
| 19619 | |
| 19620 | static void |
| 19621 | do_neon_movhf (void) |
| 19622 | { |
| 19623 | enum neon_shape rs = neon_select_shape (NS_HH, NS_NULL); |
| 19624 | constraint (rs != NS_HH, _("invalid suffix")); |
| 19625 | |
| 19626 | if (inst.cond != COND_ALWAYS) |
| 19627 | { |
| 19628 | if (thumb_mode) |
| 19629 | { |
| 19630 | as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional," |
| 19631 | " the behaviour is UNPREDICTABLE")); |
| 19632 | } |
| 19633 | else |
| 19634 | { |
| 19635 | inst.error = BAD_COND; |
| 19636 | return; |
| 19637 | } |
| 19638 | } |
| 19639 | |
| 19640 | do_vfp_sp_monadic (); |
| 19641 | |
| 19642 | inst.is_neon = 1; |
| 19643 | inst.instruction |= 0xf0000000; |
| 19644 | } |
| 19645 | |
| 19646 | static void |
| 19647 | do_neon_movl (void) |
| 19648 | { |
| 19649 | struct neon_type_el et = neon_check_type (2, NS_QD, |
| 19650 | N_EQK | N_DBL, N_SU_32 | N_KEY); |
| 19651 | unsigned sizebits = et.size >> 3; |
| 19652 | inst.instruction |= sizebits << 19; |
| 19653 | neon_two_same (0, et.type == NT_unsigned, -1); |
| 19654 | } |
| 19655 | |
| 19656 | static void |
| 19657 | do_neon_trn (void) |
| 19658 | { |
| 19659 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
| 19660 | struct neon_type_el et = neon_check_type (2, rs, |
| 19661 | N_EQK, N_8 | N_16 | N_32 | N_KEY); |
| 19662 | NEON_ENCODE (INTEGER, inst); |
| 19663 | neon_two_same (neon_quad (rs), 1, et.size); |
| 19664 | } |
| 19665 | |
| 19666 | static void |
| 19667 | do_neon_zip_uzp (void) |
| 19668 | { |
| 19669 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
| 19670 | struct neon_type_el et = neon_check_type (2, rs, |
| 19671 | N_EQK, N_8 | N_16 | N_32 | N_KEY); |
| 19672 | if (rs == NS_DD && et.size == 32) |
| 19673 | { |
| 19674 | /* Special case: encode as VTRN.32 <Dd>, <Dm>. */ |
| 19675 | inst.instruction = N_MNEM_vtrn; |
| 19676 | do_neon_trn (); |
| 19677 | return; |
| 19678 | } |
| 19679 | neon_two_same (neon_quad (rs), 1, et.size); |
| 19680 | } |
| 19681 | |
| 19682 | static void |
| 19683 | do_neon_sat_abs_neg (void) |
| 19684 | { |
| 19685 | if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH)) |
| 19686 | return; |
| 19687 | |
| 19688 | enum neon_shape rs; |
| 19689 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 19690 | rs = neon_select_shape (NS_QQ, NS_NULL); |
| 19691 | else |
| 19692 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
| 19693 | struct neon_type_el et = neon_check_type (2, rs, |
| 19694 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); |
| 19695 | neon_two_same (neon_quad (rs), 1, et.size); |
| 19696 | } |
| 19697 | |
| 19698 | static void |
| 19699 | do_neon_pair_long (void) |
| 19700 | { |
| 19701 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
| 19702 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); |
| 19703 | /* Unsigned is encoded in OP field (bit 7) for these instruction. */ |
| 19704 | inst.instruction |= (et.type == NT_unsigned) << 7; |
| 19705 | neon_two_same (neon_quad (rs), 1, et.size); |
| 19706 | } |
| 19707 | |
| 19708 | static void |
| 19709 | do_neon_recip_est (void) |
| 19710 | { |
| 19711 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
| 19712 | struct neon_type_el et = neon_check_type (2, rs, |
| 19713 | N_EQK | N_FLT, N_F_16_32 | N_U32 | N_KEY); |
| 19714 | inst.instruction |= (et.type == NT_float) << 8; |
| 19715 | neon_two_same (neon_quad (rs), 1, et.size); |
| 19716 | } |
| 19717 | |
| 19718 | static void |
| 19719 | do_neon_cls (void) |
| 19720 | { |
| 19721 | if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
| 19722 | return; |
| 19723 | |
| 19724 | enum neon_shape rs; |
| 19725 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 19726 | rs = neon_select_shape (NS_QQ, NS_NULL); |
| 19727 | else |
| 19728 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
| 19729 | |
| 19730 | struct neon_type_el et = neon_check_type (2, rs, |
| 19731 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); |
| 19732 | neon_two_same (neon_quad (rs), 1, et.size); |
| 19733 | } |
| 19734 | |
| 19735 | static void |
| 19736 | do_neon_clz (void) |
| 19737 | { |
| 19738 | if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
| 19739 | return; |
| 19740 | |
| 19741 | enum neon_shape rs; |
| 19742 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 19743 | rs = neon_select_shape (NS_QQ, NS_NULL); |
| 19744 | else |
| 19745 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
| 19746 | |
| 19747 | struct neon_type_el et = neon_check_type (2, rs, |
| 19748 | N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); |
| 19749 | neon_two_same (neon_quad (rs), 1, et.size); |
| 19750 | } |
| 19751 | |
| 19752 | static void |
| 19753 | do_neon_cnt (void) |
| 19754 | { |
| 19755 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
| 19756 | struct neon_type_el et = neon_check_type (2, rs, |
| 19757 | N_EQK | N_INT, N_8 | N_KEY); |
| 19758 | neon_two_same (neon_quad (rs), 1, et.size); |
| 19759 | } |
| 19760 | |
| 19761 | static void |
| 19762 | do_neon_swp (void) |
| 19763 | { |
| 19764 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
| 19765 | neon_two_same (neon_quad (rs), 1, -1); |
| 19766 | } |
| 19767 | |
| 19768 | static void |
| 19769 | do_neon_tbl_tbx (void) |
| 19770 | { |
| 19771 | unsigned listlenbits; |
| 19772 | neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); |
| 19773 | |
| 19774 | if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) |
| 19775 | { |
| 19776 | first_error (_("bad list length for table lookup")); |
| 19777 | return; |
| 19778 | } |
| 19779 | |
| 19780 | listlenbits = inst.operands[1].imm - 1; |
| 19781 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 19782 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 19783 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; |
| 19784 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; |
| 19785 | inst.instruction |= LOW4 (inst.operands[2].reg); |
| 19786 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; |
| 19787 | inst.instruction |= listlenbits << 8; |
| 19788 | |
| 19789 | neon_dp_fixup (&inst); |
| 19790 | } |
| 19791 | |
| 19792 | static void |
| 19793 | do_neon_ldm_stm (void) |
| 19794 | { |
| 19795 | /* P, U and L bits are part of bitmask. */ |
| 19796 | int is_dbmode = (inst.instruction & (1 << 24)) != 0; |
| 19797 | unsigned offsetbits = inst.operands[1].imm * 2; |
| 19798 | |
| 19799 | if (inst.operands[1].issingle) |
| 19800 | { |
| 19801 | do_vfp_nsyn_ldm_stm (is_dbmode); |
| 19802 | return; |
| 19803 | } |
| 19804 | |
| 19805 | constraint (is_dbmode && !inst.operands[0].writeback, |
| 19806 | _("writeback (!) must be used for VLDMDB and VSTMDB")); |
| 19807 | |
| 19808 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, |
| 19809 | _("register list must contain at least 1 and at most 16 " |
| 19810 | "registers")); |
| 19811 | |
| 19812 | inst.instruction |= inst.operands[0].reg << 16; |
| 19813 | inst.instruction |= inst.operands[0].writeback << 21; |
| 19814 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; |
| 19815 | inst.instruction |= HI1 (inst.operands[1].reg) << 22; |
| 19816 | |
| 19817 | inst.instruction |= offsetbits; |
| 19818 | |
| 19819 | do_vfp_cond_or_thumb (); |
| 19820 | } |
| 19821 | |
| 19822 | static void |
| 19823 | do_neon_ldr_str (void) |
| 19824 | { |
| 19825 | int is_ldr = (inst.instruction & (1 << 20)) != 0; |
| 19826 | |
| 19827 | /* Use of PC in vstr in ARM mode is deprecated in ARMv7. |
| 19828 | And is UNPREDICTABLE in thumb mode. */ |
| 19829 | if (!is_ldr |
| 19830 | && inst.operands[1].reg == REG_PC |
| 19831 | && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode)) |
| 19832 | { |
| 19833 | if (thumb_mode) |
| 19834 | inst.error = _("Use of PC here is UNPREDICTABLE"); |
| 19835 | else if (warn_on_deprecated) |
| 19836 | as_tsktsk (_("Use of PC here is deprecated")); |
| 19837 | } |
| 19838 | |
| 19839 | if (inst.operands[0].issingle) |
| 19840 | { |
| 19841 | if (is_ldr) |
| 19842 | do_vfp_nsyn_opcode ("flds"); |
| 19843 | else |
| 19844 | do_vfp_nsyn_opcode ("fsts"); |
| 19845 | |
| 19846 | /* ARMv8.2 vldr.16/vstr.16 instruction. */ |
| 19847 | if (inst.vectype.el[0].size == 16) |
| 19848 | do_scalar_fp16_v82_encode (); |
| 19849 | } |
| 19850 | else |
| 19851 | { |
| 19852 | if (is_ldr) |
| 19853 | do_vfp_nsyn_opcode ("fldd"); |
| 19854 | else |
| 19855 | do_vfp_nsyn_opcode ("fstd"); |
| 19856 | } |
| 19857 | } |
| 19858 | |
| 19859 | static void |
| 19860 | do_t_vldr_vstr_sysreg (void) |
| 19861 | { |
| 19862 | int fp_vldr_bitno = 20, sysreg_vldr_bitno = 20; |
| 19863 | bfd_boolean is_vldr = ((inst.instruction & (1 << fp_vldr_bitno)) != 0); |
| 19864 | |
| 19865 | /* Use of PC is UNPREDICTABLE. */ |
| 19866 | if (inst.operands[1].reg == REG_PC) |
| 19867 | inst.error = _("Use of PC here is UNPREDICTABLE"); |
| 19868 | |
| 19869 | if (inst.operands[1].immisreg) |
| 19870 | inst.error = _("instruction does not accept register index"); |
| 19871 | |
| 19872 | if (!inst.operands[1].isreg) |
| 19873 | inst.error = _("instruction does not accept PC-relative addressing"); |
| 19874 | |
| 19875 | if (abs (inst.operands[1].imm) >= (1 << 7)) |
| 19876 | inst.error = _("immediate value out of range"); |
| 19877 | |
| 19878 | inst.instruction = 0xec000f80; |
| 19879 | if (is_vldr) |
| 19880 | inst.instruction |= 1 << sysreg_vldr_bitno; |
| 19881 | encode_arm_cp_address (1, TRUE, FALSE, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM); |
| 19882 | inst.instruction |= (inst.operands[0].imm & 0x7) << 13; |
| 19883 | inst.instruction |= (inst.operands[0].imm & 0x8) << 19; |
| 19884 | } |
| 19885 | |
| 19886 | static void |
| 19887 | do_vldr_vstr (void) |
| 19888 | { |
| 19889 | bfd_boolean sysreg_op = !inst.operands[0].isreg; |
| 19890 | |
| 19891 | /* VLDR/VSTR (System Register). */ |
| 19892 | if (sysreg_op) |
| 19893 | { |
| 19894 | if (!mark_feature_used (&arm_ext_v8_1m_main)) |
| 19895 | as_bad (_("Instruction not permitted on this architecture")); |
| 19896 | |
| 19897 | do_t_vldr_vstr_sysreg (); |
| 19898 | } |
| 19899 | /* VLDR/VSTR. */ |
| 19900 | else |
| 19901 | { |
| 19902 | if (!mark_feature_used (&fpu_vfp_ext_v1xd)) |
| 19903 | as_bad (_("Instruction not permitted on this architecture")); |
| 19904 | do_neon_ldr_str (); |
| 19905 | } |
| 19906 | } |
| 19907 | |
| 19908 | /* "interleave" version also handles non-interleaving register VLD1/VST1 |
| 19909 | instructions. */ |
| 19910 | |
| 19911 | static void |
| 19912 | do_neon_ld_st_interleave (void) |
| 19913 | { |
| 19914 | struct neon_type_el et = neon_check_type (1, NS_NULL, |
| 19915 | N_8 | N_16 | N_32 | N_64); |
| 19916 | unsigned alignbits = 0; |
| 19917 | unsigned idx; |
| 19918 | /* The bits in this table go: |
| 19919 | 0: register stride of one (0) or two (1) |
| 19920 | 1,2: register list length, minus one (1, 2, 3, 4). |
| 19921 | 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>). |
| 19922 | We use -1 for invalid entries. */ |
| 19923 | const int typetable[] = |
| 19924 | { |
| 19925 | 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ |
| 19926 | -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ |
| 19927 | -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ |
| 19928 | -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ |
| 19929 | }; |
| 19930 | int typebits; |
| 19931 | |
| 19932 | if (et.type == NT_invtype) |
| 19933 | return; |
| 19934 | |
| 19935 | if (inst.operands[1].immisalign) |
| 19936 | switch (inst.operands[1].imm >> 8) |
| 19937 | { |
| 19938 | case 64: alignbits = 1; break; |
| 19939 | case 128: |
| 19940 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2 |
| 19941 | && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) |
| 19942 | goto bad_alignment; |
| 19943 | alignbits = 2; |
| 19944 | break; |
| 19945 | case 256: |
| 19946 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) |
| 19947 | goto bad_alignment; |
| 19948 | alignbits = 3; |
| 19949 | break; |
| 19950 | default: |
| 19951 | bad_alignment: |
| 19952 | first_error (_("bad alignment")); |
| 19953 | return; |
| 19954 | } |
| 19955 | |
| 19956 | inst.instruction |= alignbits << 4; |
| 19957 | inst.instruction |= neon_logbits (et.size) << 6; |
| 19958 | |
| 19959 | /* Bits [4:6] of the immediate in a list specifier encode register stride |
| 19960 | (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of |
| 19961 | VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look |
| 19962 | up the right value for "type" in a table based on this value and the given |
| 19963 | list style, then stick it back. */ |
| 19964 | idx = ((inst.operands[0].imm >> 4) & 7) |
| 19965 | | (((inst.instruction >> 8) & 3) << 3); |
| 19966 | |
| 19967 | typebits = typetable[idx]; |
| 19968 | |
| 19969 | constraint (typebits == -1, _("bad list type for instruction")); |
| 19970 | constraint (((inst.instruction >> 8) & 3) && et.size == 64, |
| 19971 | BAD_EL_TYPE); |
| 19972 | |
| 19973 | inst.instruction &= ~0xf00; |
| 19974 | inst.instruction |= typebits << 8; |
| 19975 | } |
| 19976 | |
| 19977 | /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. |
| 19978 | *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 |
| 19979 | otherwise. The variable arguments are a list of pairs of legal (size, align) |
| 19980 | values, terminated with -1. */ |
| 19981 | |
| 19982 | static int |
| 19983 | neon_alignment_bit (int size, int align, int *do_alignment, ...) |
| 19984 | { |
| 19985 | va_list ap; |
| 19986 | int result = FAIL, thissize, thisalign; |
| 19987 | |
| 19988 | if (!inst.operands[1].immisalign) |
| 19989 | { |
| 19990 | *do_alignment = 0; |
| 19991 | return SUCCESS; |
| 19992 | } |
| 19993 | |
| 19994 | va_start (ap, do_alignment); |
| 19995 | |
| 19996 | do |
| 19997 | { |
| 19998 | thissize = va_arg (ap, int); |
| 19999 | if (thissize == -1) |
| 20000 | break; |
| 20001 | thisalign = va_arg (ap, int); |
| 20002 | |
| 20003 | if (size == thissize && align == thisalign) |
| 20004 | result = SUCCESS; |
| 20005 | } |
| 20006 | while (result != SUCCESS); |
| 20007 | |
| 20008 | va_end (ap); |
| 20009 | |
| 20010 | if (result == SUCCESS) |
| 20011 | *do_alignment = 1; |
| 20012 | else |
| 20013 | first_error (_("unsupported alignment for instruction")); |
| 20014 | |
| 20015 | return result; |
| 20016 | } |
| 20017 | |
| 20018 | static void |
| 20019 | do_neon_ld_st_lane (void) |
| 20020 | { |
| 20021 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
| 20022 | int align_good, do_alignment = 0; |
| 20023 | int logsize = neon_logbits (et.size); |
| 20024 | int align = inst.operands[1].imm >> 8; |
| 20025 | int n = (inst.instruction >> 8) & 3; |
| 20026 | int max_el = 64 / et.size; |
| 20027 | |
| 20028 | if (et.type == NT_invtype) |
| 20029 | return; |
| 20030 | |
| 20031 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, |
| 20032 | _("bad list length")); |
| 20033 | constraint (NEON_LANE (inst.operands[0].imm) >= max_el, |
| 20034 | _("scalar index out of range")); |
| 20035 | constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 |
| 20036 | && et.size == 8, |
| 20037 | _("stride of 2 unavailable when element size is 8")); |
| 20038 | |
| 20039 | switch (n) |
| 20040 | { |
| 20041 | case 0: /* VLD1 / VST1. */ |
| 20042 | align_good = neon_alignment_bit (et.size, align, &do_alignment, 16, 16, |
| 20043 | 32, 32, -1); |
| 20044 | if (align_good == FAIL) |
| 20045 | return; |
| 20046 | if (do_alignment) |
| 20047 | { |
| 20048 | unsigned alignbits = 0; |
| 20049 | switch (et.size) |
| 20050 | { |
| 20051 | case 16: alignbits = 0x1; break; |
| 20052 | case 32: alignbits = 0x3; break; |
| 20053 | default: ; |
| 20054 | } |
| 20055 | inst.instruction |= alignbits << 4; |
| 20056 | } |
| 20057 | break; |
| 20058 | |
| 20059 | case 1: /* VLD2 / VST2. */ |
| 20060 | align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 16, |
| 20061 | 16, 32, 32, 64, -1); |
| 20062 | if (align_good == FAIL) |
| 20063 | return; |
| 20064 | if (do_alignment) |
| 20065 | inst.instruction |= 1 << 4; |
| 20066 | break; |
| 20067 | |
| 20068 | case 2: /* VLD3 / VST3. */ |
| 20069 | constraint (inst.operands[1].immisalign, |
| 20070 | _("can't use alignment with this instruction")); |
| 20071 | break; |
| 20072 | |
| 20073 | case 3: /* VLD4 / VST4. */ |
| 20074 | align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32, |
| 20075 | 16, 64, 32, 64, 32, 128, -1); |
| 20076 | if (align_good == FAIL) |
| 20077 | return; |
| 20078 | if (do_alignment) |
| 20079 | { |
| 20080 | unsigned alignbits = 0; |
| 20081 | switch (et.size) |
| 20082 | { |
| 20083 | case 8: alignbits = 0x1; break; |
| 20084 | case 16: alignbits = 0x1; break; |
| 20085 | case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; |
| 20086 | default: ; |
| 20087 | } |
| 20088 | inst.instruction |= alignbits << 4; |
| 20089 | } |
| 20090 | break; |
| 20091 | |
| 20092 | default: ; |
| 20093 | } |
| 20094 | |
| 20095 | /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ |
| 20096 | if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) |
| 20097 | inst.instruction |= 1 << (4 + logsize); |
| 20098 | |
| 20099 | inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); |
| 20100 | inst.instruction |= logsize << 10; |
| 20101 | } |
| 20102 | |
| 20103 | /* Encode single n-element structure to all lanes VLD<n> instructions. */ |
| 20104 | |
| 20105 | static void |
| 20106 | do_neon_ld_dup (void) |
| 20107 | { |
| 20108 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
| 20109 | int align_good, do_alignment = 0; |
| 20110 | |
| 20111 | if (et.type == NT_invtype) |
| 20112 | return; |
| 20113 | |
| 20114 | switch ((inst.instruction >> 8) & 3) |
| 20115 | { |
| 20116 | case 0: /* VLD1. */ |
| 20117 | gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); |
| 20118 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, |
| 20119 | &do_alignment, 16, 16, 32, 32, -1); |
| 20120 | if (align_good == FAIL) |
| 20121 | return; |
| 20122 | switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) |
| 20123 | { |
| 20124 | case 1: break; |
| 20125 | case 2: inst.instruction |= 1 << 5; break; |
| 20126 | default: first_error (_("bad list length")); return; |
| 20127 | } |
| 20128 | inst.instruction |= neon_logbits (et.size) << 6; |
| 20129 | break; |
| 20130 | |
| 20131 | case 1: /* VLD2. */ |
| 20132 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, |
| 20133 | &do_alignment, 8, 16, 16, 32, 32, 64, |
| 20134 | -1); |
| 20135 | if (align_good == FAIL) |
| 20136 | return; |
| 20137 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, |
| 20138 | _("bad list length")); |
| 20139 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) |
| 20140 | inst.instruction |= 1 << 5; |
| 20141 | inst.instruction |= neon_logbits (et.size) << 6; |
| 20142 | break; |
| 20143 | |
| 20144 | case 2: /* VLD3. */ |
| 20145 | constraint (inst.operands[1].immisalign, |
| 20146 | _("can't use alignment with this instruction")); |
| 20147 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, |
| 20148 | _("bad list length")); |
| 20149 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) |
| 20150 | inst.instruction |= 1 << 5; |
| 20151 | inst.instruction |= neon_logbits (et.size) << 6; |
| 20152 | break; |
| 20153 | |
| 20154 | case 3: /* VLD4. */ |
| 20155 | { |
| 20156 | int align = inst.operands[1].imm >> 8; |
| 20157 | align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32, |
| 20158 | 16, 64, 32, 64, 32, 128, -1); |
| 20159 | if (align_good == FAIL) |
| 20160 | return; |
| 20161 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, |
| 20162 | _("bad list length")); |
| 20163 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) |
| 20164 | inst.instruction |= 1 << 5; |
| 20165 | if (et.size == 32 && align == 128) |
| 20166 | inst.instruction |= 0x3 << 6; |
| 20167 | else |
| 20168 | inst.instruction |= neon_logbits (et.size) << 6; |
| 20169 | } |
| 20170 | break; |
| 20171 | |
| 20172 | default: ; |
| 20173 | } |
| 20174 | |
| 20175 | inst.instruction |= do_alignment << 4; |
| 20176 | } |
| 20177 | |
| 20178 | /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those |
| 20179 | apart from bits [11:4]. */ |
| 20180 | |
| 20181 | static void |
| 20182 | do_neon_ldx_stx (void) |
| 20183 | { |
| 20184 | if (inst.operands[1].isreg) |
| 20185 | constraint (inst.operands[1].reg == REG_PC, BAD_PC); |
| 20186 | |
| 20187 | switch (NEON_LANE (inst.operands[0].imm)) |
| 20188 | { |
| 20189 | case NEON_INTERLEAVE_LANES: |
| 20190 | NEON_ENCODE (INTERLV, inst); |
| 20191 | do_neon_ld_st_interleave (); |
| 20192 | break; |
| 20193 | |
| 20194 | case NEON_ALL_LANES: |
| 20195 | NEON_ENCODE (DUP, inst); |
| 20196 | if (inst.instruction == N_INV) |
| 20197 | { |
| 20198 | first_error ("only loads support such operands"); |
| 20199 | break; |
| 20200 | } |
| 20201 | do_neon_ld_dup (); |
| 20202 | break; |
| 20203 | |
| 20204 | default: |
| 20205 | NEON_ENCODE (LANE, inst); |
| 20206 | do_neon_ld_st_lane (); |
| 20207 | } |
| 20208 | |
| 20209 | /* L bit comes from bit mask. */ |
| 20210 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 20211 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 20212 | inst.instruction |= inst.operands[1].reg << 16; |
| 20213 | |
| 20214 | if (inst.operands[1].postind) |
| 20215 | { |
| 20216 | int postreg = inst.operands[1].imm & 0xf; |
| 20217 | constraint (!inst.operands[1].immisreg, |
| 20218 | _("post-index must be a register")); |
| 20219 | constraint (postreg == 0xd || postreg == 0xf, |
| 20220 | _("bad register for post-index")); |
| 20221 | inst.instruction |= postreg; |
| 20222 | } |
| 20223 | else |
| 20224 | { |
| 20225 | constraint (inst.operands[1].immisreg, BAD_ADDR_MODE); |
| 20226 | constraint (inst.relocs[0].exp.X_op != O_constant |
| 20227 | || inst.relocs[0].exp.X_add_number != 0, |
| 20228 | BAD_ADDR_MODE); |
| 20229 | |
| 20230 | if (inst.operands[1].writeback) |
| 20231 | { |
| 20232 | inst.instruction |= 0xd; |
| 20233 | } |
| 20234 | else |
| 20235 | inst.instruction |= 0xf; |
| 20236 | } |
| 20237 | |
| 20238 | if (thumb_mode) |
| 20239 | inst.instruction |= 0xf9000000; |
| 20240 | else |
| 20241 | inst.instruction |= 0xf4000000; |
| 20242 | } |
| 20243 | |
| 20244 | /* FP v8. */ |
| 20245 | static void |
| 20246 | do_vfp_nsyn_fpv8 (enum neon_shape rs) |
| 20247 | { |
| 20248 | /* Targets like FPv5-SP-D16 don't support FP v8 instructions with |
| 20249 | D register operands. */ |
| 20250 | if (neon_shape_class[rs] == SC_DOUBLE) |
| 20251 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), |
| 20252 | _(BAD_FPU)); |
| 20253 | |
| 20254 | NEON_ENCODE (FPV8, inst); |
| 20255 | |
| 20256 | if (rs == NS_FFF || rs == NS_HHH) |
| 20257 | { |
| 20258 | do_vfp_sp_dyadic (); |
| 20259 | |
| 20260 | /* ARMv8.2 fp16 instruction. */ |
| 20261 | if (rs == NS_HHH) |
| 20262 | do_scalar_fp16_v82_encode (); |
| 20263 | } |
| 20264 | else |
| 20265 | do_vfp_dp_rd_rn_rm (); |
| 20266 | |
| 20267 | if (rs == NS_DDD) |
| 20268 | inst.instruction |= 0x100; |
| 20269 | |
| 20270 | inst.instruction |= 0xf0000000; |
| 20271 | } |
| 20272 | |
| 20273 | static void |
| 20274 | do_vsel (void) |
| 20275 | { |
| 20276 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
| 20277 | |
| 20278 | if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS) |
| 20279 | first_error (_("invalid instruction shape")); |
| 20280 | } |
| 20281 | |
| 20282 | static void |
| 20283 | do_vmaxnm (void) |
| 20284 | { |
| 20285 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 20286 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
| 20287 | |
| 20288 | if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS) |
| 20289 | return; |
| 20290 | |
| 20291 | if (check_simd_pred_availability (1, NEON_CHECK_CC | NEON_CHECK_ARCH8)) |
| 20292 | return; |
| 20293 | |
| 20294 | neon_dyadic_misc (NT_untyped, N_F_16_32, 0); |
| 20295 | } |
| 20296 | |
| 20297 | static void |
| 20298 | do_vrint_1 (enum neon_cvt_mode mode) |
| 20299 | { |
| 20300 | enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_QQ, NS_NULL); |
| 20301 | struct neon_type_el et; |
| 20302 | |
| 20303 | if (rs == NS_NULL) |
| 20304 | return; |
| 20305 | |
| 20306 | /* Targets like FPv5-SP-D16 don't support FP v8 instructions with |
| 20307 | D register operands. */ |
| 20308 | if (neon_shape_class[rs] == SC_DOUBLE) |
| 20309 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), |
| 20310 | _(BAD_FPU)); |
| 20311 | |
| 20312 | et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY |
| 20313 | | N_VFP); |
| 20314 | if (et.type != NT_invtype) |
| 20315 | { |
| 20316 | /* VFP encodings. */ |
| 20317 | if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n |
| 20318 | || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m) |
| 20319 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
| 20320 | |
| 20321 | NEON_ENCODE (FPV8, inst); |
| 20322 | if (rs == NS_FF || rs == NS_HH) |
| 20323 | do_vfp_sp_monadic (); |
| 20324 | else |
| 20325 | do_vfp_dp_rd_rm (); |
| 20326 | |
| 20327 | switch (mode) |
| 20328 | { |
| 20329 | case neon_cvt_mode_r: inst.instruction |= 0x00000000; break; |
| 20330 | case neon_cvt_mode_z: inst.instruction |= 0x00000080; break; |
| 20331 | case neon_cvt_mode_x: inst.instruction |= 0x00010000; break; |
| 20332 | case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break; |
| 20333 | case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break; |
| 20334 | case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break; |
| 20335 | case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break; |
| 20336 | default: abort (); |
| 20337 | } |
| 20338 | |
| 20339 | inst.instruction |= (rs == NS_DD) << 8; |
| 20340 | do_vfp_cond_or_thumb (); |
| 20341 | |
| 20342 | /* ARMv8.2 fp16 vrint instruction. */ |
| 20343 | if (rs == NS_HH) |
| 20344 | do_scalar_fp16_v82_encode (); |
| 20345 | } |
| 20346 | else |
| 20347 | { |
| 20348 | /* Neon encodings (or something broken...). */ |
| 20349 | inst.error = NULL; |
| 20350 | et = neon_check_type (2, rs, N_EQK, N_F_16_32 | N_KEY); |
| 20351 | |
| 20352 | if (et.type == NT_invtype) |
| 20353 | return; |
| 20354 | |
| 20355 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
| 20356 | NEON_ENCODE (FLOAT, inst); |
| 20357 | |
| 20358 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL) |
| 20359 | return; |
| 20360 | |
| 20361 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 20362 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 20363 | inst.instruction |= LOW4 (inst.operands[1].reg); |
| 20364 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; |
| 20365 | inst.instruction |= neon_quad (rs) << 6; |
| 20366 | /* Mask off the original size bits and reencode them. */ |
| 20367 | inst.instruction = ((inst.instruction & 0xfff3ffff) |
| 20368 | | neon_logbits (et.size) << 18); |
| 20369 | |
| 20370 | switch (mode) |
| 20371 | { |
| 20372 | case neon_cvt_mode_z: inst.instruction |= 3 << 7; break; |
| 20373 | case neon_cvt_mode_x: inst.instruction |= 1 << 7; break; |
| 20374 | case neon_cvt_mode_a: inst.instruction |= 2 << 7; break; |
| 20375 | case neon_cvt_mode_n: inst.instruction |= 0 << 7; break; |
| 20376 | case neon_cvt_mode_p: inst.instruction |= 7 << 7; break; |
| 20377 | case neon_cvt_mode_m: inst.instruction |= 5 << 7; break; |
| 20378 | case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break; |
| 20379 | default: abort (); |
| 20380 | } |
| 20381 | |
| 20382 | if (thumb_mode) |
| 20383 | inst.instruction |= 0xfc000000; |
| 20384 | else |
| 20385 | inst.instruction |= 0xf0000000; |
| 20386 | } |
| 20387 | } |
| 20388 | |
| 20389 | static void |
| 20390 | do_vrintx (void) |
| 20391 | { |
| 20392 | do_vrint_1 (neon_cvt_mode_x); |
| 20393 | } |
| 20394 | |
| 20395 | static void |
| 20396 | do_vrintz (void) |
| 20397 | { |
| 20398 | do_vrint_1 (neon_cvt_mode_z); |
| 20399 | } |
| 20400 | |
| 20401 | static void |
| 20402 | do_vrintr (void) |
| 20403 | { |
| 20404 | do_vrint_1 (neon_cvt_mode_r); |
| 20405 | } |
| 20406 | |
| 20407 | static void |
| 20408 | do_vrinta (void) |
| 20409 | { |
| 20410 | do_vrint_1 (neon_cvt_mode_a); |
| 20411 | } |
| 20412 | |
| 20413 | static void |
| 20414 | do_vrintn (void) |
| 20415 | { |
| 20416 | do_vrint_1 (neon_cvt_mode_n); |
| 20417 | } |
| 20418 | |
| 20419 | static void |
| 20420 | do_vrintp (void) |
| 20421 | { |
| 20422 | do_vrint_1 (neon_cvt_mode_p); |
| 20423 | } |
| 20424 | |
| 20425 | static void |
| 20426 | do_vrintm (void) |
| 20427 | { |
| 20428 | do_vrint_1 (neon_cvt_mode_m); |
| 20429 | } |
| 20430 | |
| 20431 | static unsigned |
| 20432 | neon_scalar_for_vcmla (unsigned opnd, unsigned elsize) |
| 20433 | { |
| 20434 | unsigned regno = NEON_SCALAR_REG (opnd); |
| 20435 | unsigned elno = NEON_SCALAR_INDEX (opnd); |
| 20436 | |
| 20437 | if (elsize == 16 && elno < 2 && regno < 16) |
| 20438 | return regno | (elno << 4); |
| 20439 | else if (elsize == 32 && elno == 0) |
| 20440 | return regno; |
| 20441 | |
| 20442 | first_error (_("scalar out of range")); |
| 20443 | return 0; |
| 20444 | } |
| 20445 | |
| 20446 | static void |
| 20447 | do_vcmla (void) |
| 20448 | { |
| 20449 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext) |
| 20450 | && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8) |
| 20451 | || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU)); |
| 20452 | constraint (inst.relocs[0].exp.X_op != O_constant, |
| 20453 | _("expression too complex")); |
| 20454 | unsigned rot = inst.relocs[0].exp.X_add_number; |
| 20455 | constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270, |
| 20456 | _("immediate out of range")); |
| 20457 | rot /= 90; |
| 20458 | |
| 20459 | if (check_simd_pred_availability (1, NEON_CHECK_ARCH8 | NEON_CHECK_CC)) |
| 20460 | return; |
| 20461 | |
| 20462 | if (inst.operands[2].isscalar) |
| 20463 | { |
| 20464 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)) |
| 20465 | first_error (_("invalid instruction shape")); |
| 20466 | enum neon_shape rs = neon_select_shape (NS_DDSI, NS_QQSI, NS_NULL); |
| 20467 | unsigned size = neon_check_type (3, rs, N_EQK, N_EQK, |
| 20468 | N_KEY | N_F16 | N_F32).size; |
| 20469 | unsigned m = neon_scalar_for_vcmla (inst.operands[2].reg, size); |
| 20470 | inst.is_neon = 1; |
| 20471 | inst.instruction = 0xfe000800; |
| 20472 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 20473 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 20474 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; |
| 20475 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; |
| 20476 | inst.instruction |= LOW4 (m); |
| 20477 | inst.instruction |= HI1 (m) << 5; |
| 20478 | inst.instruction |= neon_quad (rs) << 6; |
| 20479 | inst.instruction |= rot << 20; |
| 20480 | inst.instruction |= (size == 32) << 23; |
| 20481 | } |
| 20482 | else |
| 20483 | { |
| 20484 | enum neon_shape rs; |
| 20485 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)) |
| 20486 | rs = neon_select_shape (NS_QQQI, NS_NULL); |
| 20487 | else |
| 20488 | rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); |
| 20489 | |
| 20490 | unsigned size = neon_check_type (3, rs, N_EQK, N_EQK, |
| 20491 | N_KEY | N_F16 | N_F32).size; |
| 20492 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext) && size == 32 |
| 20493 | && (inst.operands[0].reg == inst.operands[1].reg |
| 20494 | || inst.operands[0].reg == inst.operands[2].reg)) |
| 20495 | as_tsktsk (BAD_MVE_SRCDEST); |
| 20496 | |
| 20497 | neon_three_same (neon_quad (rs), 0, -1); |
| 20498 | inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */ |
| 20499 | inst.instruction |= 0xfc200800; |
| 20500 | inst.instruction |= rot << 23; |
| 20501 | inst.instruction |= (size == 32) << 20; |
| 20502 | } |
| 20503 | } |
| 20504 | |
| 20505 | static void |
| 20506 | do_vcadd (void) |
| 20507 | { |
| 20508 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) |
| 20509 | && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8) |
| 20510 | || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU)); |
| 20511 | constraint (inst.relocs[0].exp.X_op != O_constant, |
| 20512 | _("expression too complex")); |
| 20513 | |
| 20514 | unsigned rot = inst.relocs[0].exp.X_add_number; |
| 20515 | constraint (rot != 90 && rot != 270, _("immediate out of range")); |
| 20516 | enum neon_shape rs; |
| 20517 | struct neon_type_el et; |
| 20518 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 20519 | { |
| 20520 | rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); |
| 20521 | et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32); |
| 20522 | } |
| 20523 | else |
| 20524 | { |
| 20525 | rs = neon_select_shape (NS_QQQI, NS_NULL); |
| 20526 | et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32 | N_I8 |
| 20527 | | N_I16 | N_I32); |
| 20528 | if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg) |
| 20529 | as_tsktsk (_("Warning: 32-bit element size and same first and third " |
| 20530 | "operand makes instruction UNPREDICTABLE")); |
| 20531 | } |
| 20532 | |
| 20533 | if (et.type == NT_invtype) |
| 20534 | return; |
| 20535 | |
| 20536 | if (check_simd_pred_availability (et.type == NT_float, NEON_CHECK_ARCH8 |
| 20537 | | NEON_CHECK_CC)) |
| 20538 | return; |
| 20539 | |
| 20540 | if (et.type == NT_float) |
| 20541 | { |
| 20542 | neon_three_same (neon_quad (rs), 0, -1); |
| 20543 | inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */ |
| 20544 | inst.instruction |= 0xfc800800; |
| 20545 | inst.instruction |= (rot == 270) << 24; |
| 20546 | inst.instruction |= (et.size == 32) << 20; |
| 20547 | } |
| 20548 | else |
| 20549 | { |
| 20550 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); |
| 20551 | inst.instruction = 0xfe000f00; |
| 20552 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 20553 | inst.instruction |= neon_logbits (et.size) << 20; |
| 20554 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; |
| 20555 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 20556 | inst.instruction |= (rot == 270) << 12; |
| 20557 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; |
| 20558 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; |
| 20559 | inst.instruction |= LOW4 (inst.operands[2].reg); |
| 20560 | inst.is_neon = 1; |
| 20561 | } |
| 20562 | } |
| 20563 | |
| 20564 | /* Dot Product instructions encoding support. */ |
| 20565 | |
| 20566 | static void |
| 20567 | do_neon_dotproduct (int unsigned_p) |
| 20568 | { |
| 20569 | enum neon_shape rs; |
| 20570 | unsigned scalar_oprd2 = 0; |
| 20571 | int high8; |
| 20572 | |
| 20573 | if (inst.cond != COND_ALWAYS) |
| 20574 | as_warn (_("Dot Product instructions cannot be conditional, the behaviour " |
| 20575 | "is UNPREDICTABLE")); |
| 20576 | |
| 20577 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8), |
| 20578 | _(BAD_FPU)); |
| 20579 | |
| 20580 | /* Dot Product instructions are in three-same D/Q register format or the third |
| 20581 | operand can be a scalar index register. */ |
| 20582 | if (inst.operands[2].isscalar) |
| 20583 | { |
| 20584 | scalar_oprd2 = neon_scalar_for_mul (inst.operands[2].reg, 32); |
| 20585 | high8 = 0xfe000000; |
| 20586 | rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
| 20587 | } |
| 20588 | else |
| 20589 | { |
| 20590 | high8 = 0xfc000000; |
| 20591 | rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
| 20592 | } |
| 20593 | |
| 20594 | if (unsigned_p) |
| 20595 | neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_U8); |
| 20596 | else |
| 20597 | neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_S8); |
| 20598 | |
| 20599 | /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot |
| 20600 | Product instruction, so we pass 0 as the "ubit" parameter. And the |
| 20601 | "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */ |
| 20602 | neon_three_same (neon_quad (rs), 0, 32); |
| 20603 | |
| 20604 | /* Undo neon_dp_fixup. Dot Product instructions are using a slightly |
| 20605 | different NEON three-same encoding. */ |
| 20606 | inst.instruction &= 0x00ffffff; |
| 20607 | inst.instruction |= high8; |
| 20608 | /* Encode 'U' bit which indicates signedness. */ |
| 20609 | inst.instruction |= (unsigned_p ? 1 : 0) << 4; |
| 20610 | /* Re-encode operand2 if it's indexed scalar operand. What has been encoded |
| 20611 | from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not |
| 20612 | the instruction encoding. */ |
| 20613 | if (inst.operands[2].isscalar) |
| 20614 | { |
| 20615 | inst.instruction &= 0xffffffd0; |
| 20616 | inst.instruction |= LOW4 (scalar_oprd2); |
| 20617 | inst.instruction |= HI1 (scalar_oprd2) << 5; |
| 20618 | } |
| 20619 | } |
| 20620 | |
| 20621 | /* Dot Product instructions for signed integer. */ |
| 20622 | |
| 20623 | static void |
| 20624 | do_neon_dotproduct_s (void) |
| 20625 | { |
| 20626 | return do_neon_dotproduct (0); |
| 20627 | } |
| 20628 | |
| 20629 | /* Dot Product instructions for unsigned integer. */ |
| 20630 | |
| 20631 | static void |
| 20632 | do_neon_dotproduct_u (void) |
| 20633 | { |
| 20634 | return do_neon_dotproduct (1); |
| 20635 | } |
| 20636 | |
| 20637 | /* Crypto v1 instructions. */ |
| 20638 | static void |
| 20639 | do_crypto_2op_1 (unsigned elttype, int op) |
| 20640 | { |
| 20641 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
| 20642 | |
| 20643 | if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type |
| 20644 | == NT_invtype) |
| 20645 | return; |
| 20646 | |
| 20647 | inst.error = NULL; |
| 20648 | |
| 20649 | NEON_ENCODE (INTEGER, inst); |
| 20650 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
| 20651 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
| 20652 | inst.instruction |= LOW4 (inst.operands[1].reg); |
| 20653 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; |
| 20654 | if (op != -1) |
| 20655 | inst.instruction |= op << 6; |
| 20656 | |
| 20657 | if (thumb_mode) |
| 20658 | inst.instruction |= 0xfc000000; |
| 20659 | else |
| 20660 | inst.instruction |= 0xf0000000; |
| 20661 | } |
| 20662 | |
| 20663 | static void |
| 20664 | do_crypto_3op_1 (int u, int op) |
| 20665 | { |
| 20666 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
| 20667 | |
| 20668 | if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT, |
| 20669 | N_32 | N_UNT | N_KEY).type == NT_invtype) |
| 20670 | return; |
| 20671 | |
| 20672 | inst.error = NULL; |
| 20673 | |
| 20674 | NEON_ENCODE (INTEGER, inst); |
| 20675 | neon_three_same (1, u, 8 << op); |
| 20676 | } |
| 20677 | |
| 20678 | static void |
| 20679 | do_aese (void) |
| 20680 | { |
| 20681 | do_crypto_2op_1 (N_8, 0); |
| 20682 | } |
| 20683 | |
| 20684 | static void |
| 20685 | do_aesd (void) |
| 20686 | { |
| 20687 | do_crypto_2op_1 (N_8, 1); |
| 20688 | } |
| 20689 | |
| 20690 | static void |
| 20691 | do_aesmc (void) |
| 20692 | { |
| 20693 | do_crypto_2op_1 (N_8, 2); |
| 20694 | } |
| 20695 | |
| 20696 | static void |
| 20697 | do_aesimc (void) |
| 20698 | { |
| 20699 | do_crypto_2op_1 (N_8, 3); |
| 20700 | } |
| 20701 | |
| 20702 | static void |
| 20703 | do_sha1c (void) |
| 20704 | { |
| 20705 | do_crypto_3op_1 (0, 0); |
| 20706 | } |
| 20707 | |
| 20708 | static void |
| 20709 | do_sha1p (void) |
| 20710 | { |
| 20711 | do_crypto_3op_1 (0, 1); |
| 20712 | } |
| 20713 | |
| 20714 | static void |
| 20715 | do_sha1m (void) |
| 20716 | { |
| 20717 | do_crypto_3op_1 (0, 2); |
| 20718 | } |
| 20719 | |
| 20720 | static void |
| 20721 | do_sha1su0 (void) |
| 20722 | { |
| 20723 | do_crypto_3op_1 (0, 3); |
| 20724 | } |
| 20725 | |
| 20726 | static void |
| 20727 | do_sha256h (void) |
| 20728 | { |
| 20729 | do_crypto_3op_1 (1, 0); |
| 20730 | } |
| 20731 | |
| 20732 | static void |
| 20733 | do_sha256h2 (void) |
| 20734 | { |
| 20735 | do_crypto_3op_1 (1, 1); |
| 20736 | } |
| 20737 | |
| 20738 | static void |
| 20739 | do_sha256su1 (void) |
| 20740 | { |
| 20741 | do_crypto_3op_1 (1, 2); |
| 20742 | } |
| 20743 | |
| 20744 | static void |
| 20745 | do_sha1h (void) |
| 20746 | { |
| 20747 | do_crypto_2op_1 (N_32, -1); |
| 20748 | } |
| 20749 | |
| 20750 | static void |
| 20751 | do_sha1su1 (void) |
| 20752 | { |
| 20753 | do_crypto_2op_1 (N_32, 0); |
| 20754 | } |
| 20755 | |
| 20756 | static void |
| 20757 | do_sha256su0 (void) |
| 20758 | { |
| 20759 | do_crypto_2op_1 (N_32, 1); |
| 20760 | } |
| 20761 | |
| 20762 | static void |
| 20763 | do_crc32_1 (unsigned int poly, unsigned int sz) |
| 20764 | { |
| 20765 | unsigned int Rd = inst.operands[0].reg; |
| 20766 | unsigned int Rn = inst.operands[1].reg; |
| 20767 | unsigned int Rm = inst.operands[2].reg; |
| 20768 | |
| 20769 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
| 20770 | inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12); |
| 20771 | inst.instruction |= LOW4 (Rn) << 16; |
| 20772 | inst.instruction |= LOW4 (Rm); |
| 20773 | inst.instruction |= sz << (thumb_mode ? 4 : 21); |
| 20774 | inst.instruction |= poly << (thumb_mode ? 20 : 9); |
| 20775 | |
| 20776 | if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC) |
| 20777 | as_warn (UNPRED_REG ("r15")); |
| 20778 | } |
| 20779 | |
| 20780 | static void |
| 20781 | do_crc32b (void) |
| 20782 | { |
| 20783 | do_crc32_1 (0, 0); |
| 20784 | } |
| 20785 | |
| 20786 | static void |
| 20787 | do_crc32h (void) |
| 20788 | { |
| 20789 | do_crc32_1 (0, 1); |
| 20790 | } |
| 20791 | |
| 20792 | static void |
| 20793 | do_crc32w (void) |
| 20794 | { |
| 20795 | do_crc32_1 (0, 2); |
| 20796 | } |
| 20797 | |
| 20798 | static void |
| 20799 | do_crc32cb (void) |
| 20800 | { |
| 20801 | do_crc32_1 (1, 0); |
| 20802 | } |
| 20803 | |
| 20804 | static void |
| 20805 | do_crc32ch (void) |
| 20806 | { |
| 20807 | do_crc32_1 (1, 1); |
| 20808 | } |
| 20809 | |
| 20810 | static void |
| 20811 | do_crc32cw (void) |
| 20812 | { |
| 20813 | do_crc32_1 (1, 2); |
| 20814 | } |
| 20815 | |
| 20816 | static void |
| 20817 | do_vjcvt (void) |
| 20818 | { |
| 20819 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), |
| 20820 | _(BAD_FPU)); |
| 20821 | neon_check_type (2, NS_FD, N_S32, N_F64); |
| 20822 | do_vfp_sp_dp_cvt (); |
| 20823 | do_vfp_cond_or_thumb (); |
| 20824 | } |
| 20825 | |
| 20826 | \f |
| 20827 | /* Overall per-instruction processing. */ |
| 20828 | |
| 20829 | /* We need to be able to fix up arbitrary expressions in some statements. |
| 20830 | This is so that we can handle symbols that are an arbitrary distance from |
| 20831 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), |
| 20832 | which returns part of an address in a form which will be valid for |
| 20833 | a data instruction. We do this by pushing the expression into a symbol |
| 20834 | in the expr_section, and creating a fix for that. */ |
| 20835 | |
| 20836 | static void |
| 20837 | fix_new_arm (fragS * frag, |
| 20838 | int where, |
| 20839 | short int size, |
| 20840 | expressionS * exp, |
| 20841 | int pc_rel, |
| 20842 | int reloc) |
| 20843 | { |
| 20844 | fixS * new_fix; |
| 20845 | |
| 20846 | switch (exp->X_op) |
| 20847 | { |
| 20848 | case O_constant: |
| 20849 | if (pc_rel) |
| 20850 | { |
| 20851 | /* Create an absolute valued symbol, so we have something to |
| 20852 | refer to in the object file. Unfortunately for us, gas's |
| 20853 | generic expression parsing will already have folded out |
| 20854 | any use of .set foo/.type foo %function that may have |
| 20855 | been used to set type information of the target location, |
| 20856 | that's being specified symbolically. We have to presume |
| 20857 | the user knows what they are doing. */ |
| 20858 | char name[16 + 8]; |
| 20859 | symbolS *symbol; |
| 20860 | |
| 20861 | sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number); |
| 20862 | |
| 20863 | symbol = symbol_find_or_make (name); |
| 20864 | S_SET_SEGMENT (symbol, absolute_section); |
| 20865 | symbol_set_frag (symbol, &zero_address_frag); |
| 20866 | S_SET_VALUE (symbol, exp->X_add_number); |
| 20867 | exp->X_op = O_symbol; |
| 20868 | exp->X_add_symbol = symbol; |
| 20869 | exp->X_add_number = 0; |
| 20870 | } |
| 20871 | /* FALLTHROUGH */ |
| 20872 | case O_symbol: |
| 20873 | case O_add: |
| 20874 | case O_subtract: |
| 20875 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, |
| 20876 | (enum bfd_reloc_code_real) reloc); |
| 20877 | break; |
| 20878 | |
| 20879 | default: |
| 20880 | new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0, |
| 20881 | pc_rel, (enum bfd_reloc_code_real) reloc); |
| 20882 | break; |
| 20883 | } |
| 20884 | |
| 20885 | /* Mark whether the fix is to a THUMB instruction, or an ARM |
| 20886 | instruction. */ |
| 20887 | new_fix->tc_fix_data = thumb_mode; |
| 20888 | } |
| 20889 | |
| 20890 | /* Create a frg for an instruction requiring relaxation. */ |
| 20891 | static void |
| 20892 | output_relax_insn (void) |
| 20893 | { |
| 20894 | char * to; |
| 20895 | symbolS *sym; |
| 20896 | int offset; |
| 20897 | |
| 20898 | /* The size of the instruction is unknown, so tie the debug info to the |
| 20899 | start of the instruction. */ |
| 20900 | dwarf2_emit_insn (0); |
| 20901 | |
| 20902 | switch (inst.relocs[0].exp.X_op) |
| 20903 | { |
| 20904 | case O_symbol: |
| 20905 | sym = inst.relocs[0].exp.X_add_symbol; |
| 20906 | offset = inst.relocs[0].exp.X_add_number; |
| 20907 | break; |
| 20908 | case O_constant: |
| 20909 | sym = NULL; |
| 20910 | offset = inst.relocs[0].exp.X_add_number; |
| 20911 | break; |
| 20912 | default: |
| 20913 | sym = make_expr_symbol (&inst.relocs[0].exp); |
| 20914 | offset = 0; |
| 20915 | break; |
| 20916 | } |
| 20917 | to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, |
| 20918 | inst.relax, sym, offset, NULL/*offset, opcode*/); |
| 20919 | md_number_to_chars (to, inst.instruction, THUMB_SIZE); |
| 20920 | } |
| 20921 | |
| 20922 | /* Write a 32-bit thumb instruction to buf. */ |
| 20923 | static void |
| 20924 | put_thumb32_insn (char * buf, unsigned long insn) |
| 20925 | { |
| 20926 | md_number_to_chars (buf, insn >> 16, THUMB_SIZE); |
| 20927 | md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); |
| 20928 | } |
| 20929 | |
| 20930 | static void |
| 20931 | output_inst (const char * str) |
| 20932 | { |
| 20933 | char * to = NULL; |
| 20934 | |
| 20935 | if (inst.error) |
| 20936 | { |
| 20937 | as_bad ("%s -- `%s'", inst.error, str); |
| 20938 | return; |
| 20939 | } |
| 20940 | if (inst.relax) |
| 20941 | { |
| 20942 | output_relax_insn (); |
| 20943 | return; |
| 20944 | } |
| 20945 | if (inst.size == 0) |
| 20946 | return; |
| 20947 | |
| 20948 | to = frag_more (inst.size); |
| 20949 | /* PR 9814: Record the thumb mode into the current frag so that we know |
| 20950 | what type of NOP padding to use, if necessary. We override any previous |
| 20951 | setting so that if the mode has changed then the NOPS that we use will |
| 20952 | match the encoding of the last instruction in the frag. */ |
| 20953 | frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
| 20954 | |
| 20955 | if (thumb_mode && (inst.size > THUMB_SIZE)) |
| 20956 | { |
| 20957 | gas_assert (inst.size == (2 * THUMB_SIZE)); |
| 20958 | put_thumb32_insn (to, inst.instruction); |
| 20959 | } |
| 20960 | else if (inst.size > INSN_SIZE) |
| 20961 | { |
| 20962 | gas_assert (inst.size == (2 * INSN_SIZE)); |
| 20963 | md_number_to_chars (to, inst.instruction, INSN_SIZE); |
| 20964 | md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); |
| 20965 | } |
| 20966 | else |
| 20967 | md_number_to_chars (to, inst.instruction, inst.size); |
| 20968 | |
| 20969 | int r; |
| 20970 | for (r = 0; r < ARM_IT_MAX_RELOCS; r++) |
| 20971 | { |
| 20972 | if (inst.relocs[r].type != BFD_RELOC_UNUSED) |
| 20973 | fix_new_arm (frag_now, to - frag_now->fr_literal, |
| 20974 | inst.size, & inst.relocs[r].exp, inst.relocs[r].pc_rel, |
| 20975 | inst.relocs[r].type); |
| 20976 | } |
| 20977 | |
| 20978 | dwarf2_emit_insn (inst.size); |
| 20979 | } |
| 20980 | |
| 20981 | static char * |
| 20982 | output_it_inst (int cond, int mask, char * to) |
| 20983 | { |
| 20984 | unsigned long instruction = 0xbf00; |
| 20985 | |
| 20986 | mask &= 0xf; |
| 20987 | instruction |= mask; |
| 20988 | instruction |= cond << 4; |
| 20989 | |
| 20990 | if (to == NULL) |
| 20991 | { |
| 20992 | to = frag_more (2); |
| 20993 | #ifdef OBJ_ELF |
| 20994 | dwarf2_emit_insn (2); |
| 20995 | #endif |
| 20996 | } |
| 20997 | |
| 20998 | md_number_to_chars (to, instruction, 2); |
| 20999 | |
| 21000 | return to; |
| 21001 | } |
| 21002 | |
| 21003 | /* Tag values used in struct asm_opcode's tag field. */ |
| 21004 | enum opcode_tag |
| 21005 | { |
| 21006 | OT_unconditional, /* Instruction cannot be conditionalized. |
| 21007 | The ARM condition field is still 0xE. */ |
| 21008 | OT_unconditionalF, /* Instruction cannot be conditionalized |
| 21009 | and carries 0xF in its ARM condition field. */ |
| 21010 | OT_csuffix, /* Instruction takes a conditional suffix. */ |
| 21011 | OT_csuffixF, /* Some forms of the instruction take a scalar |
| 21012 | conditional suffix, others place 0xF where the |
| 21013 | condition field would be, others take a vector |
| 21014 | conditional suffix. */ |
| 21015 | OT_cinfix3, /* Instruction takes a conditional infix, |
| 21016 | beginning at character index 3. (In |
| 21017 | unified mode, it becomes a suffix.) */ |
| 21018 | OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for |
| 21019 | tsts, cmps, cmns, and teqs. */ |
| 21020 | OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at |
| 21021 | character index 3, even in unified mode. Used for |
| 21022 | legacy instructions where suffix and infix forms |
| 21023 | may be ambiguous. */ |
| 21024 | OT_csuf_or_in3, /* Instruction takes either a conditional |
| 21025 | suffix or an infix at character index 3. */ |
| 21026 | OT_odd_infix_unc, /* This is the unconditional variant of an |
| 21027 | instruction that takes a conditional infix |
| 21028 | at an unusual position. In unified mode, |
| 21029 | this variant will accept a suffix. */ |
| 21030 | OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 |
| 21031 | are the conditional variants of instructions that |
| 21032 | take conditional infixes in unusual positions. |
| 21033 | The infix appears at character index |
| 21034 | (tag - OT_odd_infix_0). These are not accepted |
| 21035 | in unified mode. */ |
| 21036 | }; |
| 21037 | |
| 21038 | /* Subroutine of md_assemble, responsible for looking up the primary |
| 21039 | opcode from the mnemonic the user wrote. STR points to the |
| 21040 | beginning of the mnemonic. |
| 21041 | |
| 21042 | This is not simply a hash table lookup, because of conditional |
| 21043 | variants. Most instructions have conditional variants, which are |
| 21044 | expressed with a _conditional affix_ to the mnemonic. If we were |
| 21045 | to encode each conditional variant as a literal string in the opcode |
| 21046 | table, it would have approximately 20,000 entries. |
| 21047 | |
| 21048 | Most mnemonics take this affix as a suffix, and in unified syntax, |
| 21049 | 'most' is upgraded to 'all'. However, in the divided syntax, some |
| 21050 | instructions take the affix as an infix, notably the s-variants of |
| 21051 | the arithmetic instructions. Of those instructions, all but six |
| 21052 | have the infix appear after the third character of the mnemonic. |
| 21053 | |
| 21054 | Accordingly, the algorithm for looking up primary opcodes given |
| 21055 | an identifier is: |
| 21056 | |
| 21057 | 1. Look up the identifier in the opcode table. |
| 21058 | If we find a match, go to step U. |
| 21059 | |
| 21060 | 2. Look up the last two characters of the identifier in the |
| 21061 | conditions table. If we find a match, look up the first N-2 |
| 21062 | characters of the identifier in the opcode table. If we |
| 21063 | find a match, go to step CE. |
| 21064 | |
| 21065 | 3. Look up the fourth and fifth characters of the identifier in |
| 21066 | the conditions table. If we find a match, extract those |
| 21067 | characters from the identifier, and look up the remaining |
| 21068 | characters in the opcode table. If we find a match, go |
| 21069 | to step CM. |
| 21070 | |
| 21071 | 4. Fail. |
| 21072 | |
| 21073 | U. Examine the tag field of the opcode structure, in case this is |
| 21074 | one of the six instructions with its conditional infix in an |
| 21075 | unusual place. If it is, the tag tells us where to find the |
| 21076 | infix; look it up in the conditions table and set inst.cond |
| 21077 | accordingly. Otherwise, this is an unconditional instruction. |
| 21078 | Again set inst.cond accordingly. Return the opcode structure. |
| 21079 | |
| 21080 | CE. Examine the tag field to make sure this is an instruction that |
| 21081 | should receive a conditional suffix. If it is not, fail. |
| 21082 | Otherwise, set inst.cond from the suffix we already looked up, |
| 21083 | and return the opcode structure. |
| 21084 | |
| 21085 | CM. Examine the tag field to make sure this is an instruction that |
| 21086 | should receive a conditional infix after the third character. |
| 21087 | If it is not, fail. Otherwise, undo the edits to the current |
| 21088 | line of input and proceed as for case CE. */ |
| 21089 | |
| 21090 | static const struct asm_opcode * |
| 21091 | opcode_lookup (char **str) |
| 21092 | { |
| 21093 | char *end, *base; |
| 21094 | char *affix; |
| 21095 | const struct asm_opcode *opcode; |
| 21096 | const struct asm_cond *cond; |
| 21097 | char save[2]; |
| 21098 | |
| 21099 | /* Scan up to the end of the mnemonic, which must end in white space, |
| 21100 | '.' (in unified mode, or for Neon/VFP instructions), or end of string. */ |
| 21101 | for (base = end = *str; *end != '\0'; end++) |
| 21102 | if (*end == ' ' || *end == '.') |
| 21103 | break; |
| 21104 | |
| 21105 | if (end == base) |
| 21106 | return NULL; |
| 21107 | |
| 21108 | /* Handle a possible width suffix and/or Neon type suffix. */ |
| 21109 | if (end[0] == '.') |
| 21110 | { |
| 21111 | int offset = 2; |
| 21112 | |
| 21113 | /* The .w and .n suffixes are only valid if the unified syntax is in |
| 21114 | use. */ |
| 21115 | if (unified_syntax && end[1] == 'w') |
| 21116 | inst.size_req = 4; |
| 21117 | else if (unified_syntax && end[1] == 'n') |
| 21118 | inst.size_req = 2; |
| 21119 | else |
| 21120 | offset = 0; |
| 21121 | |
| 21122 | inst.vectype.elems = 0; |
| 21123 | |
| 21124 | *str = end + offset; |
| 21125 | |
| 21126 | if (end[offset] == '.') |
| 21127 | { |
| 21128 | /* See if we have a Neon type suffix (possible in either unified or |
| 21129 | non-unified ARM syntax mode). */ |
| 21130 | if (parse_neon_type (&inst.vectype, str) == FAIL) |
| 21131 | return NULL; |
| 21132 | } |
| 21133 | else if (end[offset] != '\0' && end[offset] != ' ') |
| 21134 | return NULL; |
| 21135 | } |
| 21136 | else |
| 21137 | *str = end; |
| 21138 | |
| 21139 | /* Look for unaffixed or special-case affixed mnemonic. */ |
| 21140 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
| 21141 | end - base); |
| 21142 | if (opcode) |
| 21143 | { |
| 21144 | /* step U */ |
| 21145 | if (opcode->tag < OT_odd_infix_0) |
| 21146 | { |
| 21147 | inst.cond = COND_ALWAYS; |
| 21148 | return opcode; |
| 21149 | } |
| 21150 | |
| 21151 | if (warn_on_deprecated && unified_syntax) |
| 21152 | as_tsktsk (_("conditional infixes are deprecated in unified syntax")); |
| 21153 | affix = base + (opcode->tag - OT_odd_infix_0); |
| 21154 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
| 21155 | gas_assert (cond); |
| 21156 | |
| 21157 | inst.cond = cond->value; |
| 21158 | return opcode; |
| 21159 | } |
| 21160 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
| 21161 | { |
| 21162 | /* Cannot have a conditional suffix on a mnemonic of less than a character. |
| 21163 | */ |
| 21164 | if (end - base < 2) |
| 21165 | return NULL; |
| 21166 | affix = end - 1; |
| 21167 | cond = (const struct asm_cond *) hash_find_n (arm_vcond_hsh, affix, 1); |
| 21168 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
| 21169 | affix - base); |
| 21170 | /* If this opcode can not be vector predicated then don't accept it with a |
| 21171 | vector predication code. */ |
| 21172 | if (opcode && !opcode->mayBeVecPred) |
| 21173 | opcode = NULL; |
| 21174 | } |
| 21175 | if (!opcode || !cond) |
| 21176 | { |
| 21177 | /* Cannot have a conditional suffix on a mnemonic of less than two |
| 21178 | characters. */ |
| 21179 | if (end - base < 3) |
| 21180 | return NULL; |
| 21181 | |
| 21182 | /* Look for suffixed mnemonic. */ |
| 21183 | affix = end - 2; |
| 21184 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
| 21185 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
| 21186 | affix - base); |
| 21187 | } |
| 21188 | |
| 21189 | if (opcode && cond) |
| 21190 | { |
| 21191 | /* step CE */ |
| 21192 | switch (opcode->tag) |
| 21193 | { |
| 21194 | case OT_cinfix3_legacy: |
| 21195 | /* Ignore conditional suffixes matched on infix only mnemonics. */ |
| 21196 | break; |
| 21197 | |
| 21198 | case OT_cinfix3: |
| 21199 | case OT_cinfix3_deprecated: |
| 21200 | case OT_odd_infix_unc: |
| 21201 | if (!unified_syntax) |
| 21202 | return NULL; |
| 21203 | /* Fall through. */ |
| 21204 | |
| 21205 | case OT_csuffix: |
| 21206 | case OT_csuffixF: |
| 21207 | case OT_csuf_or_in3: |
| 21208 | inst.cond = cond->value; |
| 21209 | return opcode; |
| 21210 | |
| 21211 | case OT_unconditional: |
| 21212 | case OT_unconditionalF: |
| 21213 | if (thumb_mode) |
| 21214 | inst.cond = cond->value; |
| 21215 | else |
| 21216 | { |
| 21217 | /* Delayed diagnostic. */ |
| 21218 | inst.error = BAD_COND; |
| 21219 | inst.cond = COND_ALWAYS; |
| 21220 | } |
| 21221 | return opcode; |
| 21222 | |
| 21223 | default: |
| 21224 | return NULL; |
| 21225 | } |
| 21226 | } |
| 21227 | |
| 21228 | /* Cannot have a usual-position infix on a mnemonic of less than |
| 21229 | six characters (five would be a suffix). */ |
| 21230 | if (end - base < 6) |
| 21231 | return NULL; |
| 21232 | |
| 21233 | /* Look for infixed mnemonic in the usual position. */ |
| 21234 | affix = base + 3; |
| 21235 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
| 21236 | if (!cond) |
| 21237 | return NULL; |
| 21238 | |
| 21239 | memcpy (save, affix, 2); |
| 21240 | memmove (affix, affix + 2, (end - affix) - 2); |
| 21241 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
| 21242 | (end - base) - 2); |
| 21243 | memmove (affix + 2, affix, (end - affix) - 2); |
| 21244 | memcpy (affix, save, 2); |
| 21245 | |
| 21246 | if (opcode |
| 21247 | && (opcode->tag == OT_cinfix3 |
| 21248 | || opcode->tag == OT_cinfix3_deprecated |
| 21249 | || opcode->tag == OT_csuf_or_in3 |
| 21250 | || opcode->tag == OT_cinfix3_legacy)) |
| 21251 | { |
| 21252 | /* Step CM. */ |
| 21253 | if (warn_on_deprecated && unified_syntax |
| 21254 | && (opcode->tag == OT_cinfix3 |
| 21255 | || opcode->tag == OT_cinfix3_deprecated)) |
| 21256 | as_tsktsk (_("conditional infixes are deprecated in unified syntax")); |
| 21257 | |
| 21258 | inst.cond = cond->value; |
| 21259 | return opcode; |
| 21260 | } |
| 21261 | |
| 21262 | return NULL; |
| 21263 | } |
| 21264 | |
| 21265 | /* This function generates an initial IT instruction, leaving its block |
| 21266 | virtually open for the new instructions. Eventually, |
| 21267 | the mask will be updated by now_pred_add_mask () each time |
| 21268 | a new instruction needs to be included in the IT block. |
| 21269 | Finally, the block is closed with close_automatic_it_block (). |
| 21270 | The block closure can be requested either from md_assemble (), |
| 21271 | a tencode (), or due to a label hook. */ |
| 21272 | |
| 21273 | static void |
| 21274 | new_automatic_it_block (int cond) |
| 21275 | { |
| 21276 | now_pred.state = AUTOMATIC_PRED_BLOCK; |
| 21277 | now_pred.mask = 0x18; |
| 21278 | now_pred.cc = cond; |
| 21279 | now_pred.block_length = 1; |
| 21280 | mapping_state (MAP_THUMB); |
| 21281 | now_pred.insn = output_it_inst (cond, now_pred.mask, NULL); |
| 21282 | now_pred.warn_deprecated = FALSE; |
| 21283 | now_pred.insn_cond = TRUE; |
| 21284 | } |
| 21285 | |
| 21286 | /* Close an automatic IT block. |
| 21287 | See comments in new_automatic_it_block (). */ |
| 21288 | |
| 21289 | static void |
| 21290 | close_automatic_it_block (void) |
| 21291 | { |
| 21292 | now_pred.mask = 0x10; |
| 21293 | now_pred.block_length = 0; |
| 21294 | } |
| 21295 | |
| 21296 | /* Update the mask of the current automatically-generated IT |
| 21297 | instruction. See comments in new_automatic_it_block (). */ |
| 21298 | |
| 21299 | static void |
| 21300 | now_pred_add_mask (int cond) |
| 21301 | { |
| 21302 | #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit))) |
| 21303 | #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \ |
| 21304 | | ((bitvalue) << (nbit))) |
| 21305 | const int resulting_bit = (cond & 1); |
| 21306 | |
| 21307 | now_pred.mask &= 0xf; |
| 21308 | now_pred.mask = SET_BIT_VALUE (now_pred.mask, |
| 21309 | resulting_bit, |
| 21310 | (5 - now_pred.block_length)); |
| 21311 | now_pred.mask = SET_BIT_VALUE (now_pred.mask, |
| 21312 | 1, |
| 21313 | ((5 - now_pred.block_length) - 1)); |
| 21314 | output_it_inst (now_pred.cc, now_pred.mask, now_pred.insn); |
| 21315 | |
| 21316 | #undef CLEAR_BIT |
| 21317 | #undef SET_BIT_VALUE |
| 21318 | } |
| 21319 | |
| 21320 | /* The IT blocks handling machinery is accessed through the these functions: |
| 21321 | it_fsm_pre_encode () from md_assemble () |
| 21322 | set_pred_insn_type () optional, from the tencode functions |
| 21323 | set_pred_insn_type_last () ditto |
| 21324 | in_pred_block () ditto |
| 21325 | it_fsm_post_encode () from md_assemble () |
| 21326 | force_automatic_it_block_close () from label handling functions |
| 21327 | |
| 21328 | Rationale: |
| 21329 | 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (), |
| 21330 | initializing the IT insn type with a generic initial value depending |
| 21331 | on the inst.condition. |
| 21332 | 2) During the tencode function, two things may happen: |
| 21333 | a) The tencode function overrides the IT insn type by |
| 21334 | calling either set_pred_insn_type (type) or |
| 21335 | set_pred_insn_type_last (). |
| 21336 | b) The tencode function queries the IT block state by |
| 21337 | calling in_pred_block () (i.e. to determine narrow/not narrow mode). |
| 21338 | |
| 21339 | Both set_pred_insn_type and in_pred_block run the internal FSM state |
| 21340 | handling function (handle_pred_state), because: a) setting the IT insn |
| 21341 | type may incur in an invalid state (exiting the function), |
| 21342 | and b) querying the state requires the FSM to be updated. |
| 21343 | Specifically we want to avoid creating an IT block for conditional |
| 21344 | branches, so it_fsm_pre_encode is actually a guess and we can't |
| 21345 | determine whether an IT block is required until the tencode () routine |
| 21346 | has decided what type of instruction this actually it. |
| 21347 | Because of this, if set_pred_insn_type and in_pred_block have to be |
| 21348 | used, set_pred_insn_type has to be called first. |
| 21349 | |
| 21350 | set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type), |
| 21351 | that determines the insn IT type depending on the inst.cond code. |
| 21352 | When a tencode () routine encodes an instruction that can be |
| 21353 | either outside an IT block, or, in the case of being inside, has to be |
| 21354 | the last one, set_pred_insn_type_last () will determine the proper |
| 21355 | IT instruction type based on the inst.cond code. Otherwise, |
| 21356 | set_pred_insn_type can be called for overriding that logic or |
| 21357 | for covering other cases. |
| 21358 | |
| 21359 | Calling handle_pred_state () may not transition the IT block state to |
| 21360 | OUTSIDE_PRED_BLOCK immediately, since the (current) state could be |
| 21361 | still queried. Instead, if the FSM determines that the state should |
| 21362 | be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed |
| 21363 | after the tencode () function: that's what it_fsm_post_encode () does. |
| 21364 | |
| 21365 | Since in_pred_block () calls the state handling function to get an |
| 21366 | updated state, an error may occur (due to invalid insns combination). |
| 21367 | In that case, inst.error is set. |
| 21368 | Therefore, inst.error has to be checked after the execution of |
| 21369 | the tencode () routine. |
| 21370 | |
| 21371 | 3) Back in md_assemble(), it_fsm_post_encode () is called to commit |
| 21372 | any pending state change (if any) that didn't take place in |
| 21373 | handle_pred_state () as explained above. */ |
| 21374 | |
| 21375 | static void |
| 21376 | it_fsm_pre_encode (void) |
| 21377 | { |
| 21378 | if (inst.cond != COND_ALWAYS) |
| 21379 | inst.pred_insn_type = INSIDE_IT_INSN; |
| 21380 | else |
| 21381 | inst.pred_insn_type = OUTSIDE_PRED_INSN; |
| 21382 | |
| 21383 | now_pred.state_handled = 0; |
| 21384 | } |
| 21385 | |
| 21386 | /* IT state FSM handling function. */ |
| 21387 | /* MVE instructions and non-MVE instructions are handled differently because of |
| 21388 | the introduction of VPT blocks. |
| 21389 | Specifications say that any non-MVE instruction inside a VPT block is |
| 21390 | UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE |
| 21391 | instructions are deemed to be UNPREDICTABLE if inside an IT block. For the |
| 21392 | few exceptions we have MVE_UNPREDICABLE_INSN. |
| 21393 | The error messages provided depending on the different combinations possible |
| 21394 | are described in the cases below: |
| 21395 | For 'most' MVE instructions: |
| 21396 | 1) In an IT block, with an IT code: syntax error |
| 21397 | 2) In an IT block, with a VPT code: error: must be in a VPT block |
| 21398 | 3) In an IT block, with no code: warning: UNPREDICTABLE |
| 21399 | 4) In a VPT block, with an IT code: syntax error |
| 21400 | 5) In a VPT block, with a VPT code: OK! |
| 21401 | 6) In a VPT block, with no code: error: missing code |
| 21402 | 7) Outside a pred block, with an IT code: error: syntax error |
| 21403 | 8) Outside a pred block, with a VPT code: error: should be in a VPT block |
| 21404 | 9) Outside a pred block, with no code: OK! |
| 21405 | For non-MVE instructions: |
| 21406 | 10) In an IT block, with an IT code: OK! |
| 21407 | 11) In an IT block, with a VPT code: syntax error |
| 21408 | 12) In an IT block, with no code: error: missing code |
| 21409 | 13) In a VPT block, with an IT code: error: should be in an IT block |
| 21410 | 14) In a VPT block, with a VPT code: syntax error |
| 21411 | 15) In a VPT block, with no code: UNPREDICTABLE |
| 21412 | 16) Outside a pred block, with an IT code: error: should be in an IT block |
| 21413 | 17) Outside a pred block, with a VPT code: syntax error |
| 21414 | 18) Outside a pred block, with no code: OK! |
| 21415 | */ |
| 21416 | |
| 21417 | |
| 21418 | static int |
| 21419 | handle_pred_state (void) |
| 21420 | { |
| 21421 | now_pred.state_handled = 1; |
| 21422 | now_pred.insn_cond = FALSE; |
| 21423 | |
| 21424 | switch (now_pred.state) |
| 21425 | { |
| 21426 | case OUTSIDE_PRED_BLOCK: |
| 21427 | switch (inst.pred_insn_type) |
| 21428 | { |
| 21429 | case MVE_UNPREDICABLE_INSN: |
| 21430 | case MVE_OUTSIDE_PRED_INSN: |
| 21431 | if (inst.cond < COND_ALWAYS) |
| 21432 | { |
| 21433 | /* Case 7: Outside a pred block, with an IT code: error: syntax |
| 21434 | error. */ |
| 21435 | inst.error = BAD_SYNTAX; |
| 21436 | return FAIL; |
| 21437 | } |
| 21438 | /* Case 9: Outside a pred block, with no code: OK! */ |
| 21439 | break; |
| 21440 | case OUTSIDE_PRED_INSN: |
| 21441 | if (inst.cond > COND_ALWAYS) |
| 21442 | { |
| 21443 | /* Case 17: Outside a pred block, with a VPT code: syntax error. |
| 21444 | */ |
| 21445 | inst.error = BAD_SYNTAX; |
| 21446 | return FAIL; |
| 21447 | } |
| 21448 | /* Case 18: Outside a pred block, with no code: OK! */ |
| 21449 | break; |
| 21450 | |
| 21451 | case INSIDE_VPT_INSN: |
| 21452 | /* Case 8: Outside a pred block, with a VPT code: error: should be in |
| 21453 | a VPT block. */ |
| 21454 | inst.error = BAD_OUT_VPT; |
| 21455 | return FAIL; |
| 21456 | |
| 21457 | case INSIDE_IT_INSN: |
| 21458 | case INSIDE_IT_LAST_INSN: |
| 21459 | if (inst.cond < COND_ALWAYS) |
| 21460 | { |
| 21461 | /* Case 16: Outside a pred block, with an IT code: error: should |
| 21462 | be in an IT block. */ |
| 21463 | if (thumb_mode == 0) |
| 21464 | { |
| 21465 | if (unified_syntax |
| 21466 | && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM)) |
| 21467 | as_tsktsk (_("Warning: conditional outside an IT block"\ |
| 21468 | " for Thumb.")); |
| 21469 | } |
| 21470 | else |
| 21471 | { |
| 21472 | if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB) |
| 21473 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)) |
| 21474 | { |
| 21475 | /* Automatically generate the IT instruction. */ |
| 21476 | new_automatic_it_block (inst.cond); |
| 21477 | if (inst.pred_insn_type == INSIDE_IT_LAST_INSN) |
| 21478 | close_automatic_it_block (); |
| 21479 | } |
| 21480 | else |
| 21481 | { |
| 21482 | inst.error = BAD_OUT_IT; |
| 21483 | return FAIL; |
| 21484 | } |
| 21485 | } |
| 21486 | break; |
| 21487 | } |
| 21488 | else if (inst.cond > COND_ALWAYS) |
| 21489 | { |
| 21490 | /* Case 17: Outside a pred block, with a VPT code: syntax error. |
| 21491 | */ |
| 21492 | inst.error = BAD_SYNTAX; |
| 21493 | return FAIL; |
| 21494 | } |
| 21495 | else |
| 21496 | gas_assert (0); |
| 21497 | case IF_INSIDE_IT_LAST_INSN: |
| 21498 | case NEUTRAL_IT_INSN: |
| 21499 | break; |
| 21500 | |
| 21501 | case VPT_INSN: |
| 21502 | if (inst.cond != COND_ALWAYS) |
| 21503 | first_error (BAD_SYNTAX); |
| 21504 | now_pred.state = MANUAL_PRED_BLOCK; |
| 21505 | now_pred.block_length = 0; |
| 21506 | now_pred.type = VECTOR_PRED; |
| 21507 | now_pred.cc = 0; |
| 21508 | break; |
| 21509 | case IT_INSN: |
| 21510 | now_pred.state = MANUAL_PRED_BLOCK; |
| 21511 | now_pred.block_length = 0; |
| 21512 | now_pred.type = SCALAR_PRED; |
| 21513 | break; |
| 21514 | } |
| 21515 | break; |
| 21516 | |
| 21517 | case AUTOMATIC_PRED_BLOCK: |
| 21518 | /* Three things may happen now: |
| 21519 | a) We should increment current it block size; |
| 21520 | b) We should close current it block (closing insn or 4 insns); |
| 21521 | c) We should close current it block and start a new one (due |
| 21522 | to incompatible conditions or |
| 21523 | 4 insns-length block reached). */ |
| 21524 | |
| 21525 | switch (inst.pred_insn_type) |
| 21526 | { |
| 21527 | case INSIDE_VPT_INSN: |
| 21528 | case VPT_INSN: |
| 21529 | case MVE_UNPREDICABLE_INSN: |
| 21530 | case MVE_OUTSIDE_PRED_INSN: |
| 21531 | gas_assert (0); |
| 21532 | case OUTSIDE_PRED_INSN: |
| 21533 | /* The closure of the block shall happen immediately, |
| 21534 | so any in_pred_block () call reports the block as closed. */ |
| 21535 | force_automatic_it_block_close (); |
| 21536 | break; |
| 21537 | |
| 21538 | case INSIDE_IT_INSN: |
| 21539 | case INSIDE_IT_LAST_INSN: |
| 21540 | case IF_INSIDE_IT_LAST_INSN: |
| 21541 | now_pred.block_length++; |
| 21542 | |
| 21543 | if (now_pred.block_length > 4 |
| 21544 | || !now_pred_compatible (inst.cond)) |
| 21545 | { |
| 21546 | force_automatic_it_block_close (); |
| 21547 | if (inst.pred_insn_type != IF_INSIDE_IT_LAST_INSN) |
| 21548 | new_automatic_it_block (inst.cond); |
| 21549 | } |
| 21550 | else |
| 21551 | { |
| 21552 | now_pred.insn_cond = TRUE; |
| 21553 | now_pred_add_mask (inst.cond); |
| 21554 | } |
| 21555 | |
| 21556 | if (now_pred.state == AUTOMATIC_PRED_BLOCK |
| 21557 | && (inst.pred_insn_type == INSIDE_IT_LAST_INSN |
| 21558 | || inst.pred_insn_type == IF_INSIDE_IT_LAST_INSN)) |
| 21559 | close_automatic_it_block (); |
| 21560 | break; |
| 21561 | |
| 21562 | case NEUTRAL_IT_INSN: |
| 21563 | now_pred.block_length++; |
| 21564 | now_pred.insn_cond = TRUE; |
| 21565 | |
| 21566 | if (now_pred.block_length > 4) |
| 21567 | force_automatic_it_block_close (); |
| 21568 | else |
| 21569 | now_pred_add_mask (now_pred.cc & 1); |
| 21570 | break; |
| 21571 | |
| 21572 | case IT_INSN: |
| 21573 | close_automatic_it_block (); |
| 21574 | now_pred.state = MANUAL_PRED_BLOCK; |
| 21575 | break; |
| 21576 | } |
| 21577 | break; |
| 21578 | |
| 21579 | case MANUAL_PRED_BLOCK: |
| 21580 | { |
| 21581 | int cond, is_last; |
| 21582 | if (now_pred.type == SCALAR_PRED) |
| 21583 | { |
| 21584 | /* Check conditional suffixes. */ |
| 21585 | cond = now_pred.cc ^ ((now_pred.mask >> 4) & 1) ^ 1; |
| 21586 | now_pred.mask <<= 1; |
| 21587 | now_pred.mask &= 0x1f; |
| 21588 | is_last = (now_pred.mask == 0x10); |
| 21589 | } |
| 21590 | else |
| 21591 | { |
| 21592 | now_pred.cc ^= (now_pred.mask >> 4); |
| 21593 | cond = now_pred.cc + 0xf; |
| 21594 | now_pred.mask <<= 1; |
| 21595 | now_pred.mask &= 0x1f; |
| 21596 | is_last = now_pred.mask == 0x10; |
| 21597 | } |
| 21598 | now_pred.insn_cond = TRUE; |
| 21599 | |
| 21600 | switch (inst.pred_insn_type) |
| 21601 | { |
| 21602 | case OUTSIDE_PRED_INSN: |
| 21603 | if (now_pred.type == SCALAR_PRED) |
| 21604 | { |
| 21605 | if (inst.cond == COND_ALWAYS) |
| 21606 | { |
| 21607 | /* Case 12: In an IT block, with no code: error: missing |
| 21608 | code. */ |
| 21609 | inst.error = BAD_NOT_IT; |
| 21610 | return FAIL; |
| 21611 | } |
| 21612 | else if (inst.cond > COND_ALWAYS) |
| 21613 | { |
| 21614 | /* Case 11: In an IT block, with a VPT code: syntax error. |
| 21615 | */ |
| 21616 | inst.error = BAD_SYNTAX; |
| 21617 | return FAIL; |
| 21618 | } |
| 21619 | else if (thumb_mode) |
| 21620 | { |
| 21621 | /* This is for some special cases where a non-MVE |
| 21622 | instruction is not allowed in an IT block, such as cbz, |
| 21623 | but are put into one with a condition code. |
| 21624 | You could argue this should be a syntax error, but we |
| 21625 | gave the 'not allowed in IT block' diagnostic in the |
| 21626 | past so we will keep doing so. */ |
| 21627 | inst.error = BAD_NOT_IT; |
| 21628 | return FAIL; |
| 21629 | } |
| 21630 | break; |
| 21631 | } |
| 21632 | else |
| 21633 | { |
| 21634 | /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */ |
| 21635 | as_tsktsk (MVE_NOT_VPT); |
| 21636 | return SUCCESS; |
| 21637 | } |
| 21638 | case MVE_OUTSIDE_PRED_INSN: |
| 21639 | if (now_pred.type == SCALAR_PRED) |
| 21640 | { |
| 21641 | if (inst.cond == COND_ALWAYS) |
| 21642 | { |
| 21643 | /* Case 3: In an IT block, with no code: warning: |
| 21644 | UNPREDICTABLE. */ |
| 21645 | as_tsktsk (MVE_NOT_IT); |
| 21646 | return SUCCESS; |
| 21647 | } |
| 21648 | else if (inst.cond < COND_ALWAYS) |
| 21649 | { |
| 21650 | /* Case 1: In an IT block, with an IT code: syntax error. |
| 21651 | */ |
| 21652 | inst.error = BAD_SYNTAX; |
| 21653 | return FAIL; |
| 21654 | } |
| 21655 | else |
| 21656 | gas_assert (0); |
| 21657 | } |
| 21658 | else |
| 21659 | { |
| 21660 | if (inst.cond < COND_ALWAYS) |
| 21661 | { |
| 21662 | /* Case 4: In a VPT block, with an IT code: syntax error. |
| 21663 | */ |
| 21664 | inst.error = BAD_SYNTAX; |
| 21665 | return FAIL; |
| 21666 | } |
| 21667 | else if (inst.cond == COND_ALWAYS) |
| 21668 | { |
| 21669 | /* Case 6: In a VPT block, with no code: error: missing |
| 21670 | code. */ |
| 21671 | inst.error = BAD_NOT_VPT; |
| 21672 | return FAIL; |
| 21673 | } |
| 21674 | else |
| 21675 | { |
| 21676 | gas_assert (0); |
| 21677 | } |
| 21678 | } |
| 21679 | case MVE_UNPREDICABLE_INSN: |
| 21680 | as_tsktsk (now_pred.type == SCALAR_PRED ? MVE_NOT_IT : MVE_NOT_VPT); |
| 21681 | return SUCCESS; |
| 21682 | case INSIDE_IT_INSN: |
| 21683 | if (inst.cond > COND_ALWAYS) |
| 21684 | { |
| 21685 | /* Case 11: In an IT block, with a VPT code: syntax error. */ |
| 21686 | /* Case 14: In a VPT block, with a VPT code: syntax error. */ |
| 21687 | inst.error = BAD_SYNTAX; |
| 21688 | return FAIL; |
| 21689 | } |
| 21690 | else if (now_pred.type == SCALAR_PRED) |
| 21691 | { |
| 21692 | /* Case 10: In an IT block, with an IT code: OK! */ |
| 21693 | if (cond != inst.cond) |
| 21694 | { |
| 21695 | inst.error = now_pred.type == SCALAR_PRED ? BAD_IT_COND : |
| 21696 | BAD_VPT_COND; |
| 21697 | return FAIL; |
| 21698 | } |
| 21699 | } |
| 21700 | else |
| 21701 | { |
| 21702 | /* Case 13: In a VPT block, with an IT code: error: should be |
| 21703 | in an IT block. */ |
| 21704 | inst.error = BAD_OUT_IT; |
| 21705 | return FAIL; |
| 21706 | } |
| 21707 | break; |
| 21708 | |
| 21709 | case INSIDE_VPT_INSN: |
| 21710 | if (now_pred.type == SCALAR_PRED) |
| 21711 | { |
| 21712 | /* Case 2: In an IT block, with a VPT code: error: must be in a |
| 21713 | VPT block. */ |
| 21714 | inst.error = BAD_OUT_VPT; |
| 21715 | return FAIL; |
| 21716 | } |
| 21717 | /* Case 5: In a VPT block, with a VPT code: OK! */ |
| 21718 | else if (cond != inst.cond) |
| 21719 | { |
| 21720 | inst.error = BAD_VPT_COND; |
| 21721 | return FAIL; |
| 21722 | } |
| 21723 | break; |
| 21724 | case INSIDE_IT_LAST_INSN: |
| 21725 | case IF_INSIDE_IT_LAST_INSN: |
| 21726 | if (now_pred.type == VECTOR_PRED || inst.cond > COND_ALWAYS) |
| 21727 | { |
| 21728 | /* Case 4: In a VPT block, with an IT code: syntax error. */ |
| 21729 | /* Case 11: In an IT block, with a VPT code: syntax error. */ |
| 21730 | inst.error = BAD_SYNTAX; |
| 21731 | return FAIL; |
| 21732 | } |
| 21733 | else if (cond != inst.cond) |
| 21734 | { |
| 21735 | inst.error = BAD_IT_COND; |
| 21736 | return FAIL; |
| 21737 | } |
| 21738 | if (!is_last) |
| 21739 | { |
| 21740 | inst.error = BAD_BRANCH; |
| 21741 | return FAIL; |
| 21742 | } |
| 21743 | break; |
| 21744 | |
| 21745 | case NEUTRAL_IT_INSN: |
| 21746 | /* The BKPT instruction is unconditional even in a IT or VPT |
| 21747 | block. */ |
| 21748 | break; |
| 21749 | |
| 21750 | case IT_INSN: |
| 21751 | if (now_pred.type == SCALAR_PRED) |
| 21752 | { |
| 21753 | inst.error = BAD_IT_IT; |
| 21754 | return FAIL; |
| 21755 | } |
| 21756 | /* fall through. */ |
| 21757 | case VPT_INSN: |
| 21758 | if (inst.cond == COND_ALWAYS) |
| 21759 | { |
| 21760 | /* Executing a VPT/VPST instruction inside an IT block or a |
| 21761 | VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE. |
| 21762 | */ |
| 21763 | if (now_pred.type == SCALAR_PRED) |
| 21764 | as_tsktsk (MVE_NOT_IT); |
| 21765 | else |
| 21766 | as_tsktsk (MVE_NOT_VPT); |
| 21767 | return SUCCESS; |
| 21768 | } |
| 21769 | else |
| 21770 | { |
| 21771 | /* VPT/VPST do not accept condition codes. */ |
| 21772 | inst.error = BAD_SYNTAX; |
| 21773 | return FAIL; |
| 21774 | } |
| 21775 | } |
| 21776 | } |
| 21777 | break; |
| 21778 | } |
| 21779 | |
| 21780 | return SUCCESS; |
| 21781 | } |
| 21782 | |
| 21783 | struct depr_insn_mask |
| 21784 | { |
| 21785 | unsigned long pattern; |
| 21786 | unsigned long mask; |
| 21787 | const char* description; |
| 21788 | }; |
| 21789 | |
| 21790 | /* List of 16-bit instruction patterns deprecated in an IT block in |
| 21791 | ARMv8. */ |
| 21792 | static const struct depr_insn_mask depr_it_insns[] = { |
| 21793 | { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") }, |
| 21794 | { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") }, |
| 21795 | { 0xa000, 0xb800, N_("ADR") }, |
| 21796 | { 0x4800, 0xf800, N_("Literal loads") }, |
| 21797 | { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") }, |
| 21798 | { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") }, |
| 21799 | /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue' |
| 21800 | field in asm_opcode. 'tvalue' is used at the stage this check happen. */ |
| 21801 | { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") }, |
| 21802 | { 0, 0, NULL } |
| 21803 | }; |
| 21804 | |
| 21805 | static void |
| 21806 | it_fsm_post_encode (void) |
| 21807 | { |
| 21808 | int is_last; |
| 21809 | |
| 21810 | if (!now_pred.state_handled) |
| 21811 | handle_pred_state (); |
| 21812 | |
| 21813 | if (now_pred.insn_cond |
| 21814 | && !now_pred.warn_deprecated |
| 21815 | && warn_on_deprecated |
| 21816 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8) |
| 21817 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m)) |
| 21818 | { |
| 21819 | if (inst.instruction >= 0x10000) |
| 21820 | { |
| 21821 | as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are " |
| 21822 | "performance deprecated in ARMv8-A and ARMv8-R")); |
| 21823 | now_pred.warn_deprecated = TRUE; |
| 21824 | } |
| 21825 | else |
| 21826 | { |
| 21827 | const struct depr_insn_mask *p = depr_it_insns; |
| 21828 | |
| 21829 | while (p->mask != 0) |
| 21830 | { |
| 21831 | if ((inst.instruction & p->mask) == p->pattern) |
| 21832 | { |
| 21833 | as_tsktsk (_("IT blocks containing 16-bit Thumb " |
| 21834 | "instructions of the following class are " |
| 21835 | "performance deprecated in ARMv8-A and " |
| 21836 | "ARMv8-R: %s"), p->description); |
| 21837 | now_pred.warn_deprecated = TRUE; |
| 21838 | break; |
| 21839 | } |
| 21840 | |
| 21841 | ++p; |
| 21842 | } |
| 21843 | } |
| 21844 | |
| 21845 | if (now_pred.block_length > 1) |
| 21846 | { |
| 21847 | as_tsktsk (_("IT blocks containing more than one conditional " |
| 21848 | "instruction are performance deprecated in ARMv8-A and " |
| 21849 | "ARMv8-R")); |
| 21850 | now_pred.warn_deprecated = TRUE; |
| 21851 | } |
| 21852 | } |
| 21853 | |
| 21854 | is_last = (now_pred.mask == 0x10); |
| 21855 | if (is_last) |
| 21856 | { |
| 21857 | now_pred.state = OUTSIDE_PRED_BLOCK; |
| 21858 | now_pred.mask = 0; |
| 21859 | } |
| 21860 | } |
| 21861 | |
| 21862 | static void |
| 21863 | force_automatic_it_block_close (void) |
| 21864 | { |
| 21865 | if (now_pred.state == AUTOMATIC_PRED_BLOCK) |
| 21866 | { |
| 21867 | close_automatic_it_block (); |
| 21868 | now_pred.state = OUTSIDE_PRED_BLOCK; |
| 21869 | now_pred.mask = 0; |
| 21870 | } |
| 21871 | } |
| 21872 | |
| 21873 | static int |
| 21874 | in_pred_block (void) |
| 21875 | { |
| 21876 | if (!now_pred.state_handled) |
| 21877 | handle_pred_state (); |
| 21878 | |
| 21879 | return now_pred.state != OUTSIDE_PRED_BLOCK; |
| 21880 | } |
| 21881 | |
| 21882 | /* Whether OPCODE only has T32 encoding. Since this function is only used by |
| 21883 | t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed |
| 21884 | here, hence the "known" in the function name. */ |
| 21885 | |
| 21886 | static bfd_boolean |
| 21887 | known_t32_only_insn (const struct asm_opcode *opcode) |
| 21888 | { |
| 21889 | /* Original Thumb-1 wide instruction. */ |
| 21890 | if (opcode->tencode == do_t_blx |
| 21891 | || opcode->tencode == do_t_branch23 |
| 21892 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr) |
| 21893 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)) |
| 21894 | return TRUE; |
| 21895 | |
| 21896 | /* Wide-only instruction added to ARMv8-M Baseline. */ |
| 21897 | if (ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v8m_m_only) |
| 21898 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_atomics) |
| 21899 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v6t2_v8m) |
| 21900 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_div)) |
| 21901 | return TRUE; |
| 21902 | |
| 21903 | return FALSE; |
| 21904 | } |
| 21905 | |
| 21906 | /* Whether wide instruction variant can be used if available for a valid OPCODE |
| 21907 | in ARCH. */ |
| 21908 | |
| 21909 | static bfd_boolean |
| 21910 | t32_insn_ok (arm_feature_set arch, const struct asm_opcode *opcode) |
| 21911 | { |
| 21912 | if (known_t32_only_insn (opcode)) |
| 21913 | return TRUE; |
| 21914 | |
| 21915 | /* Instruction with narrow and wide encoding added to ARMv8-M. Availability |
| 21916 | of variant T3 of B.W is checked in do_t_branch. */ |
| 21917 | if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m) |
| 21918 | && opcode->tencode == do_t_branch) |
| 21919 | return TRUE; |
| 21920 | |
| 21921 | /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */ |
| 21922 | if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m) |
| 21923 | && opcode->tencode == do_t_mov_cmp |
| 21924 | /* Make sure CMP instruction is not affected. */ |
| 21925 | && opcode->aencode == do_mov) |
| 21926 | return TRUE; |
| 21927 | |
| 21928 | /* Wide instruction variants of all instructions with narrow *and* wide |
| 21929 | variants become available with ARMv6t2. Other opcodes are either |
| 21930 | narrow-only or wide-only and are thus available if OPCODE is valid. */ |
| 21931 | if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v6t2)) |
| 21932 | return TRUE; |
| 21933 | |
| 21934 | /* OPCODE with narrow only instruction variant or wide variant not |
| 21935 | available. */ |
| 21936 | return FALSE; |
| 21937 | } |
| 21938 | |
| 21939 | void |
| 21940 | md_assemble (char *str) |
| 21941 | { |
| 21942 | char *p = str; |
| 21943 | const struct asm_opcode * opcode; |
| 21944 | |
| 21945 | /* Align the previous label if needed. */ |
| 21946 | if (last_label_seen != NULL) |
| 21947 | { |
| 21948 | symbol_set_frag (last_label_seen, frag_now); |
| 21949 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); |
| 21950 | S_SET_SEGMENT (last_label_seen, now_seg); |
| 21951 | } |
| 21952 | |
| 21953 | memset (&inst, '\0', sizeof (inst)); |
| 21954 | int r; |
| 21955 | for (r = 0; r < ARM_IT_MAX_RELOCS; r++) |
| 21956 | inst.relocs[r].type = BFD_RELOC_UNUSED; |
| 21957 | |
| 21958 | opcode = opcode_lookup (&p); |
| 21959 | if (!opcode) |
| 21960 | { |
| 21961 | /* It wasn't an instruction, but it might be a register alias of |
| 21962 | the form alias .req reg, or a Neon .dn/.qn directive. */ |
| 21963 | if (! create_register_alias (str, p) |
| 21964 | && ! create_neon_reg_alias (str, p)) |
| 21965 | as_bad (_("bad instruction `%s'"), str); |
| 21966 | |
| 21967 | return; |
| 21968 | } |
| 21969 | |
| 21970 | if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated) |
| 21971 | as_tsktsk (_("s suffix on comparison instruction is deprecated")); |
| 21972 | |
| 21973 | /* The value which unconditional instructions should have in place of the |
| 21974 | condition field. */ |
| 21975 | inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; |
| 21976 | |
| 21977 | if (thumb_mode) |
| 21978 | { |
| 21979 | arm_feature_set variant; |
| 21980 | |
| 21981 | variant = cpu_variant; |
| 21982 | /* Only allow coprocessor instructions on Thumb-2 capable devices. */ |
| 21983 | if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) |
| 21984 | ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); |
| 21985 | /* Check that this instruction is supported for this CPU. */ |
| 21986 | if (!opcode->tvariant |
| 21987 | || (thumb_mode == 1 |
| 21988 | && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) |
| 21989 | { |
| 21990 | if (opcode->tencode == do_t_swi) |
| 21991 | as_bad (_("SVC is not permitted on this architecture")); |
| 21992 | else |
| 21993 | as_bad (_("selected processor does not support `%s' in Thumb mode"), str); |
| 21994 | return; |
| 21995 | } |
| 21996 | if (inst.cond != COND_ALWAYS && !unified_syntax |
| 21997 | && opcode->tencode != do_t_branch) |
| 21998 | { |
| 21999 | as_bad (_("Thumb does not support conditional execution")); |
| 22000 | return; |
| 22001 | } |
| 22002 | |
| 22003 | /* Two things are addressed here: |
| 22004 | 1) Implicit require narrow instructions on Thumb-1. |
| 22005 | This avoids relaxation accidentally introducing Thumb-2 |
| 22006 | instructions. |
| 22007 | 2) Reject wide instructions in non Thumb-2 cores. |
| 22008 | |
| 22009 | Only instructions with narrow and wide variants need to be handled |
| 22010 | but selecting all non wide-only instructions is easier. */ |
| 22011 | if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2) |
| 22012 | && !t32_insn_ok (variant, opcode)) |
| 22013 | { |
| 22014 | if (inst.size_req == 0) |
| 22015 | inst.size_req = 2; |
| 22016 | else if (inst.size_req == 4) |
| 22017 | { |
| 22018 | if (ARM_CPU_HAS_FEATURE (variant, arm_ext_v8m)) |
| 22019 | as_bad (_("selected processor does not support 32bit wide " |
| 22020 | "variant of instruction `%s'"), str); |
| 22021 | else |
| 22022 | as_bad (_("selected processor does not support `%s' in " |
| 22023 | "Thumb-2 mode"), str); |
| 22024 | return; |
| 22025 | } |
| 22026 | } |
| 22027 | |
| 22028 | inst.instruction = opcode->tvalue; |
| 22029 | |
| 22030 | if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE)) |
| 22031 | { |
| 22032 | /* Prepare the pred_insn_type for those encodings that don't set |
| 22033 | it. */ |
| 22034 | it_fsm_pre_encode (); |
| 22035 | |
| 22036 | opcode->tencode (); |
| 22037 | |
| 22038 | it_fsm_post_encode (); |
| 22039 | } |
| 22040 | |
| 22041 | if (!(inst.error || inst.relax)) |
| 22042 | { |
| 22043 | gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); |
| 22044 | inst.size = (inst.instruction > 0xffff ? 4 : 2); |
| 22045 | if (inst.size_req && inst.size_req != inst.size) |
| 22046 | { |
| 22047 | as_bad (_("cannot honor width suffix -- `%s'"), str); |
| 22048 | return; |
| 22049 | } |
| 22050 | } |
| 22051 | |
| 22052 | /* Something has gone badly wrong if we try to relax a fixed size |
| 22053 | instruction. */ |
| 22054 | gas_assert (inst.size_req == 0 || !inst.relax); |
| 22055 | |
| 22056 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
| 22057 | *opcode->tvariant); |
| 22058 | /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly |
| 22059 | set those bits when Thumb-2 32-bit instructions are seen. The impact |
| 22060 | of relaxable instructions will be considered later after we finish all |
| 22061 | relaxation. */ |
| 22062 | if (ARM_FEATURE_CORE_EQUAL (cpu_variant, arm_arch_any)) |
| 22063 | variant = arm_arch_none; |
| 22064 | else |
| 22065 | variant = cpu_variant; |
| 22066 | if (inst.size == 4 && !t32_insn_ok (variant, opcode)) |
| 22067 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
| 22068 | arm_ext_v6t2); |
| 22069 | |
| 22070 | check_neon_suffixes; |
| 22071 | |
| 22072 | if (!inst.error) |
| 22073 | { |
| 22074 | mapping_state (MAP_THUMB); |
| 22075 | } |
| 22076 | } |
| 22077 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
| 22078 | { |
| 22079 | bfd_boolean is_bx; |
| 22080 | |
| 22081 | /* bx is allowed on v5 cores, and sometimes on v4 cores. */ |
| 22082 | is_bx = (opcode->aencode == do_bx); |
| 22083 | |
| 22084 | /* Check that this instruction is supported for this CPU. */ |
| 22085 | if (!(is_bx && fix_v4bx) |
| 22086 | && !(opcode->avariant && |
| 22087 | ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))) |
| 22088 | { |
| 22089 | as_bad (_("selected processor does not support `%s' in ARM mode"), str); |
| 22090 | return; |
| 22091 | } |
| 22092 | if (inst.size_req) |
| 22093 | { |
| 22094 | as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); |
| 22095 | return; |
| 22096 | } |
| 22097 | |
| 22098 | inst.instruction = opcode->avalue; |
| 22099 | if (opcode->tag == OT_unconditionalF) |
| 22100 | inst.instruction |= 0xFU << 28; |
| 22101 | else |
| 22102 | inst.instruction |= inst.cond << 28; |
| 22103 | inst.size = INSN_SIZE; |
| 22104 | if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE)) |
| 22105 | { |
| 22106 | it_fsm_pre_encode (); |
| 22107 | opcode->aencode (); |
| 22108 | it_fsm_post_encode (); |
| 22109 | } |
| 22110 | /* Arm mode bx is marked as both v4T and v5 because it's still required |
| 22111 | on a hypothetical non-thumb v5 core. */ |
| 22112 | if (is_bx) |
| 22113 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); |
| 22114 | else |
| 22115 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, |
| 22116 | *opcode->avariant); |
| 22117 | |
| 22118 | check_neon_suffixes; |
| 22119 | |
| 22120 | if (!inst.error) |
| 22121 | { |
| 22122 | mapping_state (MAP_ARM); |
| 22123 | } |
| 22124 | } |
| 22125 | else |
| 22126 | { |
| 22127 | as_bad (_("attempt to use an ARM instruction on a Thumb-only processor " |
| 22128 | "-- `%s'"), str); |
| 22129 | return; |
| 22130 | } |
| 22131 | output_inst (str); |
| 22132 | } |
| 22133 | |
| 22134 | static void |
| 22135 | check_pred_blocks_finished (void) |
| 22136 | { |
| 22137 | #ifdef OBJ_ELF |
| 22138 | asection *sect; |
| 22139 | |
| 22140 | for (sect = stdoutput->sections; sect != NULL; sect = sect->next) |
| 22141 | if (seg_info (sect)->tc_segment_info_data.current_pred.state |
| 22142 | == MANUAL_PRED_BLOCK) |
| 22143 | { |
| 22144 | if (now_pred.type == SCALAR_PRED) |
| 22145 | as_warn (_("section '%s' finished with an open IT block."), |
| 22146 | sect->name); |
| 22147 | else |
| 22148 | as_warn (_("section '%s' finished with an open VPT/VPST block."), |
| 22149 | sect->name); |
| 22150 | } |
| 22151 | #else |
| 22152 | if (now_pred.state == MANUAL_PRED_BLOCK) |
| 22153 | { |
| 22154 | if (now_pred.type == SCALAR_PRED) |
| 22155 | as_warn (_("file finished with an open IT block.")); |
| 22156 | else |
| 22157 | as_warn (_("file finished with an open VPT/VPST block.")); |
| 22158 | } |
| 22159 | #endif |
| 22160 | } |
| 22161 | |
| 22162 | /* Various frobbings of labels and their addresses. */ |
| 22163 | |
| 22164 | void |
| 22165 | arm_start_line_hook (void) |
| 22166 | { |
| 22167 | last_label_seen = NULL; |
| 22168 | } |
| 22169 | |
| 22170 | void |
| 22171 | arm_frob_label (symbolS * sym) |
| 22172 | { |
| 22173 | last_label_seen = sym; |
| 22174 | |
| 22175 | ARM_SET_THUMB (sym, thumb_mode); |
| 22176 | |
| 22177 | #if defined OBJ_COFF || defined OBJ_ELF |
| 22178 | ARM_SET_INTERWORK (sym, support_interwork); |
| 22179 | #endif |
| 22180 | |
| 22181 | force_automatic_it_block_close (); |
| 22182 | |
| 22183 | /* Note - do not allow local symbols (.Lxxx) to be labelled |
| 22184 | as Thumb functions. This is because these labels, whilst |
| 22185 | they exist inside Thumb code, are not the entry points for |
| 22186 | possible ARM->Thumb calls. Also, these labels can be used |
| 22187 | as part of a computed goto or switch statement. eg gcc |
| 22188 | can generate code that looks like this: |
| 22189 | |
| 22190 | ldr r2, [pc, .Laaa] |
| 22191 | lsl r3, r3, #2 |
| 22192 | ldr r2, [r3, r2] |
| 22193 | mov pc, r2 |
| 22194 | |
| 22195 | .Lbbb: .word .Lxxx |
| 22196 | .Lccc: .word .Lyyy |
| 22197 | ..etc... |
| 22198 | .Laaa: .word Lbbb |
| 22199 | |
| 22200 | The first instruction loads the address of the jump table. |
| 22201 | The second instruction converts a table index into a byte offset. |
| 22202 | The third instruction gets the jump address out of the table. |
| 22203 | The fourth instruction performs the jump. |
| 22204 | |
| 22205 | If the address stored at .Laaa is that of a symbol which has the |
| 22206 | Thumb_Func bit set, then the linker will arrange for this address |
| 22207 | to have the bottom bit set, which in turn would mean that the |
| 22208 | address computation performed by the third instruction would end |
| 22209 | up with the bottom bit set. Since the ARM is capable of unaligned |
| 22210 | word loads, the instruction would then load the incorrect address |
| 22211 | out of the jump table, and chaos would ensue. */ |
| 22212 | if (label_is_thumb_function_name |
| 22213 | && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') |
| 22214 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) |
| 22215 | { |
| 22216 | /* When the address of a Thumb function is taken the bottom |
| 22217 | bit of that address should be set. This will allow |
| 22218 | interworking between Arm and Thumb functions to work |
| 22219 | correctly. */ |
| 22220 | |
| 22221 | THUMB_SET_FUNC (sym, 1); |
| 22222 | |
| 22223 | label_is_thumb_function_name = FALSE; |
| 22224 | } |
| 22225 | |
| 22226 | dwarf2_emit_label (sym); |
| 22227 | } |
| 22228 | |
| 22229 | bfd_boolean |
| 22230 | arm_data_in_code (void) |
| 22231 | { |
| 22232 | if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) |
| 22233 | { |
| 22234 | *input_line_pointer = '/'; |
| 22235 | input_line_pointer += 5; |
| 22236 | *input_line_pointer = 0; |
| 22237 | return TRUE; |
| 22238 | } |
| 22239 | |
| 22240 | return FALSE; |
| 22241 | } |
| 22242 | |
| 22243 | char * |
| 22244 | arm_canonicalize_symbol_name (char * name) |
| 22245 | { |
| 22246 | int len; |
| 22247 | |
| 22248 | if (thumb_mode && (len = strlen (name)) > 5 |
| 22249 | && streq (name + len - 5, "/data")) |
| 22250 | *(name + len - 5) = 0; |
| 22251 | |
| 22252 | return name; |
| 22253 | } |
| 22254 | \f |
| 22255 | /* Table of all register names defined by default. The user can |
| 22256 | define additional names with .req. Note that all register names |
| 22257 | should appear in both upper and lowercase variants. Some registers |
| 22258 | also have mixed-case names. */ |
| 22259 | |
| 22260 | #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } |
| 22261 | #define REGNUM(p,n,t) REGDEF(p##n, n, t) |
| 22262 | #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) |
| 22263 | #define REGSET(p,t) \ |
| 22264 | REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ |
| 22265 | REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ |
| 22266 | REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ |
| 22267 | REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) |
| 22268 | #define REGSETH(p,t) \ |
| 22269 | REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ |
| 22270 | REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ |
| 22271 | REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ |
| 22272 | REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) |
| 22273 | #define REGSET2(p,t) \ |
| 22274 | REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ |
| 22275 | REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ |
| 22276 | REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ |
| 22277 | REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) |
| 22278 | #define SPLRBANK(base,bank,t) \ |
| 22279 | REGDEF(lr_##bank, 768|((base+0)<<16), t), \ |
| 22280 | REGDEF(sp_##bank, 768|((base+1)<<16), t), \ |
| 22281 | REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \ |
| 22282 | REGDEF(LR_##bank, 768|((base+0)<<16), t), \ |
| 22283 | REGDEF(SP_##bank, 768|((base+1)<<16), t), \ |
| 22284 | REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t) |
| 22285 | |
| 22286 | static const struct reg_entry reg_names[] = |
| 22287 | { |
| 22288 | /* ARM integer registers. */ |
| 22289 | REGSET(r, RN), REGSET(R, RN), |
| 22290 | |
| 22291 | /* ATPCS synonyms. */ |
| 22292 | REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), |
| 22293 | REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), |
| 22294 | REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), |
| 22295 | |
| 22296 | REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), |
| 22297 | REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), |
| 22298 | REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), |
| 22299 | |
| 22300 | /* Well-known aliases. */ |
| 22301 | REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), |
| 22302 | REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), |
| 22303 | |
| 22304 | REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), |
| 22305 | REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), |
| 22306 | |
| 22307 | /* Defining the new Zero register from ARMv8.1-M. */ |
| 22308 | REGDEF(zr,15,ZR), |
| 22309 | REGDEF(ZR,15,ZR), |
| 22310 | |
| 22311 | /* Coprocessor numbers. */ |
| 22312 | REGSET(p, CP), REGSET(P, CP), |
| 22313 | |
| 22314 | /* Coprocessor register numbers. The "cr" variants are for backward |
| 22315 | compatibility. */ |
| 22316 | REGSET(c, CN), REGSET(C, CN), |
| 22317 | REGSET(cr, CN), REGSET(CR, CN), |
| 22318 | |
| 22319 | /* ARM banked registers. */ |
| 22320 | REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB), |
| 22321 | REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB), |
| 22322 | REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB), |
| 22323 | REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB), |
| 22324 | REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB), |
| 22325 | REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB), |
| 22326 | REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB), |
| 22327 | |
| 22328 | REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB), |
| 22329 | REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB), |
| 22330 | REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB), |
| 22331 | REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB), |
| 22332 | REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB), |
| 22333 | REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB), |
| 22334 | REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB), |
| 22335 | REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB), |
| 22336 | |
| 22337 | SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB), |
| 22338 | SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB), |
| 22339 | SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB), |
| 22340 | SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB), |
| 22341 | SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB), |
| 22342 | REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB), |
| 22343 | REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB), |
| 22344 | REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB), |
| 22345 | REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB), |
| 22346 | |
| 22347 | /* FPA registers. */ |
| 22348 | REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), |
| 22349 | REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), |
| 22350 | |
| 22351 | REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), |
| 22352 | REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), |
| 22353 | |
| 22354 | /* VFP SP registers. */ |
| 22355 | REGSET(s,VFS), REGSET(S,VFS), |
| 22356 | REGSETH(s,VFS), REGSETH(S,VFS), |
| 22357 | |
| 22358 | /* VFP DP Registers. */ |
| 22359 | REGSET(d,VFD), REGSET(D,VFD), |
| 22360 | /* Extra Neon DP registers. */ |
| 22361 | REGSETH(d,VFD), REGSETH(D,VFD), |
| 22362 | |
| 22363 | /* Neon QP registers. */ |
| 22364 | REGSET2(q,NQ), REGSET2(Q,NQ), |
| 22365 | |
| 22366 | /* VFP control registers. */ |
| 22367 | REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), |
| 22368 | REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), |
| 22369 | REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC), |
| 22370 | REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), |
| 22371 | REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), |
| 22372 | REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), |
| 22373 | REGDEF(mvfr2,5,VFC), REGDEF(MVFR2,5,VFC), |
| 22374 | |
| 22375 | /* Maverick DSP coprocessor registers. */ |
| 22376 | REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), |
| 22377 | REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), |
| 22378 | |
| 22379 | REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), |
| 22380 | REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), |
| 22381 | REGDEF(dspsc,0,DSPSC), |
| 22382 | |
| 22383 | REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), |
| 22384 | REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), |
| 22385 | REGDEF(DSPSC,0,DSPSC), |
| 22386 | |
| 22387 | /* iWMMXt data registers - p0, c0-15. */ |
| 22388 | REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), |
| 22389 | |
| 22390 | /* iWMMXt control registers - p1, c0-3. */ |
| 22391 | REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), |
| 22392 | REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), |
| 22393 | REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), |
| 22394 | REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), |
| 22395 | |
| 22396 | /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ |
| 22397 | REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), |
| 22398 | REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), |
| 22399 | REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), |
| 22400 | REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), |
| 22401 | |
| 22402 | /* XScale accumulator registers. */ |
| 22403 | REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), |
| 22404 | }; |
| 22405 | #undef REGDEF |
| 22406 | #undef REGNUM |
| 22407 | #undef REGSET |
| 22408 | |
| 22409 | /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled |
| 22410 | within psr_required_here. */ |
| 22411 | static const struct asm_psr psrs[] = |
| 22412 | { |
| 22413 | /* Backward compatibility notation. Note that "all" is no longer |
| 22414 | truly all possible PSR bits. */ |
| 22415 | {"all", PSR_c | PSR_f}, |
| 22416 | {"flg", PSR_f}, |
| 22417 | {"ctl", PSR_c}, |
| 22418 | |
| 22419 | /* Individual flags. */ |
| 22420 | {"f", PSR_f}, |
| 22421 | {"c", PSR_c}, |
| 22422 | {"x", PSR_x}, |
| 22423 | {"s", PSR_s}, |
| 22424 | |
| 22425 | /* Combinations of flags. */ |
| 22426 | {"fs", PSR_f | PSR_s}, |
| 22427 | {"fx", PSR_f | PSR_x}, |
| 22428 | {"fc", PSR_f | PSR_c}, |
| 22429 | {"sf", PSR_s | PSR_f}, |
| 22430 | {"sx", PSR_s | PSR_x}, |
| 22431 | {"sc", PSR_s | PSR_c}, |
| 22432 | {"xf", PSR_x | PSR_f}, |
| 22433 | {"xs", PSR_x | PSR_s}, |
| 22434 | {"xc", PSR_x | PSR_c}, |
| 22435 | {"cf", PSR_c | PSR_f}, |
| 22436 | {"cs", PSR_c | PSR_s}, |
| 22437 | {"cx", PSR_c | PSR_x}, |
| 22438 | {"fsx", PSR_f | PSR_s | PSR_x}, |
| 22439 | {"fsc", PSR_f | PSR_s | PSR_c}, |
| 22440 | {"fxs", PSR_f | PSR_x | PSR_s}, |
| 22441 | {"fxc", PSR_f | PSR_x | PSR_c}, |
| 22442 | {"fcs", PSR_f | PSR_c | PSR_s}, |
| 22443 | {"fcx", PSR_f | PSR_c | PSR_x}, |
| 22444 | {"sfx", PSR_s | PSR_f | PSR_x}, |
| 22445 | {"sfc", PSR_s | PSR_f | PSR_c}, |
| 22446 | {"sxf", PSR_s | PSR_x | PSR_f}, |
| 22447 | {"sxc", PSR_s | PSR_x | PSR_c}, |
| 22448 | {"scf", PSR_s | PSR_c | PSR_f}, |
| 22449 | {"scx", PSR_s | PSR_c | PSR_x}, |
| 22450 | {"xfs", PSR_x | PSR_f | PSR_s}, |
| 22451 | {"xfc", PSR_x | PSR_f | PSR_c}, |
| 22452 | {"xsf", PSR_x | PSR_s | PSR_f}, |
| 22453 | {"xsc", PSR_x | PSR_s | PSR_c}, |
| 22454 | {"xcf", PSR_x | PSR_c | PSR_f}, |
| 22455 | {"xcs", PSR_x | PSR_c | PSR_s}, |
| 22456 | {"cfs", PSR_c | PSR_f | PSR_s}, |
| 22457 | {"cfx", PSR_c | PSR_f | PSR_x}, |
| 22458 | {"csf", PSR_c | PSR_s | PSR_f}, |
| 22459 | {"csx", PSR_c | PSR_s | PSR_x}, |
| 22460 | {"cxf", PSR_c | PSR_x | PSR_f}, |
| 22461 | {"cxs", PSR_c | PSR_x | PSR_s}, |
| 22462 | {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, |
| 22463 | {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, |
| 22464 | {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, |
| 22465 | {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, |
| 22466 | {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, |
| 22467 | {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, |
| 22468 | {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, |
| 22469 | {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, |
| 22470 | {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, |
| 22471 | {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, |
| 22472 | {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, |
| 22473 | {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, |
| 22474 | {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, |
| 22475 | {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, |
| 22476 | {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, |
| 22477 | {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, |
| 22478 | {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, |
| 22479 | {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, |
| 22480 | {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, |
| 22481 | {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, |
| 22482 | {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, |
| 22483 | {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, |
| 22484 | {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, |
| 22485 | {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, |
| 22486 | }; |
| 22487 | |
| 22488 | /* Table of V7M psr names. */ |
| 22489 | static const struct asm_psr v7m_psrs[] = |
| 22490 | { |
| 22491 | {"apsr", 0x0 }, {"APSR", 0x0 }, |
| 22492 | {"iapsr", 0x1 }, {"IAPSR", 0x1 }, |
| 22493 | {"eapsr", 0x2 }, {"EAPSR", 0x2 }, |
| 22494 | {"psr", 0x3 }, {"PSR", 0x3 }, |
| 22495 | {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 }, |
| 22496 | {"ipsr", 0x5 }, {"IPSR", 0x5 }, |
| 22497 | {"epsr", 0x6 }, {"EPSR", 0x6 }, |
| 22498 | {"iepsr", 0x7 }, {"IEPSR", 0x7 }, |
| 22499 | {"msp", 0x8 }, {"MSP", 0x8 }, |
| 22500 | {"psp", 0x9 }, {"PSP", 0x9 }, |
| 22501 | {"msplim", 0xa }, {"MSPLIM", 0xa }, |
| 22502 | {"psplim", 0xb }, {"PSPLIM", 0xb }, |
| 22503 | {"primask", 0x10}, {"PRIMASK", 0x10}, |
| 22504 | {"basepri", 0x11}, {"BASEPRI", 0x11}, |
| 22505 | {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12}, |
| 22506 | {"faultmask", 0x13}, {"FAULTMASK", 0x13}, |
| 22507 | {"control", 0x14}, {"CONTROL", 0x14}, |
| 22508 | {"msp_ns", 0x88}, {"MSP_NS", 0x88}, |
| 22509 | {"psp_ns", 0x89}, {"PSP_NS", 0x89}, |
| 22510 | {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a}, |
| 22511 | {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b}, |
| 22512 | {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90}, |
| 22513 | {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91}, |
| 22514 | {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93}, |
| 22515 | {"control_ns", 0x94}, {"CONTROL_NS", 0x94}, |
| 22516 | {"sp_ns", 0x98}, {"SP_NS", 0x98 } |
| 22517 | }; |
| 22518 | |
| 22519 | /* Table of all shift-in-operand names. */ |
| 22520 | static const struct asm_shift_name shift_names [] = |
| 22521 | { |
| 22522 | { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, |
| 22523 | { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, |
| 22524 | { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, |
| 22525 | { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, |
| 22526 | { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, |
| 22527 | { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }, |
| 22528 | { "uxtw", SHIFT_UXTW}, { "UXTW", SHIFT_UXTW} |
| 22529 | }; |
| 22530 | |
| 22531 | /* Table of all explicit relocation names. */ |
| 22532 | #ifdef OBJ_ELF |
| 22533 | static struct reloc_entry reloc_names[] = |
| 22534 | { |
| 22535 | { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, |
| 22536 | { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, |
| 22537 | { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, |
| 22538 | { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, |
| 22539 | { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, |
| 22540 | { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, |
| 22541 | { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, |
| 22542 | { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, |
| 22543 | { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, |
| 22544 | { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, |
| 22545 | { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}, |
| 22546 | { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL}, |
| 22547 | { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC}, |
| 22548 | { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC}, |
| 22549 | { "tlscall", BFD_RELOC_ARM_TLS_CALL}, |
| 22550 | { "TLSCALL", BFD_RELOC_ARM_TLS_CALL}, |
| 22551 | { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ}, |
| 22552 | { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}, |
| 22553 | { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC }, |
| 22554 | { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC }, |
| 22555 | { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC }, |
| 22556 | { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC }, |
| 22557 | { "funcdesc", BFD_RELOC_ARM_FUNCDESC }, |
| 22558 | { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC }, |
| 22559 | { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC }, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC }, |
| 22560 | { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC }, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC }, |
| 22561 | { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC }, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC }, |
| 22562 | }; |
| 22563 | #endif |
| 22564 | |
| 22565 | /* Table of all conditional affixes. */ |
| 22566 | static const struct asm_cond conds[] = |
| 22567 | { |
| 22568 | {"eq", 0x0}, |
| 22569 | {"ne", 0x1}, |
| 22570 | {"cs", 0x2}, {"hs", 0x2}, |
| 22571 | {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, |
| 22572 | {"mi", 0x4}, |
| 22573 | {"pl", 0x5}, |
| 22574 | {"vs", 0x6}, |
| 22575 | {"vc", 0x7}, |
| 22576 | {"hi", 0x8}, |
| 22577 | {"ls", 0x9}, |
| 22578 | {"ge", 0xa}, |
| 22579 | {"lt", 0xb}, |
| 22580 | {"gt", 0xc}, |
| 22581 | {"le", 0xd}, |
| 22582 | {"al", 0xe} |
| 22583 | }; |
| 22584 | static const struct asm_cond vconds[] = |
| 22585 | { |
| 22586 | {"t", 0xf}, |
| 22587 | {"e", 0x10} |
| 22588 | }; |
| 22589 | |
| 22590 | #define UL_BARRIER(L,U,CODE,FEAT) \ |
| 22591 | { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \ |
| 22592 | { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) } |
| 22593 | |
| 22594 | static struct asm_barrier_opt barrier_opt_names[] = |
| 22595 | { |
| 22596 | UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER), |
| 22597 | UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER), |
| 22598 | UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8), |
| 22599 | UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER), |
| 22600 | UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER), |
| 22601 | UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER), |
| 22602 | UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER), |
| 22603 | UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8), |
| 22604 | UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER), |
| 22605 | UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER), |
| 22606 | UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER), |
| 22607 | UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER), |
| 22608 | UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8), |
| 22609 | UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER), |
| 22610 | UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER), |
| 22611 | UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8) |
| 22612 | }; |
| 22613 | |
| 22614 | #undef UL_BARRIER |
| 22615 | |
| 22616 | /* Table of ARM-format instructions. */ |
| 22617 | |
| 22618 | /* Macros for gluing together operand strings. N.B. In all cases |
| 22619 | other than OPS0, the trailing OP_stop comes from default |
| 22620 | zero-initialization of the unspecified elements of the array. */ |
| 22621 | #define OPS0() { OP_stop, } |
| 22622 | #define OPS1(a) { OP_##a, } |
| 22623 | #define OPS2(a,b) { OP_##a,OP_##b, } |
| 22624 | #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } |
| 22625 | #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } |
| 22626 | #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } |
| 22627 | #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } |
| 22628 | |
| 22629 | /* These macros are similar to the OPSn, but do not prepend the OP_ prefix. |
| 22630 | This is useful when mixing operands for ARM and THUMB, i.e. using the |
| 22631 | MIX_ARM_THUMB_OPERANDS macro. |
| 22632 | In order to use these macros, prefix the number of operands with _ |
| 22633 | e.g. _3. */ |
| 22634 | #define OPS_1(a) { a, } |
| 22635 | #define OPS_2(a,b) { a,b, } |
| 22636 | #define OPS_3(a,b,c) { a,b,c, } |
| 22637 | #define OPS_4(a,b,c,d) { a,b,c,d, } |
| 22638 | #define OPS_5(a,b,c,d,e) { a,b,c,d,e, } |
| 22639 | #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, } |
| 22640 | |
| 22641 | /* These macros abstract out the exact format of the mnemonic table and |
| 22642 | save some repeated characters. */ |
| 22643 | |
| 22644 | /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ |
| 22645 | #define TxCE(mnem, op, top, nops, ops, ae, te) \ |
| 22646 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ |
| 22647 | THUMB_VARIANT, do_##ae, do_##te, 0 } |
| 22648 | |
| 22649 | /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for |
| 22650 | a T_MNEM_xyz enumerator. */ |
| 22651 | #define TCE(mnem, aop, top, nops, ops, ae, te) \ |
| 22652 | TxCE (mnem, aop, 0x##top, nops, ops, ae, te) |
| 22653 | #define tCE(mnem, aop, top, nops, ops, ae, te) \ |
| 22654 | TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
| 22655 | |
| 22656 | /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional |
| 22657 | infix after the third character. */ |
| 22658 | #define TxC3(mnem, op, top, nops, ops, ae, te) \ |
| 22659 | { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ |
| 22660 | THUMB_VARIANT, do_##ae, do_##te, 0 } |
| 22661 | #define TxC3w(mnem, op, top, nops, ops, ae, te) \ |
| 22662 | { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ |
| 22663 | THUMB_VARIANT, do_##ae, do_##te, 0 } |
| 22664 | #define TC3(mnem, aop, top, nops, ops, ae, te) \ |
| 22665 | TxC3 (mnem, aop, 0x##top, nops, ops, ae, te) |
| 22666 | #define TC3w(mnem, aop, top, nops, ops, ae, te) \ |
| 22667 | TxC3w (mnem, aop, 0x##top, nops, ops, ae, te) |
| 22668 | #define tC3(mnem, aop, top, nops, ops, ae, te) \ |
| 22669 | TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
| 22670 | #define tC3w(mnem, aop, top, nops, ops, ae, te) \ |
| 22671 | TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
| 22672 | |
| 22673 | /* Mnemonic that cannot be conditionalized. The ARM condition-code |
| 22674 | field is still 0xE. Many of the Thumb variants can be executed |
| 22675 | conditionally, so this is checked separately. */ |
| 22676 | #define TUE(mnem, op, top, nops, ops, ae, te) \ |
| 22677 | { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ |
| 22678 | THUMB_VARIANT, do_##ae, do_##te, 0 } |
| 22679 | |
| 22680 | /* Same as TUE but the encoding function for ARM and Thumb modes is the same. |
| 22681 | Used by mnemonics that have very minimal differences in the encoding for |
| 22682 | ARM and Thumb variants and can be handled in a common function. */ |
| 22683 | #define TUEc(mnem, op, top, nops, ops, en) \ |
| 22684 | { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ |
| 22685 | THUMB_VARIANT, do_##en, do_##en, 0 } |
| 22686 | |
| 22687 | /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM |
| 22688 | condition code field. */ |
| 22689 | #define TUF(mnem, op, top, nops, ops, ae, te) \ |
| 22690 | { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ |
| 22691 | THUMB_VARIANT, do_##ae, do_##te, 0 } |
| 22692 | |
| 22693 | /* ARM-only variants of all the above. */ |
| 22694 | #define CE(mnem, op, nops, ops, ae) \ |
| 22695 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 } |
| 22696 | |
| 22697 | #define C3(mnem, op, nops, ops, ae) \ |
| 22698 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 } |
| 22699 | |
| 22700 | /* Thumb-only variants of TCE and TUE. */ |
| 22701 | #define ToC(mnem, top, nops, ops, te) \ |
| 22702 | { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \ |
| 22703 | do_##te, 0 } |
| 22704 | |
| 22705 | #define ToU(mnem, top, nops, ops, te) \ |
| 22706 | { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \ |
| 22707 | NULL, do_##te, 0 } |
| 22708 | |
| 22709 | /* T_MNEM_xyz enumerator variants of ToC. */ |
| 22710 | #define toC(mnem, top, nops, ops, te) \ |
| 22711 | { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \ |
| 22712 | do_##te, 0 } |
| 22713 | |
| 22714 | /* T_MNEM_xyz enumerator variants of ToU. */ |
| 22715 | #define toU(mnem, top, nops, ops, te) \ |
| 22716 | { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \ |
| 22717 | NULL, do_##te, 0 } |
| 22718 | |
| 22719 | /* Legacy mnemonics that always have conditional infix after the third |
| 22720 | character. */ |
| 22721 | #define CL(mnem, op, nops, ops, ae) \ |
| 22722 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
| 22723 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 } |
| 22724 | |
| 22725 | /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ |
| 22726 | #define cCE(mnem, op, nops, ops, ae) \ |
| 22727 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 } |
| 22728 | |
| 22729 | /* mov instructions that are shared between coprocessor and MVE. */ |
| 22730 | #define mcCE(mnem, op, nops, ops, ae) \ |
| 22731 | { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 } |
| 22732 | |
| 22733 | /* Legacy coprocessor instructions where conditional infix and conditional |
| 22734 | suffix are ambiguous. For consistency this includes all FPA instructions, |
| 22735 | not just the potentially ambiguous ones. */ |
| 22736 | #define cCL(mnem, op, nops, ops, ae) \ |
| 22737 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
| 22738 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 } |
| 22739 | |
| 22740 | /* Coprocessor, takes either a suffix or a position-3 infix |
| 22741 | (for an FPA corner case). */ |
| 22742 | #define C3E(mnem, op, nops, ops, ae) \ |
| 22743 | { mnem, OPS##nops ops, OT_csuf_or_in3, \ |
| 22744 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 } |
| 22745 | |
| 22746 | #define xCM_(m1, m2, m3, op, nops, ops, ae) \ |
| 22747 | { m1 #m2 m3, OPS##nops ops, \ |
| 22748 | sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ |
| 22749 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 } |
| 22750 | |
| 22751 | #define CM(m1, m2, op, nops, ops, ae) \ |
| 22752 | xCM_ (m1, , m2, op, nops, ops, ae), \ |
| 22753 | xCM_ (m1, eq, m2, op, nops, ops, ae), \ |
| 22754 | xCM_ (m1, ne, m2, op, nops, ops, ae), \ |
| 22755 | xCM_ (m1, cs, m2, op, nops, ops, ae), \ |
| 22756 | xCM_ (m1, hs, m2, op, nops, ops, ae), \ |
| 22757 | xCM_ (m1, cc, m2, op, nops, ops, ae), \ |
| 22758 | xCM_ (m1, ul, m2, op, nops, ops, ae), \ |
| 22759 | xCM_ (m1, lo, m2, op, nops, ops, ae), \ |
| 22760 | xCM_ (m1, mi, m2, op, nops, ops, ae), \ |
| 22761 | xCM_ (m1, pl, m2, op, nops, ops, ae), \ |
| 22762 | xCM_ (m1, vs, m2, op, nops, ops, ae), \ |
| 22763 | xCM_ (m1, vc, m2, op, nops, ops, ae), \ |
| 22764 | xCM_ (m1, hi, m2, op, nops, ops, ae), \ |
| 22765 | xCM_ (m1, ls, m2, op, nops, ops, ae), \ |
| 22766 | xCM_ (m1, ge, m2, op, nops, ops, ae), \ |
| 22767 | xCM_ (m1, lt, m2, op, nops, ops, ae), \ |
| 22768 | xCM_ (m1, gt, m2, op, nops, ops, ae), \ |
| 22769 | xCM_ (m1, le, m2, op, nops, ops, ae), \ |
| 22770 | xCM_ (m1, al, m2, op, nops, ops, ae) |
| 22771 | |
| 22772 | #define UE(mnem, op, nops, ops, ae) \ |
| 22773 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 } |
| 22774 | |
| 22775 | #define UF(mnem, op, nops, ops, ae) \ |
| 22776 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 } |
| 22777 | |
| 22778 | /* Neon data-processing. ARM versions are unconditional with cond=0xf. |
| 22779 | The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we |
| 22780 | use the same encoding function for each. */ |
| 22781 | #define NUF(mnem, op, nops, ops, enc) \ |
| 22782 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ |
| 22783 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 } |
| 22784 | |
| 22785 | /* Neon data processing, version which indirects through neon_enc_tab for |
| 22786 | the various overloaded versions of opcodes. */ |
| 22787 | #define nUF(mnem, op, nops, ops, enc) \ |
| 22788 | { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \ |
| 22789 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 } |
| 22790 | |
| 22791 | /* Neon insn with conditional suffix for the ARM version, non-overloaded |
| 22792 | version. */ |
| 22793 | #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \ |
| 22794 | { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ |
| 22795 | THUMB_VARIANT, do_##enc, do_##enc, mve_p } |
| 22796 | |
| 22797 | #define NCE(mnem, op, nops, ops, enc) \ |
| 22798 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0) |
| 22799 | |
| 22800 | #define NCEF(mnem, op, nops, ops, enc) \ |
| 22801 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0) |
| 22802 | |
| 22803 | /* Neon insn with conditional suffix for the ARM version, overloaded types. */ |
| 22804 | #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \ |
| 22805 | { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \ |
| 22806 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p } |
| 22807 | |
| 22808 | #define nCE(mnem, op, nops, ops, enc) \ |
| 22809 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0) |
| 22810 | |
| 22811 | #define nCEF(mnem, op, nops, ops, enc) \ |
| 22812 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0) |
| 22813 | |
| 22814 | /* */ |
| 22815 | #define mCEF(mnem, op, nops, ops, enc) \ |
| 22816 | { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \ |
| 22817 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 } |
| 22818 | |
| 22819 | |
| 22820 | /* nCEF but for MVE predicated instructions. */ |
| 22821 | #define mnCEF(mnem, op, nops, ops, enc) \ |
| 22822 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1) |
| 22823 | |
| 22824 | /* nCE but for MVE predicated instructions. */ |
| 22825 | #define mnCE(mnem, op, nops, ops, enc) \ |
| 22826 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1) |
| 22827 | |
| 22828 | /* NUF but for potentially MVE predicated instructions. */ |
| 22829 | #define MNUF(mnem, op, nops, ops, enc) \ |
| 22830 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ |
| 22831 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 } |
| 22832 | |
| 22833 | /* nUF but for potentially MVE predicated instructions. */ |
| 22834 | #define mnUF(mnem, op, nops, ops, enc) \ |
| 22835 | { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \ |
| 22836 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 } |
| 22837 | |
| 22838 | /* ToC but for potentially MVE predicated instructions. */ |
| 22839 | #define mToC(mnem, top, nops, ops, te) \ |
| 22840 | { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \ |
| 22841 | do_##te, 1 } |
| 22842 | |
| 22843 | /* NCE but for MVE predicated instructions. */ |
| 22844 | #define MNCE(mnem, op, nops, ops, enc) \ |
| 22845 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1) |
| 22846 | |
| 22847 | /* NCEF but for MVE predicated instructions. */ |
| 22848 | #define MNCEF(mnem, op, nops, ops, enc) \ |
| 22849 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1) |
| 22850 | #define do_0 0 |
| 22851 | |
| 22852 | static const struct asm_opcode insns[] = |
| 22853 | { |
| 22854 | #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */ |
| 22855 | #define THUMB_VARIANT & arm_ext_v4t |
| 22856 | tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c), |
| 22857 | tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c), |
| 22858 | tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c), |
| 22859 | tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c), |
| 22860 | tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub), |
| 22861 | tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub), |
| 22862 | tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub), |
| 22863 | tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub), |
| 22864 | tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c), |
| 22865 | tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c), |
| 22866 | tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3), |
| 22867 | tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3), |
| 22868 | tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c), |
| 22869 | tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c), |
| 22870 | tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3), |
| 22871 | tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3), |
| 22872 | |
| 22873 | /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism |
| 22874 | for setting PSR flag bits. They are obsolete in V6 and do not |
| 22875 | have Thumb equivalents. */ |
| 22876 | tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), |
| 22877 | tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), |
| 22878 | CL("tstp", 110f000, 2, (RR, SH), cmp), |
| 22879 | tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), |
| 22880 | tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), |
| 22881 | CL("cmpp", 150f000, 2, (RR, SH), cmp), |
| 22882 | tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), |
| 22883 | tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), |
| 22884 | CL("cmnp", 170f000, 2, (RR, SH), cmp), |
| 22885 | |
| 22886 | tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp), |
| 22887 | tC3("movs", 1b00000, _movs, 2, (RR, SHG), mov, t_mov_cmp), |
| 22888 | tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst), |
| 22889 | tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst), |
| 22890 | |
| 22891 | tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), |
| 22892 | tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), |
| 22893 | tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR, |
| 22894 | OP_RRnpc), |
| 22895 | OP_ADDRGLDR),ldst, t_ldst), |
| 22896 | tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), |
| 22897 | |
| 22898 | tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
| 22899 | tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
| 22900 | tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
| 22901 | tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
| 22902 | tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
| 22903 | tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
| 22904 | |
| 22905 | tCE("b", a000000, _b, 1, (EXPr), branch, t_branch), |
| 22906 | TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23), |
| 22907 | |
| 22908 | /* Pseudo ops. */ |
| 22909 | tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr), |
| 22910 | C3(adrl, 28f0000, 2, (RR, EXP), adrl), |
| 22911 | tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop), |
| 22912 | tCE("udf", 7f000f0, _udf, 1, (oIffffb), bkpt, t_udf), |
| 22913 | |
| 22914 | /* Thumb-compatibility pseudo ops. */ |
| 22915 | tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift), |
| 22916 | tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift), |
| 22917 | tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift), |
| 22918 | tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift), |
| 22919 | tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift), |
| 22920 | tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift), |
| 22921 | tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift), |
| 22922 | tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift), |
| 22923 | tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg), |
| 22924 | tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg), |
| 22925 | tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop), |
| 22926 | tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop), |
| 22927 | |
| 22928 | /* These may simplify to neg. */ |
| 22929 | TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), |
| 22930 | TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), |
| 22931 | |
| 22932 | #undef THUMB_VARIANT |
| 22933 | #define THUMB_VARIANT & arm_ext_os |
| 22934 | |
| 22935 | TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi), |
| 22936 | TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi), |
| 22937 | |
| 22938 | #undef THUMB_VARIANT |
| 22939 | #define THUMB_VARIANT & arm_ext_v6 |
| 22940 | |
| 22941 | TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), |
| 22942 | |
| 22943 | /* V1 instructions with no Thumb analogue prior to V6T2. */ |
| 22944 | #undef THUMB_VARIANT |
| 22945 | #define THUMB_VARIANT & arm_ext_v6t2 |
| 22946 | |
| 22947 | TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), |
| 22948 | TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), |
| 22949 | CL("teqp", 130f000, 2, (RR, SH), cmp), |
| 22950 | |
| 22951 | TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), |
| 22952 | TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), |
| 22953 | TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt), |
| 22954 | TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), |
| 22955 | |
| 22956 | TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
| 22957 | TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
| 22958 | |
| 22959 | TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
| 22960 | TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
| 22961 | |
| 22962 | /* V1 instructions with no Thumb analogue at all. */ |
| 22963 | CE("rsc", 0e00000, 3, (RR, oRR, SH), arit), |
| 22964 | C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), |
| 22965 | |
| 22966 | C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), |
| 22967 | C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), |
| 22968 | C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), |
| 22969 | C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), |
| 22970 | C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), |
| 22971 | C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), |
| 22972 | C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), |
| 22973 | C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), |
| 22974 | |
| 22975 | #undef ARM_VARIANT |
| 22976 | #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */ |
| 22977 | #undef THUMB_VARIANT |
| 22978 | #define THUMB_VARIANT & arm_ext_v4t |
| 22979 | |
| 22980 | tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), |
| 22981 | tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), |
| 22982 | |
| 22983 | #undef THUMB_VARIANT |
| 22984 | #define THUMB_VARIANT & arm_ext_v6t2 |
| 22985 | |
| 22986 | TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
| 22987 | C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), |
| 22988 | |
| 22989 | /* Generic coprocessor instructions. */ |
| 22990 | TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), |
| 22991 | TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), |
| 22992 | TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), |
| 22993 | TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), |
| 22994 | TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), |
| 22995 | TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), |
| 22996 | TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg), |
| 22997 | |
| 22998 | #undef ARM_VARIANT |
| 22999 | #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */ |
| 23000 | |
| 23001 | CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
| 23002 | C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
| 23003 | |
| 23004 | #undef ARM_VARIANT |
| 23005 | #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */ |
| 23006 | #undef THUMB_VARIANT |
| 23007 | #define THUMB_VARIANT & arm_ext_msr |
| 23008 | |
| 23009 | TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs), |
| 23010 | TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr), |
| 23011 | |
| 23012 | #undef ARM_VARIANT |
| 23013 | #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */ |
| 23014 | #undef THUMB_VARIANT |
| 23015 | #define THUMB_VARIANT & arm_ext_v6t2 |
| 23016 | |
| 23017 | TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), |
| 23018 | CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), |
| 23019 | TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), |
| 23020 | CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), |
| 23021 | TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), |
| 23022 | CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), |
| 23023 | TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), |
| 23024 | CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), |
| 23025 | |
| 23026 | #undef ARM_VARIANT |
| 23027 | #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */ |
| 23028 | #undef THUMB_VARIANT |
| 23029 | #define THUMB_VARIANT & arm_ext_v4t |
| 23030 | |
| 23031 | tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
| 23032 | tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
| 23033 | tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
| 23034 | tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
| 23035 | tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
| 23036 | tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
| 23037 | |
| 23038 | #undef ARM_VARIANT |
| 23039 | #define ARM_VARIANT & arm_ext_v4t_5 |
| 23040 | |
| 23041 | /* ARM Architecture 4T. */ |
| 23042 | /* Note: bx (and blx) are required on V5, even if the processor does |
| 23043 | not support Thumb. */ |
| 23044 | TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx), |
| 23045 | |
| 23046 | #undef ARM_VARIANT |
| 23047 | #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */ |
| 23048 | #undef THUMB_VARIANT |
| 23049 | #define THUMB_VARIANT & arm_ext_v5t |
| 23050 | |
| 23051 | /* Note: blx has 2 variants; the .value coded here is for |
| 23052 | BLX(2). Only this variant has conditional execution. */ |
| 23053 | TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx), |
| 23054 | TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), |
| 23055 | |
| 23056 | #undef THUMB_VARIANT |
| 23057 | #define THUMB_VARIANT & arm_ext_v6t2 |
| 23058 | |
| 23059 | TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), |
| 23060 | TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), |
| 23061 | TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), |
| 23062 | TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), |
| 23063 | TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), |
| 23064 | TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), |
| 23065 | TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), |
| 23066 | TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), |
| 23067 | |
| 23068 | #undef ARM_VARIANT |
| 23069 | #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */ |
| 23070 | #undef THUMB_VARIANT |
| 23071 | #define THUMB_VARIANT & arm_ext_v5exp |
| 23072 | |
| 23073 | TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
| 23074 | TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
| 23075 | TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
| 23076 | TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
| 23077 | |
| 23078 | TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
| 23079 | TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
| 23080 | |
| 23081 | TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), |
| 23082 | TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), |
| 23083 | TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), |
| 23084 | TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), |
| 23085 | |
| 23086 | TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
| 23087 | TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
| 23088 | TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
| 23089 | TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
| 23090 | |
| 23091 | TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
| 23092 | TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
| 23093 | |
| 23094 | TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), |
| 23095 | TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), |
| 23096 | TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), |
| 23097 | TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), |
| 23098 | |
| 23099 | #undef ARM_VARIANT |
| 23100 | #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */ |
| 23101 | #undef THUMB_VARIANT |
| 23102 | #define THUMB_VARIANT & arm_ext_v6t2 |
| 23103 | |
| 23104 | TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld), |
| 23105 | TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS), |
| 23106 | ldrd, t_ldstd), |
| 23107 | TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp, |
| 23108 | ADDRGLDRS), ldrd, t_ldstd), |
| 23109 | |
| 23110 | TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
| 23111 | TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
| 23112 | |
| 23113 | #undef ARM_VARIANT |
| 23114 | #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */ |
| 23115 | |
| 23116 | TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), |
| 23117 | |
| 23118 | #undef ARM_VARIANT |
| 23119 | #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */ |
| 23120 | #undef THUMB_VARIANT |
| 23121 | #define THUMB_VARIANT & arm_ext_v6 |
| 23122 | |
| 23123 | TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), |
| 23124 | TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), |
| 23125 | tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), |
| 23126 | tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), |
| 23127 | tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), |
| 23128 | tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), |
| 23129 | tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), |
| 23130 | tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), |
| 23131 | tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), |
| 23132 | TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend), |
| 23133 | |
| 23134 | #undef THUMB_VARIANT |
| 23135 | #define THUMB_VARIANT & arm_ext_v6t2_v8m |
| 23136 | |
| 23137 | TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex), |
| 23138 | TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), |
| 23139 | strex, t_strex), |
| 23140 | #undef THUMB_VARIANT |
| 23141 | #define THUMB_VARIANT & arm_ext_v6t2 |
| 23142 | |
| 23143 | TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
| 23144 | TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
| 23145 | |
| 23146 | TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), |
| 23147 | TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), |
| 23148 | |
| 23149 | /* ARM V6 not included in V7M. */ |
| 23150 | #undef THUMB_VARIANT |
| 23151 | #define THUMB_VARIANT & arm_ext_v6_notm |
| 23152 | TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe), |
| 23153 | TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe), |
| 23154 | UF(rfeib, 9900a00, 1, (RRw), rfe), |
| 23155 | UF(rfeda, 8100a00, 1, (RRw), rfe), |
| 23156 | TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe), |
| 23157 | TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe), |
| 23158 | UF(rfefa, 8100a00, 1, (RRw), rfe), |
| 23159 | TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe), |
| 23160 | UF(rfeed, 9900a00, 1, (RRw), rfe), |
| 23161 | TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), |
| 23162 | TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), |
| 23163 | TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), |
| 23164 | UF(srsib, 9c00500, 2, (oRRw, I31w), srs), |
| 23165 | UF(srsfa, 9c00500, 2, (oRRw, I31w), srs), |
| 23166 | UF(srsda, 8400500, 2, (oRRw, I31w), srs), |
| 23167 | UF(srsed, 8400500, 2, (oRRw, I31w), srs), |
| 23168 | TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs), |
| 23169 | TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs), |
| 23170 | TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps), |
| 23171 | |
| 23172 | /* ARM V6 not included in V7M (eg. integer SIMD). */ |
| 23173 | #undef THUMB_VARIANT |
| 23174 | #define THUMB_VARIANT & arm_ext_v6_dsp |
| 23175 | TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), |
| 23176 | TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), |
| 23177 | TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23178 | TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23179 | TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23180 | /* Old name for QASX. */ |
| 23181 | TCE("qaddsubx",6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23182 | TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23183 | /* Old name for QSAX. */ |
| 23184 | TCE("qsubaddx",6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23185 | TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23186 | TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23187 | TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23188 | TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23189 | TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23190 | /* Old name for SASX. */ |
| 23191 | TCE("saddsubx",6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23192 | TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23193 | TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23194 | TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23195 | /* Old name for SHASX. */ |
| 23196 | TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23197 | TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23198 | /* Old name for SHSAX. */ |
| 23199 | TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23200 | TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23201 | TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23202 | TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23203 | /* Old name for SSAX. */ |
| 23204 | TCE("ssubaddx",6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23205 | TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23206 | TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23207 | TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23208 | TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23209 | TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23210 | /* Old name for UASX. */ |
| 23211 | TCE("uaddsubx",6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23212 | TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23213 | TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23214 | TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23215 | /* Old name for UHASX. */ |
| 23216 | TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23217 | TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23218 | /* Old name for UHSAX. */ |
| 23219 | TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23220 | TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23221 | TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23222 | TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23223 | TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23224 | TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23225 | /* Old name for UQASX. */ |
| 23226 | TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23227 | TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23228 | /* Old name for UQSAX. */ |
| 23229 | TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23230 | TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23231 | TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23232 | TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23233 | TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23234 | /* Old name for USAX. */ |
| 23235 | TCE("usubaddx",6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23236 | TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23237 | TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), |
| 23238 | TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), |
| 23239 | TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), |
| 23240 | TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), |
| 23241 | TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), |
| 23242 | TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), |
| 23243 | TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), |
| 23244 | TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), |
| 23245 | TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
| 23246 | TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), |
| 23247 | TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), |
| 23248 | TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), |
| 23249 | TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), |
| 23250 | TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), |
| 23251 | TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), |
| 23252 | TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), |
| 23253 | TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), |
| 23254 | TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), |
| 23255 | TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), |
| 23256 | TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), |
| 23257 | TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), |
| 23258 | TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
| 23259 | TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
| 23260 | TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
| 23261 | TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
| 23262 | TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
| 23263 | TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
| 23264 | TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), |
| 23265 | TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), |
| 23266 | TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
| 23267 | TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), |
| 23268 | TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), |
| 23269 | |
| 23270 | #undef ARM_VARIANT |
| 23271 | #define ARM_VARIANT & arm_ext_v6k_v6t2 |
| 23272 | #undef THUMB_VARIANT |
| 23273 | #define THUMB_VARIANT & arm_ext_v6k_v6t2 |
| 23274 | |
| 23275 | tCE("yield", 320f001, _yield, 0, (), noargs, t_hint), |
| 23276 | tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint), |
| 23277 | tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint), |
| 23278 | tCE("sev", 320f004, _sev, 0, (), noargs, t_hint), |
| 23279 | |
| 23280 | #undef THUMB_VARIANT |
| 23281 | #define THUMB_VARIANT & arm_ext_v6_notm |
| 23282 | TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb), |
| 23283 | ldrexd, t_ldrexd), |
| 23284 | TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp, |
| 23285 | RRnpcb), strexd, t_strexd), |
| 23286 | |
| 23287 | #undef THUMB_VARIANT |
| 23288 | #define THUMB_VARIANT & arm_ext_v6t2_v8m |
| 23289 | TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb), |
| 23290 | rd_rn, rd_rn), |
| 23291 | TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb), |
| 23292 | rd_rn, rd_rn), |
| 23293 | TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), |
| 23294 | strex, t_strexbh), |
| 23295 | TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), |
| 23296 | strex, t_strexbh), |
| 23297 | TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs), |
| 23298 | |
| 23299 | #undef ARM_VARIANT |
| 23300 | #define ARM_VARIANT & arm_ext_sec |
| 23301 | #undef THUMB_VARIANT |
| 23302 | #define THUMB_VARIANT & arm_ext_sec |
| 23303 | |
| 23304 | TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc), |
| 23305 | |
| 23306 | #undef ARM_VARIANT |
| 23307 | #define ARM_VARIANT & arm_ext_virt |
| 23308 | #undef THUMB_VARIANT |
| 23309 | #define THUMB_VARIANT & arm_ext_virt |
| 23310 | |
| 23311 | TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc), |
| 23312 | TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs), |
| 23313 | |
| 23314 | #undef ARM_VARIANT |
| 23315 | #define ARM_VARIANT & arm_ext_pan |
| 23316 | #undef THUMB_VARIANT |
| 23317 | #define THUMB_VARIANT & arm_ext_pan |
| 23318 | |
| 23319 | TUF("setpan", 1100000, b610, 1, (I7), setpan, t_setpan), |
| 23320 | |
| 23321 | #undef ARM_VARIANT |
| 23322 | #define ARM_VARIANT & arm_ext_v6t2 |
| 23323 | #undef THUMB_VARIANT |
| 23324 | #define THUMB_VARIANT & arm_ext_v6t2 |
| 23325 | |
| 23326 | TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), |
| 23327 | TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), |
| 23328 | TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), |
| 23329 | TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), |
| 23330 | |
| 23331 | TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
| 23332 | TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), |
| 23333 | |
| 23334 | TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), |
| 23335 | TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), |
| 23336 | TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), |
| 23337 | TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), |
| 23338 | |
| 23339 | #undef ARM_VARIANT |
| 23340 | #define ARM_VARIANT & arm_ext_v3 |
| 23341 | #undef THUMB_VARIANT |
| 23342 | #define THUMB_VARIANT & arm_ext_v6t2 |
| 23343 | |
| 23344 | TUE("csdb", 320f014, f3af8014, 0, (), noargs, t_csdb), |
| 23345 | TUF("ssbb", 57ff040, f3bf8f40, 0, (), noargs, t_csdb), |
| 23346 | TUF("pssbb", 57ff044, f3bf8f44, 0, (), noargs, t_csdb), |
| 23347 | |
| 23348 | #undef ARM_VARIANT |
| 23349 | #define ARM_VARIANT & arm_ext_v6t2 |
| 23350 | #undef THUMB_VARIANT |
| 23351 | #define THUMB_VARIANT & arm_ext_v6t2_v8m |
| 23352 | TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), |
| 23353 | TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), |
| 23354 | |
| 23355 | /* Thumb-only instructions. */ |
| 23356 | #undef ARM_VARIANT |
| 23357 | #define ARM_VARIANT NULL |
| 23358 | TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz), |
| 23359 | TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz), |
| 23360 | |
| 23361 | /* ARM does not really have an IT instruction, so always allow it. |
| 23362 | The opcode is copied from Thumb in order to allow warnings in |
| 23363 | -mimplicit-it=[never | arm] modes. */ |
| 23364 | #undef ARM_VARIANT |
| 23365 | #define ARM_VARIANT & arm_ext_v1 |
| 23366 | #undef THUMB_VARIANT |
| 23367 | #define THUMB_VARIANT & arm_ext_v6t2 |
| 23368 | |
| 23369 | TUE("it", bf08, bf08, 1, (COND), it, t_it), |
| 23370 | TUE("itt", bf0c, bf0c, 1, (COND), it, t_it), |
| 23371 | TUE("ite", bf04, bf04, 1, (COND), it, t_it), |
| 23372 | TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it), |
| 23373 | TUE("itet", bf06, bf06, 1, (COND), it, t_it), |
| 23374 | TUE("itte", bf0a, bf0a, 1, (COND), it, t_it), |
| 23375 | TUE("itee", bf02, bf02, 1, (COND), it, t_it), |
| 23376 | TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it), |
| 23377 | TUE("itett", bf07, bf07, 1, (COND), it, t_it), |
| 23378 | TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it), |
| 23379 | TUE("iteet", bf03, bf03, 1, (COND), it, t_it), |
| 23380 | TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it), |
| 23381 | TUE("itete", bf05, bf05, 1, (COND), it, t_it), |
| 23382 | TUE("ittee", bf09, bf09, 1, (COND), it, t_it), |
| 23383 | TUE("iteee", bf01, bf01, 1, (COND), it, t_it), |
| 23384 | /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */ |
| 23385 | TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx), |
| 23386 | TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx), |
| 23387 | |
| 23388 | /* Thumb2 only instructions. */ |
| 23389 | #undef ARM_VARIANT |
| 23390 | #define ARM_VARIANT NULL |
| 23391 | |
| 23392 | TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), |
| 23393 | TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), |
| 23394 | TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn), |
| 23395 | TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn), |
| 23396 | TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb), |
| 23397 | TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb), |
| 23398 | |
| 23399 | /* Hardware division instructions. */ |
| 23400 | #undef ARM_VARIANT |
| 23401 | #define ARM_VARIANT & arm_ext_adiv |
| 23402 | #undef THUMB_VARIANT |
| 23403 | #define THUMB_VARIANT & arm_ext_div |
| 23404 | |
| 23405 | TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div), |
| 23406 | TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div), |
| 23407 | |
| 23408 | /* ARM V6M/V7 instructions. */ |
| 23409 | #undef ARM_VARIANT |
| 23410 | #define ARM_VARIANT & arm_ext_barrier |
| 23411 | #undef THUMB_VARIANT |
| 23412 | #define THUMB_VARIANT & arm_ext_barrier |
| 23413 | |
| 23414 | TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier), |
| 23415 | TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier), |
| 23416 | TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier), |
| 23417 | |
| 23418 | /* ARM V7 instructions. */ |
| 23419 | #undef ARM_VARIANT |
| 23420 | #define ARM_VARIANT & arm_ext_v7 |
| 23421 | #undef THUMB_VARIANT |
| 23422 | #define THUMB_VARIANT & arm_ext_v7 |
| 23423 | |
| 23424 | TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld), |
| 23425 | TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), |
| 23426 | |
| 23427 | #undef ARM_VARIANT |
| 23428 | #define ARM_VARIANT & arm_ext_mp |
| 23429 | #undef THUMB_VARIANT |
| 23430 | #define THUMB_VARIANT & arm_ext_mp |
| 23431 | |
| 23432 | TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld), |
| 23433 | |
| 23434 | /* AArchv8 instructions. */ |
| 23435 | #undef ARM_VARIANT |
| 23436 | #define ARM_VARIANT & arm_ext_v8 |
| 23437 | |
| 23438 | /* Instructions shared between armv8-a and armv8-m. */ |
| 23439 | #undef THUMB_VARIANT |
| 23440 | #define THUMB_VARIANT & arm_ext_atomics |
| 23441 | |
| 23442 | TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), |
| 23443 | TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), |
| 23444 | TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), |
| 23445 | TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), |
| 23446 | TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), |
| 23447 | TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), |
| 23448 | TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), |
| 23449 | TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn), |
| 23450 | TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), |
| 23451 | TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb), |
| 23452 | stlex, t_stlex), |
| 23453 | TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb), |
| 23454 | stlex, t_stlex), |
| 23455 | TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb), |
| 23456 | stlex, t_stlex), |
| 23457 | #undef THUMB_VARIANT |
| 23458 | #define THUMB_VARIANT & arm_ext_v8 |
| 23459 | |
| 23460 | tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint), |
| 23461 | TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb), |
| 23462 | ldrexd, t_ldrexd), |
| 23463 | TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), |
| 23464 | strexd, t_strexd), |
| 23465 | |
| 23466 | /* Defined in V8 but is in undefined encoding space for earlier |
| 23467 | architectures. However earlier architectures are required to treat |
| 23468 | this instuction as a semihosting trap as well. Hence while not explicitly |
| 23469 | defined as such, it is in fact correct to define the instruction for all |
| 23470 | architectures. */ |
| 23471 | #undef THUMB_VARIANT |
| 23472 | #define THUMB_VARIANT & arm_ext_v1 |
| 23473 | #undef ARM_VARIANT |
| 23474 | #define ARM_VARIANT & arm_ext_v1 |
| 23475 | TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt), |
| 23476 | |
| 23477 | /* ARMv8 T32 only. */ |
| 23478 | #undef ARM_VARIANT |
| 23479 | #define ARM_VARIANT NULL |
| 23480 | TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs), |
| 23481 | TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs), |
| 23482 | TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs), |
| 23483 | |
| 23484 | /* FP for ARMv8. */ |
| 23485 | #undef ARM_VARIANT |
| 23486 | #define ARM_VARIANT & fpu_vfp_ext_armv8xd |
| 23487 | #undef THUMB_VARIANT |
| 23488 | #define THUMB_VARIANT & fpu_vfp_ext_armv8xd |
| 23489 | |
| 23490 | nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel), |
| 23491 | nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel), |
| 23492 | nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel), |
| 23493 | nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel), |
| 23494 | nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr), |
| 23495 | nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz), |
| 23496 | nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx), |
| 23497 | nUF(vrinta, _vrinta, 2, (RNSDQ, oRNSDQ), vrinta), |
| 23498 | nUF(vrintn, _vrinta, 2, (RNSDQ, oRNSDQ), vrintn), |
| 23499 | nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp), |
| 23500 | nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm), |
| 23501 | |
| 23502 | /* Crypto v1 extensions. */ |
| 23503 | #undef ARM_VARIANT |
| 23504 | #define ARM_VARIANT & fpu_crypto_ext_armv8 |
| 23505 | #undef THUMB_VARIANT |
| 23506 | #define THUMB_VARIANT & fpu_crypto_ext_armv8 |
| 23507 | |
| 23508 | nUF(aese, _aes, 2, (RNQ, RNQ), aese), |
| 23509 | nUF(aesd, _aes, 2, (RNQ, RNQ), aesd), |
| 23510 | nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc), |
| 23511 | nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc), |
| 23512 | nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c), |
| 23513 | nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p), |
| 23514 | nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m), |
| 23515 | nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0), |
| 23516 | nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h), |
| 23517 | nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2), |
| 23518 | nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1), |
| 23519 | nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h), |
| 23520 | nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1), |
| 23521 | nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0), |
| 23522 | |
| 23523 | #undef ARM_VARIANT |
| 23524 | #define ARM_VARIANT & crc_ext_armv8 |
| 23525 | #undef THUMB_VARIANT |
| 23526 | #define THUMB_VARIANT & crc_ext_armv8 |
| 23527 | TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b), |
| 23528 | TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h), |
| 23529 | TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w), |
| 23530 | TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb), |
| 23531 | TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch), |
| 23532 | TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw), |
| 23533 | |
| 23534 | /* ARMv8.2 RAS extension. */ |
| 23535 | #undef ARM_VARIANT |
| 23536 | #define ARM_VARIANT & arm_ext_ras |
| 23537 | #undef THUMB_VARIANT |
| 23538 | #define THUMB_VARIANT & arm_ext_ras |
| 23539 | TUE ("esb", 320f010, f3af8010, 0, (), noargs, noargs), |
| 23540 | |
| 23541 | #undef ARM_VARIANT |
| 23542 | #define ARM_VARIANT & arm_ext_v8_3 |
| 23543 | #undef THUMB_VARIANT |
| 23544 | #define THUMB_VARIANT & arm_ext_v8_3 |
| 23545 | NCE (vjcvt, eb90bc0, 2, (RVS, RVD), vjcvt), |
| 23546 | |
| 23547 | #undef ARM_VARIANT |
| 23548 | #define ARM_VARIANT & fpu_neon_ext_dotprod |
| 23549 | #undef THUMB_VARIANT |
| 23550 | #define THUMB_VARIANT & fpu_neon_ext_dotprod |
| 23551 | NUF (vsdot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_s), |
| 23552 | NUF (vudot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_u), |
| 23553 | |
| 23554 | #undef ARM_VARIANT |
| 23555 | #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ |
| 23556 | #undef THUMB_VARIANT |
| 23557 | #define THUMB_VARIANT NULL |
| 23558 | |
| 23559 | cCE("wfs", e200110, 1, (RR), rd), |
| 23560 | cCE("rfs", e300110, 1, (RR), rd), |
| 23561 | cCE("wfc", e400110, 1, (RR), rd), |
| 23562 | cCE("rfc", e500110, 1, (RR), rd), |
| 23563 | |
| 23564 | cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr), |
| 23565 | cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr), |
| 23566 | cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr), |
| 23567 | cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr), |
| 23568 | |
| 23569 | cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr), |
| 23570 | cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr), |
| 23571 | cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr), |
| 23572 | cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr), |
| 23573 | |
| 23574 | cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm), |
| 23575 | cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm), |
| 23576 | cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm), |
| 23577 | cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm), |
| 23578 | cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm), |
| 23579 | cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm), |
| 23580 | cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm), |
| 23581 | cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm), |
| 23582 | cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm), |
| 23583 | cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm), |
| 23584 | cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm), |
| 23585 | cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm), |
| 23586 | |
| 23587 | cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm), |
| 23588 | cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm), |
| 23589 | cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm), |
| 23590 | cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm), |
| 23591 | cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm), |
| 23592 | cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm), |
| 23593 | cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm), |
| 23594 | cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm), |
| 23595 | cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm), |
| 23596 | cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm), |
| 23597 | cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm), |
| 23598 | cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm), |
| 23599 | |
| 23600 | cCL("abss", e208100, 2, (RF, RF_IF), rd_rm), |
| 23601 | cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm), |
| 23602 | cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm), |
| 23603 | cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm), |
| 23604 | cCL("absd", e208180, 2, (RF, RF_IF), rd_rm), |
| 23605 | cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm), |
| 23606 | cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm), |
| 23607 | cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm), |
| 23608 | cCL("abse", e288100, 2, (RF, RF_IF), rd_rm), |
| 23609 | cCL("absep", e288120, 2, (RF, RF_IF), rd_rm), |
| 23610 | cCL("absem", e288140, 2, (RF, RF_IF), rd_rm), |
| 23611 | cCL("absez", e288160, 2, (RF, RF_IF), rd_rm), |
| 23612 | |
| 23613 | cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm), |
| 23614 | cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm), |
| 23615 | cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm), |
| 23616 | cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm), |
| 23617 | cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm), |
| 23618 | cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm), |
| 23619 | cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm), |
| 23620 | cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm), |
| 23621 | cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm), |
| 23622 | cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm), |
| 23623 | cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm), |
| 23624 | cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm), |
| 23625 | |
| 23626 | cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm), |
| 23627 | cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm), |
| 23628 | cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm), |
| 23629 | cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm), |
| 23630 | cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm), |
| 23631 | cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm), |
| 23632 | cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm), |
| 23633 | cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm), |
| 23634 | cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm), |
| 23635 | cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm), |
| 23636 | cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm), |
| 23637 | cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm), |
| 23638 | |
| 23639 | cCL("logs", e508100, 2, (RF, RF_IF), rd_rm), |
| 23640 | cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm), |
| 23641 | cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm), |
| 23642 | cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm), |
| 23643 | cCL("logd", e508180, 2, (RF, RF_IF), rd_rm), |
| 23644 | cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm), |
| 23645 | cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm), |
| 23646 | cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm), |
| 23647 | cCL("loge", e588100, 2, (RF, RF_IF), rd_rm), |
| 23648 | cCL("logep", e588120, 2, (RF, RF_IF), rd_rm), |
| 23649 | cCL("logem", e588140, 2, (RF, RF_IF), rd_rm), |
| 23650 | cCL("logez", e588160, 2, (RF, RF_IF), rd_rm), |
| 23651 | |
| 23652 | cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm), |
| 23653 | cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm), |
| 23654 | cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm), |
| 23655 | cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm), |
| 23656 | cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm), |
| 23657 | cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm), |
| 23658 | cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm), |
| 23659 | cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm), |
| 23660 | cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm), |
| 23661 | cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm), |
| 23662 | cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm), |
| 23663 | cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm), |
| 23664 | |
| 23665 | cCL("exps", e708100, 2, (RF, RF_IF), rd_rm), |
| 23666 | cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm), |
| 23667 | cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm), |
| 23668 | cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm), |
| 23669 | cCL("expd", e708180, 2, (RF, RF_IF), rd_rm), |
| 23670 | cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm), |
| 23671 | cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm), |
| 23672 | cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm), |
| 23673 | cCL("expe", e788100, 2, (RF, RF_IF), rd_rm), |
| 23674 | cCL("expep", e788120, 2, (RF, RF_IF), rd_rm), |
| 23675 | cCL("expem", e788140, 2, (RF, RF_IF), rd_rm), |
| 23676 | cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm), |
| 23677 | |
| 23678 | cCL("sins", e808100, 2, (RF, RF_IF), rd_rm), |
| 23679 | cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm), |
| 23680 | cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm), |
| 23681 | cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm), |
| 23682 | cCL("sind", e808180, 2, (RF, RF_IF), rd_rm), |
| 23683 | cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm), |
| 23684 | cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm), |
| 23685 | cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm), |
| 23686 | cCL("sine", e888100, 2, (RF, RF_IF), rd_rm), |
| 23687 | cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm), |
| 23688 | cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm), |
| 23689 | cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm), |
| 23690 | |
| 23691 | cCL("coss", e908100, 2, (RF, RF_IF), rd_rm), |
| 23692 | cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm), |
| 23693 | cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm), |
| 23694 | cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm), |
| 23695 | cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm), |
| 23696 | cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm), |
| 23697 | cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm), |
| 23698 | cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm), |
| 23699 | cCL("cose", e988100, 2, (RF, RF_IF), rd_rm), |
| 23700 | cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm), |
| 23701 | cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm), |
| 23702 | cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm), |
| 23703 | |
| 23704 | cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm), |
| 23705 | cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm), |
| 23706 | cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm), |
| 23707 | cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm), |
| 23708 | cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm), |
| 23709 | cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm), |
| 23710 | cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm), |
| 23711 | cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm), |
| 23712 | cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm), |
| 23713 | cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm), |
| 23714 | cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm), |
| 23715 | cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm), |
| 23716 | |
| 23717 | cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm), |
| 23718 | cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm), |
| 23719 | cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm), |
| 23720 | cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm), |
| 23721 | cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm), |
| 23722 | cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm), |
| 23723 | cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm), |
| 23724 | cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm), |
| 23725 | cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm), |
| 23726 | cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm), |
| 23727 | cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm), |
| 23728 | cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm), |
| 23729 | |
| 23730 | cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm), |
| 23731 | cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm), |
| 23732 | cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm), |
| 23733 | cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm), |
| 23734 | cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm), |
| 23735 | cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm), |
| 23736 | cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm), |
| 23737 | cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm), |
| 23738 | cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm), |
| 23739 | cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm), |
| 23740 | cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm), |
| 23741 | cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm), |
| 23742 | |
| 23743 | cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm), |
| 23744 | cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm), |
| 23745 | cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm), |
| 23746 | cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm), |
| 23747 | cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm), |
| 23748 | cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm), |
| 23749 | cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm), |
| 23750 | cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm), |
| 23751 | cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm), |
| 23752 | cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm), |
| 23753 | cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm), |
| 23754 | cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm), |
| 23755 | |
| 23756 | cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm), |
| 23757 | cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm), |
| 23758 | cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm), |
| 23759 | cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm), |
| 23760 | cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm), |
| 23761 | cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm), |
| 23762 | cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm), |
| 23763 | cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm), |
| 23764 | cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm), |
| 23765 | cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm), |
| 23766 | cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm), |
| 23767 | cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm), |
| 23768 | |
| 23769 | cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm), |
| 23770 | cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm), |
| 23771 | cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm), |
| 23772 | cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm), |
| 23773 | cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm), |
| 23774 | cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm), |
| 23775 | cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm), |
| 23776 | cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm), |
| 23777 | cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm), |
| 23778 | cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm), |
| 23779 | cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm), |
| 23780 | cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm), |
| 23781 | |
| 23782 | cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23783 | cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23784 | cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23785 | cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23786 | cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23787 | cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23788 | cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23789 | cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23790 | cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23791 | cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23792 | cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23793 | cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23794 | |
| 23795 | cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23796 | cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23797 | cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23798 | cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23799 | cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23800 | cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23801 | cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23802 | cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23803 | cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23804 | cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23805 | cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23806 | cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23807 | |
| 23808 | cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23809 | cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23810 | cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23811 | cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23812 | cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23813 | cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23814 | cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23815 | cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23816 | cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23817 | cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23818 | cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23819 | cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23820 | |
| 23821 | cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23822 | cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23823 | cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23824 | cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23825 | cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23826 | cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23827 | cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23828 | cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23829 | cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23830 | cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23831 | cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23832 | cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23833 | |
| 23834 | cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23835 | cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23836 | cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23837 | cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23838 | cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23839 | cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23840 | cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23841 | cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23842 | cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23843 | cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23844 | cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23845 | cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23846 | |
| 23847 | cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23848 | cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23849 | cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23850 | cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23851 | cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23852 | cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23853 | cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23854 | cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23855 | cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23856 | cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23857 | cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23858 | cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23859 | |
| 23860 | cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23861 | cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23862 | cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23863 | cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23864 | cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23865 | cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23866 | cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23867 | cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23868 | cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23869 | cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23870 | cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23871 | cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23872 | |
| 23873 | cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23874 | cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23875 | cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23876 | cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23877 | cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23878 | cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23879 | cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23880 | cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23881 | cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23882 | cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23883 | cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23884 | cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23885 | |
| 23886 | cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23887 | cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23888 | cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23889 | cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23890 | cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23891 | cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23892 | cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23893 | cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23894 | cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23895 | cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23896 | cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23897 | cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23898 | |
| 23899 | cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23900 | cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23901 | cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23902 | cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23903 | cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23904 | cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23905 | cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23906 | cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23907 | cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23908 | cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23909 | cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23910 | cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23911 | |
| 23912 | cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23913 | cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23914 | cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23915 | cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23916 | cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23917 | cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23918 | cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23919 | cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23920 | cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23921 | cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23922 | cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23923 | cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23924 | |
| 23925 | cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23926 | cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23927 | cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23928 | cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23929 | cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23930 | cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23931 | cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23932 | cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23933 | cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23934 | cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23935 | cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23936 | cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23937 | |
| 23938 | cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23939 | cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23940 | cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23941 | cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23942 | cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23943 | cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23944 | cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23945 | cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23946 | cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23947 | cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23948 | cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23949 | cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), |
| 23950 | |
| 23951 | cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp), |
| 23952 | C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp), |
| 23953 | cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp), |
| 23954 | C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp), |
| 23955 | |
| 23956 | cCL("flts", e000110, 2, (RF, RR), rn_rd), |
| 23957 | cCL("fltsp", e000130, 2, (RF, RR), rn_rd), |
| 23958 | cCL("fltsm", e000150, 2, (RF, RR), rn_rd), |
| 23959 | cCL("fltsz", e000170, 2, (RF, RR), rn_rd), |
| 23960 | cCL("fltd", e000190, 2, (RF, RR), rn_rd), |
| 23961 | cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd), |
| 23962 | cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd), |
| 23963 | cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd), |
| 23964 | cCL("flte", e080110, 2, (RF, RR), rn_rd), |
| 23965 | cCL("fltep", e080130, 2, (RF, RR), rn_rd), |
| 23966 | cCL("fltem", e080150, 2, (RF, RR), rn_rd), |
| 23967 | cCL("fltez", e080170, 2, (RF, RR), rn_rd), |
| 23968 | |
| 23969 | /* The implementation of the FIX instruction is broken on some |
| 23970 | assemblers, in that it accepts a precision specifier as well as a |
| 23971 | rounding specifier, despite the fact that this is meaningless. |
| 23972 | To be more compatible, we accept it as well, though of course it |
| 23973 | does not set any bits. */ |
| 23974 | cCE("fix", e100110, 2, (RR, RF), rd_rm), |
| 23975 | cCL("fixp", e100130, 2, (RR, RF), rd_rm), |
| 23976 | cCL("fixm", e100150, 2, (RR, RF), rd_rm), |
| 23977 | cCL("fixz", e100170, 2, (RR, RF), rd_rm), |
| 23978 | cCL("fixsp", e100130, 2, (RR, RF), rd_rm), |
| 23979 | cCL("fixsm", e100150, 2, (RR, RF), rd_rm), |
| 23980 | cCL("fixsz", e100170, 2, (RR, RF), rd_rm), |
| 23981 | cCL("fixdp", e100130, 2, (RR, RF), rd_rm), |
| 23982 | cCL("fixdm", e100150, 2, (RR, RF), rd_rm), |
| 23983 | cCL("fixdz", e100170, 2, (RR, RF), rd_rm), |
| 23984 | cCL("fixep", e100130, 2, (RR, RF), rd_rm), |
| 23985 | cCL("fixem", e100150, 2, (RR, RF), rd_rm), |
| 23986 | cCL("fixez", e100170, 2, (RR, RF), rd_rm), |
| 23987 | |
| 23988 | /* Instructions that were new with the real FPA, call them V2. */ |
| 23989 | #undef ARM_VARIANT |
| 23990 | #define ARM_VARIANT & fpu_fpa_ext_v2 |
| 23991 | |
| 23992 | cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
| 23993 | cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
| 23994 | cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
| 23995 | cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
| 23996 | cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
| 23997 | cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
| 23998 | |
| 23999 | #undef ARM_VARIANT |
| 24000 | #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ |
| 24001 | |
| 24002 | /* Moves and type conversions. */ |
| 24003 | cCE("fmstat", ef1fa10, 0, (), noargs), |
| 24004 | cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs), |
| 24005 | cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr), |
| 24006 | cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), |
| 24007 | cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic), |
| 24008 | cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), |
| 24009 | cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), |
| 24010 | cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), |
| 24011 | cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), |
| 24012 | cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn), |
| 24013 | cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd), |
| 24014 | |
| 24015 | /* Memory operations. */ |
| 24016 | cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), |
| 24017 | cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), |
| 24018 | cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), |
| 24019 | cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), |
| 24020 | cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), |
| 24021 | cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), |
| 24022 | cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), |
| 24023 | cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), |
| 24024 | cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), |
| 24025 | cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), |
| 24026 | cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), |
| 24027 | cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), |
| 24028 | cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), |
| 24029 | cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), |
| 24030 | cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), |
| 24031 | cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), |
| 24032 | cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), |
| 24033 | cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), |
| 24034 | |
| 24035 | /* Monadic operations. */ |
| 24036 | cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), |
| 24037 | cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic), |
| 24038 | cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), |
| 24039 | |
| 24040 | /* Dyadic operations. */ |
| 24041 | cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
| 24042 | cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
| 24043 | cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
| 24044 | cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
| 24045 | cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
| 24046 | cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
| 24047 | cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
| 24048 | cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
| 24049 | cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
| 24050 | |
| 24051 | /* Comparisons. */ |
| 24052 | cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic), |
| 24053 | cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z), |
| 24054 | cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), |
| 24055 | cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z), |
| 24056 | |
| 24057 | /* Double precision load/store are still present on single precision |
| 24058 | implementations. */ |
| 24059 | cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), |
| 24060 | cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), |
| 24061 | cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), |
| 24062 | cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), |
| 24063 | cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), |
| 24064 | cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), |
| 24065 | cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), |
| 24066 | cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), |
| 24067 | cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), |
| 24068 | cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), |
| 24069 | |
| 24070 | #undef ARM_VARIANT |
| 24071 | #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ |
| 24072 | |
| 24073 | /* Moves and type conversions. */ |
| 24074 | cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), |
| 24075 | cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), |
| 24076 | cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd), |
| 24077 | cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd), |
| 24078 | cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn), |
| 24079 | cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn), |
| 24080 | cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), |
| 24081 | cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), |
| 24082 | cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), |
| 24083 | cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), |
| 24084 | cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), |
| 24085 | cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), |
| 24086 | |
| 24087 | /* Monadic operations. */ |
| 24088 | cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), |
| 24089 | cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
| 24090 | cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), |
| 24091 | |
| 24092 | /* Dyadic operations. */ |
| 24093 | cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
| 24094 | cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
| 24095 | cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
| 24096 | cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
| 24097 | cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
| 24098 | cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
| 24099 | cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
| 24100 | cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
| 24101 | cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
| 24102 | |
| 24103 | /* Comparisons. */ |
| 24104 | cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
| 24105 | cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd), |
| 24106 | cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), |
| 24107 | cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd), |
| 24108 | |
| 24109 | /* Instructions which may belong to either the Neon or VFP instruction sets. |
| 24110 | Individual encoder functions perform additional architecture checks. */ |
| 24111 | #undef ARM_VARIANT |
| 24112 | #define ARM_VARIANT & fpu_vfp_ext_v1xd |
| 24113 | #undef THUMB_VARIANT |
| 24114 | #define THUMB_VARIANT & fpu_vfp_ext_v1xd |
| 24115 | |
| 24116 | /* These mnemonics are unique to VFP. */ |
| 24117 | NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), |
| 24118 | NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), |
| 24119 | nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), |
| 24120 | nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), |
| 24121 | nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), |
| 24122 | NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), |
| 24123 | NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), |
| 24124 | NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), |
| 24125 | |
| 24126 | /* Mnemonics shared by Neon and VFP. */ |
| 24127 | nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), |
| 24128 | |
| 24129 | NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), |
| 24130 | NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), |
| 24131 | NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), |
| 24132 | NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), |
| 24133 | NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), |
| 24134 | NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), |
| 24135 | |
| 24136 | mnCEF(vcvt, _vcvt, 3, (RNSDQMQ, RNSDQMQ, oI32z), neon_cvt), |
| 24137 | nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr), |
| 24138 | MNCEF(vcvtb, eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtb), |
| 24139 | MNCEF(vcvtt, eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtt), |
| 24140 | |
| 24141 | |
| 24142 | /* NOTE: All VMOV encoding is special-cased! */ |
| 24143 | NCE(vmovq, 0, 1, (VMOV), neon_mov), |
| 24144 | |
| 24145 | #undef THUMB_VARIANT |
| 24146 | /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded |
| 24147 | by different feature bits. Since we are setting the Thumb guard, we can |
| 24148 | require Thumb-1 which makes it a nop guard and set the right feature bit in |
| 24149 | do_vldr_vstr (). */ |
| 24150 | #define THUMB_VARIANT & arm_ext_v4t |
| 24151 | NCE(vldr, d100b00, 2, (VLDR, ADDRGLDC), vldr_vstr), |
| 24152 | NCE(vstr, d000b00, 2, (VLDR, ADDRGLDC), vldr_vstr), |
| 24153 | |
| 24154 | #undef ARM_VARIANT |
| 24155 | #define ARM_VARIANT & arm_ext_fp16 |
| 24156 | #undef THUMB_VARIANT |
| 24157 | #define THUMB_VARIANT & arm_ext_fp16 |
| 24158 | /* New instructions added from v8.2, allowing the extraction and insertion of |
| 24159 | the upper 16 bits of a 32-bit vector register. */ |
| 24160 | NCE (vmovx, eb00a40, 2, (RVS, RVS), neon_movhf), |
| 24161 | NCE (vins, eb00ac0, 2, (RVS, RVS), neon_movhf), |
| 24162 | |
| 24163 | /* New backported fma/fms instructions optional in v8.2. */ |
| 24164 | NCE (vfmal, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmal), |
| 24165 | NCE (vfmsl, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmsl), |
| 24166 | |
| 24167 | #undef THUMB_VARIANT |
| 24168 | #define THUMB_VARIANT & fpu_neon_ext_v1 |
| 24169 | #undef ARM_VARIANT |
| 24170 | #define ARM_VARIANT & fpu_neon_ext_v1 |
| 24171 | |
| 24172 | /* Data processing with three registers of the same length. */ |
| 24173 | /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ |
| 24174 | NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), |
| 24175 | NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), |
| 24176 | NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), |
| 24177 | NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), |
| 24178 | NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), |
| 24179 | /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ |
| 24180 | NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), |
| 24181 | NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), |
| 24182 | NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), |
| 24183 | NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl), |
| 24184 | /* If not immediate, fall back to neon_dyadic_i64_su. |
| 24185 | shl_imm should accept I8 I16 I32 I64, |
| 24186 | qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */ |
| 24187 | nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm), |
| 24188 | nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm), |
| 24189 | nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm), |
| 24190 | nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm), |
| 24191 | /* Logic ops, types optional & ignored. */ |
| 24192 | nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), |
| 24193 | nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), |
| 24194 | nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), |
| 24195 | nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), |
| 24196 | nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic), |
| 24197 | /* Bitfield ops, untyped. */ |
| 24198 | NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), |
| 24199 | NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), |
| 24200 | NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), |
| 24201 | NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), |
| 24202 | NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), |
| 24203 | NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), |
| 24204 | /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */ |
| 24205 | nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), |
| 24206 | nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), |
| 24207 | nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), |
| 24208 | /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall |
| 24209 | back to neon_dyadic_if_su. */ |
| 24210 | nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), |
| 24211 | nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), |
| 24212 | nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), |
| 24213 | nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), |
| 24214 | nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), |
| 24215 | nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), |
| 24216 | nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), |
| 24217 | nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), |
| 24218 | /* Comparison. Type I8 I16 I32 F32. */ |
| 24219 | nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), |
| 24220 | nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), |
| 24221 | /* As above, D registers only. */ |
| 24222 | nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), |
| 24223 | nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), |
| 24224 | /* Int and float variants, signedness unimportant. */ |
| 24225 | nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), |
| 24226 | nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), |
| 24227 | nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), |
| 24228 | /* Add/sub take types I8 I16 I32 I64 F32. */ |
| 24229 | nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), |
| 24230 | nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), |
| 24231 | /* vtst takes sizes 8, 16, 32. */ |
| 24232 | NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), |
| 24233 | NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), |
| 24234 | /* VMUL takes I8 I16 I32 F32 P8. */ |
| 24235 | nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), |
| 24236 | /* VQD{R}MULH takes S16 S32. */ |
| 24237 | nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), |
| 24238 | nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), |
| 24239 | NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), |
| 24240 | NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), |
| 24241 | NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), |
| 24242 | NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), |
| 24243 | NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), |
| 24244 | NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), |
| 24245 | NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), |
| 24246 | NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), |
| 24247 | NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), |
| 24248 | NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), |
| 24249 | NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), |
| 24250 | NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), |
| 24251 | /* ARM v8.1 extension. */ |
| 24252 | nUF (vqrdmlahq, _vqrdmlah, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah), |
| 24253 | nUF (vqrdmlsh, _vqrdmlsh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah), |
| 24254 | nUF (vqrdmlshq, _vqrdmlsh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah), |
| 24255 | |
| 24256 | /* Two address, int/float. Types S8 S16 S32 F32. */ |
| 24257 | NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), |
| 24258 | NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), |
| 24259 | |
| 24260 | /* Data processing with two registers and a shift amount. */ |
| 24261 | /* Right shifts, and variants with rounding. |
| 24262 | Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ |
| 24263 | NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), |
| 24264 | NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), |
| 24265 | NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), |
| 24266 | NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), |
| 24267 | NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), |
| 24268 | NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), |
| 24269 | NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), |
| 24270 | NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), |
| 24271 | /* Shift and insert. Sizes accepted 8 16 32 64. */ |
| 24272 | NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli), |
| 24273 | NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), |
| 24274 | NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri), |
| 24275 | NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), |
| 24276 | /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ |
| 24277 | NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm), |
| 24278 | NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), |
| 24279 | /* Right shift immediate, saturating & narrowing, with rounding variants. |
| 24280 | Types accepted S16 S32 S64 U16 U32 U64. */ |
| 24281 | NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), |
| 24282 | NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), |
| 24283 | /* As above, unsigned. Types accepted S16 S32 S64. */ |
| 24284 | NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), |
| 24285 | NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), |
| 24286 | /* Right shift narrowing. Types accepted I16 I32 I64. */ |
| 24287 | NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), |
| 24288 | NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), |
| 24289 | /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ |
| 24290 | nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll), |
| 24291 | /* CVT with optional immediate for fixed-point variant. */ |
| 24292 | nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), |
| 24293 | |
| 24294 | nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn), |
| 24295 | |
| 24296 | /* Data processing, three registers of different lengths. */ |
| 24297 | /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ |
| 24298 | NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), |
| 24299 | /* If not scalar, fall back to neon_dyadic_long. |
| 24300 | Vector types as above, scalar types S16 S32 U16 U32. */ |
| 24301 | nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), |
| 24302 | nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), |
| 24303 | /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ |
| 24304 | NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), |
| 24305 | NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), |
| 24306 | /* Dyadic, narrowing insns. Types I16 I32 I64. */ |
| 24307 | NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), |
| 24308 | NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), |
| 24309 | NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), |
| 24310 | NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), |
| 24311 | /* Saturating doubling multiplies. Types S16 S32. */ |
| 24312 | nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), |
| 24313 | nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), |
| 24314 | nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), |
| 24315 | /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types |
| 24316 | S16 S32 U16 U32. */ |
| 24317 | nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), |
| 24318 | |
| 24319 | /* Extract. Size 8. */ |
| 24320 | NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext), |
| 24321 | NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext), |
| 24322 | |
| 24323 | /* Two registers, miscellaneous. */ |
| 24324 | /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ |
| 24325 | NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev), |
| 24326 | NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), |
| 24327 | NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev), |
| 24328 | NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), |
| 24329 | NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev), |
| 24330 | NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), |
| 24331 | /* Vector replicate. Sizes 8 16 32. */ |
| 24332 | nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup), |
| 24333 | /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ |
| 24334 | NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), |
| 24335 | /* VMOVN. Types I16 I32 I64. */ |
| 24336 | nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn), |
| 24337 | /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ |
| 24338 | nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn), |
| 24339 | /* VQMOVUN. Types S16 S32 S64. */ |
| 24340 | nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun), |
| 24341 | /* VZIP / VUZP. Sizes 8 16 32. */ |
| 24342 | NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), |
| 24343 | NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), |
| 24344 | NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), |
| 24345 | NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), |
| 24346 | /* VQABS / VQNEG. Types S8 S16 S32. */ |
| 24347 | NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), |
| 24348 | NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), |
| 24349 | /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ |
| 24350 | NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), |
| 24351 | NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), |
| 24352 | NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), |
| 24353 | NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), |
| 24354 | /* Reciprocal estimates. Types U32 F16 F32. */ |
| 24355 | NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), |
| 24356 | NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), |
| 24357 | NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), |
| 24358 | NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), |
| 24359 | /* VCLS. Types S8 S16 S32. */ |
| 24360 | NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), |
| 24361 | /* VCLZ. Types I8 I16 I32. */ |
| 24362 | NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), |
| 24363 | /* VCNT. Size 8. */ |
| 24364 | NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), |
| 24365 | NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), |
| 24366 | /* Two address, untyped. */ |
| 24367 | NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), |
| 24368 | NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), |
| 24369 | /* VTRN. Sizes 8 16 32. */ |
| 24370 | nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn), |
| 24371 | nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn), |
| 24372 | |
| 24373 | /* Table lookup. Size 8. */ |
| 24374 | NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), |
| 24375 | NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), |
| 24376 | |
| 24377 | #undef THUMB_VARIANT |
| 24378 | #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext |
| 24379 | #undef ARM_VARIANT |
| 24380 | #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext |
| 24381 | |
| 24382 | /* Neon element/structure load/store. */ |
| 24383 | nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), |
| 24384 | nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), |
| 24385 | nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), |
| 24386 | nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), |
| 24387 | nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), |
| 24388 | nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), |
| 24389 | nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), |
| 24390 | nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), |
| 24391 | |
| 24392 | #undef THUMB_VARIANT |
| 24393 | #define THUMB_VARIANT & fpu_vfp_ext_v3xd |
| 24394 | #undef ARM_VARIANT |
| 24395 | #define ARM_VARIANT & fpu_vfp_ext_v3xd |
| 24396 | cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const), |
| 24397 | cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), |
| 24398 | cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), |
| 24399 | cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), |
| 24400 | cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), |
| 24401 | cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), |
| 24402 | cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), |
| 24403 | cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), |
| 24404 | cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), |
| 24405 | |
| 24406 | #undef THUMB_VARIANT |
| 24407 | #define THUMB_VARIANT & fpu_vfp_ext_v3 |
| 24408 | #undef ARM_VARIANT |
| 24409 | #define ARM_VARIANT & fpu_vfp_ext_v3 |
| 24410 | |
| 24411 | cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const), |
| 24412 | cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
| 24413 | cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
| 24414 | cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
| 24415 | cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
| 24416 | cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
| 24417 | cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
| 24418 | cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
| 24419 | cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
| 24420 | |
| 24421 | #undef ARM_VARIANT |
| 24422 | #define ARM_VARIANT & fpu_vfp_ext_fma |
| 24423 | #undef THUMB_VARIANT |
| 24424 | #define THUMB_VARIANT & fpu_vfp_ext_fma |
| 24425 | /* Mnemonics shared by Neon, VFP and MVE. These are included in the |
| 24426 | VFP FMA variant; NEON and VFP FMA always includes the NEON |
| 24427 | FMA instructions. */ |
| 24428 | mnCEF(vfma, _vfma, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_fmac), |
| 24429 | mnCEF(vfms, _vfms, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), neon_fmac), |
| 24430 | |
| 24431 | /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas; |
| 24432 | the v form should always be used. */ |
| 24433 | cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
| 24434 | cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
| 24435 | cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
| 24436 | cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
| 24437 | nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), |
| 24438 | nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), |
| 24439 | |
| 24440 | #undef THUMB_VARIANT |
| 24441 | #undef ARM_VARIANT |
| 24442 | #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */ |
| 24443 | |
| 24444 | cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
| 24445 | cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
| 24446 | cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
| 24447 | cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
| 24448 | cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
| 24449 | cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
| 24450 | cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), |
| 24451 | cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), |
| 24452 | |
| 24453 | #undef ARM_VARIANT |
| 24454 | #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */ |
| 24455 | |
| 24456 | cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc), |
| 24457 | cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc), |
| 24458 | cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc), |
| 24459 | cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd), |
| 24460 | cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd), |
| 24461 | cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd), |
| 24462 | cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc), |
| 24463 | cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc), |
| 24464 | cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc), |
| 24465 | cCE("textrmub",e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), |
| 24466 | cCE("textrmuh",e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), |
| 24467 | cCE("textrmuw",e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), |
| 24468 | cCE("textrmsb",e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), |
| 24469 | cCE("textrmsh",e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), |
| 24470 | cCE("textrmsw",e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), |
| 24471 | cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), |
| 24472 | cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), |
| 24473 | cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), |
| 24474 | cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd), |
| 24475 | cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn), |
| 24476 | cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), |
| 24477 | cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), |
| 24478 | cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), |
| 24479 | cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), |
| 24480 | cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), |
| 24481 | cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), |
| 24482 | cCE("tmovmskb",e100030, 2, (RR, RIWR), rd_rn), |
| 24483 | cCE("tmovmskh",e500030, 2, (RR, RIWR), rd_rn), |
| 24484 | cCE("tmovmskw",e900030, 2, (RR, RIWR), rd_rn), |
| 24485 | cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn), |
| 24486 | cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm), |
| 24487 | cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc), |
| 24488 | cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc), |
| 24489 | cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc), |
| 24490 | cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn), |
| 24491 | cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn), |
| 24492 | cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn), |
| 24493 | cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24494 | cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24495 | cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24496 | cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24497 | cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24498 | cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24499 | cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24500 | cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24501 | cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24502 | cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), |
| 24503 | cCE("walignr0",e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24504 | cCE("walignr1",e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24505 | cCE("walignr2",ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24506 | cCE("walignr3",eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24507 | cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24508 | cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24509 | cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24510 | cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24511 | cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24512 | cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24513 | cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24514 | cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24515 | cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24516 | cCE("wcmpgtub",e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24517 | cCE("wcmpgtuh",e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24518 | cCE("wcmpgtuw",e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24519 | cCE("wcmpgtsb",e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24520 | cCE("wcmpgtsh",e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24521 | cCE("wcmpgtsw",eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24522 | cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), |
| 24523 | cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), |
| 24524 | cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), |
| 24525 | cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), |
| 24526 | cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24527 | cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24528 | cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24529 | cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24530 | cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24531 | cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24532 | cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24533 | cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24534 | cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24535 | cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24536 | cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24537 | cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24538 | cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24539 | cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24540 | cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24541 | cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24542 | cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24543 | cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24544 | cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov), |
| 24545 | cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24546 | cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24547 | cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24548 | cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24549 | cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24550 | cCE("wpackhss",e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24551 | cCE("wpackhus",e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24552 | cCE("wpackwss",eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24553 | cCE("wpackwus",e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24554 | cCE("wpackdss",ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24555 | cCE("wpackdus",ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24556 | cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
| 24557 | cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), |
| 24558 | cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
| 24559 | cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), |
| 24560 | cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
| 24561 | cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), |
| 24562 | cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24563 | cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24564 | cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24565 | cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24566 | cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), |
| 24567 | cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
| 24568 | cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), |
| 24569 | cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
| 24570 | cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), |
| 24571 | cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
| 24572 | cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), |
| 24573 | cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
| 24574 | cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), |
| 24575 | cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
| 24576 | cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), |
| 24577 | cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
| 24578 | cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), |
| 24579 | cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
| 24580 | cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), |
| 24581 | cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
| 24582 | cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), |
| 24583 | cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
| 24584 | cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), |
| 24585 | cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), |
| 24586 | cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), |
| 24587 | cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), |
| 24588 | cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), |
| 24589 | cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24590 | cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24591 | cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24592 | cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24593 | cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24594 | cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24595 | cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24596 | cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24597 | cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24598 | cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn), |
| 24599 | cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn), |
| 24600 | cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn), |
| 24601 | cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn), |
| 24602 | cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn), |
| 24603 | cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn), |
| 24604 | cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24605 | cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24606 | cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24607 | cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn), |
| 24608 | cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn), |
| 24609 | cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn), |
| 24610 | cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn), |
| 24611 | cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn), |
| 24612 | cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn), |
| 24613 | cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24614 | cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24615 | cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24616 | cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24617 | cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero), |
| 24618 | |
| 24619 | #undef ARM_VARIANT |
| 24620 | #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */ |
| 24621 | |
| 24622 | cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc), |
| 24623 | cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc), |
| 24624 | cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc), |
| 24625 | cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn), |
| 24626 | cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn), |
| 24627 | cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn), |
| 24628 | cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24629 | cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24630 | cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24631 | cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24632 | cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24633 | cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24634 | cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24635 | cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24636 | cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24637 | cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24638 | cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24639 | cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24640 | cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24641 | cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24642 | cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge), |
| 24643 | cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24644 | cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24645 | cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24646 | cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24647 | cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24648 | cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24649 | cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24650 | cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24651 | cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24652 | cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24653 | cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24654 | cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24655 | cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24656 | cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24657 | cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24658 | cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24659 | cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24660 | cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24661 | cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24662 | cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24663 | cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24664 | cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24665 | cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24666 | cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24667 | cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24668 | cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24669 | cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24670 | cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24671 | cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24672 | cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24673 | cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24674 | cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24675 | cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24676 | cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24677 | cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24678 | cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
| 24679 | |
| 24680 | #undef ARM_VARIANT |
| 24681 | #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */ |
| 24682 | |
| 24683 | cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), |
| 24684 | cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), |
| 24685 | cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), |
| 24686 | cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), |
| 24687 | cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), |
| 24688 | cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), |
| 24689 | cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), |
| 24690 | cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), |
| 24691 | cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd), |
| 24692 | cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn), |
| 24693 | cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd), |
| 24694 | cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn), |
| 24695 | cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd), |
| 24696 | cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn), |
| 24697 | cCE("cfmv64lr",e000510, 2, (RMDX, RR), rn_rd), |
| 24698 | cCE("cfmvr64l",e100510, 2, (RR, RMDX), rd_rn), |
| 24699 | cCE("cfmv64hr",e000530, 2, (RMDX, RR), rn_rd), |
| 24700 | cCE("cfmvr64h",e100530, 2, (RR, RMDX), rd_rn), |
| 24701 | cCE("cfmval32",e200440, 2, (RMAX, RMFX), rd_rn), |
| 24702 | cCE("cfmv32al",e100440, 2, (RMFX, RMAX), rd_rn), |
| 24703 | cCE("cfmvam32",e200460, 2, (RMAX, RMFX), rd_rn), |
| 24704 | cCE("cfmv32am",e100460, 2, (RMFX, RMAX), rd_rn), |
| 24705 | cCE("cfmvah32",e200480, 2, (RMAX, RMFX), rd_rn), |
| 24706 | cCE("cfmv32ah",e100480, 2, (RMFX, RMAX), rd_rn), |
| 24707 | cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn), |
| 24708 | cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn), |
| 24709 | cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn), |
| 24710 | cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn), |
| 24711 | cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX), mav_dspsc), |
| 24712 | cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS), rd), |
| 24713 | cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn), |
| 24714 | cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn), |
| 24715 | cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn), |
| 24716 | cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn), |
| 24717 | cCE("cfcvt32s",e000480, 2, (RMF, RMFX), rd_rn), |
| 24718 | cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX), rd_rn), |
| 24719 | cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX), rd_rn), |
| 24720 | cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX), rd_rn), |
| 24721 | cCE("cfcvts32",e100580, 2, (RMFX, RMF), rd_rn), |
| 24722 | cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD), rd_rn), |
| 24723 | cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn), |
| 24724 | cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn), |
| 24725 | cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR), mav_triple), |
| 24726 | cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR), mav_triple), |
| 24727 | cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift), |
| 24728 | cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift), |
| 24729 | cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm), |
| 24730 | cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), |
| 24731 | cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), |
| 24732 | cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), |
| 24733 | cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn), |
| 24734 | cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn), |
| 24735 | cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn), |
| 24736 | cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn), |
| 24737 | cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm), |
| 24738 | cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), |
| 24739 | cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), |
| 24740 | cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), |
| 24741 | cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm), |
| 24742 | cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm), |
| 24743 | cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn), |
| 24744 | cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn), |
| 24745 | cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn), |
| 24746 | cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn), |
| 24747 | cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), |
| 24748 | cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), |
| 24749 | cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), |
| 24750 | cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), |
| 24751 | cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), |
| 24752 | cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), |
| 24753 | cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), |
| 24754 | cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), |
| 24755 | cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), |
| 24756 | cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), |
| 24757 | cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), |
| 24758 | cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), |
| 24759 | |
| 24760 | /* ARMv8.5-A instructions. */ |
| 24761 | #undef ARM_VARIANT |
| 24762 | #define ARM_VARIANT & arm_ext_sb |
| 24763 | #undef THUMB_VARIANT |
| 24764 | #define THUMB_VARIANT & arm_ext_sb |
| 24765 | TUF("sb", 57ff070, f3bf8f70, 0, (), noargs, noargs), |
| 24766 | |
| 24767 | #undef ARM_VARIANT |
| 24768 | #define ARM_VARIANT & arm_ext_predres |
| 24769 | #undef THUMB_VARIANT |
| 24770 | #define THUMB_VARIANT & arm_ext_predres |
| 24771 | CE("cfprctx", e070f93, 1, (RRnpc), rd), |
| 24772 | CE("dvprctx", e070fb3, 1, (RRnpc), rd), |
| 24773 | CE("cpprctx", e070ff3, 1, (RRnpc), rd), |
| 24774 | |
| 24775 | /* ARMv8-M instructions. */ |
| 24776 | #undef ARM_VARIANT |
| 24777 | #define ARM_VARIANT NULL |
| 24778 | #undef THUMB_VARIANT |
| 24779 | #define THUMB_VARIANT & arm_ext_v8m |
| 24780 | ToU("sg", e97fe97f, 0, (), noargs), |
| 24781 | ToC("blxns", 4784, 1, (RRnpc), t_blx), |
| 24782 | ToC("bxns", 4704, 1, (RRnpc), t_bx), |
| 24783 | ToC("tt", e840f000, 2, (RRnpc, RRnpc), tt), |
| 24784 | ToC("ttt", e840f040, 2, (RRnpc, RRnpc), tt), |
| 24785 | ToC("tta", e840f080, 2, (RRnpc, RRnpc), tt), |
| 24786 | ToC("ttat", e840f0c0, 2, (RRnpc, RRnpc), tt), |
| 24787 | |
| 24788 | /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the |
| 24789 | instructions behave as nop if no VFP is present. */ |
| 24790 | #undef THUMB_VARIANT |
| 24791 | #define THUMB_VARIANT & arm_ext_v8m_main |
| 24792 | ToC("vlldm", ec300a00, 1, (RRnpc), rn), |
| 24793 | ToC("vlstm", ec200a00, 1, (RRnpc), rn), |
| 24794 | |
| 24795 | /* Armv8.1-M Mainline instructions. */ |
| 24796 | #undef THUMB_VARIANT |
| 24797 | #define THUMB_VARIANT & arm_ext_v8_1m_main |
| 24798 | toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future), |
| 24799 | toU("bfcsel", _bfcsel, 4, (EXPs, EXPs, EXPs, COND), t_branch_future), |
| 24800 | toC("bfx", _bfx, 2, (EXPs, RRnpcsp), t_branch_future), |
| 24801 | toC("bfl", _bfl, 2, (EXPs, EXPs), t_branch_future), |
| 24802 | toC("bflx", _bflx, 2, (EXPs, RRnpcsp), t_branch_future), |
| 24803 | |
| 24804 | toU("dls", _dls, 2, (LR, RRnpcsp), t_loloop), |
| 24805 | toU("wls", _wls, 3, (LR, RRnpcsp, EXP), t_loloop), |
| 24806 | toU("le", _le, 2, (oLR, EXP), t_loloop), |
| 24807 | |
| 24808 | ToC("clrm", e89f0000, 1, (CLRMLST), t_clrm), |
| 24809 | ToC("vscclrm", ec9f0a00, 1, (VRSDVLST), t_vscclrm), |
| 24810 | |
| 24811 | #undef THUMB_VARIANT |
| 24812 | #define THUMB_VARIANT & mve_ext |
| 24813 | |
| 24814 | ToC("vpt", ee410f00, 3, (COND, RMQ, RMQRZ), mve_vpt), |
| 24815 | ToC("vptt", ee018f00, 3, (COND, RMQ, RMQRZ), mve_vpt), |
| 24816 | ToC("vpte", ee418f00, 3, (COND, RMQ, RMQRZ), mve_vpt), |
| 24817 | ToC("vpttt", ee014f00, 3, (COND, RMQ, RMQRZ), mve_vpt), |
| 24818 | ToC("vptte", ee01cf00, 3, (COND, RMQ, RMQRZ), mve_vpt), |
| 24819 | ToC("vptet", ee41cf00, 3, (COND, RMQ, RMQRZ), mve_vpt), |
| 24820 | ToC("vptee", ee414f00, 3, (COND, RMQ, RMQRZ), mve_vpt), |
| 24821 | ToC("vptttt", ee012f00, 3, (COND, RMQ, RMQRZ), mve_vpt), |
| 24822 | ToC("vpttte", ee016f00, 3, (COND, RMQ, RMQRZ), mve_vpt), |
| 24823 | ToC("vpttet", ee01ef00, 3, (COND, RMQ, RMQRZ), mve_vpt), |
| 24824 | ToC("vpttee", ee01af00, 3, (COND, RMQ, RMQRZ), mve_vpt), |
| 24825 | ToC("vptett", ee41af00, 3, (COND, RMQ, RMQRZ), mve_vpt), |
| 24826 | ToC("vptete", ee41ef00, 3, (COND, RMQ, RMQRZ), mve_vpt), |
| 24827 | ToC("vpteet", ee416f00, 3, (COND, RMQ, RMQRZ), mve_vpt), |
| 24828 | ToC("vpteee", ee412f00, 3, (COND, RMQ, RMQRZ), mve_vpt), |
| 24829 | |
| 24830 | ToC("vpst", fe710f4d, 0, (), mve_vpt), |
| 24831 | ToC("vpstt", fe318f4d, 0, (), mve_vpt), |
| 24832 | ToC("vpste", fe718f4d, 0, (), mve_vpt), |
| 24833 | ToC("vpsttt", fe314f4d, 0, (), mve_vpt), |
| 24834 | ToC("vpstte", fe31cf4d, 0, (), mve_vpt), |
| 24835 | ToC("vpstet", fe71cf4d, 0, (), mve_vpt), |
| 24836 | ToC("vpstee", fe714f4d, 0, (), mve_vpt), |
| 24837 | ToC("vpstttt", fe312f4d, 0, (), mve_vpt), |
| 24838 | ToC("vpsttte", fe316f4d, 0, (), mve_vpt), |
| 24839 | ToC("vpsttet", fe31ef4d, 0, (), mve_vpt), |
| 24840 | ToC("vpsttee", fe31af4d, 0, (), mve_vpt), |
| 24841 | ToC("vpstett", fe71af4d, 0, (), mve_vpt), |
| 24842 | ToC("vpstete", fe71ef4d, 0, (), mve_vpt), |
| 24843 | ToC("vpsteet", fe716f4d, 0, (), mve_vpt), |
| 24844 | ToC("vpsteee", fe712f4d, 0, (), mve_vpt), |
| 24845 | |
| 24846 | /* MVE and MVE FP only. */ |
| 24847 | mToC("vhcadd", ee000f00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vhcadd), |
| 24848 | mCEF(vadc, _vadc, 3, (RMQ, RMQ, RMQ), mve_vadc), |
| 24849 | mCEF(vadci, _vadci, 3, (RMQ, RMQ, RMQ), mve_vadc), |
| 24850 | mToC("vsbc", fe300f00, 3, (RMQ, RMQ, RMQ), mve_vsbc), |
| 24851 | mToC("vsbci", fe301f00, 3, (RMQ, RMQ, RMQ), mve_vsbc), |
| 24852 | mCEF(vmullb, _vmullb, 3, (RMQ, RMQ, RMQ), mve_vmull), |
| 24853 | mCEF(vabav, _vabav, 3, (RRnpcsp, RMQ, RMQ), mve_vabav), |
| 24854 | mCEF(vmladav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav), |
| 24855 | mCEF(vmladava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav), |
| 24856 | mCEF(vmladavx, _vmladavx, 3, (RRe, RMQ, RMQ), mve_vmladav), |
| 24857 | mCEF(vmladavax, _vmladavax, 3, (RRe, RMQ, RMQ), mve_vmladav), |
| 24858 | mCEF(vmlav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav), |
| 24859 | mCEF(vmlava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav), |
| 24860 | mCEF(vmlsdav, _vmlsdav, 3, (RRe, RMQ, RMQ), mve_vmladav), |
| 24861 | mCEF(vmlsdava, _vmlsdava, 3, (RRe, RMQ, RMQ), mve_vmladav), |
| 24862 | mCEF(vmlsdavx, _vmlsdavx, 3, (RRe, RMQ, RMQ), mve_vmladav), |
| 24863 | mCEF(vmlsdavax, _vmlsdavax, 3, (RRe, RMQ, RMQ), mve_vmladav), |
| 24864 | |
| 24865 | mCEF(vst20, _vst20, 2, (MSTRLST2, ADDRMVE), mve_vst_vld), |
| 24866 | mCEF(vst21, _vst21, 2, (MSTRLST2, ADDRMVE), mve_vst_vld), |
| 24867 | mCEF(vst40, _vst40, 2, (MSTRLST4, ADDRMVE), mve_vst_vld), |
| 24868 | mCEF(vst41, _vst41, 2, (MSTRLST4, ADDRMVE), mve_vst_vld), |
| 24869 | mCEF(vst42, _vst42, 2, (MSTRLST4, ADDRMVE), mve_vst_vld), |
| 24870 | mCEF(vst43, _vst43, 2, (MSTRLST4, ADDRMVE), mve_vst_vld), |
| 24871 | mCEF(vld20, _vld20, 2, (MSTRLST2, ADDRMVE), mve_vst_vld), |
| 24872 | mCEF(vld21, _vld21, 2, (MSTRLST2, ADDRMVE), mve_vst_vld), |
| 24873 | mCEF(vld40, _vld40, 2, (MSTRLST4, ADDRMVE), mve_vst_vld), |
| 24874 | mCEF(vld41, _vld41, 2, (MSTRLST4, ADDRMVE), mve_vst_vld), |
| 24875 | mCEF(vld42, _vld42, 2, (MSTRLST4, ADDRMVE), mve_vst_vld), |
| 24876 | mCEF(vld43, _vld43, 2, (MSTRLST4, ADDRMVE), mve_vst_vld), |
| 24877 | mCEF(vstrb, _vstrb, 2, (RMQ, ADDRMVE), mve_vstr_vldr), |
| 24878 | mCEF(vstrh, _vstrh, 2, (RMQ, ADDRMVE), mve_vstr_vldr), |
| 24879 | mCEF(vstrw, _vstrw, 2, (RMQ, ADDRMVE), mve_vstr_vldr), |
| 24880 | mCEF(vstrd, _vstrd, 2, (RMQ, ADDRMVE), mve_vstr_vldr), |
| 24881 | mCEF(vldrb, _vldrb, 2, (RMQ, ADDRMVE), mve_vstr_vldr), |
| 24882 | mCEF(vldrh, _vldrh, 2, (RMQ, ADDRMVE), mve_vstr_vldr), |
| 24883 | mCEF(vldrw, _vldrw, 2, (RMQ, ADDRMVE), mve_vstr_vldr), |
| 24884 | mCEF(vldrd, _vldrd, 2, (RMQ, ADDRMVE), mve_vstr_vldr), |
| 24885 | |
| 24886 | mCEF(vmovnt, _vmovnt, 2, (RMQ, RMQ), mve_movn), |
| 24887 | mCEF(vmovnb, _vmovnb, 2, (RMQ, RMQ), mve_movn), |
| 24888 | mCEF(vbrsr, _vbrsr, 3, (RMQ, RMQ, RR), mve_vbrsr), |
| 24889 | mCEF(vaddlv, _vaddlv, 3, (RRe, RRo, RMQ), mve_vaddlv), |
| 24890 | mCEF(vaddlva, _vaddlva, 3, (RRe, RRo, RMQ), mve_vaddlv), |
| 24891 | mCEF(vaddv, _vaddv, 2, (RRe, RMQ), mve_vaddv), |
| 24892 | mCEF(vaddva, _vaddva, 2, (RRe, RMQ), mve_vaddv), |
| 24893 | mCEF(vddup, _vddup, 3, (RMQ, RRe, EXPi), mve_viddup), |
| 24894 | mCEF(vdwdup, _vdwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup), |
| 24895 | mCEF(vidup, _vidup, 3, (RMQ, RRe, EXPi), mve_viddup), |
| 24896 | mCEF(viwdup, _viwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup), |
| 24897 | mToC("vmaxa", ee330e81, 2, (RMQ, RMQ), mve_vmaxa_vmina), |
| 24898 | mToC("vmina", ee331e81, 2, (RMQ, RMQ), mve_vmaxa_vmina), |
| 24899 | mCEF(vmaxv, _vmaxv, 2, (RR, RMQ), mve_vmaxv), |
| 24900 | mCEF(vmaxav, _vmaxav, 2, (RR, RMQ), mve_vmaxv), |
| 24901 | mCEF(vminv, _vminv, 2, (RR, RMQ), mve_vmaxv), |
| 24902 | mCEF(vminav, _vminav, 2, (RR, RMQ), mve_vmaxv), |
| 24903 | |
| 24904 | mCEF(vmlaldav, _vmlaldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), |
| 24905 | mCEF(vmlaldava, _vmlaldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), |
| 24906 | mCEF(vmlaldavx, _vmlaldavx, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), |
| 24907 | mCEF(vmlaldavax, _vmlaldavax, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), |
| 24908 | mCEF(vmlalv, _vmlaldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), |
| 24909 | mCEF(vmlalva, _vmlaldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), |
| 24910 | mCEF(vmlsldav, _vmlsldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), |
| 24911 | mCEF(vmlsldava, _vmlsldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), |
| 24912 | mCEF(vmlsldavx, _vmlsldavx, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), |
| 24913 | mCEF(vmlsldavax, _vmlsldavax, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), |
| 24914 | mToC("vrmlaldavh", ee800f00, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), |
| 24915 | mToC("vrmlaldavha",ee800f20, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), |
| 24916 | mCEF(vrmlaldavhx, _vrmlaldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), |
| 24917 | mCEF(vrmlaldavhax, _vrmlaldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), |
| 24918 | mToC("vrmlalvh", ee800f00, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), |
| 24919 | mToC("vrmlalvha", ee800f20, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), |
| 24920 | mCEF(vrmlsldavh, _vrmlsldavh, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), |
| 24921 | mCEF(vrmlsldavha, _vrmlsldavha, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), |
| 24922 | mCEF(vrmlsldavhx, _vrmlsldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), |
| 24923 | mCEF(vrmlsldavhax, _vrmlsldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), |
| 24924 | |
| 24925 | mToC("vmlas", ee011e40, 3, (RMQ, RMQ, RR), mve_vmlas), |
| 24926 | mToC("vmulh", ee010e01, 3, (RMQ, RMQ, RMQ), mve_vmulh), |
| 24927 | mToC("vrmulh", ee011e01, 3, (RMQ, RMQ, RMQ), mve_vmulh), |
| 24928 | mToC("vpnot", fe310f4d, 0, (), mve_vpnot), |
| 24929 | mToC("vpsel", fe310f01, 3, (RMQ, RMQ, RMQ), mve_vpsel), |
| 24930 | |
| 24931 | mToC("vqdmladh", ee000e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh), |
| 24932 | mToC("vqdmladhx", ee001e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh), |
| 24933 | mToC("vqrdmladh", ee000e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh), |
| 24934 | mToC("vqrdmladhx",ee001e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh), |
| 24935 | mToC("vqdmlsdh", fe000e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh), |
| 24936 | mToC("vqdmlsdhx", fe001e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh), |
| 24937 | mToC("vqrdmlsdh", fe000e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh), |
| 24938 | mToC("vqrdmlsdhx",fe001e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh), |
| 24939 | mToC("vqdmlah", ee000e60, 3, (RMQ, RMQ, RR), mve_vqdmlah), |
| 24940 | mToC("vqdmlash", ee001e60, 3, (RMQ, RMQ, RR), mve_vqdmlah), |
| 24941 | mToC("vqrdmlash", ee001e40, 3, (RMQ, RMQ, RR), mve_vqdmlah), |
| 24942 | mToC("vqdmullt", ee301f00, 3, (RMQ, RMQ, RMQRR), mve_vqdmull), |
| 24943 | mToC("vqdmullb", ee300f00, 3, (RMQ, RMQ, RMQRR), mve_vqdmull), |
| 24944 | mCEF(vqmovnt, _vqmovnt, 2, (RMQ, RMQ), mve_vqmovn), |
| 24945 | mCEF(vqmovnb, _vqmovnb, 2, (RMQ, RMQ), mve_vqmovn), |
| 24946 | mCEF(vqmovunt, _vqmovunt, 2, (RMQ, RMQ), mve_vqmovn), |
| 24947 | mCEF(vqmovunb, _vqmovunb, 2, (RMQ, RMQ), mve_vqmovn), |
| 24948 | |
| 24949 | #undef THUMB_VARIANT |
| 24950 | #define THUMB_VARIANT & mve_fp_ext |
| 24951 | mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul), |
| 24952 | mToC("vfmas", ee311e40, 3, (RMQ, RMQ, RR), mve_vfmas), |
| 24953 | mToC("vmaxnma", ee3f0e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma), |
| 24954 | mToC("vminnma", ee3f1e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma), |
| 24955 | mToC("vmaxnmv", eeee0f00, 2, (RR, RMQ), mve_vmaxnmv), |
| 24956 | mToC("vmaxnmav",eeec0f00, 2, (RR, RMQ), mve_vmaxnmv), |
| 24957 | mToC("vminnmv", eeee0f80, 2, (RR, RMQ), mve_vmaxnmv), |
| 24958 | mToC("vminnmav",eeec0f80, 2, (RR, RMQ), mve_vmaxnmv), |
| 24959 | |
| 24960 | #undef ARM_VARIANT |
| 24961 | #define ARM_VARIANT & fpu_vfp_ext_v1 |
| 24962 | #undef THUMB_VARIANT |
| 24963 | #define THUMB_VARIANT & arm_ext_v6t2 |
| 24964 | mnCEF(vmla, _vmla, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mac_maybe_scalar), |
| 24965 | mnCEF(vmul, _vmul, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mul), |
| 24966 | |
| 24967 | mcCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
| 24968 | |
| 24969 | #undef ARM_VARIANT |
| 24970 | #define ARM_VARIANT & fpu_vfp_ext_v1xd |
| 24971 | |
| 24972 | MNCE(vmov, 0, 1, (VMOV), neon_mov), |
| 24973 | mcCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp), |
| 24974 | mcCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg), |
| 24975 | mcCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic), |
| 24976 | |
| 24977 | mCEF(vmullt, _vmullt, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ), mve_vmull), |
| 24978 | mnCEF(vadd, _vadd, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i), |
| 24979 | mnCEF(vsub, _vsub, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i), |
| 24980 | |
| 24981 | MNCEF(vabs, 1b10300, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg), |
| 24982 | MNCEF(vneg, 1b10380, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg), |
| 24983 | |
| 24984 | mCEF(vmovlt, _vmovlt, 1, (VMOV), mve_movl), |
| 24985 | mCEF(vmovlb, _vmovlb, 1, (VMOV), mve_movl), |
| 24986 | |
| 24987 | mnCE(vcmp, _vcmp, 3, (RVSD_COND, RSVDMQ_FI0, oRMQRZ), vfp_nsyn_cmp), |
| 24988 | mnCE(vcmpe, _vcmpe, 3, (RVSD_COND, RSVDMQ_FI0, oRMQRZ), vfp_nsyn_cmp), |
| 24989 | |
| 24990 | #undef ARM_VARIANT |
| 24991 | #define ARM_VARIANT & fpu_vfp_ext_v2 |
| 24992 | |
| 24993 | mcCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), |
| 24994 | mcCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), |
| 24995 | mcCE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), |
| 24996 | mcCE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), |
| 24997 | |
| 24998 | #undef ARM_VARIANT |
| 24999 | #define ARM_VARIANT & fpu_vfp_ext_armv8xd |
| 25000 | mnUF(vcvta, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvta), |
| 25001 | mnUF(vcvtp, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtp), |
| 25002 | mnUF(vcvtn, _vcvta, 3, (RNSDQMQ, oRNSDQMQ, oI32z), neon_cvtn), |
| 25003 | mnUF(vcvtm, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtm), |
| 25004 | mnUF(vmaxnm, _vmaxnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm), |
| 25005 | mnUF(vminnm, _vminnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm), |
| 25006 | |
| 25007 | #undef ARM_VARIANT |
| 25008 | #define ARM_VARIANT & fpu_neon_ext_v1 |
| 25009 | mnUF(vabd, _vabd, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su), |
| 25010 | mnUF(vabdl, _vabdl, 3, (RNQMQ, RNDMQ, RNDMQ), neon_dyadic_long), |
| 25011 | mnUF(vaddl, _vaddl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long), |
| 25012 | mnUF(vsubl, _vsubl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long), |
| 25013 | mnUF(vand, _vand, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic), |
| 25014 | mnUF(vbic, _vbic, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic), |
| 25015 | mnUF(vorr, _vorr, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic), |
| 25016 | mnUF(vorn, _vorn, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic), |
| 25017 | mnUF(veor, _veor, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_logic), |
| 25018 | MNUF(vcls, 1b00400, 2, (RNDQMQ, RNDQMQ), neon_cls), |
| 25019 | MNUF(vclz, 1b00480, 2, (RNDQMQ, RNDQMQ), neon_clz), |
| 25020 | mnCE(vdup, _vdup, 2, (RNDQMQ, RR_RNSC), neon_dup), |
| 25021 | MNUF(vhadd, 00000000, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su), |
| 25022 | MNUF(vrhadd, 00000100, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_i_su), |
| 25023 | MNUF(vhsub, 00000200, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su), |
| 25024 | mnUF(vmin, _vmin, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su), |
| 25025 | mnUF(vmax, _vmax, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su), |
| 25026 | MNUF(vqadd, 0000010, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su), |
| 25027 | MNUF(vqsub, 0000210, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su), |
| 25028 | mnUF(vmvn, _vmvn, 2, (RNDQMQ, RNDQMQ_Ibig), neon_mvn), |
| 25029 | MNUF(vqabs, 1b00700, 2, (RNDQMQ, RNDQMQ), neon_sat_abs_neg), |
| 25030 | MNUF(vqneg, 1b00780, 2, (RNDQMQ, RNDQMQ), neon_sat_abs_neg), |
| 25031 | mnUF(vqrdmlah, _vqrdmlah,3, (RNDQMQ, oRNDQMQ, RNDQ_RNSC_RR), neon_qrdmlah), |
| 25032 | mnUF(vqdmulh, _vqdmulh, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh), |
| 25033 | mnUF(vqrdmulh, _vqrdmulh,3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh), |
| 25034 | MNUF(vqrshl, 0000510, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl), |
| 25035 | MNUF(vrshl, 0000500, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl), |
| 25036 | |
| 25037 | #undef ARM_VARIANT |
| 25038 | #define ARM_VARIANT & arm_ext_v8_3 |
| 25039 | #undef THUMB_VARIANT |
| 25040 | #define THUMB_VARIANT & arm_ext_v6t2_v8m |
| 25041 | MNUF (vcadd, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ, EXPi), vcadd), |
| 25042 | MNUF (vcmla, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ_RNSC, EXPi), vcmla), |
| 25043 | }; |
| 25044 | #undef ARM_VARIANT |
| 25045 | #undef THUMB_VARIANT |
| 25046 | #undef TCE |
| 25047 | #undef TUE |
| 25048 | #undef TUF |
| 25049 | #undef TCC |
| 25050 | #undef cCE |
| 25051 | #undef cCL |
| 25052 | #undef C3E |
| 25053 | #undef C3 |
| 25054 | #undef CE |
| 25055 | #undef CM |
| 25056 | #undef CL |
| 25057 | #undef UE |
| 25058 | #undef UF |
| 25059 | #undef UT |
| 25060 | #undef NUF |
| 25061 | #undef nUF |
| 25062 | #undef NCE |
| 25063 | #undef nCE |
| 25064 | #undef OPS0 |
| 25065 | #undef OPS1 |
| 25066 | #undef OPS2 |
| 25067 | #undef OPS3 |
| 25068 | #undef OPS4 |
| 25069 | #undef OPS5 |
| 25070 | #undef OPS6 |
| 25071 | #undef do_0 |
| 25072 | #undef ToC |
| 25073 | #undef toC |
| 25074 | #undef ToU |
| 25075 | #undef toU |
| 25076 | \f |
| 25077 | /* MD interface: bits in the object file. */ |
| 25078 | |
| 25079 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate |
| 25080 | for use in the a.out file, and stores them in the array pointed to by buf. |
| 25081 | This knows about the endian-ness of the target machine and does |
| 25082 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) |
| 25083 | 2 (short) and 4 (long) Floating numbers are put out as a series of |
| 25084 | LITTLENUMS (shorts, here at least). */ |
| 25085 | |
| 25086 | void |
| 25087 | md_number_to_chars (char * buf, valueT val, int n) |
| 25088 | { |
| 25089 | if (target_big_endian) |
| 25090 | number_to_chars_bigendian (buf, val, n); |
| 25091 | else |
| 25092 | number_to_chars_littleendian (buf, val, n); |
| 25093 | } |
| 25094 | |
| 25095 | static valueT |
| 25096 | md_chars_to_number (char * buf, int n) |
| 25097 | { |
| 25098 | valueT result = 0; |
| 25099 | unsigned char * where = (unsigned char *) buf; |
| 25100 | |
| 25101 | if (target_big_endian) |
| 25102 | { |
| 25103 | while (n--) |
| 25104 | { |
| 25105 | result <<= 8; |
| 25106 | result |= (*where++ & 255); |
| 25107 | } |
| 25108 | } |
| 25109 | else |
| 25110 | { |
| 25111 | while (n--) |
| 25112 | { |
| 25113 | result <<= 8; |
| 25114 | result |= (where[n] & 255); |
| 25115 | } |
| 25116 | } |
| 25117 | |
| 25118 | return result; |
| 25119 | } |
| 25120 | |
| 25121 | /* MD interface: Sections. */ |
| 25122 | |
| 25123 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
| 25124 | that an rs_machine_dependent frag may reach. */ |
| 25125 | |
| 25126 | unsigned int |
| 25127 | arm_frag_max_var (fragS *fragp) |
| 25128 | { |
| 25129 | /* We only use rs_machine_dependent for variable-size Thumb instructions, |
| 25130 | which are either THUMB_SIZE (2) or INSN_SIZE (4). |
| 25131 | |
| 25132 | Note that we generate relaxable instructions even for cases that don't |
| 25133 | really need it, like an immediate that's a trivial constant. So we're |
| 25134 | overestimating the instruction size for some of those cases. Rather |
| 25135 | than putting more intelligence here, it would probably be better to |
| 25136 | avoid generating a relaxation frag in the first place when it can be |
| 25137 | determined up front that a short instruction will suffice. */ |
| 25138 | |
| 25139 | gas_assert (fragp->fr_type == rs_machine_dependent); |
| 25140 | return INSN_SIZE; |
| 25141 | } |
| 25142 | |
| 25143 | /* Estimate the size of a frag before relaxing. Assume everything fits in |
| 25144 | 2 bytes. */ |
| 25145 | |
| 25146 | int |
| 25147 | md_estimate_size_before_relax (fragS * fragp, |
| 25148 | segT segtype ATTRIBUTE_UNUSED) |
| 25149 | { |
| 25150 | fragp->fr_var = 2; |
| 25151 | return 2; |
| 25152 | } |
| 25153 | |
| 25154 | /* Convert a machine dependent frag. */ |
| 25155 | |
| 25156 | void |
| 25157 | md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) |
| 25158 | { |
| 25159 | unsigned long insn; |
| 25160 | unsigned long old_op; |
| 25161 | char *buf; |
| 25162 | expressionS exp; |
| 25163 | fixS *fixp; |
| 25164 | int reloc_type; |
| 25165 | int pc_rel; |
| 25166 | int opcode; |
| 25167 | |
| 25168 | buf = fragp->fr_literal + fragp->fr_fix; |
| 25169 | |
| 25170 | old_op = bfd_get_16(abfd, buf); |
| 25171 | if (fragp->fr_symbol) |
| 25172 | { |
| 25173 | exp.X_op = O_symbol; |
| 25174 | exp.X_add_symbol = fragp->fr_symbol; |
| 25175 | } |
| 25176 | else |
| 25177 | { |
| 25178 | exp.X_op = O_constant; |
| 25179 | } |
| 25180 | exp.X_add_number = fragp->fr_offset; |
| 25181 | opcode = fragp->fr_subtype; |
| 25182 | switch (opcode) |
| 25183 | { |
| 25184 | case T_MNEM_ldr_pc: |
| 25185 | case T_MNEM_ldr_pc2: |
| 25186 | case T_MNEM_ldr_sp: |
| 25187 | case T_MNEM_str_sp: |
| 25188 | case T_MNEM_ldr: |
| 25189 | case T_MNEM_ldrb: |
| 25190 | case T_MNEM_ldrh: |
| 25191 | case T_MNEM_str: |
| 25192 | case T_MNEM_strb: |
| 25193 | case T_MNEM_strh: |
| 25194 | if (fragp->fr_var == 4) |
| 25195 | { |
| 25196 | insn = THUMB_OP32 (opcode); |
| 25197 | if ((old_op >> 12) == 4 || (old_op >> 12) == 9) |
| 25198 | { |
| 25199 | insn |= (old_op & 0x700) << 4; |
| 25200 | } |
| 25201 | else |
| 25202 | { |
| 25203 | insn |= (old_op & 7) << 12; |
| 25204 | insn |= (old_op & 0x38) << 13; |
| 25205 | } |
| 25206 | insn |= 0x00000c00; |
| 25207 | put_thumb32_insn (buf, insn); |
| 25208 | reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
| 25209 | } |
| 25210 | else |
| 25211 | { |
| 25212 | reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; |
| 25213 | } |
| 25214 | pc_rel = (opcode == T_MNEM_ldr_pc2); |
| 25215 | break; |
| 25216 | case T_MNEM_adr: |
| 25217 | if (fragp->fr_var == 4) |
| 25218 | { |
| 25219 | insn = THUMB_OP32 (opcode); |
| 25220 | insn |= (old_op & 0xf0) << 4; |
| 25221 | put_thumb32_insn (buf, insn); |
| 25222 | reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; |
| 25223 | } |
| 25224 | else |
| 25225 | { |
| 25226 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; |
| 25227 | exp.X_add_number -= 4; |
| 25228 | } |
| 25229 | pc_rel = 1; |
| 25230 | break; |
| 25231 | case T_MNEM_mov: |
| 25232 | case T_MNEM_movs: |
| 25233 | case T_MNEM_cmp: |
| 25234 | case T_MNEM_cmn: |
| 25235 | if (fragp->fr_var == 4) |
| 25236 | { |
| 25237 | int r0off = (opcode == T_MNEM_mov |
| 25238 | || opcode == T_MNEM_movs) ? 0 : 8; |
| 25239 | insn = THUMB_OP32 (opcode); |
| 25240 | insn = (insn & 0xe1ffffff) | 0x10000000; |
| 25241 | insn |= (old_op & 0x700) << r0off; |
| 25242 | put_thumb32_insn (buf, insn); |
| 25243 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; |
| 25244 | } |
| 25245 | else |
| 25246 | { |
| 25247 | reloc_type = BFD_RELOC_ARM_THUMB_IMM; |
| 25248 | } |
| 25249 | pc_rel = 0; |
| 25250 | break; |
| 25251 | case T_MNEM_b: |
| 25252 | if (fragp->fr_var == 4) |
| 25253 | { |
| 25254 | insn = THUMB_OP32(opcode); |
| 25255 | put_thumb32_insn (buf, insn); |
| 25256 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; |
| 25257 | } |
| 25258 | else |
| 25259 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; |
| 25260 | pc_rel = 1; |
| 25261 | break; |
| 25262 | case T_MNEM_bcond: |
| 25263 | if (fragp->fr_var == 4) |
| 25264 | { |
| 25265 | insn = THUMB_OP32(opcode); |
| 25266 | insn |= (old_op & 0xf00) << 14; |
| 25267 | put_thumb32_insn (buf, insn); |
| 25268 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; |
| 25269 | } |
| 25270 | else |
| 25271 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; |
| 25272 | pc_rel = 1; |
| 25273 | break; |
| 25274 | case T_MNEM_add_sp: |
| 25275 | case T_MNEM_add_pc: |
| 25276 | case T_MNEM_inc_sp: |
| 25277 | case T_MNEM_dec_sp: |
| 25278 | if (fragp->fr_var == 4) |
| 25279 | { |
| 25280 | /* ??? Choose between add and addw. */ |
| 25281 | insn = THUMB_OP32 (opcode); |
| 25282 | insn |= (old_op & 0xf0) << 4; |
| 25283 | put_thumb32_insn (buf, insn); |
| 25284 | if (opcode == T_MNEM_add_pc) |
| 25285 | reloc_type = BFD_RELOC_ARM_T32_IMM12; |
| 25286 | else |
| 25287 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; |
| 25288 | } |
| 25289 | else |
| 25290 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; |
| 25291 | pc_rel = 0; |
| 25292 | break; |
| 25293 | |
| 25294 | case T_MNEM_addi: |
| 25295 | case T_MNEM_addis: |
| 25296 | case T_MNEM_subi: |
| 25297 | case T_MNEM_subis: |
| 25298 | if (fragp->fr_var == 4) |
| 25299 | { |
| 25300 | insn = THUMB_OP32 (opcode); |
| 25301 | insn |= (old_op & 0xf0) << 4; |
| 25302 | insn |= (old_op & 0xf) << 16; |
| 25303 | put_thumb32_insn (buf, insn); |
| 25304 | if (insn & (1 << 20)) |
| 25305 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; |
| 25306 | else |
| 25307 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; |
| 25308 | } |
| 25309 | else |
| 25310 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; |
| 25311 | pc_rel = 0; |
| 25312 | break; |
| 25313 | default: |
| 25314 | abort (); |
| 25315 | } |
| 25316 | fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, |
| 25317 | (enum bfd_reloc_code_real) reloc_type); |
| 25318 | fixp->fx_file = fragp->fr_file; |
| 25319 | fixp->fx_line = fragp->fr_line; |
| 25320 | fragp->fr_fix += fragp->fr_var; |
| 25321 | |
| 25322 | /* Set whether we use thumb-2 ISA based on final relaxation results. */ |
| 25323 | if (thumb_mode && fragp->fr_var == 4 && no_cpu_selected () |
| 25324 | && !ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2)) |
| 25325 | ARM_MERGE_FEATURE_SETS (arm_arch_used, thumb_arch_used, arm_ext_v6t2); |
| 25326 | } |
| 25327 | |
| 25328 | /* Return the size of a relaxable immediate operand instruction. |
| 25329 | SHIFT and SIZE specify the form of the allowable immediate. */ |
| 25330 | static int |
| 25331 | relax_immediate (fragS *fragp, int size, int shift) |
| 25332 | { |
| 25333 | offsetT offset; |
| 25334 | offsetT mask; |
| 25335 | offsetT low; |
| 25336 | |
| 25337 | /* ??? Should be able to do better than this. */ |
| 25338 | if (fragp->fr_symbol) |
| 25339 | return 4; |
| 25340 | |
| 25341 | low = (1 << shift) - 1; |
| 25342 | mask = (1 << (shift + size)) - (1 << shift); |
| 25343 | offset = fragp->fr_offset; |
| 25344 | /* Force misaligned offsets to 32-bit variant. */ |
| 25345 | if (offset & low) |
| 25346 | return 4; |
| 25347 | if (offset & ~mask) |
| 25348 | return 4; |
| 25349 | return 2; |
| 25350 | } |
| 25351 | |
| 25352 | /* Get the address of a symbol during relaxation. */ |
| 25353 | static addressT |
| 25354 | relaxed_symbol_addr (fragS *fragp, long stretch) |
| 25355 | { |
| 25356 | fragS *sym_frag; |
| 25357 | addressT addr; |
| 25358 | symbolS *sym; |
| 25359 | |
| 25360 | sym = fragp->fr_symbol; |
| 25361 | sym_frag = symbol_get_frag (sym); |
| 25362 | know (S_GET_SEGMENT (sym) != absolute_section |
| 25363 | || sym_frag == &zero_address_frag); |
| 25364 | addr = S_GET_VALUE (sym) + fragp->fr_offset; |
| 25365 | |
| 25366 | /* If frag has yet to be reached on this pass, assume it will |
| 25367 | move by STRETCH just as we did. If this is not so, it will |
| 25368 | be because some frag between grows, and that will force |
| 25369 | another pass. */ |
| 25370 | |
| 25371 | if (stretch != 0 |
| 25372 | && sym_frag->relax_marker != fragp->relax_marker) |
| 25373 | { |
| 25374 | fragS *f; |
| 25375 | |
| 25376 | /* Adjust stretch for any alignment frag. Note that if have |
| 25377 | been expanding the earlier code, the symbol may be |
| 25378 | defined in what appears to be an earlier frag. FIXME: |
| 25379 | This doesn't handle the fr_subtype field, which specifies |
| 25380 | a maximum number of bytes to skip when doing an |
| 25381 | alignment. */ |
| 25382 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
| 25383 | { |
| 25384 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) |
| 25385 | { |
| 25386 | if (stretch < 0) |
| 25387 | stretch = - ((- stretch) |
| 25388 | & ~ ((1 << (int) f->fr_offset) - 1)); |
| 25389 | else |
| 25390 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); |
| 25391 | if (stretch == 0) |
| 25392 | break; |
| 25393 | } |
| 25394 | } |
| 25395 | if (f != NULL) |
| 25396 | addr += stretch; |
| 25397 | } |
| 25398 | |
| 25399 | return addr; |
| 25400 | } |
| 25401 | |
| 25402 | /* Return the size of a relaxable adr pseudo-instruction or PC-relative |
| 25403 | load. */ |
| 25404 | static int |
| 25405 | relax_adr (fragS *fragp, asection *sec, long stretch) |
| 25406 | { |
| 25407 | addressT addr; |
| 25408 | offsetT val; |
| 25409 | |
| 25410 | /* Assume worst case for symbols not known to be in the same section. */ |
| 25411 | if (fragp->fr_symbol == NULL |
| 25412 | || !S_IS_DEFINED (fragp->fr_symbol) |
| 25413 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
| 25414 | || S_IS_WEAK (fragp->fr_symbol)) |
| 25415 | return 4; |
| 25416 | |
| 25417 | val = relaxed_symbol_addr (fragp, stretch); |
| 25418 | addr = fragp->fr_address + fragp->fr_fix; |
| 25419 | addr = (addr + 4) & ~3; |
| 25420 | /* Force misaligned targets to 32-bit variant. */ |
| 25421 | if (val & 3) |
| 25422 | return 4; |
| 25423 | val -= addr; |
| 25424 | if (val < 0 || val > 1020) |
| 25425 | return 4; |
| 25426 | return 2; |
| 25427 | } |
| 25428 | |
| 25429 | /* Return the size of a relaxable add/sub immediate instruction. */ |
| 25430 | static int |
| 25431 | relax_addsub (fragS *fragp, asection *sec) |
| 25432 | { |
| 25433 | char *buf; |
| 25434 | int op; |
| 25435 | |
| 25436 | buf = fragp->fr_literal + fragp->fr_fix; |
| 25437 | op = bfd_get_16(sec->owner, buf); |
| 25438 | if ((op & 0xf) == ((op >> 4) & 0xf)) |
| 25439 | return relax_immediate (fragp, 8, 0); |
| 25440 | else |
| 25441 | return relax_immediate (fragp, 3, 0); |
| 25442 | } |
| 25443 | |
| 25444 | /* Return TRUE iff the definition of symbol S could be pre-empted |
| 25445 | (overridden) at link or load time. */ |
| 25446 | static bfd_boolean |
| 25447 | symbol_preemptible (symbolS *s) |
| 25448 | { |
| 25449 | /* Weak symbols can always be pre-empted. */ |
| 25450 | if (S_IS_WEAK (s)) |
| 25451 | return TRUE; |
| 25452 | |
| 25453 | /* Non-global symbols cannot be pre-empted. */ |
| 25454 | if (! S_IS_EXTERNAL (s)) |
| 25455 | return FALSE; |
| 25456 | |
| 25457 | #ifdef OBJ_ELF |
| 25458 | /* In ELF, a global symbol can be marked protected, or private. In that |
| 25459 | case it can't be pre-empted (other definitions in the same link unit |
| 25460 | would violate the ODR). */ |
| 25461 | if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT) |
| 25462 | return FALSE; |
| 25463 | #endif |
| 25464 | |
| 25465 | /* Other global symbols might be pre-empted. */ |
| 25466 | return TRUE; |
| 25467 | } |
| 25468 | |
| 25469 | /* Return the size of a relaxable branch instruction. BITS is the |
| 25470 | size of the offset field in the narrow instruction. */ |
| 25471 | |
| 25472 | static int |
| 25473 | relax_branch (fragS *fragp, asection *sec, int bits, long stretch) |
| 25474 | { |
| 25475 | addressT addr; |
| 25476 | offsetT val; |
| 25477 | offsetT limit; |
| 25478 | |
| 25479 | /* Assume worst case for symbols not known to be in the same section. */ |
| 25480 | if (!S_IS_DEFINED (fragp->fr_symbol) |
| 25481 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
| 25482 | || S_IS_WEAK (fragp->fr_symbol)) |
| 25483 | return 4; |
| 25484 | |
| 25485 | #ifdef OBJ_ELF |
| 25486 | /* A branch to a function in ARM state will require interworking. */ |
| 25487 | if (S_IS_DEFINED (fragp->fr_symbol) |
| 25488 | && ARM_IS_FUNC (fragp->fr_symbol)) |
| 25489 | return 4; |
| 25490 | #endif |
| 25491 | |
| 25492 | if (symbol_preemptible (fragp->fr_symbol)) |
| 25493 | return 4; |
| 25494 | |
| 25495 | val = relaxed_symbol_addr (fragp, stretch); |
| 25496 | addr = fragp->fr_address + fragp->fr_fix + 4; |
| 25497 | val -= addr; |
| 25498 | |
| 25499 | /* Offset is a signed value *2 */ |
| 25500 | limit = 1 << bits; |
| 25501 | if (val >= limit || val < -limit) |
| 25502 | return 4; |
| 25503 | return 2; |
| 25504 | } |
| 25505 | |
| 25506 | |
| 25507 | /* Relax a machine dependent frag. This returns the amount by which |
| 25508 | the current size of the frag should change. */ |
| 25509 | |
| 25510 | int |
| 25511 | arm_relax_frag (asection *sec, fragS *fragp, long stretch) |
| 25512 | { |
| 25513 | int oldsize; |
| 25514 | int newsize; |
| 25515 | |
| 25516 | oldsize = fragp->fr_var; |
| 25517 | switch (fragp->fr_subtype) |
| 25518 | { |
| 25519 | case T_MNEM_ldr_pc2: |
| 25520 | newsize = relax_adr (fragp, sec, stretch); |
| 25521 | break; |
| 25522 | case T_MNEM_ldr_pc: |
| 25523 | case T_MNEM_ldr_sp: |
| 25524 | case T_MNEM_str_sp: |
| 25525 | newsize = relax_immediate (fragp, 8, 2); |
| 25526 | break; |
| 25527 | case T_MNEM_ldr: |
| 25528 | case T_MNEM_str: |
| 25529 | newsize = relax_immediate (fragp, 5, 2); |
| 25530 | break; |
| 25531 | case T_MNEM_ldrh: |
| 25532 | case T_MNEM_strh: |
| 25533 | newsize = relax_immediate (fragp, 5, 1); |
| 25534 | break; |
| 25535 | case T_MNEM_ldrb: |
| 25536 | case T_MNEM_strb: |
| 25537 | newsize = relax_immediate (fragp, 5, 0); |
| 25538 | break; |
| 25539 | case T_MNEM_adr: |
| 25540 | newsize = relax_adr (fragp, sec, stretch); |
| 25541 | break; |
| 25542 | case T_MNEM_mov: |
| 25543 | case T_MNEM_movs: |
| 25544 | case T_MNEM_cmp: |
| 25545 | case T_MNEM_cmn: |
| 25546 | newsize = relax_immediate (fragp, 8, 0); |
| 25547 | break; |
| 25548 | case T_MNEM_b: |
| 25549 | newsize = relax_branch (fragp, sec, 11, stretch); |
| 25550 | break; |
| 25551 | case T_MNEM_bcond: |
| 25552 | newsize = relax_branch (fragp, sec, 8, stretch); |
| 25553 | break; |
| 25554 | case T_MNEM_add_sp: |
| 25555 | case T_MNEM_add_pc: |
| 25556 | newsize = relax_immediate (fragp, 8, 2); |
| 25557 | break; |
| 25558 | case T_MNEM_inc_sp: |
| 25559 | case T_MNEM_dec_sp: |
| 25560 | newsize = relax_immediate (fragp, 7, 2); |
| 25561 | break; |
| 25562 | case T_MNEM_addi: |
| 25563 | case T_MNEM_addis: |
| 25564 | case T_MNEM_subi: |
| 25565 | case T_MNEM_subis: |
| 25566 | newsize = relax_addsub (fragp, sec); |
| 25567 | break; |
| 25568 | default: |
| 25569 | abort (); |
| 25570 | } |
| 25571 | |
| 25572 | fragp->fr_var = newsize; |
| 25573 | /* Freeze wide instructions that are at or before the same location as |
| 25574 | in the previous pass. This avoids infinite loops. |
| 25575 | Don't freeze them unconditionally because targets may be artificially |
| 25576 | misaligned by the expansion of preceding frags. */ |
| 25577 | if (stretch <= 0 && newsize > 2) |
| 25578 | { |
| 25579 | md_convert_frag (sec->owner, sec, fragp); |
| 25580 | frag_wane (fragp); |
| 25581 | } |
| 25582 | |
| 25583 | return newsize - oldsize; |
| 25584 | } |
| 25585 | |
| 25586 | /* Round up a section size to the appropriate boundary. */ |
| 25587 | |
| 25588 | valueT |
| 25589 | md_section_align (segT segment ATTRIBUTE_UNUSED, |
| 25590 | valueT size) |
| 25591 | { |
| 25592 | return size; |
| 25593 | } |
| 25594 | |
| 25595 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
| 25596 | of an rs_align_code fragment. */ |
| 25597 | |
| 25598 | void |
| 25599 | arm_handle_align (fragS * fragP) |
| 25600 | { |
| 25601 | static unsigned char const arm_noop[2][2][4] = |
| 25602 | { |
| 25603 | { /* ARMv1 */ |
| 25604 | {0x00, 0x00, 0xa0, 0xe1}, /* LE */ |
| 25605 | {0xe1, 0xa0, 0x00, 0x00}, /* BE */ |
| 25606 | }, |
| 25607 | { /* ARMv6k */ |
| 25608 | {0x00, 0xf0, 0x20, 0xe3}, /* LE */ |
| 25609 | {0xe3, 0x20, 0xf0, 0x00}, /* BE */ |
| 25610 | }, |
| 25611 | }; |
| 25612 | static unsigned char const thumb_noop[2][2][2] = |
| 25613 | { |
| 25614 | { /* Thumb-1 */ |
| 25615 | {0xc0, 0x46}, /* LE */ |
| 25616 | {0x46, 0xc0}, /* BE */ |
| 25617 | }, |
| 25618 | { /* Thumb-2 */ |
| 25619 | {0x00, 0xbf}, /* LE */ |
| 25620 | {0xbf, 0x00} /* BE */ |
| 25621 | } |
| 25622 | }; |
| 25623 | static unsigned char const wide_thumb_noop[2][4] = |
| 25624 | { /* Wide Thumb-2 */ |
| 25625 | {0xaf, 0xf3, 0x00, 0x80}, /* LE */ |
| 25626 | {0xf3, 0xaf, 0x80, 0x00}, /* BE */ |
| 25627 | }; |
| 25628 | |
| 25629 | unsigned bytes, fix, noop_size; |
| 25630 | char * p; |
| 25631 | const unsigned char * noop; |
| 25632 | const unsigned char *narrow_noop = NULL; |
| 25633 | #ifdef OBJ_ELF |
| 25634 | enum mstate state; |
| 25635 | #endif |
| 25636 | |
| 25637 | if (fragP->fr_type != rs_align_code) |
| 25638 | return; |
| 25639 | |
| 25640 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; |
| 25641 | p = fragP->fr_literal + fragP->fr_fix; |
| 25642 | fix = 0; |
| 25643 | |
| 25644 | if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) |
| 25645 | bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; |
| 25646 | |
| 25647 | gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0); |
| 25648 | |
| 25649 | if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED)) |
| 25650 | { |
| 25651 | if (ARM_CPU_HAS_FEATURE (selected_cpu_name[0] |
| 25652 | ? selected_cpu : arm_arch_none, arm_ext_v6t2)) |
| 25653 | { |
| 25654 | narrow_noop = thumb_noop[1][target_big_endian]; |
| 25655 | noop = wide_thumb_noop[target_big_endian]; |
| 25656 | } |
| 25657 | else |
| 25658 | noop = thumb_noop[0][target_big_endian]; |
| 25659 | noop_size = 2; |
| 25660 | #ifdef OBJ_ELF |
| 25661 | state = MAP_THUMB; |
| 25662 | #endif |
| 25663 | } |
| 25664 | else |
| 25665 | { |
| 25666 | noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu_name[0] |
| 25667 | ? selected_cpu : arm_arch_none, |
| 25668 | arm_ext_v6k) != 0] |
| 25669 | [target_big_endian]; |
| 25670 | noop_size = 4; |
| 25671 | #ifdef OBJ_ELF |
| 25672 | state = MAP_ARM; |
| 25673 | #endif |
| 25674 | } |
| 25675 | |
| 25676 | fragP->fr_var = noop_size; |
| 25677 | |
| 25678 | if (bytes & (noop_size - 1)) |
| 25679 | { |
| 25680 | fix = bytes & (noop_size - 1); |
| 25681 | #ifdef OBJ_ELF |
| 25682 | insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix); |
| 25683 | #endif |
| 25684 | memset (p, 0, fix); |
| 25685 | p += fix; |
| 25686 | bytes -= fix; |
| 25687 | } |
| 25688 | |
| 25689 | if (narrow_noop) |
| 25690 | { |
| 25691 | if (bytes & noop_size) |
| 25692 | { |
| 25693 | /* Insert a narrow noop. */ |
| 25694 | memcpy (p, narrow_noop, noop_size); |
| 25695 | p += noop_size; |
| 25696 | bytes -= noop_size; |
| 25697 | fix += noop_size; |
| 25698 | } |
| 25699 | |
| 25700 | /* Use wide noops for the remainder */ |
| 25701 | noop_size = 4; |
| 25702 | } |
| 25703 | |
| 25704 | while (bytes >= noop_size) |
| 25705 | { |
| 25706 | memcpy (p, noop, noop_size); |
| 25707 | p += noop_size; |
| 25708 | bytes -= noop_size; |
| 25709 | fix += noop_size; |
| 25710 | } |
| 25711 | |
| 25712 | fragP->fr_fix += fix; |
| 25713 | } |
| 25714 | |
| 25715 | /* Called from md_do_align. Used to create an alignment |
| 25716 | frag in a code section. */ |
| 25717 | |
| 25718 | void |
| 25719 | arm_frag_align_code (int n, int max) |
| 25720 | { |
| 25721 | char * p; |
| 25722 | |
| 25723 | /* We assume that there will never be a requirement |
| 25724 | to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */ |
| 25725 | if (max > MAX_MEM_FOR_RS_ALIGN_CODE) |
| 25726 | { |
| 25727 | char err_msg[128]; |
| 25728 | |
| 25729 | sprintf (err_msg, |
| 25730 | _("alignments greater than %d bytes not supported in .text sections."), |
| 25731 | MAX_MEM_FOR_RS_ALIGN_CODE + 1); |
| 25732 | as_fatal ("%s", err_msg); |
| 25733 | } |
| 25734 | |
| 25735 | p = frag_var (rs_align_code, |
| 25736 | MAX_MEM_FOR_RS_ALIGN_CODE, |
| 25737 | 1, |
| 25738 | (relax_substateT) max, |
| 25739 | (symbolS *) NULL, |
| 25740 | (offsetT) n, |
| 25741 | (char *) NULL); |
| 25742 | *p = 0; |
| 25743 | } |
| 25744 | |
| 25745 | /* Perform target specific initialisation of a frag. |
| 25746 | Note - despite the name this initialisation is not done when the frag |
| 25747 | is created, but only when its type is assigned. A frag can be created |
| 25748 | and used a long time before its type is set, so beware of assuming that |
| 25749 | this initialisation is performed first. */ |
| 25750 | |
| 25751 | #ifndef OBJ_ELF |
| 25752 | void |
| 25753 | arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED) |
| 25754 | { |
| 25755 | /* Record whether this frag is in an ARM or a THUMB area. */ |
| 25756 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
| 25757 | } |
| 25758 | |
| 25759 | #else /* OBJ_ELF is defined. */ |
| 25760 | void |
| 25761 | arm_init_frag (fragS * fragP, int max_chars) |
| 25762 | { |
| 25763 | bfd_boolean frag_thumb_mode; |
| 25764 | |
| 25765 | /* If the current ARM vs THUMB mode has not already |
| 25766 | been recorded into this frag then do so now. */ |
| 25767 | if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0) |
| 25768 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
| 25769 | |
| 25770 | /* PR 21809: Do not set a mapping state for debug sections |
| 25771 | - it just confuses other tools. */ |
| 25772 | if (bfd_get_section_flags (NULL, now_seg) & SEC_DEBUGGING) |
| 25773 | return; |
| 25774 | |
| 25775 | frag_thumb_mode = fragP->tc_frag_data.thumb_mode ^ MODE_RECORDED; |
| 25776 | |
| 25777 | /* Record a mapping symbol for alignment frags. We will delete this |
| 25778 | later if the alignment ends up empty. */ |
| 25779 | switch (fragP->fr_type) |
| 25780 | { |
| 25781 | case rs_align: |
| 25782 | case rs_align_test: |
| 25783 | case rs_fill: |
| 25784 | mapping_state_2 (MAP_DATA, max_chars); |
| 25785 | break; |
| 25786 | case rs_align_code: |
| 25787 | mapping_state_2 (frag_thumb_mode ? MAP_THUMB : MAP_ARM, max_chars); |
| 25788 | break; |
| 25789 | default: |
| 25790 | break; |
| 25791 | } |
| 25792 | } |
| 25793 | |
| 25794 | /* When we change sections we need to issue a new mapping symbol. */ |
| 25795 | |
| 25796 | void |
| 25797 | arm_elf_change_section (void) |
| 25798 | { |
| 25799 | /* Link an unlinked unwind index table section to the .text section. */ |
| 25800 | if (elf_section_type (now_seg) == SHT_ARM_EXIDX |
| 25801 | && elf_linked_to_section (now_seg) == NULL) |
| 25802 | elf_linked_to_section (now_seg) = text_section; |
| 25803 | } |
| 25804 | |
| 25805 | int |
| 25806 | arm_elf_section_type (const char * str, size_t len) |
| 25807 | { |
| 25808 | if (len == 5 && strncmp (str, "exidx", 5) == 0) |
| 25809 | return SHT_ARM_EXIDX; |
| 25810 | |
| 25811 | return -1; |
| 25812 | } |
| 25813 | \f |
| 25814 | /* Code to deal with unwinding tables. */ |
| 25815 | |
| 25816 | static void add_unwind_adjustsp (offsetT); |
| 25817 | |
| 25818 | /* Generate any deferred unwind frame offset. */ |
| 25819 | |
| 25820 | static void |
| 25821 | flush_pending_unwind (void) |
| 25822 | { |
| 25823 | offsetT offset; |
| 25824 | |
| 25825 | offset = unwind.pending_offset; |
| 25826 | unwind.pending_offset = 0; |
| 25827 | if (offset != 0) |
| 25828 | add_unwind_adjustsp (offset); |
| 25829 | } |
| 25830 | |
| 25831 | /* Add an opcode to this list for this function. Two-byte opcodes should |
| 25832 | be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse |
| 25833 | order. */ |
| 25834 | |
| 25835 | static void |
| 25836 | add_unwind_opcode (valueT op, int length) |
| 25837 | { |
| 25838 | /* Add any deferred stack adjustment. */ |
| 25839 | if (unwind.pending_offset) |
| 25840 | flush_pending_unwind (); |
| 25841 | |
| 25842 | unwind.sp_restored = 0; |
| 25843 | |
| 25844 | if (unwind.opcode_count + length > unwind.opcode_alloc) |
| 25845 | { |
| 25846 | unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; |
| 25847 | if (unwind.opcodes) |
| 25848 | unwind.opcodes = XRESIZEVEC (unsigned char, unwind.opcodes, |
| 25849 | unwind.opcode_alloc); |
| 25850 | else |
| 25851 | unwind.opcodes = XNEWVEC (unsigned char, unwind.opcode_alloc); |
| 25852 | } |
| 25853 | while (length > 0) |
| 25854 | { |
| 25855 | length--; |
| 25856 | unwind.opcodes[unwind.opcode_count] = op & 0xff; |
| 25857 | op >>= 8; |
| 25858 | unwind.opcode_count++; |
| 25859 | } |
| 25860 | } |
| 25861 | |
| 25862 | /* Add unwind opcodes to adjust the stack pointer. */ |
| 25863 | |
| 25864 | static void |
| 25865 | add_unwind_adjustsp (offsetT offset) |
| 25866 | { |
| 25867 | valueT op; |
| 25868 | |
| 25869 | if (offset > 0x200) |
| 25870 | { |
| 25871 | /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ |
| 25872 | char bytes[5]; |
| 25873 | int n; |
| 25874 | valueT o; |
| 25875 | |
| 25876 | /* Long form: 0xb2, uleb128. */ |
| 25877 | /* This might not fit in a word so add the individual bytes, |
| 25878 | remembering the list is built in reverse order. */ |
| 25879 | o = (valueT) ((offset - 0x204) >> 2); |
| 25880 | if (o == 0) |
| 25881 | add_unwind_opcode (0, 1); |
| 25882 | |
| 25883 | /* Calculate the uleb128 encoding of the offset. */ |
| 25884 | n = 0; |
| 25885 | while (o) |
| 25886 | { |
| 25887 | bytes[n] = o & 0x7f; |
| 25888 | o >>= 7; |
| 25889 | if (o) |
| 25890 | bytes[n] |= 0x80; |
| 25891 | n++; |
| 25892 | } |
| 25893 | /* Add the insn. */ |
| 25894 | for (; n; n--) |
| 25895 | add_unwind_opcode (bytes[n - 1], 1); |
| 25896 | add_unwind_opcode (0xb2, 1); |
| 25897 | } |
| 25898 | else if (offset > 0x100) |
| 25899 | { |
| 25900 | /* Two short opcodes. */ |
| 25901 | add_unwind_opcode (0x3f, 1); |
| 25902 | op = (offset - 0x104) >> 2; |
| 25903 | add_unwind_opcode (op, 1); |
| 25904 | } |
| 25905 | else if (offset > 0) |
| 25906 | { |
| 25907 | /* Short opcode. */ |
| 25908 | op = (offset - 4) >> 2; |
| 25909 | add_unwind_opcode (op, 1); |
| 25910 | } |
| 25911 | else if (offset < 0) |
| 25912 | { |
| 25913 | offset = -offset; |
| 25914 | while (offset > 0x100) |
| 25915 | { |
| 25916 | add_unwind_opcode (0x7f, 1); |
| 25917 | offset -= 0x100; |
| 25918 | } |
| 25919 | op = ((offset - 4) >> 2) | 0x40; |
| 25920 | add_unwind_opcode (op, 1); |
| 25921 | } |
| 25922 | } |
| 25923 | |
| 25924 | /* Finish the list of unwind opcodes for this function. */ |
| 25925 | |
| 25926 | static void |
| 25927 | finish_unwind_opcodes (void) |
| 25928 | { |
| 25929 | valueT op; |
| 25930 | |
| 25931 | if (unwind.fp_used) |
| 25932 | { |
| 25933 | /* Adjust sp as necessary. */ |
| 25934 | unwind.pending_offset += unwind.fp_offset - unwind.frame_size; |
| 25935 | flush_pending_unwind (); |
| 25936 | |
| 25937 | /* After restoring sp from the frame pointer. */ |
| 25938 | op = 0x90 | unwind.fp_reg; |
| 25939 | add_unwind_opcode (op, 1); |
| 25940 | } |
| 25941 | else |
| 25942 | flush_pending_unwind (); |
| 25943 | } |
| 25944 | |
| 25945 | |
| 25946 | /* Start an exception table entry. If idx is nonzero this is an index table |
| 25947 | entry. */ |
| 25948 | |
| 25949 | static void |
| 25950 | start_unwind_section (const segT text_seg, int idx) |
| 25951 | { |
| 25952 | const char * text_name; |
| 25953 | const char * prefix; |
| 25954 | const char * prefix_once; |
| 25955 | const char * group_name; |
| 25956 | char * sec_name; |
| 25957 | int type; |
| 25958 | int flags; |
| 25959 | int linkonce; |
| 25960 | |
| 25961 | if (idx) |
| 25962 | { |
| 25963 | prefix = ELF_STRING_ARM_unwind; |
| 25964 | prefix_once = ELF_STRING_ARM_unwind_once; |
| 25965 | type = SHT_ARM_EXIDX; |
| 25966 | } |
| 25967 | else |
| 25968 | { |
| 25969 | prefix = ELF_STRING_ARM_unwind_info; |
| 25970 | prefix_once = ELF_STRING_ARM_unwind_info_once; |
| 25971 | type = SHT_PROGBITS; |
| 25972 | } |
| 25973 | |
| 25974 | text_name = segment_name (text_seg); |
| 25975 | if (streq (text_name, ".text")) |
| 25976 | text_name = ""; |
| 25977 | |
| 25978 | if (strncmp (text_name, ".gnu.linkonce.t.", |
| 25979 | strlen (".gnu.linkonce.t.")) == 0) |
| 25980 | { |
| 25981 | prefix = prefix_once; |
| 25982 | text_name += strlen (".gnu.linkonce.t."); |
| 25983 | } |
| 25984 | |
| 25985 | sec_name = concat (prefix, text_name, (char *) NULL); |
| 25986 | |
| 25987 | flags = SHF_ALLOC; |
| 25988 | linkonce = 0; |
| 25989 | group_name = 0; |
| 25990 | |
| 25991 | /* Handle COMDAT group. */ |
| 25992 | if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) |
| 25993 | { |
| 25994 | group_name = elf_group_name (text_seg); |
| 25995 | if (group_name == NULL) |
| 25996 | { |
| 25997 | as_bad (_("Group section `%s' has no group signature"), |
| 25998 | segment_name (text_seg)); |
| 25999 | ignore_rest_of_line (); |
| 26000 | return; |
| 26001 | } |
| 26002 | flags |= SHF_GROUP; |
| 26003 | linkonce = 1; |
| 26004 | } |
| 26005 | |
| 26006 | obj_elf_change_section (sec_name, type, 0, flags, 0, group_name, |
| 26007 | linkonce, 0); |
| 26008 | |
| 26009 | /* Set the section link for index tables. */ |
| 26010 | if (idx) |
| 26011 | elf_linked_to_section (now_seg) = text_seg; |
| 26012 | } |
| 26013 | |
| 26014 | |
| 26015 | /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional |
| 26016 | personality routine data. Returns zero, or the index table value for |
| 26017 | an inline entry. */ |
| 26018 | |
| 26019 | static valueT |
| 26020 | create_unwind_entry (int have_data) |
| 26021 | { |
| 26022 | int size; |
| 26023 | addressT where; |
| 26024 | char *ptr; |
| 26025 | /* The current word of data. */ |
| 26026 | valueT data; |
| 26027 | /* The number of bytes left in this word. */ |
| 26028 | int n; |
| 26029 | |
| 26030 | finish_unwind_opcodes (); |
| 26031 | |
| 26032 | /* Remember the current text section. */ |
| 26033 | unwind.saved_seg = now_seg; |
| 26034 | unwind.saved_subseg = now_subseg; |
| 26035 | |
| 26036 | start_unwind_section (now_seg, 0); |
| 26037 | |
| 26038 | if (unwind.personality_routine == NULL) |
| 26039 | { |
| 26040 | if (unwind.personality_index == -2) |
| 26041 | { |
| 26042 | if (have_data) |
| 26043 | as_bad (_("handlerdata in cantunwind frame")); |
| 26044 | return 1; /* EXIDX_CANTUNWIND. */ |
| 26045 | } |
| 26046 | |
| 26047 | /* Use a default personality routine if none is specified. */ |
| 26048 | if (unwind.personality_index == -1) |
| 26049 | { |
| 26050 | if (unwind.opcode_count > 3) |
| 26051 | unwind.personality_index = 1; |
| 26052 | else |
| 26053 | unwind.personality_index = 0; |
| 26054 | } |
| 26055 | |
| 26056 | /* Space for the personality routine entry. */ |
| 26057 | if (unwind.personality_index == 0) |
| 26058 | { |
| 26059 | if (unwind.opcode_count > 3) |
| 26060 | as_bad (_("too many unwind opcodes for personality routine 0")); |
| 26061 | |
| 26062 | if (!have_data) |
| 26063 | { |
| 26064 | /* All the data is inline in the index table. */ |
| 26065 | data = 0x80; |
| 26066 | n = 3; |
| 26067 | while (unwind.opcode_count > 0) |
| 26068 | { |
| 26069 | unwind.opcode_count--; |
| 26070 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; |
| 26071 | n--; |
| 26072 | } |
| 26073 | |
| 26074 | /* Pad with "finish" opcodes. */ |
| 26075 | while (n--) |
| 26076 | data = (data << 8) | 0xb0; |
| 26077 | |
| 26078 | return data; |
| 26079 | } |
| 26080 | size = 0; |
| 26081 | } |
| 26082 | else |
| 26083 | /* We get two opcodes "free" in the first word. */ |
| 26084 | size = unwind.opcode_count - 2; |
| 26085 | } |
| 26086 | else |
| 26087 | { |
| 26088 | /* PR 16765: Missing or misplaced unwind directives can trigger this. */ |
| 26089 | if (unwind.personality_index != -1) |
| 26090 | { |
| 26091 | as_bad (_("attempt to recreate an unwind entry")); |
| 26092 | return 1; |
| 26093 | } |
| 26094 | |
| 26095 | /* An extra byte is required for the opcode count. */ |
| 26096 | size = unwind.opcode_count + 1; |
| 26097 | } |
| 26098 | |
| 26099 | size = (size + 3) >> 2; |
| 26100 | if (size > 0xff) |
| 26101 | as_bad (_("too many unwind opcodes")); |
| 26102 | |
| 26103 | frag_align (2, 0, 0); |
| 26104 | record_alignment (now_seg, 2); |
| 26105 | unwind.table_entry = expr_build_dot (); |
| 26106 | |
| 26107 | /* Allocate the table entry. */ |
| 26108 | ptr = frag_more ((size << 2) + 4); |
| 26109 | /* PR 13449: Zero the table entries in case some of them are not used. */ |
| 26110 | memset (ptr, 0, (size << 2) + 4); |
| 26111 | where = frag_now_fix () - ((size << 2) + 4); |
| 26112 | |
| 26113 | switch (unwind.personality_index) |
| 26114 | { |
| 26115 | case -1: |
| 26116 | /* ??? Should this be a PLT generating relocation? */ |
| 26117 | /* Custom personality routine. */ |
| 26118 | fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, |
| 26119 | BFD_RELOC_ARM_PREL31); |
| 26120 | |
| 26121 | where += 4; |
| 26122 | ptr += 4; |
| 26123 | |
| 26124 | /* Set the first byte to the number of additional words. */ |
| 26125 | data = size > 0 ? size - 1 : 0; |
| 26126 | n = 3; |
| 26127 | break; |
| 26128 | |
| 26129 | /* ABI defined personality routines. */ |
| 26130 | case 0: |
| 26131 | /* Three opcodes bytes are packed into the first word. */ |
| 26132 | data = 0x80; |
| 26133 | n = 3; |
| 26134 | break; |
| 26135 | |
| 26136 | case 1: |
| 26137 | case 2: |
| 26138 | /* The size and first two opcode bytes go in the first word. */ |
| 26139 | data = ((0x80 + unwind.personality_index) << 8) | size; |
| 26140 | n = 2; |
| 26141 | break; |
| 26142 | |
| 26143 | default: |
| 26144 | /* Should never happen. */ |
| 26145 | abort (); |
| 26146 | } |
| 26147 | |
| 26148 | /* Pack the opcodes into words (MSB first), reversing the list at the same |
| 26149 | time. */ |
| 26150 | while (unwind.opcode_count > 0) |
| 26151 | { |
| 26152 | if (n == 0) |
| 26153 | { |
| 26154 | md_number_to_chars (ptr, data, 4); |
| 26155 | ptr += 4; |
| 26156 | n = 4; |
| 26157 | data = 0; |
| 26158 | } |
| 26159 | unwind.opcode_count--; |
| 26160 | n--; |
| 26161 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; |
| 26162 | } |
| 26163 | |
| 26164 | /* Finish off the last word. */ |
| 26165 | if (n < 4) |
| 26166 | { |
| 26167 | /* Pad with "finish" opcodes. */ |
| 26168 | while (n--) |
| 26169 | data = (data << 8) | 0xb0; |
| 26170 | |
| 26171 | md_number_to_chars (ptr, data, 4); |
| 26172 | } |
| 26173 | |
| 26174 | if (!have_data) |
| 26175 | { |
| 26176 | /* Add an empty descriptor if there is no user-specified data. */ |
| 26177 | ptr = frag_more (4); |
| 26178 | md_number_to_chars (ptr, 0, 4); |
| 26179 | } |
| 26180 | |
| 26181 | return 0; |
| 26182 | } |
| 26183 | |
| 26184 | |
| 26185 | /* Initialize the DWARF-2 unwind information for this procedure. */ |
| 26186 | |
| 26187 | void |
| 26188 | tc_arm_frame_initial_instructions (void) |
| 26189 | { |
| 26190 | cfi_add_CFA_def_cfa (REG_SP, 0); |
| 26191 | } |
| 26192 | #endif /* OBJ_ELF */ |
| 26193 | |
| 26194 | /* Convert REGNAME to a DWARF-2 register number. */ |
| 26195 | |
| 26196 | int |
| 26197 | tc_arm_regname_to_dw2regnum (char *regname) |
| 26198 | { |
| 26199 | int reg = arm_reg_parse (®name, REG_TYPE_RN); |
| 26200 | if (reg != FAIL) |
| 26201 | return reg; |
| 26202 | |
| 26203 | /* PR 16694: Allow VFP registers as well. */ |
| 26204 | reg = arm_reg_parse (®name, REG_TYPE_VFS); |
| 26205 | if (reg != FAIL) |
| 26206 | return 64 + reg; |
| 26207 | |
| 26208 | reg = arm_reg_parse (®name, REG_TYPE_VFD); |
| 26209 | if (reg != FAIL) |
| 26210 | return reg + 256; |
| 26211 | |
| 26212 | return FAIL; |
| 26213 | } |
| 26214 | |
| 26215 | #ifdef TE_PE |
| 26216 | void |
| 26217 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) |
| 26218 | { |
| 26219 | expressionS exp; |
| 26220 | |
| 26221 | exp.X_op = O_secrel; |
| 26222 | exp.X_add_symbol = symbol; |
| 26223 | exp.X_add_number = 0; |
| 26224 | emit_expr (&exp, size); |
| 26225 | } |
| 26226 | #endif |
| 26227 | |
| 26228 | /* MD interface: Symbol and relocation handling. */ |
| 26229 | |
| 26230 | /* Return the address within the segment that a PC-relative fixup is |
| 26231 | relative to. For ARM, PC-relative fixups applied to instructions |
| 26232 | are generally relative to the location of the fixup plus 8 bytes. |
| 26233 | Thumb branches are offset by 4, and Thumb loads relative to PC |
| 26234 | require special handling. */ |
| 26235 | |
| 26236 | long |
| 26237 | md_pcrel_from_section (fixS * fixP, segT seg) |
| 26238 | { |
| 26239 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; |
| 26240 | |
| 26241 | /* If this is pc-relative and we are going to emit a relocation |
| 26242 | then we just want to put out any pipeline compensation that the linker |
| 26243 | will need. Otherwise we want to use the calculated base. |
| 26244 | For WinCE we skip the bias for externals as well, since this |
| 26245 | is how the MS ARM-CE assembler behaves and we want to be compatible. */ |
| 26246 | if (fixP->fx_pcrel |
| 26247 | && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) |
| 26248 | || (arm_force_relocation (fixP) |
| 26249 | #ifdef TE_WINCE |
| 26250 | && !S_IS_EXTERNAL (fixP->fx_addsy) |
| 26251 | #endif |
| 26252 | ))) |
| 26253 | base = 0; |
| 26254 | |
| 26255 | |
| 26256 | switch (fixP->fx_r_type) |
| 26257 | { |
| 26258 | /* PC relative addressing on the Thumb is slightly odd as the |
| 26259 | bottom two bits of the PC are forced to zero for the |
| 26260 | calculation. This happens *after* application of the |
| 26261 | pipeline offset. However, Thumb adrl already adjusts for |
| 26262 | this, so we need not do it again. */ |
| 26263 | case BFD_RELOC_ARM_THUMB_ADD: |
| 26264 | return base & ~3; |
| 26265 | |
| 26266 | case BFD_RELOC_ARM_THUMB_OFFSET: |
| 26267 | case BFD_RELOC_ARM_T32_OFFSET_IMM: |
| 26268 | case BFD_RELOC_ARM_T32_ADD_PC12: |
| 26269 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
| 26270 | return (base + 4) & ~3; |
| 26271 | |
| 26272 | /* Thumb branches are simply offset by +4. */ |
| 26273 | case BFD_RELOC_THUMB_PCREL_BRANCH5: |
| 26274 | case BFD_RELOC_THUMB_PCREL_BRANCH7: |
| 26275 | case BFD_RELOC_THUMB_PCREL_BRANCH9: |
| 26276 | case BFD_RELOC_THUMB_PCREL_BRANCH12: |
| 26277 | case BFD_RELOC_THUMB_PCREL_BRANCH20: |
| 26278 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
| 26279 | case BFD_RELOC_THUMB_PCREL_BFCSEL: |
| 26280 | case BFD_RELOC_ARM_THUMB_BF17: |
| 26281 | case BFD_RELOC_ARM_THUMB_BF19: |
| 26282 | case BFD_RELOC_ARM_THUMB_BF13: |
| 26283 | case BFD_RELOC_ARM_THUMB_LOOP12: |
| 26284 | return base + 4; |
| 26285 | |
| 26286 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
| 26287 | if (fixP->fx_addsy |
| 26288 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
| 26289 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
| 26290 | && ARM_IS_FUNC (fixP->fx_addsy) |
| 26291 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) |
| 26292 | base = fixP->fx_where + fixP->fx_frag->fr_address; |
| 26293 | return base + 4; |
| 26294 | |
| 26295 | /* BLX is like branches above, but forces the low two bits of PC to |
| 26296 | zero. */ |
| 26297 | case BFD_RELOC_THUMB_PCREL_BLX: |
| 26298 | if (fixP->fx_addsy |
| 26299 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
| 26300 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
| 26301 | && THUMB_IS_FUNC (fixP->fx_addsy) |
| 26302 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) |
| 26303 | base = fixP->fx_where + fixP->fx_frag->fr_address; |
| 26304 | return (base + 4) & ~3; |
| 26305 | |
| 26306 | /* ARM mode branches are offset by +8. However, the Windows CE |
| 26307 | loader expects the relocation not to take this into account. */ |
| 26308 | case BFD_RELOC_ARM_PCREL_BLX: |
| 26309 | if (fixP->fx_addsy |
| 26310 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
| 26311 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
| 26312 | && ARM_IS_FUNC (fixP->fx_addsy) |
| 26313 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) |
| 26314 | base = fixP->fx_where + fixP->fx_frag->fr_address; |
| 26315 | return base + 8; |
| 26316 | |
| 26317 | case BFD_RELOC_ARM_PCREL_CALL: |
| 26318 | if (fixP->fx_addsy |
| 26319 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
| 26320 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
| 26321 | && THUMB_IS_FUNC (fixP->fx_addsy) |
| 26322 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) |
| 26323 | base = fixP->fx_where + fixP->fx_frag->fr_address; |
| 26324 | return base + 8; |
| 26325 | |
| 26326 | case BFD_RELOC_ARM_PCREL_BRANCH: |
| 26327 | case BFD_RELOC_ARM_PCREL_JUMP: |
| 26328 | case BFD_RELOC_ARM_PLT32: |
| 26329 | #ifdef TE_WINCE |
| 26330 | /* When handling fixups immediately, because we have already |
| 26331 | discovered the value of a symbol, or the address of the frag involved |
| 26332 | we must account for the offset by +8, as the OS loader will never see the reloc. |
| 26333 | see fixup_segment() in write.c |
| 26334 | The S_IS_EXTERNAL test handles the case of global symbols. |
| 26335 | Those need the calculated base, not just the pipe compensation the linker will need. */ |
| 26336 | if (fixP->fx_pcrel |
| 26337 | && fixP->fx_addsy != NULL |
| 26338 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
| 26339 | && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) |
| 26340 | return base + 8; |
| 26341 | return base; |
| 26342 | #else |
| 26343 | return base + 8; |
| 26344 | #endif |
| 26345 | |
| 26346 | |
| 26347 | /* ARM mode loads relative to PC are also offset by +8. Unlike |
| 26348 | branches, the Windows CE loader *does* expect the relocation |
| 26349 | to take this into account. */ |
| 26350 | case BFD_RELOC_ARM_OFFSET_IMM: |
| 26351 | case BFD_RELOC_ARM_OFFSET_IMM8: |
| 26352 | case BFD_RELOC_ARM_HWLITERAL: |
| 26353 | case BFD_RELOC_ARM_LITERAL: |
| 26354 | case BFD_RELOC_ARM_CP_OFF_IMM: |
| 26355 | return base + 8; |
| 26356 | |
| 26357 | |
| 26358 | /* Other PC-relative relocations are un-offset. */ |
| 26359 | default: |
| 26360 | return base; |
| 26361 | } |
| 26362 | } |
| 26363 | |
| 26364 | static bfd_boolean flag_warn_syms = TRUE; |
| 26365 | |
| 26366 | bfd_boolean |
| 26367 | arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char * name) |
| 26368 | { |
| 26369 | /* PR 18347 - Warn if the user attempts to create a symbol with the same |
| 26370 | name as an ARM instruction. Whilst strictly speaking it is allowed, it |
| 26371 | does mean that the resulting code might be very confusing to the reader. |
| 26372 | Also this warning can be triggered if the user omits an operand before |
| 26373 | an immediate address, eg: |
| 26374 | |
| 26375 | LDR =foo |
| 26376 | |
| 26377 | GAS treats this as an assignment of the value of the symbol foo to a |
| 26378 | symbol LDR, and so (without this code) it will not issue any kind of |
| 26379 | warning or error message. |
| 26380 | |
| 26381 | Note - ARM instructions are case-insensitive but the strings in the hash |
| 26382 | table are all stored in lower case, so we must first ensure that name is |
| 26383 | lower case too. */ |
| 26384 | if (flag_warn_syms && arm_ops_hsh) |
| 26385 | { |
| 26386 | char * nbuf = strdup (name); |
| 26387 | char * p; |
| 26388 | |
| 26389 | for (p = nbuf; *p; p++) |
| 26390 | *p = TOLOWER (*p); |
| 26391 | if (hash_find (arm_ops_hsh, nbuf) != NULL) |
| 26392 | { |
| 26393 | static struct hash_control * already_warned = NULL; |
| 26394 | |
| 26395 | if (already_warned == NULL) |
| 26396 | already_warned = hash_new (); |
| 26397 | /* Only warn about the symbol once. To keep the code |
| 26398 | simple we let hash_insert do the lookup for us. */ |
| 26399 | if (hash_insert (already_warned, nbuf, NULL) == NULL) |
| 26400 | as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name); |
| 26401 | } |
| 26402 | else |
| 26403 | free (nbuf); |
| 26404 | } |
| 26405 | |
| 26406 | return FALSE; |
| 26407 | } |
| 26408 | |
| 26409 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. |
| 26410 | Otherwise we have no need to default values of symbols. */ |
| 26411 | |
| 26412 | symbolS * |
| 26413 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) |
| 26414 | { |
| 26415 | #ifdef OBJ_ELF |
| 26416 | if (name[0] == '_' && name[1] == 'G' |
| 26417 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) |
| 26418 | { |
| 26419 | if (!GOT_symbol) |
| 26420 | { |
| 26421 | if (symbol_find (name)) |
| 26422 | as_bad (_("GOT already in the symbol table")); |
| 26423 | |
| 26424 | GOT_symbol = symbol_new (name, undefined_section, |
| 26425 | (valueT) 0, & zero_address_frag); |
| 26426 | } |
| 26427 | |
| 26428 | return GOT_symbol; |
| 26429 | } |
| 26430 | #endif |
| 26431 | |
| 26432 | return NULL; |
| 26433 | } |
| 26434 | |
| 26435 | /* Subroutine of md_apply_fix. Check to see if an immediate can be |
| 26436 | computed as two separate immediate values, added together. We |
| 26437 | already know that this value cannot be computed by just one ARM |
| 26438 | instruction. */ |
| 26439 | |
| 26440 | static unsigned int |
| 26441 | validate_immediate_twopart (unsigned int val, |
| 26442 | unsigned int * highpart) |
| 26443 | { |
| 26444 | unsigned int a; |
| 26445 | unsigned int i; |
| 26446 | |
| 26447 | for (i = 0; i < 32; i += 2) |
| 26448 | if (((a = rotate_left (val, i)) & 0xff) != 0) |
| 26449 | { |
| 26450 | if (a & 0xff00) |
| 26451 | { |
| 26452 | if (a & ~ 0xffff) |
| 26453 | continue; |
| 26454 | * highpart = (a >> 8) | ((i + 24) << 7); |
| 26455 | } |
| 26456 | else if (a & 0xff0000) |
| 26457 | { |
| 26458 | if (a & 0xff000000) |
| 26459 | continue; |
| 26460 | * highpart = (a >> 16) | ((i + 16) << 7); |
| 26461 | } |
| 26462 | else |
| 26463 | { |
| 26464 | gas_assert (a & 0xff000000); |
| 26465 | * highpart = (a >> 24) | ((i + 8) << 7); |
| 26466 | } |
| 26467 | |
| 26468 | return (a & 0xff) | (i << 7); |
| 26469 | } |
| 26470 | |
| 26471 | return FAIL; |
| 26472 | } |
| 26473 | |
| 26474 | static int |
| 26475 | validate_offset_imm (unsigned int val, int hwse) |
| 26476 | { |
| 26477 | if ((hwse && val > 255) || val > 4095) |
| 26478 | return FAIL; |
| 26479 | return val; |
| 26480 | } |
| 26481 | |
| 26482 | /* Subroutine of md_apply_fix. Do those data_ops which can take a |
| 26483 | negative immediate constant by altering the instruction. A bit of |
| 26484 | a hack really. |
| 26485 | MOV <-> MVN |
| 26486 | AND <-> BIC |
| 26487 | ADC <-> SBC |
| 26488 | by inverting the second operand, and |
| 26489 | ADD <-> SUB |
| 26490 | CMP <-> CMN |
| 26491 | by negating the second operand. */ |
| 26492 | |
| 26493 | static int |
| 26494 | negate_data_op (unsigned long * instruction, |
| 26495 | unsigned long value) |
| 26496 | { |
| 26497 | int op, new_inst; |
| 26498 | unsigned long negated, inverted; |
| 26499 | |
| 26500 | negated = encode_arm_immediate (-value); |
| 26501 | inverted = encode_arm_immediate (~value); |
| 26502 | |
| 26503 | op = (*instruction >> DATA_OP_SHIFT) & 0xf; |
| 26504 | switch (op) |
| 26505 | { |
| 26506 | /* First negates. */ |
| 26507 | case OPCODE_SUB: /* ADD <-> SUB */ |
| 26508 | new_inst = OPCODE_ADD; |
| 26509 | value = negated; |
| 26510 | break; |
| 26511 | |
| 26512 | case OPCODE_ADD: |
| 26513 | new_inst = OPCODE_SUB; |
| 26514 | value = negated; |
| 26515 | break; |
| 26516 | |
| 26517 | case OPCODE_CMP: /* CMP <-> CMN */ |
| 26518 | new_inst = OPCODE_CMN; |
| 26519 | value = negated; |
| 26520 | break; |
| 26521 | |
| 26522 | case OPCODE_CMN: |
| 26523 | new_inst = OPCODE_CMP; |
| 26524 | value = negated; |
| 26525 | break; |
| 26526 | |
| 26527 | /* Now Inverted ops. */ |
| 26528 | case OPCODE_MOV: /* MOV <-> MVN */ |
| 26529 | new_inst = OPCODE_MVN; |
| 26530 | value = inverted; |
| 26531 | break; |
| 26532 | |
| 26533 | case OPCODE_MVN: |
| 26534 | new_inst = OPCODE_MOV; |
| 26535 | value = inverted; |
| 26536 | break; |
| 26537 | |
| 26538 | case OPCODE_AND: /* AND <-> BIC */ |
| 26539 | new_inst = OPCODE_BIC; |
| 26540 | value = inverted; |
| 26541 | break; |
| 26542 | |
| 26543 | case OPCODE_BIC: |
| 26544 | new_inst = OPCODE_AND; |
| 26545 | value = inverted; |
| 26546 | break; |
| 26547 | |
| 26548 | case OPCODE_ADC: /* ADC <-> SBC */ |
| 26549 | new_inst = OPCODE_SBC; |
| 26550 | value = inverted; |
| 26551 | break; |
| 26552 | |
| 26553 | case OPCODE_SBC: |
| 26554 | new_inst = OPCODE_ADC; |
| 26555 | value = inverted; |
| 26556 | break; |
| 26557 | |
| 26558 | /* We cannot do anything. */ |
| 26559 | default: |
| 26560 | return FAIL; |
| 26561 | } |
| 26562 | |
| 26563 | if (value == (unsigned) FAIL) |
| 26564 | return FAIL; |
| 26565 | |
| 26566 | *instruction &= OPCODE_MASK; |
| 26567 | *instruction |= new_inst << DATA_OP_SHIFT; |
| 26568 | return value; |
| 26569 | } |
| 26570 | |
| 26571 | /* Like negate_data_op, but for Thumb-2. */ |
| 26572 | |
| 26573 | static unsigned int |
| 26574 | thumb32_negate_data_op (offsetT *instruction, unsigned int value) |
| 26575 | { |
| 26576 | int op, new_inst; |
| 26577 | int rd; |
| 26578 | unsigned int negated, inverted; |
| 26579 | |
| 26580 | negated = encode_thumb32_immediate (-value); |
| 26581 | inverted = encode_thumb32_immediate (~value); |
| 26582 | |
| 26583 | rd = (*instruction >> 8) & 0xf; |
| 26584 | op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; |
| 26585 | switch (op) |
| 26586 | { |
| 26587 | /* ADD <-> SUB. Includes CMP <-> CMN. */ |
| 26588 | case T2_OPCODE_SUB: |
| 26589 | new_inst = T2_OPCODE_ADD; |
| 26590 | value = negated; |
| 26591 | break; |
| 26592 | |
| 26593 | case T2_OPCODE_ADD: |
| 26594 | new_inst = T2_OPCODE_SUB; |
| 26595 | value = negated; |
| 26596 | break; |
| 26597 | |
| 26598 | /* ORR <-> ORN. Includes MOV <-> MVN. */ |
| 26599 | case T2_OPCODE_ORR: |
| 26600 | new_inst = T2_OPCODE_ORN; |
| 26601 | value = inverted; |
| 26602 | break; |
| 26603 | |
| 26604 | case T2_OPCODE_ORN: |
| 26605 | new_inst = T2_OPCODE_ORR; |
| 26606 | value = inverted; |
| 26607 | break; |
| 26608 | |
| 26609 | /* AND <-> BIC. TST has no inverted equivalent. */ |
| 26610 | case T2_OPCODE_AND: |
| 26611 | new_inst = T2_OPCODE_BIC; |
| 26612 | if (rd == 15) |
| 26613 | value = FAIL; |
| 26614 | else |
| 26615 | value = inverted; |
| 26616 | break; |
| 26617 | |
| 26618 | case T2_OPCODE_BIC: |
| 26619 | new_inst = T2_OPCODE_AND; |
| 26620 | value = inverted; |
| 26621 | break; |
| 26622 | |
| 26623 | /* ADC <-> SBC */ |
| 26624 | case T2_OPCODE_ADC: |
| 26625 | new_inst = T2_OPCODE_SBC; |
| 26626 | value = inverted; |
| 26627 | break; |
| 26628 | |
| 26629 | case T2_OPCODE_SBC: |
| 26630 | new_inst = T2_OPCODE_ADC; |
| 26631 | value = inverted; |
| 26632 | break; |
| 26633 | |
| 26634 | /* We cannot do anything. */ |
| 26635 | default: |
| 26636 | return FAIL; |
| 26637 | } |
| 26638 | |
| 26639 | if (value == (unsigned int)FAIL) |
| 26640 | return FAIL; |
| 26641 | |
| 26642 | *instruction &= T2_OPCODE_MASK; |
| 26643 | *instruction |= new_inst << T2_DATA_OP_SHIFT; |
| 26644 | return value; |
| 26645 | } |
| 26646 | |
| 26647 | /* Read a 32-bit thumb instruction from buf. */ |
| 26648 | |
| 26649 | static unsigned long |
| 26650 | get_thumb32_insn (char * buf) |
| 26651 | { |
| 26652 | unsigned long insn; |
| 26653 | insn = md_chars_to_number (buf, THUMB_SIZE) << 16; |
| 26654 | insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); |
| 26655 | |
| 26656 | return insn; |
| 26657 | } |
| 26658 | |
| 26659 | /* We usually want to set the low bit on the address of thumb function |
| 26660 | symbols. In particular .word foo - . should have the low bit set. |
| 26661 | Generic code tries to fold the difference of two symbols to |
| 26662 | a constant. Prevent this and force a relocation when the first symbols |
| 26663 | is a thumb function. */ |
| 26664 | |
| 26665 | bfd_boolean |
| 26666 | arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) |
| 26667 | { |
| 26668 | if (op == O_subtract |
| 26669 | && l->X_op == O_symbol |
| 26670 | && r->X_op == O_symbol |
| 26671 | && THUMB_IS_FUNC (l->X_add_symbol)) |
| 26672 | { |
| 26673 | l->X_op = O_subtract; |
| 26674 | l->X_op_symbol = r->X_add_symbol; |
| 26675 | l->X_add_number -= r->X_add_number; |
| 26676 | return TRUE; |
| 26677 | } |
| 26678 | |
| 26679 | /* Process as normal. */ |
| 26680 | return FALSE; |
| 26681 | } |
| 26682 | |
| 26683 | /* Encode Thumb2 unconditional branches and calls. The encoding |
| 26684 | for the 2 are identical for the immediate values. */ |
| 26685 | |
| 26686 | static void |
| 26687 | encode_thumb2_b_bl_offset (char * buf, offsetT value) |
| 26688 | { |
| 26689 | #define T2I1I2MASK ((1 << 13) | (1 << 11)) |
| 26690 | offsetT newval; |
| 26691 | offsetT newval2; |
| 26692 | addressT S, I1, I2, lo, hi; |
| 26693 | |
| 26694 | S = (value >> 24) & 0x01; |
| 26695 | I1 = (value >> 23) & 0x01; |
| 26696 | I2 = (value >> 22) & 0x01; |
| 26697 | hi = (value >> 12) & 0x3ff; |
| 26698 | lo = (value >> 1) & 0x7ff; |
| 26699 | newval = md_chars_to_number (buf, THUMB_SIZE); |
| 26700 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); |
| 26701 | newval |= (S << 10) | hi; |
| 26702 | newval2 &= ~T2I1I2MASK; |
| 26703 | newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK; |
| 26704 | md_number_to_chars (buf, newval, THUMB_SIZE); |
| 26705 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); |
| 26706 | } |
| 26707 | |
| 26708 | void |
| 26709 | md_apply_fix (fixS * fixP, |
| 26710 | valueT * valP, |
| 26711 | segT seg) |
| 26712 | { |
| 26713 | offsetT value = * valP; |
| 26714 | offsetT newval; |
| 26715 | unsigned int newimm; |
| 26716 | unsigned long temp; |
| 26717 | int sign; |
| 26718 | char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; |
| 26719 | |
| 26720 | gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); |
| 26721 | |
| 26722 | /* Note whether this will delete the relocation. */ |
| 26723 | |
| 26724 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) |
| 26725 | fixP->fx_done = 1; |
| 26726 | |
| 26727 | /* On a 64-bit host, silently truncate 'value' to 32 bits for |
| 26728 | consistency with the behaviour on 32-bit hosts. Remember value |
| 26729 | for emit_reloc. */ |
| 26730 | value &= 0xffffffff; |
| 26731 | value ^= 0x80000000; |
| 26732 | value -= 0x80000000; |
| 26733 | |
| 26734 | *valP = value; |
| 26735 | fixP->fx_addnumber = value; |
| 26736 | |
| 26737 | /* Same treatment for fixP->fx_offset. */ |
| 26738 | fixP->fx_offset &= 0xffffffff; |
| 26739 | fixP->fx_offset ^= 0x80000000; |
| 26740 | fixP->fx_offset -= 0x80000000; |
| 26741 | |
| 26742 | switch (fixP->fx_r_type) |
| 26743 | { |
| 26744 | case BFD_RELOC_NONE: |
| 26745 | /* This will need to go in the object file. */ |
| 26746 | fixP->fx_done = 0; |
| 26747 | break; |
| 26748 | |
| 26749 | case BFD_RELOC_ARM_IMMEDIATE: |
| 26750 | /* We claim that this fixup has been processed here, |
| 26751 | even if in fact we generate an error because we do |
| 26752 | not have a reloc for it, so tc_gen_reloc will reject it. */ |
| 26753 | fixP->fx_done = 1; |
| 26754 | |
| 26755 | if (fixP->fx_addsy) |
| 26756 | { |
| 26757 | const char *msg = 0; |
| 26758 | |
| 26759 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
| 26760 | msg = _("undefined symbol %s used as an immediate value"); |
| 26761 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) |
| 26762 | msg = _("symbol %s is in a different section"); |
| 26763 | else if (S_IS_WEAK (fixP->fx_addsy)) |
| 26764 | msg = _("symbol %s is weak and may be overridden later"); |
| 26765 | |
| 26766 | if (msg) |
| 26767 | { |
| 26768 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 26769 | msg, S_GET_NAME (fixP->fx_addsy)); |
| 26770 | break; |
| 26771 | } |
| 26772 | } |
| 26773 | |
| 26774 | temp = md_chars_to_number (buf, INSN_SIZE); |
| 26775 | |
| 26776 | /* If the offset is negative, we should use encoding A2 for ADR. */ |
| 26777 | if ((temp & 0xfff0000) == 0x28f0000 && value < 0) |
| 26778 | newimm = negate_data_op (&temp, value); |
| 26779 | else |
| 26780 | { |
| 26781 | newimm = encode_arm_immediate (value); |
| 26782 | |
| 26783 | /* If the instruction will fail, see if we can fix things up by |
| 26784 | changing the opcode. */ |
| 26785 | if (newimm == (unsigned int) FAIL) |
| 26786 | newimm = negate_data_op (&temp, value); |
| 26787 | /* MOV accepts both ARM modified immediate (A1 encoding) and |
| 26788 | UINT16 (A2 encoding) when possible, MOVW only accepts UINT16. |
| 26789 | When disassembling, MOV is preferred when there is no encoding |
| 26790 | overlap. */ |
| 26791 | if (newimm == (unsigned int) FAIL |
| 26792 | && ((temp >> DATA_OP_SHIFT) & 0xf) == OPCODE_MOV |
| 26793 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2) |
| 26794 | && !((temp >> SBIT_SHIFT) & 0x1) |
| 26795 | && value >= 0 && value <= 0xffff) |
| 26796 | { |
| 26797 | /* Clear bits[23:20] to change encoding from A1 to A2. */ |
| 26798 | temp &= 0xff0fffff; |
| 26799 | /* Encoding high 4bits imm. Code below will encode the remaining |
| 26800 | low 12bits. */ |
| 26801 | temp |= (value & 0x0000f000) << 4; |
| 26802 | newimm = value & 0x00000fff; |
| 26803 | } |
| 26804 | } |
| 26805 | |
| 26806 | if (newimm == (unsigned int) FAIL) |
| 26807 | { |
| 26808 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 26809 | _("invalid constant (%lx) after fixup"), |
| 26810 | (unsigned long) value); |
| 26811 | break; |
| 26812 | } |
| 26813 | |
| 26814 | newimm |= (temp & 0xfffff000); |
| 26815 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); |
| 26816 | break; |
| 26817 | |
| 26818 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
| 26819 | { |
| 26820 | unsigned int highpart = 0; |
| 26821 | unsigned int newinsn = 0xe1a00000; /* nop. */ |
| 26822 | |
| 26823 | if (fixP->fx_addsy) |
| 26824 | { |
| 26825 | const char *msg = 0; |
| 26826 | |
| 26827 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
| 26828 | msg = _("undefined symbol %s used as an immediate value"); |
| 26829 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) |
| 26830 | msg = _("symbol %s is in a different section"); |
| 26831 | else if (S_IS_WEAK (fixP->fx_addsy)) |
| 26832 | msg = _("symbol %s is weak and may be overridden later"); |
| 26833 | |
| 26834 | if (msg) |
| 26835 | { |
| 26836 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 26837 | msg, S_GET_NAME (fixP->fx_addsy)); |
| 26838 | break; |
| 26839 | } |
| 26840 | } |
| 26841 | |
| 26842 | newimm = encode_arm_immediate (value); |
| 26843 | temp = md_chars_to_number (buf, INSN_SIZE); |
| 26844 | |
| 26845 | /* If the instruction will fail, see if we can fix things up by |
| 26846 | changing the opcode. */ |
| 26847 | if (newimm == (unsigned int) FAIL |
| 26848 | && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) |
| 26849 | { |
| 26850 | /* No ? OK - try using two ADD instructions to generate |
| 26851 | the value. */ |
| 26852 | newimm = validate_immediate_twopart (value, & highpart); |
| 26853 | |
| 26854 | /* Yes - then make sure that the second instruction is |
| 26855 | also an add. */ |
| 26856 | if (newimm != (unsigned int) FAIL) |
| 26857 | newinsn = temp; |
| 26858 | /* Still No ? Try using a negated value. */ |
| 26859 | else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) |
| 26860 | temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; |
| 26861 | /* Otherwise - give up. */ |
| 26862 | else |
| 26863 | { |
| 26864 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 26865 | _("unable to compute ADRL instructions for PC offset of 0x%lx"), |
| 26866 | (long) value); |
| 26867 | break; |
| 26868 | } |
| 26869 | |
| 26870 | /* Replace the first operand in the 2nd instruction (which |
| 26871 | is the PC) with the destination register. We have |
| 26872 | already added in the PC in the first instruction and we |
| 26873 | do not want to do it again. */ |
| 26874 | newinsn &= ~ 0xf0000; |
| 26875 | newinsn |= ((newinsn & 0x0f000) << 4); |
| 26876 | } |
| 26877 | |
| 26878 | newimm |= (temp & 0xfffff000); |
| 26879 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); |
| 26880 | |
| 26881 | highpart |= (newinsn & 0xfffff000); |
| 26882 | md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); |
| 26883 | } |
| 26884 | break; |
| 26885 | |
| 26886 | case BFD_RELOC_ARM_OFFSET_IMM: |
| 26887 | if (!fixP->fx_done && seg->use_rela_p) |
| 26888 | value = 0; |
| 26889 | /* Fall through. */ |
| 26890 | |
| 26891 | case BFD_RELOC_ARM_LITERAL: |
| 26892 | sign = value > 0; |
| 26893 | |
| 26894 | if (value < 0) |
| 26895 | value = - value; |
| 26896 | |
| 26897 | if (validate_offset_imm (value, 0) == FAIL) |
| 26898 | { |
| 26899 | if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) |
| 26900 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 26901 | _("invalid literal constant: pool needs to be closer")); |
| 26902 | else |
| 26903 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 26904 | _("bad immediate value for offset (%ld)"), |
| 26905 | (long) value); |
| 26906 | break; |
| 26907 | } |
| 26908 | |
| 26909 | newval = md_chars_to_number (buf, INSN_SIZE); |
| 26910 | if (value == 0) |
| 26911 | newval &= 0xfffff000; |
| 26912 | else |
| 26913 | { |
| 26914 | newval &= 0xff7ff000; |
| 26915 | newval |= value | (sign ? INDEX_UP : 0); |
| 26916 | } |
| 26917 | md_number_to_chars (buf, newval, INSN_SIZE); |
| 26918 | break; |
| 26919 | |
| 26920 | case BFD_RELOC_ARM_OFFSET_IMM8: |
| 26921 | case BFD_RELOC_ARM_HWLITERAL: |
| 26922 | sign = value > 0; |
| 26923 | |
| 26924 | if (value < 0) |
| 26925 | value = - value; |
| 26926 | |
| 26927 | if (validate_offset_imm (value, 1) == FAIL) |
| 26928 | { |
| 26929 | if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) |
| 26930 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 26931 | _("invalid literal constant: pool needs to be closer")); |
| 26932 | else |
| 26933 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 26934 | _("bad immediate value for 8-bit offset (%ld)"), |
| 26935 | (long) value); |
| 26936 | break; |
| 26937 | } |
| 26938 | |
| 26939 | newval = md_chars_to_number (buf, INSN_SIZE); |
| 26940 | if (value == 0) |
| 26941 | newval &= 0xfffff0f0; |
| 26942 | else |
| 26943 | { |
| 26944 | newval &= 0xff7ff0f0; |
| 26945 | newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); |
| 26946 | } |
| 26947 | md_number_to_chars (buf, newval, INSN_SIZE); |
| 26948 | break; |
| 26949 | |
| 26950 | case BFD_RELOC_ARM_T32_OFFSET_U8: |
| 26951 | if (value < 0 || value > 1020 || value % 4 != 0) |
| 26952 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 26953 | _("bad immediate value for offset (%ld)"), (long) value); |
| 26954 | value /= 4; |
| 26955 | |
| 26956 | newval = md_chars_to_number (buf+2, THUMB_SIZE); |
| 26957 | newval |= value; |
| 26958 | md_number_to_chars (buf+2, newval, THUMB_SIZE); |
| 26959 | break; |
| 26960 | |
| 26961 | case BFD_RELOC_ARM_T32_OFFSET_IMM: |
| 26962 | /* This is a complicated relocation used for all varieties of Thumb32 |
| 26963 | load/store instruction with immediate offset: |
| 26964 | |
| 26965 | 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, |
| 26966 | *4, optional writeback(W) |
| 26967 | (doubleword load/store) |
| 26968 | |
| 26969 | 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel |
| 26970 | 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit |
| 26971 | 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) |
| 26972 | 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit |
| 26973 | 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit |
| 26974 | |
| 26975 | Uppercase letters indicate bits that are already encoded at |
| 26976 | this point. Lowercase letters are our problem. For the |
| 26977 | second block of instructions, the secondary opcode nybble |
| 26978 | (bits 8..11) is present, and bit 23 is zero, even if this is |
| 26979 | a PC-relative operation. */ |
| 26980 | newval = md_chars_to_number (buf, THUMB_SIZE); |
| 26981 | newval <<= 16; |
| 26982 | newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); |
| 26983 | |
| 26984 | if ((newval & 0xf0000000) == 0xe0000000) |
| 26985 | { |
| 26986 | /* Doubleword load/store: 8-bit offset, scaled by 4. */ |
| 26987 | if (value >= 0) |
| 26988 | newval |= (1 << 23); |
| 26989 | else |
| 26990 | value = -value; |
| 26991 | if (value % 4 != 0) |
| 26992 | { |
| 26993 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 26994 | _("offset not a multiple of 4")); |
| 26995 | break; |
| 26996 | } |
| 26997 | value /= 4; |
| 26998 | if (value > 0xff) |
| 26999 | { |
| 27000 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27001 | _("offset out of range")); |
| 27002 | break; |
| 27003 | } |
| 27004 | newval &= ~0xff; |
| 27005 | } |
| 27006 | else if ((newval & 0x000f0000) == 0x000f0000) |
| 27007 | { |
| 27008 | /* PC-relative, 12-bit offset. */ |
| 27009 | if (value >= 0) |
| 27010 | newval |= (1 << 23); |
| 27011 | else |
| 27012 | value = -value; |
| 27013 | if (value > 0xfff) |
| 27014 | { |
| 27015 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27016 | _("offset out of range")); |
| 27017 | break; |
| 27018 | } |
| 27019 | newval &= ~0xfff; |
| 27020 | } |
| 27021 | else if ((newval & 0x00000100) == 0x00000100) |
| 27022 | { |
| 27023 | /* Writeback: 8-bit, +/- offset. */ |
| 27024 | if (value >= 0) |
| 27025 | newval |= (1 << 9); |
| 27026 | else |
| 27027 | value = -value; |
| 27028 | if (value > 0xff) |
| 27029 | { |
| 27030 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27031 | _("offset out of range")); |
| 27032 | break; |
| 27033 | } |
| 27034 | newval &= ~0xff; |
| 27035 | } |
| 27036 | else if ((newval & 0x00000f00) == 0x00000e00) |
| 27037 | { |
| 27038 | /* T-instruction: positive 8-bit offset. */ |
| 27039 | if (value < 0 || value > 0xff) |
| 27040 | { |
| 27041 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27042 | _("offset out of range")); |
| 27043 | break; |
| 27044 | } |
| 27045 | newval &= ~0xff; |
| 27046 | newval |= value; |
| 27047 | } |
| 27048 | else |
| 27049 | { |
| 27050 | /* Positive 12-bit or negative 8-bit offset. */ |
| 27051 | int limit; |
| 27052 | if (value >= 0) |
| 27053 | { |
| 27054 | newval |= (1 << 23); |
| 27055 | limit = 0xfff; |
| 27056 | } |
| 27057 | else |
| 27058 | { |
| 27059 | value = -value; |
| 27060 | limit = 0xff; |
| 27061 | } |
| 27062 | if (value > limit) |
| 27063 | { |
| 27064 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27065 | _("offset out of range")); |
| 27066 | break; |
| 27067 | } |
| 27068 | newval &= ~limit; |
| 27069 | } |
| 27070 | |
| 27071 | newval |= value; |
| 27072 | md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); |
| 27073 | md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); |
| 27074 | break; |
| 27075 | |
| 27076 | case BFD_RELOC_ARM_SHIFT_IMM: |
| 27077 | newval = md_chars_to_number (buf, INSN_SIZE); |
| 27078 | if (((unsigned long) value) > 32 |
| 27079 | || (value == 32 |
| 27080 | && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) |
| 27081 | { |
| 27082 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27083 | _("shift expression is too large")); |
| 27084 | break; |
| 27085 | } |
| 27086 | |
| 27087 | if (value == 0) |
| 27088 | /* Shifts of zero must be done as lsl. */ |
| 27089 | newval &= ~0x60; |
| 27090 | else if (value == 32) |
| 27091 | value = 0; |
| 27092 | newval &= 0xfffff07f; |
| 27093 | newval |= (value & 0x1f) << 7; |
| 27094 | md_number_to_chars (buf, newval, INSN_SIZE); |
| 27095 | break; |
| 27096 | |
| 27097 | case BFD_RELOC_ARM_T32_IMMEDIATE: |
| 27098 | case BFD_RELOC_ARM_T32_ADD_IMM: |
| 27099 | case BFD_RELOC_ARM_T32_IMM12: |
| 27100 | case BFD_RELOC_ARM_T32_ADD_PC12: |
| 27101 | /* We claim that this fixup has been processed here, |
| 27102 | even if in fact we generate an error because we do |
| 27103 | not have a reloc for it, so tc_gen_reloc will reject it. */ |
| 27104 | fixP->fx_done = 1; |
| 27105 | |
| 27106 | if (fixP->fx_addsy |
| 27107 | && ! S_IS_DEFINED (fixP->fx_addsy)) |
| 27108 | { |
| 27109 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27110 | _("undefined symbol %s used as an immediate value"), |
| 27111 | S_GET_NAME (fixP->fx_addsy)); |
| 27112 | break; |
| 27113 | } |
| 27114 | |
| 27115 | newval = md_chars_to_number (buf, THUMB_SIZE); |
| 27116 | newval <<= 16; |
| 27117 | newval |= md_chars_to_number (buf+2, THUMB_SIZE); |
| 27118 | |
| 27119 | newimm = FAIL; |
| 27120 | if ((fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE |
| 27121 | /* ARMv8-M Baseline MOV will reach here, but it doesn't support |
| 27122 | Thumb2 modified immediate encoding (T2). */ |
| 27123 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)) |
| 27124 | || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) |
| 27125 | { |
| 27126 | newimm = encode_thumb32_immediate (value); |
| 27127 | if (newimm == (unsigned int) FAIL) |
| 27128 | newimm = thumb32_negate_data_op (&newval, value); |
| 27129 | } |
| 27130 | if (newimm == (unsigned int) FAIL) |
| 27131 | { |
| 27132 | if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE) |
| 27133 | { |
| 27134 | /* Turn add/sum into addw/subw. */ |
| 27135 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) |
| 27136 | newval = (newval & 0xfeffffff) | 0x02000000; |
| 27137 | /* No flat 12-bit imm encoding for addsw/subsw. */ |
| 27138 | if ((newval & 0x00100000) == 0) |
| 27139 | { |
| 27140 | /* 12 bit immediate for addw/subw. */ |
| 27141 | if (value < 0) |
| 27142 | { |
| 27143 | value = -value; |
| 27144 | newval ^= 0x00a00000; |
| 27145 | } |
| 27146 | if (value > 0xfff) |
| 27147 | newimm = (unsigned int) FAIL; |
| 27148 | else |
| 27149 | newimm = value; |
| 27150 | } |
| 27151 | } |
| 27152 | else |
| 27153 | { |
| 27154 | /* MOV accepts both Thumb2 modified immediate (T2 encoding) and |
| 27155 | UINT16 (T3 encoding), MOVW only accepts UINT16. When |
| 27156 | disassembling, MOV is preferred when there is no encoding |
| 27157 | overlap. */ |
| 27158 | if (((newval >> T2_DATA_OP_SHIFT) & 0xf) == T2_OPCODE_ORR |
| 27159 | /* NOTE: MOV uses the ORR opcode in Thumb 2 mode |
| 27160 | but with the Rn field [19:16] set to 1111. */ |
| 27161 | && (((newval >> 16) & 0xf) == 0xf) |
| 27162 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m) |
| 27163 | && !((newval >> T2_SBIT_SHIFT) & 0x1) |
| 27164 | && value >= 0 && value <= 0xffff) |
| 27165 | { |
| 27166 | /* Toggle bit[25] to change encoding from T2 to T3. */ |
| 27167 | newval ^= 1 << 25; |
| 27168 | /* Clear bits[19:16]. */ |
| 27169 | newval &= 0xfff0ffff; |
| 27170 | /* Encoding high 4bits imm. Code below will encode the |
| 27171 | remaining low 12bits. */ |
| 27172 | newval |= (value & 0x0000f000) << 4; |
| 27173 | newimm = value & 0x00000fff; |
| 27174 | } |
| 27175 | } |
| 27176 | } |
| 27177 | |
| 27178 | if (newimm == (unsigned int)FAIL) |
| 27179 | { |
| 27180 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27181 | _("invalid constant (%lx) after fixup"), |
| 27182 | (unsigned long) value); |
| 27183 | break; |
| 27184 | } |
| 27185 | |
| 27186 | newval |= (newimm & 0x800) << 15; |
| 27187 | newval |= (newimm & 0x700) << 4; |
| 27188 | newval |= (newimm & 0x0ff); |
| 27189 | |
| 27190 | md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); |
| 27191 | md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); |
| 27192 | break; |
| 27193 | |
| 27194 | case BFD_RELOC_ARM_SMC: |
| 27195 | if (((unsigned long) value) > 0xffff) |
| 27196 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27197 | _("invalid smc expression")); |
| 27198 | newval = md_chars_to_number (buf, INSN_SIZE); |
| 27199 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); |
| 27200 | md_number_to_chars (buf, newval, INSN_SIZE); |
| 27201 | break; |
| 27202 | |
| 27203 | case BFD_RELOC_ARM_HVC: |
| 27204 | if (((unsigned long) value) > 0xffff) |
| 27205 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27206 | _("invalid hvc expression")); |
| 27207 | newval = md_chars_to_number (buf, INSN_SIZE); |
| 27208 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); |
| 27209 | md_number_to_chars (buf, newval, INSN_SIZE); |
| 27210 | break; |
| 27211 | |
| 27212 | case BFD_RELOC_ARM_SWI: |
| 27213 | if (fixP->tc_fix_data != 0) |
| 27214 | { |
| 27215 | if (((unsigned long) value) > 0xff) |
| 27216 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27217 | _("invalid swi expression")); |
| 27218 | newval = md_chars_to_number (buf, THUMB_SIZE); |
| 27219 | newval |= value; |
| 27220 | md_number_to_chars (buf, newval, THUMB_SIZE); |
| 27221 | } |
| 27222 | else |
| 27223 | { |
| 27224 | if (((unsigned long) value) > 0x00ffffff) |
| 27225 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27226 | _("invalid swi expression")); |
| 27227 | newval = md_chars_to_number (buf, INSN_SIZE); |
| 27228 | newval |= value; |
| 27229 | md_number_to_chars (buf, newval, INSN_SIZE); |
| 27230 | } |
| 27231 | break; |
| 27232 | |
| 27233 | case BFD_RELOC_ARM_MULTI: |
| 27234 | if (((unsigned long) value) > 0xffff) |
| 27235 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27236 | _("invalid expression in load/store multiple")); |
| 27237 | newval = value | md_chars_to_number (buf, INSN_SIZE); |
| 27238 | md_number_to_chars (buf, newval, INSN_SIZE); |
| 27239 | break; |
| 27240 | |
| 27241 | #ifdef OBJ_ELF |
| 27242 | case BFD_RELOC_ARM_PCREL_CALL: |
| 27243 | |
| 27244 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
| 27245 | && fixP->fx_addsy |
| 27246 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
| 27247 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
| 27248 | && THUMB_IS_FUNC (fixP->fx_addsy)) |
| 27249 | /* Flip the bl to blx. This is a simple flip |
| 27250 | bit here because we generate PCREL_CALL for |
| 27251 | unconditional bls. */ |
| 27252 | { |
| 27253 | newval = md_chars_to_number (buf, INSN_SIZE); |
| 27254 | newval = newval | 0x10000000; |
| 27255 | md_number_to_chars (buf, newval, INSN_SIZE); |
| 27256 | temp = 1; |
| 27257 | fixP->fx_done = 1; |
| 27258 | } |
| 27259 | else |
| 27260 | temp = 3; |
| 27261 | goto arm_branch_common; |
| 27262 | |
| 27263 | case BFD_RELOC_ARM_PCREL_JUMP: |
| 27264 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
| 27265 | && fixP->fx_addsy |
| 27266 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
| 27267 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
| 27268 | && THUMB_IS_FUNC (fixP->fx_addsy)) |
| 27269 | { |
| 27270 | /* This would map to a bl<cond>, b<cond>, |
| 27271 | b<always> to a Thumb function. We |
| 27272 | need to force a relocation for this particular |
| 27273 | case. */ |
| 27274 | newval = md_chars_to_number (buf, INSN_SIZE); |
| 27275 | fixP->fx_done = 0; |
| 27276 | } |
| 27277 | /* Fall through. */ |
| 27278 | |
| 27279 | case BFD_RELOC_ARM_PLT32: |
| 27280 | #endif |
| 27281 | case BFD_RELOC_ARM_PCREL_BRANCH: |
| 27282 | temp = 3; |
| 27283 | goto arm_branch_common; |
| 27284 | |
| 27285 | case BFD_RELOC_ARM_PCREL_BLX: |
| 27286 | |
| 27287 | temp = 1; |
| 27288 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
| 27289 | && fixP->fx_addsy |
| 27290 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
| 27291 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
| 27292 | && ARM_IS_FUNC (fixP->fx_addsy)) |
| 27293 | { |
| 27294 | /* Flip the blx to a bl and warn. */ |
| 27295 | const char *name = S_GET_NAME (fixP->fx_addsy); |
| 27296 | newval = 0xeb000000; |
| 27297 | as_warn_where (fixP->fx_file, fixP->fx_line, |
| 27298 | _("blx to '%s' an ARM ISA state function changed to bl"), |
| 27299 | name); |
| 27300 | md_number_to_chars (buf, newval, INSN_SIZE); |
| 27301 | temp = 3; |
| 27302 | fixP->fx_done = 1; |
| 27303 | } |
| 27304 | |
| 27305 | #ifdef OBJ_ELF |
| 27306 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) |
| 27307 | fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL; |
| 27308 | #endif |
| 27309 | |
| 27310 | arm_branch_common: |
| 27311 | /* We are going to store value (shifted right by two) in the |
| 27312 | instruction, in a 24 bit, signed field. Bits 26 through 32 either |
| 27313 | all clear or all set and bit 0 must be clear. For B/BL bit 1 must |
| 27314 | also be clear. */ |
| 27315 | if (value & temp) |
| 27316 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27317 | _("misaligned branch destination")); |
| 27318 | if ((value & (offsetT)0xfe000000) != (offsetT)0 |
| 27319 | && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) |
| 27320 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
| 27321 | |
| 27322 | if (fixP->fx_done || !seg->use_rela_p) |
| 27323 | { |
| 27324 | newval = md_chars_to_number (buf, INSN_SIZE); |
| 27325 | newval |= (value >> 2) & 0x00ffffff; |
| 27326 | /* Set the H bit on BLX instructions. */ |
| 27327 | if (temp == 1) |
| 27328 | { |
| 27329 | if (value & 2) |
| 27330 | newval |= 0x01000000; |
| 27331 | else |
| 27332 | newval &= ~0x01000000; |
| 27333 | } |
| 27334 | md_number_to_chars (buf, newval, INSN_SIZE); |
| 27335 | } |
| 27336 | break; |
| 27337 | |
| 27338 | case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */ |
| 27339 | /* CBZ can only branch forward. */ |
| 27340 | |
| 27341 | /* Attempts to use CBZ to branch to the next instruction |
| 27342 | (which, strictly speaking, are prohibited) will be turned into |
| 27343 | no-ops. |
| 27344 | |
| 27345 | FIXME: It may be better to remove the instruction completely and |
| 27346 | perform relaxation. */ |
| 27347 | if (value == -2) |
| 27348 | { |
| 27349 | newval = md_chars_to_number (buf, THUMB_SIZE); |
| 27350 | newval = 0xbf00; /* NOP encoding T1 */ |
| 27351 | md_number_to_chars (buf, newval, THUMB_SIZE); |
| 27352 | } |
| 27353 | else |
| 27354 | { |
| 27355 | if (value & ~0x7e) |
| 27356 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
| 27357 | |
| 27358 | if (fixP->fx_done || !seg->use_rela_p) |
| 27359 | { |
| 27360 | newval = md_chars_to_number (buf, THUMB_SIZE); |
| 27361 | newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); |
| 27362 | md_number_to_chars (buf, newval, THUMB_SIZE); |
| 27363 | } |
| 27364 | } |
| 27365 | break; |
| 27366 | |
| 27367 | case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ |
| 27368 | if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) |
| 27369 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
| 27370 | |
| 27371 | if (fixP->fx_done || !seg->use_rela_p) |
| 27372 | { |
| 27373 | newval = md_chars_to_number (buf, THUMB_SIZE); |
| 27374 | newval |= (value & 0x1ff) >> 1; |
| 27375 | md_number_to_chars (buf, newval, THUMB_SIZE); |
| 27376 | } |
| 27377 | break; |
| 27378 | |
| 27379 | case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ |
| 27380 | if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) |
| 27381 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
| 27382 | |
| 27383 | if (fixP->fx_done || !seg->use_rela_p) |
| 27384 | { |
| 27385 | newval = md_chars_to_number (buf, THUMB_SIZE); |
| 27386 | newval |= (value & 0xfff) >> 1; |
| 27387 | md_number_to_chars (buf, newval, THUMB_SIZE); |
| 27388 | } |
| 27389 | break; |
| 27390 | |
| 27391 | case BFD_RELOC_THUMB_PCREL_BRANCH20: |
| 27392 | if (fixP->fx_addsy |
| 27393 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
| 27394 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
| 27395 | && ARM_IS_FUNC (fixP->fx_addsy) |
| 27396 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) |
| 27397 | { |
| 27398 | /* Force a relocation for a branch 20 bits wide. */ |
| 27399 | fixP->fx_done = 0; |
| 27400 | } |
| 27401 | if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff)) |
| 27402 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27403 | _("conditional branch out of range")); |
| 27404 | |
| 27405 | if (fixP->fx_done || !seg->use_rela_p) |
| 27406 | { |
| 27407 | offsetT newval2; |
| 27408 | addressT S, J1, J2, lo, hi; |
| 27409 | |
| 27410 | S = (value & 0x00100000) >> 20; |
| 27411 | J2 = (value & 0x00080000) >> 19; |
| 27412 | J1 = (value & 0x00040000) >> 18; |
| 27413 | hi = (value & 0x0003f000) >> 12; |
| 27414 | lo = (value & 0x00000ffe) >> 1; |
| 27415 | |
| 27416 | newval = md_chars_to_number (buf, THUMB_SIZE); |
| 27417 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); |
| 27418 | newval |= (S << 10) | hi; |
| 27419 | newval2 |= (J1 << 13) | (J2 << 11) | lo; |
| 27420 | md_number_to_chars (buf, newval, THUMB_SIZE); |
| 27421 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); |
| 27422 | } |
| 27423 | break; |
| 27424 | |
| 27425 | case BFD_RELOC_THUMB_PCREL_BLX: |
| 27426 | /* If there is a blx from a thumb state function to |
| 27427 | another thumb function flip this to a bl and warn |
| 27428 | about it. */ |
| 27429 | |
| 27430 | if (fixP->fx_addsy |
| 27431 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
| 27432 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
| 27433 | && THUMB_IS_FUNC (fixP->fx_addsy)) |
| 27434 | { |
| 27435 | const char *name = S_GET_NAME (fixP->fx_addsy); |
| 27436 | as_warn_where (fixP->fx_file, fixP->fx_line, |
| 27437 | _("blx to Thumb func '%s' from Thumb ISA state changed to bl"), |
| 27438 | name); |
| 27439 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); |
| 27440 | newval = newval | 0x1000; |
| 27441 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); |
| 27442 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; |
| 27443 | fixP->fx_done = 1; |
| 27444 | } |
| 27445 | |
| 27446 | |
| 27447 | goto thumb_bl_common; |
| 27448 | |
| 27449 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
| 27450 | /* A bl from Thumb state ISA to an internal ARM state function |
| 27451 | is converted to a blx. */ |
| 27452 | if (fixP->fx_addsy |
| 27453 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
| 27454 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
| 27455 | && ARM_IS_FUNC (fixP->fx_addsy) |
| 27456 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) |
| 27457 | { |
| 27458 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); |
| 27459 | newval = newval & ~0x1000; |
| 27460 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); |
| 27461 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX; |
| 27462 | fixP->fx_done = 1; |
| 27463 | } |
| 27464 | |
| 27465 | thumb_bl_common: |
| 27466 | |
| 27467 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) |
| 27468 | /* For a BLX instruction, make sure that the relocation is rounded up |
| 27469 | to a word boundary. This follows the semantics of the instruction |
| 27470 | which specifies that bit 1 of the target address will come from bit |
| 27471 | 1 of the base address. */ |
| 27472 | value = (value + 3) & ~ 3; |
| 27473 | |
| 27474 | #ifdef OBJ_ELF |
| 27475 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 |
| 27476 | && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) |
| 27477 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; |
| 27478 | #endif |
| 27479 | |
| 27480 | if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) |
| 27481 | { |
| 27482 | if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))) |
| 27483 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
| 27484 | else if ((value & ~0x1ffffff) |
| 27485 | && ((value & ~0x1ffffff) != ~0x1ffffff)) |
| 27486 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27487 | _("Thumb2 branch out of range")); |
| 27488 | } |
| 27489 | |
| 27490 | if (fixP->fx_done || !seg->use_rela_p) |
| 27491 | encode_thumb2_b_bl_offset (buf, value); |
| 27492 | |
| 27493 | break; |
| 27494 | |
| 27495 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
| 27496 | if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff)) |
| 27497 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
| 27498 | |
| 27499 | if (fixP->fx_done || !seg->use_rela_p) |
| 27500 | encode_thumb2_b_bl_offset (buf, value); |
| 27501 | |
| 27502 | break; |
| 27503 | |
| 27504 | case BFD_RELOC_8: |
| 27505 | if (fixP->fx_done || !seg->use_rela_p) |
| 27506 | *buf = value; |
| 27507 | break; |
| 27508 | |
| 27509 | case BFD_RELOC_16: |
| 27510 | if (fixP->fx_done || !seg->use_rela_p) |
| 27511 | md_number_to_chars (buf, value, 2); |
| 27512 | break; |
| 27513 | |
| 27514 | #ifdef OBJ_ELF |
| 27515 | case BFD_RELOC_ARM_TLS_CALL: |
| 27516 | case BFD_RELOC_ARM_THM_TLS_CALL: |
| 27517 | case BFD_RELOC_ARM_TLS_DESCSEQ: |
| 27518 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: |
| 27519 | case BFD_RELOC_ARM_TLS_GOTDESC: |
| 27520 | case BFD_RELOC_ARM_TLS_GD32: |
| 27521 | case BFD_RELOC_ARM_TLS_LE32: |
| 27522 | case BFD_RELOC_ARM_TLS_IE32: |
| 27523 | case BFD_RELOC_ARM_TLS_LDM32: |
| 27524 | case BFD_RELOC_ARM_TLS_LDO32: |
| 27525 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
| 27526 | break; |
| 27527 | |
| 27528 | /* Same handling as above, but with the arm_fdpic guard. */ |
| 27529 | case BFD_RELOC_ARM_TLS_GD32_FDPIC: |
| 27530 | case BFD_RELOC_ARM_TLS_IE32_FDPIC: |
| 27531 | case BFD_RELOC_ARM_TLS_LDM32_FDPIC: |
| 27532 | if (arm_fdpic) |
| 27533 | { |
| 27534 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
| 27535 | } |
| 27536 | else |
| 27537 | { |
| 27538 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27539 | _("Relocation supported only in FDPIC mode")); |
| 27540 | } |
| 27541 | break; |
| 27542 | |
| 27543 | case BFD_RELOC_ARM_GOT32: |
| 27544 | case BFD_RELOC_ARM_GOTOFF: |
| 27545 | break; |
| 27546 | |
| 27547 | case BFD_RELOC_ARM_GOT_PREL: |
| 27548 | if (fixP->fx_done || !seg->use_rela_p) |
| 27549 | md_number_to_chars (buf, value, 4); |
| 27550 | break; |
| 27551 | |
| 27552 | case BFD_RELOC_ARM_TARGET2: |
| 27553 | /* TARGET2 is not partial-inplace, so we need to write the |
| 27554 | addend here for REL targets, because it won't be written out |
| 27555 | during reloc processing later. */ |
| 27556 | if (fixP->fx_done || !seg->use_rela_p) |
| 27557 | md_number_to_chars (buf, fixP->fx_offset, 4); |
| 27558 | break; |
| 27559 | |
| 27560 | /* Relocations for FDPIC. */ |
| 27561 | case BFD_RELOC_ARM_GOTFUNCDESC: |
| 27562 | case BFD_RELOC_ARM_GOTOFFFUNCDESC: |
| 27563 | case BFD_RELOC_ARM_FUNCDESC: |
| 27564 | if (arm_fdpic) |
| 27565 | { |
| 27566 | if (fixP->fx_done || !seg->use_rela_p) |
| 27567 | md_number_to_chars (buf, 0, 4); |
| 27568 | } |
| 27569 | else |
| 27570 | { |
| 27571 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27572 | _("Relocation supported only in FDPIC mode")); |
| 27573 | } |
| 27574 | break; |
| 27575 | #endif |
| 27576 | |
| 27577 | case BFD_RELOC_RVA: |
| 27578 | case BFD_RELOC_32: |
| 27579 | case BFD_RELOC_ARM_TARGET1: |
| 27580 | case BFD_RELOC_ARM_ROSEGREL32: |
| 27581 | case BFD_RELOC_ARM_SBREL32: |
| 27582 | case BFD_RELOC_32_PCREL: |
| 27583 | #ifdef TE_PE |
| 27584 | case BFD_RELOC_32_SECREL: |
| 27585 | #endif |
| 27586 | if (fixP->fx_done || !seg->use_rela_p) |
| 27587 | #ifdef TE_WINCE |
| 27588 | /* For WinCE we only do this for pcrel fixups. */ |
| 27589 | if (fixP->fx_done || fixP->fx_pcrel) |
| 27590 | #endif |
| 27591 | md_number_to_chars (buf, value, 4); |
| 27592 | break; |
| 27593 | |
| 27594 | #ifdef OBJ_ELF |
| 27595 | case BFD_RELOC_ARM_PREL31: |
| 27596 | if (fixP->fx_done || !seg->use_rela_p) |
| 27597 | { |
| 27598 | newval = md_chars_to_number (buf, 4) & 0x80000000; |
| 27599 | if ((value ^ (value >> 1)) & 0x40000000) |
| 27600 | { |
| 27601 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27602 | _("rel31 relocation overflow")); |
| 27603 | } |
| 27604 | newval |= value & 0x7fffffff; |
| 27605 | md_number_to_chars (buf, newval, 4); |
| 27606 | } |
| 27607 | break; |
| 27608 | #endif |
| 27609 | |
| 27610 | case BFD_RELOC_ARM_CP_OFF_IMM: |
| 27611 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
| 27612 | case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM: |
| 27613 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM) |
| 27614 | newval = md_chars_to_number (buf, INSN_SIZE); |
| 27615 | else |
| 27616 | newval = get_thumb32_insn (buf); |
| 27617 | if ((newval & 0x0f200f00) == 0x0d000900) |
| 27618 | { |
| 27619 | /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic |
| 27620 | has permitted values that are multiples of 2, in the range 0 |
| 27621 | to 510. */ |
| 27622 | if (value < -510 || value > 510 || (value & 1)) |
| 27623 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27624 | _("co-processor offset out of range")); |
| 27625 | } |
| 27626 | else if ((newval & 0xfe001f80) == 0xec000f80) |
| 27627 | { |
| 27628 | if (value < -511 || value > 512 || (value & 3)) |
| 27629 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27630 | _("co-processor offset out of range")); |
| 27631 | } |
| 27632 | else if (value < -1023 || value > 1023 || (value & 3)) |
| 27633 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27634 | _("co-processor offset out of range")); |
| 27635 | cp_off_common: |
| 27636 | sign = value > 0; |
| 27637 | if (value < 0) |
| 27638 | value = -value; |
| 27639 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
| 27640 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) |
| 27641 | newval = md_chars_to_number (buf, INSN_SIZE); |
| 27642 | else |
| 27643 | newval = get_thumb32_insn (buf); |
| 27644 | if (value == 0) |
| 27645 | { |
| 27646 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM) |
| 27647 | newval &= 0xffffff80; |
| 27648 | else |
| 27649 | newval &= 0xffffff00; |
| 27650 | } |
| 27651 | else |
| 27652 | { |
| 27653 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM) |
| 27654 | newval &= 0xff7fff80; |
| 27655 | else |
| 27656 | newval &= 0xff7fff00; |
| 27657 | if ((newval & 0x0f200f00) == 0x0d000900) |
| 27658 | { |
| 27659 | /* This is a fp16 vstr/vldr. |
| 27660 | |
| 27661 | It requires the immediate offset in the instruction is shifted |
| 27662 | left by 1 to be a half-word offset. |
| 27663 | |
| 27664 | Here, left shift by 1 first, and later right shift by 2 |
| 27665 | should get the right offset. */ |
| 27666 | value <<= 1; |
| 27667 | } |
| 27668 | newval |= (value >> 2) | (sign ? INDEX_UP : 0); |
| 27669 | } |
| 27670 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
| 27671 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) |
| 27672 | md_number_to_chars (buf, newval, INSN_SIZE); |
| 27673 | else |
| 27674 | put_thumb32_insn (buf, newval); |
| 27675 | break; |
| 27676 | |
| 27677 | case BFD_RELOC_ARM_CP_OFF_IMM_S2: |
| 27678 | case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: |
| 27679 | if (value < -255 || value > 255) |
| 27680 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27681 | _("co-processor offset out of range")); |
| 27682 | value *= 4; |
| 27683 | goto cp_off_common; |
| 27684 | |
| 27685 | case BFD_RELOC_ARM_THUMB_OFFSET: |
| 27686 | newval = md_chars_to_number (buf, THUMB_SIZE); |
| 27687 | /* Exactly what ranges, and where the offset is inserted depends |
| 27688 | on the type of instruction, we can establish this from the |
| 27689 | top 4 bits. */ |
| 27690 | switch (newval >> 12) |
| 27691 | { |
| 27692 | case 4: /* PC load. */ |
| 27693 | /* Thumb PC loads are somewhat odd, bit 1 of the PC is |
| 27694 | forced to zero for these loads; md_pcrel_from has already |
| 27695 | compensated for this. */ |
| 27696 | if (value & 3) |
| 27697 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27698 | _("invalid offset, target not word aligned (0x%08lX)"), |
| 27699 | (((unsigned long) fixP->fx_frag->fr_address |
| 27700 | + (unsigned long) fixP->fx_where) & ~3) |
| 27701 | + (unsigned long) value); |
| 27702 | |
| 27703 | if (value & ~0x3fc) |
| 27704 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27705 | _("invalid offset, value too big (0x%08lX)"), |
| 27706 | (long) value); |
| 27707 | |
| 27708 | newval |= value >> 2; |
| 27709 | break; |
| 27710 | |
| 27711 | case 9: /* SP load/store. */ |
| 27712 | if (value & ~0x3fc) |
| 27713 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27714 | _("invalid offset, value too big (0x%08lX)"), |
| 27715 | (long) value); |
| 27716 | newval |= value >> 2; |
| 27717 | break; |
| 27718 | |
| 27719 | case 6: /* Word load/store. */ |
| 27720 | if (value & ~0x7c) |
| 27721 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27722 | _("invalid offset, value too big (0x%08lX)"), |
| 27723 | (long) value); |
| 27724 | newval |= value << 4; /* 6 - 2. */ |
| 27725 | break; |
| 27726 | |
| 27727 | case 7: /* Byte load/store. */ |
| 27728 | if (value & ~0x1f) |
| 27729 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27730 | _("invalid offset, value too big (0x%08lX)"), |
| 27731 | (long) value); |
| 27732 | newval |= value << 6; |
| 27733 | break; |
| 27734 | |
| 27735 | case 8: /* Halfword load/store. */ |
| 27736 | if (value & ~0x3e) |
| 27737 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27738 | _("invalid offset, value too big (0x%08lX)"), |
| 27739 | (long) value); |
| 27740 | newval |= value << 5; /* 6 - 1. */ |
| 27741 | break; |
| 27742 | |
| 27743 | default: |
| 27744 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27745 | "Unable to process relocation for thumb opcode: %lx", |
| 27746 | (unsigned long) newval); |
| 27747 | break; |
| 27748 | } |
| 27749 | md_number_to_chars (buf, newval, THUMB_SIZE); |
| 27750 | break; |
| 27751 | |
| 27752 | case BFD_RELOC_ARM_THUMB_ADD: |
| 27753 | /* This is a complicated relocation, since we use it for all of |
| 27754 | the following immediate relocations: |
| 27755 | |
| 27756 | 3bit ADD/SUB |
| 27757 | 8bit ADD/SUB |
| 27758 | 9bit ADD/SUB SP word-aligned |
| 27759 | 10bit ADD PC/SP word-aligned |
| 27760 | |
| 27761 | The type of instruction being processed is encoded in the |
| 27762 | instruction field: |
| 27763 | |
| 27764 | 0x8000 SUB |
| 27765 | 0x00F0 Rd |
| 27766 | 0x000F Rs |
| 27767 | */ |
| 27768 | newval = md_chars_to_number (buf, THUMB_SIZE); |
| 27769 | { |
| 27770 | int rd = (newval >> 4) & 0xf; |
| 27771 | int rs = newval & 0xf; |
| 27772 | int subtract = !!(newval & 0x8000); |
| 27773 | |
| 27774 | /* Check for HI regs, only very restricted cases allowed: |
| 27775 | Adjusting SP, and using PC or SP to get an address. */ |
| 27776 | if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) |
| 27777 | || (rs > 7 && rs != REG_SP && rs != REG_PC)) |
| 27778 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27779 | _("invalid Hi register with immediate")); |
| 27780 | |
| 27781 | /* If value is negative, choose the opposite instruction. */ |
| 27782 | if (value < 0) |
| 27783 | { |
| 27784 | value = -value; |
| 27785 | subtract = !subtract; |
| 27786 | if (value < 0) |
| 27787 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27788 | _("immediate value out of range")); |
| 27789 | } |
| 27790 | |
| 27791 | if (rd == REG_SP) |
| 27792 | { |
| 27793 | if (value & ~0x1fc) |
| 27794 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27795 | _("invalid immediate for stack address calculation")); |
| 27796 | newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; |
| 27797 | newval |= value >> 2; |
| 27798 | } |
| 27799 | else if (rs == REG_PC || rs == REG_SP) |
| 27800 | { |
| 27801 | /* PR gas/18541. If the addition is for a defined symbol |
| 27802 | within range of an ADR instruction then accept it. */ |
| 27803 | if (subtract |
| 27804 | && value == 4 |
| 27805 | && fixP->fx_addsy != NULL) |
| 27806 | { |
| 27807 | subtract = 0; |
| 27808 | |
| 27809 | if (! S_IS_DEFINED (fixP->fx_addsy) |
| 27810 | || S_GET_SEGMENT (fixP->fx_addsy) != seg |
| 27811 | || S_IS_WEAK (fixP->fx_addsy)) |
| 27812 | { |
| 27813 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27814 | _("address calculation needs a strongly defined nearby symbol")); |
| 27815 | } |
| 27816 | else |
| 27817 | { |
| 27818 | offsetT v = fixP->fx_where + fixP->fx_frag->fr_address; |
| 27819 | |
| 27820 | /* Round up to the next 4-byte boundary. */ |
| 27821 | if (v & 3) |
| 27822 | v = (v + 3) & ~ 3; |
| 27823 | else |
| 27824 | v += 4; |
| 27825 | v = S_GET_VALUE (fixP->fx_addsy) - v; |
| 27826 | |
| 27827 | if (v & ~0x3fc) |
| 27828 | { |
| 27829 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27830 | _("symbol too far away")); |
| 27831 | } |
| 27832 | else |
| 27833 | { |
| 27834 | fixP->fx_done = 1; |
| 27835 | value = v; |
| 27836 | } |
| 27837 | } |
| 27838 | } |
| 27839 | |
| 27840 | if (subtract || value & ~0x3fc) |
| 27841 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27842 | _("invalid immediate for address calculation (value = 0x%08lX)"), |
| 27843 | (unsigned long) (subtract ? - value : value)); |
| 27844 | newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); |
| 27845 | newval |= rd << 8; |
| 27846 | newval |= value >> 2; |
| 27847 | } |
| 27848 | else if (rs == rd) |
| 27849 | { |
| 27850 | if (value & ~0xff) |
| 27851 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27852 | _("immediate value out of range")); |
| 27853 | newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; |
| 27854 | newval |= (rd << 8) | value; |
| 27855 | } |
| 27856 | else |
| 27857 | { |
| 27858 | if (value & ~0x7) |
| 27859 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27860 | _("immediate value out of range")); |
| 27861 | newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; |
| 27862 | newval |= rd | (rs << 3) | (value << 6); |
| 27863 | } |
| 27864 | } |
| 27865 | md_number_to_chars (buf, newval, THUMB_SIZE); |
| 27866 | break; |
| 27867 | |
| 27868 | case BFD_RELOC_ARM_THUMB_IMM: |
| 27869 | newval = md_chars_to_number (buf, THUMB_SIZE); |
| 27870 | if (value < 0 || value > 255) |
| 27871 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27872 | _("invalid immediate: %ld is out of range"), |
| 27873 | (long) value); |
| 27874 | newval |= value; |
| 27875 | md_number_to_chars (buf, newval, THUMB_SIZE); |
| 27876 | break; |
| 27877 | |
| 27878 | case BFD_RELOC_ARM_THUMB_SHIFT: |
| 27879 | /* 5bit shift value (0..32). LSL cannot take 32. */ |
| 27880 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; |
| 27881 | temp = newval & 0xf800; |
| 27882 | if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) |
| 27883 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27884 | _("invalid shift value: %ld"), (long) value); |
| 27885 | /* Shifts of zero must be encoded as LSL. */ |
| 27886 | if (value == 0) |
| 27887 | newval = (newval & 0x003f) | T_OPCODE_LSL_I; |
| 27888 | /* Shifts of 32 are encoded as zero. */ |
| 27889 | else if (value == 32) |
| 27890 | value = 0; |
| 27891 | newval |= value << 6; |
| 27892 | md_number_to_chars (buf, newval, THUMB_SIZE); |
| 27893 | break; |
| 27894 | |
| 27895 | case BFD_RELOC_VTABLE_INHERIT: |
| 27896 | case BFD_RELOC_VTABLE_ENTRY: |
| 27897 | fixP->fx_done = 0; |
| 27898 | return; |
| 27899 | |
| 27900 | case BFD_RELOC_ARM_MOVW: |
| 27901 | case BFD_RELOC_ARM_MOVT: |
| 27902 | case BFD_RELOC_ARM_THUMB_MOVW: |
| 27903 | case BFD_RELOC_ARM_THUMB_MOVT: |
| 27904 | if (fixP->fx_done || !seg->use_rela_p) |
| 27905 | { |
| 27906 | /* REL format relocations are limited to a 16-bit addend. */ |
| 27907 | if (!fixP->fx_done) |
| 27908 | { |
| 27909 | if (value < -0x8000 || value > 0x7fff) |
| 27910 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27911 | _("offset out of range")); |
| 27912 | } |
| 27913 | else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT |
| 27914 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) |
| 27915 | { |
| 27916 | value >>= 16; |
| 27917 | } |
| 27918 | |
| 27919 | if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW |
| 27920 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) |
| 27921 | { |
| 27922 | newval = get_thumb32_insn (buf); |
| 27923 | newval &= 0xfbf08f00; |
| 27924 | newval |= (value & 0xf000) << 4; |
| 27925 | newval |= (value & 0x0800) << 15; |
| 27926 | newval |= (value & 0x0700) << 4; |
| 27927 | newval |= (value & 0x00ff); |
| 27928 | put_thumb32_insn (buf, newval); |
| 27929 | } |
| 27930 | else |
| 27931 | { |
| 27932 | newval = md_chars_to_number (buf, 4); |
| 27933 | newval &= 0xfff0f000; |
| 27934 | newval |= value & 0x0fff; |
| 27935 | newval |= (value & 0xf000) << 4; |
| 27936 | md_number_to_chars (buf, newval, 4); |
| 27937 | } |
| 27938 | } |
| 27939 | return; |
| 27940 | |
| 27941 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC: |
| 27942 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC: |
| 27943 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC: |
| 27944 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC: |
| 27945 | gas_assert (!fixP->fx_done); |
| 27946 | { |
| 27947 | bfd_vma insn; |
| 27948 | bfd_boolean is_mov; |
| 27949 | bfd_vma encoded_addend = value; |
| 27950 | |
| 27951 | /* Check that addend can be encoded in instruction. */ |
| 27952 | if (!seg->use_rela_p && (value < 0 || value > 255)) |
| 27953 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27954 | _("the offset 0x%08lX is not representable"), |
| 27955 | (unsigned long) encoded_addend); |
| 27956 | |
| 27957 | /* Extract the instruction. */ |
| 27958 | insn = md_chars_to_number (buf, THUMB_SIZE); |
| 27959 | is_mov = (insn & 0xf800) == 0x2000; |
| 27960 | |
| 27961 | /* Encode insn. */ |
| 27962 | if (is_mov) |
| 27963 | { |
| 27964 | if (!seg->use_rela_p) |
| 27965 | insn |= encoded_addend; |
| 27966 | } |
| 27967 | else |
| 27968 | { |
| 27969 | int rd, rs; |
| 27970 | |
| 27971 | /* Extract the instruction. */ |
| 27972 | /* Encoding is the following |
| 27973 | 0x8000 SUB |
| 27974 | 0x00F0 Rd |
| 27975 | 0x000F Rs |
| 27976 | */ |
| 27977 | /* The following conditions must be true : |
| 27978 | - ADD |
| 27979 | - Rd == Rs |
| 27980 | - Rd <= 7 |
| 27981 | */ |
| 27982 | rd = (insn >> 4) & 0xf; |
| 27983 | rs = insn & 0xf; |
| 27984 | if ((insn & 0x8000) || (rd != rs) || rd > 7) |
| 27985 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 27986 | _("Unable to process relocation for thumb opcode: %lx"), |
| 27987 | (unsigned long) insn); |
| 27988 | |
| 27989 | /* Encode as ADD immediate8 thumb 1 code. */ |
| 27990 | insn = 0x3000 | (rd << 8); |
| 27991 | |
| 27992 | /* Place the encoded addend into the first 8 bits of the |
| 27993 | instruction. */ |
| 27994 | if (!seg->use_rela_p) |
| 27995 | insn |= encoded_addend; |
| 27996 | } |
| 27997 | |
| 27998 | /* Update the instruction. */ |
| 27999 | md_number_to_chars (buf, insn, THUMB_SIZE); |
| 28000 | } |
| 28001 | break; |
| 28002 | |
| 28003 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
| 28004 | case BFD_RELOC_ARM_ALU_PC_G0: |
| 28005 | case BFD_RELOC_ARM_ALU_PC_G1_NC: |
| 28006 | case BFD_RELOC_ARM_ALU_PC_G1: |
| 28007 | case BFD_RELOC_ARM_ALU_PC_G2: |
| 28008 | case BFD_RELOC_ARM_ALU_SB_G0_NC: |
| 28009 | case BFD_RELOC_ARM_ALU_SB_G0: |
| 28010 | case BFD_RELOC_ARM_ALU_SB_G1_NC: |
| 28011 | case BFD_RELOC_ARM_ALU_SB_G1: |
| 28012 | case BFD_RELOC_ARM_ALU_SB_G2: |
| 28013 | gas_assert (!fixP->fx_done); |
| 28014 | if (!seg->use_rela_p) |
| 28015 | { |
| 28016 | bfd_vma insn; |
| 28017 | bfd_vma encoded_addend; |
| 28018 | bfd_vma addend_abs = llabs (value); |
| 28019 | |
| 28020 | /* Check that the absolute value of the addend can be |
| 28021 | expressed as an 8-bit constant plus a rotation. */ |
| 28022 | encoded_addend = encode_arm_immediate (addend_abs); |
| 28023 | if (encoded_addend == (unsigned int) FAIL) |
| 28024 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 28025 | _("the offset 0x%08lX is not representable"), |
| 28026 | (unsigned long) addend_abs); |
| 28027 | |
| 28028 | /* Extract the instruction. */ |
| 28029 | insn = md_chars_to_number (buf, INSN_SIZE); |
| 28030 | |
| 28031 | /* If the addend is positive, use an ADD instruction. |
| 28032 | Otherwise use a SUB. Take care not to destroy the S bit. */ |
| 28033 | insn &= 0xff1fffff; |
| 28034 | if (value < 0) |
| 28035 | insn |= 1 << 22; |
| 28036 | else |
| 28037 | insn |= 1 << 23; |
| 28038 | |
| 28039 | /* Place the encoded addend into the first 12 bits of the |
| 28040 | instruction. */ |
| 28041 | insn &= 0xfffff000; |
| 28042 | insn |= encoded_addend; |
| 28043 | |
| 28044 | /* Update the instruction. */ |
| 28045 | md_number_to_chars (buf, insn, INSN_SIZE); |
| 28046 | } |
| 28047 | break; |
| 28048 | |
| 28049 | case BFD_RELOC_ARM_LDR_PC_G0: |
| 28050 | case BFD_RELOC_ARM_LDR_PC_G1: |
| 28051 | case BFD_RELOC_ARM_LDR_PC_G2: |
| 28052 | case BFD_RELOC_ARM_LDR_SB_G0: |
| 28053 | case BFD_RELOC_ARM_LDR_SB_G1: |
| 28054 | case BFD_RELOC_ARM_LDR_SB_G2: |
| 28055 | gas_assert (!fixP->fx_done); |
| 28056 | if (!seg->use_rela_p) |
| 28057 | { |
| 28058 | bfd_vma insn; |
| 28059 | bfd_vma addend_abs = llabs (value); |
| 28060 | |
| 28061 | /* Check that the absolute value of the addend can be |
| 28062 | encoded in 12 bits. */ |
| 28063 | if (addend_abs >= 0x1000) |
| 28064 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 28065 | _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), |
| 28066 | (unsigned long) addend_abs); |
| 28067 | |
| 28068 | /* Extract the instruction. */ |
| 28069 | insn = md_chars_to_number (buf, INSN_SIZE); |
| 28070 | |
| 28071 | /* If the addend is negative, clear bit 23 of the instruction. |
| 28072 | Otherwise set it. */ |
| 28073 | if (value < 0) |
| 28074 | insn &= ~(1 << 23); |
| 28075 | else |
| 28076 | insn |= 1 << 23; |
| 28077 | |
| 28078 | /* Place the absolute value of the addend into the first 12 bits |
| 28079 | of the instruction. */ |
| 28080 | insn &= 0xfffff000; |
| 28081 | insn |= addend_abs; |
| 28082 | |
| 28083 | /* Update the instruction. */ |
| 28084 | md_number_to_chars (buf, insn, INSN_SIZE); |
| 28085 | } |
| 28086 | break; |
| 28087 | |
| 28088 | case BFD_RELOC_ARM_LDRS_PC_G0: |
| 28089 | case BFD_RELOC_ARM_LDRS_PC_G1: |
| 28090 | case BFD_RELOC_ARM_LDRS_PC_G2: |
| 28091 | case BFD_RELOC_ARM_LDRS_SB_G0: |
| 28092 | case BFD_RELOC_ARM_LDRS_SB_G1: |
| 28093 | case BFD_RELOC_ARM_LDRS_SB_G2: |
| 28094 | gas_assert (!fixP->fx_done); |
| 28095 | if (!seg->use_rela_p) |
| 28096 | { |
| 28097 | bfd_vma insn; |
| 28098 | bfd_vma addend_abs = llabs (value); |
| 28099 | |
| 28100 | /* Check that the absolute value of the addend can be |
| 28101 | encoded in 8 bits. */ |
| 28102 | if (addend_abs >= 0x100) |
| 28103 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 28104 | _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), |
| 28105 | (unsigned long) addend_abs); |
| 28106 | |
| 28107 | /* Extract the instruction. */ |
| 28108 | insn = md_chars_to_number (buf, INSN_SIZE); |
| 28109 | |
| 28110 | /* If the addend is negative, clear bit 23 of the instruction. |
| 28111 | Otherwise set it. */ |
| 28112 | if (value < 0) |
| 28113 | insn &= ~(1 << 23); |
| 28114 | else |
| 28115 | insn |= 1 << 23; |
| 28116 | |
| 28117 | /* Place the first four bits of the absolute value of the addend |
| 28118 | into the first 4 bits of the instruction, and the remaining |
| 28119 | four into bits 8 .. 11. */ |
| 28120 | insn &= 0xfffff0f0; |
| 28121 | insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); |
| 28122 | |
| 28123 | /* Update the instruction. */ |
| 28124 | md_number_to_chars (buf, insn, INSN_SIZE); |
| 28125 | } |
| 28126 | break; |
| 28127 | |
| 28128 | case BFD_RELOC_ARM_LDC_PC_G0: |
| 28129 | case BFD_RELOC_ARM_LDC_PC_G1: |
| 28130 | case BFD_RELOC_ARM_LDC_PC_G2: |
| 28131 | case BFD_RELOC_ARM_LDC_SB_G0: |
| 28132 | case BFD_RELOC_ARM_LDC_SB_G1: |
| 28133 | case BFD_RELOC_ARM_LDC_SB_G2: |
| 28134 | gas_assert (!fixP->fx_done); |
| 28135 | if (!seg->use_rela_p) |
| 28136 | { |
| 28137 | bfd_vma insn; |
| 28138 | bfd_vma addend_abs = llabs (value); |
| 28139 | |
| 28140 | /* Check that the absolute value of the addend is a multiple of |
| 28141 | four and, when divided by four, fits in 8 bits. */ |
| 28142 | if (addend_abs & 0x3) |
| 28143 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 28144 | _("bad offset 0x%08lX (must be word-aligned)"), |
| 28145 | (unsigned long) addend_abs); |
| 28146 | |
| 28147 | if ((addend_abs >> 2) > 0xff) |
| 28148 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 28149 | _("bad offset 0x%08lX (must be an 8-bit number of words)"), |
| 28150 | (unsigned long) addend_abs); |
| 28151 | |
| 28152 | /* Extract the instruction. */ |
| 28153 | insn = md_chars_to_number (buf, INSN_SIZE); |
| 28154 | |
| 28155 | /* If the addend is negative, clear bit 23 of the instruction. |
| 28156 | Otherwise set it. */ |
| 28157 | if (value < 0) |
| 28158 | insn &= ~(1 << 23); |
| 28159 | else |
| 28160 | insn |= 1 << 23; |
| 28161 | |
| 28162 | /* Place the addend (divided by four) into the first eight |
| 28163 | bits of the instruction. */ |
| 28164 | insn &= 0xfffffff0; |
| 28165 | insn |= addend_abs >> 2; |
| 28166 | |
| 28167 | /* Update the instruction. */ |
| 28168 | md_number_to_chars (buf, insn, INSN_SIZE); |
| 28169 | } |
| 28170 | break; |
| 28171 | |
| 28172 | case BFD_RELOC_THUMB_PCREL_BRANCH5: |
| 28173 | if (fixP->fx_addsy |
| 28174 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
| 28175 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
| 28176 | && ARM_IS_FUNC (fixP->fx_addsy) |
| 28177 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main)) |
| 28178 | { |
| 28179 | /* Force a relocation for a branch 5 bits wide. */ |
| 28180 | fixP->fx_done = 0; |
| 28181 | } |
| 28182 | if (v8_1_branch_value_check (value, 5, FALSE) == FAIL) |
| 28183 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 28184 | BAD_BRANCH_OFF); |
| 28185 | |
| 28186 | if (fixP->fx_done || !seg->use_rela_p) |
| 28187 | { |
| 28188 | addressT boff = value >> 1; |
| 28189 | |
| 28190 | newval = md_chars_to_number (buf, THUMB_SIZE); |
| 28191 | newval |= (boff << 7); |
| 28192 | md_number_to_chars (buf, newval, THUMB_SIZE); |
| 28193 | } |
| 28194 | break; |
| 28195 | |
| 28196 | case BFD_RELOC_THUMB_PCREL_BFCSEL: |
| 28197 | if (fixP->fx_addsy |
| 28198 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
| 28199 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
| 28200 | && ARM_IS_FUNC (fixP->fx_addsy) |
| 28201 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main)) |
| 28202 | { |
| 28203 | fixP->fx_done = 0; |
| 28204 | } |
| 28205 | if ((value & ~0x7f) && ((value & ~0x3f) != ~0x3f)) |
| 28206 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 28207 | _("branch out of range")); |
| 28208 | |
| 28209 | if (fixP->fx_done || !seg->use_rela_p) |
| 28210 | { |
| 28211 | newval = md_chars_to_number (buf, THUMB_SIZE); |
| 28212 | |
| 28213 | addressT boff = ((newval & 0x0780) >> 7) << 1; |
| 28214 | addressT diff = value - boff; |
| 28215 | |
| 28216 | if (diff == 4) |
| 28217 | { |
| 28218 | newval |= 1 << 1; /* T bit. */ |
| 28219 | } |
| 28220 | else if (diff != 2) |
| 28221 | { |
| 28222 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 28223 | _("out of range label-relative fixup value")); |
| 28224 | } |
| 28225 | md_number_to_chars (buf, newval, THUMB_SIZE); |
| 28226 | } |
| 28227 | break; |
| 28228 | |
| 28229 | case BFD_RELOC_ARM_THUMB_BF17: |
| 28230 | if (fixP->fx_addsy |
| 28231 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
| 28232 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
| 28233 | && ARM_IS_FUNC (fixP->fx_addsy) |
| 28234 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main)) |
| 28235 | { |
| 28236 | /* Force a relocation for a branch 17 bits wide. */ |
| 28237 | fixP->fx_done = 0; |
| 28238 | } |
| 28239 | |
| 28240 | if (v8_1_branch_value_check (value, 17, TRUE) == FAIL) |
| 28241 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 28242 | BAD_BRANCH_OFF); |
| 28243 | |
| 28244 | if (fixP->fx_done || !seg->use_rela_p) |
| 28245 | { |
| 28246 | offsetT newval2; |
| 28247 | addressT immA, immB, immC; |
| 28248 | |
| 28249 | immA = (value & 0x0001f000) >> 12; |
| 28250 | immB = (value & 0x00000ffc) >> 2; |
| 28251 | immC = (value & 0x00000002) >> 1; |
| 28252 | |
| 28253 | newval = md_chars_to_number (buf, THUMB_SIZE); |
| 28254 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); |
| 28255 | newval |= immA; |
| 28256 | newval2 |= (immC << 11) | (immB << 1); |
| 28257 | md_number_to_chars (buf, newval, THUMB_SIZE); |
| 28258 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); |
| 28259 | } |
| 28260 | break; |
| 28261 | |
| 28262 | case BFD_RELOC_ARM_THUMB_BF19: |
| 28263 | if (fixP->fx_addsy |
| 28264 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
| 28265 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
| 28266 | && ARM_IS_FUNC (fixP->fx_addsy) |
| 28267 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main)) |
| 28268 | { |
| 28269 | /* Force a relocation for a branch 19 bits wide. */ |
| 28270 | fixP->fx_done = 0; |
| 28271 | } |
| 28272 | |
| 28273 | if (v8_1_branch_value_check (value, 19, TRUE) == FAIL) |
| 28274 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 28275 | BAD_BRANCH_OFF); |
| 28276 | |
| 28277 | if (fixP->fx_done || !seg->use_rela_p) |
| 28278 | { |
| 28279 | offsetT newval2; |
| 28280 | addressT immA, immB, immC; |
| 28281 | |
| 28282 | immA = (value & 0x0007f000) >> 12; |
| 28283 | immB = (value & 0x00000ffc) >> 2; |
| 28284 | immC = (value & 0x00000002) >> 1; |
| 28285 | |
| 28286 | newval = md_chars_to_number (buf, THUMB_SIZE); |
| 28287 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); |
| 28288 | newval |= immA; |
| 28289 | newval2 |= (immC << 11) | (immB << 1); |
| 28290 | md_number_to_chars (buf, newval, THUMB_SIZE); |
| 28291 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); |
| 28292 | } |
| 28293 | break; |
| 28294 | |
| 28295 | case BFD_RELOC_ARM_THUMB_BF13: |
| 28296 | if (fixP->fx_addsy |
| 28297 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
| 28298 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
| 28299 | && ARM_IS_FUNC (fixP->fx_addsy) |
| 28300 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main)) |
| 28301 | { |
| 28302 | /* Force a relocation for a branch 13 bits wide. */ |
| 28303 | fixP->fx_done = 0; |
| 28304 | } |
| 28305 | |
| 28306 | if (v8_1_branch_value_check (value, 13, TRUE) == FAIL) |
| 28307 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 28308 | BAD_BRANCH_OFF); |
| 28309 | |
| 28310 | if (fixP->fx_done || !seg->use_rela_p) |
| 28311 | { |
| 28312 | offsetT newval2; |
| 28313 | addressT immA, immB, immC; |
| 28314 | |
| 28315 | immA = (value & 0x00001000) >> 12; |
| 28316 | immB = (value & 0x00000ffc) >> 2; |
| 28317 | immC = (value & 0x00000002) >> 1; |
| 28318 | |
| 28319 | newval = md_chars_to_number (buf, THUMB_SIZE); |
| 28320 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); |
| 28321 | newval |= immA; |
| 28322 | newval2 |= (immC << 11) | (immB << 1); |
| 28323 | md_number_to_chars (buf, newval, THUMB_SIZE); |
| 28324 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); |
| 28325 | } |
| 28326 | break; |
| 28327 | |
| 28328 | case BFD_RELOC_ARM_THUMB_LOOP12: |
| 28329 | if (fixP->fx_addsy |
| 28330 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
| 28331 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
| 28332 | && ARM_IS_FUNC (fixP->fx_addsy) |
| 28333 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main)) |
| 28334 | { |
| 28335 | /* Force a relocation for a branch 12 bits wide. */ |
| 28336 | fixP->fx_done = 0; |
| 28337 | } |
| 28338 | |
| 28339 | bfd_vma insn = get_thumb32_insn (buf); |
| 28340 | /* le lr, <label> or le <label> */ |
| 28341 | if (((insn & 0xffffffff) == 0xf00fc001) |
| 28342 | || ((insn & 0xffffffff) == 0xf02fc001)) |
| 28343 | value = -value; |
| 28344 | |
| 28345 | if (v8_1_branch_value_check (value, 12, FALSE) == FAIL) |
| 28346 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 28347 | BAD_BRANCH_OFF); |
| 28348 | if (fixP->fx_done || !seg->use_rela_p) |
| 28349 | { |
| 28350 | addressT imml, immh; |
| 28351 | |
| 28352 | immh = (value & 0x00000ffc) >> 2; |
| 28353 | imml = (value & 0x00000002) >> 1; |
| 28354 | |
| 28355 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); |
| 28356 | newval |= (imml << 11) | (immh << 1); |
| 28357 | md_number_to_chars (buf + THUMB_SIZE, newval, THUMB_SIZE); |
| 28358 | } |
| 28359 | break; |
| 28360 | |
| 28361 | case BFD_RELOC_ARM_V4BX: |
| 28362 | /* This will need to go in the object file. */ |
| 28363 | fixP->fx_done = 0; |
| 28364 | break; |
| 28365 | |
| 28366 | case BFD_RELOC_UNUSED: |
| 28367 | default: |
| 28368 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 28369 | _("bad relocation fixup type (%d)"), fixP->fx_r_type); |
| 28370 | } |
| 28371 | } |
| 28372 | |
| 28373 | /* Translate internal representation of relocation info to BFD target |
| 28374 | format. */ |
| 28375 | |
| 28376 | arelent * |
| 28377 | tc_gen_reloc (asection *section, fixS *fixp) |
| 28378 | { |
| 28379 | arelent * reloc; |
| 28380 | bfd_reloc_code_real_type code; |
| 28381 | |
| 28382 | reloc = XNEW (arelent); |
| 28383 | |
| 28384 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
| 28385 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
| 28386 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
| 28387 | |
| 28388 | if (fixp->fx_pcrel) |
| 28389 | { |
| 28390 | if (section->use_rela_p) |
| 28391 | fixp->fx_offset -= md_pcrel_from_section (fixp, section); |
| 28392 | else |
| 28393 | fixp->fx_offset = reloc->address; |
| 28394 | } |
| 28395 | reloc->addend = fixp->fx_offset; |
| 28396 | |
| 28397 | switch (fixp->fx_r_type) |
| 28398 | { |
| 28399 | case BFD_RELOC_8: |
| 28400 | if (fixp->fx_pcrel) |
| 28401 | { |
| 28402 | code = BFD_RELOC_8_PCREL; |
| 28403 | break; |
| 28404 | } |
| 28405 | /* Fall through. */ |
| 28406 | |
| 28407 | case BFD_RELOC_16: |
| 28408 | if (fixp->fx_pcrel) |
| 28409 | { |
| 28410 | code = BFD_RELOC_16_PCREL; |
| 28411 | break; |
| 28412 | } |
| 28413 | /* Fall through. */ |
| 28414 | |
| 28415 | case BFD_RELOC_32: |
| 28416 | if (fixp->fx_pcrel) |
| 28417 | { |
| 28418 | code = BFD_RELOC_32_PCREL; |
| 28419 | break; |
| 28420 | } |
| 28421 | /* Fall through. */ |
| 28422 | |
| 28423 | case BFD_RELOC_ARM_MOVW: |
| 28424 | if (fixp->fx_pcrel) |
| 28425 | { |
| 28426 | code = BFD_RELOC_ARM_MOVW_PCREL; |
| 28427 | break; |
| 28428 | } |
| 28429 | /* Fall through. */ |
| 28430 | |
| 28431 | case BFD_RELOC_ARM_MOVT: |
| 28432 | if (fixp->fx_pcrel) |
| 28433 | { |
| 28434 | code = BFD_RELOC_ARM_MOVT_PCREL; |
| 28435 | break; |
| 28436 | } |
| 28437 | /* Fall through. */ |
| 28438 | |
| 28439 | case BFD_RELOC_ARM_THUMB_MOVW: |
| 28440 | if (fixp->fx_pcrel) |
| 28441 | { |
| 28442 | code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; |
| 28443 | break; |
| 28444 | } |
| 28445 | /* Fall through. */ |
| 28446 | |
| 28447 | case BFD_RELOC_ARM_THUMB_MOVT: |
| 28448 | if (fixp->fx_pcrel) |
| 28449 | { |
| 28450 | code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; |
| 28451 | break; |
| 28452 | } |
| 28453 | /* Fall through. */ |
| 28454 | |
| 28455 | case BFD_RELOC_NONE: |
| 28456 | case BFD_RELOC_ARM_PCREL_BRANCH: |
| 28457 | case BFD_RELOC_ARM_PCREL_BLX: |
| 28458 | case BFD_RELOC_RVA: |
| 28459 | case BFD_RELOC_THUMB_PCREL_BRANCH7: |
| 28460 | case BFD_RELOC_THUMB_PCREL_BRANCH9: |
| 28461 | case BFD_RELOC_THUMB_PCREL_BRANCH12: |
| 28462 | case BFD_RELOC_THUMB_PCREL_BRANCH20: |
| 28463 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
| 28464 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
| 28465 | case BFD_RELOC_VTABLE_ENTRY: |
| 28466 | case BFD_RELOC_VTABLE_INHERIT: |
| 28467 | #ifdef TE_PE |
| 28468 | case BFD_RELOC_32_SECREL: |
| 28469 | #endif |
| 28470 | code = fixp->fx_r_type; |
| 28471 | break; |
| 28472 | |
| 28473 | case BFD_RELOC_THUMB_PCREL_BLX: |
| 28474 | #ifdef OBJ_ELF |
| 28475 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) |
| 28476 | code = BFD_RELOC_THUMB_PCREL_BRANCH23; |
| 28477 | else |
| 28478 | #endif |
| 28479 | code = BFD_RELOC_THUMB_PCREL_BLX; |
| 28480 | break; |
| 28481 | |
| 28482 | case BFD_RELOC_ARM_LITERAL: |
| 28483 | case BFD_RELOC_ARM_HWLITERAL: |
| 28484 | /* If this is called then the a literal has |
| 28485 | been referenced across a section boundary. */ |
| 28486 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 28487 | _("literal referenced across section boundary")); |
| 28488 | return NULL; |
| 28489 | |
| 28490 | #ifdef OBJ_ELF |
| 28491 | case BFD_RELOC_ARM_TLS_CALL: |
| 28492 | case BFD_RELOC_ARM_THM_TLS_CALL: |
| 28493 | case BFD_RELOC_ARM_TLS_DESCSEQ: |
| 28494 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: |
| 28495 | case BFD_RELOC_ARM_GOT32: |
| 28496 | case BFD_RELOC_ARM_GOTOFF: |
| 28497 | case BFD_RELOC_ARM_GOT_PREL: |
| 28498 | case BFD_RELOC_ARM_PLT32: |
| 28499 | case BFD_RELOC_ARM_TARGET1: |
| 28500 | case BFD_RELOC_ARM_ROSEGREL32: |
| 28501 | case BFD_RELOC_ARM_SBREL32: |
| 28502 | case BFD_RELOC_ARM_PREL31: |
| 28503 | case BFD_RELOC_ARM_TARGET2: |
| 28504 | case BFD_RELOC_ARM_TLS_LDO32: |
| 28505 | case BFD_RELOC_ARM_PCREL_CALL: |
| 28506 | case BFD_RELOC_ARM_PCREL_JUMP: |
| 28507 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
| 28508 | case BFD_RELOC_ARM_ALU_PC_G0: |
| 28509 | case BFD_RELOC_ARM_ALU_PC_G1_NC: |
| 28510 | case BFD_RELOC_ARM_ALU_PC_G1: |
| 28511 | case BFD_RELOC_ARM_ALU_PC_G2: |
| 28512 | case BFD_RELOC_ARM_LDR_PC_G0: |
| 28513 | case BFD_RELOC_ARM_LDR_PC_G1: |
| 28514 | case BFD_RELOC_ARM_LDR_PC_G2: |
| 28515 | case BFD_RELOC_ARM_LDRS_PC_G0: |
| 28516 | case BFD_RELOC_ARM_LDRS_PC_G1: |
| 28517 | case BFD_RELOC_ARM_LDRS_PC_G2: |
| 28518 | case BFD_RELOC_ARM_LDC_PC_G0: |
| 28519 | case BFD_RELOC_ARM_LDC_PC_G1: |
| 28520 | case BFD_RELOC_ARM_LDC_PC_G2: |
| 28521 | case BFD_RELOC_ARM_ALU_SB_G0_NC: |
| 28522 | case BFD_RELOC_ARM_ALU_SB_G0: |
| 28523 | case BFD_RELOC_ARM_ALU_SB_G1_NC: |
| 28524 | case BFD_RELOC_ARM_ALU_SB_G1: |
| 28525 | case BFD_RELOC_ARM_ALU_SB_G2: |
| 28526 | case BFD_RELOC_ARM_LDR_SB_G0: |
| 28527 | case BFD_RELOC_ARM_LDR_SB_G1: |
| 28528 | case BFD_RELOC_ARM_LDR_SB_G2: |
| 28529 | case BFD_RELOC_ARM_LDRS_SB_G0: |
| 28530 | case BFD_RELOC_ARM_LDRS_SB_G1: |
| 28531 | case BFD_RELOC_ARM_LDRS_SB_G2: |
| 28532 | case BFD_RELOC_ARM_LDC_SB_G0: |
| 28533 | case BFD_RELOC_ARM_LDC_SB_G1: |
| 28534 | case BFD_RELOC_ARM_LDC_SB_G2: |
| 28535 | case BFD_RELOC_ARM_V4BX: |
| 28536 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC: |
| 28537 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC: |
| 28538 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC: |
| 28539 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC: |
| 28540 | case BFD_RELOC_ARM_GOTFUNCDESC: |
| 28541 | case BFD_RELOC_ARM_GOTOFFFUNCDESC: |
| 28542 | case BFD_RELOC_ARM_FUNCDESC: |
| 28543 | case BFD_RELOC_ARM_THUMB_BF17: |
| 28544 | case BFD_RELOC_ARM_THUMB_BF19: |
| 28545 | case BFD_RELOC_ARM_THUMB_BF13: |
| 28546 | code = fixp->fx_r_type; |
| 28547 | break; |
| 28548 | |
| 28549 | case BFD_RELOC_ARM_TLS_GOTDESC: |
| 28550 | case BFD_RELOC_ARM_TLS_GD32: |
| 28551 | case BFD_RELOC_ARM_TLS_GD32_FDPIC: |
| 28552 | case BFD_RELOC_ARM_TLS_LE32: |
| 28553 | case BFD_RELOC_ARM_TLS_IE32: |
| 28554 | case BFD_RELOC_ARM_TLS_IE32_FDPIC: |
| 28555 | case BFD_RELOC_ARM_TLS_LDM32: |
| 28556 | case BFD_RELOC_ARM_TLS_LDM32_FDPIC: |
| 28557 | /* BFD will include the symbol's address in the addend. |
| 28558 | But we don't want that, so subtract it out again here. */ |
| 28559 | if (!S_IS_COMMON (fixp->fx_addsy)) |
| 28560 | reloc->addend -= (*reloc->sym_ptr_ptr)->value; |
| 28561 | code = fixp->fx_r_type; |
| 28562 | break; |
| 28563 | #endif |
| 28564 | |
| 28565 | case BFD_RELOC_ARM_IMMEDIATE: |
| 28566 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 28567 | _("internal relocation (type: IMMEDIATE) not fixed up")); |
| 28568 | return NULL; |
| 28569 | |
| 28570 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
| 28571 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 28572 | _("ADRL used for a symbol not defined in the same file")); |
| 28573 | return NULL; |
| 28574 | |
| 28575 | case BFD_RELOC_THUMB_PCREL_BRANCH5: |
| 28576 | case BFD_RELOC_THUMB_PCREL_BFCSEL: |
| 28577 | case BFD_RELOC_ARM_THUMB_LOOP12: |
| 28578 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 28579 | _("%s used for a symbol not defined in the same file"), |
| 28580 | bfd_get_reloc_code_name (fixp->fx_r_type)); |
| 28581 | return NULL; |
| 28582 | |
| 28583 | case BFD_RELOC_ARM_OFFSET_IMM: |
| 28584 | if (section->use_rela_p) |
| 28585 | { |
| 28586 | code = fixp->fx_r_type; |
| 28587 | break; |
| 28588 | } |
| 28589 | |
| 28590 | if (fixp->fx_addsy != NULL |
| 28591 | && !S_IS_DEFINED (fixp->fx_addsy) |
| 28592 | && S_IS_LOCAL (fixp->fx_addsy)) |
| 28593 | { |
| 28594 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 28595 | _("undefined local label `%s'"), |
| 28596 | S_GET_NAME (fixp->fx_addsy)); |
| 28597 | return NULL; |
| 28598 | } |
| 28599 | |
| 28600 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 28601 | _("internal_relocation (type: OFFSET_IMM) not fixed up")); |
| 28602 | return NULL; |
| 28603 | |
| 28604 | default: |
| 28605 | { |
| 28606 | const char * type; |
| 28607 | |
| 28608 | switch (fixp->fx_r_type) |
| 28609 | { |
| 28610 | case BFD_RELOC_NONE: type = "NONE"; break; |
| 28611 | case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; |
| 28612 | case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; |
| 28613 | case BFD_RELOC_ARM_SMC: type = "SMC"; break; |
| 28614 | case BFD_RELOC_ARM_SWI: type = "SWI"; break; |
| 28615 | case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; |
| 28616 | case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; |
| 28617 | case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break; |
| 28618 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; |
| 28619 | case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; |
| 28620 | case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; |
| 28621 | case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; |
| 28622 | case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; |
| 28623 | default: type = _("<unknown>"); break; |
| 28624 | } |
| 28625 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 28626 | _("cannot represent %s relocation in this object file format"), |
| 28627 | type); |
| 28628 | return NULL; |
| 28629 | } |
| 28630 | } |
| 28631 | |
| 28632 | #ifdef OBJ_ELF |
| 28633 | if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) |
| 28634 | && GOT_symbol |
| 28635 | && fixp->fx_addsy == GOT_symbol) |
| 28636 | { |
| 28637 | code = BFD_RELOC_ARM_GOTPC; |
| 28638 | reloc->addend = fixp->fx_offset = reloc->address; |
| 28639 | } |
| 28640 | #endif |
| 28641 | |
| 28642 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
| 28643 | |
| 28644 | if (reloc->howto == NULL) |
| 28645 | { |
| 28646 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 28647 | _("cannot represent %s relocation in this object file format"), |
| 28648 | bfd_get_reloc_code_name (code)); |
| 28649 | return NULL; |
| 28650 | } |
| 28651 | |
| 28652 | /* HACK: Since arm ELF uses Rel instead of Rela, encode the |
| 28653 | vtable entry to be used in the relocation's section offset. */ |
| 28654 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
| 28655 | reloc->address = fixp->fx_offset; |
| 28656 | |
| 28657 | return reloc; |
| 28658 | } |
| 28659 | |
| 28660 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ |
| 28661 | |
| 28662 | void |
| 28663 | cons_fix_new_arm (fragS * frag, |
| 28664 | int where, |
| 28665 | int size, |
| 28666 | expressionS * exp, |
| 28667 | bfd_reloc_code_real_type reloc) |
| 28668 | { |
| 28669 | int pcrel = 0; |
| 28670 | |
| 28671 | /* Pick a reloc. |
| 28672 | FIXME: @@ Should look at CPU word size. */ |
| 28673 | switch (size) |
| 28674 | { |
| 28675 | case 1: |
| 28676 | reloc = BFD_RELOC_8; |
| 28677 | break; |
| 28678 | case 2: |
| 28679 | reloc = BFD_RELOC_16; |
| 28680 | break; |
| 28681 | case 4: |
| 28682 | default: |
| 28683 | reloc = BFD_RELOC_32; |
| 28684 | break; |
| 28685 | case 8: |
| 28686 | reloc = BFD_RELOC_64; |
| 28687 | break; |
| 28688 | } |
| 28689 | |
| 28690 | #ifdef TE_PE |
| 28691 | if (exp->X_op == O_secrel) |
| 28692 | { |
| 28693 | exp->X_op = O_symbol; |
| 28694 | reloc = BFD_RELOC_32_SECREL; |
| 28695 | } |
| 28696 | #endif |
| 28697 | |
| 28698 | fix_new_exp (frag, where, size, exp, pcrel, reloc); |
| 28699 | } |
| 28700 | |
| 28701 | #if defined (OBJ_COFF) |
| 28702 | void |
| 28703 | arm_validate_fix (fixS * fixP) |
| 28704 | { |
| 28705 | /* If the destination of the branch is a defined symbol which does not have |
| 28706 | the THUMB_FUNC attribute, then we must be calling a function which has |
| 28707 | the (interfacearm) attribute. We look for the Thumb entry point to that |
| 28708 | function and change the branch to refer to that function instead. */ |
| 28709 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 |
| 28710 | && fixP->fx_addsy != NULL |
| 28711 | && S_IS_DEFINED (fixP->fx_addsy) |
| 28712 | && ! THUMB_IS_FUNC (fixP->fx_addsy)) |
| 28713 | { |
| 28714 | fixP->fx_addsy = find_real_start (fixP->fx_addsy); |
| 28715 | } |
| 28716 | } |
| 28717 | #endif |
| 28718 | |
| 28719 | |
| 28720 | int |
| 28721 | arm_force_relocation (struct fix * fixp) |
| 28722 | { |
| 28723 | #if defined (OBJ_COFF) && defined (TE_PE) |
| 28724 | if (fixp->fx_r_type == BFD_RELOC_RVA) |
| 28725 | return 1; |
| 28726 | #endif |
| 28727 | |
| 28728 | /* In case we have a call or a branch to a function in ARM ISA mode from |
| 28729 | a thumb function or vice-versa force the relocation. These relocations |
| 28730 | are cleared off for some cores that might have blx and simple transformations |
| 28731 | are possible. */ |
| 28732 | |
| 28733 | #ifdef OBJ_ELF |
| 28734 | switch (fixp->fx_r_type) |
| 28735 | { |
| 28736 | case BFD_RELOC_ARM_PCREL_JUMP: |
| 28737 | case BFD_RELOC_ARM_PCREL_CALL: |
| 28738 | case BFD_RELOC_THUMB_PCREL_BLX: |
| 28739 | if (THUMB_IS_FUNC (fixp->fx_addsy)) |
| 28740 | return 1; |
| 28741 | break; |
| 28742 | |
| 28743 | case BFD_RELOC_ARM_PCREL_BLX: |
| 28744 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
| 28745 | case BFD_RELOC_THUMB_PCREL_BRANCH20: |
| 28746 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
| 28747 | if (ARM_IS_FUNC (fixp->fx_addsy)) |
| 28748 | return 1; |
| 28749 | break; |
| 28750 | |
| 28751 | default: |
| 28752 | break; |
| 28753 | } |
| 28754 | #endif |
| 28755 | |
| 28756 | /* Resolve these relocations even if the symbol is extern or weak. |
| 28757 | Technically this is probably wrong due to symbol preemption. |
| 28758 | In practice these relocations do not have enough range to be useful |
| 28759 | at dynamic link time, and some code (e.g. in the Linux kernel) |
| 28760 | expects these references to be resolved. */ |
| 28761 | if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE |
| 28762 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM |
| 28763 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8 |
| 28764 | || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE |
| 28765 | || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
| 28766 | || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2 |
| 28767 | || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET |
| 28768 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM |
| 28769 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE |
| 28770 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 |
| 28771 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM |
| 28772 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12 |
| 28773 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM |
| 28774 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2) |
| 28775 | return 0; |
| 28776 | |
| 28777 | /* Always leave these relocations for the linker. */ |
| 28778 | if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC |
| 28779 | && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) |
| 28780 | || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) |
| 28781 | return 1; |
| 28782 | |
| 28783 | /* Always generate relocations against function symbols. */ |
| 28784 | if (fixp->fx_r_type == BFD_RELOC_32 |
| 28785 | && fixp->fx_addsy |
| 28786 | && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)) |
| 28787 | return 1; |
| 28788 | |
| 28789 | return generic_force_reloc (fixp); |
| 28790 | } |
| 28791 | |
| 28792 | #if defined (OBJ_ELF) || defined (OBJ_COFF) |
| 28793 | /* Relocations against function names must be left unadjusted, |
| 28794 | so that the linker can use this information to generate interworking |
| 28795 | stubs. The MIPS version of this function |
| 28796 | also prevents relocations that are mips-16 specific, but I do not |
| 28797 | know why it does this. |
| 28798 | |
| 28799 | FIXME: |
| 28800 | There is one other problem that ought to be addressed here, but |
| 28801 | which currently is not: Taking the address of a label (rather |
| 28802 | than a function) and then later jumping to that address. Such |
| 28803 | addresses also ought to have their bottom bit set (assuming that |
| 28804 | they reside in Thumb code), but at the moment they will not. */ |
| 28805 | |
| 28806 | bfd_boolean |
| 28807 | arm_fix_adjustable (fixS * fixP) |
| 28808 | { |
| 28809 | if (fixP->fx_addsy == NULL) |
| 28810 | return 1; |
| 28811 | |
| 28812 | /* Preserve relocations against symbols with function type. */ |
| 28813 | if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) |
| 28814 | return FALSE; |
| 28815 | |
| 28816 | if (THUMB_IS_FUNC (fixP->fx_addsy) |
| 28817 | && fixP->fx_subsy == NULL) |
| 28818 | return FALSE; |
| 28819 | |
| 28820 | /* We need the symbol name for the VTABLE entries. */ |
| 28821 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
| 28822 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
| 28823 | return FALSE; |
| 28824 | |
| 28825 | /* Don't allow symbols to be discarded on GOT related relocs. */ |
| 28826 | if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 |
| 28827 | || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 |
| 28828 | || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF |
| 28829 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 |
| 28830 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32_FDPIC |
| 28831 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 |
| 28832 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 |
| 28833 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32_FDPIC |
| 28834 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 |
| 28835 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32_FDPIC |
| 28836 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 |
| 28837 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC |
| 28838 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL |
| 28839 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL |
| 28840 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ |
| 28841 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ |
| 28842 | || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) |
| 28843 | return FALSE; |
| 28844 | |
| 28845 | /* Similarly for group relocations. */ |
| 28846 | if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC |
| 28847 | && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) |
| 28848 | || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) |
| 28849 | return FALSE; |
| 28850 | |
| 28851 | /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */ |
| 28852 | if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW |
| 28853 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT |
| 28854 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL |
| 28855 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL |
| 28856 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW |
| 28857 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT |
| 28858 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL |
| 28859 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL) |
| 28860 | return FALSE; |
| 28861 | |
| 28862 | /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited |
| 28863 | offsets, so keep these symbols. */ |
| 28864 | if (fixP->fx_r_type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC |
| 28865 | && fixP->fx_r_type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) |
| 28866 | return FALSE; |
| 28867 | |
| 28868 | return TRUE; |
| 28869 | } |
| 28870 | #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */ |
| 28871 | |
| 28872 | #ifdef OBJ_ELF |
| 28873 | const char * |
| 28874 | elf32_arm_target_format (void) |
| 28875 | { |
| 28876 | #ifdef TE_SYMBIAN |
| 28877 | return (target_big_endian |
| 28878 | ? "elf32-bigarm-symbian" |
| 28879 | : "elf32-littlearm-symbian"); |
| 28880 | #elif defined (TE_VXWORKS) |
| 28881 | return (target_big_endian |
| 28882 | ? "elf32-bigarm-vxworks" |
| 28883 | : "elf32-littlearm-vxworks"); |
| 28884 | #elif defined (TE_NACL) |
| 28885 | return (target_big_endian |
| 28886 | ? "elf32-bigarm-nacl" |
| 28887 | : "elf32-littlearm-nacl"); |
| 28888 | #else |
| 28889 | if (arm_fdpic) |
| 28890 | { |
| 28891 | if (target_big_endian) |
| 28892 | return "elf32-bigarm-fdpic"; |
| 28893 | else |
| 28894 | return "elf32-littlearm-fdpic"; |
| 28895 | } |
| 28896 | else |
| 28897 | { |
| 28898 | if (target_big_endian) |
| 28899 | return "elf32-bigarm"; |
| 28900 | else |
| 28901 | return "elf32-littlearm"; |
| 28902 | } |
| 28903 | #endif |
| 28904 | } |
| 28905 | |
| 28906 | void |
| 28907 | armelf_frob_symbol (symbolS * symp, |
| 28908 | int * puntp) |
| 28909 | { |
| 28910 | elf_frob_symbol (symp, puntp); |
| 28911 | } |
| 28912 | #endif |
| 28913 | |
| 28914 | /* MD interface: Finalization. */ |
| 28915 | |
| 28916 | void |
| 28917 | arm_cleanup (void) |
| 28918 | { |
| 28919 | literal_pool * pool; |
| 28920 | |
| 28921 | /* Ensure that all the predication blocks are properly closed. */ |
| 28922 | check_pred_blocks_finished (); |
| 28923 | |
| 28924 | for (pool = list_of_pools; pool; pool = pool->next) |
| 28925 | { |
| 28926 | /* Put it at the end of the relevant section. */ |
| 28927 | subseg_set (pool->section, pool->sub_section); |
| 28928 | #ifdef OBJ_ELF |
| 28929 | arm_elf_change_section (); |
| 28930 | #endif |
| 28931 | s_ltorg (0); |
| 28932 | } |
| 28933 | } |
| 28934 | |
| 28935 | #ifdef OBJ_ELF |
| 28936 | /* Remove any excess mapping symbols generated for alignment frags in |
| 28937 | SEC. We may have created a mapping symbol before a zero byte |
| 28938 | alignment; remove it if there's a mapping symbol after the |
| 28939 | alignment. */ |
| 28940 | static void |
| 28941 | check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, |
| 28942 | void *dummy ATTRIBUTE_UNUSED) |
| 28943 | { |
| 28944 | segment_info_type *seginfo = seg_info (sec); |
| 28945 | fragS *fragp; |
| 28946 | |
| 28947 | if (seginfo == NULL || seginfo->frchainP == NULL) |
| 28948 | return; |
| 28949 | |
| 28950 | for (fragp = seginfo->frchainP->frch_root; |
| 28951 | fragp != NULL; |
| 28952 | fragp = fragp->fr_next) |
| 28953 | { |
| 28954 | symbolS *sym = fragp->tc_frag_data.last_map; |
| 28955 | fragS *next = fragp->fr_next; |
| 28956 | |
| 28957 | /* Variable-sized frags have been converted to fixed size by |
| 28958 | this point. But if this was variable-sized to start with, |
| 28959 | there will be a fixed-size frag after it. So don't handle |
| 28960 | next == NULL. */ |
| 28961 | if (sym == NULL || next == NULL) |
| 28962 | continue; |
| 28963 | |
| 28964 | if (S_GET_VALUE (sym) < next->fr_address) |
| 28965 | /* Not at the end of this frag. */ |
| 28966 | continue; |
| 28967 | know (S_GET_VALUE (sym) == next->fr_address); |
| 28968 | |
| 28969 | do |
| 28970 | { |
| 28971 | if (next->tc_frag_data.first_map != NULL) |
| 28972 | { |
| 28973 | /* Next frag starts with a mapping symbol. Discard this |
| 28974 | one. */ |
| 28975 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); |
| 28976 | break; |
| 28977 | } |
| 28978 | |
| 28979 | if (next->fr_next == NULL) |
| 28980 | { |
| 28981 | /* This mapping symbol is at the end of the section. Discard |
| 28982 | it. */ |
| 28983 | know (next->fr_fix == 0 && next->fr_var == 0); |
| 28984 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); |
| 28985 | break; |
| 28986 | } |
| 28987 | |
| 28988 | /* As long as we have empty frags without any mapping symbols, |
| 28989 | keep looking. */ |
| 28990 | /* If the next frag is non-empty and does not start with a |
| 28991 | mapping symbol, then this mapping symbol is required. */ |
| 28992 | if (next->fr_address != next->fr_next->fr_address) |
| 28993 | break; |
| 28994 | |
| 28995 | next = next->fr_next; |
| 28996 | } |
| 28997 | while (next != NULL); |
| 28998 | } |
| 28999 | } |
| 29000 | #endif |
| 29001 | |
| 29002 | /* Adjust the symbol table. This marks Thumb symbols as distinct from |
| 29003 | ARM ones. */ |
| 29004 | |
| 29005 | void |
| 29006 | arm_adjust_symtab (void) |
| 29007 | { |
| 29008 | #ifdef OBJ_COFF |
| 29009 | symbolS * sym; |
| 29010 | |
| 29011 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
| 29012 | { |
| 29013 | if (ARM_IS_THUMB (sym)) |
| 29014 | { |
| 29015 | if (THUMB_IS_FUNC (sym)) |
| 29016 | { |
| 29017 | /* Mark the symbol as a Thumb function. */ |
| 29018 | if ( S_GET_STORAGE_CLASS (sym) == C_STAT |
| 29019 | || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ |
| 29020 | S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); |
| 29021 | |
| 29022 | else if (S_GET_STORAGE_CLASS (sym) == C_EXT) |
| 29023 | S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); |
| 29024 | else |
| 29025 | as_bad (_("%s: unexpected function type: %d"), |
| 29026 | S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); |
| 29027 | } |
| 29028 | else switch (S_GET_STORAGE_CLASS (sym)) |
| 29029 | { |
| 29030 | case C_EXT: |
| 29031 | S_SET_STORAGE_CLASS (sym, C_THUMBEXT); |
| 29032 | break; |
| 29033 | case C_STAT: |
| 29034 | S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); |
| 29035 | break; |
| 29036 | case C_LABEL: |
| 29037 | S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); |
| 29038 | break; |
| 29039 | default: |
| 29040 | /* Do nothing. */ |
| 29041 | break; |
| 29042 | } |
| 29043 | } |
| 29044 | |
| 29045 | if (ARM_IS_INTERWORK (sym)) |
| 29046 | coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; |
| 29047 | } |
| 29048 | #endif |
| 29049 | #ifdef OBJ_ELF |
| 29050 | symbolS * sym; |
| 29051 | char bind; |
| 29052 | |
| 29053 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
| 29054 | { |
| 29055 | if (ARM_IS_THUMB (sym)) |
| 29056 | { |
| 29057 | elf_symbol_type * elf_sym; |
| 29058 | |
| 29059 | elf_sym = elf_symbol (symbol_get_bfdsym (sym)); |
| 29060 | bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); |
| 29061 | |
| 29062 | if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, |
| 29063 | BFD_ARM_SPECIAL_SYM_TYPE_ANY)) |
| 29064 | { |
| 29065 | /* If it's a .thumb_func, declare it as so, |
| 29066 | otherwise tag label as .code 16. */ |
| 29067 | if (THUMB_IS_FUNC (sym)) |
| 29068 | ARM_SET_SYM_BRANCH_TYPE (elf_sym->internal_elf_sym.st_target_internal, |
| 29069 | ST_BRANCH_TO_THUMB); |
| 29070 | else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
| 29071 | elf_sym->internal_elf_sym.st_info = |
| 29072 | ELF_ST_INFO (bind, STT_ARM_16BIT); |
| 29073 | } |
| 29074 | } |
| 29075 | } |
| 29076 | |
| 29077 | /* Remove any overlapping mapping symbols generated by alignment frags. */ |
| 29078 | bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0); |
| 29079 | /* Now do generic ELF adjustments. */ |
| 29080 | elf_adjust_symtab (); |
| 29081 | #endif |
| 29082 | } |
| 29083 | |
| 29084 | /* MD interface: Initialization. */ |
| 29085 | |
| 29086 | static void |
| 29087 | set_constant_flonums (void) |
| 29088 | { |
| 29089 | int i; |
| 29090 | |
| 29091 | for (i = 0; i < NUM_FLOAT_VALS; i++) |
| 29092 | if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) |
| 29093 | abort (); |
| 29094 | } |
| 29095 | |
| 29096 | /* Auto-select Thumb mode if it's the only available instruction set for the |
| 29097 | given architecture. */ |
| 29098 | |
| 29099 | static void |
| 29100 | autoselect_thumb_from_cpu_variant (void) |
| 29101 | { |
| 29102 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
| 29103 | opcode_select (16); |
| 29104 | } |
| 29105 | |
| 29106 | void |
| 29107 | md_begin (void) |
| 29108 | { |
| 29109 | unsigned mach; |
| 29110 | unsigned int i; |
| 29111 | |
| 29112 | if ( (arm_ops_hsh = hash_new ()) == NULL |
| 29113 | || (arm_cond_hsh = hash_new ()) == NULL |
| 29114 | || (arm_vcond_hsh = hash_new ()) == NULL |
| 29115 | || (arm_shift_hsh = hash_new ()) == NULL |
| 29116 | || (arm_psr_hsh = hash_new ()) == NULL |
| 29117 | || (arm_v7m_psr_hsh = hash_new ()) == NULL |
| 29118 | || (arm_reg_hsh = hash_new ()) == NULL |
| 29119 | || (arm_reloc_hsh = hash_new ()) == NULL |
| 29120 | || (arm_barrier_opt_hsh = hash_new ()) == NULL) |
| 29121 | as_fatal (_("virtual memory exhausted")); |
| 29122 | |
| 29123 | for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) |
| 29124 | hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i)); |
| 29125 | for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) |
| 29126 | hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i)); |
| 29127 | for (i = 0; i < sizeof (vconds) / sizeof (struct asm_cond); i++) |
| 29128 | hash_insert (arm_vcond_hsh, vconds[i].template_name, (void *) (vconds + i)); |
| 29129 | for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) |
| 29130 | hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i)); |
| 29131 | for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) |
| 29132 | hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i)); |
| 29133 | for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) |
| 29134 | hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name, |
| 29135 | (void *) (v7m_psrs + i)); |
| 29136 | for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) |
| 29137 | hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i)); |
| 29138 | for (i = 0; |
| 29139 | i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); |
| 29140 | i++) |
| 29141 | hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name, |
| 29142 | (void *) (barrier_opt_names + i)); |
| 29143 | #ifdef OBJ_ELF |
| 29144 | for (i = 0; i < ARRAY_SIZE (reloc_names); i++) |
| 29145 | { |
| 29146 | struct reloc_entry * entry = reloc_names + i; |
| 29147 | |
| 29148 | if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32) |
| 29149 | /* This makes encode_branch() use the EABI versions of this relocation. */ |
| 29150 | entry->reloc = BFD_RELOC_UNUSED; |
| 29151 | |
| 29152 | hash_insert (arm_reloc_hsh, entry->name, (void *) entry); |
| 29153 | } |
| 29154 | #endif |
| 29155 | |
| 29156 | set_constant_flonums (); |
| 29157 | |
| 29158 | /* Set the cpu variant based on the command-line options. We prefer |
| 29159 | -mcpu= over -march= if both are set (as for GCC); and we prefer |
| 29160 | -mfpu= over any other way of setting the floating point unit. |
| 29161 | Use of legacy options with new options are faulted. */ |
| 29162 | if (legacy_cpu) |
| 29163 | { |
| 29164 | if (mcpu_cpu_opt || march_cpu_opt) |
| 29165 | as_bad (_("use of old and new-style options to set CPU type")); |
| 29166 | |
| 29167 | selected_arch = *legacy_cpu; |
| 29168 | } |
| 29169 | else if (mcpu_cpu_opt) |
| 29170 | { |
| 29171 | selected_arch = *mcpu_cpu_opt; |
| 29172 | selected_ext = *mcpu_ext_opt; |
| 29173 | } |
| 29174 | else if (march_cpu_opt) |
| 29175 | { |
| 29176 | selected_arch = *march_cpu_opt; |
| 29177 | selected_ext = *march_ext_opt; |
| 29178 | } |
| 29179 | ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext); |
| 29180 | |
| 29181 | if (legacy_fpu) |
| 29182 | { |
| 29183 | if (mfpu_opt) |
| 29184 | as_bad (_("use of old and new-style options to set FPU type")); |
| 29185 | |
| 29186 | selected_fpu = *legacy_fpu; |
| 29187 | } |
| 29188 | else if (mfpu_opt) |
| 29189 | selected_fpu = *mfpu_opt; |
| 29190 | else |
| 29191 | { |
| 29192 | #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \ |
| 29193 | || defined (TE_NetBSD) || defined (TE_VXWORKS)) |
| 29194 | /* Some environments specify a default FPU. If they don't, infer it |
| 29195 | from the processor. */ |
| 29196 | if (mcpu_fpu_opt) |
| 29197 | selected_fpu = *mcpu_fpu_opt; |
| 29198 | else if (march_fpu_opt) |
| 29199 | selected_fpu = *march_fpu_opt; |
| 29200 | #else |
| 29201 | selected_fpu = fpu_default; |
| 29202 | #endif |
| 29203 | } |
| 29204 | |
| 29205 | if (ARM_FEATURE_ZERO (selected_fpu)) |
| 29206 | { |
| 29207 | if (!no_cpu_selected ()) |
| 29208 | selected_fpu = fpu_default; |
| 29209 | else |
| 29210 | selected_fpu = fpu_arch_fpa; |
| 29211 | } |
| 29212 | |
| 29213 | #ifdef CPU_DEFAULT |
| 29214 | if (ARM_FEATURE_ZERO (selected_arch)) |
| 29215 | { |
| 29216 | selected_arch = cpu_default; |
| 29217 | selected_cpu = selected_arch; |
| 29218 | } |
| 29219 | ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu); |
| 29220 | #else |
| 29221 | /* Autodection of feature mode: allow all features in cpu_variant but leave |
| 29222 | selected_cpu unset. It will be set in aeabi_set_public_attributes () |
| 29223 | after all instruction have been processed and we can decide what CPU |
| 29224 | should be selected. */ |
| 29225 | if (ARM_FEATURE_ZERO (selected_arch)) |
| 29226 | ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu); |
| 29227 | else |
| 29228 | ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu); |
| 29229 | #endif |
| 29230 | |
| 29231 | autoselect_thumb_from_cpu_variant (); |
| 29232 | |
| 29233 | arm_arch_used = thumb_arch_used = arm_arch_none; |
| 29234 | |
| 29235 | #if defined OBJ_COFF || defined OBJ_ELF |
| 29236 | { |
| 29237 | unsigned int flags = 0; |
| 29238 | |
| 29239 | #if defined OBJ_ELF |
| 29240 | flags = meabi_flags; |
| 29241 | |
| 29242 | switch (meabi_flags) |
| 29243 | { |
| 29244 | case EF_ARM_EABI_UNKNOWN: |
| 29245 | #endif |
| 29246 | /* Set the flags in the private structure. */ |
| 29247 | if (uses_apcs_26) flags |= F_APCS26; |
| 29248 | if (support_interwork) flags |= F_INTERWORK; |
| 29249 | if (uses_apcs_float) flags |= F_APCS_FLOAT; |
| 29250 | if (pic_code) flags |= F_PIC; |
| 29251 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) |
| 29252 | flags |= F_SOFT_FLOAT; |
| 29253 | |
| 29254 | switch (mfloat_abi_opt) |
| 29255 | { |
| 29256 | case ARM_FLOAT_ABI_SOFT: |
| 29257 | case ARM_FLOAT_ABI_SOFTFP: |
| 29258 | flags |= F_SOFT_FLOAT; |
| 29259 | break; |
| 29260 | |
| 29261 | case ARM_FLOAT_ABI_HARD: |
| 29262 | if (flags & F_SOFT_FLOAT) |
| 29263 | as_bad (_("hard-float conflicts with specified fpu")); |
| 29264 | break; |
| 29265 | } |
| 29266 | |
| 29267 | /* Using pure-endian doubles (even if soft-float). */ |
| 29268 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) |
| 29269 | flags |= F_VFP_FLOAT; |
| 29270 | |
| 29271 | #if defined OBJ_ELF |
| 29272 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) |
| 29273 | flags |= EF_ARM_MAVERICK_FLOAT; |
| 29274 | break; |
| 29275 | |
| 29276 | case EF_ARM_EABI_VER4: |
| 29277 | case EF_ARM_EABI_VER5: |
| 29278 | /* No additional flags to set. */ |
| 29279 | break; |
| 29280 | |
| 29281 | default: |
| 29282 | abort (); |
| 29283 | } |
| 29284 | #endif |
| 29285 | bfd_set_private_flags (stdoutput, flags); |
| 29286 | |
| 29287 | /* We have run out flags in the COFF header to encode the |
| 29288 | status of ATPCS support, so instead we create a dummy, |
| 29289 | empty, debug section called .arm.atpcs. */ |
| 29290 | if (atpcs) |
| 29291 | { |
| 29292 | asection * sec; |
| 29293 | |
| 29294 | sec = bfd_make_section (stdoutput, ".arm.atpcs"); |
| 29295 | |
| 29296 | if (sec != NULL) |
| 29297 | { |
| 29298 | bfd_set_section_flags |
| 29299 | (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); |
| 29300 | bfd_set_section_size (stdoutput, sec, 0); |
| 29301 | bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); |
| 29302 | } |
| 29303 | } |
| 29304 | } |
| 29305 | #endif |
| 29306 | |
| 29307 | /* Record the CPU type as well. */ |
| 29308 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)) |
| 29309 | mach = bfd_mach_arm_iWMMXt2; |
| 29310 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) |
| 29311 | mach = bfd_mach_arm_iWMMXt; |
| 29312 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) |
| 29313 | mach = bfd_mach_arm_XScale; |
| 29314 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) |
| 29315 | mach = bfd_mach_arm_ep9312; |
| 29316 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) |
| 29317 | mach = bfd_mach_arm_5TE; |
| 29318 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) |
| 29319 | { |
| 29320 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
| 29321 | mach = bfd_mach_arm_5T; |
| 29322 | else |
| 29323 | mach = bfd_mach_arm_5; |
| 29324 | } |
| 29325 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) |
| 29326 | { |
| 29327 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
| 29328 | mach = bfd_mach_arm_4T; |
| 29329 | else |
| 29330 | mach = bfd_mach_arm_4; |
| 29331 | } |
| 29332 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) |
| 29333 | mach = bfd_mach_arm_3M; |
| 29334 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) |
| 29335 | mach = bfd_mach_arm_3; |
| 29336 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) |
| 29337 | mach = bfd_mach_arm_2a; |
| 29338 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) |
| 29339 | mach = bfd_mach_arm_2; |
| 29340 | else |
| 29341 | mach = bfd_mach_arm_unknown; |
| 29342 | |
| 29343 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); |
| 29344 | } |
| 29345 | |
| 29346 | /* Command line processing. */ |
| 29347 | |
| 29348 | /* md_parse_option |
| 29349 | Invocation line includes a switch not recognized by the base assembler. |
| 29350 | See if it's a processor-specific option. |
| 29351 | |
| 29352 | This routine is somewhat complicated by the need for backwards |
| 29353 | compatibility (since older releases of gcc can't be changed). |
| 29354 | The new options try to make the interface as compatible as |
| 29355 | possible with GCC. |
| 29356 | |
| 29357 | New options (supported) are: |
| 29358 | |
| 29359 | -mcpu=<cpu name> Assemble for selected processor |
| 29360 | -march=<architecture name> Assemble for selected architecture |
| 29361 | -mfpu=<fpu architecture> Assemble for selected FPU. |
| 29362 | -EB/-mbig-endian Big-endian |
| 29363 | -EL/-mlittle-endian Little-endian |
| 29364 | -k Generate PIC code |
| 29365 | -mthumb Start in Thumb mode |
| 29366 | -mthumb-interwork Code supports ARM/Thumb interworking |
| 29367 | |
| 29368 | -m[no-]warn-deprecated Warn about deprecated features |
| 29369 | -m[no-]warn-syms Warn when symbols match instructions |
| 29370 | |
| 29371 | For now we will also provide support for: |
| 29372 | |
| 29373 | -mapcs-32 32-bit Program counter |
| 29374 | -mapcs-26 26-bit Program counter |
| 29375 | -macps-float Floats passed in FP registers |
| 29376 | -mapcs-reentrant Reentrant code |
| 29377 | -matpcs |
| 29378 | (sometime these will probably be replaced with -mapcs=<list of options> |
| 29379 | and -matpcs=<list of options>) |
| 29380 | |
| 29381 | The remaining options are only supported for back-wards compatibility. |
| 29382 | Cpu variants, the arm part is optional: |
| 29383 | -m[arm]1 Currently not supported. |
| 29384 | -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor |
| 29385 | -m[arm]3 Arm 3 processor |
| 29386 | -m[arm]6[xx], Arm 6 processors |
| 29387 | -m[arm]7[xx][t][[d]m] Arm 7 processors |
| 29388 | -m[arm]8[10] Arm 8 processors |
| 29389 | -m[arm]9[20][tdmi] Arm 9 processors |
| 29390 | -mstrongarm[110[0]] StrongARM processors |
| 29391 | -mxscale XScale processors |
| 29392 | -m[arm]v[2345[t[e]]] Arm architectures |
| 29393 | -mall All (except the ARM1) |
| 29394 | FP variants: |
| 29395 | -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions |
| 29396 | -mfpe-old (No float load/store multiples) |
| 29397 | -mvfpxd VFP Single precision |
| 29398 | -mvfp All VFP |
| 29399 | -mno-fpu Disable all floating point instructions |
| 29400 | |
| 29401 | The following CPU names are recognized: |
| 29402 | arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, |
| 29403 | arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, |
| 29404 | arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, |
| 29405 | arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, |
| 29406 | arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, |
| 29407 | arm10t arm10e, arm1020t, arm1020e, arm10200e, |
| 29408 | strongarm, strongarm110, strongarm1100, strongarm1110, xscale. |
| 29409 | |
| 29410 | */ |
| 29411 | |
| 29412 | const char * md_shortopts = "m:k"; |
| 29413 | |
| 29414 | #ifdef ARM_BI_ENDIAN |
| 29415 | #define OPTION_EB (OPTION_MD_BASE + 0) |
| 29416 | #define OPTION_EL (OPTION_MD_BASE + 1) |
| 29417 | #else |
| 29418 | #if TARGET_BYTES_BIG_ENDIAN |
| 29419 | #define OPTION_EB (OPTION_MD_BASE + 0) |
| 29420 | #else |
| 29421 | #define OPTION_EL (OPTION_MD_BASE + 1) |
| 29422 | #endif |
| 29423 | #endif |
| 29424 | #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2) |
| 29425 | #define OPTION_FDPIC (OPTION_MD_BASE + 3) |
| 29426 | |
| 29427 | struct option md_longopts[] = |
| 29428 | { |
| 29429 | #ifdef OPTION_EB |
| 29430 | {"EB", no_argument, NULL, OPTION_EB}, |
| 29431 | #endif |
| 29432 | #ifdef OPTION_EL |
| 29433 | {"EL", no_argument, NULL, OPTION_EL}, |
| 29434 | #endif |
| 29435 | {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX}, |
| 29436 | #ifdef OBJ_ELF |
| 29437 | {"fdpic", no_argument, NULL, OPTION_FDPIC}, |
| 29438 | #endif |
| 29439 | {NULL, no_argument, NULL, 0} |
| 29440 | }; |
| 29441 | |
| 29442 | size_t md_longopts_size = sizeof (md_longopts); |
| 29443 | |
| 29444 | struct arm_option_table |
| 29445 | { |
| 29446 | const char * option; /* Option name to match. */ |
| 29447 | const char * help; /* Help information. */ |
| 29448 | int * var; /* Variable to change. */ |
| 29449 | int value; /* What to change it to. */ |
| 29450 | const char * deprecated; /* If non-null, print this message. */ |
| 29451 | }; |
| 29452 | |
| 29453 | struct arm_option_table arm_opts[] = |
| 29454 | { |
| 29455 | {"k", N_("generate PIC code"), &pic_code, 1, NULL}, |
| 29456 | {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, |
| 29457 | {"mthumb-interwork", N_("support ARM/Thumb interworking"), |
| 29458 | &support_interwork, 1, NULL}, |
| 29459 | {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, |
| 29460 | {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, |
| 29461 | {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, |
| 29462 | 1, NULL}, |
| 29463 | {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, |
| 29464 | {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, |
| 29465 | {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, |
| 29466 | {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, |
| 29467 | NULL}, |
| 29468 | |
| 29469 | /* These are recognized by the assembler, but have no affect on code. */ |
| 29470 | {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, |
| 29471 | {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, |
| 29472 | |
| 29473 | {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL}, |
| 29474 | {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"), |
| 29475 | &warn_on_deprecated, 0, NULL}, |
| 29476 | {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms), TRUE, NULL}, |
| 29477 | {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms), FALSE, NULL}, |
| 29478 | {NULL, NULL, NULL, 0, NULL} |
| 29479 | }; |
| 29480 | |
| 29481 | struct arm_legacy_option_table |
| 29482 | { |
| 29483 | const char * option; /* Option name to match. */ |
| 29484 | const arm_feature_set ** var; /* Variable to change. */ |
| 29485 | const arm_feature_set value; /* What to change it to. */ |
| 29486 | const char * deprecated; /* If non-null, print this message. */ |
| 29487 | }; |
| 29488 | |
| 29489 | const struct arm_legacy_option_table arm_legacy_opts[] = |
| 29490 | { |
| 29491 | /* DON'T add any new processors to this list -- we want the whole list |
| 29492 | to go away... Add them to the processors table instead. */ |
| 29493 | {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, |
| 29494 | {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, |
| 29495 | {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, |
| 29496 | {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, |
| 29497 | {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, |
| 29498 | {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, |
| 29499 | {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, |
| 29500 | {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, |
| 29501 | {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, |
| 29502 | {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, |
| 29503 | {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, |
| 29504 | {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, |
| 29505 | {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, |
| 29506 | {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, |
| 29507 | {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, |
| 29508 | {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, |
| 29509 | {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, |
| 29510 | {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, |
| 29511 | {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, |
| 29512 | {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, |
| 29513 | {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, |
| 29514 | {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, |
| 29515 | {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, |
| 29516 | {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, |
| 29517 | {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, |
| 29518 | {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, |
| 29519 | {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, |
| 29520 | {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, |
| 29521 | {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, |
| 29522 | {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, |
| 29523 | {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, |
| 29524 | {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, |
| 29525 | {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, |
| 29526 | {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, |
| 29527 | {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, |
| 29528 | {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, |
| 29529 | {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, |
| 29530 | {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, |
| 29531 | {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, |
| 29532 | {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, |
| 29533 | {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, |
| 29534 | {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, |
| 29535 | {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, |
| 29536 | {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, |
| 29537 | {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, |
| 29538 | {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, |
| 29539 | {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, |
| 29540 | {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, |
| 29541 | {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, |
| 29542 | {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, |
| 29543 | {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, |
| 29544 | {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, |
| 29545 | {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, |
| 29546 | {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, |
| 29547 | {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, |
| 29548 | {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, |
| 29549 | {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, |
| 29550 | {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, |
| 29551 | {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, |
| 29552 | {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, |
| 29553 | {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, |
| 29554 | {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, |
| 29555 | {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, |
| 29556 | {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, |
| 29557 | {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, |
| 29558 | {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, |
| 29559 | {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, |
| 29560 | {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, |
| 29561 | {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, |
| 29562 | {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, |
| 29563 | N_("use -mcpu=strongarm110")}, |
| 29564 | {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, |
| 29565 | N_("use -mcpu=strongarm1100")}, |
| 29566 | {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, |
| 29567 | N_("use -mcpu=strongarm1110")}, |
| 29568 | {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, |
| 29569 | {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, |
| 29570 | {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, |
| 29571 | |
| 29572 | /* Architecture variants -- don't add any more to this list either. */ |
| 29573 | {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, |
| 29574 | {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, |
| 29575 | {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, |
| 29576 | {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, |
| 29577 | {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, |
| 29578 | {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, |
| 29579 | {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, |
| 29580 | {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, |
| 29581 | {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, |
| 29582 | {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, |
| 29583 | {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, |
| 29584 | {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, |
| 29585 | {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, |
| 29586 | {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, |
| 29587 | {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, |
| 29588 | {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, |
| 29589 | {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, |
| 29590 | {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, |
| 29591 | |
| 29592 | /* Floating point variants -- don't add any more to this list either. */ |
| 29593 | {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, |
| 29594 | {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, |
| 29595 | {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, |
| 29596 | {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, |
| 29597 | N_("use either -mfpu=softfpa or -mfpu=softvfp")}, |
| 29598 | |
| 29599 | {NULL, NULL, ARM_ARCH_NONE, NULL} |
| 29600 | }; |
| 29601 | |
| 29602 | struct arm_cpu_option_table |
| 29603 | { |
| 29604 | const char * name; |
| 29605 | size_t name_len; |
| 29606 | const arm_feature_set value; |
| 29607 | const arm_feature_set ext; |
| 29608 | /* For some CPUs we assume an FPU unless the user explicitly sets |
| 29609 | -mfpu=... */ |
| 29610 | const arm_feature_set default_fpu; |
| 29611 | /* The canonical name of the CPU, or NULL to use NAME converted to upper |
| 29612 | case. */ |
| 29613 | const char * canonical_name; |
| 29614 | }; |
| 29615 | |
| 29616 | /* This list should, at a minimum, contain all the cpu names |
| 29617 | recognized by GCC. */ |
| 29618 | #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN } |
| 29619 | |
| 29620 | static const struct arm_cpu_option_table arm_cpus[] = |
| 29621 | { |
| 29622 | ARM_CPU_OPT ("all", NULL, ARM_ANY, |
| 29623 | ARM_ARCH_NONE, |
| 29624 | FPU_ARCH_FPA), |
| 29625 | ARM_CPU_OPT ("arm1", NULL, ARM_ARCH_V1, |
| 29626 | ARM_ARCH_NONE, |
| 29627 | FPU_ARCH_FPA), |
| 29628 | ARM_CPU_OPT ("arm2", NULL, ARM_ARCH_V2, |
| 29629 | ARM_ARCH_NONE, |
| 29630 | FPU_ARCH_FPA), |
| 29631 | ARM_CPU_OPT ("arm250", NULL, ARM_ARCH_V2S, |
| 29632 | ARM_ARCH_NONE, |
| 29633 | FPU_ARCH_FPA), |
| 29634 | ARM_CPU_OPT ("arm3", NULL, ARM_ARCH_V2S, |
| 29635 | ARM_ARCH_NONE, |
| 29636 | FPU_ARCH_FPA), |
| 29637 | ARM_CPU_OPT ("arm6", NULL, ARM_ARCH_V3, |
| 29638 | ARM_ARCH_NONE, |
| 29639 | FPU_ARCH_FPA), |
| 29640 | ARM_CPU_OPT ("arm60", NULL, ARM_ARCH_V3, |
| 29641 | ARM_ARCH_NONE, |
| 29642 | FPU_ARCH_FPA), |
| 29643 | ARM_CPU_OPT ("arm600", NULL, ARM_ARCH_V3, |
| 29644 | ARM_ARCH_NONE, |
| 29645 | FPU_ARCH_FPA), |
| 29646 | ARM_CPU_OPT ("arm610", NULL, ARM_ARCH_V3, |
| 29647 | ARM_ARCH_NONE, |
| 29648 | FPU_ARCH_FPA), |
| 29649 | ARM_CPU_OPT ("arm620", NULL, ARM_ARCH_V3, |
| 29650 | ARM_ARCH_NONE, |
| 29651 | FPU_ARCH_FPA), |
| 29652 | ARM_CPU_OPT ("arm7", NULL, ARM_ARCH_V3, |
| 29653 | ARM_ARCH_NONE, |
| 29654 | FPU_ARCH_FPA), |
| 29655 | ARM_CPU_OPT ("arm7m", NULL, ARM_ARCH_V3M, |
| 29656 | ARM_ARCH_NONE, |
| 29657 | FPU_ARCH_FPA), |
| 29658 | ARM_CPU_OPT ("arm7d", NULL, ARM_ARCH_V3, |
| 29659 | ARM_ARCH_NONE, |
| 29660 | FPU_ARCH_FPA), |
| 29661 | ARM_CPU_OPT ("arm7dm", NULL, ARM_ARCH_V3M, |
| 29662 | ARM_ARCH_NONE, |
| 29663 | FPU_ARCH_FPA), |
| 29664 | ARM_CPU_OPT ("arm7di", NULL, ARM_ARCH_V3, |
| 29665 | ARM_ARCH_NONE, |
| 29666 | FPU_ARCH_FPA), |
| 29667 | ARM_CPU_OPT ("arm7dmi", NULL, ARM_ARCH_V3M, |
| 29668 | ARM_ARCH_NONE, |
| 29669 | FPU_ARCH_FPA), |
| 29670 | ARM_CPU_OPT ("arm70", NULL, ARM_ARCH_V3, |
| 29671 | ARM_ARCH_NONE, |
| 29672 | FPU_ARCH_FPA), |
| 29673 | ARM_CPU_OPT ("arm700", NULL, ARM_ARCH_V3, |
| 29674 | ARM_ARCH_NONE, |
| 29675 | FPU_ARCH_FPA), |
| 29676 | ARM_CPU_OPT ("arm700i", NULL, ARM_ARCH_V3, |
| 29677 | ARM_ARCH_NONE, |
| 29678 | FPU_ARCH_FPA), |
| 29679 | ARM_CPU_OPT ("arm710", NULL, ARM_ARCH_V3, |
| 29680 | ARM_ARCH_NONE, |
| 29681 | FPU_ARCH_FPA), |
| 29682 | ARM_CPU_OPT ("arm710t", NULL, ARM_ARCH_V4T, |
| 29683 | ARM_ARCH_NONE, |
| 29684 | FPU_ARCH_FPA), |
| 29685 | ARM_CPU_OPT ("arm720", NULL, ARM_ARCH_V3, |
| 29686 | ARM_ARCH_NONE, |
| 29687 | FPU_ARCH_FPA), |
| 29688 | ARM_CPU_OPT ("arm720t", NULL, ARM_ARCH_V4T, |
| 29689 | ARM_ARCH_NONE, |
| 29690 | FPU_ARCH_FPA), |
| 29691 | ARM_CPU_OPT ("arm740t", NULL, ARM_ARCH_V4T, |
| 29692 | ARM_ARCH_NONE, |
| 29693 | FPU_ARCH_FPA), |
| 29694 | ARM_CPU_OPT ("arm710c", NULL, ARM_ARCH_V3, |
| 29695 | ARM_ARCH_NONE, |
| 29696 | FPU_ARCH_FPA), |
| 29697 | ARM_CPU_OPT ("arm7100", NULL, ARM_ARCH_V3, |
| 29698 | ARM_ARCH_NONE, |
| 29699 | FPU_ARCH_FPA), |
| 29700 | ARM_CPU_OPT ("arm7500", NULL, ARM_ARCH_V3, |
| 29701 | ARM_ARCH_NONE, |
| 29702 | FPU_ARCH_FPA), |
| 29703 | ARM_CPU_OPT ("arm7500fe", NULL, ARM_ARCH_V3, |
| 29704 | ARM_ARCH_NONE, |
| 29705 | FPU_ARCH_FPA), |
| 29706 | ARM_CPU_OPT ("arm7t", NULL, ARM_ARCH_V4T, |
| 29707 | ARM_ARCH_NONE, |
| 29708 | FPU_ARCH_FPA), |
| 29709 | ARM_CPU_OPT ("arm7tdmi", NULL, ARM_ARCH_V4T, |
| 29710 | ARM_ARCH_NONE, |
| 29711 | FPU_ARCH_FPA), |
| 29712 | ARM_CPU_OPT ("arm7tdmi-s", NULL, ARM_ARCH_V4T, |
| 29713 | ARM_ARCH_NONE, |
| 29714 | FPU_ARCH_FPA), |
| 29715 | ARM_CPU_OPT ("arm8", NULL, ARM_ARCH_V4, |
| 29716 | ARM_ARCH_NONE, |
| 29717 | FPU_ARCH_FPA), |
| 29718 | ARM_CPU_OPT ("arm810", NULL, ARM_ARCH_V4, |
| 29719 | ARM_ARCH_NONE, |
| 29720 | FPU_ARCH_FPA), |
| 29721 | ARM_CPU_OPT ("strongarm", NULL, ARM_ARCH_V4, |
| 29722 | ARM_ARCH_NONE, |
| 29723 | FPU_ARCH_FPA), |
| 29724 | ARM_CPU_OPT ("strongarm1", NULL, ARM_ARCH_V4, |
| 29725 | ARM_ARCH_NONE, |
| 29726 | FPU_ARCH_FPA), |
| 29727 | ARM_CPU_OPT ("strongarm110", NULL, ARM_ARCH_V4, |
| 29728 | ARM_ARCH_NONE, |
| 29729 | FPU_ARCH_FPA), |
| 29730 | ARM_CPU_OPT ("strongarm1100", NULL, ARM_ARCH_V4, |
| 29731 | ARM_ARCH_NONE, |
| 29732 | FPU_ARCH_FPA), |
| 29733 | ARM_CPU_OPT ("strongarm1110", NULL, ARM_ARCH_V4, |
| 29734 | ARM_ARCH_NONE, |
| 29735 | FPU_ARCH_FPA), |
| 29736 | ARM_CPU_OPT ("arm9", NULL, ARM_ARCH_V4T, |
| 29737 | ARM_ARCH_NONE, |
| 29738 | FPU_ARCH_FPA), |
| 29739 | ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T, |
| 29740 | ARM_ARCH_NONE, |
| 29741 | FPU_ARCH_FPA), |
| 29742 | ARM_CPU_OPT ("arm920t", NULL, ARM_ARCH_V4T, |
| 29743 | ARM_ARCH_NONE, |
| 29744 | FPU_ARCH_FPA), |
| 29745 | ARM_CPU_OPT ("arm922t", NULL, ARM_ARCH_V4T, |
| 29746 | ARM_ARCH_NONE, |
| 29747 | FPU_ARCH_FPA), |
| 29748 | ARM_CPU_OPT ("arm940t", NULL, ARM_ARCH_V4T, |
| 29749 | ARM_ARCH_NONE, |
| 29750 | FPU_ARCH_FPA), |
| 29751 | ARM_CPU_OPT ("arm9tdmi", NULL, ARM_ARCH_V4T, |
| 29752 | ARM_ARCH_NONE, |
| 29753 | FPU_ARCH_FPA), |
| 29754 | ARM_CPU_OPT ("fa526", NULL, ARM_ARCH_V4, |
| 29755 | ARM_ARCH_NONE, |
| 29756 | FPU_ARCH_FPA), |
| 29757 | ARM_CPU_OPT ("fa626", NULL, ARM_ARCH_V4, |
| 29758 | ARM_ARCH_NONE, |
| 29759 | FPU_ARCH_FPA), |
| 29760 | |
| 29761 | /* For V5 or later processors we default to using VFP; but the user |
| 29762 | should really set the FPU type explicitly. */ |
| 29763 | ARM_CPU_OPT ("arm9e-r0", NULL, ARM_ARCH_V5TExP, |
| 29764 | ARM_ARCH_NONE, |
| 29765 | FPU_ARCH_VFP_V2), |
| 29766 | ARM_CPU_OPT ("arm9e", NULL, ARM_ARCH_V5TE, |
| 29767 | ARM_ARCH_NONE, |
| 29768 | FPU_ARCH_VFP_V2), |
| 29769 | ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ, |
| 29770 | ARM_ARCH_NONE, |
| 29771 | FPU_ARCH_VFP_V2), |
| 29772 | ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ, |
| 29773 | ARM_ARCH_NONE, |
| 29774 | FPU_ARCH_VFP_V2), |
| 29775 | ARM_CPU_OPT ("arm926ej-s", NULL, ARM_ARCH_V5TEJ, |
| 29776 | ARM_ARCH_NONE, |
| 29777 | FPU_ARCH_VFP_V2), |
| 29778 | ARM_CPU_OPT ("arm946e-r0", NULL, ARM_ARCH_V5TExP, |
| 29779 | ARM_ARCH_NONE, |
| 29780 | FPU_ARCH_VFP_V2), |
| 29781 | ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE, |
| 29782 | ARM_ARCH_NONE, |
| 29783 | FPU_ARCH_VFP_V2), |
| 29784 | ARM_CPU_OPT ("arm946e-s", NULL, ARM_ARCH_V5TE, |
| 29785 | ARM_ARCH_NONE, |
| 29786 | FPU_ARCH_VFP_V2), |
| 29787 | ARM_CPU_OPT ("arm966e-r0", NULL, ARM_ARCH_V5TExP, |
| 29788 | ARM_ARCH_NONE, |
| 29789 | FPU_ARCH_VFP_V2), |
| 29790 | ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE, |
| 29791 | ARM_ARCH_NONE, |
| 29792 | FPU_ARCH_VFP_V2), |
| 29793 | ARM_CPU_OPT ("arm966e-s", NULL, ARM_ARCH_V5TE, |
| 29794 | ARM_ARCH_NONE, |
| 29795 | FPU_ARCH_VFP_V2), |
| 29796 | ARM_CPU_OPT ("arm968e-s", NULL, ARM_ARCH_V5TE, |
| 29797 | ARM_ARCH_NONE, |
| 29798 | FPU_ARCH_VFP_V2), |
| 29799 | ARM_CPU_OPT ("arm10t", NULL, ARM_ARCH_V5T, |
| 29800 | ARM_ARCH_NONE, |
| 29801 | FPU_ARCH_VFP_V1), |
| 29802 | ARM_CPU_OPT ("arm10tdmi", NULL, ARM_ARCH_V5T, |
| 29803 | ARM_ARCH_NONE, |
| 29804 | FPU_ARCH_VFP_V1), |
| 29805 | ARM_CPU_OPT ("arm10e", NULL, ARM_ARCH_V5TE, |
| 29806 | ARM_ARCH_NONE, |
| 29807 | FPU_ARCH_VFP_V2), |
| 29808 | ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE, |
| 29809 | ARM_ARCH_NONE, |
| 29810 | FPU_ARCH_VFP_V2), |
| 29811 | ARM_CPU_OPT ("arm1020t", NULL, ARM_ARCH_V5T, |
| 29812 | ARM_ARCH_NONE, |
| 29813 | FPU_ARCH_VFP_V1), |
| 29814 | ARM_CPU_OPT ("arm1020e", NULL, ARM_ARCH_V5TE, |
| 29815 | ARM_ARCH_NONE, |
| 29816 | FPU_ARCH_VFP_V2), |
| 29817 | ARM_CPU_OPT ("arm1022e", NULL, ARM_ARCH_V5TE, |
| 29818 | ARM_ARCH_NONE, |
| 29819 | FPU_ARCH_VFP_V2), |
| 29820 | ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ, |
| 29821 | ARM_ARCH_NONE, |
| 29822 | FPU_ARCH_VFP_V2), |
| 29823 | ARM_CPU_OPT ("arm1026ej-s", NULL, ARM_ARCH_V5TEJ, |
| 29824 | ARM_ARCH_NONE, |
| 29825 | FPU_ARCH_VFP_V2), |
| 29826 | ARM_CPU_OPT ("fa606te", NULL, ARM_ARCH_V5TE, |
| 29827 | ARM_ARCH_NONE, |
| 29828 | FPU_ARCH_VFP_V2), |
| 29829 | ARM_CPU_OPT ("fa616te", NULL, ARM_ARCH_V5TE, |
| 29830 | ARM_ARCH_NONE, |
| 29831 | FPU_ARCH_VFP_V2), |
| 29832 | ARM_CPU_OPT ("fa626te", NULL, ARM_ARCH_V5TE, |
| 29833 | ARM_ARCH_NONE, |
| 29834 | FPU_ARCH_VFP_V2), |
| 29835 | ARM_CPU_OPT ("fmp626", NULL, ARM_ARCH_V5TE, |
| 29836 | ARM_ARCH_NONE, |
| 29837 | FPU_ARCH_VFP_V2), |
| 29838 | ARM_CPU_OPT ("fa726te", NULL, ARM_ARCH_V5TE, |
| 29839 | ARM_ARCH_NONE, |
| 29840 | FPU_ARCH_VFP_V2), |
| 29841 | ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6, |
| 29842 | ARM_ARCH_NONE, |
| 29843 | FPU_NONE), |
| 29844 | ARM_CPU_OPT ("arm1136j-s", NULL, ARM_ARCH_V6, |
| 29845 | ARM_ARCH_NONE, |
| 29846 | FPU_NONE), |
| 29847 | ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6, |
| 29848 | ARM_ARCH_NONE, |
| 29849 | FPU_ARCH_VFP_V2), |
| 29850 | ARM_CPU_OPT ("arm1136jf-s", NULL, ARM_ARCH_V6, |
| 29851 | ARM_ARCH_NONE, |
| 29852 | FPU_ARCH_VFP_V2), |
| 29853 | ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K, |
| 29854 | ARM_ARCH_NONE, |
| 29855 | FPU_ARCH_VFP_V2), |
| 29856 | ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K, |
| 29857 | ARM_ARCH_NONE, |
| 29858 | FPU_NONE), |
| 29859 | ARM_CPU_OPT ("arm1156t2-s", NULL, ARM_ARCH_V6T2, |
| 29860 | ARM_ARCH_NONE, |
| 29861 | FPU_NONE), |
| 29862 | ARM_CPU_OPT ("arm1156t2f-s", NULL, ARM_ARCH_V6T2, |
| 29863 | ARM_ARCH_NONE, |
| 29864 | FPU_ARCH_VFP_V2), |
| 29865 | ARM_CPU_OPT ("arm1176jz-s", NULL, ARM_ARCH_V6KZ, |
| 29866 | ARM_ARCH_NONE, |
| 29867 | FPU_NONE), |
| 29868 | ARM_CPU_OPT ("arm1176jzf-s", NULL, ARM_ARCH_V6KZ, |
| 29869 | ARM_ARCH_NONE, |
| 29870 | FPU_ARCH_VFP_V2), |
| 29871 | ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A, |
| 29872 | ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC), |
| 29873 | FPU_NONE), |
| 29874 | ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE, |
| 29875 | ARM_ARCH_NONE, |
| 29876 | FPU_ARCH_NEON_VFP_V4), |
| 29877 | ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A, |
| 29878 | ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), |
| 29879 | ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)), |
| 29880 | ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A, |
| 29881 | ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC), |
| 29882 | ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)), |
| 29883 | ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE, |
| 29884 | ARM_ARCH_NONE, |
| 29885 | FPU_ARCH_NEON_VFP_V4), |
| 29886 | ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE, |
| 29887 | ARM_ARCH_NONE, |
| 29888 | FPU_ARCH_NEON_VFP_V4), |
| 29889 | ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE, |
| 29890 | ARM_ARCH_NONE, |
| 29891 | FPU_ARCH_NEON_VFP_V4), |
| 29892 | ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A, |
| 29893 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), |
| 29894 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), |
| 29895 | ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A, |
| 29896 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), |
| 29897 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), |
| 29898 | ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A, |
| 29899 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), |
| 29900 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), |
| 29901 | ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A, |
| 29902 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 29903 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD), |
| 29904 | ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A, |
| 29905 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), |
| 29906 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), |
| 29907 | ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A, |
| 29908 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), |
| 29909 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), |
| 29910 | ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A, |
| 29911 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), |
| 29912 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), |
| 29913 | ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A, |
| 29914 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 29915 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD), |
| 29916 | ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A, |
| 29917 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 29918 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD), |
| 29919 | ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A, |
| 29920 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 29921 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD), |
| 29922 | ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R, |
| 29923 | ARM_ARCH_NONE, |
| 29924 | FPU_NONE), |
| 29925 | ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R, |
| 29926 | ARM_ARCH_NONE, |
| 29927 | FPU_ARCH_VFP_V3D16), |
| 29928 | ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R, |
| 29929 | ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), |
| 29930 | FPU_NONE), |
| 29931 | ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R, |
| 29932 | ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), |
| 29933 | FPU_ARCH_VFP_V3D16), |
| 29934 | ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R, |
| 29935 | ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), |
| 29936 | FPU_ARCH_VFP_V3D16), |
| 29937 | ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R, |
| 29938 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), |
| 29939 | FPU_ARCH_NEON_VFP_ARMV8), |
| 29940 | ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN, |
| 29941 | ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP), |
| 29942 | FPU_NONE), |
| 29943 | ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE, |
| 29944 | ARM_ARCH_NONE, |
| 29945 | FPU_NONE), |
| 29946 | ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM, |
| 29947 | ARM_ARCH_NONE, |
| 29948 | FPU_NONE), |
| 29949 | ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM, |
| 29950 | ARM_ARCH_NONE, |
| 29951 | FPU_NONE), |
| 29952 | ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M, |
| 29953 | ARM_ARCH_NONE, |
| 29954 | FPU_NONE), |
| 29955 | ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM, |
| 29956 | ARM_ARCH_NONE, |
| 29957 | FPU_NONE), |
| 29958 | ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM, |
| 29959 | ARM_ARCH_NONE, |
| 29960 | FPU_NONE), |
| 29961 | ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM, |
| 29962 | ARM_ARCH_NONE, |
| 29963 | FPU_NONE), |
| 29964 | ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A, |
| 29965 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), |
| 29966 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), |
| 29967 | ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A, |
| 29968 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 29969 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD), |
| 29970 | /* ??? XSCALE is really an architecture. */ |
| 29971 | ARM_CPU_OPT ("xscale", NULL, ARM_ARCH_XSCALE, |
| 29972 | ARM_ARCH_NONE, |
| 29973 | FPU_ARCH_VFP_V2), |
| 29974 | |
| 29975 | /* ??? iwmmxt is not a processor. */ |
| 29976 | ARM_CPU_OPT ("iwmmxt", NULL, ARM_ARCH_IWMMXT, |
| 29977 | ARM_ARCH_NONE, |
| 29978 | FPU_ARCH_VFP_V2), |
| 29979 | ARM_CPU_OPT ("iwmmxt2", NULL, ARM_ARCH_IWMMXT2, |
| 29980 | ARM_ARCH_NONE, |
| 29981 | FPU_ARCH_VFP_V2), |
| 29982 | ARM_CPU_OPT ("i80200", NULL, ARM_ARCH_XSCALE, |
| 29983 | ARM_ARCH_NONE, |
| 29984 | FPU_ARCH_VFP_V2), |
| 29985 | |
| 29986 | /* Maverick. */ |
| 29987 | ARM_CPU_OPT ("ep9312", "ARM920T", |
| 29988 | ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), |
| 29989 | ARM_ARCH_NONE, FPU_ARCH_MAVERICK), |
| 29990 | |
| 29991 | /* Marvell processors. */ |
| 29992 | ARM_CPU_OPT ("marvell-pj4", NULL, ARM_ARCH_V7A, |
| 29993 | ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC), |
| 29994 | FPU_ARCH_VFP_V3D16), |
| 29995 | ARM_CPU_OPT ("marvell-whitney", NULL, ARM_ARCH_V7A, |
| 29996 | ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC), |
| 29997 | FPU_ARCH_NEON_VFP_V4), |
| 29998 | |
| 29999 | /* APM X-Gene family. */ |
| 30000 | ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A, |
| 30001 | ARM_ARCH_NONE, |
| 30002 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), |
| 30003 | ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A, |
| 30004 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), |
| 30005 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), |
| 30006 | |
| 30007 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL } |
| 30008 | }; |
| 30009 | #undef ARM_CPU_OPT |
| 30010 | |
| 30011 | struct arm_ext_table |
| 30012 | { |
| 30013 | const char * name; |
| 30014 | size_t name_len; |
| 30015 | const arm_feature_set merge; |
| 30016 | const arm_feature_set clear; |
| 30017 | }; |
| 30018 | |
| 30019 | struct arm_arch_option_table |
| 30020 | { |
| 30021 | const char * name; |
| 30022 | size_t name_len; |
| 30023 | const arm_feature_set value; |
| 30024 | const arm_feature_set default_fpu; |
| 30025 | const struct arm_ext_table * ext_table; |
| 30026 | }; |
| 30027 | |
| 30028 | /* Used to add support for +E and +noE extension. */ |
| 30029 | #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C } |
| 30030 | /* Used to add support for a +E extension. */ |
| 30031 | #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE } |
| 30032 | /* Used to add support for a +noE extension. */ |
| 30033 | #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C } |
| 30034 | |
| 30035 | #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \ |
| 30036 | ~0 & ~FPU_ENDIAN_PURE) |
| 30037 | |
| 30038 | static const struct arm_ext_table armv5te_ext_table[] = |
| 30039 | { |
| 30040 | ARM_EXT ("fp", FPU_ARCH_VFP_V2, ALL_FP), |
| 30041 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } |
| 30042 | }; |
| 30043 | |
| 30044 | static const struct arm_ext_table armv7_ext_table[] = |
| 30045 | { |
| 30046 | ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP), |
| 30047 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } |
| 30048 | }; |
| 30049 | |
| 30050 | static const struct arm_ext_table armv7ve_ext_table[] = |
| 30051 | { |
| 30052 | ARM_EXT ("fp", FPU_ARCH_VFP_V4D16, ALL_FP), |
| 30053 | ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), |
| 30054 | ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3), |
| 30055 | ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16), |
| 30056 | ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16), |
| 30057 | ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16), /* Alias for +fp. */ |
| 30058 | ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4), |
| 30059 | |
| 30060 | ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4, |
| 30061 | ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)), |
| 30062 | |
| 30063 | /* Aliases for +simd. */ |
| 30064 | ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4), |
| 30065 | |
| 30066 | ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1), |
| 30067 | ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1), |
| 30068 | ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16), |
| 30069 | |
| 30070 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } |
| 30071 | }; |
| 30072 | |
| 30073 | static const struct arm_ext_table armv7a_ext_table[] = |
| 30074 | { |
| 30075 | ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP), |
| 30076 | ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp. */ |
| 30077 | ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3), |
| 30078 | ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16), |
| 30079 | ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16), |
| 30080 | ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16), |
| 30081 | ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4), |
| 30082 | |
| 30083 | ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1, |
| 30084 | ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)), |
| 30085 | |
| 30086 | /* Aliases for +simd. */ |
| 30087 | ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1), |
| 30088 | ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1), |
| 30089 | |
| 30090 | ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16), |
| 30091 | ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4), |
| 30092 | |
| 30093 | ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP)), |
| 30094 | ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC)), |
| 30095 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } |
| 30096 | }; |
| 30097 | |
| 30098 | static const struct arm_ext_table armv7r_ext_table[] = |
| 30099 | { |
| 30100 | ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD), |
| 30101 | ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD), /* Alias for +fp.sp. */ |
| 30102 | ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP), |
| 30103 | ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp. */ |
| 30104 | ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16), |
| 30105 | ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16), |
| 30106 | ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV), |
| 30107 | ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV)), |
| 30108 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } |
| 30109 | }; |
| 30110 | |
| 30111 | static const struct arm_ext_table armv7em_ext_table[] = |
| 30112 | { |
| 30113 | ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16, ALL_FP), |
| 30114 | /* Alias for +fp, used to be known as fpv4-sp-d16. */ |
| 30115 | ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16), |
| 30116 | ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16), |
| 30117 | ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16), |
| 30118 | ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16), |
| 30119 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } |
| 30120 | }; |
| 30121 | |
| 30122 | static const struct arm_ext_table armv8a_ext_table[] = |
| 30123 | { |
| 30124 | ARM_ADD ("crc", ARCH_CRC_ARMV8), |
| 30125 | ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8), |
| 30126 | ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, |
| 30127 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)), |
| 30128 | |
| 30129 | /* Armv8-a does not allow an FP implementation without SIMD, so the user |
| 30130 | should use the +simd option to turn on FP. */ |
| 30131 | ARM_REMOVE ("fp", ALL_FP), |
| 30132 | ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)), |
| 30133 | ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)), |
| 30134 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } |
| 30135 | }; |
| 30136 | |
| 30137 | |
| 30138 | static const struct arm_ext_table armv81a_ext_table[] = |
| 30139 | { |
| 30140 | ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1), |
| 30141 | ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1, |
| 30142 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)), |
| 30143 | |
| 30144 | /* Armv8-a does not allow an FP implementation without SIMD, so the user |
| 30145 | should use the +simd option to turn on FP. */ |
| 30146 | ARM_REMOVE ("fp", ALL_FP), |
| 30147 | ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)), |
| 30148 | ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)), |
| 30149 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } |
| 30150 | }; |
| 30151 | |
| 30152 | static const struct arm_ext_table armv82a_ext_table[] = |
| 30153 | { |
| 30154 | ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1), |
| 30155 | ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16), |
| 30156 | ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML), |
| 30157 | ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1, |
| 30158 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)), |
| 30159 | ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8), |
| 30160 | |
| 30161 | /* Armv8-a does not allow an FP implementation without SIMD, so the user |
| 30162 | should use the +simd option to turn on FP. */ |
| 30163 | ARM_REMOVE ("fp", ALL_FP), |
| 30164 | ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)), |
| 30165 | ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)), |
| 30166 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } |
| 30167 | }; |
| 30168 | |
| 30169 | static const struct arm_ext_table armv84a_ext_table[] = |
| 30170 | { |
| 30171 | ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8), |
| 30172 | ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML), |
| 30173 | ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4, |
| 30174 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)), |
| 30175 | |
| 30176 | /* Armv8-a does not allow an FP implementation without SIMD, so the user |
| 30177 | should use the +simd option to turn on FP. */ |
| 30178 | ARM_REMOVE ("fp", ALL_FP), |
| 30179 | ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)), |
| 30180 | ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)), |
| 30181 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } |
| 30182 | }; |
| 30183 | |
| 30184 | static const struct arm_ext_table armv85a_ext_table[] = |
| 30185 | { |
| 30186 | ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8), |
| 30187 | ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML), |
| 30188 | ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4, |
| 30189 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)), |
| 30190 | |
| 30191 | /* Armv8-a does not allow an FP implementation without SIMD, so the user |
| 30192 | should use the +simd option to turn on FP. */ |
| 30193 | ARM_REMOVE ("fp", ALL_FP), |
| 30194 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } |
| 30195 | }; |
| 30196 | |
| 30197 | static const struct arm_ext_table armv8m_main_ext_table[] = |
| 30198 | { |
| 30199 | ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP), |
| 30200 | ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP)), |
| 30201 | ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16, ALL_FP), |
| 30202 | ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16), |
| 30203 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } |
| 30204 | }; |
| 30205 | |
| 30206 | static const struct arm_ext_table armv8_1m_main_ext_table[] = |
| 30207 | { |
| 30208 | ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP), |
| 30209 | ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP)), |
| 30210 | ARM_EXT ("fp", |
| 30211 | ARM_FEATURE (0, ARM_EXT2_FP16_INST, |
| 30212 | FPU_VFP_V5_SP_D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA), |
| 30213 | ALL_FP), |
| 30214 | ARM_ADD ("fp.dp", |
| 30215 | ARM_FEATURE (0, ARM_EXT2_FP16_INST, |
| 30216 | FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)), |
| 30217 | ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE), |
| 30218 | ARM_FEATURE_COPROC (FPU_MVE | FPU_MVE_FP)), |
| 30219 | ARM_ADD ("mve.fp", |
| 30220 | ARM_FEATURE (0, ARM_EXT2_FP16_INST, |
| 30221 | FPU_MVE | FPU_MVE_FP | FPU_VFP_V5_SP_D16 | |
| 30222 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)), |
| 30223 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } |
| 30224 | }; |
| 30225 | |
| 30226 | static const struct arm_ext_table armv8r_ext_table[] = |
| 30227 | { |
| 30228 | ARM_ADD ("crc", ARCH_CRC_ARMV8), |
| 30229 | ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8), |
| 30230 | ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, |
| 30231 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)), |
| 30232 | ARM_REMOVE ("fp", ALL_FP), |
| 30233 | ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16), |
| 30234 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } |
| 30235 | }; |
| 30236 | |
| 30237 | /* This list should, at a minimum, contain all the architecture names |
| 30238 | recognized by GCC. */ |
| 30239 | #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL } |
| 30240 | #define ARM_ARCH_OPT2(N, V, DF, ext) \ |
| 30241 | { N, sizeof (N) - 1, V, DF, ext##_ext_table } |
| 30242 | |
| 30243 | static const struct arm_arch_option_table arm_archs[] = |
| 30244 | { |
| 30245 | ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA), |
| 30246 | ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA), |
| 30247 | ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA), |
| 30248 | ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA), |
| 30249 | ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA), |
| 30250 | ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA), |
| 30251 | ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA), |
| 30252 | ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA), |
| 30253 | ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA), |
| 30254 | ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA), |
| 30255 | ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA), |
| 30256 | ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP), |
| 30257 | ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP), |
| 30258 | ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP), |
| 30259 | ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP, armv5te), |
| 30260 | ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP, armv5te), |
| 30261 | ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP, armv5te), |
| 30262 | ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP, armv5te), |
| 30263 | ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP, armv5te), |
| 30264 | ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP, armv5te), |
| 30265 | ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP, armv5te), |
| 30266 | /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is |
| 30267 | kept to preserve existing behaviour. */ |
| 30268 | ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ, FPU_ARCH_VFP, armv5te), |
| 30269 | ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ, FPU_ARCH_VFP, armv5te), |
| 30270 | ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP, armv5te), |
| 30271 | ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP, armv5te), |
| 30272 | ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP, armv5te), |
| 30273 | /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is |
| 30274 | kept to preserve existing behaviour. */ |
| 30275 | ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP, armv5te), |
| 30276 | ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP, armv5te), |
| 30277 | ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP), |
| 30278 | ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP), |
| 30279 | ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP, armv7), |
| 30280 | /* The official spelling of the ARMv7 profile variants is the dashed form. |
| 30281 | Accept the non-dashed form for compatibility with old toolchains. */ |
| 30282 | ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP, armv7a), |
| 30283 | ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE, FPU_ARCH_VFP, armv7ve), |
| 30284 | ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP, armv7r), |
| 30285 | ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP), |
| 30286 | ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP, armv7a), |
| 30287 | ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP, armv7r), |
| 30288 | ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP), |
| 30289 | ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP, armv7em), |
| 30290 | ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE, FPU_ARCH_VFP), |
| 30291 | ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN, FPU_ARCH_VFP, |
| 30292 | armv8m_main), |
| 30293 | ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN, FPU_ARCH_VFP, |
| 30294 | armv8_1m_main), |
| 30295 | ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP, armv8a), |
| 30296 | ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP, armv81a), |
| 30297 | ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A, FPU_ARCH_VFP, armv82a), |
| 30298 | ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A, FPU_ARCH_VFP, armv82a), |
| 30299 | ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R, FPU_ARCH_VFP, armv8r), |
| 30300 | ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A, FPU_ARCH_VFP, armv84a), |
| 30301 | ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A, FPU_ARCH_VFP, armv85a), |
| 30302 | ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP), |
| 30303 | ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP), |
| 30304 | ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2, FPU_ARCH_VFP), |
| 30305 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL } |
| 30306 | }; |
| 30307 | #undef ARM_ARCH_OPT |
| 30308 | |
| 30309 | /* ISA extensions in the co-processor and main instruction set space. */ |
| 30310 | |
| 30311 | struct arm_option_extension_value_table |
| 30312 | { |
| 30313 | const char * name; |
| 30314 | size_t name_len; |
| 30315 | const arm_feature_set merge_value; |
| 30316 | const arm_feature_set clear_value; |
| 30317 | /* List of architectures for which an extension is available. ARM_ARCH_NONE |
| 30318 | indicates that an extension is available for all architectures while |
| 30319 | ARM_ANY marks an empty entry. */ |
| 30320 | const arm_feature_set allowed_archs[2]; |
| 30321 | }; |
| 30322 | |
| 30323 | /* The following table must be in alphabetical order with a NULL last entry. */ |
| 30324 | |
| 30325 | #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } } |
| 30326 | #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} } |
| 30327 | |
| 30328 | /* DEPRECATED: Refrain from using this table to add any new extensions, instead |
| 30329 | use the context sensitive approach using arm_ext_table's. */ |
| 30330 | static const struct arm_option_extension_value_table arm_extensions[] = |
| 30331 | { |
| 30332 | ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE_COPROC (CRC_EXT_ARMV8), |
| 30333 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), |
| 30334 | ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, |
| 30335 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8), |
| 30336 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), |
| 30337 | ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8, |
| 30338 | ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), |
| 30339 | ARM_ARCH_V8_2A), |
| 30340 | ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP), |
| 30341 | ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP), |
| 30342 | ARM_FEATURE_CORE (ARM_EXT_V7M, ARM_EXT2_V8M)), |
| 30343 | ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, ARM_FEATURE_COPROC (FPU_VFP_ARMV8), |
| 30344 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), |
| 30345 | ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 30346 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 30347 | ARM_ARCH_V8_2A), |
| 30348 | ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST |
| 30349 | | ARM_EXT2_FP16_FML), |
| 30350 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST |
| 30351 | | ARM_EXT2_FP16_FML), |
| 30352 | ARM_ARCH_V8_2A), |
| 30353 | ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV), |
| 30354 | ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV), |
| 30355 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7A), |
| 30356 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)), |
| 30357 | /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of |
| 30358 | Thumb divide instruction. Due to this having the same name as the |
| 30359 | previous entry, this will be ignored when doing command-line parsing and |
| 30360 | only considered by build attribute selection code. */ |
| 30361 | ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), |
| 30362 | ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), |
| 30363 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7)), |
| 30364 | ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), |
| 30365 | ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), ARM_ARCH_NONE), |
| 30366 | ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), |
| 30367 | ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), ARM_ARCH_NONE), |
| 30368 | ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), |
| 30369 | ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), ARM_ARCH_NONE), |
| 30370 | ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP), |
| 30371 | ARM_FEATURE_CORE_LOW (ARM_EXT_MP), |
| 30372 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7A), |
| 30373 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)), |
| 30374 | ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS), |
| 30375 | ARM_FEATURE_CORE_LOW (ARM_EXT_OS), |
| 30376 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6M)), |
| 30377 | ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), |
| 30378 | ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0), |
| 30379 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)), |
| 30380 | ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES), |
| 30381 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES), |
| 30382 | ARM_ARCH_V8A), |
| 30383 | ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), |
| 30384 | ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_RAS, 0), |
| 30385 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)), |
| 30386 | ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1, |
| 30387 | ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA), |
| 30388 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)), |
| 30389 | ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), |
| 30390 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), |
| 30391 | ARM_ARCH_V8A), |
| 30392 | ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), |
| 30393 | ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), |
| 30394 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), |
| 30395 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)), |
| 30396 | ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8, |
| 30397 | ARM_FEATURE_COPROC (FPU_NEON_ARMV8), |
| 30398 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), |
| 30399 | ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT | ARM_EXT_ADIV |
| 30400 | | ARM_EXT_DIV), |
| 30401 | ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), |
| 30402 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)), |
| 30403 | ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 30404 | ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), ARM_ARCH_NONE), |
| 30405 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, { ARM_ARCH_NONE, ARM_ARCH_NONE } } |
| 30406 | }; |
| 30407 | #undef ARM_EXT_OPT |
| 30408 | |
| 30409 | /* ISA floating-point and Advanced SIMD extensions. */ |
| 30410 | struct arm_option_fpu_value_table |
| 30411 | { |
| 30412 | const char * name; |
| 30413 | const arm_feature_set value; |
| 30414 | }; |
| 30415 | |
| 30416 | /* This list should, at a minimum, contain all the fpu names |
| 30417 | recognized by GCC. */ |
| 30418 | static const struct arm_option_fpu_value_table arm_fpus[] = |
| 30419 | { |
| 30420 | {"softfpa", FPU_NONE}, |
| 30421 | {"fpe", FPU_ARCH_FPE}, |
| 30422 | {"fpe2", FPU_ARCH_FPE}, |
| 30423 | {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ |
| 30424 | {"fpa", FPU_ARCH_FPA}, |
| 30425 | {"fpa10", FPU_ARCH_FPA}, |
| 30426 | {"fpa11", FPU_ARCH_FPA}, |
| 30427 | {"arm7500fe", FPU_ARCH_FPA}, |
| 30428 | {"softvfp", FPU_ARCH_VFP}, |
| 30429 | {"softvfp+vfp", FPU_ARCH_VFP_V2}, |
| 30430 | {"vfp", FPU_ARCH_VFP_V2}, |
| 30431 | {"vfp9", FPU_ARCH_VFP_V2}, |
| 30432 | {"vfp3", FPU_ARCH_VFP_V3}, /* Undocumented, use vfpv3. */ |
| 30433 | {"vfp10", FPU_ARCH_VFP_V2}, |
| 30434 | {"vfp10-r0", FPU_ARCH_VFP_V1}, |
| 30435 | {"vfpxd", FPU_ARCH_VFP_V1xD}, |
| 30436 | {"vfpv2", FPU_ARCH_VFP_V2}, |
| 30437 | {"vfpv3", FPU_ARCH_VFP_V3}, |
| 30438 | {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16}, |
| 30439 | {"vfpv3-d16", FPU_ARCH_VFP_V3D16}, |
| 30440 | {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16}, |
| 30441 | {"vfpv3xd", FPU_ARCH_VFP_V3xD}, |
| 30442 | {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16}, |
| 30443 | {"arm1020t", FPU_ARCH_VFP_V1}, |
| 30444 | {"arm1020e", FPU_ARCH_VFP_V2}, |
| 30445 | {"arm1136jfs", FPU_ARCH_VFP_V2}, /* Undocumented, use arm1136jf-s. */ |
| 30446 | {"arm1136jf-s", FPU_ARCH_VFP_V2}, |
| 30447 | {"maverick", FPU_ARCH_MAVERICK}, |
| 30448 | {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, |
| 30449 | {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, |
| 30450 | {"neon-fp16", FPU_ARCH_NEON_FP16}, |
| 30451 | {"vfpv4", FPU_ARCH_VFP_V4}, |
| 30452 | {"vfpv4-d16", FPU_ARCH_VFP_V4D16}, |
| 30453 | {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16}, |
| 30454 | {"fpv5-d16", FPU_ARCH_VFP_V5D16}, |
| 30455 | {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16}, |
| 30456 | {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4}, |
| 30457 | {"fp-armv8", FPU_ARCH_VFP_ARMV8}, |
| 30458 | {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8}, |
| 30459 | {"crypto-neon-fp-armv8", |
| 30460 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8}, |
| 30461 | {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1}, |
| 30462 | {"crypto-neon-fp-armv8.1", |
| 30463 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1}, |
| 30464 | {NULL, ARM_ARCH_NONE} |
| 30465 | }; |
| 30466 | |
| 30467 | struct arm_option_value_table |
| 30468 | { |
| 30469 | const char *name; |
| 30470 | long value; |
| 30471 | }; |
| 30472 | |
| 30473 | static const struct arm_option_value_table arm_float_abis[] = |
| 30474 | { |
| 30475 | {"hard", ARM_FLOAT_ABI_HARD}, |
| 30476 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, |
| 30477 | {"soft", ARM_FLOAT_ABI_SOFT}, |
| 30478 | {NULL, 0} |
| 30479 | }; |
| 30480 | |
| 30481 | #ifdef OBJ_ELF |
| 30482 | /* We only know how to output GNU and ver 4/5 (AAELF) formats. */ |
| 30483 | static const struct arm_option_value_table arm_eabis[] = |
| 30484 | { |
| 30485 | {"gnu", EF_ARM_EABI_UNKNOWN}, |
| 30486 | {"4", EF_ARM_EABI_VER4}, |
| 30487 | {"5", EF_ARM_EABI_VER5}, |
| 30488 | {NULL, 0} |
| 30489 | }; |
| 30490 | #endif |
| 30491 | |
| 30492 | struct arm_long_option_table |
| 30493 | { |
| 30494 | const char * option; /* Substring to match. */ |
| 30495 | const char * help; /* Help information. */ |
| 30496 | int (* func) (const char * subopt); /* Function to decode sub-option. */ |
| 30497 | const char * deprecated; /* If non-null, print this message. */ |
| 30498 | }; |
| 30499 | |
| 30500 | static bfd_boolean |
| 30501 | arm_parse_extension (const char *str, const arm_feature_set *opt_set, |
| 30502 | arm_feature_set *ext_set, |
| 30503 | const struct arm_ext_table *ext_table) |
| 30504 | { |
| 30505 | /* We insist on extensions being specified in alphabetical order, and with |
| 30506 | extensions being added before being removed. We achieve this by having |
| 30507 | the global ARM_EXTENSIONS table in alphabetical order, and using the |
| 30508 | ADDING_VALUE variable to indicate whether we are adding an extension (1) |
| 30509 | or removing it (0) and only allowing it to change in the order |
| 30510 | -1 -> 1 -> 0. */ |
| 30511 | const struct arm_option_extension_value_table * opt = NULL; |
| 30512 | const arm_feature_set arm_any = ARM_ANY; |
| 30513 | int adding_value = -1; |
| 30514 | |
| 30515 | while (str != NULL && *str != 0) |
| 30516 | { |
| 30517 | const char *ext; |
| 30518 | size_t len; |
| 30519 | |
| 30520 | if (*str != '+') |
| 30521 | { |
| 30522 | as_bad (_("invalid architectural extension")); |
| 30523 | return FALSE; |
| 30524 | } |
| 30525 | |
| 30526 | str++; |
| 30527 | ext = strchr (str, '+'); |
| 30528 | |
| 30529 | if (ext != NULL) |
| 30530 | len = ext - str; |
| 30531 | else |
| 30532 | len = strlen (str); |
| 30533 | |
| 30534 | if (len >= 2 && strncmp (str, "no", 2) == 0) |
| 30535 | { |
| 30536 | if (adding_value != 0) |
| 30537 | { |
| 30538 | adding_value = 0; |
| 30539 | opt = arm_extensions; |
| 30540 | } |
| 30541 | |
| 30542 | len -= 2; |
| 30543 | str += 2; |
| 30544 | } |
| 30545 | else if (len > 0) |
| 30546 | { |
| 30547 | if (adding_value == -1) |
| 30548 | { |
| 30549 | adding_value = 1; |
| 30550 | opt = arm_extensions; |
| 30551 | } |
| 30552 | else if (adding_value != 1) |
| 30553 | { |
| 30554 | as_bad (_("must specify extensions to add before specifying " |
| 30555 | "those to remove")); |
| 30556 | return FALSE; |
| 30557 | } |
| 30558 | } |
| 30559 | |
| 30560 | if (len == 0) |
| 30561 | { |
| 30562 | as_bad (_("missing architectural extension")); |
| 30563 | return FALSE; |
| 30564 | } |
| 30565 | |
| 30566 | gas_assert (adding_value != -1); |
| 30567 | gas_assert (opt != NULL); |
| 30568 | |
| 30569 | if (ext_table != NULL) |
| 30570 | { |
| 30571 | const struct arm_ext_table * ext_opt = ext_table; |
| 30572 | bfd_boolean found = FALSE; |
| 30573 | for (; ext_opt->name != NULL; ext_opt++) |
| 30574 | if (ext_opt->name_len == len |
| 30575 | && strncmp (ext_opt->name, str, len) == 0) |
| 30576 | { |
| 30577 | if (adding_value) |
| 30578 | { |
| 30579 | if (ARM_FEATURE_ZERO (ext_opt->merge)) |
| 30580 | /* TODO: Option not supported. When we remove the |
| 30581 | legacy table this case should error out. */ |
| 30582 | continue; |
| 30583 | |
| 30584 | ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, ext_opt->merge); |
| 30585 | } |
| 30586 | else |
| 30587 | { |
| 30588 | if (ARM_FEATURE_ZERO (ext_opt->clear)) |
| 30589 | /* TODO: Option not supported. When we remove the |
| 30590 | legacy table this case should error out. */ |
| 30591 | continue; |
| 30592 | ARM_CLEAR_FEATURE (*ext_set, *ext_set, ext_opt->clear); |
| 30593 | } |
| 30594 | found = TRUE; |
| 30595 | break; |
| 30596 | } |
| 30597 | if (found) |
| 30598 | { |
| 30599 | str = ext; |
| 30600 | continue; |
| 30601 | } |
| 30602 | } |
| 30603 | |
| 30604 | /* Scan over the options table trying to find an exact match. */ |
| 30605 | for (; opt->name != NULL; opt++) |
| 30606 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
| 30607 | { |
| 30608 | int i, nb_allowed_archs = |
| 30609 | sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]); |
| 30610 | /* Check we can apply the extension to this architecture. */ |
| 30611 | for (i = 0; i < nb_allowed_archs; i++) |
| 30612 | { |
| 30613 | /* Empty entry. */ |
| 30614 | if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_any)) |
| 30615 | continue; |
| 30616 | if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *opt_set)) |
| 30617 | break; |
| 30618 | } |
| 30619 | if (i == nb_allowed_archs) |
| 30620 | { |
| 30621 | as_bad (_("extension does not apply to the base architecture")); |
| 30622 | return FALSE; |
| 30623 | } |
| 30624 | |
| 30625 | /* Add or remove the extension. */ |
| 30626 | if (adding_value) |
| 30627 | ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->merge_value); |
| 30628 | else |
| 30629 | ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->clear_value); |
| 30630 | |
| 30631 | /* Allowing Thumb division instructions for ARMv7 in autodetection |
| 30632 | rely on this break so that duplicate extensions (extensions |
| 30633 | with the same name as a previous extension in the list) are not |
| 30634 | considered for command-line parsing. */ |
| 30635 | break; |
| 30636 | } |
| 30637 | |
| 30638 | if (opt->name == NULL) |
| 30639 | { |
| 30640 | /* Did we fail to find an extension because it wasn't specified in |
| 30641 | alphabetical order, or because it does not exist? */ |
| 30642 | |
| 30643 | for (opt = arm_extensions; opt->name != NULL; opt++) |
| 30644 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
| 30645 | break; |
| 30646 | |
| 30647 | if (opt->name == NULL) |
| 30648 | as_bad (_("unknown architectural extension `%s'"), str); |
| 30649 | else |
| 30650 | as_bad (_("architectural extensions must be specified in " |
| 30651 | "alphabetical order")); |
| 30652 | |
| 30653 | return FALSE; |
| 30654 | } |
| 30655 | else |
| 30656 | { |
| 30657 | /* We should skip the extension we've just matched the next time |
| 30658 | round. */ |
| 30659 | opt++; |
| 30660 | } |
| 30661 | |
| 30662 | str = ext; |
| 30663 | }; |
| 30664 | |
| 30665 | return TRUE; |
| 30666 | } |
| 30667 | |
| 30668 | static bfd_boolean |
| 30669 | arm_parse_cpu (const char *str) |
| 30670 | { |
| 30671 | const struct arm_cpu_option_table *opt; |
| 30672 | const char *ext = strchr (str, '+'); |
| 30673 | size_t len; |
| 30674 | |
| 30675 | if (ext != NULL) |
| 30676 | len = ext - str; |
| 30677 | else |
| 30678 | len = strlen (str); |
| 30679 | |
| 30680 | if (len == 0) |
| 30681 | { |
| 30682 | as_bad (_("missing cpu name `%s'"), str); |
| 30683 | return FALSE; |
| 30684 | } |
| 30685 | |
| 30686 | for (opt = arm_cpus; opt->name != NULL; opt++) |
| 30687 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
| 30688 | { |
| 30689 | mcpu_cpu_opt = &opt->value; |
| 30690 | if (mcpu_ext_opt == NULL) |
| 30691 | mcpu_ext_opt = XNEW (arm_feature_set); |
| 30692 | *mcpu_ext_opt = opt->ext; |
| 30693 | mcpu_fpu_opt = &opt->default_fpu; |
| 30694 | if (opt->canonical_name) |
| 30695 | { |
| 30696 | gas_assert (sizeof selected_cpu_name > strlen (opt->canonical_name)); |
| 30697 | strcpy (selected_cpu_name, opt->canonical_name); |
| 30698 | } |
| 30699 | else |
| 30700 | { |
| 30701 | size_t i; |
| 30702 | |
| 30703 | if (len >= sizeof selected_cpu_name) |
| 30704 | len = (sizeof selected_cpu_name) - 1; |
| 30705 | |
| 30706 | for (i = 0; i < len; i++) |
| 30707 | selected_cpu_name[i] = TOUPPER (opt->name[i]); |
| 30708 | selected_cpu_name[i] = 0; |
| 30709 | } |
| 30710 | |
| 30711 | if (ext != NULL) |
| 30712 | return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, NULL); |
| 30713 | |
| 30714 | return TRUE; |
| 30715 | } |
| 30716 | |
| 30717 | as_bad (_("unknown cpu `%s'"), str); |
| 30718 | return FALSE; |
| 30719 | } |
| 30720 | |
| 30721 | static bfd_boolean |
| 30722 | arm_parse_arch (const char *str) |
| 30723 | { |
| 30724 | const struct arm_arch_option_table *opt; |
| 30725 | const char *ext = strchr (str, '+'); |
| 30726 | size_t len; |
| 30727 | |
| 30728 | if (ext != NULL) |
| 30729 | len = ext - str; |
| 30730 | else |
| 30731 | len = strlen (str); |
| 30732 | |
| 30733 | if (len == 0) |
| 30734 | { |
| 30735 | as_bad (_("missing architecture name `%s'"), str); |
| 30736 | return FALSE; |
| 30737 | } |
| 30738 | |
| 30739 | for (opt = arm_archs; opt->name != NULL; opt++) |
| 30740 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
| 30741 | { |
| 30742 | march_cpu_opt = &opt->value; |
| 30743 | if (march_ext_opt == NULL) |
| 30744 | march_ext_opt = XNEW (arm_feature_set); |
| 30745 | *march_ext_opt = arm_arch_none; |
| 30746 | march_fpu_opt = &opt->default_fpu; |
| 30747 | strcpy (selected_cpu_name, opt->name); |
| 30748 | |
| 30749 | if (ext != NULL) |
| 30750 | return arm_parse_extension (ext, march_cpu_opt, march_ext_opt, |
| 30751 | opt->ext_table); |
| 30752 | |
| 30753 | return TRUE; |
| 30754 | } |
| 30755 | |
| 30756 | as_bad (_("unknown architecture `%s'\n"), str); |
| 30757 | return FALSE; |
| 30758 | } |
| 30759 | |
| 30760 | static bfd_boolean |
| 30761 | arm_parse_fpu (const char * str) |
| 30762 | { |
| 30763 | const struct arm_option_fpu_value_table * opt; |
| 30764 | |
| 30765 | for (opt = arm_fpus; opt->name != NULL; opt++) |
| 30766 | if (streq (opt->name, str)) |
| 30767 | { |
| 30768 | mfpu_opt = &opt->value; |
| 30769 | return TRUE; |
| 30770 | } |
| 30771 | |
| 30772 | as_bad (_("unknown floating point format `%s'\n"), str); |
| 30773 | return FALSE; |
| 30774 | } |
| 30775 | |
| 30776 | static bfd_boolean |
| 30777 | arm_parse_float_abi (const char * str) |
| 30778 | { |
| 30779 | const struct arm_option_value_table * opt; |
| 30780 | |
| 30781 | for (opt = arm_float_abis; opt->name != NULL; opt++) |
| 30782 | if (streq (opt->name, str)) |
| 30783 | { |
| 30784 | mfloat_abi_opt = opt->value; |
| 30785 | return TRUE; |
| 30786 | } |
| 30787 | |
| 30788 | as_bad (_("unknown floating point abi `%s'\n"), str); |
| 30789 | return FALSE; |
| 30790 | } |
| 30791 | |
| 30792 | #ifdef OBJ_ELF |
| 30793 | static bfd_boolean |
| 30794 | arm_parse_eabi (const char * str) |
| 30795 | { |
| 30796 | const struct arm_option_value_table *opt; |
| 30797 | |
| 30798 | for (opt = arm_eabis; opt->name != NULL; opt++) |
| 30799 | if (streq (opt->name, str)) |
| 30800 | { |
| 30801 | meabi_flags = opt->value; |
| 30802 | return TRUE; |
| 30803 | } |
| 30804 | as_bad (_("unknown EABI `%s'\n"), str); |
| 30805 | return FALSE; |
| 30806 | } |
| 30807 | #endif |
| 30808 | |
| 30809 | static bfd_boolean |
| 30810 | arm_parse_it_mode (const char * str) |
| 30811 | { |
| 30812 | bfd_boolean ret = TRUE; |
| 30813 | |
| 30814 | if (streq ("arm", str)) |
| 30815 | implicit_it_mode = IMPLICIT_IT_MODE_ARM; |
| 30816 | else if (streq ("thumb", str)) |
| 30817 | implicit_it_mode = IMPLICIT_IT_MODE_THUMB; |
| 30818 | else if (streq ("always", str)) |
| 30819 | implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS; |
| 30820 | else if (streq ("never", str)) |
| 30821 | implicit_it_mode = IMPLICIT_IT_MODE_NEVER; |
| 30822 | else |
| 30823 | { |
| 30824 | as_bad (_("unknown implicit IT mode `%s', should be "\ |
| 30825 | "arm, thumb, always, or never."), str); |
| 30826 | ret = FALSE; |
| 30827 | } |
| 30828 | |
| 30829 | return ret; |
| 30830 | } |
| 30831 | |
| 30832 | static bfd_boolean |
| 30833 | arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED) |
| 30834 | { |
| 30835 | codecomposer_syntax = TRUE; |
| 30836 | arm_comment_chars[0] = ';'; |
| 30837 | arm_line_separator_chars[0] = 0; |
| 30838 | return TRUE; |
| 30839 | } |
| 30840 | |
| 30841 | struct arm_long_option_table arm_long_opts[] = |
| 30842 | { |
| 30843 | {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), |
| 30844 | arm_parse_cpu, NULL}, |
| 30845 | {"march=", N_("<arch name>\t assemble for architecture <arch name>"), |
| 30846 | arm_parse_arch, NULL}, |
| 30847 | {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), |
| 30848 | arm_parse_fpu, NULL}, |
| 30849 | {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), |
| 30850 | arm_parse_float_abi, NULL}, |
| 30851 | #ifdef OBJ_ELF |
| 30852 | {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"), |
| 30853 | arm_parse_eabi, NULL}, |
| 30854 | #endif |
| 30855 | {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"), |
| 30856 | arm_parse_it_mode, NULL}, |
| 30857 | {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"), |
| 30858 | arm_ccs_mode, NULL}, |
| 30859 | {NULL, NULL, 0, NULL} |
| 30860 | }; |
| 30861 | |
| 30862 | int |
| 30863 | md_parse_option (int c, const char * arg) |
| 30864 | { |
| 30865 | struct arm_option_table *opt; |
| 30866 | const struct arm_legacy_option_table *fopt; |
| 30867 | struct arm_long_option_table *lopt; |
| 30868 | |
| 30869 | switch (c) |
| 30870 | { |
| 30871 | #ifdef OPTION_EB |
| 30872 | case OPTION_EB: |
| 30873 | target_big_endian = 1; |
| 30874 | break; |
| 30875 | #endif |
| 30876 | |
| 30877 | #ifdef OPTION_EL |
| 30878 | case OPTION_EL: |
| 30879 | target_big_endian = 0; |
| 30880 | break; |
| 30881 | #endif |
| 30882 | |
| 30883 | case OPTION_FIX_V4BX: |
| 30884 | fix_v4bx = TRUE; |
| 30885 | break; |
| 30886 | |
| 30887 | #ifdef OBJ_ELF |
| 30888 | case OPTION_FDPIC: |
| 30889 | arm_fdpic = TRUE; |
| 30890 | break; |
| 30891 | #endif /* OBJ_ELF */ |
| 30892 | |
| 30893 | case 'a': |
| 30894 | /* Listing option. Just ignore these, we don't support additional |
| 30895 | ones. */ |
| 30896 | return 0; |
| 30897 | |
| 30898 | default: |
| 30899 | for (opt = arm_opts; opt->option != NULL; opt++) |
| 30900 | { |
| 30901 | if (c == opt->option[0] |
| 30902 | && ((arg == NULL && opt->option[1] == 0) |
| 30903 | || streq (arg, opt->option + 1))) |
| 30904 | { |
| 30905 | /* If the option is deprecated, tell the user. */ |
| 30906 | if (warn_on_deprecated && opt->deprecated != NULL) |
| 30907 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
| 30908 | arg ? arg : "", _(opt->deprecated)); |
| 30909 | |
| 30910 | if (opt->var != NULL) |
| 30911 | *opt->var = opt->value; |
| 30912 | |
| 30913 | return 1; |
| 30914 | } |
| 30915 | } |
| 30916 | |
| 30917 | for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) |
| 30918 | { |
| 30919 | if (c == fopt->option[0] |
| 30920 | && ((arg == NULL && fopt->option[1] == 0) |
| 30921 | || streq (arg, fopt->option + 1))) |
| 30922 | { |
| 30923 | /* If the option is deprecated, tell the user. */ |
| 30924 | if (warn_on_deprecated && fopt->deprecated != NULL) |
| 30925 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
| 30926 | arg ? arg : "", _(fopt->deprecated)); |
| 30927 | |
| 30928 | if (fopt->var != NULL) |
| 30929 | *fopt->var = &fopt->value; |
| 30930 | |
| 30931 | return 1; |
| 30932 | } |
| 30933 | } |
| 30934 | |
| 30935 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
| 30936 | { |
| 30937 | /* These options are expected to have an argument. */ |
| 30938 | if (c == lopt->option[0] |
| 30939 | && arg != NULL |
| 30940 | && strncmp (arg, lopt->option + 1, |
| 30941 | strlen (lopt->option + 1)) == 0) |
| 30942 | { |
| 30943 | /* If the option is deprecated, tell the user. */ |
| 30944 | if (warn_on_deprecated && lopt->deprecated != NULL) |
| 30945 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, |
| 30946 | _(lopt->deprecated)); |
| 30947 | |
| 30948 | /* Call the sup-option parser. */ |
| 30949 | return lopt->func (arg + strlen (lopt->option) - 1); |
| 30950 | } |
| 30951 | } |
| 30952 | |
| 30953 | return 0; |
| 30954 | } |
| 30955 | |
| 30956 | return 1; |
| 30957 | } |
| 30958 | |
| 30959 | void |
| 30960 | md_show_usage (FILE * fp) |
| 30961 | { |
| 30962 | struct arm_option_table *opt; |
| 30963 | struct arm_long_option_table *lopt; |
| 30964 | |
| 30965 | fprintf (fp, _(" ARM-specific assembler options:\n")); |
| 30966 | |
| 30967 | for (opt = arm_opts; opt->option != NULL; opt++) |
| 30968 | if (opt->help != NULL) |
| 30969 | fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); |
| 30970 | |
| 30971 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
| 30972 | if (lopt->help != NULL) |
| 30973 | fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); |
| 30974 | |
| 30975 | #ifdef OPTION_EB |
| 30976 | fprintf (fp, _("\ |
| 30977 | -EB assemble code for a big-endian cpu\n")); |
| 30978 | #endif |
| 30979 | |
| 30980 | #ifdef OPTION_EL |
| 30981 | fprintf (fp, _("\ |
| 30982 | -EL assemble code for a little-endian cpu\n")); |
| 30983 | #endif |
| 30984 | |
| 30985 | fprintf (fp, _("\ |
| 30986 | --fix-v4bx Allow BX in ARMv4 code\n")); |
| 30987 | |
| 30988 | #ifdef OBJ_ELF |
| 30989 | fprintf (fp, _("\ |
| 30990 | --fdpic generate an FDPIC object file\n")); |
| 30991 | #endif /* OBJ_ELF */ |
| 30992 | } |
| 30993 | |
| 30994 | #ifdef OBJ_ELF |
| 30995 | |
| 30996 | typedef struct |
| 30997 | { |
| 30998 | int val; |
| 30999 | arm_feature_set flags; |
| 31000 | } cpu_arch_ver_table; |
| 31001 | |
| 31002 | /* Mapping from CPU features to EABI CPU arch values. Table must be sorted |
| 31003 | chronologically for architectures, with an exception for ARMv6-M and |
| 31004 | ARMv6S-M due to legacy reasons. No new architecture should have a |
| 31005 | special case. This allows for build attribute selection results to be |
| 31006 | stable when new architectures are added. */ |
| 31007 | static const cpu_arch_ver_table cpu_arch_ver[] = |
| 31008 | { |
| 31009 | {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V1}, |
| 31010 | {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2}, |
| 31011 | {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2S}, |
| 31012 | {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3}, |
| 31013 | {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3M}, |
| 31014 | {TAG_CPU_ARCH_V4, ARM_ARCH_V4xM}, |
| 31015 | {TAG_CPU_ARCH_V4, ARM_ARCH_V4}, |
| 31016 | {TAG_CPU_ARCH_V4T, ARM_ARCH_V4TxM}, |
| 31017 | {TAG_CPU_ARCH_V4T, ARM_ARCH_V4T}, |
| 31018 | {TAG_CPU_ARCH_V5T, ARM_ARCH_V5xM}, |
| 31019 | {TAG_CPU_ARCH_V5T, ARM_ARCH_V5}, |
| 31020 | {TAG_CPU_ARCH_V5T, ARM_ARCH_V5TxM}, |
| 31021 | {TAG_CPU_ARCH_V5T, ARM_ARCH_V5T}, |
| 31022 | {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TExP}, |
| 31023 | {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TE}, |
| 31024 | {TAG_CPU_ARCH_V5TEJ, ARM_ARCH_V5TEJ}, |
| 31025 | {TAG_CPU_ARCH_V6, ARM_ARCH_V6}, |
| 31026 | {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6Z}, |
| 31027 | {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6KZ}, |
| 31028 | {TAG_CPU_ARCH_V6K, ARM_ARCH_V6K}, |
| 31029 | {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6T2}, |
| 31030 | {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KT2}, |
| 31031 | {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6ZT2}, |
| 31032 | {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KZT2}, |
| 31033 | |
| 31034 | /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as |
| 31035 | always selected build attributes to match those of ARMv6-M |
| 31036 | (resp. ARMv6S-M). However, due to these architectures being a strict |
| 31037 | subset of ARMv7-M in terms of instructions available, ARMv7-M attributes |
| 31038 | would be selected when fully respecting chronology of architectures. |
| 31039 | It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and |
| 31040 | move them before ARMv7 architectures. */ |
| 31041 | {TAG_CPU_ARCH_V6_M, ARM_ARCH_V6M}, |
| 31042 | {TAG_CPU_ARCH_V6S_M, ARM_ARCH_V6SM}, |
| 31043 | |
| 31044 | {TAG_CPU_ARCH_V7, ARM_ARCH_V7}, |
| 31045 | {TAG_CPU_ARCH_V7, ARM_ARCH_V7A}, |
| 31046 | {TAG_CPU_ARCH_V7, ARM_ARCH_V7R}, |
| 31047 | {TAG_CPU_ARCH_V7, ARM_ARCH_V7M}, |
| 31048 | {TAG_CPU_ARCH_V7, ARM_ARCH_V7VE}, |
| 31049 | {TAG_CPU_ARCH_V7E_M, ARM_ARCH_V7EM}, |
| 31050 | {TAG_CPU_ARCH_V8, ARM_ARCH_V8A}, |
| 31051 | {TAG_CPU_ARCH_V8, ARM_ARCH_V8_1A}, |
| 31052 | {TAG_CPU_ARCH_V8, ARM_ARCH_V8_2A}, |
| 31053 | {TAG_CPU_ARCH_V8, ARM_ARCH_V8_3A}, |
| 31054 | {TAG_CPU_ARCH_V8M_BASE, ARM_ARCH_V8M_BASE}, |
| 31055 | {TAG_CPU_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN}, |
| 31056 | {TAG_CPU_ARCH_V8R, ARM_ARCH_V8R}, |
| 31057 | {TAG_CPU_ARCH_V8, ARM_ARCH_V8_4A}, |
| 31058 | {TAG_CPU_ARCH_V8, ARM_ARCH_V8_5A}, |
| 31059 | {TAG_CPU_ARCH_V8_1M_MAIN, ARM_ARCH_V8_1M_MAIN}, |
| 31060 | {-1, ARM_ARCH_NONE} |
| 31061 | }; |
| 31062 | |
| 31063 | /* Set an attribute if it has not already been set by the user. */ |
| 31064 | |
| 31065 | static void |
| 31066 | aeabi_set_attribute_int (int tag, int value) |
| 31067 | { |
| 31068 | if (tag < 1 |
| 31069 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES |
| 31070 | || !attributes_set_explicitly[tag]) |
| 31071 | bfd_elf_add_proc_attr_int (stdoutput, tag, value); |
| 31072 | } |
| 31073 | |
| 31074 | static void |
| 31075 | aeabi_set_attribute_string (int tag, const char *value) |
| 31076 | { |
| 31077 | if (tag < 1 |
| 31078 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES |
| 31079 | || !attributes_set_explicitly[tag]) |
| 31080 | bfd_elf_add_proc_attr_string (stdoutput, tag, value); |
| 31081 | } |
| 31082 | |
| 31083 | /* Return whether features in the *NEEDED feature set are available via |
| 31084 | extensions for the architecture whose feature set is *ARCH_FSET. */ |
| 31085 | |
| 31086 | static bfd_boolean |
| 31087 | have_ext_for_needed_feat_p (const arm_feature_set *arch_fset, |
| 31088 | const arm_feature_set *needed) |
| 31089 | { |
| 31090 | int i, nb_allowed_archs; |
| 31091 | arm_feature_set ext_fset; |
| 31092 | const struct arm_option_extension_value_table *opt; |
| 31093 | |
| 31094 | ext_fset = arm_arch_none; |
| 31095 | for (opt = arm_extensions; opt->name != NULL; opt++) |
| 31096 | { |
| 31097 | /* Extension does not provide any feature we need. */ |
| 31098 | if (!ARM_CPU_HAS_FEATURE (*needed, opt->merge_value)) |
| 31099 | continue; |
| 31100 | |
| 31101 | nb_allowed_archs = |
| 31102 | sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]); |
| 31103 | for (i = 0; i < nb_allowed_archs; i++) |
| 31104 | { |
| 31105 | /* Empty entry. */ |
| 31106 | if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_arch_any)) |
| 31107 | break; |
| 31108 | |
| 31109 | /* Extension is available, add it. */ |
| 31110 | if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *arch_fset)) |
| 31111 | ARM_MERGE_FEATURE_SETS (ext_fset, ext_fset, opt->merge_value); |
| 31112 | } |
| 31113 | } |
| 31114 | |
| 31115 | /* Can we enable all features in *needed? */ |
| 31116 | return ARM_FSET_CPU_SUBSET (*needed, ext_fset); |
| 31117 | } |
| 31118 | |
| 31119 | /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for |
| 31120 | a given architecture feature set *ARCH_EXT_FSET including extension feature |
| 31121 | set *EXT_FSET. Selection logic used depend on EXACT_MATCH: |
| 31122 | - if true, check for an exact match of the architecture modulo extensions; |
| 31123 | - otherwise, select build attribute value of the first superset |
| 31124 | architecture released so that results remains stable when new architectures |
| 31125 | are added. |
| 31126 | For -march/-mcpu=all the build attribute value of the most featureful |
| 31127 | architecture is returned. Tag_CPU_arch_profile result is returned in |
| 31128 | PROFILE. */ |
| 31129 | |
| 31130 | static int |
| 31131 | get_aeabi_cpu_arch_from_fset (const arm_feature_set *arch_ext_fset, |
| 31132 | const arm_feature_set *ext_fset, |
| 31133 | char *profile, int exact_match) |
| 31134 | { |
| 31135 | arm_feature_set arch_fset; |
| 31136 | const cpu_arch_ver_table *p_ver, *p_ver_ret = NULL; |
| 31137 | |
| 31138 | /* Select most featureful architecture with all its extensions if building |
| 31139 | for -march=all as the feature sets used to set build attributes. */ |
| 31140 | if (ARM_FEATURE_EQUAL (*arch_ext_fset, arm_arch_any)) |
| 31141 | { |
| 31142 | /* Force revisiting of decision for each new architecture. */ |
| 31143 | gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V8_1M_MAIN); |
| 31144 | *profile = 'A'; |
| 31145 | return TAG_CPU_ARCH_V8; |
| 31146 | } |
| 31147 | |
| 31148 | ARM_CLEAR_FEATURE (arch_fset, *arch_ext_fset, *ext_fset); |
| 31149 | |
| 31150 | for (p_ver = cpu_arch_ver; p_ver->val != -1; p_ver++) |
| 31151 | { |
| 31152 | arm_feature_set known_arch_fset; |
| 31153 | |
| 31154 | ARM_CLEAR_FEATURE (known_arch_fset, p_ver->flags, fpu_any); |
| 31155 | if (exact_match) |
| 31156 | { |
| 31157 | /* Base architecture match user-specified architecture and |
| 31158 | extensions, eg. ARMv6S-M matching -march=armv6-m+os. */ |
| 31159 | if (ARM_FEATURE_EQUAL (*arch_ext_fset, known_arch_fset)) |
| 31160 | { |
| 31161 | p_ver_ret = p_ver; |
| 31162 | goto found; |
| 31163 | } |
| 31164 | /* Base architecture match user-specified architecture only |
| 31165 | (eg. ARMv6-M in the same case as above). Record it in case we |
| 31166 | find a match with above condition. */ |
| 31167 | else if (p_ver_ret == NULL |
| 31168 | && ARM_FEATURE_EQUAL (arch_fset, known_arch_fset)) |
| 31169 | p_ver_ret = p_ver; |
| 31170 | } |
| 31171 | else |
| 31172 | { |
| 31173 | |
| 31174 | /* Architecture has all features wanted. */ |
| 31175 | if (ARM_FSET_CPU_SUBSET (arch_fset, known_arch_fset)) |
| 31176 | { |
| 31177 | arm_feature_set added_fset; |
| 31178 | |
| 31179 | /* Compute features added by this architecture over the one |
| 31180 | recorded in p_ver_ret. */ |
| 31181 | if (p_ver_ret != NULL) |
| 31182 | ARM_CLEAR_FEATURE (added_fset, known_arch_fset, |
| 31183 | p_ver_ret->flags); |
| 31184 | /* First architecture that match incl. with extensions, or the |
| 31185 | only difference in features over the recorded match is |
| 31186 | features that were optional and are now mandatory. */ |
| 31187 | if (p_ver_ret == NULL |
| 31188 | || ARM_FSET_CPU_SUBSET (added_fset, arch_fset)) |
| 31189 | { |
| 31190 | p_ver_ret = p_ver; |
| 31191 | goto found; |
| 31192 | } |
| 31193 | } |
| 31194 | else if (p_ver_ret == NULL) |
| 31195 | { |
| 31196 | arm_feature_set needed_ext_fset; |
| 31197 | |
| 31198 | ARM_CLEAR_FEATURE (needed_ext_fset, arch_fset, known_arch_fset); |
| 31199 | |
| 31200 | /* Architecture has all features needed when using some |
| 31201 | extensions. Record it and continue searching in case there |
| 31202 | exist an architecture providing all needed features without |
| 31203 | the need for extensions (eg. ARMv6S-M Vs ARMv6-M with |
| 31204 | OS extension). */ |
| 31205 | if (have_ext_for_needed_feat_p (&known_arch_fset, |
| 31206 | &needed_ext_fset)) |
| 31207 | p_ver_ret = p_ver; |
| 31208 | } |
| 31209 | } |
| 31210 | } |
| 31211 | |
| 31212 | if (p_ver_ret == NULL) |
| 31213 | return -1; |
| 31214 | |
| 31215 | found: |
| 31216 | /* Tag_CPU_arch_profile. */ |
| 31217 | if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7a) |
| 31218 | || ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8) |
| 31219 | || (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_atomics) |
| 31220 | && !ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8m_m_only))) |
| 31221 | *profile = 'A'; |
| 31222 | else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7r)) |
| 31223 | *profile = 'R'; |
| 31224 | else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_m)) |
| 31225 | *profile = 'M'; |
| 31226 | else |
| 31227 | *profile = '\0'; |
| 31228 | return p_ver_ret->val; |
| 31229 | } |
| 31230 | |
| 31231 | /* Set the public EABI object attributes. */ |
| 31232 | |
| 31233 | static void |
| 31234 | aeabi_set_public_attributes (void) |
| 31235 | { |
| 31236 | char profile = '\0'; |
| 31237 | int arch = -1; |
| 31238 | int virt_sec = 0; |
| 31239 | int fp16_optional = 0; |
| 31240 | int skip_exact_match = 0; |
| 31241 | arm_feature_set flags, flags_arch, flags_ext; |
| 31242 | |
| 31243 | /* Autodetection mode, choose the architecture based the instructions |
| 31244 | actually used. */ |
| 31245 | if (no_cpu_selected ()) |
| 31246 | { |
| 31247 | ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); |
| 31248 | |
| 31249 | if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)) |
| 31250 | ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1); |
| 31251 | |
| 31252 | if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any)) |
| 31253 | ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t); |
| 31254 | |
| 31255 | /* Code run during relaxation relies on selected_cpu being set. */ |
| 31256 | ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any); |
| 31257 | flags_ext = arm_arch_none; |
| 31258 | ARM_CLEAR_FEATURE (selected_arch, flags_arch, flags_ext); |
| 31259 | selected_ext = flags_ext; |
| 31260 | selected_cpu = flags; |
| 31261 | } |
| 31262 | /* Otherwise, choose the architecture based on the capabilities of the |
| 31263 | requested cpu. */ |
| 31264 | else |
| 31265 | { |
| 31266 | ARM_MERGE_FEATURE_SETS (flags_arch, selected_arch, selected_ext); |
| 31267 | ARM_CLEAR_FEATURE (flags_arch, flags_arch, fpu_any); |
| 31268 | flags_ext = selected_ext; |
| 31269 | flags = selected_cpu; |
| 31270 | } |
| 31271 | ARM_MERGE_FEATURE_SETS (flags, flags, selected_fpu); |
| 31272 | |
| 31273 | /* Allow the user to override the reported architecture. */ |
| 31274 | if (!ARM_FEATURE_ZERO (selected_object_arch)) |
| 31275 | { |
| 31276 | ARM_CLEAR_FEATURE (flags_arch, selected_object_arch, fpu_any); |
| 31277 | flags_ext = arm_arch_none; |
| 31278 | } |
| 31279 | else |
| 31280 | skip_exact_match = ARM_FEATURE_EQUAL (selected_cpu, arm_arch_any); |
| 31281 | |
| 31282 | /* When this function is run again after relaxation has happened there is no |
| 31283 | way to determine whether an architecture or CPU was specified by the user: |
| 31284 | - selected_cpu is set above for relaxation to work; |
| 31285 | - march_cpu_opt is not set if only -mcpu or .cpu is used; |
| 31286 | - mcpu_cpu_opt is set to arm_arch_any for autodetection. |
| 31287 | Therefore, if not in -march=all case we first try an exact match and fall |
| 31288 | back to autodetection. */ |
| 31289 | if (!skip_exact_match) |
| 31290 | arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 1); |
| 31291 | if (arch == -1) |
| 31292 | arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 0); |
| 31293 | if (arch == -1) |
| 31294 | as_bad (_("no architecture contains all the instructions used\n")); |
| 31295 | |
| 31296 | /* Tag_CPU_name. */ |
| 31297 | if (selected_cpu_name[0]) |
| 31298 | { |
| 31299 | char *q; |
| 31300 | |
| 31301 | q = selected_cpu_name; |
| 31302 | if (strncmp (q, "armv", 4) == 0) |
| 31303 | { |
| 31304 | int i; |
| 31305 | |
| 31306 | q += 4; |
| 31307 | for (i = 0; q[i]; i++) |
| 31308 | q[i] = TOUPPER (q[i]); |
| 31309 | } |
| 31310 | aeabi_set_attribute_string (Tag_CPU_name, q); |
| 31311 | } |
| 31312 | |
| 31313 | /* Tag_CPU_arch. */ |
| 31314 | aeabi_set_attribute_int (Tag_CPU_arch, arch); |
| 31315 | |
| 31316 | /* Tag_CPU_arch_profile. */ |
| 31317 | if (profile != '\0') |
| 31318 | aeabi_set_attribute_int (Tag_CPU_arch_profile, profile); |
| 31319 | |
| 31320 | /* Tag_DSP_extension. */ |
| 31321 | if (ARM_CPU_HAS_FEATURE (selected_ext, arm_ext_dsp)) |
| 31322 | aeabi_set_attribute_int (Tag_DSP_extension, 1); |
| 31323 | |
| 31324 | ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any); |
| 31325 | /* Tag_ARM_ISA_use. */ |
| 31326 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1) |
| 31327 | || ARM_FEATURE_ZERO (flags_arch)) |
| 31328 | aeabi_set_attribute_int (Tag_ARM_ISA_use, 1); |
| 31329 | |
| 31330 | /* Tag_THUMB_ISA_use. */ |
| 31331 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t) |
| 31332 | || ARM_FEATURE_ZERO (flags_arch)) |
| 31333 | { |
| 31334 | int thumb_isa_use; |
| 31335 | |
| 31336 | if (!ARM_CPU_HAS_FEATURE (flags, arm_ext_v8) |
| 31337 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m_m_only)) |
| 31338 | thumb_isa_use = 3; |
| 31339 | else if (ARM_CPU_HAS_FEATURE (flags, arm_arch_t2)) |
| 31340 | thumb_isa_use = 2; |
| 31341 | else |
| 31342 | thumb_isa_use = 1; |
| 31343 | aeabi_set_attribute_int (Tag_THUMB_ISA_use, thumb_isa_use); |
| 31344 | } |
| 31345 | |
| 31346 | /* Tag_VFP_arch. */ |
| 31347 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8xd)) |
| 31348 | aeabi_set_attribute_int (Tag_VFP_arch, |
| 31349 | ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32) |
| 31350 | ? 7 : 8); |
| 31351 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma)) |
| 31352 | aeabi_set_attribute_int (Tag_VFP_arch, |
| 31353 | ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32) |
| 31354 | ? 5 : 6); |
| 31355 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)) |
| 31356 | { |
| 31357 | fp16_optional = 1; |
| 31358 | aeabi_set_attribute_int (Tag_VFP_arch, 3); |
| 31359 | } |
| 31360 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd)) |
| 31361 | { |
| 31362 | aeabi_set_attribute_int (Tag_VFP_arch, 4); |
| 31363 | fp16_optional = 1; |
| 31364 | } |
| 31365 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2)) |
| 31366 | aeabi_set_attribute_int (Tag_VFP_arch, 2); |
| 31367 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1) |
| 31368 | || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)) |
| 31369 | aeabi_set_attribute_int (Tag_VFP_arch, 1); |
| 31370 | |
| 31371 | /* Tag_ABI_HardFP_use. */ |
| 31372 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd) |
| 31373 | && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)) |
| 31374 | aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1); |
| 31375 | |
| 31376 | /* Tag_WMMX_arch. */ |
| 31377 | if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2)) |
| 31378 | aeabi_set_attribute_int (Tag_WMMX_arch, 2); |
| 31379 | else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt)) |
| 31380 | aeabi_set_attribute_int (Tag_WMMX_arch, 1); |
| 31381 | |
| 31382 | /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */ |
| 31383 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v8_1)) |
| 31384 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 4); |
| 31385 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8)) |
| 31386 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3); |
| 31387 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1)) |
| 31388 | { |
| 31389 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma)) |
| 31390 | { |
| 31391 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2); |
| 31392 | } |
| 31393 | else |
| 31394 | { |
| 31395 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1); |
| 31396 | fp16_optional = 1; |
| 31397 | } |
| 31398 | } |
| 31399 | |
| 31400 | if (ARM_CPU_HAS_FEATURE (flags, mve_fp_ext)) |
| 31401 | aeabi_set_attribute_int (Tag_MVE_arch, 2); |
| 31402 | else if (ARM_CPU_HAS_FEATURE (flags, mve_ext)) |
| 31403 | aeabi_set_attribute_int (Tag_MVE_arch, 1); |
| 31404 | |
| 31405 | /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */ |
| 31406 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional) |
| 31407 | aeabi_set_attribute_int (Tag_VFP_HP_extension, 1); |
| 31408 | |
| 31409 | /* Tag_DIV_use. |
| 31410 | |
| 31411 | We set Tag_DIV_use to two when integer divide instructions have been used |
| 31412 | in ARM state, or when Thumb integer divide instructions have been used, |
| 31413 | but we have no architecture profile set, nor have we any ARM instructions. |
| 31414 | |
| 31415 | For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied |
| 31416 | by the base architecture. |
| 31417 | |
| 31418 | For new architectures we will have to check these tests. */ |
| 31419 | gas_assert (arch <= TAG_CPU_ARCH_V8_1M_MAIN); |
| 31420 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8) |
| 31421 | || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m)) |
| 31422 | aeabi_set_attribute_int (Tag_DIV_use, 0); |
| 31423 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv) |
| 31424 | || (profile == '\0' |
| 31425 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_div) |
| 31426 | && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))) |
| 31427 | aeabi_set_attribute_int (Tag_DIV_use, 2); |
| 31428 | |
| 31429 | /* Tag_MP_extension_use. */ |
| 31430 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp)) |
| 31431 | aeabi_set_attribute_int (Tag_MPextension_use, 1); |
| 31432 | |
| 31433 | /* Tag Virtualization_use. */ |
| 31434 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec)) |
| 31435 | virt_sec |= 1; |
| 31436 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt)) |
| 31437 | virt_sec |= 2; |
| 31438 | if (virt_sec != 0) |
| 31439 | aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec); |
| 31440 | } |
| 31441 | |
| 31442 | /* Post relaxation hook. Recompute ARM attributes now that relaxation is |
| 31443 | finished and free extension feature bits which will not be used anymore. */ |
| 31444 | |
| 31445 | void |
| 31446 | arm_md_post_relax (void) |
| 31447 | { |
| 31448 | aeabi_set_public_attributes (); |
| 31449 | XDELETE (mcpu_ext_opt); |
| 31450 | mcpu_ext_opt = NULL; |
| 31451 | XDELETE (march_ext_opt); |
| 31452 | march_ext_opt = NULL; |
| 31453 | } |
| 31454 | |
| 31455 | /* Add the default contents for the .ARM.attributes section. */ |
| 31456 | |
| 31457 | void |
| 31458 | arm_md_end (void) |
| 31459 | { |
| 31460 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
| 31461 | return; |
| 31462 | |
| 31463 | aeabi_set_public_attributes (); |
| 31464 | } |
| 31465 | #endif /* OBJ_ELF */ |
| 31466 | |
| 31467 | /* Parse a .cpu directive. */ |
| 31468 | |
| 31469 | static void |
| 31470 | s_arm_cpu (int ignored ATTRIBUTE_UNUSED) |
| 31471 | { |
| 31472 | const struct arm_cpu_option_table *opt; |
| 31473 | char *name; |
| 31474 | char saved_char; |
| 31475 | |
| 31476 | name = input_line_pointer; |
| 31477 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
| 31478 | input_line_pointer++; |
| 31479 | saved_char = *input_line_pointer; |
| 31480 | *input_line_pointer = 0; |
| 31481 | |
| 31482 | /* Skip the first "all" entry. */ |
| 31483 | for (opt = arm_cpus + 1; opt->name != NULL; opt++) |
| 31484 | if (streq (opt->name, name)) |
| 31485 | { |
| 31486 | selected_arch = opt->value; |
| 31487 | selected_ext = opt->ext; |
| 31488 | ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext); |
| 31489 | if (opt->canonical_name) |
| 31490 | strcpy (selected_cpu_name, opt->canonical_name); |
| 31491 | else |
| 31492 | { |
| 31493 | int i; |
| 31494 | for (i = 0; opt->name[i]; i++) |
| 31495 | selected_cpu_name[i] = TOUPPER (opt->name[i]); |
| 31496 | |
| 31497 | selected_cpu_name[i] = 0; |
| 31498 | } |
| 31499 | ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu); |
| 31500 | |
| 31501 | *input_line_pointer = saved_char; |
| 31502 | demand_empty_rest_of_line (); |
| 31503 | return; |
| 31504 | } |
| 31505 | as_bad (_("unknown cpu `%s'"), name); |
| 31506 | *input_line_pointer = saved_char; |
| 31507 | ignore_rest_of_line (); |
| 31508 | } |
| 31509 | |
| 31510 | /* Parse a .arch directive. */ |
| 31511 | |
| 31512 | static void |
| 31513 | s_arm_arch (int ignored ATTRIBUTE_UNUSED) |
| 31514 | { |
| 31515 | const struct arm_arch_option_table *opt; |
| 31516 | char saved_char; |
| 31517 | char *name; |
| 31518 | |
| 31519 | name = input_line_pointer; |
| 31520 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
| 31521 | input_line_pointer++; |
| 31522 | saved_char = *input_line_pointer; |
| 31523 | *input_line_pointer = 0; |
| 31524 | |
| 31525 | /* Skip the first "all" entry. */ |
| 31526 | for (opt = arm_archs + 1; opt->name != NULL; opt++) |
| 31527 | if (streq (opt->name, name)) |
| 31528 | { |
| 31529 | selected_arch = opt->value; |
| 31530 | selected_ext = arm_arch_none; |
| 31531 | selected_cpu = selected_arch; |
| 31532 | strcpy (selected_cpu_name, opt->name); |
| 31533 | ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu); |
| 31534 | *input_line_pointer = saved_char; |
| 31535 | demand_empty_rest_of_line (); |
| 31536 | return; |
| 31537 | } |
| 31538 | |
| 31539 | as_bad (_("unknown architecture `%s'\n"), name); |
| 31540 | *input_line_pointer = saved_char; |
| 31541 | ignore_rest_of_line (); |
| 31542 | } |
| 31543 | |
| 31544 | /* Parse a .object_arch directive. */ |
| 31545 | |
| 31546 | static void |
| 31547 | s_arm_object_arch (int ignored ATTRIBUTE_UNUSED) |
| 31548 | { |
| 31549 | const struct arm_arch_option_table *opt; |
| 31550 | char saved_char; |
| 31551 | char *name; |
| 31552 | |
| 31553 | name = input_line_pointer; |
| 31554 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
| 31555 | input_line_pointer++; |
| 31556 | saved_char = *input_line_pointer; |
| 31557 | *input_line_pointer = 0; |
| 31558 | |
| 31559 | /* Skip the first "all" entry. */ |
| 31560 | for (opt = arm_archs + 1; opt->name != NULL; opt++) |
| 31561 | if (streq (opt->name, name)) |
| 31562 | { |
| 31563 | selected_object_arch = opt->value; |
| 31564 | *input_line_pointer = saved_char; |
| 31565 | demand_empty_rest_of_line (); |
| 31566 | return; |
| 31567 | } |
| 31568 | |
| 31569 | as_bad (_("unknown architecture `%s'\n"), name); |
| 31570 | *input_line_pointer = saved_char; |
| 31571 | ignore_rest_of_line (); |
| 31572 | } |
| 31573 | |
| 31574 | /* Parse a .arch_extension directive. */ |
| 31575 | |
| 31576 | static void |
| 31577 | s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED) |
| 31578 | { |
| 31579 | const struct arm_option_extension_value_table *opt; |
| 31580 | char saved_char; |
| 31581 | char *name; |
| 31582 | int adding_value = 1; |
| 31583 | |
| 31584 | name = input_line_pointer; |
| 31585 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
| 31586 | input_line_pointer++; |
| 31587 | saved_char = *input_line_pointer; |
| 31588 | *input_line_pointer = 0; |
| 31589 | |
| 31590 | if (strlen (name) >= 2 |
| 31591 | && strncmp (name, "no", 2) == 0) |
| 31592 | { |
| 31593 | adding_value = 0; |
| 31594 | name += 2; |
| 31595 | } |
| 31596 | |
| 31597 | for (opt = arm_extensions; opt->name != NULL; opt++) |
| 31598 | if (streq (opt->name, name)) |
| 31599 | { |
| 31600 | int i, nb_allowed_archs = |
| 31601 | sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[i]); |
| 31602 | for (i = 0; i < nb_allowed_archs; i++) |
| 31603 | { |
| 31604 | /* Empty entry. */ |
| 31605 | if (ARM_CPU_IS_ANY (opt->allowed_archs[i])) |
| 31606 | continue; |
| 31607 | if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], selected_arch)) |
| 31608 | break; |
| 31609 | } |
| 31610 | |
| 31611 | if (i == nb_allowed_archs) |
| 31612 | { |
| 31613 | as_bad (_("architectural extension `%s' is not allowed for the " |
| 31614 | "current base architecture"), name); |
| 31615 | break; |
| 31616 | } |
| 31617 | |
| 31618 | if (adding_value) |
| 31619 | ARM_MERGE_FEATURE_SETS (selected_ext, selected_ext, |
| 31620 | opt->merge_value); |
| 31621 | else |
| 31622 | ARM_CLEAR_FEATURE (selected_ext, selected_ext, opt->clear_value); |
| 31623 | |
| 31624 | ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext); |
| 31625 | ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu); |
| 31626 | *input_line_pointer = saved_char; |
| 31627 | demand_empty_rest_of_line (); |
| 31628 | /* Allowing Thumb division instructions for ARMv7 in autodetection rely |
| 31629 | on this return so that duplicate extensions (extensions with the |
| 31630 | same name as a previous extension in the list) are not considered |
| 31631 | for command-line parsing. */ |
| 31632 | return; |
| 31633 | } |
| 31634 | |
| 31635 | if (opt->name == NULL) |
| 31636 | as_bad (_("unknown architecture extension `%s'\n"), name); |
| 31637 | |
| 31638 | *input_line_pointer = saved_char; |
| 31639 | ignore_rest_of_line (); |
| 31640 | } |
| 31641 | |
| 31642 | /* Parse a .fpu directive. */ |
| 31643 | |
| 31644 | static void |
| 31645 | s_arm_fpu (int ignored ATTRIBUTE_UNUSED) |
| 31646 | { |
| 31647 | const struct arm_option_fpu_value_table *opt; |
| 31648 | char saved_char; |
| 31649 | char *name; |
| 31650 | |
| 31651 | name = input_line_pointer; |
| 31652 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
| 31653 | input_line_pointer++; |
| 31654 | saved_char = *input_line_pointer; |
| 31655 | *input_line_pointer = 0; |
| 31656 | |
| 31657 | for (opt = arm_fpus; opt->name != NULL; opt++) |
| 31658 | if (streq (opt->name, name)) |
| 31659 | { |
| 31660 | selected_fpu = opt->value; |
| 31661 | #ifndef CPU_DEFAULT |
| 31662 | if (no_cpu_selected ()) |
| 31663 | ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu); |
| 31664 | else |
| 31665 | #endif |
| 31666 | ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu); |
| 31667 | *input_line_pointer = saved_char; |
| 31668 | demand_empty_rest_of_line (); |
| 31669 | return; |
| 31670 | } |
| 31671 | |
| 31672 | as_bad (_("unknown floating point format `%s'\n"), name); |
| 31673 | *input_line_pointer = saved_char; |
| 31674 | ignore_rest_of_line (); |
| 31675 | } |
| 31676 | |
| 31677 | /* Copy symbol information. */ |
| 31678 | |
| 31679 | void |
| 31680 | arm_copy_symbol_attributes (symbolS *dest, symbolS *src) |
| 31681 | { |
| 31682 | ARM_GET_FLAG (dest) = ARM_GET_FLAG (src); |
| 31683 | } |
| 31684 | |
| 31685 | #ifdef OBJ_ELF |
| 31686 | /* Given a symbolic attribute NAME, return the proper integer value. |
| 31687 | Returns -1 if the attribute is not known. */ |
| 31688 | |
| 31689 | int |
| 31690 | arm_convert_symbolic_attribute (const char *name) |
| 31691 | { |
| 31692 | static const struct |
| 31693 | { |
| 31694 | const char * name; |
| 31695 | const int tag; |
| 31696 | } |
| 31697 | attribute_table[] = |
| 31698 | { |
| 31699 | /* When you modify this table you should |
| 31700 | also modify the list in doc/c-arm.texi. */ |
| 31701 | #define T(tag) {#tag, tag} |
| 31702 | T (Tag_CPU_raw_name), |
| 31703 | T (Tag_CPU_name), |
| 31704 | T (Tag_CPU_arch), |
| 31705 | T (Tag_CPU_arch_profile), |
| 31706 | T (Tag_ARM_ISA_use), |
| 31707 | T (Tag_THUMB_ISA_use), |
| 31708 | T (Tag_FP_arch), |
| 31709 | T (Tag_VFP_arch), |
| 31710 | T (Tag_WMMX_arch), |
| 31711 | T (Tag_Advanced_SIMD_arch), |
| 31712 | T (Tag_PCS_config), |
| 31713 | T (Tag_ABI_PCS_R9_use), |
| 31714 | T (Tag_ABI_PCS_RW_data), |
| 31715 | T (Tag_ABI_PCS_RO_data), |
| 31716 | T (Tag_ABI_PCS_GOT_use), |
| 31717 | T (Tag_ABI_PCS_wchar_t), |
| 31718 | T (Tag_ABI_FP_rounding), |
| 31719 | T (Tag_ABI_FP_denormal), |
| 31720 | T (Tag_ABI_FP_exceptions), |
| 31721 | T (Tag_ABI_FP_user_exceptions), |
| 31722 | T (Tag_ABI_FP_number_model), |
| 31723 | T (Tag_ABI_align_needed), |
| 31724 | T (Tag_ABI_align8_needed), |
| 31725 | T (Tag_ABI_align_preserved), |
| 31726 | T (Tag_ABI_align8_preserved), |
| 31727 | T (Tag_ABI_enum_size), |
| 31728 | T (Tag_ABI_HardFP_use), |
| 31729 | T (Tag_ABI_VFP_args), |
| 31730 | T (Tag_ABI_WMMX_args), |
| 31731 | T (Tag_ABI_optimization_goals), |
| 31732 | T (Tag_ABI_FP_optimization_goals), |
| 31733 | T (Tag_compatibility), |
| 31734 | T (Tag_CPU_unaligned_access), |
| 31735 | T (Tag_FP_HP_extension), |
| 31736 | T (Tag_VFP_HP_extension), |
| 31737 | T (Tag_ABI_FP_16bit_format), |
| 31738 | T (Tag_MPextension_use), |
| 31739 | T (Tag_DIV_use), |
| 31740 | T (Tag_nodefaults), |
| 31741 | T (Tag_also_compatible_with), |
| 31742 | T (Tag_conformance), |
| 31743 | T (Tag_T2EE_use), |
| 31744 | T (Tag_Virtualization_use), |
| 31745 | T (Tag_DSP_extension), |
| 31746 | T (Tag_MVE_arch), |
| 31747 | /* We deliberately do not include Tag_MPextension_use_legacy. */ |
| 31748 | #undef T |
| 31749 | }; |
| 31750 | unsigned int i; |
| 31751 | |
| 31752 | if (name == NULL) |
| 31753 | return -1; |
| 31754 | |
| 31755 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) |
| 31756 | if (streq (name, attribute_table[i].name)) |
| 31757 | return attribute_table[i].tag; |
| 31758 | |
| 31759 | return -1; |
| 31760 | } |
| 31761 | |
| 31762 | /* Apply sym value for relocations only in the case that they are for |
| 31763 | local symbols in the same segment as the fixup and you have the |
| 31764 | respective architectural feature for blx and simple switches. */ |
| 31765 | |
| 31766 | int |
| 31767 | arm_apply_sym_value (struct fix * fixP, segT this_seg) |
| 31768 | { |
| 31769 | if (fixP->fx_addsy |
| 31770 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
| 31771 | /* PR 17444: If the local symbol is in a different section then a reloc |
| 31772 | will always be generated for it, so applying the symbol value now |
| 31773 | will result in a double offset being stored in the relocation. */ |
| 31774 | && (S_GET_SEGMENT (fixP->fx_addsy) == this_seg) |
| 31775 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
| 31776 | { |
| 31777 | switch (fixP->fx_r_type) |
| 31778 | { |
| 31779 | case BFD_RELOC_ARM_PCREL_BLX: |
| 31780 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
| 31781 | if (ARM_IS_FUNC (fixP->fx_addsy)) |
| 31782 | return 1; |
| 31783 | break; |
| 31784 | |
| 31785 | case BFD_RELOC_ARM_PCREL_CALL: |
| 31786 | case BFD_RELOC_THUMB_PCREL_BLX: |
| 31787 | if (THUMB_IS_FUNC (fixP->fx_addsy)) |
| 31788 | return 1; |
| 31789 | break; |
| 31790 | |
| 31791 | default: |
| 31792 | break; |
| 31793 | } |
| 31794 | |
| 31795 | } |
| 31796 | return 0; |
| 31797 | } |
| 31798 | #endif /* OBJ_ELF */ |