| 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
| 2 | Copyright (C) 1989-2020 Free Software Foundation, Inc. |
| 3 | |
| 4 | This file is part of GAS, the GNU Assembler. |
| 5 | |
| 6 | GAS is free software; you can redistribute it and/or modify |
| 7 | it under the terms of the GNU General Public License as published by |
| 8 | the Free Software Foundation; either version 3, or (at your option) |
| 9 | any later version. |
| 10 | |
| 11 | GAS is distributed in the hope that it will be useful, |
| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | GNU General Public License for more details. |
| 15 | |
| 16 | You should have received a copy of the GNU General Public License |
| 17 | along with GAS; see the file COPYING. If not, write to the Free |
| 18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
| 19 | 02110-1301, USA. */ |
| 20 | |
| 21 | /* Intel 80386 machine specific gas. |
| 22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). |
| 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
| 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
| 25 | Bugs & suggestions are completely welcome. This is free software. |
| 26 | Please help us make it better. */ |
| 27 | |
| 28 | #include "as.h" |
| 29 | #include "safe-ctype.h" |
| 30 | #include "subsegs.h" |
| 31 | #include "dwarf2dbg.h" |
| 32 | #include "dw2gencfi.h" |
| 33 | #include "elf/x86-64.h" |
| 34 | #include "opcodes/i386-init.h" |
| 35 | |
| 36 | #ifdef HAVE_LIMITS_H |
| 37 | #include <limits.h> |
| 38 | #else |
| 39 | #ifdef HAVE_SYS_PARAM_H |
| 40 | #include <sys/param.h> |
| 41 | #endif |
| 42 | #ifndef INT_MAX |
| 43 | #define INT_MAX (int) (((unsigned) (-1)) >> 1) |
| 44 | #endif |
| 45 | #endif |
| 46 | |
| 47 | #ifndef INFER_ADDR_PREFIX |
| 48 | #define INFER_ADDR_PREFIX 1 |
| 49 | #endif |
| 50 | |
| 51 | #ifndef DEFAULT_ARCH |
| 52 | #define DEFAULT_ARCH "i386" |
| 53 | #endif |
| 54 | |
| 55 | #ifndef INLINE |
| 56 | #if __GNUC__ >= 2 |
| 57 | #define INLINE __inline__ |
| 58 | #else |
| 59 | #define INLINE |
| 60 | #endif |
| 61 | #endif |
| 62 | |
| 63 | /* Prefixes will be emitted in the order defined below. |
| 64 | WAIT_PREFIX must be the first prefix since FWAIT is really is an |
| 65 | instruction, and so must come before any prefixes. |
| 66 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, |
| 67 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
| 68 | #define WAIT_PREFIX 0 |
| 69 | #define SEG_PREFIX 1 |
| 70 | #define ADDR_PREFIX 2 |
| 71 | #define DATA_PREFIX 3 |
| 72 | #define REP_PREFIX 4 |
| 73 | #define HLE_PREFIX REP_PREFIX |
| 74 | #define BND_PREFIX REP_PREFIX |
| 75 | #define LOCK_PREFIX 5 |
| 76 | #define REX_PREFIX 6 /* must come last. */ |
| 77 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ |
| 78 | |
| 79 | /* we define the syntax here (modulo base,index,scale syntax) */ |
| 80 | #define REGISTER_PREFIX '%' |
| 81 | #define IMMEDIATE_PREFIX '$' |
| 82 | #define ABSOLUTE_PREFIX '*' |
| 83 | |
| 84 | /* these are the instruction mnemonic suffixes in AT&T syntax or |
| 85 | memory operand size in Intel syntax. */ |
| 86 | #define WORD_MNEM_SUFFIX 'w' |
| 87 | #define BYTE_MNEM_SUFFIX 'b' |
| 88 | #define SHORT_MNEM_SUFFIX 's' |
| 89 | #define LONG_MNEM_SUFFIX 'l' |
| 90 | #define QWORD_MNEM_SUFFIX 'q' |
| 91 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
| 92 | in instructions. */ |
| 93 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' |
| 94 | |
| 95 | #define END_OF_INSN '\0' |
| 96 | |
| 97 | /* This matches the C -> StaticRounding alias in the opcode table. */ |
| 98 | #define commutative staticrounding |
| 99 | |
| 100 | /* |
| 101 | 'templates' is for grouping together 'template' structures for opcodes |
| 102 | of the same name. This is only used for storing the insns in the grand |
| 103 | ole hash table of insns. |
| 104 | The templates themselves start at START and range up to (but not including) |
| 105 | END. |
| 106 | */ |
| 107 | typedef struct |
| 108 | { |
| 109 | const insn_template *start; |
| 110 | const insn_template *end; |
| 111 | } |
| 112 | templates; |
| 113 | |
| 114 | /* 386 operand encoding bytes: see 386 book for details of this. */ |
| 115 | typedef struct |
| 116 | { |
| 117 | unsigned int regmem; /* codes register or memory operand */ |
| 118 | unsigned int reg; /* codes register operand (or extended opcode) */ |
| 119 | unsigned int mode; /* how to interpret regmem & reg */ |
| 120 | } |
| 121 | modrm_byte; |
| 122 | |
| 123 | /* x86-64 extension prefix. */ |
| 124 | typedef int rex_byte; |
| 125 | |
| 126 | /* 386 opcode byte to code indirect addressing. */ |
| 127 | typedef struct |
| 128 | { |
| 129 | unsigned base; |
| 130 | unsigned index; |
| 131 | unsigned scale; |
| 132 | } |
| 133 | sib_byte; |
| 134 | |
| 135 | /* x86 arch names, types and features */ |
| 136 | typedef struct |
| 137 | { |
| 138 | const char *name; /* arch name */ |
| 139 | unsigned int len; /* arch string length */ |
| 140 | enum processor_type type; /* arch type */ |
| 141 | i386_cpu_flags flags; /* cpu feature flags */ |
| 142 | unsigned int skip; /* show_arch should skip this. */ |
| 143 | } |
| 144 | arch_entry; |
| 145 | |
| 146 | /* Used to turn off indicated flags. */ |
| 147 | typedef struct |
| 148 | { |
| 149 | const char *name; /* arch name */ |
| 150 | unsigned int len; /* arch string length */ |
| 151 | i386_cpu_flags flags; /* cpu feature flags */ |
| 152 | } |
| 153 | noarch_entry; |
| 154 | |
| 155 | static void update_code_flag (int, int); |
| 156 | static void set_code_flag (int); |
| 157 | static void set_16bit_gcc_code_flag (int); |
| 158 | static void set_intel_syntax (int); |
| 159 | static void set_intel_mnemonic (int); |
| 160 | static void set_allow_index_reg (int); |
| 161 | static void set_check (int); |
| 162 | static void set_cpu_arch (int); |
| 163 | #ifdef TE_PE |
| 164 | static void pe_directive_secrel (int); |
| 165 | #endif |
| 166 | static void signed_cons (int); |
| 167 | static char *output_invalid (int c); |
| 168 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
| 169 | const char *); |
| 170 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, |
| 171 | const char *); |
| 172 | static int i386_att_operand (char *); |
| 173 | static int i386_intel_operand (char *, int); |
| 174 | static int i386_intel_simplify (expressionS *); |
| 175 | static int i386_intel_parse_name (const char *, expressionS *); |
| 176 | static const reg_entry *parse_register (char *, char **); |
| 177 | static char *parse_insn (char *, char *); |
| 178 | static char *parse_operands (char *, const char *); |
| 179 | static void swap_operands (void); |
| 180 | static void swap_2_operands (int, int); |
| 181 | static enum flag_code i386_addressing_mode (void); |
| 182 | static void optimize_imm (void); |
| 183 | static void optimize_disp (void); |
| 184 | static const insn_template *match_template (char); |
| 185 | static int check_string (void); |
| 186 | static int process_suffix (void); |
| 187 | static int check_byte_reg (void); |
| 188 | static int check_long_reg (void); |
| 189 | static int check_qword_reg (void); |
| 190 | static int check_word_reg (void); |
| 191 | static int finalize_imm (void); |
| 192 | static int process_operands (void); |
| 193 | static const seg_entry *build_modrm_byte (void); |
| 194 | static void output_insn (void); |
| 195 | static void output_imm (fragS *, offsetT); |
| 196 | static void output_disp (fragS *, offsetT); |
| 197 | #ifndef I386COFF |
| 198 | static void s_bss (int); |
| 199 | #endif |
| 200 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 201 | static void handle_large_common (int small ATTRIBUTE_UNUSED); |
| 202 | |
| 203 | /* GNU_PROPERTY_X86_ISA_1_USED. */ |
| 204 | static unsigned int x86_isa_1_used; |
| 205 | /* GNU_PROPERTY_X86_FEATURE_2_USED. */ |
| 206 | static unsigned int x86_feature_2_used; |
| 207 | /* Generate x86 used ISA and feature properties. */ |
| 208 | static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE; |
| 209 | #endif |
| 210 | |
| 211 | static const char *default_arch = DEFAULT_ARCH; |
| 212 | |
| 213 | /* This struct describes rounding control and SAE in the instruction. */ |
| 214 | struct RC_Operation |
| 215 | { |
| 216 | enum rc_type |
| 217 | { |
| 218 | rne = 0, |
| 219 | rd, |
| 220 | ru, |
| 221 | rz, |
| 222 | saeonly |
| 223 | } type; |
| 224 | int operand; |
| 225 | }; |
| 226 | |
| 227 | static struct RC_Operation rc_op; |
| 228 | |
| 229 | /* The struct describes masking, applied to OPERAND in the instruction. |
| 230 | MASK is a pointer to the corresponding mask register. ZEROING tells |
| 231 | whether merging or zeroing mask is used. */ |
| 232 | struct Mask_Operation |
| 233 | { |
| 234 | const reg_entry *mask; |
| 235 | unsigned int zeroing; |
| 236 | /* The operand where this operation is associated. */ |
| 237 | int operand; |
| 238 | }; |
| 239 | |
| 240 | static struct Mask_Operation mask_op; |
| 241 | |
| 242 | /* The struct describes broadcasting, applied to OPERAND. FACTOR is |
| 243 | broadcast factor. */ |
| 244 | struct Broadcast_Operation |
| 245 | { |
| 246 | /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */ |
| 247 | int type; |
| 248 | |
| 249 | /* Index of broadcasted operand. */ |
| 250 | int operand; |
| 251 | |
| 252 | /* Number of bytes to broadcast. */ |
| 253 | int bytes; |
| 254 | }; |
| 255 | |
| 256 | static struct Broadcast_Operation broadcast_op; |
| 257 | |
| 258 | /* VEX prefix. */ |
| 259 | typedef struct |
| 260 | { |
| 261 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
| 262 | unsigned char bytes[4]; |
| 263 | unsigned int length; |
| 264 | /* Destination or source register specifier. */ |
| 265 | const reg_entry *register_specifier; |
| 266 | } vex_prefix; |
| 267 | |
| 268 | /* 'md_assemble ()' gathers together information and puts it into a |
| 269 | i386_insn. */ |
| 270 | |
| 271 | union i386_op |
| 272 | { |
| 273 | expressionS *disps; |
| 274 | expressionS *imms; |
| 275 | const reg_entry *regs; |
| 276 | }; |
| 277 | |
| 278 | enum i386_error |
| 279 | { |
| 280 | operand_size_mismatch, |
| 281 | operand_type_mismatch, |
| 282 | register_type_mismatch, |
| 283 | number_of_operands_mismatch, |
| 284 | invalid_instruction_suffix, |
| 285 | bad_imm4, |
| 286 | unsupported_with_intel_mnemonic, |
| 287 | unsupported_syntax, |
| 288 | unsupported, |
| 289 | invalid_vsib_address, |
| 290 | invalid_vector_register_set, |
| 291 | unsupported_vector_index_register, |
| 292 | unsupported_broadcast, |
| 293 | broadcast_needed, |
| 294 | unsupported_masking, |
| 295 | mask_not_on_destination, |
| 296 | no_default_mask, |
| 297 | unsupported_rc_sae, |
| 298 | rc_sae_operand_not_last_imm, |
| 299 | invalid_register_operand, |
| 300 | }; |
| 301 | |
| 302 | struct _i386_insn |
| 303 | { |
| 304 | /* TM holds the template for the insn were currently assembling. */ |
| 305 | insn_template tm; |
| 306 | |
| 307 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
| 308 | or qword, if given. */ |
| 309 | char suffix; |
| 310 | |
| 311 | /* OPERANDS gives the number of given operands. */ |
| 312 | unsigned int operands; |
| 313 | |
| 314 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number |
| 315 | of given register, displacement, memory operands and immediate |
| 316 | operands. */ |
| 317 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
| 318 | |
| 319 | /* TYPES [i] is the type (see above #defines) which tells us how to |
| 320 | use OP[i] for the corresponding operand. */ |
| 321 | i386_operand_type types[MAX_OPERANDS]; |
| 322 | |
| 323 | /* Displacement expression, immediate expression, or register for each |
| 324 | operand. */ |
| 325 | union i386_op op[MAX_OPERANDS]; |
| 326 | |
| 327 | /* Flags for operands. */ |
| 328 | unsigned int flags[MAX_OPERANDS]; |
| 329 | #define Operand_PCrel 1 |
| 330 | #define Operand_Mem 2 |
| 331 | |
| 332 | /* Relocation type for operand */ |
| 333 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
| 334 | |
| 335 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
| 336 | the base index byte below. */ |
| 337 | const reg_entry *base_reg; |
| 338 | const reg_entry *index_reg; |
| 339 | unsigned int log2_scale_factor; |
| 340 | |
| 341 | /* SEG gives the seg_entries of this insn. They are zero unless |
| 342 | explicit segment overrides are given. */ |
| 343 | const seg_entry *seg[2]; |
| 344 | |
| 345 | /* Copied first memory operand string, for re-checking. */ |
| 346 | char *memop1_string; |
| 347 | |
| 348 | /* PREFIX holds all the given prefix opcodes (usually null). |
| 349 | PREFIXES is the number of prefix opcodes. */ |
| 350 | unsigned int prefixes; |
| 351 | unsigned char prefix[MAX_PREFIXES]; |
| 352 | |
| 353 | /* Register is in low 3 bits of opcode. */ |
| 354 | bfd_boolean short_form; |
| 355 | |
| 356 | /* The operand to a branch insn indicates an absolute branch. */ |
| 357 | bfd_boolean jumpabsolute; |
| 358 | |
| 359 | /* Has MMX register operands. */ |
| 360 | bfd_boolean has_regmmx; |
| 361 | |
| 362 | /* Has XMM register operands. */ |
| 363 | bfd_boolean has_regxmm; |
| 364 | |
| 365 | /* Has YMM register operands. */ |
| 366 | bfd_boolean has_regymm; |
| 367 | |
| 368 | /* Has ZMM register operands. */ |
| 369 | bfd_boolean has_regzmm; |
| 370 | |
| 371 | /* Has GOTPC or TLS relocation. */ |
| 372 | bfd_boolean has_gotpc_tls_reloc; |
| 373 | |
| 374 | /* RM and SIB are the modrm byte and the sib byte where the |
| 375 | addressing modes of this insn are encoded. */ |
| 376 | modrm_byte rm; |
| 377 | rex_byte rex; |
| 378 | rex_byte vrex; |
| 379 | sib_byte sib; |
| 380 | vex_prefix vex; |
| 381 | |
| 382 | /* Masking attributes. */ |
| 383 | struct Mask_Operation *mask; |
| 384 | |
| 385 | /* Rounding control and SAE attributes. */ |
| 386 | struct RC_Operation *rounding; |
| 387 | |
| 388 | /* Broadcasting attributes. */ |
| 389 | struct Broadcast_Operation *broadcast; |
| 390 | |
| 391 | /* Compressed disp8*N attribute. */ |
| 392 | unsigned int memshift; |
| 393 | |
| 394 | /* Prefer load or store in encoding. */ |
| 395 | enum |
| 396 | { |
| 397 | dir_encoding_default = 0, |
| 398 | dir_encoding_load, |
| 399 | dir_encoding_store, |
| 400 | dir_encoding_swap |
| 401 | } dir_encoding; |
| 402 | |
| 403 | /* Prefer 8bit or 32bit displacement in encoding. */ |
| 404 | enum |
| 405 | { |
| 406 | disp_encoding_default = 0, |
| 407 | disp_encoding_8bit, |
| 408 | disp_encoding_32bit |
| 409 | } disp_encoding; |
| 410 | |
| 411 | /* Prefer the REX byte in encoding. */ |
| 412 | bfd_boolean rex_encoding; |
| 413 | |
| 414 | /* Disable instruction size optimization. */ |
| 415 | bfd_boolean no_optimize; |
| 416 | |
| 417 | /* How to encode vector instructions. */ |
| 418 | enum |
| 419 | { |
| 420 | vex_encoding_default = 0, |
| 421 | vex_encoding_vex, |
| 422 | vex_encoding_vex3, |
| 423 | vex_encoding_evex |
| 424 | } vec_encoding; |
| 425 | |
| 426 | /* REP prefix. */ |
| 427 | const char *rep_prefix; |
| 428 | |
| 429 | /* HLE prefix. */ |
| 430 | const char *hle_prefix; |
| 431 | |
| 432 | /* Have BND prefix. */ |
| 433 | const char *bnd_prefix; |
| 434 | |
| 435 | /* Have NOTRACK prefix. */ |
| 436 | const char *notrack_prefix; |
| 437 | |
| 438 | /* Error message. */ |
| 439 | enum i386_error error; |
| 440 | }; |
| 441 | |
| 442 | typedef struct _i386_insn i386_insn; |
| 443 | |
| 444 | /* Link RC type with corresponding string, that'll be looked for in |
| 445 | asm. */ |
| 446 | struct RC_name |
| 447 | { |
| 448 | enum rc_type type; |
| 449 | const char *name; |
| 450 | unsigned int len; |
| 451 | }; |
| 452 | |
| 453 | static const struct RC_name RC_NamesTable[] = |
| 454 | { |
| 455 | { rne, STRING_COMMA_LEN ("rn-sae") }, |
| 456 | { rd, STRING_COMMA_LEN ("rd-sae") }, |
| 457 | { ru, STRING_COMMA_LEN ("ru-sae") }, |
| 458 | { rz, STRING_COMMA_LEN ("rz-sae") }, |
| 459 | { saeonly, STRING_COMMA_LEN ("sae") }, |
| 460 | }; |
| 461 | |
| 462 | /* List of chars besides those in app.c:symbol_chars that can start an |
| 463 | operand. Used to prevent the scrubber eating vital white-space. */ |
| 464 | const char extra_symbol_chars[] = "*%-([{}" |
| 465 | #ifdef LEX_AT |
| 466 | "@" |
| 467 | #endif |
| 468 | #ifdef LEX_QM |
| 469 | "?" |
| 470 | #endif |
| 471 | ; |
| 472 | |
| 473 | #if (defined (TE_I386AIX) \ |
| 474 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ |
| 475 | && !defined (TE_GNU) \ |
| 476 | && !defined (TE_LINUX) \ |
| 477 | && !defined (TE_NACL) \ |
| 478 | && !defined (TE_FreeBSD) \ |
| 479 | && !defined (TE_DragonFly) \ |
| 480 | && !defined (TE_NetBSD))) |
| 481 | /* This array holds the chars that always start a comment. If the |
| 482 | pre-processor is disabled, these aren't very useful. The option |
| 483 | --divide will remove '/' from this list. */ |
| 484 | const char *i386_comment_chars = "#/"; |
| 485 | #define SVR4_COMMENT_CHARS 1 |
| 486 | #define PREFIX_SEPARATOR '\\' |
| 487 | |
| 488 | #else |
| 489 | const char *i386_comment_chars = "#"; |
| 490 | #define PREFIX_SEPARATOR '/' |
| 491 | #endif |
| 492 | |
| 493 | /* This array holds the chars that only start a comment at the beginning of |
| 494 | a line. If the line seems to have the form '# 123 filename' |
| 495 | .line and .file directives will appear in the pre-processed output. |
| 496 | Note that input_file.c hand checks for '#' at the beginning of the |
| 497 | first line of the input file. This is because the compiler outputs |
| 498 | #NO_APP at the beginning of its output. |
| 499 | Also note that comments started like this one will always work if |
| 500 | '/' isn't otherwise defined. */ |
| 501 | const char line_comment_chars[] = "#/"; |
| 502 | |
| 503 | const char line_separator_chars[] = ";"; |
| 504 | |
| 505 | /* Chars that can be used to separate mant from exp in floating point |
| 506 | nums. */ |
| 507 | const char EXP_CHARS[] = "eE"; |
| 508 | |
| 509 | /* Chars that mean this number is a floating point constant |
| 510 | As in 0f12.456 |
| 511 | or 0d1.2345e12. */ |
| 512 | const char FLT_CHARS[] = "fFdDxX"; |
| 513 | |
| 514 | /* Tables for lexical analysis. */ |
| 515 | static char mnemonic_chars[256]; |
| 516 | static char register_chars[256]; |
| 517 | static char operand_chars[256]; |
| 518 | static char identifier_chars[256]; |
| 519 | static char digit_chars[256]; |
| 520 | |
| 521 | /* Lexical macros. */ |
| 522 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
| 523 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) |
| 524 | #define is_register_char(x) (register_chars[(unsigned char) x]) |
| 525 | #define is_space_char(x) ((x) == ' ') |
| 526 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) |
| 527 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) |
| 528 | |
| 529 | /* All non-digit non-letter characters that may occur in an operand. */ |
| 530 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
| 531 | |
| 532 | /* md_assemble() always leaves the strings it's passed unaltered. To |
| 533 | effect this we maintain a stack of saved characters that we've smashed |
| 534 | with '\0's (indicating end of strings for various sub-fields of the |
| 535 | assembler instruction). */ |
| 536 | static char save_stack[32]; |
| 537 | static char *save_stack_p; |
| 538 | #define END_STRING_AND_SAVE(s) \ |
| 539 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) |
| 540 | #define RESTORE_END_STRING(s) \ |
| 541 | do { *(s) = *--save_stack_p; } while (0) |
| 542 | |
| 543 | /* The instruction we're assembling. */ |
| 544 | static i386_insn i; |
| 545 | |
| 546 | /* Possible templates for current insn. */ |
| 547 | static const templates *current_templates; |
| 548 | |
| 549 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
| 550 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; |
| 551 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; |
| 552 | |
| 553 | /* Current operand we are working on. */ |
| 554 | static int this_operand = -1; |
| 555 | |
| 556 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
| 557 | these. */ |
| 558 | |
| 559 | enum flag_code { |
| 560 | CODE_32BIT, |
| 561 | CODE_16BIT, |
| 562 | CODE_64BIT }; |
| 563 | |
| 564 | static enum flag_code flag_code; |
| 565 | static unsigned int object_64bit; |
| 566 | static unsigned int disallow_64bit_reloc; |
| 567 | static int use_rela_relocations = 0; |
| 568 | /* __tls_get_addr/___tls_get_addr symbol for TLS. */ |
| 569 | static const char *tls_get_addr; |
| 570 | |
| 571 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
| 572 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
| 573 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
| 574 | |
| 575 | /* The ELF ABI to use. */ |
| 576 | enum x86_elf_abi |
| 577 | { |
| 578 | I386_ABI, |
| 579 | X86_64_ABI, |
| 580 | X86_64_X32_ABI |
| 581 | }; |
| 582 | |
| 583 | static enum x86_elf_abi x86_elf_abi = I386_ABI; |
| 584 | #endif |
| 585 | |
| 586 | #if defined (TE_PE) || defined (TE_PEP) |
| 587 | /* Use big object file format. */ |
| 588 | static int use_big_obj = 0; |
| 589 | #endif |
| 590 | |
| 591 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 592 | /* 1 if generating code for a shared library. */ |
| 593 | static int shared = 0; |
| 594 | #endif |
| 595 | |
| 596 | /* 1 for intel syntax, |
| 597 | 0 if att syntax. */ |
| 598 | static int intel_syntax = 0; |
| 599 | |
| 600 | static enum x86_64_isa |
| 601 | { |
| 602 | amd64 = 1, /* AMD64 ISA. */ |
| 603 | intel64 /* Intel64 ISA. */ |
| 604 | } isa64; |
| 605 | |
| 606 | /* 1 for intel mnemonic, |
| 607 | 0 if att mnemonic. */ |
| 608 | static int intel_mnemonic = !SYSV386_COMPAT; |
| 609 | |
| 610 | /* 1 if pseudo registers are permitted. */ |
| 611 | static int allow_pseudo_reg = 0; |
| 612 | |
| 613 | /* 1 if register prefix % not required. */ |
| 614 | static int allow_naked_reg = 0; |
| 615 | |
| 616 | /* 1 if the assembler should add BND prefix for all control-transferring |
| 617 | instructions supporting it, even if this prefix wasn't specified |
| 618 | explicitly. */ |
| 619 | static int add_bnd_prefix = 0; |
| 620 | |
| 621 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
| 622 | static int allow_index_reg = 0; |
| 623 | |
| 624 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
| 625 | specified explicitly. */ |
| 626 | static int omit_lock_prefix = 0; |
| 627 | |
| 628 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
| 629 | "lock addl $0, (%{re}sp)". */ |
| 630 | static int avoid_fence = 0; |
| 631 | |
| 632 | /* 1 if lfence should be inserted after every load. */ |
| 633 | static int lfence_after_load = 0; |
| 634 | |
| 635 | /* Non-zero if lfence should be inserted before indirect branch. */ |
| 636 | static enum lfence_before_indirect_branch_kind |
| 637 | { |
| 638 | lfence_branch_none = 0, |
| 639 | lfence_branch_register, |
| 640 | lfence_branch_memory, |
| 641 | lfence_branch_all |
| 642 | } |
| 643 | lfence_before_indirect_branch; |
| 644 | |
| 645 | /* Non-zero if lfence should be inserted before ret. */ |
| 646 | static enum lfence_before_ret_kind |
| 647 | { |
| 648 | lfence_before_ret_none = 0, |
| 649 | lfence_before_ret_not, |
| 650 | lfence_before_ret_or, |
| 651 | lfence_before_ret_shl |
| 652 | } |
| 653 | lfence_before_ret; |
| 654 | |
| 655 | /* Types of previous instruction is .byte or prefix. */ |
| 656 | static struct |
| 657 | { |
| 658 | segT seg; |
| 659 | const char *file; |
| 660 | const char *name; |
| 661 | unsigned int line; |
| 662 | enum last_insn_kind |
| 663 | { |
| 664 | last_insn_other = 0, |
| 665 | last_insn_directive, |
| 666 | last_insn_prefix |
| 667 | } kind; |
| 668 | } last_insn; |
| 669 | |
| 670 | /* 1 if the assembler should generate relax relocations. */ |
| 671 | |
| 672 | static int generate_relax_relocations |
| 673 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; |
| 674 | |
| 675 | static enum check_kind |
| 676 | { |
| 677 | check_none = 0, |
| 678 | check_warning, |
| 679 | check_error |
| 680 | } |
| 681 | sse_check, operand_check = check_warning; |
| 682 | |
| 683 | /* Non-zero if branches should be aligned within power of 2 boundary. */ |
| 684 | static int align_branch_power = 0; |
| 685 | |
| 686 | /* Types of branches to align. */ |
| 687 | enum align_branch_kind |
| 688 | { |
| 689 | align_branch_none = 0, |
| 690 | align_branch_jcc = 1, |
| 691 | align_branch_fused = 2, |
| 692 | align_branch_jmp = 3, |
| 693 | align_branch_call = 4, |
| 694 | align_branch_indirect = 5, |
| 695 | align_branch_ret = 6 |
| 696 | }; |
| 697 | |
| 698 | /* Type bits of branches to align. */ |
| 699 | enum align_branch_bit |
| 700 | { |
| 701 | align_branch_jcc_bit = 1 << align_branch_jcc, |
| 702 | align_branch_fused_bit = 1 << align_branch_fused, |
| 703 | align_branch_jmp_bit = 1 << align_branch_jmp, |
| 704 | align_branch_call_bit = 1 << align_branch_call, |
| 705 | align_branch_indirect_bit = 1 << align_branch_indirect, |
| 706 | align_branch_ret_bit = 1 << align_branch_ret |
| 707 | }; |
| 708 | |
| 709 | static unsigned int align_branch = (align_branch_jcc_bit |
| 710 | | align_branch_fused_bit |
| 711 | | align_branch_jmp_bit); |
| 712 | |
| 713 | /* Types of condition jump used by macro-fusion. */ |
| 714 | enum mf_jcc_kind |
| 715 | { |
| 716 | mf_jcc_jo = 0, /* base opcode 0x70 */ |
| 717 | mf_jcc_jc, /* base opcode 0x72 */ |
| 718 | mf_jcc_je, /* base opcode 0x74 */ |
| 719 | mf_jcc_jna, /* base opcode 0x76 */ |
| 720 | mf_jcc_js, /* base opcode 0x78 */ |
| 721 | mf_jcc_jp, /* base opcode 0x7a */ |
| 722 | mf_jcc_jl, /* base opcode 0x7c */ |
| 723 | mf_jcc_jle, /* base opcode 0x7e */ |
| 724 | }; |
| 725 | |
| 726 | /* Types of compare flag-modifying insntructions used by macro-fusion. */ |
| 727 | enum mf_cmp_kind |
| 728 | { |
| 729 | mf_cmp_test_and, /* test/cmp */ |
| 730 | mf_cmp_alu_cmp, /* add/sub/cmp */ |
| 731 | mf_cmp_incdec /* inc/dec */ |
| 732 | }; |
| 733 | |
| 734 | /* The maximum padding size for fused jcc. CMP like instruction can |
| 735 | be 9 bytes and jcc can be 6 bytes. Leave room just in case for |
| 736 | prefixes. */ |
| 737 | #define MAX_FUSED_JCC_PADDING_SIZE 20 |
| 738 | |
| 739 | /* The maximum number of prefixes added for an instruction. */ |
| 740 | static unsigned int align_branch_prefix_size = 5; |
| 741 | |
| 742 | /* Optimization: |
| 743 | 1. Clear the REX_W bit with register operand if possible. |
| 744 | 2. Above plus use 128bit vector instruction to clear the full vector |
| 745 | register. |
| 746 | */ |
| 747 | static int optimize = 0; |
| 748 | |
| 749 | /* Optimization: |
| 750 | 1. Clear the REX_W bit with register operand if possible. |
| 751 | 2. Above plus use 128bit vector instruction to clear the full vector |
| 752 | register. |
| 753 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to |
| 754 | "testb $imm7,%r8". |
| 755 | */ |
| 756 | static int optimize_for_space = 0; |
| 757 | |
| 758 | /* Register prefix used for error message. */ |
| 759 | static const char *register_prefix = "%"; |
| 760 | |
| 761 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
| 762 | leave, push, and pop instructions so that gcc has the same stack |
| 763 | frame as in 32 bit mode. */ |
| 764 | static char stackop_size = '\0'; |
| 765 | |
| 766 | /* Non-zero to optimize code alignment. */ |
| 767 | int optimize_align_code = 1; |
| 768 | |
| 769 | /* Non-zero to quieten some warnings. */ |
| 770 | static int quiet_warnings = 0; |
| 771 | |
| 772 | /* CPU name. */ |
| 773 | static const char *cpu_arch_name = NULL; |
| 774 | static char *cpu_sub_arch_name = NULL; |
| 775 | |
| 776 | /* CPU feature flags. */ |
| 777 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
| 778 | |
| 779 | /* If we have selected a cpu we are generating instructions for. */ |
| 780 | static int cpu_arch_tune_set = 0; |
| 781 | |
| 782 | /* Cpu we are generating instructions for. */ |
| 783 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
| 784 | |
| 785 | /* CPU feature flags of cpu we are generating instructions for. */ |
| 786 | static i386_cpu_flags cpu_arch_tune_flags; |
| 787 | |
| 788 | /* CPU instruction set architecture used. */ |
| 789 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
| 790 | |
| 791 | /* CPU feature flags of instruction set architecture used. */ |
| 792 | i386_cpu_flags cpu_arch_isa_flags; |
| 793 | |
| 794 | /* If set, conditional jumps are not automatically promoted to handle |
| 795 | larger than a byte offset. */ |
| 796 | static unsigned int no_cond_jump_promotion = 0; |
| 797 | |
| 798 | /* Encode SSE instructions with VEX prefix. */ |
| 799 | static unsigned int sse2avx; |
| 800 | |
| 801 | /* Encode scalar AVX instructions with specific vector length. */ |
| 802 | static enum |
| 803 | { |
| 804 | vex128 = 0, |
| 805 | vex256 |
| 806 | } avxscalar; |
| 807 | |
| 808 | /* Encode VEX WIG instructions with specific vex.w. */ |
| 809 | static enum |
| 810 | { |
| 811 | vexw0 = 0, |
| 812 | vexw1 |
| 813 | } vexwig; |
| 814 | |
| 815 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
| 816 | static enum |
| 817 | { |
| 818 | evexl128 = 0, |
| 819 | evexl256, |
| 820 | evexl512 |
| 821 | } evexlig; |
| 822 | |
| 823 | /* Encode EVEX WIG instructions with specific evex.w. */ |
| 824 | static enum |
| 825 | { |
| 826 | evexw0 = 0, |
| 827 | evexw1 |
| 828 | } evexwig; |
| 829 | |
| 830 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
| 831 | static enum rc_type evexrcig = rne; |
| 832 | |
| 833 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
| 834 | static symbolS *GOT_symbol; |
| 835 | |
| 836 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
| 837 | unsigned int x86_dwarf2_return_column; |
| 838 | |
| 839 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ |
| 840 | int x86_cie_data_alignment; |
| 841 | |
| 842 | /* Interface to relax_segment. |
| 843 | There are 3 major relax states for 386 jump insns because the |
| 844 | different types of jumps add different sizes to frags when we're |
| 845 | figuring out what sort of jump to choose to reach a given label. |
| 846 | |
| 847 | BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align |
| 848 | branches which are handled by md_estimate_size_before_relax() and |
| 849 | i386_generic_table_relax_frag(). */ |
| 850 | |
| 851 | /* Types. */ |
| 852 | #define UNCOND_JUMP 0 |
| 853 | #define COND_JUMP 1 |
| 854 | #define COND_JUMP86 2 |
| 855 | #define BRANCH_PADDING 3 |
| 856 | #define BRANCH_PREFIX 4 |
| 857 | #define FUSED_JCC_PADDING 5 |
| 858 | |
| 859 | /* Sizes. */ |
| 860 | #define CODE16 1 |
| 861 | #define SMALL 0 |
| 862 | #define SMALL16 (SMALL | CODE16) |
| 863 | #define BIG 2 |
| 864 | #define BIG16 (BIG | CODE16) |
| 865 | |
| 866 | #ifndef INLINE |
| 867 | #ifdef __GNUC__ |
| 868 | #define INLINE __inline__ |
| 869 | #else |
| 870 | #define INLINE |
| 871 | #endif |
| 872 | #endif |
| 873 | |
| 874 | #define ENCODE_RELAX_STATE(type, size) \ |
| 875 | ((relax_substateT) (((type) << 2) | (size))) |
| 876 | #define TYPE_FROM_RELAX_STATE(s) \ |
| 877 | ((s) >> 2) |
| 878 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ |
| 879 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) |
| 880 | |
| 881 | /* This table is used by relax_frag to promote short jumps to long |
| 882 | ones where necessary. SMALL (short) jumps may be promoted to BIG |
| 883 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We |
| 884 | don't allow a short jump in a 32 bit code segment to be promoted to |
| 885 | a 16 bit offset jump because it's slower (requires data size |
| 886 | prefix), and doesn't work, unless the destination is in the bottom |
| 887 | 64k of the code segment (The top 16 bits of eip are zeroed). */ |
| 888 | |
| 889 | const relax_typeS md_relax_table[] = |
| 890 | { |
| 891 | /* The fields are: |
| 892 | 1) most positive reach of this state, |
| 893 | 2) most negative reach of this state, |
| 894 | 3) how many bytes this mode will have in the variable part of the frag |
| 895 | 4) which index into the table to try if we can't fit into this one. */ |
| 896 | |
| 897 | /* UNCOND_JUMP states. */ |
| 898 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
| 899 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, |
| 900 | /* dword jmp adds 4 bytes to frag: |
| 901 | 0 extra opcode bytes, 4 displacement bytes. */ |
| 902 | {0, 0, 4, 0}, |
| 903 | /* word jmp adds 2 byte2 to frag: |
| 904 | 0 extra opcode bytes, 2 displacement bytes. */ |
| 905 | {0, 0, 2, 0}, |
| 906 | |
| 907 | /* COND_JUMP states. */ |
| 908 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, |
| 909 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, |
| 910 | /* dword conditionals adds 5 bytes to frag: |
| 911 | 1 extra opcode byte, 4 displacement bytes. */ |
| 912 | {0, 0, 5, 0}, |
| 913 | /* word conditionals add 3 bytes to frag: |
| 914 | 1 extra opcode byte, 2 displacement bytes. */ |
| 915 | {0, 0, 3, 0}, |
| 916 | |
| 917 | /* COND_JUMP86 states. */ |
| 918 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, |
| 919 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, |
| 920 | /* dword conditionals adds 5 bytes to frag: |
| 921 | 1 extra opcode byte, 4 displacement bytes. */ |
| 922 | {0, 0, 5, 0}, |
| 923 | /* word conditionals add 4 bytes to frag: |
| 924 | 1 displacement byte and a 3 byte long branch insn. */ |
| 925 | {0, 0, 4, 0} |
| 926 | }; |
| 927 | |
| 928 | static const arch_entry cpu_arch[] = |
| 929 | { |
| 930 | /* Do not replace the first two entries - i386_target_format() |
| 931 | relies on them being there in this order. */ |
| 932 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
| 933 | CPU_GENERIC32_FLAGS, 0 }, |
| 934 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
| 935 | CPU_GENERIC64_FLAGS, 0 }, |
| 936 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
| 937 | CPU_NONE_FLAGS, 0 }, |
| 938 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
| 939 | CPU_I186_FLAGS, 0 }, |
| 940 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
| 941 | CPU_I286_FLAGS, 0 }, |
| 942 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
| 943 | CPU_I386_FLAGS, 0 }, |
| 944 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
| 945 | CPU_I486_FLAGS, 0 }, |
| 946 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
| 947 | CPU_I586_FLAGS, 0 }, |
| 948 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
| 949 | CPU_I686_FLAGS, 0 }, |
| 950 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
| 951 | CPU_I586_FLAGS, 0 }, |
| 952 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
| 953 | CPU_PENTIUMPRO_FLAGS, 0 }, |
| 954 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
| 955 | CPU_P2_FLAGS, 0 }, |
| 956 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
| 957 | CPU_P3_FLAGS, 0 }, |
| 958 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
| 959 | CPU_P4_FLAGS, 0 }, |
| 960 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
| 961 | CPU_CORE_FLAGS, 0 }, |
| 962 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
| 963 | CPU_NOCONA_FLAGS, 0 }, |
| 964 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
| 965 | CPU_CORE_FLAGS, 1 }, |
| 966 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
| 967 | CPU_CORE_FLAGS, 0 }, |
| 968 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
| 969 | CPU_CORE2_FLAGS, 1 }, |
| 970 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
| 971 | CPU_CORE2_FLAGS, 0 }, |
| 972 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
| 973 | CPU_COREI7_FLAGS, 0 }, |
| 974 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
| 975 | CPU_L1OM_FLAGS, 0 }, |
| 976 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
| 977 | CPU_K1OM_FLAGS, 0 }, |
| 978 | { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, |
| 979 | CPU_IAMCU_FLAGS, 0 }, |
| 980 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
| 981 | CPU_K6_FLAGS, 0 }, |
| 982 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
| 983 | CPU_K6_2_FLAGS, 0 }, |
| 984 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
| 985 | CPU_ATHLON_FLAGS, 0 }, |
| 986 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
| 987 | CPU_K8_FLAGS, 1 }, |
| 988 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
| 989 | CPU_K8_FLAGS, 0 }, |
| 990 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
| 991 | CPU_K8_FLAGS, 0 }, |
| 992 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
| 993 | CPU_AMDFAM10_FLAGS, 0 }, |
| 994 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
| 995 | CPU_BDVER1_FLAGS, 0 }, |
| 996 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
| 997 | CPU_BDVER2_FLAGS, 0 }, |
| 998 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
| 999 | CPU_BDVER3_FLAGS, 0 }, |
| 1000 | { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, |
| 1001 | CPU_BDVER4_FLAGS, 0 }, |
| 1002 | { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, |
| 1003 | CPU_ZNVER1_FLAGS, 0 }, |
| 1004 | { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER, |
| 1005 | CPU_ZNVER2_FLAGS, 0 }, |
| 1006 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
| 1007 | CPU_BTVER1_FLAGS, 0 }, |
| 1008 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, |
| 1009 | CPU_BTVER2_FLAGS, 0 }, |
| 1010 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
| 1011 | CPU_8087_FLAGS, 0 }, |
| 1012 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
| 1013 | CPU_287_FLAGS, 0 }, |
| 1014 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
| 1015 | CPU_387_FLAGS, 0 }, |
| 1016 | { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, |
| 1017 | CPU_687_FLAGS, 0 }, |
| 1018 | { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN, |
| 1019 | CPU_CMOV_FLAGS, 0 }, |
| 1020 | { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN, |
| 1021 | CPU_FXSR_FLAGS, 0 }, |
| 1022 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
| 1023 | CPU_MMX_FLAGS, 0 }, |
| 1024 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
| 1025 | CPU_SSE_FLAGS, 0 }, |
| 1026 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
| 1027 | CPU_SSE2_FLAGS, 0 }, |
| 1028 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
| 1029 | CPU_SSE3_FLAGS, 0 }, |
| 1030 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
| 1031 | CPU_SSE4A_FLAGS, 0 }, |
| 1032 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
| 1033 | CPU_SSSE3_FLAGS, 0 }, |
| 1034 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
| 1035 | CPU_SSE4_1_FLAGS, 0 }, |
| 1036 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
| 1037 | CPU_SSE4_2_FLAGS, 0 }, |
| 1038 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
| 1039 | CPU_SSE4_2_FLAGS, 0 }, |
| 1040 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
| 1041 | CPU_AVX_FLAGS, 0 }, |
| 1042 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
| 1043 | CPU_AVX2_FLAGS, 0 }, |
| 1044 | { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, |
| 1045 | CPU_AVX512F_FLAGS, 0 }, |
| 1046 | { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, |
| 1047 | CPU_AVX512CD_FLAGS, 0 }, |
| 1048 | { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, |
| 1049 | CPU_AVX512ER_FLAGS, 0 }, |
| 1050 | { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, |
| 1051 | CPU_AVX512PF_FLAGS, 0 }, |
| 1052 | { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, |
| 1053 | CPU_AVX512DQ_FLAGS, 0 }, |
| 1054 | { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, |
| 1055 | CPU_AVX512BW_FLAGS, 0 }, |
| 1056 | { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, |
| 1057 | CPU_AVX512VL_FLAGS, 0 }, |
| 1058 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
| 1059 | CPU_VMX_FLAGS, 0 }, |
| 1060 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
| 1061 | CPU_VMFUNC_FLAGS, 0 }, |
| 1062 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
| 1063 | CPU_SMX_FLAGS, 0 }, |
| 1064 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
| 1065 | CPU_XSAVE_FLAGS, 0 }, |
| 1066 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
| 1067 | CPU_XSAVEOPT_FLAGS, 0 }, |
| 1068 | { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, |
| 1069 | CPU_XSAVEC_FLAGS, 0 }, |
| 1070 | { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, |
| 1071 | CPU_XSAVES_FLAGS, 0 }, |
| 1072 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
| 1073 | CPU_AES_FLAGS, 0 }, |
| 1074 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
| 1075 | CPU_PCLMUL_FLAGS, 0 }, |
| 1076 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
| 1077 | CPU_PCLMUL_FLAGS, 1 }, |
| 1078 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
| 1079 | CPU_FSGSBASE_FLAGS, 0 }, |
| 1080 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
| 1081 | CPU_RDRND_FLAGS, 0 }, |
| 1082 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
| 1083 | CPU_F16C_FLAGS, 0 }, |
| 1084 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
| 1085 | CPU_BMI2_FLAGS, 0 }, |
| 1086 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
| 1087 | CPU_FMA_FLAGS, 0 }, |
| 1088 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
| 1089 | CPU_FMA4_FLAGS, 0 }, |
| 1090 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
| 1091 | CPU_XOP_FLAGS, 0 }, |
| 1092 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
| 1093 | CPU_LWP_FLAGS, 0 }, |
| 1094 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
| 1095 | CPU_MOVBE_FLAGS, 0 }, |
| 1096 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
| 1097 | CPU_CX16_FLAGS, 0 }, |
| 1098 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
| 1099 | CPU_EPT_FLAGS, 0 }, |
| 1100 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
| 1101 | CPU_LZCNT_FLAGS, 0 }, |
| 1102 | { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN, |
| 1103 | CPU_POPCNT_FLAGS, 0 }, |
| 1104 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
| 1105 | CPU_HLE_FLAGS, 0 }, |
| 1106 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, |
| 1107 | CPU_RTM_FLAGS, 0 }, |
| 1108 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
| 1109 | CPU_INVPCID_FLAGS, 0 }, |
| 1110 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
| 1111 | CPU_CLFLUSH_FLAGS, 0 }, |
| 1112 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
| 1113 | CPU_NOP_FLAGS, 0 }, |
| 1114 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
| 1115 | CPU_SYSCALL_FLAGS, 0 }, |
| 1116 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
| 1117 | CPU_RDTSCP_FLAGS, 0 }, |
| 1118 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
| 1119 | CPU_3DNOW_FLAGS, 0 }, |
| 1120 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
| 1121 | CPU_3DNOWA_FLAGS, 0 }, |
| 1122 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
| 1123 | CPU_PADLOCK_FLAGS, 0 }, |
| 1124 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
| 1125 | CPU_SVME_FLAGS, 1 }, |
| 1126 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
| 1127 | CPU_SVME_FLAGS, 0 }, |
| 1128 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
| 1129 | CPU_SSE4A_FLAGS, 0 }, |
| 1130 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
| 1131 | CPU_ABM_FLAGS, 0 }, |
| 1132 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
| 1133 | CPU_BMI_FLAGS, 0 }, |
| 1134 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
| 1135 | CPU_TBM_FLAGS, 0 }, |
| 1136 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
| 1137 | CPU_ADX_FLAGS, 0 }, |
| 1138 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, |
| 1139 | CPU_RDSEED_FLAGS, 0 }, |
| 1140 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, |
| 1141 | CPU_PRFCHW_FLAGS, 0 }, |
| 1142 | { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, |
| 1143 | CPU_SMAP_FLAGS, 0 }, |
| 1144 | { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, |
| 1145 | CPU_MPX_FLAGS, 0 }, |
| 1146 | { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, |
| 1147 | CPU_SHA_FLAGS, 0 }, |
| 1148 | { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, |
| 1149 | CPU_CLFLUSHOPT_FLAGS, 0 }, |
| 1150 | { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, |
| 1151 | CPU_PREFETCHWT1_FLAGS, 0 }, |
| 1152 | { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, |
| 1153 | CPU_SE1_FLAGS, 0 }, |
| 1154 | { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, |
| 1155 | CPU_CLWB_FLAGS, 0 }, |
| 1156 | { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, |
| 1157 | CPU_AVX512IFMA_FLAGS, 0 }, |
| 1158 | { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, |
| 1159 | CPU_AVX512VBMI_FLAGS, 0 }, |
| 1160 | { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, |
| 1161 | CPU_AVX512_4FMAPS_FLAGS, 0 }, |
| 1162 | { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, |
| 1163 | CPU_AVX512_4VNNIW_FLAGS, 0 }, |
| 1164 | { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, |
| 1165 | CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, |
| 1166 | { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN, |
| 1167 | CPU_AVX512_VBMI2_FLAGS, 0 }, |
| 1168 | { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN, |
| 1169 | CPU_AVX512_VNNI_FLAGS, 0 }, |
| 1170 | { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN, |
| 1171 | CPU_AVX512_BITALG_FLAGS, 0 }, |
| 1172 | { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, |
| 1173 | CPU_CLZERO_FLAGS, 0 }, |
| 1174 | { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, |
| 1175 | CPU_MWAITX_FLAGS, 0 }, |
| 1176 | { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, |
| 1177 | CPU_OSPKE_FLAGS, 0 }, |
| 1178 | { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, |
| 1179 | CPU_RDPID_FLAGS, 0 }, |
| 1180 | { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, |
| 1181 | CPU_PTWRITE_FLAGS, 0 }, |
| 1182 | { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN, |
| 1183 | CPU_IBT_FLAGS, 0 }, |
| 1184 | { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN, |
| 1185 | CPU_SHSTK_FLAGS, 0 }, |
| 1186 | { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN, |
| 1187 | CPU_GFNI_FLAGS, 0 }, |
| 1188 | { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN, |
| 1189 | CPU_VAES_FLAGS, 0 }, |
| 1190 | { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN, |
| 1191 | CPU_VPCLMULQDQ_FLAGS, 0 }, |
| 1192 | { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN, |
| 1193 | CPU_WBNOINVD_FLAGS, 0 }, |
| 1194 | { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN, |
| 1195 | CPU_PCONFIG_FLAGS, 0 }, |
| 1196 | { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN, |
| 1197 | CPU_WAITPKG_FLAGS, 0 }, |
| 1198 | { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN, |
| 1199 | CPU_CLDEMOTE_FLAGS, 0 }, |
| 1200 | { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN, |
| 1201 | CPU_MOVDIRI_FLAGS, 0 }, |
| 1202 | { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN, |
| 1203 | CPU_MOVDIR64B_FLAGS, 0 }, |
| 1204 | { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN, |
| 1205 | CPU_AVX512_BF16_FLAGS, 0 }, |
| 1206 | { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN, |
| 1207 | CPU_AVX512_VP2INTERSECT_FLAGS, 0 }, |
| 1208 | { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN, |
| 1209 | CPU_ENQCMD_FLAGS, 0 }, |
| 1210 | { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN, |
| 1211 | CPU_SERIALIZE_FLAGS, 0 }, |
| 1212 | { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN, |
| 1213 | CPU_RDPRU_FLAGS, 0 }, |
| 1214 | { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN, |
| 1215 | CPU_MCOMMIT_FLAGS, 0 }, |
| 1216 | { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN, |
| 1217 | CPU_SEV_ES_FLAGS, 0 }, |
| 1218 | { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN, |
| 1219 | CPU_TSXLDTRK_FLAGS, 0 }, |
| 1220 | }; |
| 1221 | |
| 1222 | static const noarch_entry cpu_noarch[] = |
| 1223 | { |
| 1224 | { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, |
| 1225 | { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, |
| 1226 | { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, |
| 1227 | { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, |
| 1228 | { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS }, |
| 1229 | { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS }, |
| 1230 | { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, |
| 1231 | { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, |
| 1232 | { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, |
| 1233 | { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, |
| 1234 | { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS }, |
| 1235 | { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, |
| 1236 | { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, |
| 1237 | { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, |
| 1238 | { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, |
| 1239 | { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, |
| 1240 | { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, |
| 1241 | { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, |
| 1242 | { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, |
| 1243 | { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, |
| 1244 | { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, |
| 1245 | { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, |
| 1246 | { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, |
| 1247 | { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, |
| 1248 | { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, |
| 1249 | { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, |
| 1250 | { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, |
| 1251 | { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, |
| 1252 | { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, |
| 1253 | { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS }, |
| 1254 | { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS }, |
| 1255 | { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS }, |
| 1256 | { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS }, |
| 1257 | { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS }, |
| 1258 | { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS }, |
| 1259 | { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS }, |
| 1260 | { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS }, |
| 1261 | { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS }, |
| 1262 | { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS }, |
| 1263 | { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS }, |
| 1264 | { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS }, |
| 1265 | }; |
| 1266 | |
| 1267 | #ifdef I386COFF |
| 1268 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
| 1269 | is allowed to be optional. */ |
| 1270 | |
| 1271 | static symbolS * |
| 1272 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) |
| 1273 | { |
| 1274 | addressT align = 0; |
| 1275 | |
| 1276 | SKIP_WHITESPACE (); |
| 1277 | |
| 1278 | if (needs_align |
| 1279 | && *input_line_pointer == ',') |
| 1280 | { |
| 1281 | align = parse_align (needs_align - 1); |
| 1282 | |
| 1283 | if (align == (addressT) -1) |
| 1284 | return NULL; |
| 1285 | } |
| 1286 | else |
| 1287 | { |
| 1288 | if (size >= 8) |
| 1289 | align = 3; |
| 1290 | else if (size >= 4) |
| 1291 | align = 2; |
| 1292 | else if (size >= 2) |
| 1293 | align = 1; |
| 1294 | else |
| 1295 | align = 0; |
| 1296 | } |
| 1297 | |
| 1298 | bss_alloc (symbolP, size, align); |
| 1299 | return symbolP; |
| 1300 | } |
| 1301 | |
| 1302 | static void |
| 1303 | pe_lcomm (int needs_align) |
| 1304 | { |
| 1305 | s_comm_internal (needs_align * 2, pe_lcomm_internal); |
| 1306 | } |
| 1307 | #endif |
| 1308 | |
| 1309 | const pseudo_typeS md_pseudo_table[] = |
| 1310 | { |
| 1311 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) |
| 1312 | {"align", s_align_bytes, 0}, |
| 1313 | #else |
| 1314 | {"align", s_align_ptwo, 0}, |
| 1315 | #endif |
| 1316 | {"arch", set_cpu_arch, 0}, |
| 1317 | #ifndef I386COFF |
| 1318 | {"bss", s_bss, 0}, |
| 1319 | #else |
| 1320 | {"lcomm", pe_lcomm, 1}, |
| 1321 | #endif |
| 1322 | {"ffloat", float_cons, 'f'}, |
| 1323 | {"dfloat", float_cons, 'd'}, |
| 1324 | {"tfloat", float_cons, 'x'}, |
| 1325 | {"value", cons, 2}, |
| 1326 | {"slong", signed_cons, 4}, |
| 1327 | {"noopt", s_ignore, 0}, |
| 1328 | {"optim", s_ignore, 0}, |
| 1329 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, |
| 1330 | {"code16", set_code_flag, CODE_16BIT}, |
| 1331 | {"code32", set_code_flag, CODE_32BIT}, |
| 1332 | #ifdef BFD64 |
| 1333 | {"code64", set_code_flag, CODE_64BIT}, |
| 1334 | #endif |
| 1335 | {"intel_syntax", set_intel_syntax, 1}, |
| 1336 | {"att_syntax", set_intel_syntax, 0}, |
| 1337 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
| 1338 | {"att_mnemonic", set_intel_mnemonic, 0}, |
| 1339 | {"allow_index_reg", set_allow_index_reg, 1}, |
| 1340 | {"disallow_index_reg", set_allow_index_reg, 0}, |
| 1341 | {"sse_check", set_check, 0}, |
| 1342 | {"operand_check", set_check, 1}, |
| 1343 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 1344 | {"largecomm", handle_large_common, 0}, |
| 1345 | #else |
| 1346 | {"file", dwarf2_directive_file, 0}, |
| 1347 | {"loc", dwarf2_directive_loc, 0}, |
| 1348 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, |
| 1349 | #endif |
| 1350 | #ifdef TE_PE |
| 1351 | {"secrel32", pe_directive_secrel, 0}, |
| 1352 | #endif |
| 1353 | {0, 0, 0} |
| 1354 | }; |
| 1355 | |
| 1356 | /* For interface with expression (). */ |
| 1357 | extern char *input_line_pointer; |
| 1358 | |
| 1359 | /* Hash table for instruction mnemonic lookup. */ |
| 1360 | static struct hash_control *op_hash; |
| 1361 | |
| 1362 | /* Hash table for register lookup. */ |
| 1363 | static struct hash_control *reg_hash; |
| 1364 | \f |
| 1365 | /* Various efficient no-op patterns for aligning code labels. |
| 1366 | Note: Don't try to assemble the instructions in the comments. |
| 1367 | 0L and 0w are not legal. */ |
| 1368 | static const unsigned char f32_1[] = |
| 1369 | {0x90}; /* nop */ |
| 1370 | static const unsigned char f32_2[] = |
| 1371 | {0x66,0x90}; /* xchg %ax,%ax */ |
| 1372 | static const unsigned char f32_3[] = |
| 1373 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ |
| 1374 | static const unsigned char f32_4[] = |
| 1375 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ |
| 1376 | static const unsigned char f32_6[] = |
| 1377 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ |
| 1378 | static const unsigned char f32_7[] = |
| 1379 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ |
| 1380 | static const unsigned char f16_3[] = |
| 1381 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
| 1382 | static const unsigned char f16_4[] = |
| 1383 | {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */ |
| 1384 | static const unsigned char jump_disp8[] = |
| 1385 | {0xeb}; /* jmp disp8 */ |
| 1386 | static const unsigned char jump32_disp32[] = |
| 1387 | {0xe9}; /* jmp disp32 */ |
| 1388 | static const unsigned char jump16_disp32[] = |
| 1389 | {0x66,0xe9}; /* jmp disp32 */ |
| 1390 | /* 32-bit NOPs patterns. */ |
| 1391 | static const unsigned char *const f32_patt[] = { |
| 1392 | f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7 |
| 1393 | }; |
| 1394 | /* 16-bit NOPs patterns. */ |
| 1395 | static const unsigned char *const f16_patt[] = { |
| 1396 | f32_1, f32_2, f16_3, f16_4 |
| 1397 | }; |
| 1398 | /* nopl (%[re]ax) */ |
| 1399 | static const unsigned char alt_3[] = |
| 1400 | {0x0f,0x1f,0x00}; |
| 1401 | /* nopl 0(%[re]ax) */ |
| 1402 | static const unsigned char alt_4[] = |
| 1403 | {0x0f,0x1f,0x40,0x00}; |
| 1404 | /* nopl 0(%[re]ax,%[re]ax,1) */ |
| 1405 | static const unsigned char alt_5[] = |
| 1406 | {0x0f,0x1f,0x44,0x00,0x00}; |
| 1407 | /* nopw 0(%[re]ax,%[re]ax,1) */ |
| 1408 | static const unsigned char alt_6[] = |
| 1409 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; |
| 1410 | /* nopl 0L(%[re]ax) */ |
| 1411 | static const unsigned char alt_7[] = |
| 1412 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; |
| 1413 | /* nopl 0L(%[re]ax,%[re]ax,1) */ |
| 1414 | static const unsigned char alt_8[] = |
| 1415 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
| 1416 | /* nopw 0L(%[re]ax,%[re]ax,1) */ |
| 1417 | static const unsigned char alt_9[] = |
| 1418 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
| 1419 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ |
| 1420 | static const unsigned char alt_10[] = |
| 1421 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
| 1422 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
| 1423 | static const unsigned char alt_11[] = |
| 1424 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
| 1425 | /* 32-bit and 64-bit NOPs patterns. */ |
| 1426 | static const unsigned char *const alt_patt[] = { |
| 1427 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, |
| 1428 | alt_9, alt_10, alt_11 |
| 1429 | }; |
| 1430 | |
| 1431 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum |
| 1432 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ |
| 1433 | |
| 1434 | static void |
| 1435 | i386_output_nops (char *where, const unsigned char *const *patt, |
| 1436 | int count, int max_single_nop_size) |
| 1437 | |
| 1438 | { |
| 1439 | /* Place the longer NOP first. */ |
| 1440 | int last; |
| 1441 | int offset; |
| 1442 | const unsigned char *nops; |
| 1443 | |
| 1444 | if (max_single_nop_size < 1) |
| 1445 | { |
| 1446 | as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"), |
| 1447 | max_single_nop_size); |
| 1448 | return; |
| 1449 | } |
| 1450 | |
| 1451 | nops = patt[max_single_nop_size - 1]; |
| 1452 | |
| 1453 | /* Use the smaller one if the requsted one isn't available. */ |
| 1454 | if (nops == NULL) |
| 1455 | { |
| 1456 | max_single_nop_size--; |
| 1457 | nops = patt[max_single_nop_size - 1]; |
| 1458 | } |
| 1459 | |
| 1460 | last = count % max_single_nop_size; |
| 1461 | |
| 1462 | count -= last; |
| 1463 | for (offset = 0; offset < count; offset += max_single_nop_size) |
| 1464 | memcpy (where + offset, nops, max_single_nop_size); |
| 1465 | |
| 1466 | if (last) |
| 1467 | { |
| 1468 | nops = patt[last - 1]; |
| 1469 | if (nops == NULL) |
| 1470 | { |
| 1471 | /* Use the smaller one plus one-byte NOP if the needed one |
| 1472 | isn't available. */ |
| 1473 | last--; |
| 1474 | nops = patt[last - 1]; |
| 1475 | memcpy (where + offset, nops, last); |
| 1476 | where[offset + last] = *patt[0]; |
| 1477 | } |
| 1478 | else |
| 1479 | memcpy (where + offset, nops, last); |
| 1480 | } |
| 1481 | } |
| 1482 | |
| 1483 | static INLINE int |
| 1484 | fits_in_imm7 (offsetT num) |
| 1485 | { |
| 1486 | return (num & 0x7f) == num; |
| 1487 | } |
| 1488 | |
| 1489 | static INLINE int |
| 1490 | fits_in_imm31 (offsetT num) |
| 1491 | { |
| 1492 | return (num & 0x7fffffff) == num; |
| 1493 | } |
| 1494 | |
| 1495 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a |
| 1496 | single NOP instruction LIMIT. */ |
| 1497 | |
| 1498 | void |
| 1499 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
| 1500 | { |
| 1501 | const unsigned char *const *patt = NULL; |
| 1502 | int max_single_nop_size; |
| 1503 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
| 1504 | int max_number_of_nops; |
| 1505 | |
| 1506 | switch (fragP->fr_type) |
| 1507 | { |
| 1508 | case rs_fill_nop: |
| 1509 | case rs_align_code: |
| 1510 | break; |
| 1511 | case rs_machine_dependent: |
| 1512 | /* Allow NOP padding for jumps and calls. */ |
| 1513 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
| 1514 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) |
| 1515 | break; |
| 1516 | /* Fall through. */ |
| 1517 | default: |
| 1518 | return; |
| 1519 | } |
| 1520 | |
| 1521 | /* We need to decide which NOP sequence to use for 32bit and |
| 1522 | 64bit. When -mtune= is used: |
| 1523 | |
| 1524 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
| 1525 | PROCESSOR_GENERIC32, f32_patt will be used. |
| 1526 | 2. For the rest, alt_patt will be used. |
| 1527 | |
| 1528 | When -mtune= isn't used, alt_patt will be used if |
| 1529 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
| 1530 | be used. |
| 1531 | |
| 1532 | When -march= or .arch is used, we can't use anything beyond |
| 1533 | cpu_arch_isa_flags. */ |
| 1534 | |
| 1535 | if (flag_code == CODE_16BIT) |
| 1536 | { |
| 1537 | patt = f16_patt; |
| 1538 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); |
| 1539 | /* Limit number of NOPs to 2 in 16-bit mode. */ |
| 1540 | max_number_of_nops = 2; |
| 1541 | } |
| 1542 | else |
| 1543 | { |
| 1544 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
| 1545 | { |
| 1546 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ |
| 1547 | switch (cpu_arch_tune) |
| 1548 | { |
| 1549 | case PROCESSOR_UNKNOWN: |
| 1550 | /* We use cpu_arch_isa_flags to check if we SHOULD |
| 1551 | optimize with nops. */ |
| 1552 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
| 1553 | patt = alt_patt; |
| 1554 | else |
| 1555 | patt = f32_patt; |
| 1556 | break; |
| 1557 | case PROCESSOR_PENTIUM4: |
| 1558 | case PROCESSOR_NOCONA: |
| 1559 | case PROCESSOR_CORE: |
| 1560 | case PROCESSOR_CORE2: |
| 1561 | case PROCESSOR_COREI7: |
| 1562 | case PROCESSOR_L1OM: |
| 1563 | case PROCESSOR_K1OM: |
| 1564 | case PROCESSOR_GENERIC64: |
| 1565 | case PROCESSOR_K6: |
| 1566 | case PROCESSOR_ATHLON: |
| 1567 | case PROCESSOR_K8: |
| 1568 | case PROCESSOR_AMDFAM10: |
| 1569 | case PROCESSOR_BD: |
| 1570 | case PROCESSOR_ZNVER: |
| 1571 | case PROCESSOR_BT: |
| 1572 | patt = alt_patt; |
| 1573 | break; |
| 1574 | case PROCESSOR_I386: |
| 1575 | case PROCESSOR_I486: |
| 1576 | case PROCESSOR_PENTIUM: |
| 1577 | case PROCESSOR_PENTIUMPRO: |
| 1578 | case PROCESSOR_IAMCU: |
| 1579 | case PROCESSOR_GENERIC32: |
| 1580 | patt = f32_patt; |
| 1581 | break; |
| 1582 | } |
| 1583 | } |
| 1584 | else |
| 1585 | { |
| 1586 | switch (fragP->tc_frag_data.tune) |
| 1587 | { |
| 1588 | case PROCESSOR_UNKNOWN: |
| 1589 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
| 1590 | PROCESSOR_UNKNOWN. */ |
| 1591 | abort (); |
| 1592 | break; |
| 1593 | |
| 1594 | case PROCESSOR_I386: |
| 1595 | case PROCESSOR_I486: |
| 1596 | case PROCESSOR_PENTIUM: |
| 1597 | case PROCESSOR_IAMCU: |
| 1598 | case PROCESSOR_K6: |
| 1599 | case PROCESSOR_ATHLON: |
| 1600 | case PROCESSOR_K8: |
| 1601 | case PROCESSOR_AMDFAM10: |
| 1602 | case PROCESSOR_BD: |
| 1603 | case PROCESSOR_ZNVER: |
| 1604 | case PROCESSOR_BT: |
| 1605 | case PROCESSOR_GENERIC32: |
| 1606 | /* We use cpu_arch_isa_flags to check if we CAN optimize |
| 1607 | with nops. */ |
| 1608 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
| 1609 | patt = alt_patt; |
| 1610 | else |
| 1611 | patt = f32_patt; |
| 1612 | break; |
| 1613 | case PROCESSOR_PENTIUMPRO: |
| 1614 | case PROCESSOR_PENTIUM4: |
| 1615 | case PROCESSOR_NOCONA: |
| 1616 | case PROCESSOR_CORE: |
| 1617 | case PROCESSOR_CORE2: |
| 1618 | case PROCESSOR_COREI7: |
| 1619 | case PROCESSOR_L1OM: |
| 1620 | case PROCESSOR_K1OM: |
| 1621 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
| 1622 | patt = alt_patt; |
| 1623 | else |
| 1624 | patt = f32_patt; |
| 1625 | break; |
| 1626 | case PROCESSOR_GENERIC64: |
| 1627 | patt = alt_patt; |
| 1628 | break; |
| 1629 | } |
| 1630 | } |
| 1631 | |
| 1632 | if (patt == f32_patt) |
| 1633 | { |
| 1634 | max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]); |
| 1635 | /* Limit number of NOPs to 2 for older processors. */ |
| 1636 | max_number_of_nops = 2; |
| 1637 | } |
| 1638 | else |
| 1639 | { |
| 1640 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); |
| 1641 | /* Limit number of NOPs to 7 for newer processors. */ |
| 1642 | max_number_of_nops = 7; |
| 1643 | } |
| 1644 | } |
| 1645 | |
| 1646 | if (limit == 0) |
| 1647 | limit = max_single_nop_size; |
| 1648 | |
| 1649 | if (fragP->fr_type == rs_fill_nop) |
| 1650 | { |
| 1651 | /* Output NOPs for .nop directive. */ |
| 1652 | if (limit > max_single_nop_size) |
| 1653 | { |
| 1654 | as_bad_where (fragP->fr_file, fragP->fr_line, |
| 1655 | _("invalid single nop size: %d " |
| 1656 | "(expect within [0, %d])"), |
| 1657 | limit, max_single_nop_size); |
| 1658 | return; |
| 1659 | } |
| 1660 | } |
| 1661 | else if (fragP->fr_type != rs_machine_dependent) |
| 1662 | fragP->fr_var = count; |
| 1663 | |
| 1664 | if ((count / max_single_nop_size) > max_number_of_nops) |
| 1665 | { |
| 1666 | /* Generate jump over NOPs. */ |
| 1667 | offsetT disp = count - 2; |
| 1668 | if (fits_in_imm7 (disp)) |
| 1669 | { |
| 1670 | /* Use "jmp disp8" if possible. */ |
| 1671 | count = disp; |
| 1672 | where[0] = jump_disp8[0]; |
| 1673 | where[1] = count; |
| 1674 | where += 2; |
| 1675 | } |
| 1676 | else |
| 1677 | { |
| 1678 | unsigned int size_of_jump; |
| 1679 | |
| 1680 | if (flag_code == CODE_16BIT) |
| 1681 | { |
| 1682 | where[0] = jump16_disp32[0]; |
| 1683 | where[1] = jump16_disp32[1]; |
| 1684 | size_of_jump = 2; |
| 1685 | } |
| 1686 | else |
| 1687 | { |
| 1688 | where[0] = jump32_disp32[0]; |
| 1689 | size_of_jump = 1; |
| 1690 | } |
| 1691 | |
| 1692 | count -= size_of_jump + 4; |
| 1693 | if (!fits_in_imm31 (count)) |
| 1694 | { |
| 1695 | as_bad_where (fragP->fr_file, fragP->fr_line, |
| 1696 | _("jump over nop padding out of range")); |
| 1697 | return; |
| 1698 | } |
| 1699 | |
| 1700 | md_number_to_chars (where + size_of_jump, count, 4); |
| 1701 | where += size_of_jump + 4; |
| 1702 | } |
| 1703 | } |
| 1704 | |
| 1705 | /* Generate multiple NOPs. */ |
| 1706 | i386_output_nops (where, patt, count, limit); |
| 1707 | } |
| 1708 | |
| 1709 | static INLINE int |
| 1710 | operand_type_all_zero (const union i386_operand_type *x) |
| 1711 | { |
| 1712 | switch (ARRAY_SIZE(x->array)) |
| 1713 | { |
| 1714 | case 3: |
| 1715 | if (x->array[2]) |
| 1716 | return 0; |
| 1717 | /* Fall through. */ |
| 1718 | case 2: |
| 1719 | if (x->array[1]) |
| 1720 | return 0; |
| 1721 | /* Fall through. */ |
| 1722 | case 1: |
| 1723 | return !x->array[0]; |
| 1724 | default: |
| 1725 | abort (); |
| 1726 | } |
| 1727 | } |
| 1728 | |
| 1729 | static INLINE void |
| 1730 | operand_type_set (union i386_operand_type *x, unsigned int v) |
| 1731 | { |
| 1732 | switch (ARRAY_SIZE(x->array)) |
| 1733 | { |
| 1734 | case 3: |
| 1735 | x->array[2] = v; |
| 1736 | /* Fall through. */ |
| 1737 | case 2: |
| 1738 | x->array[1] = v; |
| 1739 | /* Fall through. */ |
| 1740 | case 1: |
| 1741 | x->array[0] = v; |
| 1742 | /* Fall through. */ |
| 1743 | break; |
| 1744 | default: |
| 1745 | abort (); |
| 1746 | } |
| 1747 | |
| 1748 | x->bitfield.class = ClassNone; |
| 1749 | x->bitfield.instance = InstanceNone; |
| 1750 | } |
| 1751 | |
| 1752 | static INLINE int |
| 1753 | operand_type_equal (const union i386_operand_type *x, |
| 1754 | const union i386_operand_type *y) |
| 1755 | { |
| 1756 | switch (ARRAY_SIZE(x->array)) |
| 1757 | { |
| 1758 | case 3: |
| 1759 | if (x->array[2] != y->array[2]) |
| 1760 | return 0; |
| 1761 | /* Fall through. */ |
| 1762 | case 2: |
| 1763 | if (x->array[1] != y->array[1]) |
| 1764 | return 0; |
| 1765 | /* Fall through. */ |
| 1766 | case 1: |
| 1767 | return x->array[0] == y->array[0]; |
| 1768 | break; |
| 1769 | default: |
| 1770 | abort (); |
| 1771 | } |
| 1772 | } |
| 1773 | |
| 1774 | static INLINE int |
| 1775 | cpu_flags_all_zero (const union i386_cpu_flags *x) |
| 1776 | { |
| 1777 | switch (ARRAY_SIZE(x->array)) |
| 1778 | { |
| 1779 | case 4: |
| 1780 | if (x->array[3]) |
| 1781 | return 0; |
| 1782 | /* Fall through. */ |
| 1783 | case 3: |
| 1784 | if (x->array[2]) |
| 1785 | return 0; |
| 1786 | /* Fall through. */ |
| 1787 | case 2: |
| 1788 | if (x->array[1]) |
| 1789 | return 0; |
| 1790 | /* Fall through. */ |
| 1791 | case 1: |
| 1792 | return !x->array[0]; |
| 1793 | default: |
| 1794 | abort (); |
| 1795 | } |
| 1796 | } |
| 1797 | |
| 1798 | static INLINE int |
| 1799 | cpu_flags_equal (const union i386_cpu_flags *x, |
| 1800 | const union i386_cpu_flags *y) |
| 1801 | { |
| 1802 | switch (ARRAY_SIZE(x->array)) |
| 1803 | { |
| 1804 | case 4: |
| 1805 | if (x->array[3] != y->array[3]) |
| 1806 | return 0; |
| 1807 | /* Fall through. */ |
| 1808 | case 3: |
| 1809 | if (x->array[2] != y->array[2]) |
| 1810 | return 0; |
| 1811 | /* Fall through. */ |
| 1812 | case 2: |
| 1813 | if (x->array[1] != y->array[1]) |
| 1814 | return 0; |
| 1815 | /* Fall through. */ |
| 1816 | case 1: |
| 1817 | return x->array[0] == y->array[0]; |
| 1818 | break; |
| 1819 | default: |
| 1820 | abort (); |
| 1821 | } |
| 1822 | } |
| 1823 | |
| 1824 | static INLINE int |
| 1825 | cpu_flags_check_cpu64 (i386_cpu_flags f) |
| 1826 | { |
| 1827 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) |
| 1828 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); |
| 1829 | } |
| 1830 | |
| 1831 | static INLINE i386_cpu_flags |
| 1832 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) |
| 1833 | { |
| 1834 | switch (ARRAY_SIZE (x.array)) |
| 1835 | { |
| 1836 | case 4: |
| 1837 | x.array [3] &= y.array [3]; |
| 1838 | /* Fall through. */ |
| 1839 | case 3: |
| 1840 | x.array [2] &= y.array [2]; |
| 1841 | /* Fall through. */ |
| 1842 | case 2: |
| 1843 | x.array [1] &= y.array [1]; |
| 1844 | /* Fall through. */ |
| 1845 | case 1: |
| 1846 | x.array [0] &= y.array [0]; |
| 1847 | break; |
| 1848 | default: |
| 1849 | abort (); |
| 1850 | } |
| 1851 | return x; |
| 1852 | } |
| 1853 | |
| 1854 | static INLINE i386_cpu_flags |
| 1855 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) |
| 1856 | { |
| 1857 | switch (ARRAY_SIZE (x.array)) |
| 1858 | { |
| 1859 | case 4: |
| 1860 | x.array [3] |= y.array [3]; |
| 1861 | /* Fall through. */ |
| 1862 | case 3: |
| 1863 | x.array [2] |= y.array [2]; |
| 1864 | /* Fall through. */ |
| 1865 | case 2: |
| 1866 | x.array [1] |= y.array [1]; |
| 1867 | /* Fall through. */ |
| 1868 | case 1: |
| 1869 | x.array [0] |= y.array [0]; |
| 1870 | break; |
| 1871 | default: |
| 1872 | abort (); |
| 1873 | } |
| 1874 | return x; |
| 1875 | } |
| 1876 | |
| 1877 | static INLINE i386_cpu_flags |
| 1878 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) |
| 1879 | { |
| 1880 | switch (ARRAY_SIZE (x.array)) |
| 1881 | { |
| 1882 | case 4: |
| 1883 | x.array [3] &= ~y.array [3]; |
| 1884 | /* Fall through. */ |
| 1885 | case 3: |
| 1886 | x.array [2] &= ~y.array [2]; |
| 1887 | /* Fall through. */ |
| 1888 | case 2: |
| 1889 | x.array [1] &= ~y.array [1]; |
| 1890 | /* Fall through. */ |
| 1891 | case 1: |
| 1892 | x.array [0] &= ~y.array [0]; |
| 1893 | break; |
| 1894 | default: |
| 1895 | abort (); |
| 1896 | } |
| 1897 | return x; |
| 1898 | } |
| 1899 | |
| 1900 | static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; |
| 1901 | |
| 1902 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
| 1903 | #define CPU_FLAGS_64BIT_MATCH 0x2 |
| 1904 | |
| 1905 | #define CPU_FLAGS_PERFECT_MATCH \ |
| 1906 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH) |
| 1907 | |
| 1908 | /* Return CPU flags match bits. */ |
| 1909 | |
| 1910 | static int |
| 1911 | cpu_flags_match (const insn_template *t) |
| 1912 | { |
| 1913 | i386_cpu_flags x = t->cpu_flags; |
| 1914 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; |
| 1915 | |
| 1916 | x.bitfield.cpu64 = 0; |
| 1917 | x.bitfield.cpuno64 = 0; |
| 1918 | |
| 1919 | if (cpu_flags_all_zero (&x)) |
| 1920 | { |
| 1921 | /* This instruction is available on all archs. */ |
| 1922 | match |= CPU_FLAGS_ARCH_MATCH; |
| 1923 | } |
| 1924 | else |
| 1925 | { |
| 1926 | /* This instruction is available only on some archs. */ |
| 1927 | i386_cpu_flags cpu = cpu_arch_flags; |
| 1928 | |
| 1929 | /* AVX512VL is no standalone feature - match it and then strip it. */ |
| 1930 | if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl) |
| 1931 | return match; |
| 1932 | x.bitfield.cpuavx512vl = 0; |
| 1933 | |
| 1934 | cpu = cpu_flags_and (x, cpu); |
| 1935 | if (!cpu_flags_all_zero (&cpu)) |
| 1936 | { |
| 1937 | if (x.bitfield.cpuavx) |
| 1938 | { |
| 1939 | /* We need to check a few extra flags with AVX. */ |
| 1940 | if (cpu.bitfield.cpuavx |
| 1941 | && (!t->opcode_modifier.sse2avx || sse2avx) |
| 1942 | && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) |
| 1943 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) |
| 1944 | && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul)) |
| 1945 | match |= CPU_FLAGS_ARCH_MATCH; |
| 1946 | } |
| 1947 | else if (x.bitfield.cpuavx512f) |
| 1948 | { |
| 1949 | /* We need to check a few extra flags with AVX512F. */ |
| 1950 | if (cpu.bitfield.cpuavx512f |
| 1951 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) |
| 1952 | && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes) |
| 1953 | && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq)) |
| 1954 | match |= CPU_FLAGS_ARCH_MATCH; |
| 1955 | } |
| 1956 | else |
| 1957 | match |= CPU_FLAGS_ARCH_MATCH; |
| 1958 | } |
| 1959 | } |
| 1960 | return match; |
| 1961 | } |
| 1962 | |
| 1963 | static INLINE i386_operand_type |
| 1964 | operand_type_and (i386_operand_type x, i386_operand_type y) |
| 1965 | { |
| 1966 | if (x.bitfield.class != y.bitfield.class) |
| 1967 | x.bitfield.class = ClassNone; |
| 1968 | if (x.bitfield.instance != y.bitfield.instance) |
| 1969 | x.bitfield.instance = InstanceNone; |
| 1970 | |
| 1971 | switch (ARRAY_SIZE (x.array)) |
| 1972 | { |
| 1973 | case 3: |
| 1974 | x.array [2] &= y.array [2]; |
| 1975 | /* Fall through. */ |
| 1976 | case 2: |
| 1977 | x.array [1] &= y.array [1]; |
| 1978 | /* Fall through. */ |
| 1979 | case 1: |
| 1980 | x.array [0] &= y.array [0]; |
| 1981 | break; |
| 1982 | default: |
| 1983 | abort (); |
| 1984 | } |
| 1985 | return x; |
| 1986 | } |
| 1987 | |
| 1988 | static INLINE i386_operand_type |
| 1989 | operand_type_and_not (i386_operand_type x, i386_operand_type y) |
| 1990 | { |
| 1991 | gas_assert (y.bitfield.class == ClassNone); |
| 1992 | gas_assert (y.bitfield.instance == InstanceNone); |
| 1993 | |
| 1994 | switch (ARRAY_SIZE (x.array)) |
| 1995 | { |
| 1996 | case 3: |
| 1997 | x.array [2] &= ~y.array [2]; |
| 1998 | /* Fall through. */ |
| 1999 | case 2: |
| 2000 | x.array [1] &= ~y.array [1]; |
| 2001 | /* Fall through. */ |
| 2002 | case 1: |
| 2003 | x.array [0] &= ~y.array [0]; |
| 2004 | break; |
| 2005 | default: |
| 2006 | abort (); |
| 2007 | } |
| 2008 | return x; |
| 2009 | } |
| 2010 | |
| 2011 | static INLINE i386_operand_type |
| 2012 | operand_type_or (i386_operand_type x, i386_operand_type y) |
| 2013 | { |
| 2014 | gas_assert (x.bitfield.class == ClassNone || |
| 2015 | y.bitfield.class == ClassNone || |
| 2016 | x.bitfield.class == y.bitfield.class); |
| 2017 | gas_assert (x.bitfield.instance == InstanceNone || |
| 2018 | y.bitfield.instance == InstanceNone || |
| 2019 | x.bitfield.instance == y.bitfield.instance); |
| 2020 | |
| 2021 | switch (ARRAY_SIZE (x.array)) |
| 2022 | { |
| 2023 | case 3: |
| 2024 | x.array [2] |= y.array [2]; |
| 2025 | /* Fall through. */ |
| 2026 | case 2: |
| 2027 | x.array [1] |= y.array [1]; |
| 2028 | /* Fall through. */ |
| 2029 | case 1: |
| 2030 | x.array [0] |= y.array [0]; |
| 2031 | break; |
| 2032 | default: |
| 2033 | abort (); |
| 2034 | } |
| 2035 | return x; |
| 2036 | } |
| 2037 | |
| 2038 | static INLINE i386_operand_type |
| 2039 | operand_type_xor (i386_operand_type x, i386_operand_type y) |
| 2040 | { |
| 2041 | gas_assert (y.bitfield.class == ClassNone); |
| 2042 | gas_assert (y.bitfield.instance == InstanceNone); |
| 2043 | |
| 2044 | switch (ARRAY_SIZE (x.array)) |
| 2045 | { |
| 2046 | case 3: |
| 2047 | x.array [2] ^= y.array [2]; |
| 2048 | /* Fall through. */ |
| 2049 | case 2: |
| 2050 | x.array [1] ^= y.array [1]; |
| 2051 | /* Fall through. */ |
| 2052 | case 1: |
| 2053 | x.array [0] ^= y.array [0]; |
| 2054 | break; |
| 2055 | default: |
| 2056 | abort (); |
| 2057 | } |
| 2058 | return x; |
| 2059 | } |
| 2060 | |
| 2061 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; |
| 2062 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; |
| 2063 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; |
| 2064 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; |
| 2065 | static const i386_operand_type anydisp = OPERAND_TYPE_ANYDISP; |
| 2066 | static const i386_operand_type anyimm = OPERAND_TYPE_ANYIMM; |
| 2067 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
| 2068 | static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; |
| 2069 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
| 2070 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; |
| 2071 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; |
| 2072 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; |
| 2073 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; |
| 2074 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; |
| 2075 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; |
| 2076 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; |
| 2077 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; |
| 2078 | |
| 2079 | enum operand_type |
| 2080 | { |
| 2081 | reg, |
| 2082 | imm, |
| 2083 | disp, |
| 2084 | anymem |
| 2085 | }; |
| 2086 | |
| 2087 | static INLINE int |
| 2088 | operand_type_check (i386_operand_type t, enum operand_type c) |
| 2089 | { |
| 2090 | switch (c) |
| 2091 | { |
| 2092 | case reg: |
| 2093 | return t.bitfield.class == Reg; |
| 2094 | |
| 2095 | case imm: |
| 2096 | return (t.bitfield.imm8 |
| 2097 | || t.bitfield.imm8s |
| 2098 | || t.bitfield.imm16 |
| 2099 | || t.bitfield.imm32 |
| 2100 | || t.bitfield.imm32s |
| 2101 | || t.bitfield.imm64); |
| 2102 | |
| 2103 | case disp: |
| 2104 | return (t.bitfield.disp8 |
| 2105 | || t.bitfield.disp16 |
| 2106 | || t.bitfield.disp32 |
| 2107 | || t.bitfield.disp32s |
| 2108 | || t.bitfield.disp64); |
| 2109 | |
| 2110 | case anymem: |
| 2111 | return (t.bitfield.disp8 |
| 2112 | || t.bitfield.disp16 |
| 2113 | || t.bitfield.disp32 |
| 2114 | || t.bitfield.disp32s |
| 2115 | || t.bitfield.disp64 |
| 2116 | || t.bitfield.baseindex); |
| 2117 | |
| 2118 | default: |
| 2119 | abort (); |
| 2120 | } |
| 2121 | |
| 2122 | return 0; |
| 2123 | } |
| 2124 | |
| 2125 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size |
| 2126 | between operand GIVEN and opeand WANTED for instruction template T. */ |
| 2127 | |
| 2128 | static INLINE int |
| 2129 | match_operand_size (const insn_template *t, unsigned int wanted, |
| 2130 | unsigned int given) |
| 2131 | { |
| 2132 | return !((i.types[given].bitfield.byte |
| 2133 | && !t->operand_types[wanted].bitfield.byte) |
| 2134 | || (i.types[given].bitfield.word |
| 2135 | && !t->operand_types[wanted].bitfield.word) |
| 2136 | || (i.types[given].bitfield.dword |
| 2137 | && !t->operand_types[wanted].bitfield.dword) |
| 2138 | || (i.types[given].bitfield.qword |
| 2139 | && !t->operand_types[wanted].bitfield.qword) |
| 2140 | || (i.types[given].bitfield.tbyte |
| 2141 | && !t->operand_types[wanted].bitfield.tbyte)); |
| 2142 | } |
| 2143 | |
| 2144 | /* Return 1 if there is no conflict in SIMD register between operand |
| 2145 | GIVEN and opeand WANTED for instruction template T. */ |
| 2146 | |
| 2147 | static INLINE int |
| 2148 | match_simd_size (const insn_template *t, unsigned int wanted, |
| 2149 | unsigned int given) |
| 2150 | { |
| 2151 | return !((i.types[given].bitfield.xmmword |
| 2152 | && !t->operand_types[wanted].bitfield.xmmword) |
| 2153 | || (i.types[given].bitfield.ymmword |
| 2154 | && !t->operand_types[wanted].bitfield.ymmword) |
| 2155 | || (i.types[given].bitfield.zmmword |
| 2156 | && !t->operand_types[wanted].bitfield.zmmword)); |
| 2157 | } |
| 2158 | |
| 2159 | /* Return 1 if there is no conflict in any size between operand GIVEN |
| 2160 | and opeand WANTED for instruction template T. */ |
| 2161 | |
| 2162 | static INLINE int |
| 2163 | match_mem_size (const insn_template *t, unsigned int wanted, |
| 2164 | unsigned int given) |
| 2165 | { |
| 2166 | return (match_operand_size (t, wanted, given) |
| 2167 | && !((i.types[given].bitfield.unspecified |
| 2168 | && !i.broadcast |
| 2169 | && !t->operand_types[wanted].bitfield.unspecified) |
| 2170 | || (i.types[given].bitfield.fword |
| 2171 | && !t->operand_types[wanted].bitfield.fword) |
| 2172 | /* For scalar opcode templates to allow register and memory |
| 2173 | operands at the same time, some special casing is needed |
| 2174 | here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and |
| 2175 | down-conversion vpmov*. */ |
| 2176 | || ((t->operand_types[wanted].bitfield.class == RegSIMD |
| 2177 | && t->operand_types[wanted].bitfield.byte |
| 2178 | + t->operand_types[wanted].bitfield.word |
| 2179 | + t->operand_types[wanted].bitfield.dword |
| 2180 | + t->operand_types[wanted].bitfield.qword |
| 2181 | > !!t->opcode_modifier.broadcast) |
| 2182 | ? (i.types[given].bitfield.xmmword |
| 2183 | || i.types[given].bitfield.ymmword |
| 2184 | || i.types[given].bitfield.zmmword) |
| 2185 | : !match_simd_size(t, wanted, given)))); |
| 2186 | } |
| 2187 | |
| 2188 | /* Return value has MATCH_STRAIGHT set if there is no size conflict on any |
| 2189 | operands for instruction template T, and it has MATCH_REVERSE set if there |
| 2190 | is no size conflict on any operands for the template with operands reversed |
| 2191 | (and the template allows for reversing in the first place). */ |
| 2192 | |
| 2193 | #define MATCH_STRAIGHT 1 |
| 2194 | #define MATCH_REVERSE 2 |
| 2195 | |
| 2196 | static INLINE unsigned int |
| 2197 | operand_size_match (const insn_template *t) |
| 2198 | { |
| 2199 | unsigned int j, match = MATCH_STRAIGHT; |
| 2200 | |
| 2201 | /* Don't check non-absolute jump instructions. */ |
| 2202 | if (t->opcode_modifier.jump |
| 2203 | && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
| 2204 | return match; |
| 2205 | |
| 2206 | /* Check memory and accumulator operand size. */ |
| 2207 | for (j = 0; j < i.operands; j++) |
| 2208 | { |
| 2209 | if (i.types[j].bitfield.class != Reg |
| 2210 | && i.types[j].bitfield.class != RegSIMD |
| 2211 | && t->opcode_modifier.anysize) |
| 2212 | continue; |
| 2213 | |
| 2214 | if (t->operand_types[j].bitfield.class == Reg |
| 2215 | && !match_operand_size (t, j, j)) |
| 2216 | { |
| 2217 | match = 0; |
| 2218 | break; |
| 2219 | } |
| 2220 | |
| 2221 | if (t->operand_types[j].bitfield.class == RegSIMD |
| 2222 | && !match_simd_size (t, j, j)) |
| 2223 | { |
| 2224 | match = 0; |
| 2225 | break; |
| 2226 | } |
| 2227 | |
| 2228 | if (t->operand_types[j].bitfield.instance == Accum |
| 2229 | && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j))) |
| 2230 | { |
| 2231 | match = 0; |
| 2232 | break; |
| 2233 | } |
| 2234 | |
| 2235 | if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j)) |
| 2236 | { |
| 2237 | match = 0; |
| 2238 | break; |
| 2239 | } |
| 2240 | } |
| 2241 | |
| 2242 | if (!t->opcode_modifier.d) |
| 2243 | { |
| 2244 | mismatch: |
| 2245 | if (!match) |
| 2246 | i.error = operand_size_mismatch; |
| 2247 | return match; |
| 2248 | } |
| 2249 | |
| 2250 | /* Check reverse. */ |
| 2251 | gas_assert (i.operands >= 2 && i.operands <= 3); |
| 2252 | |
| 2253 | for (j = 0; j < i.operands; j++) |
| 2254 | { |
| 2255 | unsigned int given = i.operands - j - 1; |
| 2256 | |
| 2257 | if (t->operand_types[j].bitfield.class == Reg |
| 2258 | && !match_operand_size (t, j, given)) |
| 2259 | goto mismatch; |
| 2260 | |
| 2261 | if (t->operand_types[j].bitfield.class == RegSIMD |
| 2262 | && !match_simd_size (t, j, given)) |
| 2263 | goto mismatch; |
| 2264 | |
| 2265 | if (t->operand_types[j].bitfield.instance == Accum |
| 2266 | && (!match_operand_size (t, j, given) |
| 2267 | || !match_simd_size (t, j, given))) |
| 2268 | goto mismatch; |
| 2269 | |
| 2270 | if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given)) |
| 2271 | goto mismatch; |
| 2272 | } |
| 2273 | |
| 2274 | return match | MATCH_REVERSE; |
| 2275 | } |
| 2276 | |
| 2277 | static INLINE int |
| 2278 | operand_type_match (i386_operand_type overlap, |
| 2279 | i386_operand_type given) |
| 2280 | { |
| 2281 | i386_operand_type temp = overlap; |
| 2282 | |
| 2283 | temp.bitfield.unspecified = 0; |
| 2284 | temp.bitfield.byte = 0; |
| 2285 | temp.bitfield.word = 0; |
| 2286 | temp.bitfield.dword = 0; |
| 2287 | temp.bitfield.fword = 0; |
| 2288 | temp.bitfield.qword = 0; |
| 2289 | temp.bitfield.tbyte = 0; |
| 2290 | temp.bitfield.xmmword = 0; |
| 2291 | temp.bitfield.ymmword = 0; |
| 2292 | temp.bitfield.zmmword = 0; |
| 2293 | if (operand_type_all_zero (&temp)) |
| 2294 | goto mismatch; |
| 2295 | |
| 2296 | if (given.bitfield.baseindex == overlap.bitfield.baseindex) |
| 2297 | return 1; |
| 2298 | |
| 2299 | mismatch: |
| 2300 | i.error = operand_type_mismatch; |
| 2301 | return 0; |
| 2302 | } |
| 2303 | |
| 2304 | /* If given types g0 and g1 are registers they must be of the same type |
| 2305 | unless the expected operand type register overlap is null. |
| 2306 | Some Intel syntax memory operand size checking also happens here. */ |
| 2307 | |
| 2308 | static INLINE int |
| 2309 | operand_type_register_match (i386_operand_type g0, |
| 2310 | i386_operand_type t0, |
| 2311 | i386_operand_type g1, |
| 2312 | i386_operand_type t1) |
| 2313 | { |
| 2314 | if (g0.bitfield.class != Reg |
| 2315 | && g0.bitfield.class != RegSIMD |
| 2316 | && (!operand_type_check (g0, anymem) |
| 2317 | || g0.bitfield.unspecified |
| 2318 | || (t0.bitfield.class != Reg |
| 2319 | && t0.bitfield.class != RegSIMD))) |
| 2320 | return 1; |
| 2321 | |
| 2322 | if (g1.bitfield.class != Reg |
| 2323 | && g1.bitfield.class != RegSIMD |
| 2324 | && (!operand_type_check (g1, anymem) |
| 2325 | || g1.bitfield.unspecified |
| 2326 | || (t1.bitfield.class != Reg |
| 2327 | && t1.bitfield.class != RegSIMD))) |
| 2328 | return 1; |
| 2329 | |
| 2330 | if (g0.bitfield.byte == g1.bitfield.byte |
| 2331 | && g0.bitfield.word == g1.bitfield.word |
| 2332 | && g0.bitfield.dword == g1.bitfield.dword |
| 2333 | && g0.bitfield.qword == g1.bitfield.qword |
| 2334 | && g0.bitfield.xmmword == g1.bitfield.xmmword |
| 2335 | && g0.bitfield.ymmword == g1.bitfield.ymmword |
| 2336 | && g0.bitfield.zmmword == g1.bitfield.zmmword) |
| 2337 | return 1; |
| 2338 | |
| 2339 | if (!(t0.bitfield.byte & t1.bitfield.byte) |
| 2340 | && !(t0.bitfield.word & t1.bitfield.word) |
| 2341 | && !(t0.bitfield.dword & t1.bitfield.dword) |
| 2342 | && !(t0.bitfield.qword & t1.bitfield.qword) |
| 2343 | && !(t0.bitfield.xmmword & t1.bitfield.xmmword) |
| 2344 | && !(t0.bitfield.ymmword & t1.bitfield.ymmword) |
| 2345 | && !(t0.bitfield.zmmword & t1.bitfield.zmmword)) |
| 2346 | return 1; |
| 2347 | |
| 2348 | i.error = register_type_mismatch; |
| 2349 | |
| 2350 | return 0; |
| 2351 | } |
| 2352 | |
| 2353 | static INLINE unsigned int |
| 2354 | register_number (const reg_entry *r) |
| 2355 | { |
| 2356 | unsigned int nr = r->reg_num; |
| 2357 | |
| 2358 | if (r->reg_flags & RegRex) |
| 2359 | nr += 8; |
| 2360 | |
| 2361 | if (r->reg_flags & RegVRex) |
| 2362 | nr += 16; |
| 2363 | |
| 2364 | return nr; |
| 2365 | } |
| 2366 | |
| 2367 | static INLINE unsigned int |
| 2368 | mode_from_disp_size (i386_operand_type t) |
| 2369 | { |
| 2370 | if (t.bitfield.disp8) |
| 2371 | return 1; |
| 2372 | else if (t.bitfield.disp16 |
| 2373 | || t.bitfield.disp32 |
| 2374 | || t.bitfield.disp32s) |
| 2375 | return 2; |
| 2376 | else |
| 2377 | return 0; |
| 2378 | } |
| 2379 | |
| 2380 | static INLINE int |
| 2381 | fits_in_signed_byte (addressT num) |
| 2382 | { |
| 2383 | return num + 0x80 <= 0xff; |
| 2384 | } |
| 2385 | |
| 2386 | static INLINE int |
| 2387 | fits_in_unsigned_byte (addressT num) |
| 2388 | { |
| 2389 | return num <= 0xff; |
| 2390 | } |
| 2391 | |
| 2392 | static INLINE int |
| 2393 | fits_in_unsigned_word (addressT num) |
| 2394 | { |
| 2395 | return num <= 0xffff; |
| 2396 | } |
| 2397 | |
| 2398 | static INLINE int |
| 2399 | fits_in_signed_word (addressT num) |
| 2400 | { |
| 2401 | return num + 0x8000 <= 0xffff; |
| 2402 | } |
| 2403 | |
| 2404 | static INLINE int |
| 2405 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
| 2406 | { |
| 2407 | #ifndef BFD64 |
| 2408 | return 1; |
| 2409 | #else |
| 2410 | return num + 0x80000000 <= 0xffffffff; |
| 2411 | #endif |
| 2412 | } /* fits_in_signed_long() */ |
| 2413 | |
| 2414 | static INLINE int |
| 2415 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
| 2416 | { |
| 2417 | #ifndef BFD64 |
| 2418 | return 1; |
| 2419 | #else |
| 2420 | return num <= 0xffffffff; |
| 2421 | #endif |
| 2422 | } /* fits_in_unsigned_long() */ |
| 2423 | |
| 2424 | static INLINE int |
| 2425 | fits_in_disp8 (offsetT num) |
| 2426 | { |
| 2427 | int shift = i.memshift; |
| 2428 | unsigned int mask; |
| 2429 | |
| 2430 | if (shift == -1) |
| 2431 | abort (); |
| 2432 | |
| 2433 | mask = (1 << shift) - 1; |
| 2434 | |
| 2435 | /* Return 0 if NUM isn't properly aligned. */ |
| 2436 | if ((num & mask)) |
| 2437 | return 0; |
| 2438 | |
| 2439 | /* Check if NUM will fit in 8bit after shift. */ |
| 2440 | return fits_in_signed_byte (num >> shift); |
| 2441 | } |
| 2442 | |
| 2443 | static INLINE int |
| 2444 | fits_in_imm4 (offsetT num) |
| 2445 | { |
| 2446 | return (num & 0xf) == num; |
| 2447 | } |
| 2448 | |
| 2449 | static i386_operand_type |
| 2450 | smallest_imm_type (offsetT num) |
| 2451 | { |
| 2452 | i386_operand_type t; |
| 2453 | |
| 2454 | operand_type_set (&t, 0); |
| 2455 | t.bitfield.imm64 = 1; |
| 2456 | |
| 2457 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) |
| 2458 | { |
| 2459 | /* This code is disabled on the 486 because all the Imm1 forms |
| 2460 | in the opcode table are slower on the i486. They're the |
| 2461 | versions with the implicitly specified single-position |
| 2462 | displacement, which has another syntax if you really want to |
| 2463 | use that form. */ |
| 2464 | t.bitfield.imm1 = 1; |
| 2465 | t.bitfield.imm8 = 1; |
| 2466 | t.bitfield.imm8s = 1; |
| 2467 | t.bitfield.imm16 = 1; |
| 2468 | t.bitfield.imm32 = 1; |
| 2469 | t.bitfield.imm32s = 1; |
| 2470 | } |
| 2471 | else if (fits_in_signed_byte (num)) |
| 2472 | { |
| 2473 | t.bitfield.imm8 = 1; |
| 2474 | t.bitfield.imm8s = 1; |
| 2475 | t.bitfield.imm16 = 1; |
| 2476 | t.bitfield.imm32 = 1; |
| 2477 | t.bitfield.imm32s = 1; |
| 2478 | } |
| 2479 | else if (fits_in_unsigned_byte (num)) |
| 2480 | { |
| 2481 | t.bitfield.imm8 = 1; |
| 2482 | t.bitfield.imm16 = 1; |
| 2483 | t.bitfield.imm32 = 1; |
| 2484 | t.bitfield.imm32s = 1; |
| 2485 | } |
| 2486 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) |
| 2487 | { |
| 2488 | t.bitfield.imm16 = 1; |
| 2489 | t.bitfield.imm32 = 1; |
| 2490 | t.bitfield.imm32s = 1; |
| 2491 | } |
| 2492 | else if (fits_in_signed_long (num)) |
| 2493 | { |
| 2494 | t.bitfield.imm32 = 1; |
| 2495 | t.bitfield.imm32s = 1; |
| 2496 | } |
| 2497 | else if (fits_in_unsigned_long (num)) |
| 2498 | t.bitfield.imm32 = 1; |
| 2499 | |
| 2500 | return t; |
| 2501 | } |
| 2502 | |
| 2503 | static offsetT |
| 2504 | offset_in_range (offsetT val, int size) |
| 2505 | { |
| 2506 | addressT mask; |
| 2507 | |
| 2508 | switch (size) |
| 2509 | { |
| 2510 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
| 2511 | case 2: mask = ((addressT) 1 << 16) - 1; break; |
| 2512 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
| 2513 | #ifdef BFD64 |
| 2514 | case 8: mask = ((addressT) 2 << 63) - 1; break; |
| 2515 | #endif |
| 2516 | default: abort (); |
| 2517 | } |
| 2518 | |
| 2519 | #ifdef BFD64 |
| 2520 | /* If BFD64, sign extend val for 32bit address mode. */ |
| 2521 | if (flag_code != CODE_64BIT |
| 2522 | || i.prefix[ADDR_PREFIX]) |
| 2523 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
| 2524 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); |
| 2525 | #endif |
| 2526 | |
| 2527 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
| 2528 | { |
| 2529 | char buf1[40], buf2[40]; |
| 2530 | |
| 2531 | sprint_value (buf1, val); |
| 2532 | sprint_value (buf2, val & mask); |
| 2533 | as_warn (_("%s shortened to %s"), buf1, buf2); |
| 2534 | } |
| 2535 | return val & mask; |
| 2536 | } |
| 2537 | |
| 2538 | enum PREFIX_GROUP |
| 2539 | { |
| 2540 | PREFIX_EXIST = 0, |
| 2541 | PREFIX_LOCK, |
| 2542 | PREFIX_REP, |
| 2543 | PREFIX_DS, |
| 2544 | PREFIX_OTHER |
| 2545 | }; |
| 2546 | |
| 2547 | /* Returns |
| 2548 | a. PREFIX_EXIST if attempting to add a prefix where one from the |
| 2549 | same class already exists. |
| 2550 | b. PREFIX_LOCK if lock prefix is added. |
| 2551 | c. PREFIX_REP if rep/repne prefix is added. |
| 2552 | d. PREFIX_DS if ds prefix is added. |
| 2553 | e. PREFIX_OTHER if other prefix is added. |
| 2554 | */ |
| 2555 | |
| 2556 | static enum PREFIX_GROUP |
| 2557 | add_prefix (unsigned int prefix) |
| 2558 | { |
| 2559 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
| 2560 | unsigned int q; |
| 2561 | |
| 2562 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
| 2563 | && flag_code == CODE_64BIT) |
| 2564 | { |
| 2565 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
| 2566 | || (i.prefix[REX_PREFIX] & prefix & REX_R) |
| 2567 | || (i.prefix[REX_PREFIX] & prefix & REX_X) |
| 2568 | || (i.prefix[REX_PREFIX] & prefix & REX_B)) |
| 2569 | ret = PREFIX_EXIST; |
| 2570 | q = REX_PREFIX; |
| 2571 | } |
| 2572 | else |
| 2573 | { |
| 2574 | switch (prefix) |
| 2575 | { |
| 2576 | default: |
| 2577 | abort (); |
| 2578 | |
| 2579 | case DS_PREFIX_OPCODE: |
| 2580 | ret = PREFIX_DS; |
| 2581 | /* Fall through. */ |
| 2582 | case CS_PREFIX_OPCODE: |
| 2583 | case ES_PREFIX_OPCODE: |
| 2584 | case FS_PREFIX_OPCODE: |
| 2585 | case GS_PREFIX_OPCODE: |
| 2586 | case SS_PREFIX_OPCODE: |
| 2587 | q = SEG_PREFIX; |
| 2588 | break; |
| 2589 | |
| 2590 | case REPNE_PREFIX_OPCODE: |
| 2591 | case REPE_PREFIX_OPCODE: |
| 2592 | q = REP_PREFIX; |
| 2593 | ret = PREFIX_REP; |
| 2594 | break; |
| 2595 | |
| 2596 | case LOCK_PREFIX_OPCODE: |
| 2597 | q = LOCK_PREFIX; |
| 2598 | ret = PREFIX_LOCK; |
| 2599 | break; |
| 2600 | |
| 2601 | case FWAIT_OPCODE: |
| 2602 | q = WAIT_PREFIX; |
| 2603 | break; |
| 2604 | |
| 2605 | case ADDR_PREFIX_OPCODE: |
| 2606 | q = ADDR_PREFIX; |
| 2607 | break; |
| 2608 | |
| 2609 | case DATA_PREFIX_OPCODE: |
| 2610 | q = DATA_PREFIX; |
| 2611 | break; |
| 2612 | } |
| 2613 | if (i.prefix[q] != 0) |
| 2614 | ret = PREFIX_EXIST; |
| 2615 | } |
| 2616 | |
| 2617 | if (ret) |
| 2618 | { |
| 2619 | if (!i.prefix[q]) |
| 2620 | ++i.prefixes; |
| 2621 | i.prefix[q] |= prefix; |
| 2622 | } |
| 2623 | else |
| 2624 | as_bad (_("same type of prefix used twice")); |
| 2625 | |
| 2626 | return ret; |
| 2627 | } |
| 2628 | |
| 2629 | static void |
| 2630 | update_code_flag (int value, int check) |
| 2631 | { |
| 2632 | PRINTF_LIKE ((*as_error)); |
| 2633 | |
| 2634 | flag_code = (enum flag_code) value; |
| 2635 | if (flag_code == CODE_64BIT) |
| 2636 | { |
| 2637 | cpu_arch_flags.bitfield.cpu64 = 1; |
| 2638 | cpu_arch_flags.bitfield.cpuno64 = 0; |
| 2639 | } |
| 2640 | else |
| 2641 | { |
| 2642 | cpu_arch_flags.bitfield.cpu64 = 0; |
| 2643 | cpu_arch_flags.bitfield.cpuno64 = 1; |
| 2644 | } |
| 2645 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) |
| 2646 | { |
| 2647 | if (check) |
| 2648 | as_error = as_fatal; |
| 2649 | else |
| 2650 | as_error = as_bad; |
| 2651 | (*as_error) (_("64bit mode not supported on `%s'."), |
| 2652 | cpu_arch_name ? cpu_arch_name : default_arch); |
| 2653 | } |
| 2654 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
| 2655 | { |
| 2656 | if (check) |
| 2657 | as_error = as_fatal; |
| 2658 | else |
| 2659 | as_error = as_bad; |
| 2660 | (*as_error) (_("32bit mode not supported on `%s'."), |
| 2661 | cpu_arch_name ? cpu_arch_name : default_arch); |
| 2662 | } |
| 2663 | stackop_size = '\0'; |
| 2664 | } |
| 2665 | |
| 2666 | static void |
| 2667 | set_code_flag (int value) |
| 2668 | { |
| 2669 | update_code_flag (value, 0); |
| 2670 | } |
| 2671 | |
| 2672 | static void |
| 2673 | set_16bit_gcc_code_flag (int new_code_flag) |
| 2674 | { |
| 2675 | flag_code = (enum flag_code) new_code_flag; |
| 2676 | if (flag_code != CODE_16BIT) |
| 2677 | abort (); |
| 2678 | cpu_arch_flags.bitfield.cpu64 = 0; |
| 2679 | cpu_arch_flags.bitfield.cpuno64 = 1; |
| 2680 | stackop_size = LONG_MNEM_SUFFIX; |
| 2681 | } |
| 2682 | |
| 2683 | static void |
| 2684 | set_intel_syntax (int syntax_flag) |
| 2685 | { |
| 2686 | /* Find out if register prefixing is specified. */ |
| 2687 | int ask_naked_reg = 0; |
| 2688 | |
| 2689 | SKIP_WHITESPACE (); |
| 2690 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
| 2691 | { |
| 2692 | char *string; |
| 2693 | int e = get_symbol_name (&string); |
| 2694 | |
| 2695 | if (strcmp (string, "prefix") == 0) |
| 2696 | ask_naked_reg = 1; |
| 2697 | else if (strcmp (string, "noprefix") == 0) |
| 2698 | ask_naked_reg = -1; |
| 2699 | else |
| 2700 | as_bad (_("bad argument to syntax directive.")); |
| 2701 | (void) restore_line_pointer (e); |
| 2702 | } |
| 2703 | demand_empty_rest_of_line (); |
| 2704 | |
| 2705 | intel_syntax = syntax_flag; |
| 2706 | |
| 2707 | if (ask_naked_reg == 0) |
| 2708 | allow_naked_reg = (intel_syntax |
| 2709 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); |
| 2710 | else |
| 2711 | allow_naked_reg = (ask_naked_reg < 0); |
| 2712 | |
| 2713 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
| 2714 | |
| 2715 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
| 2716 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
| 2717 | register_prefix = allow_naked_reg ? "" : "%"; |
| 2718 | } |
| 2719 | |
| 2720 | static void |
| 2721 | set_intel_mnemonic (int mnemonic_flag) |
| 2722 | { |
| 2723 | intel_mnemonic = mnemonic_flag; |
| 2724 | } |
| 2725 | |
| 2726 | static void |
| 2727 | set_allow_index_reg (int flag) |
| 2728 | { |
| 2729 | allow_index_reg = flag; |
| 2730 | } |
| 2731 | |
| 2732 | static void |
| 2733 | set_check (int what) |
| 2734 | { |
| 2735 | enum check_kind *kind; |
| 2736 | const char *str; |
| 2737 | |
| 2738 | if (what) |
| 2739 | { |
| 2740 | kind = &operand_check; |
| 2741 | str = "operand"; |
| 2742 | } |
| 2743 | else |
| 2744 | { |
| 2745 | kind = &sse_check; |
| 2746 | str = "sse"; |
| 2747 | } |
| 2748 | |
| 2749 | SKIP_WHITESPACE (); |
| 2750 | |
| 2751 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
| 2752 | { |
| 2753 | char *string; |
| 2754 | int e = get_symbol_name (&string); |
| 2755 | |
| 2756 | if (strcmp (string, "none") == 0) |
| 2757 | *kind = check_none; |
| 2758 | else if (strcmp (string, "warning") == 0) |
| 2759 | *kind = check_warning; |
| 2760 | else if (strcmp (string, "error") == 0) |
| 2761 | *kind = check_error; |
| 2762 | else |
| 2763 | as_bad (_("bad argument to %s_check directive."), str); |
| 2764 | (void) restore_line_pointer (e); |
| 2765 | } |
| 2766 | else |
| 2767 | as_bad (_("missing argument for %s_check directive"), str); |
| 2768 | |
| 2769 | demand_empty_rest_of_line (); |
| 2770 | } |
| 2771 | |
| 2772 | static void |
| 2773 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, |
| 2774 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
| 2775 | { |
| 2776 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 2777 | static const char *arch; |
| 2778 | |
| 2779 | /* Intel LIOM is only supported on ELF. */ |
| 2780 | if (!IS_ELF) |
| 2781 | return; |
| 2782 | |
| 2783 | if (!arch) |
| 2784 | { |
| 2785 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise |
| 2786 | use default_arch. */ |
| 2787 | arch = cpu_arch_name; |
| 2788 | if (!arch) |
| 2789 | arch = default_arch; |
| 2790 | } |
| 2791 | |
| 2792 | /* If we are targeting Intel MCU, we must enable it. */ |
| 2793 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU |
| 2794 | || new_flag.bitfield.cpuiamcu) |
| 2795 | return; |
| 2796 | |
| 2797 | /* If we are targeting Intel L1OM, we must enable it. */ |
| 2798 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
| 2799 | || new_flag.bitfield.cpul1om) |
| 2800 | return; |
| 2801 | |
| 2802 | /* If we are targeting Intel K1OM, we must enable it. */ |
| 2803 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM |
| 2804 | || new_flag.bitfield.cpuk1om) |
| 2805 | return; |
| 2806 | |
| 2807 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
| 2808 | #endif |
| 2809 | } |
| 2810 | |
| 2811 | static void |
| 2812 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
| 2813 | { |
| 2814 | SKIP_WHITESPACE (); |
| 2815 | |
| 2816 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
| 2817 | { |
| 2818 | char *string; |
| 2819 | int e = get_symbol_name (&string); |
| 2820 | unsigned int j; |
| 2821 | i386_cpu_flags flags; |
| 2822 | |
| 2823 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
| 2824 | { |
| 2825 | if (strcmp (string, cpu_arch[j].name) == 0) |
| 2826 | { |
| 2827 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
| 2828 | |
| 2829 | if (*string != '.') |
| 2830 | { |
| 2831 | cpu_arch_name = cpu_arch[j].name; |
| 2832 | cpu_sub_arch_name = NULL; |
| 2833 | cpu_arch_flags = cpu_arch[j].flags; |
| 2834 | if (flag_code == CODE_64BIT) |
| 2835 | { |
| 2836 | cpu_arch_flags.bitfield.cpu64 = 1; |
| 2837 | cpu_arch_flags.bitfield.cpuno64 = 0; |
| 2838 | } |
| 2839 | else |
| 2840 | { |
| 2841 | cpu_arch_flags.bitfield.cpu64 = 0; |
| 2842 | cpu_arch_flags.bitfield.cpuno64 = 1; |
| 2843 | } |
| 2844 | cpu_arch_isa = cpu_arch[j].type; |
| 2845 | cpu_arch_isa_flags = cpu_arch[j].flags; |
| 2846 | if (!cpu_arch_tune_set) |
| 2847 | { |
| 2848 | cpu_arch_tune = cpu_arch_isa; |
| 2849 | cpu_arch_tune_flags = cpu_arch_isa_flags; |
| 2850 | } |
| 2851 | break; |
| 2852 | } |
| 2853 | |
| 2854 | flags = cpu_flags_or (cpu_arch_flags, |
| 2855 | cpu_arch[j].flags); |
| 2856 | |
| 2857 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
| 2858 | { |
| 2859 | if (cpu_sub_arch_name) |
| 2860 | { |
| 2861 | char *name = cpu_sub_arch_name; |
| 2862 | cpu_sub_arch_name = concat (name, |
| 2863 | cpu_arch[j].name, |
| 2864 | (const char *) NULL); |
| 2865 | free (name); |
| 2866 | } |
| 2867 | else |
| 2868 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
| 2869 | cpu_arch_flags = flags; |
| 2870 | cpu_arch_isa_flags = flags; |
| 2871 | } |
| 2872 | else |
| 2873 | cpu_arch_isa_flags |
| 2874 | = cpu_flags_or (cpu_arch_isa_flags, |
| 2875 | cpu_arch[j].flags); |
| 2876 | (void) restore_line_pointer (e); |
| 2877 | demand_empty_rest_of_line (); |
| 2878 | return; |
| 2879 | } |
| 2880 | } |
| 2881 | |
| 2882 | if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) |
| 2883 | { |
| 2884 | /* Disable an ISA extension. */ |
| 2885 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
| 2886 | if (strcmp (string + 1, cpu_noarch [j].name) == 0) |
| 2887 | { |
| 2888 | flags = cpu_flags_and_not (cpu_arch_flags, |
| 2889 | cpu_noarch[j].flags); |
| 2890 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
| 2891 | { |
| 2892 | if (cpu_sub_arch_name) |
| 2893 | { |
| 2894 | char *name = cpu_sub_arch_name; |
| 2895 | cpu_sub_arch_name = concat (name, string, |
| 2896 | (const char *) NULL); |
| 2897 | free (name); |
| 2898 | } |
| 2899 | else |
| 2900 | cpu_sub_arch_name = xstrdup (string); |
| 2901 | cpu_arch_flags = flags; |
| 2902 | cpu_arch_isa_flags = flags; |
| 2903 | } |
| 2904 | (void) restore_line_pointer (e); |
| 2905 | demand_empty_rest_of_line (); |
| 2906 | return; |
| 2907 | } |
| 2908 | |
| 2909 | j = ARRAY_SIZE (cpu_arch); |
| 2910 | } |
| 2911 | |
| 2912 | if (j >= ARRAY_SIZE (cpu_arch)) |
| 2913 | as_bad (_("no such architecture: `%s'"), string); |
| 2914 | |
| 2915 | *input_line_pointer = e; |
| 2916 | } |
| 2917 | else |
| 2918 | as_bad (_("missing cpu architecture")); |
| 2919 | |
| 2920 | no_cond_jump_promotion = 0; |
| 2921 | if (*input_line_pointer == ',' |
| 2922 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
| 2923 | { |
| 2924 | char *string; |
| 2925 | char e; |
| 2926 | |
| 2927 | ++input_line_pointer; |
| 2928 | e = get_symbol_name (&string); |
| 2929 | |
| 2930 | if (strcmp (string, "nojumps") == 0) |
| 2931 | no_cond_jump_promotion = 1; |
| 2932 | else if (strcmp (string, "jumps") == 0) |
| 2933 | ; |
| 2934 | else |
| 2935 | as_bad (_("no such architecture modifier: `%s'"), string); |
| 2936 | |
| 2937 | (void) restore_line_pointer (e); |
| 2938 | } |
| 2939 | |
| 2940 | demand_empty_rest_of_line (); |
| 2941 | } |
| 2942 | |
| 2943 | enum bfd_architecture |
| 2944 | i386_arch (void) |
| 2945 | { |
| 2946 | if (cpu_arch_isa == PROCESSOR_L1OM) |
| 2947 | { |
| 2948 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
| 2949 | || flag_code != CODE_64BIT) |
| 2950 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
| 2951 | return bfd_arch_l1om; |
| 2952 | } |
| 2953 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
| 2954 | { |
| 2955 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
| 2956 | || flag_code != CODE_64BIT) |
| 2957 | as_fatal (_("Intel K1OM is 64bit ELF only")); |
| 2958 | return bfd_arch_k1om; |
| 2959 | } |
| 2960 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
| 2961 | { |
| 2962 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
| 2963 | || flag_code == CODE_64BIT) |
| 2964 | as_fatal (_("Intel MCU is 32bit ELF only")); |
| 2965 | return bfd_arch_iamcu; |
| 2966 | } |
| 2967 | else |
| 2968 | return bfd_arch_i386; |
| 2969 | } |
| 2970 | |
| 2971 | unsigned long |
| 2972 | i386_mach (void) |
| 2973 | { |
| 2974 | if (!strncmp (default_arch, "x86_64", 6)) |
| 2975 | { |
| 2976 | if (cpu_arch_isa == PROCESSOR_L1OM) |
| 2977 | { |
| 2978 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
| 2979 | || default_arch[6] != '\0') |
| 2980 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
| 2981 | return bfd_mach_l1om; |
| 2982 | } |
| 2983 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
| 2984 | { |
| 2985 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
| 2986 | || default_arch[6] != '\0') |
| 2987 | as_fatal (_("Intel K1OM is 64bit ELF only")); |
| 2988 | return bfd_mach_k1om; |
| 2989 | } |
| 2990 | else if (default_arch[6] == '\0') |
| 2991 | return bfd_mach_x86_64; |
| 2992 | else |
| 2993 | return bfd_mach_x64_32; |
| 2994 | } |
| 2995 | else if (!strcmp (default_arch, "i386") |
| 2996 | || !strcmp (default_arch, "iamcu")) |
| 2997 | { |
| 2998 | if (cpu_arch_isa == PROCESSOR_IAMCU) |
| 2999 | { |
| 3000 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
| 3001 | as_fatal (_("Intel MCU is 32bit ELF only")); |
| 3002 | return bfd_mach_i386_iamcu; |
| 3003 | } |
| 3004 | else |
| 3005 | return bfd_mach_i386_i386; |
| 3006 | } |
| 3007 | else |
| 3008 | as_fatal (_("unknown architecture")); |
| 3009 | } |
| 3010 | \f |
| 3011 | void |
| 3012 | md_begin (void) |
| 3013 | { |
| 3014 | const char *hash_err; |
| 3015 | |
| 3016 | /* Support pseudo prefixes like {disp32}. */ |
| 3017 | lex_type ['{'] = LEX_BEGIN_NAME; |
| 3018 | |
| 3019 | /* Initialize op_hash hash table. */ |
| 3020 | op_hash = hash_new (); |
| 3021 | |
| 3022 | { |
| 3023 | const insn_template *optab; |
| 3024 | templates *core_optab; |
| 3025 | |
| 3026 | /* Setup for loop. */ |
| 3027 | optab = i386_optab; |
| 3028 | core_optab = XNEW (templates); |
| 3029 | core_optab->start = optab; |
| 3030 | |
| 3031 | while (1) |
| 3032 | { |
| 3033 | ++optab; |
| 3034 | if (optab->name == NULL |
| 3035 | || strcmp (optab->name, (optab - 1)->name) != 0) |
| 3036 | { |
| 3037 | /* different name --> ship out current template list; |
| 3038 | add to hash table; & begin anew. */ |
| 3039 | core_optab->end = optab; |
| 3040 | hash_err = hash_insert (op_hash, |
| 3041 | (optab - 1)->name, |
| 3042 | (void *) core_optab); |
| 3043 | if (hash_err) |
| 3044 | { |
| 3045 | as_fatal (_("can't hash %s: %s"), |
| 3046 | (optab - 1)->name, |
| 3047 | hash_err); |
| 3048 | } |
| 3049 | if (optab->name == NULL) |
| 3050 | break; |
| 3051 | core_optab = XNEW (templates); |
| 3052 | core_optab->start = optab; |
| 3053 | } |
| 3054 | } |
| 3055 | } |
| 3056 | |
| 3057 | /* Initialize reg_hash hash table. */ |
| 3058 | reg_hash = hash_new (); |
| 3059 | { |
| 3060 | const reg_entry *regtab; |
| 3061 | unsigned int regtab_size = i386_regtab_size; |
| 3062 | |
| 3063 | for (regtab = i386_regtab; regtab_size--; regtab++) |
| 3064 | { |
| 3065 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
| 3066 | if (hash_err) |
| 3067 | as_fatal (_("can't hash %s: %s"), |
| 3068 | regtab->reg_name, |
| 3069 | hash_err); |
| 3070 | } |
| 3071 | } |
| 3072 | |
| 3073 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
| 3074 | { |
| 3075 | int c; |
| 3076 | char *p; |
| 3077 | |
| 3078 | for (c = 0; c < 256; c++) |
| 3079 | { |
| 3080 | if (ISDIGIT (c)) |
| 3081 | { |
| 3082 | digit_chars[c] = c; |
| 3083 | mnemonic_chars[c] = c; |
| 3084 | register_chars[c] = c; |
| 3085 | operand_chars[c] = c; |
| 3086 | } |
| 3087 | else if (ISLOWER (c)) |
| 3088 | { |
| 3089 | mnemonic_chars[c] = c; |
| 3090 | register_chars[c] = c; |
| 3091 | operand_chars[c] = c; |
| 3092 | } |
| 3093 | else if (ISUPPER (c)) |
| 3094 | { |
| 3095 | mnemonic_chars[c] = TOLOWER (c); |
| 3096 | register_chars[c] = mnemonic_chars[c]; |
| 3097 | operand_chars[c] = c; |
| 3098 | } |
| 3099 | else if (c == '{' || c == '}') |
| 3100 | { |
| 3101 | mnemonic_chars[c] = c; |
| 3102 | operand_chars[c] = c; |
| 3103 | } |
| 3104 | |
| 3105 | if (ISALPHA (c) || ISDIGIT (c)) |
| 3106 | identifier_chars[c] = c; |
| 3107 | else if (c >= 128) |
| 3108 | { |
| 3109 | identifier_chars[c] = c; |
| 3110 | operand_chars[c] = c; |
| 3111 | } |
| 3112 | } |
| 3113 | |
| 3114 | #ifdef LEX_AT |
| 3115 | identifier_chars['@'] = '@'; |
| 3116 | #endif |
| 3117 | #ifdef LEX_QM |
| 3118 | identifier_chars['?'] = '?'; |
| 3119 | operand_chars['?'] = '?'; |
| 3120 | #endif |
| 3121 | digit_chars['-'] = '-'; |
| 3122 | mnemonic_chars['_'] = '_'; |
| 3123 | mnemonic_chars['-'] = '-'; |
| 3124 | mnemonic_chars['.'] = '.'; |
| 3125 | identifier_chars['_'] = '_'; |
| 3126 | identifier_chars['.'] = '.'; |
| 3127 | |
| 3128 | for (p = operand_special_chars; *p != '\0'; p++) |
| 3129 | operand_chars[(unsigned char) *p] = *p; |
| 3130 | } |
| 3131 | |
| 3132 | if (flag_code == CODE_64BIT) |
| 3133 | { |
| 3134 | #if defined (OBJ_COFF) && defined (TE_PE) |
| 3135 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour |
| 3136 | ? 32 : 16); |
| 3137 | #else |
| 3138 | x86_dwarf2_return_column = 16; |
| 3139 | #endif |
| 3140 | x86_cie_data_alignment = -8; |
| 3141 | } |
| 3142 | else |
| 3143 | { |
| 3144 | x86_dwarf2_return_column = 8; |
| 3145 | x86_cie_data_alignment = -4; |
| 3146 | } |
| 3147 | |
| 3148 | /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it |
| 3149 | can be turned into BRANCH_PREFIX frag. */ |
| 3150 | if (align_branch_prefix_size > MAX_FUSED_JCC_PADDING_SIZE) |
| 3151 | abort (); |
| 3152 | } |
| 3153 | |
| 3154 | void |
| 3155 | i386_print_statistics (FILE *file) |
| 3156 | { |
| 3157 | hash_print_statistics (file, "i386 opcode", op_hash); |
| 3158 | hash_print_statistics (file, "i386 register", reg_hash); |
| 3159 | } |
| 3160 | \f |
| 3161 | #ifdef DEBUG386 |
| 3162 | |
| 3163 | /* Debugging routines for md_assemble. */ |
| 3164 | static void pte (insn_template *); |
| 3165 | static void pt (i386_operand_type); |
| 3166 | static void pe (expressionS *); |
| 3167 | static void ps (symbolS *); |
| 3168 | |
| 3169 | static void |
| 3170 | pi (const char *line, i386_insn *x) |
| 3171 | { |
| 3172 | unsigned int j; |
| 3173 | |
| 3174 | fprintf (stdout, "%s: template ", line); |
| 3175 | pte (&x->tm); |
| 3176 | fprintf (stdout, " address: base %s index %s scale %x\n", |
| 3177 | x->base_reg ? x->base_reg->reg_name : "none", |
| 3178 | x->index_reg ? x->index_reg->reg_name : "none", |
| 3179 | x->log2_scale_factor); |
| 3180 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", |
| 3181 | x->rm.mode, x->rm.reg, x->rm.regmem); |
| 3182 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
| 3183 | x->sib.base, x->sib.index, x->sib.scale); |
| 3184 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", |
| 3185 | (x->rex & REX_W) != 0, |
| 3186 | (x->rex & REX_R) != 0, |
| 3187 | (x->rex & REX_X) != 0, |
| 3188 | (x->rex & REX_B) != 0); |
| 3189 | for (j = 0; j < x->operands; j++) |
| 3190 | { |
| 3191 | fprintf (stdout, " #%d: ", j + 1); |
| 3192 | pt (x->types[j]); |
| 3193 | fprintf (stdout, "\n"); |
| 3194 | if (x->types[j].bitfield.class == Reg |
| 3195 | || x->types[j].bitfield.class == RegMMX |
| 3196 | || x->types[j].bitfield.class == RegSIMD |
| 3197 | || x->types[j].bitfield.class == SReg |
| 3198 | || x->types[j].bitfield.class == RegCR |
| 3199 | || x->types[j].bitfield.class == RegDR |
| 3200 | || x->types[j].bitfield.class == RegTR) |
| 3201 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); |
| 3202 | if (operand_type_check (x->types[j], imm)) |
| 3203 | pe (x->op[j].imms); |
| 3204 | if (operand_type_check (x->types[j], disp)) |
| 3205 | pe (x->op[j].disps); |
| 3206 | } |
| 3207 | } |
| 3208 | |
| 3209 | static void |
| 3210 | pte (insn_template *t) |
| 3211 | { |
| 3212 | unsigned int j; |
| 3213 | fprintf (stdout, " %d operands ", t->operands); |
| 3214 | fprintf (stdout, "opcode %x ", t->base_opcode); |
| 3215 | if (t->extension_opcode != None) |
| 3216 | fprintf (stdout, "ext %x ", t->extension_opcode); |
| 3217 | if (t->opcode_modifier.d) |
| 3218 | fprintf (stdout, "D"); |
| 3219 | if (t->opcode_modifier.w) |
| 3220 | fprintf (stdout, "W"); |
| 3221 | fprintf (stdout, "\n"); |
| 3222 | for (j = 0; j < t->operands; j++) |
| 3223 | { |
| 3224 | fprintf (stdout, " #%d type ", j + 1); |
| 3225 | pt (t->operand_types[j]); |
| 3226 | fprintf (stdout, "\n"); |
| 3227 | } |
| 3228 | } |
| 3229 | |
| 3230 | static void |
| 3231 | pe (expressionS *e) |
| 3232 | { |
| 3233 | fprintf (stdout, " operation %d\n", e->X_op); |
| 3234 | fprintf (stdout, " add_number %ld (%lx)\n", |
| 3235 | (long) e->X_add_number, (long) e->X_add_number); |
| 3236 | if (e->X_add_symbol) |
| 3237 | { |
| 3238 | fprintf (stdout, " add_symbol "); |
| 3239 | ps (e->X_add_symbol); |
| 3240 | fprintf (stdout, "\n"); |
| 3241 | } |
| 3242 | if (e->X_op_symbol) |
| 3243 | { |
| 3244 | fprintf (stdout, " op_symbol "); |
| 3245 | ps (e->X_op_symbol); |
| 3246 | fprintf (stdout, "\n"); |
| 3247 | } |
| 3248 | } |
| 3249 | |
| 3250 | static void |
| 3251 | ps (symbolS *s) |
| 3252 | { |
| 3253 | fprintf (stdout, "%s type %s%s", |
| 3254 | S_GET_NAME (s), |
| 3255 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", |
| 3256 | segment_name (S_GET_SEGMENT (s))); |
| 3257 | } |
| 3258 | |
| 3259 | static struct type_name |
| 3260 | { |
| 3261 | i386_operand_type mask; |
| 3262 | const char *name; |
| 3263 | } |
| 3264 | const type_names[] = |
| 3265 | { |
| 3266 | { OPERAND_TYPE_REG8, "r8" }, |
| 3267 | { OPERAND_TYPE_REG16, "r16" }, |
| 3268 | { OPERAND_TYPE_REG32, "r32" }, |
| 3269 | { OPERAND_TYPE_REG64, "r64" }, |
| 3270 | { OPERAND_TYPE_ACC8, "acc8" }, |
| 3271 | { OPERAND_TYPE_ACC16, "acc16" }, |
| 3272 | { OPERAND_TYPE_ACC32, "acc32" }, |
| 3273 | { OPERAND_TYPE_ACC64, "acc64" }, |
| 3274 | { OPERAND_TYPE_IMM8, "i8" }, |
| 3275 | { OPERAND_TYPE_IMM8, "i8s" }, |
| 3276 | { OPERAND_TYPE_IMM16, "i16" }, |
| 3277 | { OPERAND_TYPE_IMM32, "i32" }, |
| 3278 | { OPERAND_TYPE_IMM32S, "i32s" }, |
| 3279 | { OPERAND_TYPE_IMM64, "i64" }, |
| 3280 | { OPERAND_TYPE_IMM1, "i1" }, |
| 3281 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, |
| 3282 | { OPERAND_TYPE_DISP8, "d8" }, |
| 3283 | { OPERAND_TYPE_DISP16, "d16" }, |
| 3284 | { OPERAND_TYPE_DISP32, "d32" }, |
| 3285 | { OPERAND_TYPE_DISP32S, "d32s" }, |
| 3286 | { OPERAND_TYPE_DISP64, "d64" }, |
| 3287 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, |
| 3288 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, |
| 3289 | { OPERAND_TYPE_CONTROL, "control reg" }, |
| 3290 | { OPERAND_TYPE_TEST, "test reg" }, |
| 3291 | { OPERAND_TYPE_DEBUG, "debug reg" }, |
| 3292 | { OPERAND_TYPE_FLOATREG, "FReg" }, |
| 3293 | { OPERAND_TYPE_FLOATACC, "FAcc" }, |
| 3294 | { OPERAND_TYPE_SREG, "SReg" }, |
| 3295 | { OPERAND_TYPE_REGMMX, "rMMX" }, |
| 3296 | { OPERAND_TYPE_REGXMM, "rXMM" }, |
| 3297 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
| 3298 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
| 3299 | { OPERAND_TYPE_REGMASK, "Mask reg" }, |
| 3300 | }; |
| 3301 | |
| 3302 | static void |
| 3303 | pt (i386_operand_type t) |
| 3304 | { |
| 3305 | unsigned int j; |
| 3306 | i386_operand_type a; |
| 3307 | |
| 3308 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
| 3309 | { |
| 3310 | a = operand_type_and (t, type_names[j].mask); |
| 3311 | if (operand_type_equal (&a, &type_names[j].mask)) |
| 3312 | fprintf (stdout, "%s, ", type_names[j].name); |
| 3313 | } |
| 3314 | fflush (stdout); |
| 3315 | } |
| 3316 | |
| 3317 | #endif /* DEBUG386 */ |
| 3318 | \f |
| 3319 | static bfd_reloc_code_real_type |
| 3320 | reloc (unsigned int size, |
| 3321 | int pcrel, |
| 3322 | int sign, |
| 3323 | bfd_reloc_code_real_type other) |
| 3324 | { |
| 3325 | if (other != NO_RELOC) |
| 3326 | { |
| 3327 | reloc_howto_type *rel; |
| 3328 | |
| 3329 | if (size == 8) |
| 3330 | switch (other) |
| 3331 | { |
| 3332 | case BFD_RELOC_X86_64_GOT32: |
| 3333 | return BFD_RELOC_X86_64_GOT64; |
| 3334 | break; |
| 3335 | case BFD_RELOC_X86_64_GOTPLT64: |
| 3336 | return BFD_RELOC_X86_64_GOTPLT64; |
| 3337 | break; |
| 3338 | case BFD_RELOC_X86_64_PLTOFF64: |
| 3339 | return BFD_RELOC_X86_64_PLTOFF64; |
| 3340 | break; |
| 3341 | case BFD_RELOC_X86_64_GOTPC32: |
| 3342 | other = BFD_RELOC_X86_64_GOTPC64; |
| 3343 | break; |
| 3344 | case BFD_RELOC_X86_64_GOTPCREL: |
| 3345 | other = BFD_RELOC_X86_64_GOTPCREL64; |
| 3346 | break; |
| 3347 | case BFD_RELOC_X86_64_TPOFF32: |
| 3348 | other = BFD_RELOC_X86_64_TPOFF64; |
| 3349 | break; |
| 3350 | case BFD_RELOC_X86_64_DTPOFF32: |
| 3351 | other = BFD_RELOC_X86_64_DTPOFF64; |
| 3352 | break; |
| 3353 | default: |
| 3354 | break; |
| 3355 | } |
| 3356 | |
| 3357 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 3358 | if (other == BFD_RELOC_SIZE32) |
| 3359 | { |
| 3360 | if (size == 8) |
| 3361 | other = BFD_RELOC_SIZE64; |
| 3362 | if (pcrel) |
| 3363 | { |
| 3364 | as_bad (_("there are no pc-relative size relocations")); |
| 3365 | return NO_RELOC; |
| 3366 | } |
| 3367 | } |
| 3368 | #endif |
| 3369 | |
| 3370 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
| 3371 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
| 3372 | sign = -1; |
| 3373 | |
| 3374 | rel = bfd_reloc_type_lookup (stdoutput, other); |
| 3375 | if (!rel) |
| 3376 | as_bad (_("unknown relocation (%u)"), other); |
| 3377 | else if (size != bfd_get_reloc_size (rel)) |
| 3378 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
| 3379 | bfd_get_reloc_size (rel), |
| 3380 | size); |
| 3381 | else if (pcrel && !rel->pc_relative) |
| 3382 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
| 3383 | else if ((rel->complain_on_overflow == complain_overflow_signed |
| 3384 | && !sign) |
| 3385 | || (rel->complain_on_overflow == complain_overflow_unsigned |
| 3386 | && sign > 0)) |
| 3387 | as_bad (_("relocated field and relocation type differ in signedness")); |
| 3388 | else |
| 3389 | return other; |
| 3390 | return NO_RELOC; |
| 3391 | } |
| 3392 | |
| 3393 | if (pcrel) |
| 3394 | { |
| 3395 | if (!sign) |
| 3396 | as_bad (_("there are no unsigned pc-relative relocations")); |
| 3397 | switch (size) |
| 3398 | { |
| 3399 | case 1: return BFD_RELOC_8_PCREL; |
| 3400 | case 2: return BFD_RELOC_16_PCREL; |
| 3401 | case 4: return BFD_RELOC_32_PCREL; |
| 3402 | case 8: return BFD_RELOC_64_PCREL; |
| 3403 | } |
| 3404 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
| 3405 | } |
| 3406 | else |
| 3407 | { |
| 3408 | if (sign > 0) |
| 3409 | switch (size) |
| 3410 | { |
| 3411 | case 4: return BFD_RELOC_X86_64_32S; |
| 3412 | } |
| 3413 | else |
| 3414 | switch (size) |
| 3415 | { |
| 3416 | case 1: return BFD_RELOC_8; |
| 3417 | case 2: return BFD_RELOC_16; |
| 3418 | case 4: return BFD_RELOC_32; |
| 3419 | case 8: return BFD_RELOC_64; |
| 3420 | } |
| 3421 | as_bad (_("cannot do %s %u byte relocation"), |
| 3422 | sign > 0 ? "signed" : "unsigned", size); |
| 3423 | } |
| 3424 | |
| 3425 | return NO_RELOC; |
| 3426 | } |
| 3427 | |
| 3428 | /* Here we decide which fixups can be adjusted to make them relative to |
| 3429 | the beginning of the section instead of the symbol. Basically we need |
| 3430 | to make sure that the dynamic relocations are done correctly, so in |
| 3431 | some cases we force the original symbol to be used. */ |
| 3432 | |
| 3433 | int |
| 3434 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
| 3435 | { |
| 3436 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 3437 | if (!IS_ELF) |
| 3438 | return 1; |
| 3439 | |
| 3440 | /* Don't adjust pc-relative references to merge sections in 64-bit |
| 3441 | mode. */ |
| 3442 | if (use_rela_relocations |
| 3443 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 |
| 3444 | && fixP->fx_pcrel) |
| 3445 | return 0; |
| 3446 | |
| 3447 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
| 3448 | and changed later by validate_fix. */ |
| 3449 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol |
| 3450 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) |
| 3451 | return 0; |
| 3452 | |
| 3453 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
| 3454 | for size relocations. */ |
| 3455 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 |
| 3456 | || fixP->fx_r_type == BFD_RELOC_SIZE64 |
| 3457 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
| 3458 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 |
| 3459 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
| 3460 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
| 3461 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM |
| 3462 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 |
| 3463 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 |
| 3464 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
| 3465 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE |
| 3466 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
| 3467 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE |
| 3468 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
| 3469 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL |
| 3470 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 |
| 3471 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
| 3472 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
| 3473 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX |
| 3474 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
| 3475 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD |
| 3476 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 |
| 3477 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
| 3478 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
| 3479 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 |
| 3480 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
| 3481 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 |
| 3482 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
| 3483 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL |
| 3484 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
| 3485 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
| 3486 | return 0; |
| 3487 | #endif |
| 3488 | return 1; |
| 3489 | } |
| 3490 | |
| 3491 | static int |
| 3492 | intel_float_operand (const char *mnemonic) |
| 3493 | { |
| 3494 | /* Note that the value returned is meaningful only for opcodes with (memory) |
| 3495 | operands, hence the code here is free to improperly handle opcodes that |
| 3496 | have no operands (for better performance and smaller code). */ |
| 3497 | |
| 3498 | if (mnemonic[0] != 'f') |
| 3499 | return 0; /* non-math */ |
| 3500 | |
| 3501 | switch (mnemonic[1]) |
| 3502 | { |
| 3503 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and |
| 3504 | the fs segment override prefix not currently handled because no |
| 3505 | call path can make opcodes without operands get here */ |
| 3506 | case 'i': |
| 3507 | return 2 /* integer op */; |
| 3508 | case 'l': |
| 3509 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) |
| 3510 | return 3; /* fldcw/fldenv */ |
| 3511 | break; |
| 3512 | case 'n': |
| 3513 | if (mnemonic[2] != 'o' /* fnop */) |
| 3514 | return 3; /* non-waiting control op */ |
| 3515 | break; |
| 3516 | case 'r': |
| 3517 | if (mnemonic[2] == 's') |
| 3518 | return 3; /* frstor/frstpm */ |
| 3519 | break; |
| 3520 | case 's': |
| 3521 | if (mnemonic[2] == 'a') |
| 3522 | return 3; /* fsave */ |
| 3523 | if (mnemonic[2] == 't') |
| 3524 | { |
| 3525 | switch (mnemonic[3]) |
| 3526 | { |
| 3527 | case 'c': /* fstcw */ |
| 3528 | case 'd': /* fstdw */ |
| 3529 | case 'e': /* fstenv */ |
| 3530 | case 's': /* fsts[gw] */ |
| 3531 | return 3; |
| 3532 | } |
| 3533 | } |
| 3534 | break; |
| 3535 | case 'x': |
| 3536 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') |
| 3537 | return 0; /* fxsave/fxrstor are not really math ops */ |
| 3538 | break; |
| 3539 | } |
| 3540 | |
| 3541 | return 1; |
| 3542 | } |
| 3543 | |
| 3544 | /* Build the VEX prefix. */ |
| 3545 | |
| 3546 | static void |
| 3547 | build_vex_prefix (const insn_template *t) |
| 3548 | { |
| 3549 | unsigned int register_specifier; |
| 3550 | unsigned int implied_prefix; |
| 3551 | unsigned int vector_length; |
| 3552 | unsigned int w; |
| 3553 | |
| 3554 | /* Check register specifier. */ |
| 3555 | if (i.vex.register_specifier) |
| 3556 | { |
| 3557 | register_specifier = |
| 3558 | ~register_number (i.vex.register_specifier) & 0xf; |
| 3559 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); |
| 3560 | } |
| 3561 | else |
| 3562 | register_specifier = 0xf; |
| 3563 | |
| 3564 | /* Use 2-byte VEX prefix by swapping destination and source operand |
| 3565 | if there are more than 1 register operand. */ |
| 3566 | if (i.reg_operands > 1 |
| 3567 | && i.vec_encoding != vex_encoding_vex3 |
| 3568 | && i.dir_encoding == dir_encoding_default |
| 3569 | && i.operands == i.reg_operands |
| 3570 | && operand_type_equal (&i.types[0], &i.types[i.operands - 1]) |
| 3571 | && i.tm.opcode_modifier.vexopcode == VEX0F |
| 3572 | && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d) |
| 3573 | && i.rex == REX_B) |
| 3574 | { |
| 3575 | unsigned int xchg = i.operands - 1; |
| 3576 | union i386_op temp_op; |
| 3577 | i386_operand_type temp_type; |
| 3578 | |
| 3579 | temp_type = i.types[xchg]; |
| 3580 | i.types[xchg] = i.types[0]; |
| 3581 | i.types[0] = temp_type; |
| 3582 | temp_op = i.op[xchg]; |
| 3583 | i.op[xchg] = i.op[0]; |
| 3584 | i.op[0] = temp_op; |
| 3585 | |
| 3586 | gas_assert (i.rm.mode == 3); |
| 3587 | |
| 3588 | i.rex = REX_R; |
| 3589 | xchg = i.rm.regmem; |
| 3590 | i.rm.regmem = i.rm.reg; |
| 3591 | i.rm.reg = xchg; |
| 3592 | |
| 3593 | if (i.tm.opcode_modifier.d) |
| 3594 | i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e |
| 3595 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; |
| 3596 | else /* Use the next insn. */ |
| 3597 | i.tm = t[1]; |
| 3598 | } |
| 3599 | |
| 3600 | /* Use 2-byte VEX prefix by swapping commutative source operands if there |
| 3601 | are no memory operands and at least 3 register ones. */ |
| 3602 | if (i.reg_operands >= 3 |
| 3603 | && i.vec_encoding != vex_encoding_vex3 |
| 3604 | && i.reg_operands == i.operands - i.imm_operands |
| 3605 | && i.tm.opcode_modifier.vex |
| 3606 | && i.tm.opcode_modifier.commutative |
| 3607 | && (i.tm.opcode_modifier.sse2avx || optimize > 1) |
| 3608 | && i.rex == REX_B |
| 3609 | && i.vex.register_specifier |
| 3610 | && !(i.vex.register_specifier->reg_flags & RegRex)) |
| 3611 | { |
| 3612 | unsigned int xchg = i.operands - i.reg_operands; |
| 3613 | union i386_op temp_op; |
| 3614 | i386_operand_type temp_type; |
| 3615 | |
| 3616 | gas_assert (i.tm.opcode_modifier.vexopcode == VEX0F); |
| 3617 | gas_assert (!i.tm.opcode_modifier.sae); |
| 3618 | gas_assert (operand_type_equal (&i.types[i.operands - 2], |
| 3619 | &i.types[i.operands - 3])); |
| 3620 | gas_assert (i.rm.mode == 3); |
| 3621 | |
| 3622 | temp_type = i.types[xchg]; |
| 3623 | i.types[xchg] = i.types[xchg + 1]; |
| 3624 | i.types[xchg + 1] = temp_type; |
| 3625 | temp_op = i.op[xchg]; |
| 3626 | i.op[xchg] = i.op[xchg + 1]; |
| 3627 | i.op[xchg + 1] = temp_op; |
| 3628 | |
| 3629 | i.rex = 0; |
| 3630 | xchg = i.rm.regmem | 8; |
| 3631 | i.rm.regmem = ~register_specifier & 0xf; |
| 3632 | gas_assert (!(i.rm.regmem & 8)); |
| 3633 | i.vex.register_specifier += xchg - i.rm.regmem; |
| 3634 | register_specifier = ~xchg & 0xf; |
| 3635 | } |
| 3636 | |
| 3637 | if (i.tm.opcode_modifier.vex == VEXScalar) |
| 3638 | vector_length = avxscalar; |
| 3639 | else if (i.tm.opcode_modifier.vex == VEX256) |
| 3640 | vector_length = 1; |
| 3641 | else |
| 3642 | { |
| 3643 | unsigned int op; |
| 3644 | |
| 3645 | /* Determine vector length from the last multi-length vector |
| 3646 | operand. */ |
| 3647 | vector_length = 0; |
| 3648 | for (op = t->operands; op--;) |
| 3649 | if (t->operand_types[op].bitfield.xmmword |
| 3650 | && t->operand_types[op].bitfield.ymmword |
| 3651 | && i.types[op].bitfield.ymmword) |
| 3652 | { |
| 3653 | vector_length = 1; |
| 3654 | break; |
| 3655 | } |
| 3656 | } |
| 3657 | |
| 3658 | switch ((i.tm.base_opcode >> 8) & 0xff) |
| 3659 | { |
| 3660 | case 0: |
| 3661 | implied_prefix = 0; |
| 3662 | break; |
| 3663 | case DATA_PREFIX_OPCODE: |
| 3664 | implied_prefix = 1; |
| 3665 | break; |
| 3666 | case REPE_PREFIX_OPCODE: |
| 3667 | implied_prefix = 2; |
| 3668 | break; |
| 3669 | case REPNE_PREFIX_OPCODE: |
| 3670 | implied_prefix = 3; |
| 3671 | break; |
| 3672 | default: |
| 3673 | abort (); |
| 3674 | } |
| 3675 | |
| 3676 | /* Check the REX.W bit and VEXW. */ |
| 3677 | if (i.tm.opcode_modifier.vexw == VEXWIG) |
| 3678 | w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0; |
| 3679 | else if (i.tm.opcode_modifier.vexw) |
| 3680 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; |
| 3681 | else |
| 3682 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0; |
| 3683 | |
| 3684 | /* Use 2-byte VEX prefix if possible. */ |
| 3685 | if (w == 0 |
| 3686 | && i.vec_encoding != vex_encoding_vex3 |
| 3687 | && i.tm.opcode_modifier.vexopcode == VEX0F |
| 3688 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
| 3689 | { |
| 3690 | /* 2-byte VEX prefix. */ |
| 3691 | unsigned int r; |
| 3692 | |
| 3693 | i.vex.length = 2; |
| 3694 | i.vex.bytes[0] = 0xc5; |
| 3695 | |
| 3696 | /* Check the REX.R bit. */ |
| 3697 | r = (i.rex & REX_R) ? 0 : 1; |
| 3698 | i.vex.bytes[1] = (r << 7 |
| 3699 | | register_specifier << 3 |
| 3700 | | vector_length << 2 |
| 3701 | | implied_prefix); |
| 3702 | } |
| 3703 | else |
| 3704 | { |
| 3705 | /* 3-byte VEX prefix. */ |
| 3706 | unsigned int m; |
| 3707 | |
| 3708 | i.vex.length = 3; |
| 3709 | |
| 3710 | switch (i.tm.opcode_modifier.vexopcode) |
| 3711 | { |
| 3712 | case VEX0F: |
| 3713 | m = 0x1; |
| 3714 | i.vex.bytes[0] = 0xc4; |
| 3715 | break; |
| 3716 | case VEX0F38: |
| 3717 | m = 0x2; |
| 3718 | i.vex.bytes[0] = 0xc4; |
| 3719 | break; |
| 3720 | case VEX0F3A: |
| 3721 | m = 0x3; |
| 3722 | i.vex.bytes[0] = 0xc4; |
| 3723 | break; |
| 3724 | case XOP08: |
| 3725 | m = 0x8; |
| 3726 | i.vex.bytes[0] = 0x8f; |
| 3727 | break; |
| 3728 | case XOP09: |
| 3729 | m = 0x9; |
| 3730 | i.vex.bytes[0] = 0x8f; |
| 3731 | break; |
| 3732 | case XOP0A: |
| 3733 | m = 0xa; |
| 3734 | i.vex.bytes[0] = 0x8f; |
| 3735 | break; |
| 3736 | default: |
| 3737 | abort (); |
| 3738 | } |
| 3739 | |
| 3740 | /* The high 3 bits of the second VEX byte are 1's compliment |
| 3741 | of RXB bits from REX. */ |
| 3742 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; |
| 3743 | |
| 3744 | i.vex.bytes[2] = (w << 7 |
| 3745 | | register_specifier << 3 |
| 3746 | | vector_length << 2 |
| 3747 | | implied_prefix); |
| 3748 | } |
| 3749 | } |
| 3750 | |
| 3751 | static INLINE bfd_boolean |
| 3752 | is_evex_encoding (const insn_template *t) |
| 3753 | { |
| 3754 | return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift |
| 3755 | || t->opcode_modifier.broadcast || t->opcode_modifier.masking |
| 3756 | || t->opcode_modifier.sae; |
| 3757 | } |
| 3758 | |
| 3759 | static INLINE bfd_boolean |
| 3760 | is_any_vex_encoding (const insn_template *t) |
| 3761 | { |
| 3762 | return t->opcode_modifier.vex || t->opcode_modifier.vexopcode |
| 3763 | || is_evex_encoding (t); |
| 3764 | } |
| 3765 | |
| 3766 | /* Build the EVEX prefix. */ |
| 3767 | |
| 3768 | static void |
| 3769 | build_evex_prefix (void) |
| 3770 | { |
| 3771 | unsigned int register_specifier; |
| 3772 | unsigned int implied_prefix; |
| 3773 | unsigned int m, w; |
| 3774 | rex_byte vrex_used = 0; |
| 3775 | |
| 3776 | /* Check register specifier. */ |
| 3777 | if (i.vex.register_specifier) |
| 3778 | { |
| 3779 | gas_assert ((i.vrex & REX_X) == 0); |
| 3780 | |
| 3781 | register_specifier = i.vex.register_specifier->reg_num; |
| 3782 | if ((i.vex.register_specifier->reg_flags & RegRex)) |
| 3783 | register_specifier += 8; |
| 3784 | /* The upper 16 registers are encoded in the fourth byte of the |
| 3785 | EVEX prefix. */ |
| 3786 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) |
| 3787 | i.vex.bytes[3] = 0x8; |
| 3788 | register_specifier = ~register_specifier & 0xf; |
| 3789 | } |
| 3790 | else |
| 3791 | { |
| 3792 | register_specifier = 0xf; |
| 3793 | |
| 3794 | /* Encode upper 16 vector index register in the fourth byte of |
| 3795 | the EVEX prefix. */ |
| 3796 | if (!(i.vrex & REX_X)) |
| 3797 | i.vex.bytes[3] = 0x8; |
| 3798 | else |
| 3799 | vrex_used |= REX_X; |
| 3800 | } |
| 3801 | |
| 3802 | switch ((i.tm.base_opcode >> 8) & 0xff) |
| 3803 | { |
| 3804 | case 0: |
| 3805 | implied_prefix = 0; |
| 3806 | break; |
| 3807 | case DATA_PREFIX_OPCODE: |
| 3808 | implied_prefix = 1; |
| 3809 | break; |
| 3810 | case REPE_PREFIX_OPCODE: |
| 3811 | implied_prefix = 2; |
| 3812 | break; |
| 3813 | case REPNE_PREFIX_OPCODE: |
| 3814 | implied_prefix = 3; |
| 3815 | break; |
| 3816 | default: |
| 3817 | abort (); |
| 3818 | } |
| 3819 | |
| 3820 | /* 4 byte EVEX prefix. */ |
| 3821 | i.vex.length = 4; |
| 3822 | i.vex.bytes[0] = 0x62; |
| 3823 | |
| 3824 | /* mmmm bits. */ |
| 3825 | switch (i.tm.opcode_modifier.vexopcode) |
| 3826 | { |
| 3827 | case VEX0F: |
| 3828 | m = 1; |
| 3829 | break; |
| 3830 | case VEX0F38: |
| 3831 | m = 2; |
| 3832 | break; |
| 3833 | case VEX0F3A: |
| 3834 | m = 3; |
| 3835 | break; |
| 3836 | default: |
| 3837 | abort (); |
| 3838 | break; |
| 3839 | } |
| 3840 | |
| 3841 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB |
| 3842 | bits from REX. */ |
| 3843 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; |
| 3844 | |
| 3845 | /* The fifth bit of the second EVEX byte is 1's compliment of the |
| 3846 | REX_R bit in VREX. */ |
| 3847 | if (!(i.vrex & REX_R)) |
| 3848 | i.vex.bytes[1] |= 0x10; |
| 3849 | else |
| 3850 | vrex_used |= REX_R; |
| 3851 | |
| 3852 | if ((i.reg_operands + i.imm_operands) == i.operands) |
| 3853 | { |
| 3854 | /* When all operands are registers, the REX_X bit in REX is not |
| 3855 | used. We reuse it to encode the upper 16 registers, which is |
| 3856 | indicated by the REX_B bit in VREX. The REX_X bit is encoded |
| 3857 | as 1's compliment. */ |
| 3858 | if ((i.vrex & REX_B)) |
| 3859 | { |
| 3860 | vrex_used |= REX_B; |
| 3861 | i.vex.bytes[1] &= ~0x40; |
| 3862 | } |
| 3863 | } |
| 3864 | |
| 3865 | /* EVEX instructions shouldn't need the REX prefix. */ |
| 3866 | i.vrex &= ~vrex_used; |
| 3867 | gas_assert (i.vrex == 0); |
| 3868 | |
| 3869 | /* Check the REX.W bit and VEXW. */ |
| 3870 | if (i.tm.opcode_modifier.vexw == VEXWIG) |
| 3871 | w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0; |
| 3872 | else if (i.tm.opcode_modifier.vexw) |
| 3873 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; |
| 3874 | else |
| 3875 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0; |
| 3876 | |
| 3877 | /* Encode the U bit. */ |
| 3878 | implied_prefix |= 0x4; |
| 3879 | |
| 3880 | /* The third byte of the EVEX prefix. */ |
| 3881 | i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix); |
| 3882 | |
| 3883 | /* The fourth byte of the EVEX prefix. */ |
| 3884 | /* The zeroing-masking bit. */ |
| 3885 | if (i.mask && i.mask->zeroing) |
| 3886 | i.vex.bytes[3] |= 0x80; |
| 3887 | |
| 3888 | /* Don't always set the broadcast bit if there is no RC. */ |
| 3889 | if (!i.rounding) |
| 3890 | { |
| 3891 | /* Encode the vector length. */ |
| 3892 | unsigned int vec_length; |
| 3893 | |
| 3894 | if (!i.tm.opcode_modifier.evex |
| 3895 | || i.tm.opcode_modifier.evex == EVEXDYN) |
| 3896 | { |
| 3897 | unsigned int op; |
| 3898 | |
| 3899 | /* Determine vector length from the last multi-length vector |
| 3900 | operand. */ |
| 3901 | vec_length = 0; |
| 3902 | for (op = i.operands; op--;) |
| 3903 | if (i.tm.operand_types[op].bitfield.xmmword |
| 3904 | + i.tm.operand_types[op].bitfield.ymmword |
| 3905 | + i.tm.operand_types[op].bitfield.zmmword > 1) |
| 3906 | { |
| 3907 | if (i.types[op].bitfield.zmmword) |
| 3908 | { |
| 3909 | i.tm.opcode_modifier.evex = EVEX512; |
| 3910 | break; |
| 3911 | } |
| 3912 | else if (i.types[op].bitfield.ymmword) |
| 3913 | { |
| 3914 | i.tm.opcode_modifier.evex = EVEX256; |
| 3915 | break; |
| 3916 | } |
| 3917 | else if (i.types[op].bitfield.xmmword) |
| 3918 | { |
| 3919 | i.tm.opcode_modifier.evex = EVEX128; |
| 3920 | break; |
| 3921 | } |
| 3922 | else if (i.broadcast && (int) op == i.broadcast->operand) |
| 3923 | { |
| 3924 | switch (i.broadcast->bytes) |
| 3925 | { |
| 3926 | case 64: |
| 3927 | i.tm.opcode_modifier.evex = EVEX512; |
| 3928 | break; |
| 3929 | case 32: |
| 3930 | i.tm.opcode_modifier.evex = EVEX256; |
| 3931 | break; |
| 3932 | case 16: |
| 3933 | i.tm.opcode_modifier.evex = EVEX128; |
| 3934 | break; |
| 3935 | default: |
| 3936 | abort (); |
| 3937 | } |
| 3938 | break; |
| 3939 | } |
| 3940 | } |
| 3941 | |
| 3942 | if (op >= MAX_OPERANDS) |
| 3943 | abort (); |
| 3944 | } |
| 3945 | |
| 3946 | switch (i.tm.opcode_modifier.evex) |
| 3947 | { |
| 3948 | case EVEXLIG: /* LL' is ignored */ |
| 3949 | vec_length = evexlig << 5; |
| 3950 | break; |
| 3951 | case EVEX128: |
| 3952 | vec_length = 0 << 5; |
| 3953 | break; |
| 3954 | case EVEX256: |
| 3955 | vec_length = 1 << 5; |
| 3956 | break; |
| 3957 | case EVEX512: |
| 3958 | vec_length = 2 << 5; |
| 3959 | break; |
| 3960 | default: |
| 3961 | abort (); |
| 3962 | break; |
| 3963 | } |
| 3964 | i.vex.bytes[3] |= vec_length; |
| 3965 | /* Encode the broadcast bit. */ |
| 3966 | if (i.broadcast) |
| 3967 | i.vex.bytes[3] |= 0x10; |
| 3968 | } |
| 3969 | else |
| 3970 | { |
| 3971 | if (i.rounding->type != saeonly) |
| 3972 | i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5); |
| 3973 | else |
| 3974 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
| 3975 | } |
| 3976 | |
| 3977 | if (i.mask && i.mask->mask) |
| 3978 | i.vex.bytes[3] |= i.mask->mask->reg_num; |
| 3979 | } |
| 3980 | |
| 3981 | static void |
| 3982 | process_immext (void) |
| 3983 | { |
| 3984 | expressionS *exp; |
| 3985 | |
| 3986 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
| 3987 | which is coded in the same place as an 8-bit immediate field |
| 3988 | would be. Here we fake an 8-bit immediate operand from the |
| 3989 | opcode suffix stored in tm.extension_opcode. |
| 3990 | |
| 3991 | AVX instructions also use this encoding, for some of |
| 3992 | 3 argument instructions. */ |
| 3993 | |
| 3994 | gas_assert (i.imm_operands <= 1 |
| 3995 | && (i.operands <= 2 |
| 3996 | || (is_any_vex_encoding (&i.tm) |
| 3997 | && i.operands <= 4))); |
| 3998 | |
| 3999 | exp = &im_expressions[i.imm_operands++]; |
| 4000 | i.op[i.operands].imms = exp; |
| 4001 | i.types[i.operands] = imm8; |
| 4002 | i.operands++; |
| 4003 | exp->X_op = O_constant; |
| 4004 | exp->X_add_number = i.tm.extension_opcode; |
| 4005 | i.tm.extension_opcode = None; |
| 4006 | } |
| 4007 | |
| 4008 | |
| 4009 | static int |
| 4010 | check_hle (void) |
| 4011 | { |
| 4012 | switch (i.tm.opcode_modifier.hleprefixok) |
| 4013 | { |
| 4014 | default: |
| 4015 | abort (); |
| 4016 | case HLEPrefixNone: |
| 4017 | as_bad (_("invalid instruction `%s' after `%s'"), |
| 4018 | i.tm.name, i.hle_prefix); |
| 4019 | return 0; |
| 4020 | case HLEPrefixLock: |
| 4021 | if (i.prefix[LOCK_PREFIX]) |
| 4022 | return 1; |
| 4023 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
| 4024 | return 0; |
| 4025 | case HLEPrefixAny: |
| 4026 | return 1; |
| 4027 | case HLEPrefixRelease: |
| 4028 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
| 4029 | { |
| 4030 | as_bad (_("instruction `%s' after `xacquire' not allowed"), |
| 4031 | i.tm.name); |
| 4032 | return 0; |
| 4033 | } |
| 4034 | if (i.mem_operands == 0 || !(i.flags[i.operands - 1] & Operand_Mem)) |
| 4035 | { |
| 4036 | as_bad (_("memory destination needed for instruction `%s'" |
| 4037 | " after `xrelease'"), i.tm.name); |
| 4038 | return 0; |
| 4039 | } |
| 4040 | return 1; |
| 4041 | } |
| 4042 | } |
| 4043 | |
| 4044 | /* Try the shortest encoding by shortening operand size. */ |
| 4045 | |
| 4046 | static void |
| 4047 | optimize_encoding (void) |
| 4048 | { |
| 4049 | unsigned int j; |
| 4050 | |
| 4051 | if (optimize_for_space |
| 4052 | && !is_any_vex_encoding (&i.tm) |
| 4053 | && i.reg_operands == 1 |
| 4054 | && i.imm_operands == 1 |
| 4055 | && !i.types[1].bitfield.byte |
| 4056 | && i.op[0].imms->X_op == O_constant |
| 4057 | && fits_in_imm7 (i.op[0].imms->X_add_number) |
| 4058 | && (i.tm.base_opcode == 0xa8 |
| 4059 | || (i.tm.base_opcode == 0xf6 |
| 4060 | && i.tm.extension_opcode == 0x0))) |
| 4061 | { |
| 4062 | /* Optimize: -Os: |
| 4063 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 |
| 4064 | */ |
| 4065 | unsigned int base_regnum = i.op[1].regs->reg_num; |
| 4066 | if (flag_code == CODE_64BIT || base_regnum < 4) |
| 4067 | { |
| 4068 | i.types[1].bitfield.byte = 1; |
| 4069 | /* Ignore the suffix. */ |
| 4070 | i.suffix = 0; |
| 4071 | /* Convert to byte registers. */ |
| 4072 | if (i.types[1].bitfield.word) |
| 4073 | j = 16; |
| 4074 | else if (i.types[1].bitfield.dword) |
| 4075 | j = 32; |
| 4076 | else |
| 4077 | j = 48; |
| 4078 | if (!(i.op[1].regs->reg_flags & RegRex) && base_regnum < 4) |
| 4079 | j += 8; |
| 4080 | i.op[1].regs -= j; |
| 4081 | } |
| 4082 | } |
| 4083 | else if (flag_code == CODE_64BIT |
| 4084 | && !is_any_vex_encoding (&i.tm) |
| 4085 | && ((i.types[1].bitfield.qword |
| 4086 | && i.reg_operands == 1 |
| 4087 | && i.imm_operands == 1 |
| 4088 | && i.op[0].imms->X_op == O_constant |
| 4089 | && ((i.tm.base_opcode == 0xb8 |
| 4090 | && i.tm.extension_opcode == None |
| 4091 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) |
| 4092 | || (fits_in_imm31 (i.op[0].imms->X_add_number) |
| 4093 | && ((i.tm.base_opcode == 0x24 |
| 4094 | || i.tm.base_opcode == 0xa8) |
| 4095 | || (i.tm.base_opcode == 0x80 |
| 4096 | && i.tm.extension_opcode == 0x4) |
| 4097 | || ((i.tm.base_opcode == 0xf6 |
| 4098 | || (i.tm.base_opcode | 1) == 0xc7) |
| 4099 | && i.tm.extension_opcode == 0x0))) |
| 4100 | || (fits_in_imm7 (i.op[0].imms->X_add_number) |
| 4101 | && i.tm.base_opcode == 0x83 |
| 4102 | && i.tm.extension_opcode == 0x4))) |
| 4103 | || (i.types[0].bitfield.qword |
| 4104 | && ((i.reg_operands == 2 |
| 4105 | && i.op[0].regs == i.op[1].regs |
| 4106 | && (i.tm.base_opcode == 0x30 |
| 4107 | || i.tm.base_opcode == 0x28)) |
| 4108 | || (i.reg_operands == 1 |
| 4109 | && i.operands == 1 |
| 4110 | && i.tm.base_opcode == 0x30))))) |
| 4111 | { |
| 4112 | /* Optimize: -O: |
| 4113 | andq $imm31, %r64 -> andl $imm31, %r32 |
| 4114 | andq $imm7, %r64 -> andl $imm7, %r32 |
| 4115 | testq $imm31, %r64 -> testl $imm31, %r32 |
| 4116 | xorq %r64, %r64 -> xorl %r32, %r32 |
| 4117 | subq %r64, %r64 -> subl %r32, %r32 |
| 4118 | movq $imm31, %r64 -> movl $imm31, %r32 |
| 4119 | movq $imm32, %r64 -> movl $imm32, %r32 |
| 4120 | */ |
| 4121 | i.tm.opcode_modifier.norex64 = 1; |
| 4122 | if (i.tm.base_opcode == 0xb8 || (i.tm.base_opcode | 1) == 0xc7) |
| 4123 | { |
| 4124 | /* Handle |
| 4125 | movq $imm31, %r64 -> movl $imm31, %r32 |
| 4126 | movq $imm32, %r64 -> movl $imm32, %r32 |
| 4127 | */ |
| 4128 | i.tm.operand_types[0].bitfield.imm32 = 1; |
| 4129 | i.tm.operand_types[0].bitfield.imm32s = 0; |
| 4130 | i.tm.operand_types[0].bitfield.imm64 = 0; |
| 4131 | i.types[0].bitfield.imm32 = 1; |
| 4132 | i.types[0].bitfield.imm32s = 0; |
| 4133 | i.types[0].bitfield.imm64 = 0; |
| 4134 | i.types[1].bitfield.dword = 1; |
| 4135 | i.types[1].bitfield.qword = 0; |
| 4136 | if ((i.tm.base_opcode | 1) == 0xc7) |
| 4137 | { |
| 4138 | /* Handle |
| 4139 | movq $imm31, %r64 -> movl $imm31, %r32 |
| 4140 | */ |
| 4141 | i.tm.base_opcode = 0xb8; |
| 4142 | i.tm.extension_opcode = None; |
| 4143 | i.tm.opcode_modifier.w = 0; |
| 4144 | i.tm.opcode_modifier.modrm = 0; |
| 4145 | } |
| 4146 | } |
| 4147 | } |
| 4148 | else if (optimize > 1 |
| 4149 | && !optimize_for_space |
| 4150 | && !is_any_vex_encoding (&i.tm) |
| 4151 | && i.reg_operands == 2 |
| 4152 | && i.op[0].regs == i.op[1].regs |
| 4153 | && ((i.tm.base_opcode & ~(Opcode_D | 1)) == 0x8 |
| 4154 | || (i.tm.base_opcode & ~(Opcode_D | 1)) == 0x20) |
| 4155 | && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword)) |
| 4156 | { |
| 4157 | /* Optimize: -O2: |
| 4158 | andb %rN, %rN -> testb %rN, %rN |
| 4159 | andw %rN, %rN -> testw %rN, %rN |
| 4160 | andq %rN, %rN -> testq %rN, %rN |
| 4161 | orb %rN, %rN -> testb %rN, %rN |
| 4162 | orw %rN, %rN -> testw %rN, %rN |
| 4163 | orq %rN, %rN -> testq %rN, %rN |
| 4164 | |
| 4165 | and outside of 64-bit mode |
| 4166 | |
| 4167 | andl %rN, %rN -> testl %rN, %rN |
| 4168 | orl %rN, %rN -> testl %rN, %rN |
| 4169 | */ |
| 4170 | i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1); |
| 4171 | } |
| 4172 | else if (i.reg_operands == 3 |
| 4173 | && i.op[0].regs == i.op[1].regs |
| 4174 | && !i.types[2].bitfield.xmmword |
| 4175 | && (i.tm.opcode_modifier.vex |
| 4176 | || ((!i.mask || i.mask->zeroing) |
| 4177 | && !i.rounding |
| 4178 | && is_evex_encoding (&i.tm) |
| 4179 | && (i.vec_encoding != vex_encoding_evex |
| 4180 | || cpu_arch_isa_flags.bitfield.cpuavx512vl |
| 4181 | || i.tm.cpu_flags.bitfield.cpuavx512vl |
| 4182 | || (i.tm.operand_types[2].bitfield.zmmword |
| 4183 | && i.types[2].bitfield.ymmword)))) |
| 4184 | && ((i.tm.base_opcode == 0x55 |
| 4185 | || i.tm.base_opcode == 0x6655 |
| 4186 | || i.tm.base_opcode == 0x66df |
| 4187 | || i.tm.base_opcode == 0x57 |
| 4188 | || i.tm.base_opcode == 0x6657 |
| 4189 | || i.tm.base_opcode == 0x66ef |
| 4190 | || i.tm.base_opcode == 0x66f8 |
| 4191 | || i.tm.base_opcode == 0x66f9 |
| 4192 | || i.tm.base_opcode == 0x66fa |
| 4193 | || i.tm.base_opcode == 0x66fb |
| 4194 | || i.tm.base_opcode == 0x42 |
| 4195 | || i.tm.base_opcode == 0x6642 |
| 4196 | || i.tm.base_opcode == 0x47 |
| 4197 | || i.tm.base_opcode == 0x6647) |
| 4198 | && i.tm.extension_opcode == None)) |
| 4199 | { |
| 4200 | /* Optimize: -O1: |
| 4201 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
| 4202 | vpsubq and vpsubw: |
| 4203 | EVEX VOP %zmmM, %zmmM, %zmmN |
| 4204 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) |
| 4205 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
| 4206 | EVEX VOP %ymmM, %ymmM, %ymmN |
| 4207 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) |
| 4208 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
| 4209 | VEX VOP %ymmM, %ymmM, %ymmN |
| 4210 | -> VEX VOP %xmmM, %xmmM, %xmmN |
| 4211 | VOP, one of vpandn and vpxor: |
| 4212 | VEX VOP %ymmM, %ymmM, %ymmN |
| 4213 | -> VEX VOP %xmmM, %xmmM, %xmmN |
| 4214 | VOP, one of vpandnd and vpandnq: |
| 4215 | EVEX VOP %zmmM, %zmmM, %zmmN |
| 4216 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) |
| 4217 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
| 4218 | EVEX VOP %ymmM, %ymmM, %ymmN |
| 4219 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) |
| 4220 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
| 4221 | VOP, one of vpxord and vpxorq: |
| 4222 | EVEX VOP %zmmM, %zmmM, %zmmN |
| 4223 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) |
| 4224 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
| 4225 | EVEX VOP %ymmM, %ymmM, %ymmN |
| 4226 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) |
| 4227 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
| 4228 | VOP, one of kxord and kxorq: |
| 4229 | VEX VOP %kM, %kM, %kN |
| 4230 | -> VEX kxorw %kM, %kM, %kN |
| 4231 | VOP, one of kandnd and kandnq: |
| 4232 | VEX VOP %kM, %kM, %kN |
| 4233 | -> VEX kandnw %kM, %kM, %kN |
| 4234 | */ |
| 4235 | if (is_evex_encoding (&i.tm)) |
| 4236 | { |
| 4237 | if (i.vec_encoding != vex_encoding_evex) |
| 4238 | { |
| 4239 | i.tm.opcode_modifier.vex = VEX128; |
| 4240 | i.tm.opcode_modifier.vexw = VEXW0; |
| 4241 | i.tm.opcode_modifier.evex = 0; |
| 4242 | } |
| 4243 | else if (optimize > 1) |
| 4244 | i.tm.opcode_modifier.evex = EVEX128; |
| 4245 | else |
| 4246 | return; |
| 4247 | } |
| 4248 | else if (i.tm.operand_types[0].bitfield.class == RegMask) |
| 4249 | { |
| 4250 | i.tm.base_opcode &= 0xff; |
| 4251 | i.tm.opcode_modifier.vexw = VEXW0; |
| 4252 | } |
| 4253 | else |
| 4254 | i.tm.opcode_modifier.vex = VEX128; |
| 4255 | |
| 4256 | if (i.tm.opcode_modifier.vex) |
| 4257 | for (j = 0; j < 3; j++) |
| 4258 | { |
| 4259 | i.types[j].bitfield.xmmword = 1; |
| 4260 | i.types[j].bitfield.ymmword = 0; |
| 4261 | } |
| 4262 | } |
| 4263 | else if (i.vec_encoding != vex_encoding_evex |
| 4264 | && !i.types[0].bitfield.zmmword |
| 4265 | && !i.types[1].bitfield.zmmword |
| 4266 | && !i.mask |
| 4267 | && !i.broadcast |
| 4268 | && is_evex_encoding (&i.tm) |
| 4269 | && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x666f |
| 4270 | || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf36f |
| 4271 | || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f |
| 4272 | || (i.tm.base_opcode & ~4) == 0x66db |
| 4273 | || (i.tm.base_opcode & ~4) == 0x66eb) |
| 4274 | && i.tm.extension_opcode == None) |
| 4275 | { |
| 4276 | /* Optimize: -O1: |
| 4277 | VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, |
| 4278 | vmovdqu32 and vmovdqu64: |
| 4279 | EVEX VOP %xmmM, %xmmN |
| 4280 | -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16) |
| 4281 | EVEX VOP %ymmM, %ymmN |
| 4282 | -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16) |
| 4283 | EVEX VOP %xmmM, mem |
| 4284 | -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16) |
| 4285 | EVEX VOP %ymmM, mem |
| 4286 | -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16) |
| 4287 | EVEX VOP mem, %xmmN |
| 4288 | -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16) |
| 4289 | EVEX VOP mem, %ymmN |
| 4290 | -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16) |
| 4291 | VOP, one of vpand, vpandn, vpor, vpxor: |
| 4292 | EVEX VOP{d,q} %xmmL, %xmmM, %xmmN |
| 4293 | -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16) |
| 4294 | EVEX VOP{d,q} %ymmL, %ymmM, %ymmN |
| 4295 | -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16) |
| 4296 | EVEX VOP{d,q} mem, %xmmM, %xmmN |
| 4297 | -> VEX VOP mem, %xmmM, %xmmN (M and N < 16) |
| 4298 | EVEX VOP{d,q} mem, %ymmM, %ymmN |
| 4299 | -> VEX VOP mem, %ymmM, %ymmN (M and N < 16) |
| 4300 | */ |
| 4301 | for (j = 0; j < i.operands; j++) |
| 4302 | if (operand_type_check (i.types[j], disp) |
| 4303 | && i.op[j].disps->X_op == O_constant) |
| 4304 | { |
| 4305 | /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix |
| 4306 | has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4 |
| 4307 | bytes, we choose EVEX Disp8 over VEX Disp32. */ |
| 4308 | int evex_disp8, vex_disp8; |
| 4309 | unsigned int memshift = i.memshift; |
| 4310 | offsetT n = i.op[j].disps->X_add_number; |
| 4311 | |
| 4312 | evex_disp8 = fits_in_disp8 (n); |
| 4313 | i.memshift = 0; |
| 4314 | vex_disp8 = fits_in_disp8 (n); |
| 4315 | if (evex_disp8 != vex_disp8) |
| 4316 | { |
| 4317 | i.memshift = memshift; |
| 4318 | return; |
| 4319 | } |
| 4320 | |
| 4321 | i.types[j].bitfield.disp8 = vex_disp8; |
| 4322 | break; |
| 4323 | } |
| 4324 | if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f) |
| 4325 | i.tm.base_opcode ^= 0xf36f ^ 0xf26f; |
| 4326 | i.tm.opcode_modifier.vex |
| 4327 | = i.types[0].bitfield.ymmword ? VEX256 : VEX128; |
| 4328 | i.tm.opcode_modifier.vexw = VEXW0; |
| 4329 | /* VPAND, VPOR, and VPXOR are commutative. */ |
| 4330 | if (i.reg_operands == 3 && i.tm.base_opcode != 0x66df) |
| 4331 | i.tm.opcode_modifier.commutative = 1; |
| 4332 | i.tm.opcode_modifier.evex = 0; |
| 4333 | i.tm.opcode_modifier.masking = 0; |
| 4334 | i.tm.opcode_modifier.broadcast = 0; |
| 4335 | i.tm.opcode_modifier.disp8memshift = 0; |
| 4336 | i.memshift = 0; |
| 4337 | if (j < i.operands) |
| 4338 | i.types[j].bitfield.disp8 |
| 4339 | = fits_in_disp8 (i.op[j].disps->X_add_number); |
| 4340 | } |
| 4341 | } |
| 4342 | |
| 4343 | /* Return non-zero for load instruction. */ |
| 4344 | |
| 4345 | static int |
| 4346 | load_insn_p (void) |
| 4347 | { |
| 4348 | unsigned int dest; |
| 4349 | int any_vex_p = is_any_vex_encoding (&i.tm); |
| 4350 | unsigned int base_opcode = i.tm.base_opcode | 1; |
| 4351 | |
| 4352 | if (!any_vex_p) |
| 4353 | { |
| 4354 | /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0, |
| 4355 | prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn, |
| 4356 | bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */ |
| 4357 | if (i.tm.opcode_modifier.anysize) |
| 4358 | return 0; |
| 4359 | |
| 4360 | /* pop, popf, popa. */ |
| 4361 | if (strcmp (i.tm.name, "pop") == 0 |
| 4362 | || i.tm.base_opcode == 0x9d |
| 4363 | || i.tm.base_opcode == 0x61) |
| 4364 | return 1; |
| 4365 | |
| 4366 | /* movs, cmps, lods, scas. */ |
| 4367 | if ((i.tm.base_opcode | 0xb) == 0xaf) |
| 4368 | return 1; |
| 4369 | |
| 4370 | /* outs, xlatb. */ |
| 4371 | if (base_opcode == 0x6f |
| 4372 | || i.tm.base_opcode == 0xd7) |
| 4373 | return 1; |
| 4374 | /* NB: For AMD-specific insns with implicit memory operands, |
| 4375 | they're intentionally not covered. */ |
| 4376 | } |
| 4377 | |
| 4378 | /* No memory operand. */ |
| 4379 | if (!i.mem_operands) |
| 4380 | return 0; |
| 4381 | |
| 4382 | if (any_vex_p) |
| 4383 | { |
| 4384 | /* vldmxcsr. */ |
| 4385 | if (i.tm.base_opcode == 0xae |
| 4386 | && i.tm.opcode_modifier.vex |
| 4387 | && i.tm.opcode_modifier.vexopcode == VEX0F |
| 4388 | && i.tm.extension_opcode == 2) |
| 4389 | return 1; |
| 4390 | } |
| 4391 | else |
| 4392 | { |
| 4393 | /* test, not, neg, mul, imul, div, idiv. */ |
| 4394 | if ((i.tm.base_opcode == 0xf6 || i.tm.base_opcode == 0xf7) |
| 4395 | && i.tm.extension_opcode != 1) |
| 4396 | return 1; |
| 4397 | |
| 4398 | /* inc, dec. */ |
| 4399 | if (base_opcode == 0xff && i.tm.extension_opcode <= 1) |
| 4400 | return 1; |
| 4401 | |
| 4402 | /* add, or, adc, sbb, and, sub, xor, cmp. */ |
| 4403 | if (i.tm.base_opcode >= 0x80 && i.tm.base_opcode <= 0x83) |
| 4404 | return 1; |
| 4405 | |
| 4406 | /* bt, bts, btr, btc. */ |
| 4407 | if (i.tm.base_opcode == 0xfba |
| 4408 | && (i.tm.extension_opcode >= 4 && i.tm.extension_opcode <= 7)) |
| 4409 | return 1; |
| 4410 | |
| 4411 | /* rol, ror, rcl, rcr, shl/sal, shr, sar. */ |
| 4412 | if ((base_opcode == 0xc1 |
| 4413 | || (i.tm.base_opcode >= 0xd0 && i.tm.base_opcode <= 0xd3)) |
| 4414 | && i.tm.extension_opcode != 6) |
| 4415 | return 1; |
| 4416 | |
| 4417 | /* cmpxchg8b, cmpxchg16b, xrstors. */ |
| 4418 | if (i.tm.base_opcode == 0xfc7 |
| 4419 | && (i.tm.extension_opcode == 1 || i.tm.extension_opcode == 3)) |
| 4420 | return 1; |
| 4421 | |
| 4422 | /* fxrstor, ldmxcsr, xrstor. */ |
| 4423 | if (i.tm.base_opcode == 0xfae |
| 4424 | && (i.tm.extension_opcode == 1 |
| 4425 | || i.tm.extension_opcode == 2 |
| 4426 | || i.tm.extension_opcode == 5)) |
| 4427 | return 1; |
| 4428 | |
| 4429 | /* lgdt, lidt, lmsw. */ |
| 4430 | if (i.tm.base_opcode == 0xf01 |
| 4431 | && (i.tm.extension_opcode == 2 |
| 4432 | || i.tm.extension_opcode == 3 |
| 4433 | || i.tm.extension_opcode == 6)) |
| 4434 | return 1; |
| 4435 | |
| 4436 | /* vmptrld */ |
| 4437 | if (i.tm.base_opcode == 0xfc7 |
| 4438 | && i.tm.extension_opcode == 6) |
| 4439 | return 1; |
| 4440 | |
| 4441 | /* Check for x87 instructions. */ |
| 4442 | if (i.tm.base_opcode >= 0xd8 && i.tm.base_opcode <= 0xdf) |
| 4443 | { |
| 4444 | /* Skip fst, fstp, fstenv, fstcw. */ |
| 4445 | if (i.tm.base_opcode == 0xd9 |
| 4446 | && (i.tm.extension_opcode == 2 |
| 4447 | || i.tm.extension_opcode == 3 |
| 4448 | || i.tm.extension_opcode == 6 |
| 4449 | || i.tm.extension_opcode == 7)) |
| 4450 | return 0; |
| 4451 | |
| 4452 | /* Skip fisttp, fist, fistp, fstp. */ |
| 4453 | if (i.tm.base_opcode == 0xdb |
| 4454 | && (i.tm.extension_opcode == 1 |
| 4455 | || i.tm.extension_opcode == 2 |
| 4456 | || i.tm.extension_opcode == 3 |
| 4457 | || i.tm.extension_opcode == 7)) |
| 4458 | return 0; |
| 4459 | |
| 4460 | /* Skip fisttp, fst, fstp, fsave, fstsw. */ |
| 4461 | if (i.tm.base_opcode == 0xdd |
| 4462 | && (i.tm.extension_opcode == 1 |
| 4463 | || i.tm.extension_opcode == 2 |
| 4464 | || i.tm.extension_opcode == 3 |
| 4465 | || i.tm.extension_opcode == 6 |
| 4466 | || i.tm.extension_opcode == 7)) |
| 4467 | return 0; |
| 4468 | |
| 4469 | /* Skip fisttp, fist, fistp, fbstp, fistp. */ |
| 4470 | if (i.tm.base_opcode == 0xdf |
| 4471 | && (i.tm.extension_opcode == 1 |
| 4472 | || i.tm.extension_opcode == 2 |
| 4473 | || i.tm.extension_opcode == 3 |
| 4474 | || i.tm.extension_opcode == 6 |
| 4475 | || i.tm.extension_opcode == 7)) |
| 4476 | return 0; |
| 4477 | |
| 4478 | return 1; |
| 4479 | } |
| 4480 | } |
| 4481 | |
| 4482 | dest = i.operands - 1; |
| 4483 | |
| 4484 | /* Check fake imm8 operand and 3 source operands. */ |
| 4485 | if ((i.tm.opcode_modifier.immext |
| 4486 | || i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
| 4487 | && i.types[dest].bitfield.imm8) |
| 4488 | dest--; |
| 4489 | |
| 4490 | /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */ |
| 4491 | if (!any_vex_p |
| 4492 | && (base_opcode == 0x1 |
| 4493 | || base_opcode == 0x9 |
| 4494 | || base_opcode == 0x11 |
| 4495 | || base_opcode == 0x19 |
| 4496 | || base_opcode == 0x21 |
| 4497 | || base_opcode == 0x29 |
| 4498 | || base_opcode == 0x31 |
| 4499 | || base_opcode == 0x39 |
| 4500 | || (i.tm.base_opcode >= 0x84 && i.tm.base_opcode <= 0x87) |
| 4501 | || base_opcode == 0xfc1)) |
| 4502 | return 1; |
| 4503 | |
| 4504 | /* Check for load instruction. */ |
| 4505 | return (i.types[dest].bitfield.class != ClassNone |
| 4506 | || i.types[dest].bitfield.instance == Accum); |
| 4507 | } |
| 4508 | |
| 4509 | /* Output lfence, 0xfaee8, after instruction. */ |
| 4510 | |
| 4511 | static void |
| 4512 | insert_lfence_after (void) |
| 4513 | { |
| 4514 | if (lfence_after_load && load_insn_p ()) |
| 4515 | { |
| 4516 | /* There are also two REP string instructions that require |
| 4517 | special treatment. Specifically, the compare string (CMPS) |
| 4518 | and scan string (SCAS) instructions set EFLAGS in a manner |
| 4519 | that depends on the data being compared/scanned. When used |
| 4520 | with a REP prefix, the number of iterations may therefore |
| 4521 | vary depending on this data. If the data is a program secret |
| 4522 | chosen by the adversary using an LVI method, |
| 4523 | then this data-dependent behavior may leak some aspect |
| 4524 | of the secret. */ |
| 4525 | if (((i.tm.base_opcode | 0x1) == 0xa7 |
| 4526 | || (i.tm.base_opcode | 0x1) == 0xaf) |
| 4527 | && i.prefix[REP_PREFIX]) |
| 4528 | { |
| 4529 | as_warn (_("`%s` changes flags which would affect control flow behavior"), |
| 4530 | i.tm.name); |
| 4531 | } |
| 4532 | char *p = frag_more (3); |
| 4533 | *p++ = 0xf; |
| 4534 | *p++ = 0xae; |
| 4535 | *p = 0xe8; |
| 4536 | } |
| 4537 | } |
| 4538 | |
| 4539 | /* Output lfence, 0xfaee8, before instruction. */ |
| 4540 | |
| 4541 | static void |
| 4542 | insert_lfence_before (void) |
| 4543 | { |
| 4544 | char *p; |
| 4545 | |
| 4546 | if (is_any_vex_encoding (&i.tm)) |
| 4547 | return; |
| 4548 | |
| 4549 | if (i.tm.base_opcode == 0xff |
| 4550 | && (i.tm.extension_opcode == 2 || i.tm.extension_opcode == 4)) |
| 4551 | { |
| 4552 | /* Insert lfence before indirect branch if needed. */ |
| 4553 | |
| 4554 | if (lfence_before_indirect_branch == lfence_branch_none) |
| 4555 | return; |
| 4556 | |
| 4557 | if (i.operands != 1) |
| 4558 | abort (); |
| 4559 | |
| 4560 | if (i.reg_operands == 1) |
| 4561 | { |
| 4562 | /* Indirect branch via register. Don't insert lfence with |
| 4563 | -mlfence-after-load=yes. */ |
| 4564 | if (lfence_after_load |
| 4565 | || lfence_before_indirect_branch == lfence_branch_memory) |
| 4566 | return; |
| 4567 | } |
| 4568 | else if (i.mem_operands == 1 |
| 4569 | && lfence_before_indirect_branch != lfence_branch_register) |
| 4570 | { |
| 4571 | as_warn (_("indirect `%s` with memory operand should be avoided"), |
| 4572 | i.tm.name); |
| 4573 | return; |
| 4574 | } |
| 4575 | else |
| 4576 | return; |
| 4577 | |
| 4578 | if (last_insn.kind != last_insn_other |
| 4579 | && last_insn.seg == now_seg) |
| 4580 | { |
| 4581 | as_warn_where (last_insn.file, last_insn.line, |
| 4582 | _("`%s` skips -mlfence-before-indirect-branch on `%s`"), |
| 4583 | last_insn.name, i.tm.name); |
| 4584 | return; |
| 4585 | } |
| 4586 | |
| 4587 | p = frag_more (3); |
| 4588 | *p++ = 0xf; |
| 4589 | *p++ = 0xae; |
| 4590 | *p = 0xe8; |
| 4591 | return; |
| 4592 | } |
| 4593 | |
| 4594 | /* Output or/not/shl and lfence before ret/lret/iret. */ |
| 4595 | if (lfence_before_ret != lfence_before_ret_none |
| 4596 | && (i.tm.base_opcode == 0xc2 |
| 4597 | || i.tm.base_opcode == 0xc3 |
| 4598 | || i.tm.base_opcode == 0xca |
| 4599 | || i.tm.base_opcode == 0xcb |
| 4600 | || i.tm.base_opcode == 0xcf)) |
| 4601 | { |
| 4602 | if (last_insn.kind != last_insn_other |
| 4603 | && last_insn.seg == now_seg) |
| 4604 | { |
| 4605 | as_warn_where (last_insn.file, last_insn.line, |
| 4606 | _("`%s` skips -mlfence-before-ret on `%s`"), |
| 4607 | last_insn.name, i.tm.name); |
| 4608 | return; |
| 4609 | } |
| 4610 | |
| 4611 | /* lret or iret. */ |
| 4612 | bfd_boolean lret = (i.tm.base_opcode | 0x5) == 0xcf; |
| 4613 | bfd_boolean has_rexw = i.prefix[REX_PREFIX] & REX_W; |
| 4614 | char prefix = 0x0; |
| 4615 | /* Default operand size for far return is 32 bits, |
| 4616 | 64 bits for near return. */ |
| 4617 | /* Near ret ingore operand size override under CPU64. */ |
| 4618 | if ((!lret && flag_code == CODE_64BIT) || has_rexw) |
| 4619 | prefix = 0x48; |
| 4620 | else if (i.prefix[DATA_PREFIX]) |
| 4621 | prefix = 0x66; |
| 4622 | |
| 4623 | if (lfence_before_ret == lfence_before_ret_not) |
| 4624 | { |
| 4625 | /* not: 0xf71424, may add prefix |
| 4626 | for operand size override or 64-bit code. */ |
| 4627 | p = frag_more ((prefix ? 2 : 0) + 6 + 3); |
| 4628 | if (prefix) |
| 4629 | *p++ = prefix; |
| 4630 | *p++ = 0xf7; |
| 4631 | *p++ = 0x14; |
| 4632 | *p++ = 0x24; |
| 4633 | if (prefix) |
| 4634 | *p++ = prefix; |
| 4635 | *p++ = 0xf7; |
| 4636 | *p++ = 0x14; |
| 4637 | *p++ = 0x24; |
| 4638 | } |
| 4639 | else |
| 4640 | { |
| 4641 | p = frag_more ((prefix ? 1 : 0) + 4 + 3); |
| 4642 | if (prefix) |
| 4643 | *p++ = prefix; |
| 4644 | if (lfence_before_ret == lfence_before_ret_or) |
| 4645 | { |
| 4646 | /* or: 0x830c2400, may add prefix |
| 4647 | for operand size override or 64-bit code. */ |
| 4648 | *p++ = 0x83; |
| 4649 | *p++ = 0x0c; |
| 4650 | } |
| 4651 | else |
| 4652 | { |
| 4653 | /* shl: 0xc1242400, may add prefix |
| 4654 | for operand size override or 64-bit code. */ |
| 4655 | *p++ = 0xc1; |
| 4656 | *p++ = 0x24; |
| 4657 | } |
| 4658 | |
| 4659 | *p++ = 0x24; |
| 4660 | *p++ = 0x0; |
| 4661 | } |
| 4662 | |
| 4663 | *p++ = 0xf; |
| 4664 | *p++ = 0xae; |
| 4665 | *p = 0xe8; |
| 4666 | } |
| 4667 | } |
| 4668 | |
| 4669 | /* This is the guts of the machine-dependent assembler. LINE points to a |
| 4670 | machine dependent instruction. This function is supposed to emit |
| 4671 | the frags/bytes it assembles to. */ |
| 4672 | |
| 4673 | void |
| 4674 | md_assemble (char *line) |
| 4675 | { |
| 4676 | unsigned int j; |
| 4677 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix; |
| 4678 | const insn_template *t; |
| 4679 | |
| 4680 | /* Initialize globals. */ |
| 4681 | memset (&i, '\0', sizeof (i)); |
| 4682 | for (j = 0; j < MAX_OPERANDS; j++) |
| 4683 | i.reloc[j] = NO_RELOC; |
| 4684 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
| 4685 | memset (im_expressions, '\0', sizeof (im_expressions)); |
| 4686 | save_stack_p = save_stack; |
| 4687 | |
| 4688 | /* First parse an instruction mnemonic & call i386_operand for the operands. |
| 4689 | We assume that the scrubber has arranged it so that line[0] is the valid |
| 4690 | start of a (possibly prefixed) mnemonic. */ |
| 4691 | |
| 4692 | line = parse_insn (line, mnemonic); |
| 4693 | if (line == NULL) |
| 4694 | return; |
| 4695 | mnem_suffix = i.suffix; |
| 4696 | |
| 4697 | line = parse_operands (line, mnemonic); |
| 4698 | this_operand = -1; |
| 4699 | xfree (i.memop1_string); |
| 4700 | i.memop1_string = NULL; |
| 4701 | if (line == NULL) |
| 4702 | return; |
| 4703 | |
| 4704 | /* Now we've parsed the mnemonic into a set of templates, and have the |
| 4705 | operands at hand. */ |
| 4706 | |
| 4707 | /* All Intel opcodes have reversed operands except for "bound", "enter", |
| 4708 | "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse |
| 4709 | intersegment "jmp" and "call" instructions with 2 immediate operands so |
| 4710 | that the immediate segment precedes the offset, as it does when in AT&T |
| 4711 | mode. */ |
| 4712 | if (intel_syntax |
| 4713 | && i.operands > 1 |
| 4714 | && (strcmp (mnemonic, "bound") != 0) |
| 4715 | && (strcmp (mnemonic, "invlpga") != 0) |
| 4716 | && (strncmp (mnemonic, "monitor", 7) != 0) |
| 4717 | && (strncmp (mnemonic, "mwait", 5) != 0) |
| 4718 | && (strcmp (mnemonic, "tpause") != 0) |
| 4719 | && (strcmp (mnemonic, "umwait") != 0) |
| 4720 | && !(operand_type_check (i.types[0], imm) |
| 4721 | && operand_type_check (i.types[1], imm))) |
| 4722 | swap_operands (); |
| 4723 | |
| 4724 | /* The order of the immediates should be reversed |
| 4725 | for 2 immediates extrq and insertq instructions */ |
| 4726 | if (i.imm_operands == 2 |
| 4727 | && (strcmp (mnemonic, "extrq") == 0 |
| 4728 | || strcmp (mnemonic, "insertq") == 0)) |
| 4729 | swap_2_operands (0, 1); |
| 4730 | |
| 4731 | if (i.imm_operands) |
| 4732 | optimize_imm (); |
| 4733 | |
| 4734 | /* Don't optimize displacement for movabs since it only takes 64bit |
| 4735 | displacement. */ |
| 4736 | if (i.disp_operands |
| 4737 | && i.disp_encoding != disp_encoding_32bit |
| 4738 | && (flag_code != CODE_64BIT |
| 4739 | || strcmp (mnemonic, "movabs") != 0)) |
| 4740 | optimize_disp (); |
| 4741 | |
| 4742 | /* Next, we find a template that matches the given insn, |
| 4743 | making sure the overlap of the given operands types is consistent |
| 4744 | with the template operand types. */ |
| 4745 | |
| 4746 | if (!(t = match_template (mnem_suffix))) |
| 4747 | return; |
| 4748 | |
| 4749 | if (sse_check != check_none |
| 4750 | && !i.tm.opcode_modifier.noavx |
| 4751 | && !i.tm.cpu_flags.bitfield.cpuavx |
| 4752 | && !i.tm.cpu_flags.bitfield.cpuavx512f |
| 4753 | && (i.tm.cpu_flags.bitfield.cpusse |
| 4754 | || i.tm.cpu_flags.bitfield.cpusse2 |
| 4755 | || i.tm.cpu_flags.bitfield.cpusse3 |
| 4756 | || i.tm.cpu_flags.bitfield.cpussse3 |
| 4757 | || i.tm.cpu_flags.bitfield.cpusse4_1 |
| 4758 | || i.tm.cpu_flags.bitfield.cpusse4_2 |
| 4759 | || i.tm.cpu_flags.bitfield.cpusse4a |
| 4760 | || i.tm.cpu_flags.bitfield.cpupclmul |
| 4761 | || i.tm.cpu_flags.bitfield.cpuaes |
| 4762 | || i.tm.cpu_flags.bitfield.cpusha |
| 4763 | || i.tm.cpu_flags.bitfield.cpugfni)) |
| 4764 | { |
| 4765 | (sse_check == check_warning |
| 4766 | ? as_warn |
| 4767 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); |
| 4768 | } |
| 4769 | |
| 4770 | if (i.tm.opcode_modifier.fwait) |
| 4771 | if (!add_prefix (FWAIT_OPCODE)) |
| 4772 | return; |
| 4773 | |
| 4774 | /* Check if REP prefix is OK. */ |
| 4775 | if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok) |
| 4776 | { |
| 4777 | as_bad (_("invalid instruction `%s' after `%s'"), |
| 4778 | i.tm.name, i.rep_prefix); |
| 4779 | return; |
| 4780 | } |
| 4781 | |
| 4782 | /* Check for lock without a lockable instruction. Destination operand |
| 4783 | must be memory unless it is xchg (0x86). */ |
| 4784 | if (i.prefix[LOCK_PREFIX] |
| 4785 | && (!i.tm.opcode_modifier.islockable |
| 4786 | || i.mem_operands == 0 |
| 4787 | || (i.tm.base_opcode != 0x86 |
| 4788 | && !(i.flags[i.operands - 1] & Operand_Mem)))) |
| 4789 | { |
| 4790 | as_bad (_("expecting lockable instruction after `lock'")); |
| 4791 | return; |
| 4792 | } |
| 4793 | |
| 4794 | /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */ |
| 4795 | if (i.prefix[DATA_PREFIX] && is_any_vex_encoding (&i.tm)) |
| 4796 | { |
| 4797 | as_bad (_("data size prefix invalid with `%s'"), i.tm.name); |
| 4798 | return; |
| 4799 | } |
| 4800 | |
| 4801 | /* Check if HLE prefix is OK. */ |
| 4802 | if (i.hle_prefix && !check_hle ()) |
| 4803 | return; |
| 4804 | |
| 4805 | /* Check BND prefix. */ |
| 4806 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) |
| 4807 | as_bad (_("expecting valid branch instruction after `bnd'")); |
| 4808 | |
| 4809 | /* Check NOTRACK prefix. */ |
| 4810 | if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok) |
| 4811 | as_bad (_("expecting indirect branch instruction after `notrack'")); |
| 4812 | |
| 4813 | if (i.tm.cpu_flags.bitfield.cpumpx) |
| 4814 | { |
| 4815 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) |
| 4816 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); |
| 4817 | else if (flag_code != CODE_16BIT |
| 4818 | ? i.prefix[ADDR_PREFIX] |
| 4819 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) |
| 4820 | as_bad (_("16-bit address isn't allowed in MPX instructions")); |
| 4821 | } |
| 4822 | |
| 4823 | /* Insert BND prefix. */ |
| 4824 | if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok) |
| 4825 | { |
| 4826 | if (!i.prefix[BND_PREFIX]) |
| 4827 | add_prefix (BND_PREFIX_OPCODE); |
| 4828 | else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE) |
| 4829 | { |
| 4830 | as_warn (_("replacing `rep'/`repe' prefix by `bnd'")); |
| 4831 | i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE; |
| 4832 | } |
| 4833 | } |
| 4834 | |
| 4835 | /* Check string instruction segment overrides. */ |
| 4836 | if (i.tm.opcode_modifier.isstring >= IS_STRING_ES_OP0) |
| 4837 | { |
| 4838 | gas_assert (i.mem_operands); |
| 4839 | if (!check_string ()) |
| 4840 | return; |
| 4841 | i.disp_operands = 0; |
| 4842 | } |
| 4843 | |
| 4844 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
| 4845 | optimize_encoding (); |
| 4846 | |
| 4847 | if (!process_suffix ()) |
| 4848 | return; |
| 4849 | |
| 4850 | /* Update operand types. */ |
| 4851 | for (j = 0; j < i.operands; j++) |
| 4852 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); |
| 4853 | |
| 4854 | /* Make still unresolved immediate matches conform to size of immediate |
| 4855 | given in i.suffix. */ |
| 4856 | if (!finalize_imm ()) |
| 4857 | return; |
| 4858 | |
| 4859 | if (i.types[0].bitfield.imm1) |
| 4860 | i.imm_operands = 0; /* kludge for shift insns. */ |
| 4861 | |
| 4862 | /* We only need to check those implicit registers for instructions |
| 4863 | with 3 operands or less. */ |
| 4864 | if (i.operands <= 3) |
| 4865 | for (j = 0; j < i.operands; j++) |
| 4866 | if (i.types[j].bitfield.instance != InstanceNone |
| 4867 | && !i.types[j].bitfield.xmmword) |
| 4868 | i.reg_operands--; |
| 4869 | |
| 4870 | /* ImmExt should be processed after SSE2AVX. */ |
| 4871 | if (!i.tm.opcode_modifier.sse2avx |
| 4872 | && i.tm.opcode_modifier.immext) |
| 4873 | process_immext (); |
| 4874 | |
| 4875 | /* For insns with operands there are more diddles to do to the opcode. */ |
| 4876 | if (i.operands) |
| 4877 | { |
| 4878 | if (!process_operands ()) |
| 4879 | return; |
| 4880 | } |
| 4881 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
| 4882 | { |
| 4883 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ |
| 4884 | as_warn (_("translating to `%sp'"), i.tm.name); |
| 4885 | } |
| 4886 | |
| 4887 | if (is_any_vex_encoding (&i.tm)) |
| 4888 | { |
| 4889 | if (!cpu_arch_flags.bitfield.cpui286) |
| 4890 | { |
| 4891 | as_bad (_("instruction `%s' isn't supported outside of protected mode."), |
| 4892 | i.tm.name); |
| 4893 | return; |
| 4894 | } |
| 4895 | |
| 4896 | if (i.tm.opcode_modifier.vex) |
| 4897 | build_vex_prefix (t); |
| 4898 | else |
| 4899 | build_evex_prefix (); |
| 4900 | } |
| 4901 | |
| 4902 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
| 4903 | instructions may define INT_OPCODE as well, so avoid this corner |
| 4904 | case for those instructions that use MODRM. */ |
| 4905 | if (i.tm.base_opcode == INT_OPCODE |
| 4906 | && !i.tm.opcode_modifier.modrm |
| 4907 | && i.op[0].imms->X_add_number == 3) |
| 4908 | { |
| 4909 | i.tm.base_opcode = INT3_OPCODE; |
| 4910 | i.imm_operands = 0; |
| 4911 | } |
| 4912 | |
| 4913 | if ((i.tm.opcode_modifier.jump == JUMP |
| 4914 | || i.tm.opcode_modifier.jump == JUMP_BYTE |
| 4915 | || i.tm.opcode_modifier.jump == JUMP_DWORD) |
| 4916 | && i.op[0].disps->X_op == O_constant) |
| 4917 | { |
| 4918 | /* Convert "jmp constant" (and "call constant") to a jump (call) to |
| 4919 | the absolute address given by the constant. Since ix86 jumps and |
| 4920 | calls are pc relative, we need to generate a reloc. */ |
| 4921 | i.op[0].disps->X_add_symbol = &abs_symbol; |
| 4922 | i.op[0].disps->X_op = O_symbol; |
| 4923 | } |
| 4924 | |
| 4925 | /* For 8 bit registers we need an empty rex prefix. Also if the |
| 4926 | instruction already has a prefix, we need to convert old |
| 4927 | registers to new ones. */ |
| 4928 | |
| 4929 | if ((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte |
| 4930 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
| 4931 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte |
| 4932 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
| 4933 | || (((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte) |
| 4934 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte)) |
| 4935 | && i.rex != 0)) |
| 4936 | { |
| 4937 | int x; |
| 4938 | |
| 4939 | i.rex |= REX_OPCODE; |
| 4940 | for (x = 0; x < 2; x++) |
| 4941 | { |
| 4942 | /* Look for 8 bit operand that uses old registers. */ |
| 4943 | if (i.types[x].bitfield.class == Reg && i.types[x].bitfield.byte |
| 4944 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
| 4945 | { |
| 4946 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
| 4947 | /* In case it is "hi" register, give up. */ |
| 4948 | if (i.op[x].regs->reg_num > 3) |
| 4949 | as_bad (_("can't encode register '%s%s' in an " |
| 4950 | "instruction requiring REX prefix."), |
| 4951 | register_prefix, i.op[x].regs->reg_name); |
| 4952 | |
| 4953 | /* Otherwise it is equivalent to the extended register. |
| 4954 | Since the encoding doesn't change this is merely |
| 4955 | cosmetic cleanup for debug output. */ |
| 4956 | |
| 4957 | i.op[x].regs = i.op[x].regs + 8; |
| 4958 | } |
| 4959 | } |
| 4960 | } |
| 4961 | |
| 4962 | if (i.rex == 0 && i.rex_encoding) |
| 4963 | { |
| 4964 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand |
| 4965 | that uses legacy register. If it is "hi" register, don't add |
| 4966 | the REX_OPCODE byte. */ |
| 4967 | int x; |
| 4968 | for (x = 0; x < 2; x++) |
| 4969 | if (i.types[x].bitfield.class == Reg |
| 4970 | && i.types[x].bitfield.byte |
| 4971 | && (i.op[x].regs->reg_flags & RegRex64) == 0 |
| 4972 | && i.op[x].regs->reg_num > 3) |
| 4973 | { |
| 4974 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
| 4975 | i.rex_encoding = FALSE; |
| 4976 | break; |
| 4977 | } |
| 4978 | |
| 4979 | if (i.rex_encoding) |
| 4980 | i.rex = REX_OPCODE; |
| 4981 | } |
| 4982 | |
| 4983 | if (i.rex != 0) |
| 4984 | add_prefix (REX_OPCODE | i.rex); |
| 4985 | |
| 4986 | insert_lfence_before (); |
| 4987 | |
| 4988 | /* We are ready to output the insn. */ |
| 4989 | output_insn (); |
| 4990 | |
| 4991 | insert_lfence_after (); |
| 4992 | |
| 4993 | last_insn.seg = now_seg; |
| 4994 | |
| 4995 | if (i.tm.opcode_modifier.isprefix) |
| 4996 | { |
| 4997 | last_insn.kind = last_insn_prefix; |
| 4998 | last_insn.name = i.tm.name; |
| 4999 | last_insn.file = as_where (&last_insn.line); |
| 5000 | } |
| 5001 | else |
| 5002 | last_insn.kind = last_insn_other; |
| 5003 | } |
| 5004 | |
| 5005 | static char * |
| 5006 | parse_insn (char *line, char *mnemonic) |
| 5007 | { |
| 5008 | char *l = line; |
| 5009 | char *token_start = l; |
| 5010 | char *mnem_p; |
| 5011 | int supported; |
| 5012 | const insn_template *t; |
| 5013 | char *dot_p = NULL; |
| 5014 | |
| 5015 | while (1) |
| 5016 | { |
| 5017 | mnem_p = mnemonic; |
| 5018 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) |
| 5019 | { |
| 5020 | if (*mnem_p == '.') |
| 5021 | dot_p = mnem_p; |
| 5022 | mnem_p++; |
| 5023 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) |
| 5024 | { |
| 5025 | as_bad (_("no such instruction: `%s'"), token_start); |
| 5026 | return NULL; |
| 5027 | } |
| 5028 | l++; |
| 5029 | } |
| 5030 | if (!is_space_char (*l) |
| 5031 | && *l != END_OF_INSN |
| 5032 | && (intel_syntax |
| 5033 | || (*l != PREFIX_SEPARATOR |
| 5034 | && *l != ','))) |
| 5035 | { |
| 5036 | as_bad (_("invalid character %s in mnemonic"), |
| 5037 | output_invalid (*l)); |
| 5038 | return NULL; |
| 5039 | } |
| 5040 | if (token_start == l) |
| 5041 | { |
| 5042 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
| 5043 | as_bad (_("expecting prefix; got nothing")); |
| 5044 | else |
| 5045 | as_bad (_("expecting mnemonic; got nothing")); |
| 5046 | return NULL; |
| 5047 | } |
| 5048 | |
| 5049 | /* Look up instruction (or prefix) via hash table. */ |
| 5050 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
| 5051 | |
| 5052 | if (*l != END_OF_INSN |
| 5053 | && (!is_space_char (*l) || l[1] != END_OF_INSN) |
| 5054 | && current_templates |
| 5055 | && current_templates->start->opcode_modifier.isprefix) |
| 5056 | { |
| 5057 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
| 5058 | { |
| 5059 | as_bad ((flag_code != CODE_64BIT |
| 5060 | ? _("`%s' is only supported in 64-bit mode") |
| 5061 | : _("`%s' is not supported in 64-bit mode")), |
| 5062 | current_templates->start->name); |
| 5063 | return NULL; |
| 5064 | } |
| 5065 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
| 5066 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ |
| 5067 | if ((current_templates->start->opcode_modifier.size == SIZE16 |
| 5068 | || current_templates->start->opcode_modifier.size == SIZE32) |
| 5069 | && flag_code != CODE_64BIT |
| 5070 | && ((current_templates->start->opcode_modifier.size == SIZE32) |
| 5071 | ^ (flag_code == CODE_16BIT))) |
| 5072 | { |
| 5073 | as_bad (_("redundant %s prefix"), |
| 5074 | current_templates->start->name); |
| 5075 | return NULL; |
| 5076 | } |
| 5077 | if (current_templates->start->opcode_length == 0) |
| 5078 | { |
| 5079 | /* Handle pseudo prefixes. */ |
| 5080 | switch (current_templates->start->base_opcode) |
| 5081 | { |
| 5082 | case 0x0: |
| 5083 | /* {disp8} */ |
| 5084 | i.disp_encoding = disp_encoding_8bit; |
| 5085 | break; |
| 5086 | case 0x1: |
| 5087 | /* {disp32} */ |
| 5088 | i.disp_encoding = disp_encoding_32bit; |
| 5089 | break; |
| 5090 | case 0x2: |
| 5091 | /* {load} */ |
| 5092 | i.dir_encoding = dir_encoding_load; |
| 5093 | break; |
| 5094 | case 0x3: |
| 5095 | /* {store} */ |
| 5096 | i.dir_encoding = dir_encoding_store; |
| 5097 | break; |
| 5098 | case 0x4: |
| 5099 | /* {vex} */ |
| 5100 | i.vec_encoding = vex_encoding_vex; |
| 5101 | break; |
| 5102 | case 0x5: |
| 5103 | /* {vex3} */ |
| 5104 | i.vec_encoding = vex_encoding_vex3; |
| 5105 | break; |
| 5106 | case 0x6: |
| 5107 | /* {evex} */ |
| 5108 | i.vec_encoding = vex_encoding_evex; |
| 5109 | break; |
| 5110 | case 0x7: |
| 5111 | /* {rex} */ |
| 5112 | i.rex_encoding = TRUE; |
| 5113 | break; |
| 5114 | case 0x8: |
| 5115 | /* {nooptimize} */ |
| 5116 | i.no_optimize = TRUE; |
| 5117 | break; |
| 5118 | default: |
| 5119 | abort (); |
| 5120 | } |
| 5121 | } |
| 5122 | else |
| 5123 | { |
| 5124 | /* Add prefix, checking for repeated prefixes. */ |
| 5125 | switch (add_prefix (current_templates->start->base_opcode)) |
| 5126 | { |
| 5127 | case PREFIX_EXIST: |
| 5128 | return NULL; |
| 5129 | case PREFIX_DS: |
| 5130 | if (current_templates->start->cpu_flags.bitfield.cpuibt) |
| 5131 | i.notrack_prefix = current_templates->start->name; |
| 5132 | break; |
| 5133 | case PREFIX_REP: |
| 5134 | if (current_templates->start->cpu_flags.bitfield.cpuhle) |
| 5135 | i.hle_prefix = current_templates->start->name; |
| 5136 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) |
| 5137 | i.bnd_prefix = current_templates->start->name; |
| 5138 | else |
| 5139 | i.rep_prefix = current_templates->start->name; |
| 5140 | break; |
| 5141 | default: |
| 5142 | break; |
| 5143 | } |
| 5144 | } |
| 5145 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ |
| 5146 | token_start = ++l; |
| 5147 | } |
| 5148 | else |
| 5149 | break; |
| 5150 | } |
| 5151 | |
| 5152 | if (!current_templates) |
| 5153 | { |
| 5154 | /* Deprecated functionality (new code should use pseudo-prefixes instead): |
| 5155 | Check if we should swap operand or force 32bit displacement in |
| 5156 | encoding. */ |
| 5157 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
| 5158 | i.dir_encoding = dir_encoding_swap; |
| 5159 | else if (mnem_p - 3 == dot_p |
| 5160 | && dot_p[1] == 'd' |
| 5161 | && dot_p[2] == '8') |
| 5162 | i.disp_encoding = disp_encoding_8bit; |
| 5163 | else if (mnem_p - 4 == dot_p |
| 5164 | && dot_p[1] == 'd' |
| 5165 | && dot_p[2] == '3' |
| 5166 | && dot_p[3] == '2') |
| 5167 | i.disp_encoding = disp_encoding_32bit; |
| 5168 | else |
| 5169 | goto check_suffix; |
| 5170 | mnem_p = dot_p; |
| 5171 | *dot_p = '\0'; |
| 5172 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
| 5173 | } |
| 5174 | |
| 5175 | if (!current_templates) |
| 5176 | { |
| 5177 | check_suffix: |
| 5178 | if (mnem_p > mnemonic) |
| 5179 | { |
| 5180 | /* See if we can get a match by trimming off a suffix. */ |
| 5181 | switch (mnem_p[-1]) |
| 5182 | { |
| 5183 | case WORD_MNEM_SUFFIX: |
| 5184 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) |
| 5185 | i.suffix = SHORT_MNEM_SUFFIX; |
| 5186 | else |
| 5187 | /* Fall through. */ |
| 5188 | case BYTE_MNEM_SUFFIX: |
| 5189 | case QWORD_MNEM_SUFFIX: |
| 5190 | i.suffix = mnem_p[-1]; |
| 5191 | mnem_p[-1] = '\0'; |
| 5192 | current_templates = (const templates *) hash_find (op_hash, |
| 5193 | mnemonic); |
| 5194 | break; |
| 5195 | case SHORT_MNEM_SUFFIX: |
| 5196 | case LONG_MNEM_SUFFIX: |
| 5197 | if (!intel_syntax) |
| 5198 | { |
| 5199 | i.suffix = mnem_p[-1]; |
| 5200 | mnem_p[-1] = '\0'; |
| 5201 | current_templates = (const templates *) hash_find (op_hash, |
| 5202 | mnemonic); |
| 5203 | } |
| 5204 | break; |
| 5205 | |
| 5206 | /* Intel Syntax. */ |
| 5207 | case 'd': |
| 5208 | if (intel_syntax) |
| 5209 | { |
| 5210 | if (intel_float_operand (mnemonic) == 1) |
| 5211 | i.suffix = SHORT_MNEM_SUFFIX; |
| 5212 | else |
| 5213 | i.suffix = LONG_MNEM_SUFFIX; |
| 5214 | mnem_p[-1] = '\0'; |
| 5215 | current_templates = (const templates *) hash_find (op_hash, |
| 5216 | mnemonic); |
| 5217 | } |
| 5218 | break; |
| 5219 | } |
| 5220 | } |
| 5221 | |
| 5222 | if (!current_templates) |
| 5223 | { |
| 5224 | as_bad (_("no such instruction: `%s'"), token_start); |
| 5225 | return NULL; |
| 5226 | } |
| 5227 | } |
| 5228 | |
| 5229 | if (current_templates->start->opcode_modifier.jump == JUMP |
| 5230 | || current_templates->start->opcode_modifier.jump == JUMP_BYTE) |
| 5231 | { |
| 5232 | /* Check for a branch hint. We allow ",pt" and ",pn" for |
| 5233 | predict taken and predict not taken respectively. |
| 5234 | I'm not sure that branch hints actually do anything on loop |
| 5235 | and jcxz insns (JumpByte) for current Pentium4 chips. They |
| 5236 | may work in the future and it doesn't hurt to accept them |
| 5237 | now. */ |
| 5238 | if (l[0] == ',' && l[1] == 'p') |
| 5239 | { |
| 5240 | if (l[2] == 't') |
| 5241 | { |
| 5242 | if (!add_prefix (DS_PREFIX_OPCODE)) |
| 5243 | return NULL; |
| 5244 | l += 3; |
| 5245 | } |
| 5246 | else if (l[2] == 'n') |
| 5247 | { |
| 5248 | if (!add_prefix (CS_PREFIX_OPCODE)) |
| 5249 | return NULL; |
| 5250 | l += 3; |
| 5251 | } |
| 5252 | } |
| 5253 | } |
| 5254 | /* Any other comma loses. */ |
| 5255 | if (*l == ',') |
| 5256 | { |
| 5257 | as_bad (_("invalid character %s in mnemonic"), |
| 5258 | output_invalid (*l)); |
| 5259 | return NULL; |
| 5260 | } |
| 5261 | |
| 5262 | /* Check if instruction is supported on specified architecture. */ |
| 5263 | supported = 0; |
| 5264 | for (t = current_templates->start; t < current_templates->end; ++t) |
| 5265 | { |
| 5266 | supported |= cpu_flags_match (t); |
| 5267 | if (supported == CPU_FLAGS_PERFECT_MATCH) |
| 5268 | { |
| 5269 | if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT)) |
| 5270 | as_warn (_("use .code16 to ensure correct addressing mode")); |
| 5271 | |
| 5272 | return l; |
| 5273 | } |
| 5274 | } |
| 5275 | |
| 5276 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
| 5277 | as_bad (flag_code == CODE_64BIT |
| 5278 | ? _("`%s' is not supported in 64-bit mode") |
| 5279 | : _("`%s' is only supported in 64-bit mode"), |
| 5280 | current_templates->start->name); |
| 5281 | else |
| 5282 | as_bad (_("`%s' is not supported on `%s%s'"), |
| 5283 | current_templates->start->name, |
| 5284 | cpu_arch_name ? cpu_arch_name : default_arch, |
| 5285 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); |
| 5286 | |
| 5287 | return NULL; |
| 5288 | } |
| 5289 | |
| 5290 | static char * |
| 5291 | parse_operands (char *l, const char *mnemonic) |
| 5292 | { |
| 5293 | char *token_start; |
| 5294 | |
| 5295 | /* 1 if operand is pending after ','. */ |
| 5296 | unsigned int expecting_operand = 0; |
| 5297 | |
| 5298 | /* Non-zero if operand parens not balanced. */ |
| 5299 | unsigned int paren_not_balanced; |
| 5300 | |
| 5301 | while (*l != END_OF_INSN) |
| 5302 | { |
| 5303 | /* Skip optional white space before operand. */ |
| 5304 | if (is_space_char (*l)) |
| 5305 | ++l; |
| 5306 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
| 5307 | { |
| 5308 | as_bad (_("invalid character %s before operand %d"), |
| 5309 | output_invalid (*l), |
| 5310 | i.operands + 1); |
| 5311 | return NULL; |
| 5312 | } |
| 5313 | token_start = l; /* After white space. */ |
| 5314 | paren_not_balanced = 0; |
| 5315 | while (paren_not_balanced || *l != ',') |
| 5316 | { |
| 5317 | if (*l == END_OF_INSN) |
| 5318 | { |
| 5319 | if (paren_not_balanced) |
| 5320 | { |
| 5321 | if (!intel_syntax) |
| 5322 | as_bad (_("unbalanced parenthesis in operand %d."), |
| 5323 | i.operands + 1); |
| 5324 | else |
| 5325 | as_bad (_("unbalanced brackets in operand %d."), |
| 5326 | i.operands + 1); |
| 5327 | return NULL; |
| 5328 | } |
| 5329 | else |
| 5330 | break; /* we are done */ |
| 5331 | } |
| 5332 | else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') |
| 5333 | { |
| 5334 | as_bad (_("invalid character %s in operand %d"), |
| 5335 | output_invalid (*l), |
| 5336 | i.operands + 1); |
| 5337 | return NULL; |
| 5338 | } |
| 5339 | if (!intel_syntax) |
| 5340 | { |
| 5341 | if (*l == '(') |
| 5342 | ++paren_not_balanced; |
| 5343 | if (*l == ')') |
| 5344 | --paren_not_balanced; |
| 5345 | } |
| 5346 | else |
| 5347 | { |
| 5348 | if (*l == '[') |
| 5349 | ++paren_not_balanced; |
| 5350 | if (*l == ']') |
| 5351 | --paren_not_balanced; |
| 5352 | } |
| 5353 | l++; |
| 5354 | } |
| 5355 | if (l != token_start) |
| 5356 | { /* Yes, we've read in another operand. */ |
| 5357 | unsigned int operand_ok; |
| 5358 | this_operand = i.operands++; |
| 5359 | if (i.operands > MAX_OPERANDS) |
| 5360 | { |
| 5361 | as_bad (_("spurious operands; (%d operands/instruction max)"), |
| 5362 | MAX_OPERANDS); |
| 5363 | return NULL; |
| 5364 | } |
| 5365 | i.types[this_operand].bitfield.unspecified = 1; |
| 5366 | /* Now parse operand adding info to 'i' as we go along. */ |
| 5367 | END_STRING_AND_SAVE (l); |
| 5368 | |
| 5369 | if (i.mem_operands > 1) |
| 5370 | { |
| 5371 | as_bad (_("too many memory references for `%s'"), |
| 5372 | mnemonic); |
| 5373 | return 0; |
| 5374 | } |
| 5375 | |
| 5376 | if (intel_syntax) |
| 5377 | operand_ok = |
| 5378 | i386_intel_operand (token_start, |
| 5379 | intel_float_operand (mnemonic)); |
| 5380 | else |
| 5381 | operand_ok = i386_att_operand (token_start); |
| 5382 | |
| 5383 | RESTORE_END_STRING (l); |
| 5384 | if (!operand_ok) |
| 5385 | return NULL; |
| 5386 | } |
| 5387 | else |
| 5388 | { |
| 5389 | if (expecting_operand) |
| 5390 | { |
| 5391 | expecting_operand_after_comma: |
| 5392 | as_bad (_("expecting operand after ','; got nothing")); |
| 5393 | return NULL; |
| 5394 | } |
| 5395 | if (*l == ',') |
| 5396 | { |
| 5397 | as_bad (_("expecting operand before ','; got nothing")); |
| 5398 | return NULL; |
| 5399 | } |
| 5400 | } |
| 5401 | |
| 5402 | /* Now *l must be either ',' or END_OF_INSN. */ |
| 5403 | if (*l == ',') |
| 5404 | { |
| 5405 | if (*++l == END_OF_INSN) |
| 5406 | { |
| 5407 | /* Just skip it, if it's \n complain. */ |
| 5408 | goto expecting_operand_after_comma; |
| 5409 | } |
| 5410 | expecting_operand = 1; |
| 5411 | } |
| 5412 | } |
| 5413 | return l; |
| 5414 | } |
| 5415 | |
| 5416 | static void |
| 5417 | swap_2_operands (int xchg1, int xchg2) |
| 5418 | { |
| 5419 | union i386_op temp_op; |
| 5420 | i386_operand_type temp_type; |
| 5421 | unsigned int temp_flags; |
| 5422 | enum bfd_reloc_code_real temp_reloc; |
| 5423 | |
| 5424 | temp_type = i.types[xchg2]; |
| 5425 | i.types[xchg2] = i.types[xchg1]; |
| 5426 | i.types[xchg1] = temp_type; |
| 5427 | |
| 5428 | temp_flags = i.flags[xchg2]; |
| 5429 | i.flags[xchg2] = i.flags[xchg1]; |
| 5430 | i.flags[xchg1] = temp_flags; |
| 5431 | |
| 5432 | temp_op = i.op[xchg2]; |
| 5433 | i.op[xchg2] = i.op[xchg1]; |
| 5434 | i.op[xchg1] = temp_op; |
| 5435 | |
| 5436 | temp_reloc = i.reloc[xchg2]; |
| 5437 | i.reloc[xchg2] = i.reloc[xchg1]; |
| 5438 | i.reloc[xchg1] = temp_reloc; |
| 5439 | |
| 5440 | if (i.mask) |
| 5441 | { |
| 5442 | if (i.mask->operand == xchg1) |
| 5443 | i.mask->operand = xchg2; |
| 5444 | else if (i.mask->operand == xchg2) |
| 5445 | i.mask->operand = xchg1; |
| 5446 | } |
| 5447 | if (i.broadcast) |
| 5448 | { |
| 5449 | if (i.broadcast->operand == xchg1) |
| 5450 | i.broadcast->operand = xchg2; |
| 5451 | else if (i.broadcast->operand == xchg2) |
| 5452 | i.broadcast->operand = xchg1; |
| 5453 | } |
| 5454 | if (i.rounding) |
| 5455 | { |
| 5456 | if (i.rounding->operand == xchg1) |
| 5457 | i.rounding->operand = xchg2; |
| 5458 | else if (i.rounding->operand == xchg2) |
| 5459 | i.rounding->operand = xchg1; |
| 5460 | } |
| 5461 | } |
| 5462 | |
| 5463 | static void |
| 5464 | swap_operands (void) |
| 5465 | { |
| 5466 | switch (i.operands) |
| 5467 | { |
| 5468 | case 5: |
| 5469 | case 4: |
| 5470 | swap_2_operands (1, i.operands - 2); |
| 5471 | /* Fall through. */ |
| 5472 | case 3: |
| 5473 | case 2: |
| 5474 | swap_2_operands (0, i.operands - 1); |
| 5475 | break; |
| 5476 | default: |
| 5477 | abort (); |
| 5478 | } |
| 5479 | |
| 5480 | if (i.mem_operands == 2) |
| 5481 | { |
| 5482 | const seg_entry *temp_seg; |
| 5483 | temp_seg = i.seg[0]; |
| 5484 | i.seg[0] = i.seg[1]; |
| 5485 | i.seg[1] = temp_seg; |
| 5486 | } |
| 5487 | } |
| 5488 | |
| 5489 | /* Try to ensure constant immediates are represented in the smallest |
| 5490 | opcode possible. */ |
| 5491 | static void |
| 5492 | optimize_imm (void) |
| 5493 | { |
| 5494 | char guess_suffix = 0; |
| 5495 | int op; |
| 5496 | |
| 5497 | if (i.suffix) |
| 5498 | guess_suffix = i.suffix; |
| 5499 | else if (i.reg_operands) |
| 5500 | { |
| 5501 | /* Figure out a suffix from the last register operand specified. |
| 5502 | We can't do this properly yet, i.e. excluding special register |
| 5503 | instances, but the following works for instructions with |
| 5504 | immediates. In any case, we can't set i.suffix yet. */ |
| 5505 | for (op = i.operands; --op >= 0;) |
| 5506 | if (i.types[op].bitfield.class != Reg) |
| 5507 | continue; |
| 5508 | else if (i.types[op].bitfield.byte) |
| 5509 | { |
| 5510 | guess_suffix = BYTE_MNEM_SUFFIX; |
| 5511 | break; |
| 5512 | } |
| 5513 | else if (i.types[op].bitfield.word) |
| 5514 | { |
| 5515 | guess_suffix = WORD_MNEM_SUFFIX; |
| 5516 | break; |
| 5517 | } |
| 5518 | else if (i.types[op].bitfield.dword) |
| 5519 | { |
| 5520 | guess_suffix = LONG_MNEM_SUFFIX; |
| 5521 | break; |
| 5522 | } |
| 5523 | else if (i.types[op].bitfield.qword) |
| 5524 | { |
| 5525 | guess_suffix = QWORD_MNEM_SUFFIX; |
| 5526 | break; |
| 5527 | } |
| 5528 | } |
| 5529 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
| 5530 | guess_suffix = WORD_MNEM_SUFFIX; |
| 5531 | |
| 5532 | for (op = i.operands; --op >= 0;) |
| 5533 | if (operand_type_check (i.types[op], imm)) |
| 5534 | { |
| 5535 | switch (i.op[op].imms->X_op) |
| 5536 | { |
| 5537 | case O_constant: |
| 5538 | /* If a suffix is given, this operand may be shortened. */ |
| 5539 | switch (guess_suffix) |
| 5540 | { |
| 5541 | case LONG_MNEM_SUFFIX: |
| 5542 | i.types[op].bitfield.imm32 = 1; |
| 5543 | i.types[op].bitfield.imm64 = 1; |
| 5544 | break; |
| 5545 | case WORD_MNEM_SUFFIX: |
| 5546 | i.types[op].bitfield.imm16 = 1; |
| 5547 | i.types[op].bitfield.imm32 = 1; |
| 5548 | i.types[op].bitfield.imm32s = 1; |
| 5549 | i.types[op].bitfield.imm64 = 1; |
| 5550 | break; |
| 5551 | case BYTE_MNEM_SUFFIX: |
| 5552 | i.types[op].bitfield.imm8 = 1; |
| 5553 | i.types[op].bitfield.imm8s = 1; |
| 5554 | i.types[op].bitfield.imm16 = 1; |
| 5555 | i.types[op].bitfield.imm32 = 1; |
| 5556 | i.types[op].bitfield.imm32s = 1; |
| 5557 | i.types[op].bitfield.imm64 = 1; |
| 5558 | break; |
| 5559 | } |
| 5560 | |
| 5561 | /* If this operand is at most 16 bits, convert it |
| 5562 | to a signed 16 bit number before trying to see |
| 5563 | whether it will fit in an even smaller size. |
| 5564 | This allows a 16-bit operand such as $0xffe0 to |
| 5565 | be recognised as within Imm8S range. */ |
| 5566 | if ((i.types[op].bitfield.imm16) |
| 5567 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
| 5568 | { |
| 5569 | i.op[op].imms->X_add_number = |
| 5570 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); |
| 5571 | } |
| 5572 | #ifdef BFD64 |
| 5573 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ |
| 5574 | if ((i.types[op].bitfield.imm32) |
| 5575 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
| 5576 | == 0)) |
| 5577 | { |
| 5578 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number |
| 5579 | ^ ((offsetT) 1 << 31)) |
| 5580 | - ((offsetT) 1 << 31)); |
| 5581 | } |
| 5582 | #endif |
| 5583 | i.types[op] |
| 5584 | = operand_type_or (i.types[op], |
| 5585 | smallest_imm_type (i.op[op].imms->X_add_number)); |
| 5586 | |
| 5587 | /* We must avoid matching of Imm32 templates when 64bit |
| 5588 | only immediate is available. */ |
| 5589 | if (guess_suffix == QWORD_MNEM_SUFFIX) |
| 5590 | i.types[op].bitfield.imm32 = 0; |
| 5591 | break; |
| 5592 | |
| 5593 | case O_absent: |
| 5594 | case O_register: |
| 5595 | abort (); |
| 5596 | |
| 5597 | /* Symbols and expressions. */ |
| 5598 | default: |
| 5599 | /* Convert symbolic operand to proper sizes for matching, but don't |
| 5600 | prevent matching a set of insns that only supports sizes other |
| 5601 | than those matching the insn suffix. */ |
| 5602 | { |
| 5603 | i386_operand_type mask, allowed; |
| 5604 | const insn_template *t; |
| 5605 | |
| 5606 | operand_type_set (&mask, 0); |
| 5607 | operand_type_set (&allowed, 0); |
| 5608 | |
| 5609 | for (t = current_templates->start; |
| 5610 | t < current_templates->end; |
| 5611 | ++t) |
| 5612 | { |
| 5613 | allowed = operand_type_or (allowed, t->operand_types[op]); |
| 5614 | allowed = operand_type_and (allowed, anyimm); |
| 5615 | } |
| 5616 | switch (guess_suffix) |
| 5617 | { |
| 5618 | case QWORD_MNEM_SUFFIX: |
| 5619 | mask.bitfield.imm64 = 1; |
| 5620 | mask.bitfield.imm32s = 1; |
| 5621 | break; |
| 5622 | case LONG_MNEM_SUFFIX: |
| 5623 | mask.bitfield.imm32 = 1; |
| 5624 | break; |
| 5625 | case WORD_MNEM_SUFFIX: |
| 5626 | mask.bitfield.imm16 = 1; |
| 5627 | break; |
| 5628 | case BYTE_MNEM_SUFFIX: |
| 5629 | mask.bitfield.imm8 = 1; |
| 5630 | break; |
| 5631 | default: |
| 5632 | break; |
| 5633 | } |
| 5634 | allowed = operand_type_and (mask, allowed); |
| 5635 | if (!operand_type_all_zero (&allowed)) |
| 5636 | i.types[op] = operand_type_and (i.types[op], mask); |
| 5637 | } |
| 5638 | break; |
| 5639 | } |
| 5640 | } |
| 5641 | } |
| 5642 | |
| 5643 | /* Try to use the smallest displacement type too. */ |
| 5644 | static void |
| 5645 | optimize_disp (void) |
| 5646 | { |
| 5647 | int op; |
| 5648 | |
| 5649 | for (op = i.operands; --op >= 0;) |
| 5650 | if (operand_type_check (i.types[op], disp)) |
| 5651 | { |
| 5652 | if (i.op[op].disps->X_op == O_constant) |
| 5653 | { |
| 5654 | offsetT op_disp = i.op[op].disps->X_add_number; |
| 5655 | |
| 5656 | if (i.types[op].bitfield.disp16 |
| 5657 | && (op_disp & ~(offsetT) 0xffff) == 0) |
| 5658 | { |
| 5659 | /* If this operand is at most 16 bits, convert |
| 5660 | to a signed 16 bit number and don't use 64bit |
| 5661 | displacement. */ |
| 5662 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
| 5663 | i.types[op].bitfield.disp64 = 0; |
| 5664 | } |
| 5665 | #ifdef BFD64 |
| 5666 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ |
| 5667 | if (i.types[op].bitfield.disp32 |
| 5668 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
| 5669 | { |
| 5670 | /* If this operand is at most 32 bits, convert |
| 5671 | to a signed 32 bit number and don't use 64bit |
| 5672 | displacement. */ |
| 5673 | op_disp &= (((offsetT) 2 << 31) - 1); |
| 5674 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); |
| 5675 | i.types[op].bitfield.disp64 = 0; |
| 5676 | } |
| 5677 | #endif |
| 5678 | if (!op_disp && i.types[op].bitfield.baseindex) |
| 5679 | { |
| 5680 | i.types[op].bitfield.disp8 = 0; |
| 5681 | i.types[op].bitfield.disp16 = 0; |
| 5682 | i.types[op].bitfield.disp32 = 0; |
| 5683 | i.types[op].bitfield.disp32s = 0; |
| 5684 | i.types[op].bitfield.disp64 = 0; |
| 5685 | i.op[op].disps = 0; |
| 5686 | i.disp_operands--; |
| 5687 | } |
| 5688 | else if (flag_code == CODE_64BIT) |
| 5689 | { |
| 5690 | if (fits_in_signed_long (op_disp)) |
| 5691 | { |
| 5692 | i.types[op].bitfield.disp64 = 0; |
| 5693 | i.types[op].bitfield.disp32s = 1; |
| 5694 | } |
| 5695 | if (i.prefix[ADDR_PREFIX] |
| 5696 | && fits_in_unsigned_long (op_disp)) |
| 5697 | i.types[op].bitfield.disp32 = 1; |
| 5698 | } |
| 5699 | if ((i.types[op].bitfield.disp32 |
| 5700 | || i.types[op].bitfield.disp32s |
| 5701 | || i.types[op].bitfield.disp16) |
| 5702 | && fits_in_disp8 (op_disp)) |
| 5703 | i.types[op].bitfield.disp8 = 1; |
| 5704 | } |
| 5705 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
| 5706 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) |
| 5707 | { |
| 5708 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, |
| 5709 | i.op[op].disps, 0, i.reloc[op]); |
| 5710 | i.types[op].bitfield.disp8 = 0; |
| 5711 | i.types[op].bitfield.disp16 = 0; |
| 5712 | i.types[op].bitfield.disp32 = 0; |
| 5713 | i.types[op].bitfield.disp32s = 0; |
| 5714 | i.types[op].bitfield.disp64 = 0; |
| 5715 | } |
| 5716 | else |
| 5717 | /* We only support 64bit displacement on constants. */ |
| 5718 | i.types[op].bitfield.disp64 = 0; |
| 5719 | } |
| 5720 | } |
| 5721 | |
| 5722 | /* Return 1 if there is a match in broadcast bytes between operand |
| 5723 | GIVEN and instruction template T. */ |
| 5724 | |
| 5725 | static INLINE int |
| 5726 | match_broadcast_size (const insn_template *t, unsigned int given) |
| 5727 | { |
| 5728 | return ((t->opcode_modifier.broadcast == BYTE_BROADCAST |
| 5729 | && i.types[given].bitfield.byte) |
| 5730 | || (t->opcode_modifier.broadcast == WORD_BROADCAST |
| 5731 | && i.types[given].bitfield.word) |
| 5732 | || (t->opcode_modifier.broadcast == DWORD_BROADCAST |
| 5733 | && i.types[given].bitfield.dword) |
| 5734 | || (t->opcode_modifier.broadcast == QWORD_BROADCAST |
| 5735 | && i.types[given].bitfield.qword)); |
| 5736 | } |
| 5737 | |
| 5738 | /* Check if operands are valid for the instruction. */ |
| 5739 | |
| 5740 | static int |
| 5741 | check_VecOperands (const insn_template *t) |
| 5742 | { |
| 5743 | unsigned int op; |
| 5744 | i386_cpu_flags cpu; |
| 5745 | |
| 5746 | /* Templates allowing for ZMMword as well as YMMword and/or XMMword for |
| 5747 | any one operand are implicity requiring AVX512VL support if the actual |
| 5748 | operand size is YMMword or XMMword. Since this function runs after |
| 5749 | template matching, there's no need to check for YMMword/XMMword in |
| 5750 | the template. */ |
| 5751 | cpu = cpu_flags_and (t->cpu_flags, avx512); |
| 5752 | if (!cpu_flags_all_zero (&cpu) |
| 5753 | && !t->cpu_flags.bitfield.cpuavx512vl |
| 5754 | && !cpu_arch_flags.bitfield.cpuavx512vl) |
| 5755 | { |
| 5756 | for (op = 0; op < t->operands; ++op) |
| 5757 | { |
| 5758 | if (t->operand_types[op].bitfield.zmmword |
| 5759 | && (i.types[op].bitfield.ymmword |
| 5760 | || i.types[op].bitfield.xmmword)) |
| 5761 | { |
| 5762 | i.error = unsupported; |
| 5763 | return 1; |
| 5764 | } |
| 5765 | } |
| 5766 | } |
| 5767 | |
| 5768 | /* Without VSIB byte, we can't have a vector register for index. */ |
| 5769 | if (!t->opcode_modifier.vecsib |
| 5770 | && i.index_reg |
| 5771 | && (i.index_reg->reg_type.bitfield.xmmword |
| 5772 | || i.index_reg->reg_type.bitfield.ymmword |
| 5773 | || i.index_reg->reg_type.bitfield.zmmword)) |
| 5774 | { |
| 5775 | i.error = unsupported_vector_index_register; |
| 5776 | return 1; |
| 5777 | } |
| 5778 | |
| 5779 | /* Check if default mask is allowed. */ |
| 5780 | if (t->opcode_modifier.nodefmask |
| 5781 | && (!i.mask || i.mask->mask->reg_num == 0)) |
| 5782 | { |
| 5783 | i.error = no_default_mask; |
| 5784 | return 1; |
| 5785 | } |
| 5786 | |
| 5787 | /* For VSIB byte, we need a vector register for index, and all vector |
| 5788 | registers must be distinct. */ |
| 5789 | if (t->opcode_modifier.vecsib) |
| 5790 | { |
| 5791 | if (!i.index_reg |
| 5792 | || !((t->opcode_modifier.vecsib == VecSIB128 |
| 5793 | && i.index_reg->reg_type.bitfield.xmmword) |
| 5794 | || (t->opcode_modifier.vecsib == VecSIB256 |
| 5795 | && i.index_reg->reg_type.bitfield.ymmword) |
| 5796 | || (t->opcode_modifier.vecsib == VecSIB512 |
| 5797 | && i.index_reg->reg_type.bitfield.zmmword))) |
| 5798 | { |
| 5799 | i.error = invalid_vsib_address; |
| 5800 | return 1; |
| 5801 | } |
| 5802 | |
| 5803 | gas_assert (i.reg_operands == 2 || i.mask); |
| 5804 | if (i.reg_operands == 2 && !i.mask) |
| 5805 | { |
| 5806 | gas_assert (i.types[0].bitfield.class == RegSIMD); |
| 5807 | gas_assert (i.types[0].bitfield.xmmword |
| 5808 | || i.types[0].bitfield.ymmword); |
| 5809 | gas_assert (i.types[2].bitfield.class == RegSIMD); |
| 5810 | gas_assert (i.types[2].bitfield.xmmword |
| 5811 | || i.types[2].bitfield.ymmword); |
| 5812 | if (operand_check == check_none) |
| 5813 | return 0; |
| 5814 | if (register_number (i.op[0].regs) |
| 5815 | != register_number (i.index_reg) |
| 5816 | && register_number (i.op[2].regs) |
| 5817 | != register_number (i.index_reg) |
| 5818 | && register_number (i.op[0].regs) |
| 5819 | != register_number (i.op[2].regs)) |
| 5820 | return 0; |
| 5821 | if (operand_check == check_error) |
| 5822 | { |
| 5823 | i.error = invalid_vector_register_set; |
| 5824 | return 1; |
| 5825 | } |
| 5826 | as_warn (_("mask, index, and destination registers should be distinct")); |
| 5827 | } |
| 5828 | else if (i.reg_operands == 1 && i.mask) |
| 5829 | { |
| 5830 | if (i.types[1].bitfield.class == RegSIMD |
| 5831 | && (i.types[1].bitfield.xmmword |
| 5832 | || i.types[1].bitfield.ymmword |
| 5833 | || i.types[1].bitfield.zmmword) |
| 5834 | && (register_number (i.op[1].regs) |
| 5835 | == register_number (i.index_reg))) |
| 5836 | { |
| 5837 | if (operand_check == check_error) |
| 5838 | { |
| 5839 | i.error = invalid_vector_register_set; |
| 5840 | return 1; |
| 5841 | } |
| 5842 | if (operand_check != check_none) |
| 5843 | as_warn (_("index and destination registers should be distinct")); |
| 5844 | } |
| 5845 | } |
| 5846 | } |
| 5847 | |
| 5848 | /* Check if broadcast is supported by the instruction and is applied |
| 5849 | to the memory operand. */ |
| 5850 | if (i.broadcast) |
| 5851 | { |
| 5852 | i386_operand_type type, overlap; |
| 5853 | |
| 5854 | /* Check if specified broadcast is supported in this instruction, |
| 5855 | and its broadcast bytes match the memory operand. */ |
| 5856 | op = i.broadcast->operand; |
| 5857 | if (!t->opcode_modifier.broadcast |
| 5858 | || !(i.flags[op] & Operand_Mem) |
| 5859 | || (!i.types[op].bitfield.unspecified |
| 5860 | && !match_broadcast_size (t, op))) |
| 5861 | { |
| 5862 | bad_broadcast: |
| 5863 | i.error = unsupported_broadcast; |
| 5864 | return 1; |
| 5865 | } |
| 5866 | |
| 5867 | i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1)) |
| 5868 | * i.broadcast->type); |
| 5869 | operand_type_set (&type, 0); |
| 5870 | switch (i.broadcast->bytes) |
| 5871 | { |
| 5872 | case 2: |
| 5873 | type.bitfield.word = 1; |
| 5874 | break; |
| 5875 | case 4: |
| 5876 | type.bitfield.dword = 1; |
| 5877 | break; |
| 5878 | case 8: |
| 5879 | type.bitfield.qword = 1; |
| 5880 | break; |
| 5881 | case 16: |
| 5882 | type.bitfield.xmmword = 1; |
| 5883 | break; |
| 5884 | case 32: |
| 5885 | type.bitfield.ymmword = 1; |
| 5886 | break; |
| 5887 | case 64: |
| 5888 | type.bitfield.zmmword = 1; |
| 5889 | break; |
| 5890 | default: |
| 5891 | goto bad_broadcast; |
| 5892 | } |
| 5893 | |
| 5894 | overlap = operand_type_and (type, t->operand_types[op]); |
| 5895 | if (t->operand_types[op].bitfield.class == RegSIMD |
| 5896 | && t->operand_types[op].bitfield.byte |
| 5897 | + t->operand_types[op].bitfield.word |
| 5898 | + t->operand_types[op].bitfield.dword |
| 5899 | + t->operand_types[op].bitfield.qword > 1) |
| 5900 | { |
| 5901 | overlap.bitfield.xmmword = 0; |
| 5902 | overlap.bitfield.ymmword = 0; |
| 5903 | overlap.bitfield.zmmword = 0; |
| 5904 | } |
| 5905 | if (operand_type_all_zero (&overlap)) |
| 5906 | goto bad_broadcast; |
| 5907 | |
| 5908 | if (t->opcode_modifier.checkregsize) |
| 5909 | { |
| 5910 | unsigned int j; |
| 5911 | |
| 5912 | type.bitfield.baseindex = 1; |
| 5913 | for (j = 0; j < i.operands; ++j) |
| 5914 | { |
| 5915 | if (j != op |
| 5916 | && !operand_type_register_match(i.types[j], |
| 5917 | t->operand_types[j], |
| 5918 | type, |
| 5919 | t->operand_types[op])) |
| 5920 | goto bad_broadcast; |
| 5921 | } |
| 5922 | } |
| 5923 | } |
| 5924 | /* If broadcast is supported in this instruction, we need to check if |
| 5925 | operand of one-element size isn't specified without broadcast. */ |
| 5926 | else if (t->opcode_modifier.broadcast && i.mem_operands) |
| 5927 | { |
| 5928 | /* Find memory operand. */ |
| 5929 | for (op = 0; op < i.operands; op++) |
| 5930 | if (i.flags[op] & Operand_Mem) |
| 5931 | break; |
| 5932 | gas_assert (op < i.operands); |
| 5933 | /* Check size of the memory operand. */ |
| 5934 | if (match_broadcast_size (t, op)) |
| 5935 | { |
| 5936 | i.error = broadcast_needed; |
| 5937 | return 1; |
| 5938 | } |
| 5939 | } |
| 5940 | else |
| 5941 | op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */ |
| 5942 | |
| 5943 | /* Check if requested masking is supported. */ |
| 5944 | if (i.mask) |
| 5945 | { |
| 5946 | switch (t->opcode_modifier.masking) |
| 5947 | { |
| 5948 | case BOTH_MASKING: |
| 5949 | break; |
| 5950 | case MERGING_MASKING: |
| 5951 | if (i.mask->zeroing) |
| 5952 | { |
| 5953 | case 0: |
| 5954 | i.error = unsupported_masking; |
| 5955 | return 1; |
| 5956 | } |
| 5957 | break; |
| 5958 | case DYNAMIC_MASKING: |
| 5959 | /* Memory destinations allow only merging masking. */ |
| 5960 | if (i.mask->zeroing && i.mem_operands) |
| 5961 | { |
| 5962 | /* Find memory operand. */ |
| 5963 | for (op = 0; op < i.operands; op++) |
| 5964 | if (i.flags[op] & Operand_Mem) |
| 5965 | break; |
| 5966 | gas_assert (op < i.operands); |
| 5967 | if (op == i.operands - 1) |
| 5968 | { |
| 5969 | i.error = unsupported_masking; |
| 5970 | return 1; |
| 5971 | } |
| 5972 | } |
| 5973 | break; |
| 5974 | default: |
| 5975 | abort (); |
| 5976 | } |
| 5977 | } |
| 5978 | |
| 5979 | /* Check if masking is applied to dest operand. */ |
| 5980 | if (i.mask && (i.mask->operand != (int) (i.operands - 1))) |
| 5981 | { |
| 5982 | i.error = mask_not_on_destination; |
| 5983 | return 1; |
| 5984 | } |
| 5985 | |
| 5986 | /* Check RC/SAE. */ |
| 5987 | if (i.rounding) |
| 5988 | { |
| 5989 | if (!t->opcode_modifier.sae |
| 5990 | || (i.rounding->type != saeonly && !t->opcode_modifier.staticrounding)) |
| 5991 | { |
| 5992 | i.error = unsupported_rc_sae; |
| 5993 | return 1; |
| 5994 | } |
| 5995 | /* If the instruction has several immediate operands and one of |
| 5996 | them is rounding, the rounding operand should be the last |
| 5997 | immediate operand. */ |
| 5998 | if (i.imm_operands > 1 |
| 5999 | && i.rounding->operand != (int) (i.imm_operands - 1)) |
| 6000 | { |
| 6001 | i.error = rc_sae_operand_not_last_imm; |
| 6002 | return 1; |
| 6003 | } |
| 6004 | } |
| 6005 | |
| 6006 | /* Check vector Disp8 operand. */ |
| 6007 | if (t->opcode_modifier.disp8memshift |
| 6008 | && i.disp_encoding != disp_encoding_32bit) |
| 6009 | { |
| 6010 | if (i.broadcast) |
| 6011 | i.memshift = t->opcode_modifier.broadcast - 1; |
| 6012 | else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL) |
| 6013 | i.memshift = t->opcode_modifier.disp8memshift; |
| 6014 | else |
| 6015 | { |
| 6016 | const i386_operand_type *type = NULL; |
| 6017 | |
| 6018 | i.memshift = 0; |
| 6019 | for (op = 0; op < i.operands; op++) |
| 6020 | if (i.flags[op] & Operand_Mem) |
| 6021 | { |
| 6022 | if (t->opcode_modifier.evex == EVEXLIG) |
| 6023 | i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); |
| 6024 | else if (t->operand_types[op].bitfield.xmmword |
| 6025 | + t->operand_types[op].bitfield.ymmword |
| 6026 | + t->operand_types[op].bitfield.zmmword <= 1) |
| 6027 | type = &t->operand_types[op]; |
| 6028 | else if (!i.types[op].bitfield.unspecified) |
| 6029 | type = &i.types[op]; |
| 6030 | } |
| 6031 | else if (i.types[op].bitfield.class == RegSIMD |
| 6032 | && t->opcode_modifier.evex != EVEXLIG) |
| 6033 | { |
| 6034 | if (i.types[op].bitfield.zmmword) |
| 6035 | i.memshift = 6; |
| 6036 | else if (i.types[op].bitfield.ymmword && i.memshift < 5) |
| 6037 | i.memshift = 5; |
| 6038 | else if (i.types[op].bitfield.xmmword && i.memshift < 4) |
| 6039 | i.memshift = 4; |
| 6040 | } |
| 6041 | |
| 6042 | if (type) |
| 6043 | { |
| 6044 | if (type->bitfield.zmmword) |
| 6045 | i.memshift = 6; |
| 6046 | else if (type->bitfield.ymmword) |
| 6047 | i.memshift = 5; |
| 6048 | else if (type->bitfield.xmmword) |
| 6049 | i.memshift = 4; |
| 6050 | } |
| 6051 | |
| 6052 | /* For the check in fits_in_disp8(). */ |
| 6053 | if (i.memshift == 0) |
| 6054 | i.memshift = -1; |
| 6055 | } |
| 6056 | |
| 6057 | for (op = 0; op < i.operands; op++) |
| 6058 | if (operand_type_check (i.types[op], disp) |
| 6059 | && i.op[op].disps->X_op == O_constant) |
| 6060 | { |
| 6061 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
| 6062 | { |
| 6063 | i.types[op].bitfield.disp8 = 1; |
| 6064 | return 0; |
| 6065 | } |
| 6066 | i.types[op].bitfield.disp8 = 0; |
| 6067 | } |
| 6068 | } |
| 6069 | |
| 6070 | i.memshift = 0; |
| 6071 | |
| 6072 | return 0; |
| 6073 | } |
| 6074 | |
| 6075 | /* Check if operands are valid for the instruction. Update VEX |
| 6076 | operand types. */ |
| 6077 | |
| 6078 | static int |
| 6079 | VEX_check_operands (const insn_template *t) |
| 6080 | { |
| 6081 | if (i.vec_encoding == vex_encoding_evex) |
| 6082 | { |
| 6083 | /* This instruction must be encoded with EVEX prefix. */ |
| 6084 | if (!is_evex_encoding (t)) |
| 6085 | { |
| 6086 | i.error = unsupported; |
| 6087 | return 1; |
| 6088 | } |
| 6089 | return 0; |
| 6090 | } |
| 6091 | |
| 6092 | if (!t->opcode_modifier.vex) |
| 6093 | { |
| 6094 | /* This instruction template doesn't have VEX prefix. */ |
| 6095 | if (i.vec_encoding != vex_encoding_default) |
| 6096 | { |
| 6097 | i.error = unsupported; |
| 6098 | return 1; |
| 6099 | } |
| 6100 | return 0; |
| 6101 | } |
| 6102 | |
| 6103 | /* Check the special Imm4 cases; must be the first operand. */ |
| 6104 | if (t->cpu_flags.bitfield.cpuxop && t->operands == 5) |
| 6105 | { |
| 6106 | if (i.op[0].imms->X_op != O_constant |
| 6107 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) |
| 6108 | { |
| 6109 | i.error = bad_imm4; |
| 6110 | return 1; |
| 6111 | } |
| 6112 | |
| 6113 | /* Turn off Imm<N> so that update_imm won't complain. */ |
| 6114 | operand_type_set (&i.types[0], 0); |
| 6115 | } |
| 6116 | |
| 6117 | return 0; |
| 6118 | } |
| 6119 | |
| 6120 | static const insn_template * |
| 6121 | match_template (char mnem_suffix) |
| 6122 | { |
| 6123 | /* Points to template once we've found it. */ |
| 6124 | const insn_template *t; |
| 6125 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
| 6126 | i386_operand_type overlap4; |
| 6127 | unsigned int found_reverse_match; |
| 6128 | i386_opcode_modifier suffix_check; |
| 6129 | i386_operand_type operand_types [MAX_OPERANDS]; |
| 6130 | int addr_prefix_disp; |
| 6131 | unsigned int j, size_match, check_register; |
| 6132 | enum i386_error specific_error = 0; |
| 6133 | |
| 6134 | #if MAX_OPERANDS != 5 |
| 6135 | # error "MAX_OPERANDS must be 5." |
| 6136 | #endif |
| 6137 | |
| 6138 | found_reverse_match = 0; |
| 6139 | addr_prefix_disp = -1; |
| 6140 | |
| 6141 | /* Prepare for mnemonic suffix check. */ |
| 6142 | memset (&suffix_check, 0, sizeof (suffix_check)); |
| 6143 | switch (mnem_suffix) |
| 6144 | { |
| 6145 | case BYTE_MNEM_SUFFIX: |
| 6146 | suffix_check.no_bsuf = 1; |
| 6147 | break; |
| 6148 | case WORD_MNEM_SUFFIX: |
| 6149 | suffix_check.no_wsuf = 1; |
| 6150 | break; |
| 6151 | case SHORT_MNEM_SUFFIX: |
| 6152 | suffix_check.no_ssuf = 1; |
| 6153 | break; |
| 6154 | case LONG_MNEM_SUFFIX: |
| 6155 | suffix_check.no_lsuf = 1; |
| 6156 | break; |
| 6157 | case QWORD_MNEM_SUFFIX: |
| 6158 | suffix_check.no_qsuf = 1; |
| 6159 | break; |
| 6160 | default: |
| 6161 | /* NB: In Intel syntax, normally we can check for memory operand |
| 6162 | size when there is no mnemonic suffix. But jmp and call have |
| 6163 | 2 different encodings with Dword memory operand size, one with |
| 6164 | No_ldSuf and the other without. i.suffix is set to |
| 6165 | LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */ |
| 6166 | if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) |
| 6167 | suffix_check.no_ldsuf = 1; |
| 6168 | } |
| 6169 | |
| 6170 | /* Must have right number of operands. */ |
| 6171 | i.error = number_of_operands_mismatch; |
| 6172 | |
| 6173 | for (t = current_templates->start; t < current_templates->end; t++) |
| 6174 | { |
| 6175 | addr_prefix_disp = -1; |
| 6176 | found_reverse_match = 0; |
| 6177 | |
| 6178 | if (i.operands != t->operands) |
| 6179 | continue; |
| 6180 | |
| 6181 | /* Check processor support. */ |
| 6182 | i.error = unsupported; |
| 6183 | if (cpu_flags_match (t) != CPU_FLAGS_PERFECT_MATCH) |
| 6184 | continue; |
| 6185 | |
| 6186 | /* Check AT&T mnemonic. */ |
| 6187 | i.error = unsupported_with_intel_mnemonic; |
| 6188 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
| 6189 | continue; |
| 6190 | |
| 6191 | /* Check AT&T/Intel syntax. */ |
| 6192 | i.error = unsupported_syntax; |
| 6193 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
| 6194 | || (!intel_syntax && t->opcode_modifier.intelsyntax)) |
| 6195 | continue; |
| 6196 | |
| 6197 | /* Check Intel64/AMD64 ISA. */ |
| 6198 | switch (isa64) |
| 6199 | { |
| 6200 | default: |
| 6201 | /* Default: Don't accept Intel64. */ |
| 6202 | if (t->opcode_modifier.isa64 == INTEL64) |
| 6203 | continue; |
| 6204 | break; |
| 6205 | case amd64: |
| 6206 | /* -mamd64: Don't accept Intel64 and Intel64 only. */ |
| 6207 | if (t->opcode_modifier.isa64 >= INTEL64) |
| 6208 | continue; |
| 6209 | break; |
| 6210 | case intel64: |
| 6211 | /* -mintel64: Don't accept AMD64. */ |
| 6212 | if (t->opcode_modifier.isa64 == AMD64 && flag_code == CODE_64BIT) |
| 6213 | continue; |
| 6214 | break; |
| 6215 | } |
| 6216 | |
| 6217 | /* Check the suffix. */ |
| 6218 | i.error = invalid_instruction_suffix; |
| 6219 | if ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) |
| 6220 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) |
| 6221 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) |
| 6222 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) |
| 6223 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) |
| 6224 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)) |
| 6225 | continue; |
| 6226 | |
| 6227 | size_match = operand_size_match (t); |
| 6228 | if (!size_match) |
| 6229 | continue; |
| 6230 | |
| 6231 | /* This is intentionally not |
| 6232 | |
| 6233 | if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE)) |
| 6234 | |
| 6235 | as the case of a missing * on the operand is accepted (perhaps with |
| 6236 | a warning, issued further down). */ |
| 6237 | if (i.jumpabsolute && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
| 6238 | { |
| 6239 | i.error = operand_type_mismatch; |
| 6240 | continue; |
| 6241 | } |
| 6242 | |
| 6243 | for (j = 0; j < MAX_OPERANDS; j++) |
| 6244 | operand_types[j] = t->operand_types[j]; |
| 6245 | |
| 6246 | /* In general, don't allow |
| 6247 | - 64-bit operands outside of 64-bit mode, |
| 6248 | - 32-bit operands on pre-386. */ |
| 6249 | j = i.imm_operands + (t->operands > i.imm_operands + 1); |
| 6250 | if (((i.suffix == QWORD_MNEM_SUFFIX |
| 6251 | && flag_code != CODE_64BIT |
| 6252 | && (t->base_opcode != 0x0fc7 |
| 6253 | || t->extension_opcode != 1 /* cmpxchg8b */)) |
| 6254 | || (i.suffix == LONG_MNEM_SUFFIX |
| 6255 | && !cpu_arch_flags.bitfield.cpui386)) |
| 6256 | && (intel_syntax |
| 6257 | ? (t->opcode_modifier.mnemonicsize != IGNORESIZE |
| 6258 | && !intel_float_operand (t->name)) |
| 6259 | : intel_float_operand (t->name) != 2) |
| 6260 | && (t->operands == i.imm_operands |
| 6261 | || (operand_types[i.imm_operands].bitfield.class != RegMMX |
| 6262 | && operand_types[i.imm_operands].bitfield.class != RegSIMD |
| 6263 | && operand_types[i.imm_operands].bitfield.class != RegMask) |
| 6264 | || (operand_types[j].bitfield.class != RegMMX |
| 6265 | && operand_types[j].bitfield.class != RegSIMD |
| 6266 | && operand_types[j].bitfield.class != RegMask)) |
| 6267 | && !t->opcode_modifier.vecsib) |
| 6268 | continue; |
| 6269 | |
| 6270 | /* Do not verify operands when there are none. */ |
| 6271 | if (!t->operands) |
| 6272 | /* We've found a match; break out of loop. */ |
| 6273 | break; |
| 6274 | |
| 6275 | if (!t->opcode_modifier.jump |
| 6276 | || t->opcode_modifier.jump == JUMP_ABSOLUTE) |
| 6277 | { |
| 6278 | /* There should be only one Disp operand. */ |
| 6279 | for (j = 0; j < MAX_OPERANDS; j++) |
| 6280 | if (operand_type_check (operand_types[j], disp)) |
| 6281 | break; |
| 6282 | if (j < MAX_OPERANDS) |
| 6283 | { |
| 6284 | bfd_boolean override = (i.prefix[ADDR_PREFIX] != 0); |
| 6285 | |
| 6286 | addr_prefix_disp = j; |
| 6287 | |
| 6288 | /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16 |
| 6289 | operand into Disp32/Disp32/Disp16/Disp32 operand. */ |
| 6290 | switch (flag_code) |
| 6291 | { |
| 6292 | case CODE_16BIT: |
| 6293 | override = !override; |
| 6294 | /* Fall through. */ |
| 6295 | case CODE_32BIT: |
| 6296 | if (operand_types[j].bitfield.disp32 |
| 6297 | && operand_types[j].bitfield.disp16) |
| 6298 | { |
| 6299 | operand_types[j].bitfield.disp16 = override; |
| 6300 | operand_types[j].bitfield.disp32 = !override; |
| 6301 | } |
| 6302 | operand_types[j].bitfield.disp32s = 0; |
| 6303 | operand_types[j].bitfield.disp64 = 0; |
| 6304 | break; |
| 6305 | |
| 6306 | case CODE_64BIT: |
| 6307 | if (operand_types[j].bitfield.disp32s |
| 6308 | || operand_types[j].bitfield.disp64) |
| 6309 | { |
| 6310 | operand_types[j].bitfield.disp64 &= !override; |
| 6311 | operand_types[j].bitfield.disp32s &= !override; |
| 6312 | operand_types[j].bitfield.disp32 = override; |
| 6313 | } |
| 6314 | operand_types[j].bitfield.disp16 = 0; |
| 6315 | break; |
| 6316 | } |
| 6317 | } |
| 6318 | } |
| 6319 | |
| 6320 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ |
| 6321 | if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0) |
| 6322 | continue; |
| 6323 | |
| 6324 | /* We check register size if needed. */ |
| 6325 | if (t->opcode_modifier.checkregsize) |
| 6326 | { |
| 6327 | check_register = (1 << t->operands) - 1; |
| 6328 | if (i.broadcast) |
| 6329 | check_register &= ~(1 << i.broadcast->operand); |
| 6330 | } |
| 6331 | else |
| 6332 | check_register = 0; |
| 6333 | |
| 6334 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
| 6335 | switch (t->operands) |
| 6336 | { |
| 6337 | case 1: |
| 6338 | if (!operand_type_match (overlap0, i.types[0])) |
| 6339 | continue; |
| 6340 | break; |
| 6341 | case 2: |
| 6342 | /* xchg %eax, %eax is a special case. It is an alias for nop |
| 6343 | only in 32bit mode and we can use opcode 0x90. In 64bit |
| 6344 | mode, we can't use 0x90 for xchg %eax, %eax since it should |
| 6345 | zero-extend %eax to %rax. */ |
| 6346 | if (flag_code == CODE_64BIT |
| 6347 | && t->base_opcode == 0x90 |
| 6348 | && i.types[0].bitfield.instance == Accum |
| 6349 | && i.types[0].bitfield.dword |
| 6350 | && i.types[1].bitfield.instance == Accum |
| 6351 | && i.types[1].bitfield.dword) |
| 6352 | continue; |
| 6353 | /* xrelease mov %eax, <disp> is another special case. It must not |
| 6354 | match the accumulator-only encoding of mov. */ |
| 6355 | if (flag_code != CODE_64BIT |
| 6356 | && i.hle_prefix |
| 6357 | && t->base_opcode == 0xa0 |
| 6358 | && i.types[0].bitfield.instance == Accum |
| 6359 | && (i.flags[1] & Operand_Mem)) |
| 6360 | continue; |
| 6361 | /* Fall through. */ |
| 6362 | |
| 6363 | case 3: |
| 6364 | if (!(size_match & MATCH_STRAIGHT)) |
| 6365 | goto check_reverse; |
| 6366 | /* Reverse direction of operands if swapping is possible in the first |
| 6367 | place (operands need to be symmetric) and |
| 6368 | - the load form is requested, and the template is a store form, |
| 6369 | - the store form is requested, and the template is a load form, |
| 6370 | - the non-default (swapped) form is requested. */ |
| 6371 | overlap1 = operand_type_and (operand_types[0], operand_types[1]); |
| 6372 | if (t->opcode_modifier.d && i.reg_operands == i.operands |
| 6373 | && !operand_type_all_zero (&overlap1)) |
| 6374 | switch (i.dir_encoding) |
| 6375 | { |
| 6376 | case dir_encoding_load: |
| 6377 | if (operand_type_check (operand_types[i.operands - 1], anymem) |
| 6378 | || t->opcode_modifier.regmem) |
| 6379 | goto check_reverse; |
| 6380 | break; |
| 6381 | |
| 6382 | case dir_encoding_store: |
| 6383 | if (!operand_type_check (operand_types[i.operands - 1], anymem) |
| 6384 | && !t->opcode_modifier.regmem) |
| 6385 | goto check_reverse; |
| 6386 | break; |
| 6387 | |
| 6388 | case dir_encoding_swap: |
| 6389 | goto check_reverse; |
| 6390 | |
| 6391 | case dir_encoding_default: |
| 6392 | break; |
| 6393 | } |
| 6394 | /* If we want store form, we skip the current load. */ |
| 6395 | if ((i.dir_encoding == dir_encoding_store |
| 6396 | || i.dir_encoding == dir_encoding_swap) |
| 6397 | && i.mem_operands == 0 |
| 6398 | && t->opcode_modifier.load) |
| 6399 | continue; |
| 6400 | /* Fall through. */ |
| 6401 | case 4: |
| 6402 | case 5: |
| 6403 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
| 6404 | if (!operand_type_match (overlap0, i.types[0]) |
| 6405 | || !operand_type_match (overlap1, i.types[1]) |
| 6406 | || ((check_register & 3) == 3 |
| 6407 | && !operand_type_register_match (i.types[0], |
| 6408 | operand_types[0], |
| 6409 | i.types[1], |
| 6410 | operand_types[1]))) |
| 6411 | { |
| 6412 | /* Check if other direction is valid ... */ |
| 6413 | if (!t->opcode_modifier.d) |
| 6414 | continue; |
| 6415 | |
| 6416 | check_reverse: |
| 6417 | if (!(size_match & MATCH_REVERSE)) |
| 6418 | continue; |
| 6419 | /* Try reversing direction of operands. */ |
| 6420 | overlap0 = operand_type_and (i.types[0], operand_types[i.operands - 1]); |
| 6421 | overlap1 = operand_type_and (i.types[i.operands - 1], operand_types[0]); |
| 6422 | if (!operand_type_match (overlap0, i.types[0]) |
| 6423 | || !operand_type_match (overlap1, i.types[i.operands - 1]) |
| 6424 | || (check_register |
| 6425 | && !operand_type_register_match (i.types[0], |
| 6426 | operand_types[i.operands - 1], |
| 6427 | i.types[i.operands - 1], |
| 6428 | operand_types[0]))) |
| 6429 | { |
| 6430 | /* Does not match either direction. */ |
| 6431 | continue; |
| 6432 | } |
| 6433 | /* found_reverse_match holds which of D or FloatR |
| 6434 | we've found. */ |
| 6435 | if (!t->opcode_modifier.d) |
| 6436 | found_reverse_match = 0; |
| 6437 | else if (operand_types[0].bitfield.tbyte) |
| 6438 | found_reverse_match = Opcode_FloatD; |
| 6439 | else if (operand_types[0].bitfield.xmmword |
| 6440 | || operand_types[i.operands - 1].bitfield.xmmword |
| 6441 | || operand_types[0].bitfield.class == RegMMX |
| 6442 | || operand_types[i.operands - 1].bitfield.class == RegMMX |
| 6443 | || is_any_vex_encoding(t)) |
| 6444 | found_reverse_match = (t->base_opcode & 0xee) != 0x6e |
| 6445 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; |
| 6446 | else |
| 6447 | found_reverse_match = Opcode_D; |
| 6448 | if (t->opcode_modifier.floatr) |
| 6449 | found_reverse_match |= Opcode_FloatR; |
| 6450 | } |
| 6451 | else |
| 6452 | { |
| 6453 | /* Found a forward 2 operand match here. */ |
| 6454 | switch (t->operands) |
| 6455 | { |
| 6456 | case 5: |
| 6457 | overlap4 = operand_type_and (i.types[4], |
| 6458 | operand_types[4]); |
| 6459 | /* Fall through. */ |
| 6460 | case 4: |
| 6461 | overlap3 = operand_type_and (i.types[3], |
| 6462 | operand_types[3]); |
| 6463 | /* Fall through. */ |
| 6464 | case 3: |
| 6465 | overlap2 = operand_type_and (i.types[2], |
| 6466 | operand_types[2]); |
| 6467 | break; |
| 6468 | } |
| 6469 | |
| 6470 | switch (t->operands) |
| 6471 | { |
| 6472 | case 5: |
| 6473 | if (!operand_type_match (overlap4, i.types[4]) |
| 6474 | || !operand_type_register_match (i.types[3], |
| 6475 | operand_types[3], |
| 6476 | i.types[4], |
| 6477 | operand_types[4])) |
| 6478 | continue; |
| 6479 | /* Fall through. */ |
| 6480 | case 4: |
| 6481 | if (!operand_type_match (overlap3, i.types[3]) |
| 6482 | || ((check_register & 0xa) == 0xa |
| 6483 | && !operand_type_register_match (i.types[1], |
| 6484 | operand_types[1], |
| 6485 | i.types[3], |
| 6486 | operand_types[3])) |
| 6487 | || ((check_register & 0xc) == 0xc |
| 6488 | && !operand_type_register_match (i.types[2], |
| 6489 | operand_types[2], |
| 6490 | i.types[3], |
| 6491 | operand_types[3]))) |
| 6492 | continue; |
| 6493 | /* Fall through. */ |
| 6494 | case 3: |
| 6495 | /* Here we make use of the fact that there are no |
| 6496 | reverse match 3 operand instructions. */ |
| 6497 | if (!operand_type_match (overlap2, i.types[2]) |
| 6498 | || ((check_register & 5) == 5 |
| 6499 | && !operand_type_register_match (i.types[0], |
| 6500 | operand_types[0], |
| 6501 | i.types[2], |
| 6502 | operand_types[2])) |
| 6503 | || ((check_register & 6) == 6 |
| 6504 | && !operand_type_register_match (i.types[1], |
| 6505 | operand_types[1], |
| 6506 | i.types[2], |
| 6507 | operand_types[2]))) |
| 6508 | continue; |
| 6509 | break; |
| 6510 | } |
| 6511 | } |
| 6512 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
| 6513 | slip through to break. */ |
| 6514 | } |
| 6515 | |
| 6516 | /* Check if vector and VEX operands are valid. */ |
| 6517 | if (check_VecOperands (t) || VEX_check_operands (t)) |
| 6518 | { |
| 6519 | specific_error = i.error; |
| 6520 | continue; |
| 6521 | } |
| 6522 | |
| 6523 | /* We've found a match; break out of loop. */ |
| 6524 | break; |
| 6525 | } |
| 6526 | |
| 6527 | if (t == current_templates->end) |
| 6528 | { |
| 6529 | /* We found no match. */ |
| 6530 | const char *err_msg; |
| 6531 | switch (specific_error ? specific_error : i.error) |
| 6532 | { |
| 6533 | default: |
| 6534 | abort (); |
| 6535 | case operand_size_mismatch: |
| 6536 | err_msg = _("operand size mismatch"); |
| 6537 | break; |
| 6538 | case operand_type_mismatch: |
| 6539 | err_msg = _("operand type mismatch"); |
| 6540 | break; |
| 6541 | case register_type_mismatch: |
| 6542 | err_msg = _("register type mismatch"); |
| 6543 | break; |
| 6544 | case number_of_operands_mismatch: |
| 6545 | err_msg = _("number of operands mismatch"); |
| 6546 | break; |
| 6547 | case invalid_instruction_suffix: |
| 6548 | err_msg = _("invalid instruction suffix"); |
| 6549 | break; |
| 6550 | case bad_imm4: |
| 6551 | err_msg = _("constant doesn't fit in 4 bits"); |
| 6552 | break; |
| 6553 | case unsupported_with_intel_mnemonic: |
| 6554 | err_msg = _("unsupported with Intel mnemonic"); |
| 6555 | break; |
| 6556 | case unsupported_syntax: |
| 6557 | err_msg = _("unsupported syntax"); |
| 6558 | break; |
| 6559 | case unsupported: |
| 6560 | as_bad (_("unsupported instruction `%s'"), |
| 6561 | current_templates->start->name); |
| 6562 | return NULL; |
| 6563 | case invalid_vsib_address: |
| 6564 | err_msg = _("invalid VSIB address"); |
| 6565 | break; |
| 6566 | case invalid_vector_register_set: |
| 6567 | err_msg = _("mask, index, and destination registers must be distinct"); |
| 6568 | break; |
| 6569 | case unsupported_vector_index_register: |
| 6570 | err_msg = _("unsupported vector index register"); |
| 6571 | break; |
| 6572 | case unsupported_broadcast: |
| 6573 | err_msg = _("unsupported broadcast"); |
| 6574 | break; |
| 6575 | case broadcast_needed: |
| 6576 | err_msg = _("broadcast is needed for operand of such type"); |
| 6577 | break; |
| 6578 | case unsupported_masking: |
| 6579 | err_msg = _("unsupported masking"); |
| 6580 | break; |
| 6581 | case mask_not_on_destination: |
| 6582 | err_msg = _("mask not on destination operand"); |
| 6583 | break; |
| 6584 | case no_default_mask: |
| 6585 | err_msg = _("default mask isn't allowed"); |
| 6586 | break; |
| 6587 | case unsupported_rc_sae: |
| 6588 | err_msg = _("unsupported static rounding/sae"); |
| 6589 | break; |
| 6590 | case rc_sae_operand_not_last_imm: |
| 6591 | if (intel_syntax) |
| 6592 | err_msg = _("RC/SAE operand must precede immediate operands"); |
| 6593 | else |
| 6594 | err_msg = _("RC/SAE operand must follow immediate operands"); |
| 6595 | break; |
| 6596 | case invalid_register_operand: |
| 6597 | err_msg = _("invalid register operand"); |
| 6598 | break; |
| 6599 | } |
| 6600 | as_bad (_("%s for `%s'"), err_msg, |
| 6601 | current_templates->start->name); |
| 6602 | return NULL; |
| 6603 | } |
| 6604 | |
| 6605 | if (!quiet_warnings) |
| 6606 | { |
| 6607 | if (!intel_syntax |
| 6608 | && (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))) |
| 6609 | as_warn (_("indirect %s without `*'"), t->name); |
| 6610 | |
| 6611 | if (t->opcode_modifier.isprefix |
| 6612 | && t->opcode_modifier.mnemonicsize == IGNORESIZE) |
| 6613 | { |
| 6614 | /* Warn them that a data or address size prefix doesn't |
| 6615 | affect assembly of the next line of code. */ |
| 6616 | as_warn (_("stand-alone `%s' prefix"), t->name); |
| 6617 | } |
| 6618 | } |
| 6619 | |
| 6620 | /* Copy the template we found. */ |
| 6621 | i.tm = *t; |
| 6622 | |
| 6623 | if (addr_prefix_disp != -1) |
| 6624 | i.tm.operand_types[addr_prefix_disp] |
| 6625 | = operand_types[addr_prefix_disp]; |
| 6626 | |
| 6627 | if (found_reverse_match) |
| 6628 | { |
| 6629 | /* If we found a reverse match we must alter the opcode direction |
| 6630 | bit and clear/flip the regmem modifier one. found_reverse_match |
| 6631 | holds bits to change (different for int & float insns). */ |
| 6632 | |
| 6633 | i.tm.base_opcode ^= found_reverse_match; |
| 6634 | |
| 6635 | i.tm.operand_types[0] = operand_types[i.operands - 1]; |
| 6636 | i.tm.operand_types[i.operands - 1] = operand_types[0]; |
| 6637 | |
| 6638 | /* Certain SIMD insns have their load forms specified in the opcode |
| 6639 | table, and hence we need to _set_ RegMem instead of clearing it. |
| 6640 | We need to avoid setting the bit though on insns like KMOVW. */ |
| 6641 | i.tm.opcode_modifier.regmem |
| 6642 | = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d |
| 6643 | && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx |
| 6644 | && !i.tm.opcode_modifier.regmem; |
| 6645 | } |
| 6646 | |
| 6647 | return t; |
| 6648 | } |
| 6649 | |
| 6650 | static int |
| 6651 | check_string (void) |
| 6652 | { |
| 6653 | unsigned int es_op = i.tm.opcode_modifier.isstring - IS_STRING_ES_OP0; |
| 6654 | unsigned int op = i.tm.operand_types[0].bitfield.baseindex ? es_op : 0; |
| 6655 | |
| 6656 | if (i.seg[op] != NULL && i.seg[op] != &es) |
| 6657 | { |
| 6658 | as_bad (_("`%s' operand %u must use `%ses' segment"), |
| 6659 | i.tm.name, |
| 6660 | intel_syntax ? i.tm.operands - es_op : es_op + 1, |
| 6661 | register_prefix); |
| 6662 | return 0; |
| 6663 | } |
| 6664 | |
| 6665 | /* There's only ever one segment override allowed per instruction. |
| 6666 | This instruction possibly has a legal segment override on the |
| 6667 | second operand, so copy the segment to where non-string |
| 6668 | instructions store it, allowing common code. */ |
| 6669 | i.seg[op] = i.seg[1]; |
| 6670 | |
| 6671 | return 1; |
| 6672 | } |
| 6673 | |
| 6674 | static int |
| 6675 | process_suffix (void) |
| 6676 | { |
| 6677 | /* If matched instruction specifies an explicit instruction mnemonic |
| 6678 | suffix, use it. */ |
| 6679 | if (i.tm.opcode_modifier.size == SIZE16) |
| 6680 | i.suffix = WORD_MNEM_SUFFIX; |
| 6681 | else if (i.tm.opcode_modifier.size == SIZE32) |
| 6682 | i.suffix = LONG_MNEM_SUFFIX; |
| 6683 | else if (i.tm.opcode_modifier.size == SIZE64) |
| 6684 | i.suffix = QWORD_MNEM_SUFFIX; |
| 6685 | else if (i.reg_operands |
| 6686 | && (i.operands > 1 || i.types[0].bitfield.class == Reg) |
| 6687 | && !i.tm.opcode_modifier.addrprefixopreg) |
| 6688 | { |
| 6689 | unsigned int numop = i.operands; |
| 6690 | |
| 6691 | /* movsx/movzx want only their source operand considered here, for the |
| 6692 | ambiguity checking below. The suffix will be replaced afterwards |
| 6693 | to represent the destination (register). */ |
| 6694 | if (((i.tm.base_opcode | 8) == 0xfbe && i.tm.opcode_modifier.w) |
| 6695 | || (i.tm.base_opcode == 0x63 && i.tm.cpu_flags.bitfield.cpu64)) |
| 6696 | --i.operands; |
| 6697 | |
| 6698 | /* crc32 needs REX.W set regardless of suffix / source operand size. */ |
| 6699 | if (i.tm.base_opcode == 0xf20f38f0 |
| 6700 | && i.tm.operand_types[1].bitfield.qword) |
| 6701 | i.rex |= REX_W; |
| 6702 | |
| 6703 | /* If there's no instruction mnemonic suffix we try to invent one |
| 6704 | based on GPR operands. */ |
| 6705 | if (!i.suffix) |
| 6706 | { |
| 6707 | /* We take i.suffix from the last register operand specified, |
| 6708 | Destination register type is more significant than source |
| 6709 | register type. crc32 in SSE4.2 prefers source register |
| 6710 | type. */ |
| 6711 | unsigned int op = i.tm.base_opcode != 0xf20f38f0 ? i.operands : 1; |
| 6712 | |
| 6713 | while (op--) |
| 6714 | if (i.tm.operand_types[op].bitfield.instance == InstanceNone |
| 6715 | || i.tm.operand_types[op].bitfield.instance == Accum) |
| 6716 | { |
| 6717 | if (i.types[op].bitfield.class != Reg) |
| 6718 | continue; |
| 6719 | if (i.types[op].bitfield.byte) |
| 6720 | i.suffix = BYTE_MNEM_SUFFIX; |
| 6721 | else if (i.types[op].bitfield.word) |
| 6722 | i.suffix = WORD_MNEM_SUFFIX; |
| 6723 | else if (i.types[op].bitfield.dword) |
| 6724 | i.suffix = LONG_MNEM_SUFFIX; |
| 6725 | else if (i.types[op].bitfield.qword) |
| 6726 | i.suffix = QWORD_MNEM_SUFFIX; |
| 6727 | else |
| 6728 | continue; |
| 6729 | break; |
| 6730 | } |
| 6731 | |
| 6732 | /* As an exception, movsx/movzx silently default to a byte source |
| 6733 | in AT&T mode. */ |
| 6734 | if ((i.tm.base_opcode | 8) == 0xfbe && i.tm.opcode_modifier.w |
| 6735 | && !i.suffix && !intel_syntax) |
| 6736 | i.suffix = BYTE_MNEM_SUFFIX; |
| 6737 | } |
| 6738 | else if (i.suffix == BYTE_MNEM_SUFFIX) |
| 6739 | { |
| 6740 | if (intel_syntax |
| 6741 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
| 6742 | && i.tm.opcode_modifier.no_bsuf) |
| 6743 | i.suffix = 0; |
| 6744 | else if (!check_byte_reg ()) |
| 6745 | return 0; |
| 6746 | } |
| 6747 | else if (i.suffix == LONG_MNEM_SUFFIX) |
| 6748 | { |
| 6749 | if (intel_syntax |
| 6750 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
| 6751 | && i.tm.opcode_modifier.no_lsuf |
| 6752 | && !i.tm.opcode_modifier.todword |
| 6753 | && !i.tm.opcode_modifier.toqword) |
| 6754 | i.suffix = 0; |
| 6755 | else if (!check_long_reg ()) |
| 6756 | return 0; |
| 6757 | } |
| 6758 | else if (i.suffix == QWORD_MNEM_SUFFIX) |
| 6759 | { |
| 6760 | if (intel_syntax |
| 6761 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
| 6762 | && i.tm.opcode_modifier.no_qsuf |
| 6763 | && !i.tm.opcode_modifier.todword |
| 6764 | && !i.tm.opcode_modifier.toqword) |
| 6765 | i.suffix = 0; |
| 6766 | else if (!check_qword_reg ()) |
| 6767 | return 0; |
| 6768 | } |
| 6769 | else if (i.suffix == WORD_MNEM_SUFFIX) |
| 6770 | { |
| 6771 | if (intel_syntax |
| 6772 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
| 6773 | && i.tm.opcode_modifier.no_wsuf) |
| 6774 | i.suffix = 0; |
| 6775 | else if (!check_word_reg ()) |
| 6776 | return 0; |
| 6777 | } |
| 6778 | else if (intel_syntax |
| 6779 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE) |
| 6780 | /* Do nothing if the instruction is going to ignore the prefix. */ |
| 6781 | ; |
| 6782 | else |
| 6783 | abort (); |
| 6784 | |
| 6785 | /* Undo the movsx/movzx change done above. */ |
| 6786 | i.operands = numop; |
| 6787 | } |
| 6788 | else if (i.tm.opcode_modifier.mnemonicsize == DEFAULTSIZE |
| 6789 | && !i.suffix) |
| 6790 | { |
| 6791 | i.suffix = stackop_size; |
| 6792 | if (stackop_size == LONG_MNEM_SUFFIX) |
| 6793 | { |
| 6794 | /* stackop_size is set to LONG_MNEM_SUFFIX for the |
| 6795 | .code16gcc directive to support 16-bit mode with |
| 6796 | 32-bit address. For IRET without a suffix, generate |
| 6797 | 16-bit IRET (opcode 0xcf) to return from an interrupt |
| 6798 | handler. */ |
| 6799 | if (i.tm.base_opcode == 0xcf) |
| 6800 | { |
| 6801 | i.suffix = WORD_MNEM_SUFFIX; |
| 6802 | as_warn (_("generating 16-bit `iret' for .code16gcc directive")); |
| 6803 | } |
| 6804 | /* Warn about changed behavior for segment register push/pop. */ |
| 6805 | else if ((i.tm.base_opcode | 1) == 0x07) |
| 6806 | as_warn (_("generating 32-bit `%s', unlike earlier gas versions"), |
| 6807 | i.tm.name); |
| 6808 | } |
| 6809 | } |
| 6810 | else if (!i.suffix |
| 6811 | && (i.tm.opcode_modifier.jump == JUMP_ABSOLUTE |
| 6812 | || i.tm.opcode_modifier.jump == JUMP_BYTE |
| 6813 | || i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT |
| 6814 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
| 6815 | && i.tm.extension_opcode <= 3))) |
| 6816 | { |
| 6817 | switch (flag_code) |
| 6818 | { |
| 6819 | case CODE_64BIT: |
| 6820 | if (!i.tm.opcode_modifier.no_qsuf) |
| 6821 | { |
| 6822 | i.suffix = QWORD_MNEM_SUFFIX; |
| 6823 | break; |
| 6824 | } |
| 6825 | /* Fall through. */ |
| 6826 | case CODE_32BIT: |
| 6827 | if (!i.tm.opcode_modifier.no_lsuf) |
| 6828 | i.suffix = LONG_MNEM_SUFFIX; |
| 6829 | break; |
| 6830 | case CODE_16BIT: |
| 6831 | if (!i.tm.opcode_modifier.no_wsuf) |
| 6832 | i.suffix = WORD_MNEM_SUFFIX; |
| 6833 | break; |
| 6834 | } |
| 6835 | } |
| 6836 | |
| 6837 | if (!i.suffix |
| 6838 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
| 6839 | /* Also cover lret/retf/iret in 64-bit mode. */ |
| 6840 | || (flag_code == CODE_64BIT |
| 6841 | && !i.tm.opcode_modifier.no_lsuf |
| 6842 | && !i.tm.opcode_modifier.no_qsuf)) |
| 6843 | && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
| 6844 | /* Accept FLDENV et al without suffix. */ |
| 6845 | && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf)) |
| 6846 | { |
| 6847 | unsigned int suffixes, evex = 0; |
| 6848 | |
| 6849 | suffixes = !i.tm.opcode_modifier.no_bsuf; |
| 6850 | if (!i.tm.opcode_modifier.no_wsuf) |
| 6851 | suffixes |= 1 << 1; |
| 6852 | if (!i.tm.opcode_modifier.no_lsuf) |
| 6853 | suffixes |= 1 << 2; |
| 6854 | if (!i.tm.opcode_modifier.no_ldsuf) |
| 6855 | suffixes |= 1 << 3; |
| 6856 | if (!i.tm.opcode_modifier.no_ssuf) |
| 6857 | suffixes |= 1 << 4; |
| 6858 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) |
| 6859 | suffixes |= 1 << 5; |
| 6860 | |
| 6861 | /* For [XYZ]MMWORD operands inspect operand sizes. While generally |
| 6862 | also suitable for AT&T syntax mode, it was requested that this be |
| 6863 | restricted to just Intel syntax. */ |
| 6864 | if (intel_syntax && is_any_vex_encoding (&i.tm) && !i.broadcast) |
| 6865 | { |
| 6866 | unsigned int op; |
| 6867 | |
| 6868 | for (op = 0; op < i.tm.operands; ++op) |
| 6869 | { |
| 6870 | if (is_evex_encoding (&i.tm) |
| 6871 | && !cpu_arch_flags.bitfield.cpuavx512vl) |
| 6872 | { |
| 6873 | if (i.tm.operand_types[op].bitfield.ymmword) |
| 6874 | i.tm.operand_types[op].bitfield.xmmword = 0; |
| 6875 | if (i.tm.operand_types[op].bitfield.zmmword) |
| 6876 | i.tm.operand_types[op].bitfield.ymmword = 0; |
| 6877 | if (!i.tm.opcode_modifier.evex |
| 6878 | || i.tm.opcode_modifier.evex == EVEXDYN) |
| 6879 | i.tm.opcode_modifier.evex = EVEX512; |
| 6880 | } |
| 6881 | |
| 6882 | if (i.tm.operand_types[op].bitfield.xmmword |
| 6883 | + i.tm.operand_types[op].bitfield.ymmword |
| 6884 | + i.tm.operand_types[op].bitfield.zmmword < 2) |
| 6885 | continue; |
| 6886 | |
| 6887 | /* Any properly sized operand disambiguates the insn. */ |
| 6888 | if (i.types[op].bitfield.xmmword |
| 6889 | || i.types[op].bitfield.ymmword |
| 6890 | || i.types[op].bitfield.zmmword) |
| 6891 | { |
| 6892 | suffixes &= ~(7 << 6); |
| 6893 | evex = 0; |
| 6894 | break; |
| 6895 | } |
| 6896 | |
| 6897 | if ((i.flags[op] & Operand_Mem) |
| 6898 | && i.tm.operand_types[op].bitfield.unspecified) |
| 6899 | { |
| 6900 | if (i.tm.operand_types[op].bitfield.xmmword) |
| 6901 | suffixes |= 1 << 6; |
| 6902 | if (i.tm.operand_types[op].bitfield.ymmword) |
| 6903 | suffixes |= 1 << 7; |
| 6904 | if (i.tm.operand_types[op].bitfield.zmmword) |
| 6905 | suffixes |= 1 << 8; |
| 6906 | if (is_evex_encoding (&i.tm)) |
| 6907 | evex = EVEX512; |
| 6908 | } |
| 6909 | } |
| 6910 | } |
| 6911 | |
| 6912 | /* Are multiple suffixes / operand sizes allowed? */ |
| 6913 | if (suffixes & (suffixes - 1)) |
| 6914 | { |
| 6915 | if (intel_syntax |
| 6916 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
| 6917 | || operand_check == check_error)) |
| 6918 | { |
| 6919 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
| 6920 | return 0; |
| 6921 | } |
| 6922 | if (operand_check == check_error) |
| 6923 | { |
| 6924 | as_bad (_("no instruction mnemonic suffix given and " |
| 6925 | "no register operands; can't size `%s'"), i.tm.name); |
| 6926 | return 0; |
| 6927 | } |
| 6928 | if (operand_check == check_warning) |
| 6929 | as_warn (_("%s; using default for `%s'"), |
| 6930 | intel_syntax |
| 6931 | ? _("ambiguous operand size") |
| 6932 | : _("no instruction mnemonic suffix given and " |
| 6933 | "no register operands"), |
| 6934 | i.tm.name); |
| 6935 | |
| 6936 | if (i.tm.opcode_modifier.floatmf) |
| 6937 | i.suffix = SHORT_MNEM_SUFFIX; |
| 6938 | else if ((i.tm.base_opcode | 8) == 0xfbe |
| 6939 | || (i.tm.base_opcode == 0x63 |
| 6940 | && i.tm.cpu_flags.bitfield.cpu64)) |
| 6941 | /* handled below */; |
| 6942 | else if (evex) |
| 6943 | i.tm.opcode_modifier.evex = evex; |
| 6944 | else if (flag_code == CODE_16BIT) |
| 6945 | i.suffix = WORD_MNEM_SUFFIX; |
| 6946 | else if (!i.tm.opcode_modifier.no_lsuf) |
| 6947 | i.suffix = LONG_MNEM_SUFFIX; |
| 6948 | else |
| 6949 | i.suffix = QWORD_MNEM_SUFFIX; |
| 6950 | } |
| 6951 | } |
| 6952 | |
| 6953 | if ((i.tm.base_opcode | 8) == 0xfbe |
| 6954 | || (i.tm.base_opcode == 0x63 && i.tm.cpu_flags.bitfield.cpu64)) |
| 6955 | { |
| 6956 | /* In Intel syntax, movsx/movzx must have a "suffix" (checked above). |
| 6957 | In AT&T syntax, if there is no suffix (warned about above), the default |
| 6958 | will be byte extension. */ |
| 6959 | if (i.tm.opcode_modifier.w && i.suffix && i.suffix != BYTE_MNEM_SUFFIX) |
| 6960 | i.tm.base_opcode |= 1; |
| 6961 | |
| 6962 | /* For further processing, the suffix should represent the destination |
| 6963 | (register). This is already the case when one was used with |
| 6964 | mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was |
| 6965 | no suffix to begin with. */ |
| 6966 | if (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63 || !i.suffix) |
| 6967 | { |
| 6968 | if (i.types[1].bitfield.word) |
| 6969 | i.suffix = WORD_MNEM_SUFFIX; |
| 6970 | else if (i.types[1].bitfield.qword) |
| 6971 | i.suffix = QWORD_MNEM_SUFFIX; |
| 6972 | else |
| 6973 | i.suffix = LONG_MNEM_SUFFIX; |
| 6974 | |
| 6975 | i.tm.opcode_modifier.w = 0; |
| 6976 | } |
| 6977 | } |
| 6978 | |
| 6979 | if (!i.tm.opcode_modifier.modrm && i.reg_operands && i.tm.operands < 3) |
| 6980 | i.short_form = (i.tm.operand_types[0].bitfield.class == Reg) |
| 6981 | != (i.tm.operand_types[1].bitfield.class == Reg); |
| 6982 | |
| 6983 | /* Change the opcode based on the operand size given by i.suffix. */ |
| 6984 | switch (i.suffix) |
| 6985 | { |
| 6986 | /* Size floating point instruction. */ |
| 6987 | case LONG_MNEM_SUFFIX: |
| 6988 | if (i.tm.opcode_modifier.floatmf) |
| 6989 | { |
| 6990 | i.tm.base_opcode ^= 4; |
| 6991 | break; |
| 6992 | } |
| 6993 | /* fall through */ |
| 6994 | case WORD_MNEM_SUFFIX: |
| 6995 | case QWORD_MNEM_SUFFIX: |
| 6996 | /* It's not a byte, select word/dword operation. */ |
| 6997 | if (i.tm.opcode_modifier.w) |
| 6998 | { |
| 6999 | if (i.short_form) |
| 7000 | i.tm.base_opcode |= 8; |
| 7001 | else |
| 7002 | i.tm.base_opcode |= 1; |
| 7003 | } |
| 7004 | /* fall through */ |
| 7005 | case SHORT_MNEM_SUFFIX: |
| 7006 | /* Now select between word & dword operations via the operand |
| 7007 | size prefix, except for instructions that will ignore this |
| 7008 | prefix anyway. */ |
| 7009 | if (i.suffix != QWORD_MNEM_SUFFIX |
| 7010 | && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
| 7011 | && !i.tm.opcode_modifier.floatmf |
| 7012 | && !is_any_vex_encoding (&i.tm) |
| 7013 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
| 7014 | || (flag_code == CODE_64BIT |
| 7015 | && i.tm.opcode_modifier.jump == JUMP_BYTE))) |
| 7016 | { |
| 7017 | unsigned int prefix = DATA_PREFIX_OPCODE; |
| 7018 | |
| 7019 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) /* jcxz, loop */ |
| 7020 | prefix = ADDR_PREFIX_OPCODE; |
| 7021 | |
| 7022 | if (!add_prefix (prefix)) |
| 7023 | return 0; |
| 7024 | } |
| 7025 | |
| 7026 | /* Set mode64 for an operand. */ |
| 7027 | if (i.suffix == QWORD_MNEM_SUFFIX |
| 7028 | && flag_code == CODE_64BIT |
| 7029 | && !i.tm.opcode_modifier.norex64 |
| 7030 | && !i.tm.opcode_modifier.vexw |
| 7031 | /* Special case for xchg %rax,%rax. It is NOP and doesn't |
| 7032 | need rex64. */ |
| 7033 | && ! (i.operands == 2 |
| 7034 | && i.tm.base_opcode == 0x90 |
| 7035 | && i.tm.extension_opcode == None |
| 7036 | && i.types[0].bitfield.instance == Accum |
| 7037 | && i.types[0].bitfield.qword |
| 7038 | && i.types[1].bitfield.instance == Accum |
| 7039 | && i.types[1].bitfield.qword)) |
| 7040 | i.rex |= REX_W; |
| 7041 | |
| 7042 | break; |
| 7043 | } |
| 7044 | |
| 7045 | if (i.tm.opcode_modifier.addrprefixopreg) |
| 7046 | { |
| 7047 | gas_assert (!i.suffix); |
| 7048 | gas_assert (i.reg_operands); |
| 7049 | |
| 7050 | if (i.tm.operand_types[0].bitfield.instance == Accum |
| 7051 | || i.operands == 1) |
| 7052 | { |
| 7053 | /* The address size override prefix changes the size of the |
| 7054 | first operand. */ |
| 7055 | if (flag_code == CODE_64BIT |
| 7056 | && i.op[0].regs->reg_type.bitfield.word) |
| 7057 | { |
| 7058 | as_bad (_("16-bit addressing unavailable for `%s'"), |
| 7059 | i.tm.name); |
| 7060 | return 0; |
| 7061 | } |
| 7062 | |
| 7063 | if ((flag_code == CODE_32BIT |
| 7064 | ? i.op[0].regs->reg_type.bitfield.word |
| 7065 | : i.op[0].regs->reg_type.bitfield.dword) |
| 7066 | && !add_prefix (ADDR_PREFIX_OPCODE)) |
| 7067 | return 0; |
| 7068 | } |
| 7069 | else |
| 7070 | { |
| 7071 | /* Check invalid register operand when the address size override |
| 7072 | prefix changes the size of register operands. */ |
| 7073 | unsigned int op; |
| 7074 | enum { need_word, need_dword, need_qword } need; |
| 7075 | |
| 7076 | if (flag_code == CODE_32BIT) |
| 7077 | need = i.prefix[ADDR_PREFIX] ? need_word : need_dword; |
| 7078 | else if (i.prefix[ADDR_PREFIX]) |
| 7079 | need = need_dword; |
| 7080 | else |
| 7081 | need = flag_code == CODE_64BIT ? need_qword : need_word; |
| 7082 | |
| 7083 | for (op = 0; op < i.operands; op++) |
| 7084 | { |
| 7085 | if (i.types[op].bitfield.class != Reg) |
| 7086 | continue; |
| 7087 | |
| 7088 | switch (need) |
| 7089 | { |
| 7090 | case need_word: |
| 7091 | if (i.op[op].regs->reg_type.bitfield.word) |
| 7092 | continue; |
| 7093 | break; |
| 7094 | case need_dword: |
| 7095 | if (i.op[op].regs->reg_type.bitfield.dword) |
| 7096 | continue; |
| 7097 | break; |
| 7098 | case need_qword: |
| 7099 | if (i.op[op].regs->reg_type.bitfield.qword) |
| 7100 | continue; |
| 7101 | break; |
| 7102 | } |
| 7103 | |
| 7104 | as_bad (_("invalid register operand size for `%s'"), |
| 7105 | i.tm.name); |
| 7106 | return 0; |
| 7107 | } |
| 7108 | } |
| 7109 | } |
| 7110 | |
| 7111 | return 1; |
| 7112 | } |
| 7113 | |
| 7114 | static int |
| 7115 | check_byte_reg (void) |
| 7116 | { |
| 7117 | int op; |
| 7118 | |
| 7119 | for (op = i.operands; --op >= 0;) |
| 7120 | { |
| 7121 | /* Skip non-register operands. */ |
| 7122 | if (i.types[op].bitfield.class != Reg) |
| 7123 | continue; |
| 7124 | |
| 7125 | /* If this is an eight bit register, it's OK. If it's the 16 or |
| 7126 | 32 bit version of an eight bit register, we will just use the |
| 7127 | low portion, and that's OK too. */ |
| 7128 | if (i.types[op].bitfield.byte) |
| 7129 | continue; |
| 7130 | |
| 7131 | /* I/O port address operands are OK too. */ |
| 7132 | if (i.tm.operand_types[op].bitfield.instance == RegD |
| 7133 | && i.tm.operand_types[op].bitfield.word) |
| 7134 | continue; |
| 7135 | |
| 7136 | /* crc32 only wants its source operand checked here. */ |
| 7137 | if (i.tm.base_opcode == 0xf20f38f0 && op) |
| 7138 | continue; |
| 7139 | |
| 7140 | /* Any other register is bad. */ |
| 7141 | if (i.types[op].bitfield.class == Reg |
| 7142 | || i.types[op].bitfield.class == RegMMX |
| 7143 | || i.types[op].bitfield.class == RegSIMD |
| 7144 | || i.types[op].bitfield.class == SReg |
| 7145 | || i.types[op].bitfield.class == RegCR |
| 7146 | || i.types[op].bitfield.class == RegDR |
| 7147 | || i.types[op].bitfield.class == RegTR) |
| 7148 | { |
| 7149 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
| 7150 | register_prefix, |
| 7151 | i.op[op].regs->reg_name, |
| 7152 | i.tm.name, |
| 7153 | i.suffix); |
| 7154 | return 0; |
| 7155 | } |
| 7156 | } |
| 7157 | return 1; |
| 7158 | } |
| 7159 | |
| 7160 | static int |
| 7161 | check_long_reg (void) |
| 7162 | { |
| 7163 | int op; |
| 7164 | |
| 7165 | for (op = i.operands; --op >= 0;) |
| 7166 | /* Skip non-register operands. */ |
| 7167 | if (i.types[op].bitfield.class != Reg) |
| 7168 | continue; |
| 7169 | /* Reject eight bit registers, except where the template requires |
| 7170 | them. (eg. movzb) */ |
| 7171 | else if (i.types[op].bitfield.byte |
| 7172 | && (i.tm.operand_types[op].bitfield.class == Reg |
| 7173 | || i.tm.operand_types[op].bitfield.instance == Accum) |
| 7174 | && (i.tm.operand_types[op].bitfield.word |
| 7175 | || i.tm.operand_types[op].bitfield.dword)) |
| 7176 | { |
| 7177 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
| 7178 | register_prefix, |
| 7179 | i.op[op].regs->reg_name, |
| 7180 | i.tm.name, |
| 7181 | i.suffix); |
| 7182 | return 0; |
| 7183 | } |
| 7184 | /* Error if the e prefix on a general reg is missing. */ |
| 7185 | else if (i.types[op].bitfield.word |
| 7186 | && (i.tm.operand_types[op].bitfield.class == Reg |
| 7187 | || i.tm.operand_types[op].bitfield.instance == Accum) |
| 7188 | && i.tm.operand_types[op].bitfield.dword) |
| 7189 | { |
| 7190 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
| 7191 | register_prefix, i.op[op].regs->reg_name, |
| 7192 | i.suffix); |
| 7193 | return 0; |
| 7194 | } |
| 7195 | /* Warn if the r prefix on a general reg is present. */ |
| 7196 | else if (i.types[op].bitfield.qword |
| 7197 | && (i.tm.operand_types[op].bitfield.class == Reg |
| 7198 | || i.tm.operand_types[op].bitfield.instance == Accum) |
| 7199 | && i.tm.operand_types[op].bitfield.dword) |
| 7200 | { |
| 7201 | if (intel_syntax |
| 7202 | && i.tm.opcode_modifier.toqword |
| 7203 | && i.types[0].bitfield.class != RegSIMD) |
| 7204 | { |
| 7205 | /* Convert to QWORD. We want REX byte. */ |
| 7206 | i.suffix = QWORD_MNEM_SUFFIX; |
| 7207 | } |
| 7208 | else |
| 7209 | { |
| 7210 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
| 7211 | register_prefix, i.op[op].regs->reg_name, |
| 7212 | i.suffix); |
| 7213 | return 0; |
| 7214 | } |
| 7215 | } |
| 7216 | return 1; |
| 7217 | } |
| 7218 | |
| 7219 | static int |
| 7220 | check_qword_reg (void) |
| 7221 | { |
| 7222 | int op; |
| 7223 | |
| 7224 | for (op = i.operands; --op >= 0; ) |
| 7225 | /* Skip non-register operands. */ |
| 7226 | if (i.types[op].bitfield.class != Reg) |
| 7227 | continue; |
| 7228 | /* Reject eight bit registers, except where the template requires |
| 7229 | them. (eg. movzb) */ |
| 7230 | else if (i.types[op].bitfield.byte |
| 7231 | && (i.tm.operand_types[op].bitfield.class == Reg |
| 7232 | || i.tm.operand_types[op].bitfield.instance == Accum) |
| 7233 | && (i.tm.operand_types[op].bitfield.word |
| 7234 | || i.tm.operand_types[op].bitfield.dword)) |
| 7235 | { |
| 7236 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
| 7237 | register_prefix, |
| 7238 | i.op[op].regs->reg_name, |
| 7239 | i.tm.name, |
| 7240 | i.suffix); |
| 7241 | return 0; |
| 7242 | } |
| 7243 | /* Warn if the r prefix on a general reg is missing. */ |
| 7244 | else if ((i.types[op].bitfield.word |
| 7245 | || i.types[op].bitfield.dword) |
| 7246 | && (i.tm.operand_types[op].bitfield.class == Reg |
| 7247 | || i.tm.operand_types[op].bitfield.instance == Accum) |
| 7248 | && i.tm.operand_types[op].bitfield.qword) |
| 7249 | { |
| 7250 | /* Prohibit these changes in the 64bit mode, since the |
| 7251 | lowering is more complicated. */ |
| 7252 | if (intel_syntax |
| 7253 | && i.tm.opcode_modifier.todword |
| 7254 | && i.types[0].bitfield.class != RegSIMD) |
| 7255 | { |
| 7256 | /* Convert to DWORD. We don't want REX byte. */ |
| 7257 | i.suffix = LONG_MNEM_SUFFIX; |
| 7258 | } |
| 7259 | else |
| 7260 | { |
| 7261 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
| 7262 | register_prefix, i.op[op].regs->reg_name, |
| 7263 | i.suffix); |
| 7264 | return 0; |
| 7265 | } |
| 7266 | } |
| 7267 | return 1; |
| 7268 | } |
| 7269 | |
| 7270 | static int |
| 7271 | check_word_reg (void) |
| 7272 | { |
| 7273 | int op; |
| 7274 | for (op = i.operands; --op >= 0;) |
| 7275 | /* Skip non-register operands. */ |
| 7276 | if (i.types[op].bitfield.class != Reg) |
| 7277 | continue; |
| 7278 | /* Reject eight bit registers, except where the template requires |
| 7279 | them. (eg. movzb) */ |
| 7280 | else if (i.types[op].bitfield.byte |
| 7281 | && (i.tm.operand_types[op].bitfield.class == Reg |
| 7282 | || i.tm.operand_types[op].bitfield.instance == Accum) |
| 7283 | && (i.tm.operand_types[op].bitfield.word |
| 7284 | || i.tm.operand_types[op].bitfield.dword)) |
| 7285 | { |
| 7286 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
| 7287 | register_prefix, |
| 7288 | i.op[op].regs->reg_name, |
| 7289 | i.tm.name, |
| 7290 | i.suffix); |
| 7291 | return 0; |
| 7292 | } |
| 7293 | /* Error if the e or r prefix on a general reg is present. */ |
| 7294 | else if ((i.types[op].bitfield.dword |
| 7295 | || i.types[op].bitfield.qword) |
| 7296 | && (i.tm.operand_types[op].bitfield.class == Reg |
| 7297 | || i.tm.operand_types[op].bitfield.instance == Accum) |
| 7298 | && i.tm.operand_types[op].bitfield.word) |
| 7299 | { |
| 7300 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
| 7301 | register_prefix, i.op[op].regs->reg_name, |
| 7302 | i.suffix); |
| 7303 | return 0; |
| 7304 | } |
| 7305 | return 1; |
| 7306 | } |
| 7307 | |
| 7308 | static int |
| 7309 | update_imm (unsigned int j) |
| 7310 | { |
| 7311 | i386_operand_type overlap = i.types[j]; |
| 7312 | if ((overlap.bitfield.imm8 |
| 7313 | || overlap.bitfield.imm8s |
| 7314 | || overlap.bitfield.imm16 |
| 7315 | || overlap.bitfield.imm32 |
| 7316 | || overlap.bitfield.imm32s |
| 7317 | || overlap.bitfield.imm64) |
| 7318 | && !operand_type_equal (&overlap, &imm8) |
| 7319 | && !operand_type_equal (&overlap, &imm8s) |
| 7320 | && !operand_type_equal (&overlap, &imm16) |
| 7321 | && !operand_type_equal (&overlap, &imm32) |
| 7322 | && !operand_type_equal (&overlap, &imm32s) |
| 7323 | && !operand_type_equal (&overlap, &imm64)) |
| 7324 | { |
| 7325 | if (i.suffix) |
| 7326 | { |
| 7327 | i386_operand_type temp; |
| 7328 | |
| 7329 | operand_type_set (&temp, 0); |
| 7330 | if (i.suffix == BYTE_MNEM_SUFFIX) |
| 7331 | { |
| 7332 | temp.bitfield.imm8 = overlap.bitfield.imm8; |
| 7333 | temp.bitfield.imm8s = overlap.bitfield.imm8s; |
| 7334 | } |
| 7335 | else if (i.suffix == WORD_MNEM_SUFFIX) |
| 7336 | temp.bitfield.imm16 = overlap.bitfield.imm16; |
| 7337 | else if (i.suffix == QWORD_MNEM_SUFFIX) |
| 7338 | { |
| 7339 | temp.bitfield.imm64 = overlap.bitfield.imm64; |
| 7340 | temp.bitfield.imm32s = overlap.bitfield.imm32s; |
| 7341 | } |
| 7342 | else |
| 7343 | temp.bitfield.imm32 = overlap.bitfield.imm32; |
| 7344 | overlap = temp; |
| 7345 | } |
| 7346 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
| 7347 | || operand_type_equal (&overlap, &imm16_32) |
| 7348 | || operand_type_equal (&overlap, &imm16_32s)) |
| 7349 | { |
| 7350 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
| 7351 | overlap = imm16; |
| 7352 | else |
| 7353 | overlap = imm32s; |
| 7354 | } |
| 7355 | if (!operand_type_equal (&overlap, &imm8) |
| 7356 | && !operand_type_equal (&overlap, &imm8s) |
| 7357 | && !operand_type_equal (&overlap, &imm16) |
| 7358 | && !operand_type_equal (&overlap, &imm32) |
| 7359 | && !operand_type_equal (&overlap, &imm32s) |
| 7360 | && !operand_type_equal (&overlap, &imm64)) |
| 7361 | { |
| 7362 | as_bad (_("no instruction mnemonic suffix given; " |
| 7363 | "can't determine immediate size")); |
| 7364 | return 0; |
| 7365 | } |
| 7366 | } |
| 7367 | i.types[j] = overlap; |
| 7368 | |
| 7369 | return 1; |
| 7370 | } |
| 7371 | |
| 7372 | static int |
| 7373 | finalize_imm (void) |
| 7374 | { |
| 7375 | unsigned int j, n; |
| 7376 | |
| 7377 | /* Update the first 2 immediate operands. */ |
| 7378 | n = i.operands > 2 ? 2 : i.operands; |
| 7379 | if (n) |
| 7380 | { |
| 7381 | for (j = 0; j < n; j++) |
| 7382 | if (update_imm (j) == 0) |
| 7383 | return 0; |
| 7384 | |
| 7385 | /* The 3rd operand can't be immediate operand. */ |
| 7386 | gas_assert (operand_type_check (i.types[2], imm) == 0); |
| 7387 | } |
| 7388 | |
| 7389 | return 1; |
| 7390 | } |
| 7391 | |
| 7392 | static int |
| 7393 | process_operands (void) |
| 7394 | { |
| 7395 | /* Default segment register this instruction will use for memory |
| 7396 | accesses. 0 means unknown. This is only for optimizing out |
| 7397 | unnecessary segment overrides. */ |
| 7398 | const seg_entry *default_seg = 0; |
| 7399 | |
| 7400 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
| 7401 | { |
| 7402 | unsigned int dupl = i.operands; |
| 7403 | unsigned int dest = dupl - 1; |
| 7404 | unsigned int j; |
| 7405 | |
| 7406 | /* The destination must be an xmm register. */ |
| 7407 | gas_assert (i.reg_operands |
| 7408 | && MAX_OPERANDS > dupl |
| 7409 | && operand_type_equal (&i.types[dest], ®xmm)); |
| 7410 | |
| 7411 | if (i.tm.operand_types[0].bitfield.instance == Accum |
| 7412 | && i.tm.operand_types[0].bitfield.xmmword) |
| 7413 | { |
| 7414 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
| 7415 | { |
| 7416 | /* Keep xmm0 for instructions with VEX prefix and 3 |
| 7417 | sources. */ |
| 7418 | i.tm.operand_types[0].bitfield.instance = InstanceNone; |
| 7419 | i.tm.operand_types[0].bitfield.class = RegSIMD; |
| 7420 | goto duplicate; |
| 7421 | } |
| 7422 | else |
| 7423 | { |
| 7424 | /* We remove the first xmm0 and keep the number of |
| 7425 | operands unchanged, which in fact duplicates the |
| 7426 | destination. */ |
| 7427 | for (j = 1; j < i.operands; j++) |
| 7428 | { |
| 7429 | i.op[j - 1] = i.op[j]; |
| 7430 | i.types[j - 1] = i.types[j]; |
| 7431 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; |
| 7432 | i.flags[j - 1] = i.flags[j]; |
| 7433 | } |
| 7434 | } |
| 7435 | } |
| 7436 | else if (i.tm.opcode_modifier.implicit1stxmm0) |
| 7437 | { |
| 7438 | gas_assert ((MAX_OPERANDS - 1) > dupl |
| 7439 | && (i.tm.opcode_modifier.vexsources |
| 7440 | == VEX3SOURCES)); |
| 7441 | |
| 7442 | /* Add the implicit xmm0 for instructions with VEX prefix |
| 7443 | and 3 sources. */ |
| 7444 | for (j = i.operands; j > 0; j--) |
| 7445 | { |
| 7446 | i.op[j] = i.op[j - 1]; |
| 7447 | i.types[j] = i.types[j - 1]; |
| 7448 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; |
| 7449 | i.flags[j] = i.flags[j - 1]; |
| 7450 | } |
| 7451 | i.op[0].regs |
| 7452 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); |
| 7453 | i.types[0] = regxmm; |
| 7454 | i.tm.operand_types[0] = regxmm; |
| 7455 | |
| 7456 | i.operands += 2; |
| 7457 | i.reg_operands += 2; |
| 7458 | i.tm.operands += 2; |
| 7459 | |
| 7460 | dupl++; |
| 7461 | dest++; |
| 7462 | i.op[dupl] = i.op[dest]; |
| 7463 | i.types[dupl] = i.types[dest]; |
| 7464 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; |
| 7465 | i.flags[dupl] = i.flags[dest]; |
| 7466 | } |
| 7467 | else |
| 7468 | { |
| 7469 | duplicate: |
| 7470 | i.operands++; |
| 7471 | i.reg_operands++; |
| 7472 | i.tm.operands++; |
| 7473 | |
| 7474 | i.op[dupl] = i.op[dest]; |
| 7475 | i.types[dupl] = i.types[dest]; |
| 7476 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; |
| 7477 | i.flags[dupl] = i.flags[dest]; |
| 7478 | } |
| 7479 | |
| 7480 | if (i.tm.opcode_modifier.immext) |
| 7481 | process_immext (); |
| 7482 | } |
| 7483 | else if (i.tm.operand_types[0].bitfield.instance == Accum |
| 7484 | && i.tm.operand_types[0].bitfield.xmmword) |
| 7485 | { |
| 7486 | unsigned int j; |
| 7487 | |
| 7488 | for (j = 1; j < i.operands; j++) |
| 7489 | { |
| 7490 | i.op[j - 1] = i.op[j]; |
| 7491 | i.types[j - 1] = i.types[j]; |
| 7492 | |
| 7493 | /* We need to adjust fields in i.tm since they are used by |
| 7494 | build_modrm_byte. */ |
| 7495 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; |
| 7496 | |
| 7497 | i.flags[j - 1] = i.flags[j]; |
| 7498 | } |
| 7499 | |
| 7500 | i.operands--; |
| 7501 | i.reg_operands--; |
| 7502 | i.tm.operands--; |
| 7503 | } |
| 7504 | else if (i.tm.opcode_modifier.implicitquadgroup) |
| 7505 | { |
| 7506 | unsigned int regnum, first_reg_in_group, last_reg_in_group; |
| 7507 | |
| 7508 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ |
| 7509 | gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD); |
| 7510 | regnum = register_number (i.op[1].regs); |
| 7511 | first_reg_in_group = regnum & ~3; |
| 7512 | last_reg_in_group = first_reg_in_group + 3; |
| 7513 | if (regnum != first_reg_in_group) |
| 7514 | as_warn (_("source register `%s%s' implicitly denotes" |
| 7515 | " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"), |
| 7516 | register_prefix, i.op[1].regs->reg_name, |
| 7517 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, |
| 7518 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, |
| 7519 | i.tm.name); |
| 7520 | } |
| 7521 | else if (i.tm.opcode_modifier.regkludge) |
| 7522 | { |
| 7523 | /* The imul $imm, %reg instruction is converted into |
| 7524 | imul $imm, %reg, %reg, and the clr %reg instruction |
| 7525 | is converted into xor %reg, %reg. */ |
| 7526 | |
| 7527 | unsigned int first_reg_op; |
| 7528 | |
| 7529 | if (operand_type_check (i.types[0], reg)) |
| 7530 | first_reg_op = 0; |
| 7531 | else |
| 7532 | first_reg_op = 1; |
| 7533 | /* Pretend we saw the extra register operand. */ |
| 7534 | gas_assert (i.reg_operands == 1 |
| 7535 | && i.op[first_reg_op + 1].regs == 0); |
| 7536 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
| 7537 | i.types[first_reg_op + 1] = i.types[first_reg_op]; |
| 7538 | i.operands++; |
| 7539 | i.reg_operands++; |
| 7540 | } |
| 7541 | |
| 7542 | if (i.tm.opcode_modifier.modrm) |
| 7543 | { |
| 7544 | /* The opcode is completed (modulo i.tm.extension_opcode which |
| 7545 | must be put into the modrm byte). Now, we make the modrm and |
| 7546 | index base bytes based on all the info we've collected. */ |
| 7547 | |
| 7548 | default_seg = build_modrm_byte (); |
| 7549 | } |
| 7550 | else if (i.types[0].bitfield.class == SReg) |
| 7551 | { |
| 7552 | if (flag_code != CODE_64BIT |
| 7553 | ? i.tm.base_opcode == POP_SEG_SHORT |
| 7554 | && i.op[0].regs->reg_num == 1 |
| 7555 | : (i.tm.base_opcode | 1) == POP_SEG386_SHORT |
| 7556 | && i.op[0].regs->reg_num < 4) |
| 7557 | { |
| 7558 | as_bad (_("you can't `%s %s%s'"), |
| 7559 | i.tm.name, register_prefix, i.op[0].regs->reg_name); |
| 7560 | return 0; |
| 7561 | } |
| 7562 | if ( i.op[0].regs->reg_num > 3 && i.tm.opcode_length == 1 ) |
| 7563 | { |
| 7564 | i.tm.base_opcode ^= POP_SEG_SHORT ^ POP_SEG386_SHORT; |
| 7565 | i.tm.opcode_length = 2; |
| 7566 | } |
| 7567 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
| 7568 | } |
| 7569 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
| 7570 | { |
| 7571 | default_seg = &ds; |
| 7572 | } |
| 7573 | else if (i.tm.opcode_modifier.isstring) |
| 7574 | { |
| 7575 | /* For the string instructions that allow a segment override |
| 7576 | on one of their operands, the default segment is ds. */ |
| 7577 | default_seg = &ds; |
| 7578 | } |
| 7579 | else if (i.short_form) |
| 7580 | { |
| 7581 | /* The register or float register operand is in operand |
| 7582 | 0 or 1. */ |
| 7583 | unsigned int op = i.tm.operand_types[0].bitfield.class != Reg; |
| 7584 | |
| 7585 | /* Register goes in low 3 bits of opcode. */ |
| 7586 | i.tm.base_opcode |= i.op[op].regs->reg_num; |
| 7587 | if ((i.op[op].regs->reg_flags & RegRex) != 0) |
| 7588 | i.rex |= REX_B; |
| 7589 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
| 7590 | { |
| 7591 | /* Warn about some common errors, but press on regardless. |
| 7592 | The first case can be generated by gcc (<= 2.8.1). */ |
| 7593 | if (i.operands == 2) |
| 7594 | { |
| 7595 | /* Reversed arguments on faddp, fsubp, etc. */ |
| 7596 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, |
| 7597 | register_prefix, i.op[!intel_syntax].regs->reg_name, |
| 7598 | register_prefix, i.op[intel_syntax].regs->reg_name); |
| 7599 | } |
| 7600 | else |
| 7601 | { |
| 7602 | /* Extraneous `l' suffix on fp insn. */ |
| 7603 | as_warn (_("translating to `%s %s%s'"), i.tm.name, |
| 7604 | register_prefix, i.op[0].regs->reg_name); |
| 7605 | } |
| 7606 | } |
| 7607 | } |
| 7608 | |
| 7609 | if ((i.seg[0] || i.prefix[SEG_PREFIX]) |
| 7610 | && i.tm.base_opcode == 0x8d /* lea */ |
| 7611 | && !is_any_vex_encoding(&i.tm)) |
| 7612 | { |
| 7613 | if (!quiet_warnings) |
| 7614 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
| 7615 | if (optimize) |
| 7616 | { |
| 7617 | i.seg[0] = NULL; |
| 7618 | i.prefix[SEG_PREFIX] = 0; |
| 7619 | } |
| 7620 | } |
| 7621 | |
| 7622 | /* If a segment was explicitly specified, and the specified segment |
| 7623 | is neither the default nor the one already recorded from a prefix, |
| 7624 | use an opcode prefix to select it. If we never figured out what |
| 7625 | the default segment is, then default_seg will be zero at this |
| 7626 | point, and the specified segment prefix will always be used. */ |
| 7627 | if (i.seg[0] |
| 7628 | && i.seg[0] != default_seg |
| 7629 | && i.seg[0]->seg_prefix != i.prefix[SEG_PREFIX]) |
| 7630 | { |
| 7631 | if (!add_prefix (i.seg[0]->seg_prefix)) |
| 7632 | return 0; |
| 7633 | } |
| 7634 | return 1; |
| 7635 | } |
| 7636 | |
| 7637 | static const seg_entry * |
| 7638 | build_modrm_byte (void) |
| 7639 | { |
| 7640 | const seg_entry *default_seg = 0; |
| 7641 | unsigned int source, dest; |
| 7642 | int vex_3_sources; |
| 7643 | |
| 7644 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
| 7645 | if (vex_3_sources) |
| 7646 | { |
| 7647 | unsigned int nds, reg_slot; |
| 7648 | expressionS *exp; |
| 7649 | |
| 7650 | dest = i.operands - 1; |
| 7651 | nds = dest - 1; |
| 7652 | |
| 7653 | /* There are 2 kinds of instructions: |
| 7654 | 1. 5 operands: 4 register operands or 3 register operands |
| 7655 | plus 1 memory operand plus one Imm4 operand, VexXDS, and |
| 7656 | VexW0 or VexW1. The destination must be either XMM, YMM or |
| 7657 | ZMM register. |
| 7658 | 2. 4 operands: 4 register operands or 3 register operands |
| 7659 | plus 1 memory operand, with VexXDS. */ |
| 7660 | gas_assert ((i.reg_operands == 4 |
| 7661 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
| 7662 | && i.tm.opcode_modifier.vexvvvv == VEXXDS |
| 7663 | && i.tm.opcode_modifier.vexw |
| 7664 | && i.tm.operand_types[dest].bitfield.class == RegSIMD); |
| 7665 | |
| 7666 | /* If VexW1 is set, the first non-immediate operand is the source and |
| 7667 | the second non-immediate one is encoded in the immediate operand. */ |
| 7668 | if (i.tm.opcode_modifier.vexw == VEXW1) |
| 7669 | { |
| 7670 | source = i.imm_operands; |
| 7671 | reg_slot = i.imm_operands + 1; |
| 7672 | } |
| 7673 | else |
| 7674 | { |
| 7675 | source = i.imm_operands + 1; |
| 7676 | reg_slot = i.imm_operands; |
| 7677 | } |
| 7678 | |
| 7679 | if (i.imm_operands == 0) |
| 7680 | { |
| 7681 | /* When there is no immediate operand, generate an 8bit |
| 7682 | immediate operand to encode the first operand. */ |
| 7683 | exp = &im_expressions[i.imm_operands++]; |
| 7684 | i.op[i.operands].imms = exp; |
| 7685 | i.types[i.operands] = imm8; |
| 7686 | i.operands++; |
| 7687 | |
| 7688 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
| 7689 | exp->X_op = O_constant; |
| 7690 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; |
| 7691 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
| 7692 | } |
| 7693 | else |
| 7694 | { |
| 7695 | gas_assert (i.imm_operands == 1); |
| 7696 | gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number)); |
| 7697 | gas_assert (!i.tm.opcode_modifier.immext); |
| 7698 | |
| 7699 | /* Turn on Imm8 again so that output_imm will generate it. */ |
| 7700 | i.types[0].bitfield.imm8 = 1; |
| 7701 | |
| 7702 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
| 7703 | i.op[0].imms->X_add_number |
| 7704 | |= register_number (i.op[reg_slot].regs) << 4; |
| 7705 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
| 7706 | } |
| 7707 | |
| 7708 | gas_assert (i.tm.operand_types[nds].bitfield.class == RegSIMD); |
| 7709 | i.vex.register_specifier = i.op[nds].regs; |
| 7710 | } |
| 7711 | else |
| 7712 | source = dest = 0; |
| 7713 | |
| 7714 | /* i.reg_operands MUST be the number of real register operands; |
| 7715 | implicit registers do not count. If there are 3 register |
| 7716 | operands, it must be a instruction with VexNDS. For a |
| 7717 | instruction with VexNDD, the destination register is encoded |
| 7718 | in VEX prefix. If there are 4 register operands, it must be |
| 7719 | a instruction with VEX prefix and 3 sources. */ |
| 7720 | if (i.mem_operands == 0 |
| 7721 | && ((i.reg_operands == 2 |
| 7722 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
| 7723 | || (i.reg_operands == 3 |
| 7724 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
| 7725 | || (i.reg_operands == 4 && vex_3_sources))) |
| 7726 | { |
| 7727 | switch (i.operands) |
| 7728 | { |
| 7729 | case 2: |
| 7730 | source = 0; |
| 7731 | break; |
| 7732 | case 3: |
| 7733 | /* When there are 3 operands, one of them may be immediate, |
| 7734 | which may be the first or the last operand. Otherwise, |
| 7735 | the first operand must be shift count register (cl) or it |
| 7736 | is an instruction with VexNDS. */ |
| 7737 | gas_assert (i.imm_operands == 1 |
| 7738 | || (i.imm_operands == 0 |
| 7739 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
| 7740 | || (i.types[0].bitfield.instance == RegC |
| 7741 | && i.types[0].bitfield.byte)))); |
| 7742 | if (operand_type_check (i.types[0], imm) |
| 7743 | || (i.types[0].bitfield.instance == RegC |
| 7744 | && i.types[0].bitfield.byte)) |
| 7745 | source = 1; |
| 7746 | else |
| 7747 | source = 0; |
| 7748 | break; |
| 7749 | case 4: |
| 7750 | /* When there are 4 operands, the first two must be 8bit |
| 7751 | immediate operands. The source operand will be the 3rd |
| 7752 | one. |
| 7753 | |
| 7754 | For instructions with VexNDS, if the first operand |
| 7755 | an imm8, the source operand is the 2nd one. If the last |
| 7756 | operand is imm8, the source operand is the first one. */ |
| 7757 | gas_assert ((i.imm_operands == 2 |
| 7758 | && i.types[0].bitfield.imm8 |
| 7759 | && i.types[1].bitfield.imm8) |
| 7760 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
| 7761 | && i.imm_operands == 1 |
| 7762 | && (i.types[0].bitfield.imm8 |
| 7763 | || i.types[i.operands - 1].bitfield.imm8 |
| 7764 | || i.rounding))); |
| 7765 | if (i.imm_operands == 2) |
| 7766 | source = 2; |
| 7767 | else |
| 7768 | { |
| 7769 | if (i.types[0].bitfield.imm8) |
| 7770 | source = 1; |
| 7771 | else |
| 7772 | source = 0; |
| 7773 | } |
| 7774 | break; |
| 7775 | case 5: |
| 7776 | if (is_evex_encoding (&i.tm)) |
| 7777 | { |
| 7778 | /* For EVEX instructions, when there are 5 operands, the |
| 7779 | first one must be immediate operand. If the second one |
| 7780 | is immediate operand, the source operand is the 3th |
| 7781 | one. If the last one is immediate operand, the source |
| 7782 | operand is the 2nd one. */ |
| 7783 | gas_assert (i.imm_operands == 2 |
| 7784 | && i.tm.opcode_modifier.sae |
| 7785 | && operand_type_check (i.types[0], imm)); |
| 7786 | if (operand_type_check (i.types[1], imm)) |
| 7787 | source = 2; |
| 7788 | else if (operand_type_check (i.types[4], imm)) |
| 7789 | source = 1; |
| 7790 | else |
| 7791 | abort (); |
| 7792 | } |
| 7793 | break; |
| 7794 | default: |
| 7795 | abort (); |
| 7796 | } |
| 7797 | |
| 7798 | if (!vex_3_sources) |
| 7799 | { |
| 7800 | dest = source + 1; |
| 7801 | |
| 7802 | /* RC/SAE operand could be between DEST and SRC. That happens |
| 7803 | when one operand is GPR and the other one is XMM/YMM/ZMM |
| 7804 | register. */ |
| 7805 | if (i.rounding && i.rounding->operand == (int) dest) |
| 7806 | dest++; |
| 7807 | |
| 7808 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
| 7809 | { |
| 7810 | /* For instructions with VexNDS, the register-only source |
| 7811 | operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask |
| 7812 | register. It is encoded in VEX prefix. */ |
| 7813 | |
| 7814 | i386_operand_type op; |
| 7815 | unsigned int vvvv; |
| 7816 | |
| 7817 | /* Check register-only source operand when two source |
| 7818 | operands are swapped. */ |
| 7819 | if (!i.tm.operand_types[source].bitfield.baseindex |
| 7820 | && i.tm.operand_types[dest].bitfield.baseindex) |
| 7821 | { |
| 7822 | vvvv = source; |
| 7823 | source = dest; |
| 7824 | } |
| 7825 | else |
| 7826 | vvvv = dest; |
| 7827 | |
| 7828 | op = i.tm.operand_types[vvvv]; |
| 7829 | if ((dest + 1) >= i.operands |
| 7830 | || ((op.bitfield.class != Reg |
| 7831 | || (!op.bitfield.dword && !op.bitfield.qword)) |
| 7832 | && op.bitfield.class != RegSIMD |
| 7833 | && !operand_type_equal (&op, ®mask))) |
| 7834 | abort (); |
| 7835 | i.vex.register_specifier = i.op[vvvv].regs; |
| 7836 | dest++; |
| 7837 | } |
| 7838 | } |
| 7839 | |
| 7840 | i.rm.mode = 3; |
| 7841 | /* One of the register operands will be encoded in the i.rm.reg |
| 7842 | field, the other in the combined i.rm.mode and i.rm.regmem |
| 7843 | fields. If no form of this instruction supports a memory |
| 7844 | destination operand, then we assume the source operand may |
| 7845 | sometimes be a memory operand and so we need to store the |
| 7846 | destination in the i.rm.reg field. */ |
| 7847 | if (!i.tm.opcode_modifier.regmem |
| 7848 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) |
| 7849 | { |
| 7850 | i.rm.reg = i.op[dest].regs->reg_num; |
| 7851 | i.rm.regmem = i.op[source].regs->reg_num; |
| 7852 | if (i.op[dest].regs->reg_type.bitfield.class == RegMMX |
| 7853 | || i.op[source].regs->reg_type.bitfield.class == RegMMX) |
| 7854 | i.has_regmmx = TRUE; |
| 7855 | else if (i.op[dest].regs->reg_type.bitfield.class == RegSIMD |
| 7856 | || i.op[source].regs->reg_type.bitfield.class == RegSIMD) |
| 7857 | { |
| 7858 | if (i.types[dest].bitfield.zmmword |
| 7859 | || i.types[source].bitfield.zmmword) |
| 7860 | i.has_regzmm = TRUE; |
| 7861 | else if (i.types[dest].bitfield.ymmword |
| 7862 | || i.types[source].bitfield.ymmword) |
| 7863 | i.has_regymm = TRUE; |
| 7864 | else |
| 7865 | i.has_regxmm = TRUE; |
| 7866 | } |
| 7867 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) |
| 7868 | i.rex |= REX_R; |
| 7869 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
| 7870 | i.vrex |= REX_R; |
| 7871 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
| 7872 | i.rex |= REX_B; |
| 7873 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
| 7874 | i.vrex |= REX_B; |
| 7875 | } |
| 7876 | else |
| 7877 | { |
| 7878 | i.rm.reg = i.op[source].regs->reg_num; |
| 7879 | i.rm.regmem = i.op[dest].regs->reg_num; |
| 7880 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) |
| 7881 | i.rex |= REX_B; |
| 7882 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
| 7883 | i.vrex |= REX_B; |
| 7884 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
| 7885 | i.rex |= REX_R; |
| 7886 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
| 7887 | i.vrex |= REX_R; |
| 7888 | } |
| 7889 | if (flag_code != CODE_64BIT && (i.rex & REX_R)) |
| 7890 | { |
| 7891 | if (i.types[!i.tm.opcode_modifier.regmem].bitfield.class != RegCR) |
| 7892 | abort (); |
| 7893 | i.rex &= ~REX_R; |
| 7894 | add_prefix (LOCK_PREFIX_OPCODE); |
| 7895 | } |
| 7896 | } |
| 7897 | else |
| 7898 | { /* If it's not 2 reg operands... */ |
| 7899 | unsigned int mem; |
| 7900 | |
| 7901 | if (i.mem_operands) |
| 7902 | { |
| 7903 | unsigned int fake_zero_displacement = 0; |
| 7904 | unsigned int op; |
| 7905 | |
| 7906 | for (op = 0; op < i.operands; op++) |
| 7907 | if (i.flags[op] & Operand_Mem) |
| 7908 | break; |
| 7909 | gas_assert (op < i.operands); |
| 7910 | |
| 7911 | if (i.tm.opcode_modifier.vecsib) |
| 7912 | { |
| 7913 | if (i.index_reg->reg_num == RegIZ) |
| 7914 | abort (); |
| 7915 | |
| 7916 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
| 7917 | if (!i.base_reg) |
| 7918 | { |
| 7919 | i.sib.base = NO_BASE_REGISTER; |
| 7920 | i.sib.scale = i.log2_scale_factor; |
| 7921 | i.types[op].bitfield.disp8 = 0; |
| 7922 | i.types[op].bitfield.disp16 = 0; |
| 7923 | i.types[op].bitfield.disp64 = 0; |
| 7924 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
| 7925 | { |
| 7926 | /* Must be 32 bit */ |
| 7927 | i.types[op].bitfield.disp32 = 1; |
| 7928 | i.types[op].bitfield.disp32s = 0; |
| 7929 | } |
| 7930 | else |
| 7931 | { |
| 7932 | i.types[op].bitfield.disp32 = 0; |
| 7933 | i.types[op].bitfield.disp32s = 1; |
| 7934 | } |
| 7935 | } |
| 7936 | i.sib.index = i.index_reg->reg_num; |
| 7937 | if ((i.index_reg->reg_flags & RegRex) != 0) |
| 7938 | i.rex |= REX_X; |
| 7939 | if ((i.index_reg->reg_flags & RegVRex) != 0) |
| 7940 | i.vrex |= REX_X; |
| 7941 | } |
| 7942 | |
| 7943 | default_seg = &ds; |
| 7944 | |
| 7945 | if (i.base_reg == 0) |
| 7946 | { |
| 7947 | i.rm.mode = 0; |
| 7948 | if (!i.disp_operands) |
| 7949 | fake_zero_displacement = 1; |
| 7950 | if (i.index_reg == 0) |
| 7951 | { |
| 7952 | i386_operand_type newdisp; |
| 7953 | |
| 7954 | gas_assert (!i.tm.opcode_modifier.vecsib); |
| 7955 | /* Operand is just <disp> */ |
| 7956 | if (flag_code == CODE_64BIT) |
| 7957 | { |
| 7958 | /* 64bit mode overwrites the 32bit absolute |
| 7959 | addressing by RIP relative addressing and |
| 7960 | absolute addressing is encoded by one of the |
| 7961 | redundant SIB forms. */ |
| 7962 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
| 7963 | i.sib.base = NO_BASE_REGISTER; |
| 7964 | i.sib.index = NO_INDEX_REGISTER; |
| 7965 | newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32); |
| 7966 | } |
| 7967 | else if ((flag_code == CODE_16BIT) |
| 7968 | ^ (i.prefix[ADDR_PREFIX] != 0)) |
| 7969 | { |
| 7970 | i.rm.regmem = NO_BASE_REGISTER_16; |
| 7971 | newdisp = disp16; |
| 7972 | } |
| 7973 | else |
| 7974 | { |
| 7975 | i.rm.regmem = NO_BASE_REGISTER; |
| 7976 | newdisp = disp32; |
| 7977 | } |
| 7978 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
| 7979 | i.types[op] = operand_type_or (i.types[op], newdisp); |
| 7980 | } |
| 7981 | else if (!i.tm.opcode_modifier.vecsib) |
| 7982 | { |
| 7983 | /* !i.base_reg && i.index_reg */ |
| 7984 | if (i.index_reg->reg_num == RegIZ) |
| 7985 | i.sib.index = NO_INDEX_REGISTER; |
| 7986 | else |
| 7987 | i.sib.index = i.index_reg->reg_num; |
| 7988 | i.sib.base = NO_BASE_REGISTER; |
| 7989 | i.sib.scale = i.log2_scale_factor; |
| 7990 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
| 7991 | i.types[op].bitfield.disp8 = 0; |
| 7992 | i.types[op].bitfield.disp16 = 0; |
| 7993 | i.types[op].bitfield.disp64 = 0; |
| 7994 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
| 7995 | { |
| 7996 | /* Must be 32 bit */ |
| 7997 | i.types[op].bitfield.disp32 = 1; |
| 7998 | i.types[op].bitfield.disp32s = 0; |
| 7999 | } |
| 8000 | else |
| 8001 | { |
| 8002 | i.types[op].bitfield.disp32 = 0; |
| 8003 | i.types[op].bitfield.disp32s = 1; |
| 8004 | } |
| 8005 | if ((i.index_reg->reg_flags & RegRex) != 0) |
| 8006 | i.rex |= REX_X; |
| 8007 | } |
| 8008 | } |
| 8009 | /* RIP addressing for 64bit mode. */ |
| 8010 | else if (i.base_reg->reg_num == RegIP) |
| 8011 | { |
| 8012 | gas_assert (!i.tm.opcode_modifier.vecsib); |
| 8013 | i.rm.regmem = NO_BASE_REGISTER; |
| 8014 | i.types[op].bitfield.disp8 = 0; |
| 8015 | i.types[op].bitfield.disp16 = 0; |
| 8016 | i.types[op].bitfield.disp32 = 0; |
| 8017 | i.types[op].bitfield.disp32s = 1; |
| 8018 | i.types[op].bitfield.disp64 = 0; |
| 8019 | i.flags[op] |= Operand_PCrel; |
| 8020 | if (! i.disp_operands) |
| 8021 | fake_zero_displacement = 1; |
| 8022 | } |
| 8023 | else if (i.base_reg->reg_type.bitfield.word) |
| 8024 | { |
| 8025 | gas_assert (!i.tm.opcode_modifier.vecsib); |
| 8026 | switch (i.base_reg->reg_num) |
| 8027 | { |
| 8028 | case 3: /* (%bx) */ |
| 8029 | if (i.index_reg == 0) |
| 8030 | i.rm.regmem = 7; |
| 8031 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ |
| 8032 | i.rm.regmem = i.index_reg->reg_num - 6; |
| 8033 | break; |
| 8034 | case 5: /* (%bp) */ |
| 8035 | default_seg = &ss; |
| 8036 | if (i.index_reg == 0) |
| 8037 | { |
| 8038 | i.rm.regmem = 6; |
| 8039 | if (operand_type_check (i.types[op], disp) == 0) |
| 8040 | { |
| 8041 | /* fake (%bp) into 0(%bp) */ |
| 8042 | i.types[op].bitfield.disp8 = 1; |
| 8043 | fake_zero_displacement = 1; |
| 8044 | } |
| 8045 | } |
| 8046 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ |
| 8047 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; |
| 8048 | break; |
| 8049 | default: /* (%si) -> 4 or (%di) -> 5 */ |
| 8050 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; |
| 8051 | } |
| 8052 | i.rm.mode = mode_from_disp_size (i.types[op]); |
| 8053 | } |
| 8054 | else /* i.base_reg and 32/64 bit mode */ |
| 8055 | { |
| 8056 | if (flag_code == CODE_64BIT |
| 8057 | && operand_type_check (i.types[op], disp)) |
| 8058 | { |
| 8059 | i.types[op].bitfield.disp16 = 0; |
| 8060 | i.types[op].bitfield.disp64 = 0; |
| 8061 | if (i.prefix[ADDR_PREFIX] == 0) |
| 8062 | { |
| 8063 | i.types[op].bitfield.disp32 = 0; |
| 8064 | i.types[op].bitfield.disp32s = 1; |
| 8065 | } |
| 8066 | else |
| 8067 | { |
| 8068 | i.types[op].bitfield.disp32 = 1; |
| 8069 | i.types[op].bitfield.disp32s = 0; |
| 8070 | } |
| 8071 | } |
| 8072 | |
| 8073 | if (!i.tm.opcode_modifier.vecsib) |
| 8074 | i.rm.regmem = i.base_reg->reg_num; |
| 8075 | if ((i.base_reg->reg_flags & RegRex) != 0) |
| 8076 | i.rex |= REX_B; |
| 8077 | i.sib.base = i.base_reg->reg_num; |
| 8078 | /* x86-64 ignores REX prefix bit here to avoid decoder |
| 8079 | complications. */ |
| 8080 | if (!(i.base_reg->reg_flags & RegRex) |
| 8081 | && (i.base_reg->reg_num == EBP_REG_NUM |
| 8082 | || i.base_reg->reg_num == ESP_REG_NUM)) |
| 8083 | default_seg = &ss; |
| 8084 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
| 8085 | { |
| 8086 | fake_zero_displacement = 1; |
| 8087 | i.types[op].bitfield.disp8 = 1; |
| 8088 | } |
| 8089 | i.sib.scale = i.log2_scale_factor; |
| 8090 | if (i.index_reg == 0) |
| 8091 | { |
| 8092 | gas_assert (!i.tm.opcode_modifier.vecsib); |
| 8093 | /* <disp>(%esp) becomes two byte modrm with no index |
| 8094 | register. We've already stored the code for esp |
| 8095 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. |
| 8096 | Any base register besides %esp will not use the |
| 8097 | extra modrm byte. */ |
| 8098 | i.sib.index = NO_INDEX_REGISTER; |
| 8099 | } |
| 8100 | else if (!i.tm.opcode_modifier.vecsib) |
| 8101 | { |
| 8102 | if (i.index_reg->reg_num == RegIZ) |
| 8103 | i.sib.index = NO_INDEX_REGISTER; |
| 8104 | else |
| 8105 | i.sib.index = i.index_reg->reg_num; |
| 8106 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
| 8107 | if ((i.index_reg->reg_flags & RegRex) != 0) |
| 8108 | i.rex |= REX_X; |
| 8109 | } |
| 8110 | |
| 8111 | if (i.disp_operands |
| 8112 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
| 8113 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) |
| 8114 | i.rm.mode = 0; |
| 8115 | else |
| 8116 | { |
| 8117 | if (!fake_zero_displacement |
| 8118 | && !i.disp_operands |
| 8119 | && i.disp_encoding) |
| 8120 | { |
| 8121 | fake_zero_displacement = 1; |
| 8122 | if (i.disp_encoding == disp_encoding_8bit) |
| 8123 | i.types[op].bitfield.disp8 = 1; |
| 8124 | else |
| 8125 | i.types[op].bitfield.disp32 = 1; |
| 8126 | } |
| 8127 | i.rm.mode = mode_from_disp_size (i.types[op]); |
| 8128 | } |
| 8129 | } |
| 8130 | |
| 8131 | if (fake_zero_displacement) |
| 8132 | { |
| 8133 | /* Fakes a zero displacement assuming that i.types[op] |
| 8134 | holds the correct displacement size. */ |
| 8135 | expressionS *exp; |
| 8136 | |
| 8137 | gas_assert (i.op[op].disps == 0); |
| 8138 | exp = &disp_expressions[i.disp_operands++]; |
| 8139 | i.op[op].disps = exp; |
| 8140 | exp->X_op = O_constant; |
| 8141 | exp->X_add_number = 0; |
| 8142 | exp->X_add_symbol = (symbolS *) 0; |
| 8143 | exp->X_op_symbol = (symbolS *) 0; |
| 8144 | } |
| 8145 | |
| 8146 | mem = op; |
| 8147 | } |
| 8148 | else |
| 8149 | mem = ~0; |
| 8150 | |
| 8151 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
| 8152 | { |
| 8153 | if (operand_type_check (i.types[0], imm)) |
| 8154 | i.vex.register_specifier = NULL; |
| 8155 | else |
| 8156 | { |
| 8157 | /* VEX.vvvv encodes one of the sources when the first |
| 8158 | operand is not an immediate. */ |
| 8159 | if (i.tm.opcode_modifier.vexw == VEXW0) |
| 8160 | i.vex.register_specifier = i.op[0].regs; |
| 8161 | else |
| 8162 | i.vex.register_specifier = i.op[1].regs; |
| 8163 | } |
| 8164 | |
| 8165 | /* Destination is a XMM register encoded in the ModRM.reg |
| 8166 | and VEX.R bit. */ |
| 8167 | i.rm.reg = i.op[2].regs->reg_num; |
| 8168 | if ((i.op[2].regs->reg_flags & RegRex) != 0) |
| 8169 | i.rex |= REX_R; |
| 8170 | |
| 8171 | /* ModRM.rm and VEX.B encodes the other source. */ |
| 8172 | if (!i.mem_operands) |
| 8173 | { |
| 8174 | i.rm.mode = 3; |
| 8175 | |
| 8176 | if (i.tm.opcode_modifier.vexw == VEXW0) |
| 8177 | i.rm.regmem = i.op[1].regs->reg_num; |
| 8178 | else |
| 8179 | i.rm.regmem = i.op[0].regs->reg_num; |
| 8180 | |
| 8181 | if ((i.op[1].regs->reg_flags & RegRex) != 0) |
| 8182 | i.rex |= REX_B; |
| 8183 | } |
| 8184 | } |
| 8185 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
| 8186 | { |
| 8187 | i.vex.register_specifier = i.op[2].regs; |
| 8188 | if (!i.mem_operands) |
| 8189 | { |
| 8190 | i.rm.mode = 3; |
| 8191 | i.rm.regmem = i.op[1].regs->reg_num; |
| 8192 | if ((i.op[1].regs->reg_flags & RegRex) != 0) |
| 8193 | i.rex |= REX_B; |
| 8194 | } |
| 8195 | } |
| 8196 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
| 8197 | (if any) based on i.tm.extension_opcode. Again, we must be |
| 8198 | careful to make sure that segment/control/debug/test/MMX |
| 8199 | registers are coded into the i.rm.reg field. */ |
| 8200 | else if (i.reg_operands) |
| 8201 | { |
| 8202 | unsigned int op; |
| 8203 | unsigned int vex_reg = ~0; |
| 8204 | |
| 8205 | for (op = 0; op < i.operands; op++) |
| 8206 | { |
| 8207 | if (i.types[op].bitfield.class == Reg |
| 8208 | || i.types[op].bitfield.class == RegBND |
| 8209 | || i.types[op].bitfield.class == RegMask |
| 8210 | || i.types[op].bitfield.class == SReg |
| 8211 | || i.types[op].bitfield.class == RegCR |
| 8212 | || i.types[op].bitfield.class == RegDR |
| 8213 | || i.types[op].bitfield.class == RegTR) |
| 8214 | break; |
| 8215 | if (i.types[op].bitfield.class == RegSIMD) |
| 8216 | { |
| 8217 | if (i.types[op].bitfield.zmmword) |
| 8218 | i.has_regzmm = TRUE; |
| 8219 | else if (i.types[op].bitfield.ymmword) |
| 8220 | i.has_regymm = TRUE; |
| 8221 | else |
| 8222 | i.has_regxmm = TRUE; |
| 8223 | break; |
| 8224 | } |
| 8225 | if (i.types[op].bitfield.class == RegMMX) |
| 8226 | { |
| 8227 | i.has_regmmx = TRUE; |
| 8228 | break; |
| 8229 | } |
| 8230 | } |
| 8231 | |
| 8232 | if (vex_3_sources) |
| 8233 | op = dest; |
| 8234 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
| 8235 | { |
| 8236 | /* For instructions with VexNDS, the register-only |
| 8237 | source operand is encoded in VEX prefix. */ |
| 8238 | gas_assert (mem != (unsigned int) ~0); |
| 8239 | |
| 8240 | if (op > mem) |
| 8241 | { |
| 8242 | vex_reg = op++; |
| 8243 | gas_assert (op < i.operands); |
| 8244 | } |
| 8245 | else |
| 8246 | { |
| 8247 | /* Check register-only source operand when two source |
| 8248 | operands are swapped. */ |
| 8249 | if (!i.tm.operand_types[op].bitfield.baseindex |
| 8250 | && i.tm.operand_types[op + 1].bitfield.baseindex) |
| 8251 | { |
| 8252 | vex_reg = op; |
| 8253 | op += 2; |
| 8254 | gas_assert (mem == (vex_reg + 1) |
| 8255 | && op < i.operands); |
| 8256 | } |
| 8257 | else |
| 8258 | { |
| 8259 | vex_reg = op + 1; |
| 8260 | gas_assert (vex_reg < i.operands); |
| 8261 | } |
| 8262 | } |
| 8263 | } |
| 8264 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
| 8265 | { |
| 8266 | /* For instructions with VexNDD, the register destination |
| 8267 | is encoded in VEX prefix. */ |
| 8268 | if (i.mem_operands == 0) |
| 8269 | { |
| 8270 | /* There is no memory operand. */ |
| 8271 | gas_assert ((op + 2) == i.operands); |
| 8272 | vex_reg = op + 1; |
| 8273 | } |
| 8274 | else |
| 8275 | { |
| 8276 | /* There are only 2 non-immediate operands. */ |
| 8277 | gas_assert (op < i.imm_operands + 2 |
| 8278 | && i.operands == i.imm_operands + 2); |
| 8279 | vex_reg = i.imm_operands + 1; |
| 8280 | } |
| 8281 | } |
| 8282 | else |
| 8283 | gas_assert (op < i.operands); |
| 8284 | |
| 8285 | if (vex_reg != (unsigned int) ~0) |
| 8286 | { |
| 8287 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
| 8288 | |
| 8289 | if ((type->bitfield.class != Reg |
| 8290 | || (!type->bitfield.dword && !type->bitfield.qword)) |
| 8291 | && type->bitfield.class != RegSIMD |
| 8292 | && !operand_type_equal (type, ®mask)) |
| 8293 | abort (); |
| 8294 | |
| 8295 | i.vex.register_specifier = i.op[vex_reg].regs; |
| 8296 | } |
| 8297 | |
| 8298 | /* Don't set OP operand twice. */ |
| 8299 | if (vex_reg != op) |
| 8300 | { |
| 8301 | /* If there is an extension opcode to put here, the |
| 8302 | register number must be put into the regmem field. */ |
| 8303 | if (i.tm.extension_opcode != None) |
| 8304 | { |
| 8305 | i.rm.regmem = i.op[op].regs->reg_num; |
| 8306 | if ((i.op[op].regs->reg_flags & RegRex) != 0) |
| 8307 | i.rex |= REX_B; |
| 8308 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
| 8309 | i.vrex |= REX_B; |
| 8310 | } |
| 8311 | else |
| 8312 | { |
| 8313 | i.rm.reg = i.op[op].regs->reg_num; |
| 8314 | if ((i.op[op].regs->reg_flags & RegRex) != 0) |
| 8315 | i.rex |= REX_R; |
| 8316 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
| 8317 | i.vrex |= REX_R; |
| 8318 | } |
| 8319 | } |
| 8320 | |
| 8321 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
| 8322 | must set it to 3 to indicate this is a register operand |
| 8323 | in the regmem field. */ |
| 8324 | if (!i.mem_operands) |
| 8325 | i.rm.mode = 3; |
| 8326 | } |
| 8327 | |
| 8328 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
| 8329 | if (i.tm.extension_opcode != None) |
| 8330 | i.rm.reg = i.tm.extension_opcode; |
| 8331 | } |
| 8332 | return default_seg; |
| 8333 | } |
| 8334 | |
| 8335 | static unsigned int |
| 8336 | flip_code16 (unsigned int code16) |
| 8337 | { |
| 8338 | gas_assert (i.tm.operands == 1); |
| 8339 | |
| 8340 | return !(i.prefix[REX_PREFIX] & REX_W) |
| 8341 | && (code16 ? i.tm.operand_types[0].bitfield.disp32 |
| 8342 | || i.tm.operand_types[0].bitfield.disp32s |
| 8343 | : i.tm.operand_types[0].bitfield.disp16) |
| 8344 | ? CODE16 : 0; |
| 8345 | } |
| 8346 | |
| 8347 | static void |
| 8348 | output_branch (void) |
| 8349 | { |
| 8350 | char *p; |
| 8351 | int size; |
| 8352 | int code16; |
| 8353 | int prefix; |
| 8354 | relax_substateT subtype; |
| 8355 | symbolS *sym; |
| 8356 | offsetT off; |
| 8357 | |
| 8358 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
| 8359 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
| 8360 | |
| 8361 | prefix = 0; |
| 8362 | if (i.prefix[DATA_PREFIX] != 0) |
| 8363 | { |
| 8364 | prefix = 1; |
| 8365 | i.prefixes -= 1; |
| 8366 | code16 ^= flip_code16(code16); |
| 8367 | } |
| 8368 | /* Pentium4 branch hints. */ |
| 8369 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ |
| 8370 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) |
| 8371 | { |
| 8372 | prefix++; |
| 8373 | i.prefixes--; |
| 8374 | } |
| 8375 | if (i.prefix[REX_PREFIX] != 0) |
| 8376 | { |
| 8377 | prefix++; |
| 8378 | i.prefixes--; |
| 8379 | } |
| 8380 | |
| 8381 | /* BND prefixed jump. */ |
| 8382 | if (i.prefix[BND_PREFIX] != 0) |
| 8383 | { |
| 8384 | prefix++; |
| 8385 | i.prefixes--; |
| 8386 | } |
| 8387 | |
| 8388 | if (i.prefixes != 0) |
| 8389 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); |
| 8390 | |
| 8391 | /* It's always a symbol; End frag & setup for relax. |
| 8392 | Make sure there is enough room in this frag for the largest |
| 8393 | instruction we may generate in md_convert_frag. This is 2 |
| 8394 | bytes for the opcode and room for the prefix and largest |
| 8395 | displacement. */ |
| 8396 | frag_grow (prefix + 2 + 4); |
| 8397 | /* Prefix and 1 opcode byte go in fr_fix. */ |
| 8398 | p = frag_more (prefix + 1); |
| 8399 | if (i.prefix[DATA_PREFIX] != 0) |
| 8400 | *p++ = DATA_PREFIX_OPCODE; |
| 8401 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE |
| 8402 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) |
| 8403 | *p++ = i.prefix[SEG_PREFIX]; |
| 8404 | if (i.prefix[BND_PREFIX] != 0) |
| 8405 | *p++ = BND_PREFIX_OPCODE; |
| 8406 | if (i.prefix[REX_PREFIX] != 0) |
| 8407 | *p++ = i.prefix[REX_PREFIX]; |
| 8408 | *p = i.tm.base_opcode; |
| 8409 | |
| 8410 | if ((unsigned char) *p == JUMP_PC_RELATIVE) |
| 8411 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
| 8412 | else if (cpu_arch_flags.bitfield.cpui386) |
| 8413 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
| 8414 | else |
| 8415 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
| 8416 | subtype |= code16; |
| 8417 | |
| 8418 | sym = i.op[0].disps->X_add_symbol; |
| 8419 | off = i.op[0].disps->X_add_number; |
| 8420 | |
| 8421 | if (i.op[0].disps->X_op != O_constant |
| 8422 | && i.op[0].disps->X_op != O_symbol) |
| 8423 | { |
| 8424 | /* Handle complex expressions. */ |
| 8425 | sym = make_expr_symbol (i.op[0].disps); |
| 8426 | off = 0; |
| 8427 | } |
| 8428 | |
| 8429 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
| 8430 | Pass reloc in fr_var. */ |
| 8431 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
| 8432 | } |
| 8433 | |
| 8434 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 8435 | /* Return TRUE iff PLT32 relocation should be used for branching to |
| 8436 | symbol S. */ |
| 8437 | |
| 8438 | static bfd_boolean |
| 8439 | need_plt32_p (symbolS *s) |
| 8440 | { |
| 8441 | /* PLT32 relocation is ELF only. */ |
| 8442 | if (!IS_ELF) |
| 8443 | return FALSE; |
| 8444 | |
| 8445 | #ifdef TE_SOLARIS |
| 8446 | /* Don't emit PLT32 relocation on Solaris: neither native linker nor |
| 8447 | krtld support it. */ |
| 8448 | return FALSE; |
| 8449 | #endif |
| 8450 | |
| 8451 | /* Since there is no need to prepare for PLT branch on x86-64, we |
| 8452 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can |
| 8453 | be used as a marker for 32-bit PC-relative branches. */ |
| 8454 | if (!object_64bit) |
| 8455 | return FALSE; |
| 8456 | |
| 8457 | /* Weak or undefined symbol need PLT32 relocation. */ |
| 8458 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) |
| 8459 | return TRUE; |
| 8460 | |
| 8461 | /* Non-global symbol doesn't need PLT32 relocation. */ |
| 8462 | if (! S_IS_EXTERNAL (s)) |
| 8463 | return FALSE; |
| 8464 | |
| 8465 | /* Other global symbols need PLT32 relocation. NB: Symbol with |
| 8466 | non-default visibilities are treated as normal global symbol |
| 8467 | so that PLT32 relocation can be used as a marker for 32-bit |
| 8468 | PC-relative branches. It is useful for linker relaxation. */ |
| 8469 | return TRUE; |
| 8470 | } |
| 8471 | #endif |
| 8472 | |
| 8473 | static void |
| 8474 | output_jump (void) |
| 8475 | { |
| 8476 | char *p; |
| 8477 | int size; |
| 8478 | fixS *fixP; |
| 8479 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
| 8480 | |
| 8481 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) |
| 8482 | { |
| 8483 | /* This is a loop or jecxz type instruction. */ |
| 8484 | size = 1; |
| 8485 | if (i.prefix[ADDR_PREFIX] != 0) |
| 8486 | { |
| 8487 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); |
| 8488 | i.prefixes -= 1; |
| 8489 | } |
| 8490 | /* Pentium4 branch hints. */ |
| 8491 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ |
| 8492 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) |
| 8493 | { |
| 8494 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); |
| 8495 | i.prefixes--; |
| 8496 | } |
| 8497 | } |
| 8498 | else |
| 8499 | { |
| 8500 | int code16; |
| 8501 | |
| 8502 | code16 = 0; |
| 8503 | if (flag_code == CODE_16BIT) |
| 8504 | code16 = CODE16; |
| 8505 | |
| 8506 | if (i.prefix[DATA_PREFIX] != 0) |
| 8507 | { |
| 8508 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); |
| 8509 | i.prefixes -= 1; |
| 8510 | code16 ^= flip_code16(code16); |
| 8511 | } |
| 8512 | |
| 8513 | size = 4; |
| 8514 | if (code16) |
| 8515 | size = 2; |
| 8516 | } |
| 8517 | |
| 8518 | /* BND prefixed jump. */ |
| 8519 | if (i.prefix[BND_PREFIX] != 0) |
| 8520 | { |
| 8521 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); |
| 8522 | i.prefixes -= 1; |
| 8523 | } |
| 8524 | |
| 8525 | if (i.prefix[REX_PREFIX] != 0) |
| 8526 | { |
| 8527 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); |
| 8528 | i.prefixes -= 1; |
| 8529 | } |
| 8530 | |
| 8531 | if (i.prefixes != 0) |
| 8532 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); |
| 8533 | |
| 8534 | p = frag_more (i.tm.opcode_length + size); |
| 8535 | switch (i.tm.opcode_length) |
| 8536 | { |
| 8537 | case 2: |
| 8538 | *p++ = i.tm.base_opcode >> 8; |
| 8539 | /* Fall through. */ |
| 8540 | case 1: |
| 8541 | *p++ = i.tm.base_opcode; |
| 8542 | break; |
| 8543 | default: |
| 8544 | abort (); |
| 8545 | } |
| 8546 | |
| 8547 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 8548 | if (size == 4 |
| 8549 | && jump_reloc == NO_RELOC |
| 8550 | && need_plt32_p (i.op[0].disps->X_add_symbol)) |
| 8551 | jump_reloc = BFD_RELOC_X86_64_PLT32; |
| 8552 | #endif |
| 8553 | |
| 8554 | jump_reloc = reloc (size, 1, 1, jump_reloc); |
| 8555 | |
| 8556 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
| 8557 | i.op[0].disps, 1, jump_reloc); |
| 8558 | |
| 8559 | /* All jumps handled here are signed, but don't use a signed limit |
| 8560 | check for 32 and 16 bit jumps as we want to allow wrap around at |
| 8561 | 4G and 64k respectively. */ |
| 8562 | if (size == 1) |
| 8563 | fixP->fx_signed = 1; |
| 8564 | } |
| 8565 | |
| 8566 | static void |
| 8567 | output_interseg_jump (void) |
| 8568 | { |
| 8569 | char *p; |
| 8570 | int size; |
| 8571 | int prefix; |
| 8572 | int code16; |
| 8573 | |
| 8574 | code16 = 0; |
| 8575 | if (flag_code == CODE_16BIT) |
| 8576 | code16 = CODE16; |
| 8577 | |
| 8578 | prefix = 0; |
| 8579 | if (i.prefix[DATA_PREFIX] != 0) |
| 8580 | { |
| 8581 | prefix = 1; |
| 8582 | i.prefixes -= 1; |
| 8583 | code16 ^= CODE16; |
| 8584 | } |
| 8585 | |
| 8586 | gas_assert (!i.prefix[REX_PREFIX]); |
| 8587 | |
| 8588 | size = 4; |
| 8589 | if (code16) |
| 8590 | size = 2; |
| 8591 | |
| 8592 | if (i.prefixes != 0) |
| 8593 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); |
| 8594 | |
| 8595 | /* 1 opcode; 2 segment; offset */ |
| 8596 | p = frag_more (prefix + 1 + 2 + size); |
| 8597 | |
| 8598 | if (i.prefix[DATA_PREFIX] != 0) |
| 8599 | *p++ = DATA_PREFIX_OPCODE; |
| 8600 | |
| 8601 | if (i.prefix[REX_PREFIX] != 0) |
| 8602 | *p++ = i.prefix[REX_PREFIX]; |
| 8603 | |
| 8604 | *p++ = i.tm.base_opcode; |
| 8605 | if (i.op[1].imms->X_op == O_constant) |
| 8606 | { |
| 8607 | offsetT n = i.op[1].imms->X_add_number; |
| 8608 | |
| 8609 | if (size == 2 |
| 8610 | && !fits_in_unsigned_word (n) |
| 8611 | && !fits_in_signed_word (n)) |
| 8612 | { |
| 8613 | as_bad (_("16-bit jump out of range")); |
| 8614 | return; |
| 8615 | } |
| 8616 | md_number_to_chars (p, n, size); |
| 8617 | } |
| 8618 | else |
| 8619 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
| 8620 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
| 8621 | if (i.op[0].imms->X_op != O_constant) |
| 8622 | as_bad (_("can't handle non absolute segment in `%s'"), |
| 8623 | i.tm.name); |
| 8624 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); |
| 8625 | } |
| 8626 | |
| 8627 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 8628 | void |
| 8629 | x86_cleanup (void) |
| 8630 | { |
| 8631 | char *p; |
| 8632 | asection *seg = now_seg; |
| 8633 | subsegT subseg = now_subseg; |
| 8634 | asection *sec; |
| 8635 | unsigned int alignment, align_size_1; |
| 8636 | unsigned int isa_1_descsz, feature_2_descsz, descsz; |
| 8637 | unsigned int isa_1_descsz_raw, feature_2_descsz_raw; |
| 8638 | unsigned int padding; |
| 8639 | |
| 8640 | if (!IS_ELF || !x86_used_note) |
| 8641 | return; |
| 8642 | |
| 8643 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86; |
| 8644 | |
| 8645 | /* The .note.gnu.property section layout: |
| 8646 | |
| 8647 | Field Length Contents |
| 8648 | ---- ---- ---- |
| 8649 | n_namsz 4 4 |
| 8650 | n_descsz 4 The note descriptor size |
| 8651 | n_type 4 NT_GNU_PROPERTY_TYPE_0 |
| 8652 | n_name 4 "GNU" |
| 8653 | n_desc n_descsz The program property array |
| 8654 | .... .... .... |
| 8655 | */ |
| 8656 | |
| 8657 | /* Create the .note.gnu.property section. */ |
| 8658 | sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0); |
| 8659 | bfd_set_section_flags (sec, |
| 8660 | (SEC_ALLOC |
| 8661 | | SEC_LOAD |
| 8662 | | SEC_DATA |
| 8663 | | SEC_HAS_CONTENTS |
| 8664 | | SEC_READONLY)); |
| 8665 | |
| 8666 | if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64) |
| 8667 | { |
| 8668 | align_size_1 = 7; |
| 8669 | alignment = 3; |
| 8670 | } |
| 8671 | else |
| 8672 | { |
| 8673 | align_size_1 = 3; |
| 8674 | alignment = 2; |
| 8675 | } |
| 8676 | |
| 8677 | bfd_set_section_alignment (sec, alignment); |
| 8678 | elf_section_type (sec) = SHT_NOTE; |
| 8679 | |
| 8680 | /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size |
| 8681 | + 4-byte data */ |
| 8682 | isa_1_descsz_raw = 4 + 4 + 4; |
| 8683 | /* Align GNU_PROPERTY_X86_ISA_1_USED. */ |
| 8684 | isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1; |
| 8685 | |
| 8686 | feature_2_descsz_raw = isa_1_descsz; |
| 8687 | /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size |
| 8688 | + 4-byte data */ |
| 8689 | feature_2_descsz_raw += 4 + 4 + 4; |
| 8690 | /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */ |
| 8691 | feature_2_descsz = ((feature_2_descsz_raw + align_size_1) |
| 8692 | & ~align_size_1); |
| 8693 | |
| 8694 | descsz = feature_2_descsz; |
| 8695 | /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */ |
| 8696 | p = frag_more (4 + 4 + 4 + 4 + descsz); |
| 8697 | |
| 8698 | /* Write n_namsz. */ |
| 8699 | md_number_to_chars (p, (valueT) 4, 4); |
| 8700 | |
| 8701 | /* Write n_descsz. */ |
| 8702 | md_number_to_chars (p + 4, (valueT) descsz, 4); |
| 8703 | |
| 8704 | /* Write n_type. */ |
| 8705 | md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4); |
| 8706 | |
| 8707 | /* Write n_name. */ |
| 8708 | memcpy (p + 4 * 3, "GNU", 4); |
| 8709 | |
| 8710 | /* Write 4-byte type. */ |
| 8711 | md_number_to_chars (p + 4 * 4, |
| 8712 | (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4); |
| 8713 | |
| 8714 | /* Write 4-byte data size. */ |
| 8715 | md_number_to_chars (p + 4 * 5, (valueT) 4, 4); |
| 8716 | |
| 8717 | /* Write 4-byte data. */ |
| 8718 | md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4); |
| 8719 | |
| 8720 | /* Zero out paddings. */ |
| 8721 | padding = isa_1_descsz - isa_1_descsz_raw; |
| 8722 | if (padding) |
| 8723 | memset (p + 4 * 7, 0, padding); |
| 8724 | |
| 8725 | /* Write 4-byte type. */ |
| 8726 | md_number_to_chars (p + isa_1_descsz + 4 * 4, |
| 8727 | (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4); |
| 8728 | |
| 8729 | /* Write 4-byte data size. */ |
| 8730 | md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4); |
| 8731 | |
| 8732 | /* Write 4-byte data. */ |
| 8733 | md_number_to_chars (p + isa_1_descsz + 4 * 6, |
| 8734 | (valueT) x86_feature_2_used, 4); |
| 8735 | |
| 8736 | /* Zero out paddings. */ |
| 8737 | padding = feature_2_descsz - feature_2_descsz_raw; |
| 8738 | if (padding) |
| 8739 | memset (p + isa_1_descsz + 4 * 7, 0, padding); |
| 8740 | |
| 8741 | /* We probably can't restore the current segment, for there likely |
| 8742 | isn't one yet... */ |
| 8743 | if (seg && subseg) |
| 8744 | subseg_set (seg, subseg); |
| 8745 | } |
| 8746 | #endif |
| 8747 | |
| 8748 | static unsigned int |
| 8749 | encoding_length (const fragS *start_frag, offsetT start_off, |
| 8750 | const char *frag_now_ptr) |
| 8751 | { |
| 8752 | unsigned int len = 0; |
| 8753 | |
| 8754 | if (start_frag != frag_now) |
| 8755 | { |
| 8756 | const fragS *fr = start_frag; |
| 8757 | |
| 8758 | do { |
| 8759 | len += fr->fr_fix; |
| 8760 | fr = fr->fr_next; |
| 8761 | } while (fr && fr != frag_now); |
| 8762 | } |
| 8763 | |
| 8764 | return len - start_off + (frag_now_ptr - frag_now->fr_literal); |
| 8765 | } |
| 8766 | |
| 8767 | /* Return 1 for test, and, cmp, add, sub, inc and dec which may |
| 8768 | be macro-fused with conditional jumps. |
| 8769 | NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address, |
| 8770 | or is one of the following format: |
| 8771 | |
| 8772 | cmp m, imm |
| 8773 | add m, imm |
| 8774 | sub m, imm |
| 8775 | test m, imm |
| 8776 | and m, imm |
| 8777 | inc m |
| 8778 | dec m |
| 8779 | |
| 8780 | it is unfusible. */ |
| 8781 | |
| 8782 | static int |
| 8783 | maybe_fused_with_jcc_p (enum mf_cmp_kind* mf_cmp_p) |
| 8784 | { |
| 8785 | /* No RIP address. */ |
| 8786 | if (i.base_reg && i.base_reg->reg_num == RegIP) |
| 8787 | return 0; |
| 8788 | |
| 8789 | /* No VEX/EVEX encoding. */ |
| 8790 | if (is_any_vex_encoding (&i.tm)) |
| 8791 | return 0; |
| 8792 | |
| 8793 | /* add, sub without add/sub m, imm. */ |
| 8794 | if (i.tm.base_opcode <= 5 |
| 8795 | || (i.tm.base_opcode >= 0x28 && i.tm.base_opcode <= 0x2d) |
| 8796 | || ((i.tm.base_opcode | 3) == 0x83 |
| 8797 | && (i.tm.extension_opcode == 0x5 |
| 8798 | || i.tm.extension_opcode == 0x0))) |
| 8799 | { |
| 8800 | *mf_cmp_p = mf_cmp_alu_cmp; |
| 8801 | return !(i.mem_operands && i.imm_operands); |
| 8802 | } |
| 8803 | |
| 8804 | /* and without and m, imm. */ |
| 8805 | if ((i.tm.base_opcode >= 0x20 && i.tm.base_opcode <= 0x25) |
| 8806 | || ((i.tm.base_opcode | 3) == 0x83 |
| 8807 | && i.tm.extension_opcode == 0x4)) |
| 8808 | { |
| 8809 | *mf_cmp_p = mf_cmp_test_and; |
| 8810 | return !(i.mem_operands && i.imm_operands); |
| 8811 | } |
| 8812 | |
| 8813 | /* test without test m imm. */ |
| 8814 | if ((i.tm.base_opcode | 1) == 0x85 |
| 8815 | || (i.tm.base_opcode | 1) == 0xa9 |
| 8816 | || ((i.tm.base_opcode | 1) == 0xf7 |
| 8817 | && i.tm.extension_opcode == 0)) |
| 8818 | { |
| 8819 | *mf_cmp_p = mf_cmp_test_and; |
| 8820 | return !(i.mem_operands && i.imm_operands); |
| 8821 | } |
| 8822 | |
| 8823 | /* cmp without cmp m, imm. */ |
| 8824 | if ((i.tm.base_opcode >= 0x38 && i.tm.base_opcode <= 0x3d) |
| 8825 | || ((i.tm.base_opcode | 3) == 0x83 |
| 8826 | && (i.tm.extension_opcode == 0x7))) |
| 8827 | { |
| 8828 | *mf_cmp_p = mf_cmp_alu_cmp; |
| 8829 | return !(i.mem_operands && i.imm_operands); |
| 8830 | } |
| 8831 | |
| 8832 | /* inc, dec without inc/dec m. */ |
| 8833 | if ((i.tm.cpu_flags.bitfield.cpuno64 |
| 8834 | && (i.tm.base_opcode | 0xf) == 0x4f) |
| 8835 | || ((i.tm.base_opcode | 1) == 0xff |
| 8836 | && i.tm.extension_opcode <= 0x1)) |
| 8837 | { |
| 8838 | *mf_cmp_p = mf_cmp_incdec; |
| 8839 | return !i.mem_operands; |
| 8840 | } |
| 8841 | |
| 8842 | return 0; |
| 8843 | } |
| 8844 | |
| 8845 | /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */ |
| 8846 | |
| 8847 | static int |
| 8848 | add_fused_jcc_padding_frag_p (enum mf_cmp_kind* mf_cmp_p) |
| 8849 | { |
| 8850 | /* NB: Don't work with COND_JUMP86 without i386. */ |
| 8851 | if (!align_branch_power |
| 8852 | || now_seg == absolute_section |
| 8853 | || !cpu_arch_flags.bitfield.cpui386 |
| 8854 | || !(align_branch & align_branch_fused_bit)) |
| 8855 | return 0; |
| 8856 | |
| 8857 | if (maybe_fused_with_jcc_p (mf_cmp_p)) |
| 8858 | { |
| 8859 | if (last_insn.kind == last_insn_other |
| 8860 | || last_insn.seg != now_seg) |
| 8861 | return 1; |
| 8862 | if (flag_debug) |
| 8863 | as_warn_where (last_insn.file, last_insn.line, |
| 8864 | _("`%s` skips -malign-branch-boundary on `%s`"), |
| 8865 | last_insn.name, i.tm.name); |
| 8866 | } |
| 8867 | |
| 8868 | return 0; |
| 8869 | } |
| 8870 | |
| 8871 | /* Return 1 if a BRANCH_PREFIX frag should be generated. */ |
| 8872 | |
| 8873 | static int |
| 8874 | add_branch_prefix_frag_p (void) |
| 8875 | { |
| 8876 | /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix |
| 8877 | to PadLock instructions since they include prefixes in opcode. */ |
| 8878 | if (!align_branch_power |
| 8879 | || !align_branch_prefix_size |
| 8880 | || now_seg == absolute_section |
| 8881 | || i.tm.cpu_flags.bitfield.cpupadlock |
| 8882 | || !cpu_arch_flags.bitfield.cpui386) |
| 8883 | return 0; |
| 8884 | |
| 8885 | /* Don't add prefix if it is a prefix or there is no operand in case |
| 8886 | that segment prefix is special. */ |
| 8887 | if (!i.operands || i.tm.opcode_modifier.isprefix) |
| 8888 | return 0; |
| 8889 | |
| 8890 | if (last_insn.kind == last_insn_other |
| 8891 | || last_insn.seg != now_seg) |
| 8892 | return 1; |
| 8893 | |
| 8894 | if (flag_debug) |
| 8895 | as_warn_where (last_insn.file, last_insn.line, |
| 8896 | _("`%s` skips -malign-branch-boundary on `%s`"), |
| 8897 | last_insn.name, i.tm.name); |
| 8898 | |
| 8899 | return 0; |
| 8900 | } |
| 8901 | |
| 8902 | /* Return 1 if a BRANCH_PADDING frag should be generated. */ |
| 8903 | |
| 8904 | static int |
| 8905 | add_branch_padding_frag_p (enum align_branch_kind *branch_p, |
| 8906 | enum mf_jcc_kind *mf_jcc_p) |
| 8907 | { |
| 8908 | int add_padding; |
| 8909 | |
| 8910 | /* NB: Don't work with COND_JUMP86 without i386. */ |
| 8911 | if (!align_branch_power |
| 8912 | || now_seg == absolute_section |
| 8913 | || !cpu_arch_flags.bitfield.cpui386) |
| 8914 | return 0; |
| 8915 | |
| 8916 | add_padding = 0; |
| 8917 | |
| 8918 | /* Check for jcc and direct jmp. */ |
| 8919 | if (i.tm.opcode_modifier.jump == JUMP) |
| 8920 | { |
| 8921 | if (i.tm.base_opcode == JUMP_PC_RELATIVE) |
| 8922 | { |
| 8923 | *branch_p = align_branch_jmp; |
| 8924 | add_padding = align_branch & align_branch_jmp_bit; |
| 8925 | } |
| 8926 | else |
| 8927 | { |
| 8928 | /* Because J<cc> and JN<cc> share same group in macro-fusible table, |
| 8929 | igore the lowest bit. */ |
| 8930 | *mf_jcc_p = (i.tm.base_opcode & 0x0e) >> 1; |
| 8931 | *branch_p = align_branch_jcc; |
| 8932 | if ((align_branch & align_branch_jcc_bit)) |
| 8933 | add_padding = 1; |
| 8934 | } |
| 8935 | } |
| 8936 | else if (is_any_vex_encoding (&i.tm)) |
| 8937 | return 0; |
| 8938 | else if ((i.tm.base_opcode | 1) == 0xc3) |
| 8939 | { |
| 8940 | /* Near ret. */ |
| 8941 | *branch_p = align_branch_ret; |
| 8942 | if ((align_branch & align_branch_ret_bit)) |
| 8943 | add_padding = 1; |
| 8944 | } |
| 8945 | else |
| 8946 | { |
| 8947 | /* Check for indirect jmp, direct and indirect calls. */ |
| 8948 | if (i.tm.base_opcode == 0xe8) |
| 8949 | { |
| 8950 | /* Direct call. */ |
| 8951 | *branch_p = align_branch_call; |
| 8952 | if ((align_branch & align_branch_call_bit)) |
| 8953 | add_padding = 1; |
| 8954 | } |
| 8955 | else if (i.tm.base_opcode == 0xff |
| 8956 | && (i.tm.extension_opcode == 2 |
| 8957 | || i.tm.extension_opcode == 4)) |
| 8958 | { |
| 8959 | /* Indirect call and jmp. */ |
| 8960 | *branch_p = align_branch_indirect; |
| 8961 | if ((align_branch & align_branch_indirect_bit)) |
| 8962 | add_padding = 1; |
| 8963 | } |
| 8964 | |
| 8965 | if (add_padding |
| 8966 | && i.disp_operands |
| 8967 | && tls_get_addr |
| 8968 | && (i.op[0].disps->X_op == O_symbol |
| 8969 | || (i.op[0].disps->X_op == O_subtract |
| 8970 | && i.op[0].disps->X_op_symbol == GOT_symbol))) |
| 8971 | { |
| 8972 | symbolS *s = i.op[0].disps->X_add_symbol; |
| 8973 | /* No padding to call to global or undefined tls_get_addr. */ |
| 8974 | if ((S_IS_EXTERNAL (s) || !S_IS_DEFINED (s)) |
| 8975 | && strcmp (S_GET_NAME (s), tls_get_addr) == 0) |
| 8976 | return 0; |
| 8977 | } |
| 8978 | } |
| 8979 | |
| 8980 | if (add_padding |
| 8981 | && last_insn.kind != last_insn_other |
| 8982 | && last_insn.seg == now_seg) |
| 8983 | { |
| 8984 | if (flag_debug) |
| 8985 | as_warn_where (last_insn.file, last_insn.line, |
| 8986 | _("`%s` skips -malign-branch-boundary on `%s`"), |
| 8987 | last_insn.name, i.tm.name); |
| 8988 | return 0; |
| 8989 | } |
| 8990 | |
| 8991 | return add_padding; |
| 8992 | } |
| 8993 | |
| 8994 | static void |
| 8995 | output_insn (void) |
| 8996 | { |
| 8997 | fragS *insn_start_frag; |
| 8998 | offsetT insn_start_off; |
| 8999 | fragS *fragP = NULL; |
| 9000 | enum align_branch_kind branch = align_branch_none; |
| 9001 | /* The initializer is arbitrary just to avoid uninitialized error. |
| 9002 | it's actually either assigned in add_branch_padding_frag_p |
| 9003 | or never be used. */ |
| 9004 | enum mf_jcc_kind mf_jcc = mf_jcc_jo; |
| 9005 | |
| 9006 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 9007 | if (IS_ELF && x86_used_note) |
| 9008 | { |
| 9009 | if (i.tm.cpu_flags.bitfield.cpucmov) |
| 9010 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_CMOV; |
| 9011 | if (i.tm.cpu_flags.bitfield.cpusse) |
| 9012 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE; |
| 9013 | if (i.tm.cpu_flags.bitfield.cpusse2) |
| 9014 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE2; |
| 9015 | if (i.tm.cpu_flags.bitfield.cpusse3) |
| 9016 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE3; |
| 9017 | if (i.tm.cpu_flags.bitfield.cpussse3) |
| 9018 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSSE3; |
| 9019 | if (i.tm.cpu_flags.bitfield.cpusse4_1) |
| 9020 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_1; |
| 9021 | if (i.tm.cpu_flags.bitfield.cpusse4_2) |
| 9022 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_2; |
| 9023 | if (i.tm.cpu_flags.bitfield.cpuavx) |
| 9024 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX; |
| 9025 | if (i.tm.cpu_flags.bitfield.cpuavx2) |
| 9026 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX2; |
| 9027 | if (i.tm.cpu_flags.bitfield.cpufma) |
| 9028 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_FMA; |
| 9029 | if (i.tm.cpu_flags.bitfield.cpuavx512f) |
| 9030 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512F; |
| 9031 | if (i.tm.cpu_flags.bitfield.cpuavx512cd) |
| 9032 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512CD; |
| 9033 | if (i.tm.cpu_flags.bitfield.cpuavx512er) |
| 9034 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512ER; |
| 9035 | if (i.tm.cpu_flags.bitfield.cpuavx512pf) |
| 9036 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512PF; |
| 9037 | if (i.tm.cpu_flags.bitfield.cpuavx512vl) |
| 9038 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512VL; |
| 9039 | if (i.tm.cpu_flags.bitfield.cpuavx512dq) |
| 9040 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512DQ; |
| 9041 | if (i.tm.cpu_flags.bitfield.cpuavx512bw) |
| 9042 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512BW; |
| 9043 | if (i.tm.cpu_flags.bitfield.cpuavx512_4fmaps) |
| 9044 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS; |
| 9045 | if (i.tm.cpu_flags.bitfield.cpuavx512_4vnniw) |
| 9046 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW; |
| 9047 | if (i.tm.cpu_flags.bitfield.cpuavx512_bitalg) |
| 9048 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG; |
| 9049 | if (i.tm.cpu_flags.bitfield.cpuavx512ifma) |
| 9050 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA; |
| 9051 | if (i.tm.cpu_flags.bitfield.cpuavx512vbmi) |
| 9052 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI; |
| 9053 | if (i.tm.cpu_flags.bitfield.cpuavx512_vbmi2) |
| 9054 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2; |
| 9055 | if (i.tm.cpu_flags.bitfield.cpuavx512_vnni) |
| 9056 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI; |
| 9057 | if (i.tm.cpu_flags.bitfield.cpuavx512_bf16) |
| 9058 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BF16; |
| 9059 | |
| 9060 | if (i.tm.cpu_flags.bitfield.cpu8087 |
| 9061 | || i.tm.cpu_flags.bitfield.cpu287 |
| 9062 | || i.tm.cpu_flags.bitfield.cpu387 |
| 9063 | || i.tm.cpu_flags.bitfield.cpu687 |
| 9064 | || i.tm.cpu_flags.bitfield.cpufisttp) |
| 9065 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87; |
| 9066 | if (i.has_regmmx |
| 9067 | || i.tm.base_opcode == 0xf77 /* emms */ |
| 9068 | || i.tm.base_opcode == 0xf0e /* femms */ |
| 9069 | || i.tm.base_opcode == 0xf2a /* cvtpi2ps */ |
| 9070 | || i.tm.base_opcode == 0x660f2a /* cvtpi2pd */) |
| 9071 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX; |
| 9072 | if (i.has_regxmm) |
| 9073 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM; |
| 9074 | if (i.has_regymm) |
| 9075 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM; |
| 9076 | if (i.has_regzmm) |
| 9077 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM; |
| 9078 | if (i.tm.cpu_flags.bitfield.cpufxsr) |
| 9079 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR; |
| 9080 | if (i.tm.cpu_flags.bitfield.cpuxsave) |
| 9081 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE; |
| 9082 | if (i.tm.cpu_flags.bitfield.cpuxsaveopt) |
| 9083 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT; |
| 9084 | if (i.tm.cpu_flags.bitfield.cpuxsavec) |
| 9085 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC; |
| 9086 | } |
| 9087 | #endif |
| 9088 | |
| 9089 | /* Tie dwarf2 debug info to the address at the start of the insn. |
| 9090 | We can't do this after the insn has been output as the current |
| 9091 | frag may have been closed off. eg. by frag_var. */ |
| 9092 | dwarf2_emit_insn (0); |
| 9093 | |
| 9094 | insn_start_frag = frag_now; |
| 9095 | insn_start_off = frag_now_fix (); |
| 9096 | |
| 9097 | if (add_branch_padding_frag_p (&branch, &mf_jcc)) |
| 9098 | { |
| 9099 | char *p; |
| 9100 | /* Branch can be 8 bytes. Leave some room for prefixes. */ |
| 9101 | unsigned int max_branch_padding_size = 14; |
| 9102 | |
| 9103 | /* Align section to boundary. */ |
| 9104 | record_alignment (now_seg, align_branch_power); |
| 9105 | |
| 9106 | /* Make room for padding. */ |
| 9107 | frag_grow (max_branch_padding_size); |
| 9108 | |
| 9109 | /* Start of the padding. */ |
| 9110 | p = frag_more (0); |
| 9111 | |
| 9112 | fragP = frag_now; |
| 9113 | |
| 9114 | frag_var (rs_machine_dependent, max_branch_padding_size, 0, |
| 9115 | ENCODE_RELAX_STATE (BRANCH_PADDING, 0), |
| 9116 | NULL, 0, p); |
| 9117 | |
| 9118 | fragP->tc_frag_data.mf_type = mf_jcc; |
| 9119 | fragP->tc_frag_data.branch_type = branch; |
| 9120 | fragP->tc_frag_data.max_bytes = max_branch_padding_size; |
| 9121 | } |
| 9122 | |
| 9123 | /* Output jumps. */ |
| 9124 | if (i.tm.opcode_modifier.jump == JUMP) |
| 9125 | output_branch (); |
| 9126 | else if (i.tm.opcode_modifier.jump == JUMP_BYTE |
| 9127 | || i.tm.opcode_modifier.jump == JUMP_DWORD) |
| 9128 | output_jump (); |
| 9129 | else if (i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT) |
| 9130 | output_interseg_jump (); |
| 9131 | else |
| 9132 | { |
| 9133 | /* Output normal instructions here. */ |
| 9134 | char *p; |
| 9135 | unsigned char *q; |
| 9136 | unsigned int j; |
| 9137 | unsigned int prefix; |
| 9138 | enum mf_cmp_kind mf_cmp; |
| 9139 | |
| 9140 | if (avoid_fence |
| 9141 | && (i.tm.base_opcode == 0xfaee8 |
| 9142 | || i.tm.base_opcode == 0xfaef0 |
| 9143 | || i.tm.base_opcode == 0xfaef8)) |
| 9144 | { |
| 9145 | /* Encode lfence, mfence, and sfence as |
| 9146 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ |
| 9147 | offsetT val = 0x240483f0ULL; |
| 9148 | p = frag_more (5); |
| 9149 | md_number_to_chars (p, val, 5); |
| 9150 | return; |
| 9151 | } |
| 9152 | |
| 9153 | /* Some processors fail on LOCK prefix. This options makes |
| 9154 | assembler ignore LOCK prefix and serves as a workaround. */ |
| 9155 | if (omit_lock_prefix) |
| 9156 | { |
| 9157 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE) |
| 9158 | return; |
| 9159 | i.prefix[LOCK_PREFIX] = 0; |
| 9160 | } |
| 9161 | |
| 9162 | if (branch) |
| 9163 | /* Skip if this is a branch. */ |
| 9164 | ; |
| 9165 | else if (add_fused_jcc_padding_frag_p (&mf_cmp)) |
| 9166 | { |
| 9167 | /* Make room for padding. */ |
| 9168 | frag_grow (MAX_FUSED_JCC_PADDING_SIZE); |
| 9169 | p = frag_more (0); |
| 9170 | |
| 9171 | fragP = frag_now; |
| 9172 | |
| 9173 | frag_var (rs_machine_dependent, MAX_FUSED_JCC_PADDING_SIZE, 0, |
| 9174 | ENCODE_RELAX_STATE (FUSED_JCC_PADDING, 0), |
| 9175 | NULL, 0, p); |
| 9176 | |
| 9177 | fragP->tc_frag_data.mf_type = mf_cmp; |
| 9178 | fragP->tc_frag_data.branch_type = align_branch_fused; |
| 9179 | fragP->tc_frag_data.max_bytes = MAX_FUSED_JCC_PADDING_SIZE; |
| 9180 | } |
| 9181 | else if (add_branch_prefix_frag_p ()) |
| 9182 | { |
| 9183 | unsigned int max_prefix_size = align_branch_prefix_size; |
| 9184 | |
| 9185 | /* Make room for padding. */ |
| 9186 | frag_grow (max_prefix_size); |
| 9187 | p = frag_more (0); |
| 9188 | |
| 9189 | fragP = frag_now; |
| 9190 | |
| 9191 | frag_var (rs_machine_dependent, max_prefix_size, 0, |
| 9192 | ENCODE_RELAX_STATE (BRANCH_PREFIX, 0), |
| 9193 | NULL, 0, p); |
| 9194 | |
| 9195 | fragP->tc_frag_data.max_bytes = max_prefix_size; |
| 9196 | } |
| 9197 | |
| 9198 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
| 9199 | don't need the explicit prefix. */ |
| 9200 | if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) |
| 9201 | { |
| 9202 | switch (i.tm.opcode_length) |
| 9203 | { |
| 9204 | case 3: |
| 9205 | if (i.tm.base_opcode & 0xff000000) |
| 9206 | { |
| 9207 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
| 9208 | if (!i.tm.cpu_flags.bitfield.cpupadlock |
| 9209 | || prefix != REPE_PREFIX_OPCODE |
| 9210 | || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE)) |
| 9211 | add_prefix (prefix); |
| 9212 | } |
| 9213 | break; |
| 9214 | case 2: |
| 9215 | if ((i.tm.base_opcode & 0xff0000) != 0) |
| 9216 | { |
| 9217 | prefix = (i.tm.base_opcode >> 16) & 0xff; |
| 9218 | add_prefix (prefix); |
| 9219 | } |
| 9220 | break; |
| 9221 | case 1: |
| 9222 | break; |
| 9223 | case 0: |
| 9224 | /* Check for pseudo prefixes. */ |
| 9225 | as_bad_where (insn_start_frag->fr_file, |
| 9226 | insn_start_frag->fr_line, |
| 9227 | _("pseudo prefix without instruction")); |
| 9228 | return; |
| 9229 | default: |
| 9230 | abort (); |
| 9231 | } |
| 9232 | |
| 9233 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
| 9234 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
| 9235 | R_X86_64_GOTTPOFF relocation so that linker can safely |
| 9236 | perform IE->LE optimization. A dummy REX_OPCODE prefix |
| 9237 | is also needed for lea with R_X86_64_GOTPC32_TLSDESC |
| 9238 | relocation for GDesc -> IE/LE optimization. */ |
| 9239 | if (x86_elf_abi == X86_64_X32_ABI |
| 9240 | && i.operands == 2 |
| 9241 | && (i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF |
| 9242 | || i.reloc[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC) |
| 9243 | && i.prefix[REX_PREFIX] == 0) |
| 9244 | add_prefix (REX_OPCODE); |
| 9245 | #endif |
| 9246 | |
| 9247 | /* The prefix bytes. */ |
| 9248 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) |
| 9249 | if (*q) |
| 9250 | FRAG_APPEND_1_CHAR (*q); |
| 9251 | } |
| 9252 | else |
| 9253 | { |
| 9254 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) |
| 9255 | if (*q) |
| 9256 | switch (j) |
| 9257 | { |
| 9258 | case REX_PREFIX: |
| 9259 | /* REX byte is encoded in VEX prefix. */ |
| 9260 | break; |
| 9261 | case SEG_PREFIX: |
| 9262 | case ADDR_PREFIX: |
| 9263 | FRAG_APPEND_1_CHAR (*q); |
| 9264 | break; |
| 9265 | default: |
| 9266 | /* There should be no other prefixes for instructions |
| 9267 | with VEX prefix. */ |
| 9268 | abort (); |
| 9269 | } |
| 9270 | |
| 9271 | /* For EVEX instructions i.vrex should become 0 after |
| 9272 | build_evex_prefix. For VEX instructions upper 16 registers |
| 9273 | aren't available, so VREX should be 0. */ |
| 9274 | if (i.vrex) |
| 9275 | abort (); |
| 9276 | /* Now the VEX prefix. */ |
| 9277 | p = frag_more (i.vex.length); |
| 9278 | for (j = 0; j < i.vex.length; j++) |
| 9279 | p[j] = i.vex.bytes[j]; |
| 9280 | } |
| 9281 | |
| 9282 | /* Now the opcode; be careful about word order here! */ |
| 9283 | if (i.tm.opcode_length == 1) |
| 9284 | { |
| 9285 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); |
| 9286 | } |
| 9287 | else |
| 9288 | { |
| 9289 | switch (i.tm.opcode_length) |
| 9290 | { |
| 9291 | case 4: |
| 9292 | p = frag_more (4); |
| 9293 | *p++ = (i.tm.base_opcode >> 24) & 0xff; |
| 9294 | *p++ = (i.tm.base_opcode >> 16) & 0xff; |
| 9295 | break; |
| 9296 | case 3: |
| 9297 | p = frag_more (3); |
| 9298 | *p++ = (i.tm.base_opcode >> 16) & 0xff; |
| 9299 | break; |
| 9300 | case 2: |
| 9301 | p = frag_more (2); |
| 9302 | break; |
| 9303 | default: |
| 9304 | abort (); |
| 9305 | break; |
| 9306 | } |
| 9307 | |
| 9308 | /* Put out high byte first: can't use md_number_to_chars! */ |
| 9309 | *p++ = (i.tm.base_opcode >> 8) & 0xff; |
| 9310 | *p = i.tm.base_opcode & 0xff; |
| 9311 | } |
| 9312 | |
| 9313 | /* Now the modrm byte and sib byte (if present). */ |
| 9314 | if (i.tm.opcode_modifier.modrm) |
| 9315 | { |
| 9316 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
| 9317 | | i.rm.reg << 3 |
| 9318 | | i.rm.mode << 6)); |
| 9319 | /* If i.rm.regmem == ESP (4) |
| 9320 | && i.rm.mode != (Register mode) |
| 9321 | && not 16 bit |
| 9322 | ==> need second modrm byte. */ |
| 9323 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING |
| 9324 | && i.rm.mode != 3 |
| 9325 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
| 9326 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
| 9327 | | i.sib.index << 3 |
| 9328 | | i.sib.scale << 6)); |
| 9329 | } |
| 9330 | |
| 9331 | if (i.disp_operands) |
| 9332 | output_disp (insn_start_frag, insn_start_off); |
| 9333 | |
| 9334 | if (i.imm_operands) |
| 9335 | output_imm (insn_start_frag, insn_start_off); |
| 9336 | |
| 9337 | /* |
| 9338 | * frag_now_fix () returning plain abs_section_offset when we're in the |
| 9339 | * absolute section, and abs_section_offset not getting updated as data |
| 9340 | * gets added to the frag breaks the logic below. |
| 9341 | */ |
| 9342 | if (now_seg != absolute_section) |
| 9343 | { |
| 9344 | j = encoding_length (insn_start_frag, insn_start_off, frag_more (0)); |
| 9345 | if (j > 15) |
| 9346 | as_warn (_("instruction length of %u bytes exceeds the limit of 15"), |
| 9347 | j); |
| 9348 | else if (fragP) |
| 9349 | { |
| 9350 | /* NB: Don't add prefix with GOTPC relocation since |
| 9351 | output_disp() above depends on the fixed encoding |
| 9352 | length. Can't add prefix with TLS relocation since |
| 9353 | it breaks TLS linker optimization. */ |
| 9354 | unsigned int max = i.has_gotpc_tls_reloc ? 0 : 15 - j; |
| 9355 | /* Prefix count on the current instruction. */ |
| 9356 | unsigned int count = i.vex.length; |
| 9357 | unsigned int k; |
| 9358 | for (k = 0; k < ARRAY_SIZE (i.prefix); k++) |
| 9359 | /* REX byte is encoded in VEX/EVEX prefix. */ |
| 9360 | if (i.prefix[k] && (k != REX_PREFIX || !i.vex.length)) |
| 9361 | count++; |
| 9362 | |
| 9363 | /* Count prefixes for extended opcode maps. */ |
| 9364 | if (!i.vex.length) |
| 9365 | switch (i.tm.opcode_length) |
| 9366 | { |
| 9367 | case 3: |
| 9368 | if (((i.tm.base_opcode >> 16) & 0xff) == 0xf) |
| 9369 | { |
| 9370 | count++; |
| 9371 | switch ((i.tm.base_opcode >> 8) & 0xff) |
| 9372 | { |
| 9373 | case 0x38: |
| 9374 | case 0x3a: |
| 9375 | count++; |
| 9376 | break; |
| 9377 | default: |
| 9378 | break; |
| 9379 | } |
| 9380 | } |
| 9381 | break; |
| 9382 | case 2: |
| 9383 | if (((i.tm.base_opcode >> 8) & 0xff) == 0xf) |
| 9384 | count++; |
| 9385 | break; |
| 9386 | case 1: |
| 9387 | break; |
| 9388 | default: |
| 9389 | abort (); |
| 9390 | } |
| 9391 | |
| 9392 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) |
| 9393 | == BRANCH_PREFIX) |
| 9394 | { |
| 9395 | /* Set the maximum prefix size in BRANCH_PREFIX |
| 9396 | frag. */ |
| 9397 | if (fragP->tc_frag_data.max_bytes > max) |
| 9398 | fragP->tc_frag_data.max_bytes = max; |
| 9399 | if (fragP->tc_frag_data.max_bytes > count) |
| 9400 | fragP->tc_frag_data.max_bytes -= count; |
| 9401 | else |
| 9402 | fragP->tc_frag_data.max_bytes = 0; |
| 9403 | } |
| 9404 | else |
| 9405 | { |
| 9406 | /* Remember the maximum prefix size in FUSED_JCC_PADDING |
| 9407 | frag. */ |
| 9408 | unsigned int max_prefix_size; |
| 9409 | if (align_branch_prefix_size > max) |
| 9410 | max_prefix_size = max; |
| 9411 | else |
| 9412 | max_prefix_size = align_branch_prefix_size; |
| 9413 | if (max_prefix_size > count) |
| 9414 | fragP->tc_frag_data.max_prefix_length |
| 9415 | = max_prefix_size - count; |
| 9416 | } |
| 9417 | |
| 9418 | /* Use existing segment prefix if possible. Use CS |
| 9419 | segment prefix in 64-bit mode. In 32-bit mode, use SS |
| 9420 | segment prefix with ESP/EBP base register and use DS |
| 9421 | segment prefix without ESP/EBP base register. */ |
| 9422 | if (i.prefix[SEG_PREFIX]) |
| 9423 | fragP->tc_frag_data.default_prefix = i.prefix[SEG_PREFIX]; |
| 9424 | else if (flag_code == CODE_64BIT) |
| 9425 | fragP->tc_frag_data.default_prefix = CS_PREFIX_OPCODE; |
| 9426 | else if (i.base_reg |
| 9427 | && (i.base_reg->reg_num == 4 |
| 9428 | || i.base_reg->reg_num == 5)) |
| 9429 | fragP->tc_frag_data.default_prefix = SS_PREFIX_OPCODE; |
| 9430 | else |
| 9431 | fragP->tc_frag_data.default_prefix = DS_PREFIX_OPCODE; |
| 9432 | } |
| 9433 | } |
| 9434 | } |
| 9435 | |
| 9436 | /* NB: Don't work with COND_JUMP86 without i386. */ |
| 9437 | if (align_branch_power |
| 9438 | && now_seg != absolute_section |
| 9439 | && cpu_arch_flags.bitfield.cpui386) |
| 9440 | { |
| 9441 | /* Terminate each frag so that we can add prefix and check for |
| 9442 | fused jcc. */ |
| 9443 | frag_wane (frag_now); |
| 9444 | frag_new (0); |
| 9445 | } |
| 9446 | |
| 9447 | #ifdef DEBUG386 |
| 9448 | if (flag_debug) |
| 9449 | { |
| 9450 | pi ("" /*line*/, &i); |
| 9451 | } |
| 9452 | #endif /* DEBUG386 */ |
| 9453 | } |
| 9454 | |
| 9455 | /* Return the size of the displacement operand N. */ |
| 9456 | |
| 9457 | static int |
| 9458 | disp_size (unsigned int n) |
| 9459 | { |
| 9460 | int size = 4; |
| 9461 | |
| 9462 | if (i.types[n].bitfield.disp64) |
| 9463 | size = 8; |
| 9464 | else if (i.types[n].bitfield.disp8) |
| 9465 | size = 1; |
| 9466 | else if (i.types[n].bitfield.disp16) |
| 9467 | size = 2; |
| 9468 | return size; |
| 9469 | } |
| 9470 | |
| 9471 | /* Return the size of the immediate operand N. */ |
| 9472 | |
| 9473 | static int |
| 9474 | imm_size (unsigned int n) |
| 9475 | { |
| 9476 | int size = 4; |
| 9477 | if (i.types[n].bitfield.imm64) |
| 9478 | size = 8; |
| 9479 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) |
| 9480 | size = 1; |
| 9481 | else if (i.types[n].bitfield.imm16) |
| 9482 | size = 2; |
| 9483 | return size; |
| 9484 | } |
| 9485 | |
| 9486 | static void |
| 9487 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
| 9488 | { |
| 9489 | char *p; |
| 9490 | unsigned int n; |
| 9491 | |
| 9492 | for (n = 0; n < i.operands; n++) |
| 9493 | { |
| 9494 | if (operand_type_check (i.types[n], disp)) |
| 9495 | { |
| 9496 | if (i.op[n].disps->X_op == O_constant) |
| 9497 | { |
| 9498 | int size = disp_size (n); |
| 9499 | offsetT val = i.op[n].disps->X_add_number; |
| 9500 | |
| 9501 | val = offset_in_range (val >> (size == 1 ? i.memshift : 0), |
| 9502 | size); |
| 9503 | p = frag_more (size); |
| 9504 | md_number_to_chars (p, val, size); |
| 9505 | } |
| 9506 | else |
| 9507 | { |
| 9508 | enum bfd_reloc_code_real reloc_type; |
| 9509 | int size = disp_size (n); |
| 9510 | int sign = i.types[n].bitfield.disp32s; |
| 9511 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
| 9512 | fixS *fixP; |
| 9513 | |
| 9514 | /* We can't have 8 bit displacement here. */ |
| 9515 | gas_assert (!i.types[n].bitfield.disp8); |
| 9516 | |
| 9517 | /* The PC relative address is computed relative |
| 9518 | to the instruction boundary, so in case immediate |
| 9519 | fields follows, we need to adjust the value. */ |
| 9520 | if (pcrel && i.imm_operands) |
| 9521 | { |
| 9522 | unsigned int n1; |
| 9523 | int sz = 0; |
| 9524 | |
| 9525 | for (n1 = 0; n1 < i.operands; n1++) |
| 9526 | if (operand_type_check (i.types[n1], imm)) |
| 9527 | { |
| 9528 | /* Only one immediate is allowed for PC |
| 9529 | relative address. */ |
| 9530 | gas_assert (sz == 0); |
| 9531 | sz = imm_size (n1); |
| 9532 | i.op[n].disps->X_add_number -= sz; |
| 9533 | } |
| 9534 | /* We should find the immediate. */ |
| 9535 | gas_assert (sz != 0); |
| 9536 | } |
| 9537 | |
| 9538 | p = frag_more (size); |
| 9539 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
| 9540 | if (GOT_symbol |
| 9541 | && GOT_symbol == i.op[n].disps->X_add_symbol |
| 9542 | && (((reloc_type == BFD_RELOC_32 |
| 9543 | || reloc_type == BFD_RELOC_X86_64_32S |
| 9544 | || (reloc_type == BFD_RELOC_64 |
| 9545 | && object_64bit)) |
| 9546 | && (i.op[n].disps->X_op == O_symbol |
| 9547 | || (i.op[n].disps->X_op == O_add |
| 9548 | && ((symbol_get_value_expression |
| 9549 | (i.op[n].disps->X_op_symbol)->X_op) |
| 9550 | == O_subtract)))) |
| 9551 | || reloc_type == BFD_RELOC_32_PCREL)) |
| 9552 | { |
| 9553 | if (!object_64bit) |
| 9554 | { |
| 9555 | reloc_type = BFD_RELOC_386_GOTPC; |
| 9556 | i.has_gotpc_tls_reloc = TRUE; |
| 9557 | i.op[n].imms->X_add_number += |
| 9558 | encoding_length (insn_start_frag, insn_start_off, p); |
| 9559 | } |
| 9560 | else if (reloc_type == BFD_RELOC_64) |
| 9561 | reloc_type = BFD_RELOC_X86_64_GOTPC64; |
| 9562 | else |
| 9563 | /* Don't do the adjustment for x86-64, as there |
| 9564 | the pcrel addressing is relative to the _next_ |
| 9565 | insn, and that is taken care of in other code. */ |
| 9566 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
| 9567 | } |
| 9568 | else if (align_branch_power) |
| 9569 | { |
| 9570 | switch (reloc_type) |
| 9571 | { |
| 9572 | case BFD_RELOC_386_TLS_GD: |
| 9573 | case BFD_RELOC_386_TLS_LDM: |
| 9574 | case BFD_RELOC_386_TLS_IE: |
| 9575 | case BFD_RELOC_386_TLS_IE_32: |
| 9576 | case BFD_RELOC_386_TLS_GOTIE: |
| 9577 | case BFD_RELOC_386_TLS_GOTDESC: |
| 9578 | case BFD_RELOC_386_TLS_DESC_CALL: |
| 9579 | case BFD_RELOC_X86_64_TLSGD: |
| 9580 | case BFD_RELOC_X86_64_TLSLD: |
| 9581 | case BFD_RELOC_X86_64_GOTTPOFF: |
| 9582 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
| 9583 | case BFD_RELOC_X86_64_TLSDESC_CALL: |
| 9584 | i.has_gotpc_tls_reloc = TRUE; |
| 9585 | default: |
| 9586 | break; |
| 9587 | } |
| 9588 | } |
| 9589 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
| 9590 | size, i.op[n].disps, pcrel, |
| 9591 | reloc_type); |
| 9592 | /* Check for "call/jmp *mem", "mov mem, %reg", |
| 9593 | "test %reg, mem" and "binop mem, %reg" where binop |
| 9594 | is one of adc, add, and, cmp, or, sbb, sub, xor |
| 9595 | instructions without data prefix. Always generate |
| 9596 | R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */ |
| 9597 | if (i.prefix[DATA_PREFIX] == 0 |
| 9598 | && (generate_relax_relocations |
| 9599 | || (!object_64bit |
| 9600 | && i.rm.mode == 0 |
| 9601 | && i.rm.regmem == 5)) |
| 9602 | && (i.rm.mode == 2 |
| 9603 | || (i.rm.mode == 0 && i.rm.regmem == 5)) |
| 9604 | && !is_any_vex_encoding(&i.tm) |
| 9605 | && ((i.operands == 1 |
| 9606 | && i.tm.base_opcode == 0xff |
| 9607 | && (i.rm.reg == 2 || i.rm.reg == 4)) |
| 9608 | || (i.operands == 2 |
| 9609 | && (i.tm.base_opcode == 0x8b |
| 9610 | || i.tm.base_opcode == 0x85 |
| 9611 | || (i.tm.base_opcode & ~0x38) == 0x03)))) |
| 9612 | { |
| 9613 | if (object_64bit) |
| 9614 | { |
| 9615 | fixP->fx_tcbit = i.rex != 0; |
| 9616 | if (i.base_reg |
| 9617 | && (i.base_reg->reg_num == RegIP)) |
| 9618 | fixP->fx_tcbit2 = 1; |
| 9619 | } |
| 9620 | else |
| 9621 | fixP->fx_tcbit2 = 1; |
| 9622 | } |
| 9623 | } |
| 9624 | } |
| 9625 | } |
| 9626 | } |
| 9627 | |
| 9628 | static void |
| 9629 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
| 9630 | { |
| 9631 | char *p; |
| 9632 | unsigned int n; |
| 9633 | |
| 9634 | for (n = 0; n < i.operands; n++) |
| 9635 | { |
| 9636 | /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ |
| 9637 | if (i.rounding && (int) n == i.rounding->operand) |
| 9638 | continue; |
| 9639 | |
| 9640 | if (operand_type_check (i.types[n], imm)) |
| 9641 | { |
| 9642 | if (i.op[n].imms->X_op == O_constant) |
| 9643 | { |
| 9644 | int size = imm_size (n); |
| 9645 | offsetT val; |
| 9646 | |
| 9647 | val = offset_in_range (i.op[n].imms->X_add_number, |
| 9648 | size); |
| 9649 | p = frag_more (size); |
| 9650 | md_number_to_chars (p, val, size); |
| 9651 | } |
| 9652 | else |
| 9653 | { |
| 9654 | /* Not absolute_section. |
| 9655 | Need a 32-bit fixup (don't support 8bit |
| 9656 | non-absolute imms). Try to support other |
| 9657 | sizes ... */ |
| 9658 | enum bfd_reloc_code_real reloc_type; |
| 9659 | int size = imm_size (n); |
| 9660 | int sign; |
| 9661 | |
| 9662 | if (i.types[n].bitfield.imm32s |
| 9663 | && (i.suffix == QWORD_MNEM_SUFFIX |
| 9664 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
| 9665 | sign = 1; |
| 9666 | else |
| 9667 | sign = 0; |
| 9668 | |
| 9669 | p = frag_more (size); |
| 9670 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
| 9671 | |
| 9672 | /* This is tough to explain. We end up with this one if we |
| 9673 | * have operands that look like |
| 9674 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to |
| 9675 | * obtain the absolute address of the GOT, and it is strongly |
| 9676 | * preferable from a performance point of view to avoid using |
| 9677 | * a runtime relocation for this. The actual sequence of |
| 9678 | * instructions often look something like: |
| 9679 | * |
| 9680 | * call .L66 |
| 9681 | * .L66: |
| 9682 | * popl %ebx |
| 9683 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx |
| 9684 | * |
| 9685 | * The call and pop essentially return the absolute address |
| 9686 | * of the label .L66 and store it in %ebx. The linker itself |
| 9687 | * will ultimately change the first operand of the addl so |
| 9688 | * that %ebx points to the GOT, but to keep things simple, the |
| 9689 | * .o file must have this operand set so that it generates not |
| 9690 | * the absolute address of .L66, but the absolute address of |
| 9691 | * itself. This allows the linker itself simply treat a GOTPC |
| 9692 | * relocation as asking for a pcrel offset to the GOT to be |
| 9693 | * added in, and the addend of the relocation is stored in the |
| 9694 | * operand field for the instruction itself. |
| 9695 | * |
| 9696 | * Our job here is to fix the operand so that it would add |
| 9697 | * the correct offset so that %ebx would point to itself. The |
| 9698 | * thing that is tricky is that .-.L66 will point to the |
| 9699 | * beginning of the instruction, so we need to further modify |
| 9700 | * the operand so that it will point to itself. There are |
| 9701 | * other cases where you have something like: |
| 9702 | * |
| 9703 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] |
| 9704 | * |
| 9705 | * and here no correction would be required. Internally in |
| 9706 | * the assembler we treat operands of this form as not being |
| 9707 | * pcrel since the '.' is explicitly mentioned, and I wonder |
| 9708 | * whether it would simplify matters to do it this way. Who |
| 9709 | * knows. In earlier versions of the PIC patches, the |
| 9710 | * pcrel_adjust field was used to store the correction, but |
| 9711 | * since the expression is not pcrel, I felt it would be |
| 9712 | * confusing to do it this way. */ |
| 9713 | |
| 9714 | if ((reloc_type == BFD_RELOC_32 |
| 9715 | || reloc_type == BFD_RELOC_X86_64_32S |
| 9716 | || reloc_type == BFD_RELOC_64) |
| 9717 | && GOT_symbol |
| 9718 | && GOT_symbol == i.op[n].imms->X_add_symbol |
| 9719 | && (i.op[n].imms->X_op == O_symbol |
| 9720 | || (i.op[n].imms->X_op == O_add |
| 9721 | && ((symbol_get_value_expression |
| 9722 | (i.op[n].imms->X_op_symbol)->X_op) |
| 9723 | == O_subtract)))) |
| 9724 | { |
| 9725 | if (!object_64bit) |
| 9726 | reloc_type = BFD_RELOC_386_GOTPC; |
| 9727 | else if (size == 4) |
| 9728 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
| 9729 | else if (size == 8) |
| 9730 | reloc_type = BFD_RELOC_X86_64_GOTPC64; |
| 9731 | i.has_gotpc_tls_reloc = TRUE; |
| 9732 | i.op[n].imms->X_add_number += |
| 9733 | encoding_length (insn_start_frag, insn_start_off, p); |
| 9734 | } |
| 9735 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
| 9736 | i.op[n].imms, 0, reloc_type); |
| 9737 | } |
| 9738 | } |
| 9739 | } |
| 9740 | } |
| 9741 | \f |
| 9742 | /* x86_cons_fix_new is called via the expression parsing code when a |
| 9743 | reloc is needed. We use this hook to get the correct .got reloc. */ |
| 9744 | static int cons_sign = -1; |
| 9745 | |
| 9746 | void |
| 9747 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
| 9748 | expressionS *exp, bfd_reloc_code_real_type r) |
| 9749 | { |
| 9750 | r = reloc (len, 0, cons_sign, r); |
| 9751 | |
| 9752 | #ifdef TE_PE |
| 9753 | if (exp->X_op == O_secrel) |
| 9754 | { |
| 9755 | exp->X_op = O_symbol; |
| 9756 | r = BFD_RELOC_32_SECREL; |
| 9757 | } |
| 9758 | #endif |
| 9759 | |
| 9760 | fix_new_exp (frag, off, len, exp, 0, r); |
| 9761 | } |
| 9762 | |
| 9763 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
| 9764 | purpose of the `.dc.a' internal pseudo-op. */ |
| 9765 | |
| 9766 | int |
| 9767 | x86_address_bytes (void) |
| 9768 | { |
| 9769 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) |
| 9770 | return 4; |
| 9771 | return stdoutput->arch_info->bits_per_address / 8; |
| 9772 | } |
| 9773 | |
| 9774 | #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
| 9775 | || defined (LEX_AT) |
| 9776 | # define lex_got(reloc, adjust, types) NULL |
| 9777 | #else |
| 9778 | /* Parse operands of the form |
| 9779 | <symbol>@GOTOFF+<nnn> |
| 9780 | and similar .plt or .got references. |
| 9781 | |
| 9782 | If we find one, set up the correct relocation in RELOC and copy the |
| 9783 | input string, minus the `@GOTOFF' into a malloc'd buffer for |
| 9784 | parsing by the calling routine. Return this buffer, and if ADJUST |
| 9785 | is non-null set it to the length of the string we removed from the |
| 9786 | input line. Otherwise return NULL. */ |
| 9787 | static char * |
| 9788 | lex_got (enum bfd_reloc_code_real *rel, |
| 9789 | int *adjust, |
| 9790 | i386_operand_type *types) |
| 9791 | { |
| 9792 | /* Some of the relocations depend on the size of what field is to |
| 9793 | be relocated. But in our callers i386_immediate and i386_displacement |
| 9794 | we don't yet know the operand size (this will be set by insn |
| 9795 | matching). Hence we record the word32 relocation here, |
| 9796 | and adjust the reloc according to the real size in reloc(). */ |
| 9797 | static const struct { |
| 9798 | const char *str; |
| 9799 | int len; |
| 9800 | const enum bfd_reloc_code_real rel[2]; |
| 9801 | const i386_operand_type types64; |
| 9802 | } gotrel[] = { |
| 9803 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 9804 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
| 9805 | BFD_RELOC_SIZE32 }, |
| 9806 | OPERAND_TYPE_IMM32_64 }, |
| 9807 | #endif |
| 9808 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
| 9809 | BFD_RELOC_X86_64_PLTOFF64 }, |
| 9810 | OPERAND_TYPE_IMM64 }, |
| 9811 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
| 9812 | BFD_RELOC_X86_64_PLT32 }, |
| 9813 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
| 9814 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
| 9815 | BFD_RELOC_X86_64_GOTPLT64 }, |
| 9816 | OPERAND_TYPE_IMM64_DISP64 }, |
| 9817 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
| 9818 | BFD_RELOC_X86_64_GOTOFF64 }, |
| 9819 | OPERAND_TYPE_IMM64_DISP64 }, |
| 9820 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
| 9821 | BFD_RELOC_X86_64_GOTPCREL }, |
| 9822 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
| 9823 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
| 9824 | BFD_RELOC_X86_64_TLSGD }, |
| 9825 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
| 9826 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
| 9827 | _dummy_first_bfd_reloc_code_real }, |
| 9828 | OPERAND_TYPE_NONE }, |
| 9829 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
| 9830 | BFD_RELOC_X86_64_TLSLD }, |
| 9831 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
| 9832 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
| 9833 | BFD_RELOC_X86_64_GOTTPOFF }, |
| 9834 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
| 9835 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
| 9836 | BFD_RELOC_X86_64_TPOFF32 }, |
| 9837 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
| 9838 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
| 9839 | _dummy_first_bfd_reloc_code_real }, |
| 9840 | OPERAND_TYPE_NONE }, |
| 9841 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
| 9842 | BFD_RELOC_X86_64_DTPOFF32 }, |
| 9843 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
| 9844 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
| 9845 | _dummy_first_bfd_reloc_code_real }, |
| 9846 | OPERAND_TYPE_NONE }, |
| 9847 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
| 9848 | _dummy_first_bfd_reloc_code_real }, |
| 9849 | OPERAND_TYPE_NONE }, |
| 9850 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
| 9851 | BFD_RELOC_X86_64_GOT32 }, |
| 9852 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
| 9853 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
| 9854 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, |
| 9855 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
| 9856 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
| 9857 | BFD_RELOC_X86_64_TLSDESC_CALL }, |
| 9858 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
| 9859 | }; |
| 9860 | char *cp; |
| 9861 | unsigned int j; |
| 9862 | |
| 9863 | #if defined (OBJ_MAYBE_ELF) |
| 9864 | if (!IS_ELF) |
| 9865 | return NULL; |
| 9866 | #endif |
| 9867 | |
| 9868 | for (cp = input_line_pointer; *cp != '@'; cp++) |
| 9869 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
| 9870 | return NULL; |
| 9871 | |
| 9872 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
| 9873 | { |
| 9874 | int len = gotrel[j].len; |
| 9875 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
| 9876 | { |
| 9877 | if (gotrel[j].rel[object_64bit] != 0) |
| 9878 | { |
| 9879 | int first, second; |
| 9880 | char *tmpbuf, *past_reloc; |
| 9881 | |
| 9882 | *rel = gotrel[j].rel[object_64bit]; |
| 9883 | |
| 9884 | if (types) |
| 9885 | { |
| 9886 | if (flag_code != CODE_64BIT) |
| 9887 | { |
| 9888 | types->bitfield.imm32 = 1; |
| 9889 | types->bitfield.disp32 = 1; |
| 9890 | } |
| 9891 | else |
| 9892 | *types = gotrel[j].types64; |
| 9893 | } |
| 9894 | |
| 9895 | if (j != 0 && GOT_symbol == NULL) |
| 9896 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
| 9897 | |
| 9898 | /* The length of the first part of our input line. */ |
| 9899 | first = cp - input_line_pointer; |
| 9900 | |
| 9901 | /* The second part goes from after the reloc token until |
| 9902 | (and including) an end_of_line char or comma. */ |
| 9903 | past_reloc = cp + 1 + len; |
| 9904 | cp = past_reloc; |
| 9905 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') |
| 9906 | ++cp; |
| 9907 | second = cp + 1 - past_reloc; |
| 9908 | |
| 9909 | /* Allocate and copy string. The trailing NUL shouldn't |
| 9910 | be necessary, but be safe. */ |
| 9911 | tmpbuf = XNEWVEC (char, first + second + 2); |
| 9912 | memcpy (tmpbuf, input_line_pointer, first); |
| 9913 | if (second != 0 && *past_reloc != ' ') |
| 9914 | /* Replace the relocation token with ' ', so that |
| 9915 | errors like foo@GOTOFF1 will be detected. */ |
| 9916 | tmpbuf[first++] = ' '; |
| 9917 | else |
| 9918 | /* Increment length by 1 if the relocation token is |
| 9919 | removed. */ |
| 9920 | len++; |
| 9921 | if (adjust) |
| 9922 | *adjust = len; |
| 9923 | memcpy (tmpbuf + first, past_reloc, second); |
| 9924 | tmpbuf[first + second] = '\0'; |
| 9925 | return tmpbuf; |
| 9926 | } |
| 9927 | |
| 9928 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
| 9929 | gotrel[j].str, 1 << (5 + object_64bit)); |
| 9930 | return NULL; |
| 9931 | } |
| 9932 | } |
| 9933 | |
| 9934 | /* Might be a symbol version string. Don't as_bad here. */ |
| 9935 | return NULL; |
| 9936 | } |
| 9937 | #endif |
| 9938 | |
| 9939 | #ifdef TE_PE |
| 9940 | #ifdef lex_got |
| 9941 | #undef lex_got |
| 9942 | #endif |
| 9943 | /* Parse operands of the form |
| 9944 | <symbol>@SECREL32+<nnn> |
| 9945 | |
| 9946 | If we find one, set up the correct relocation in RELOC and copy the |
| 9947 | input string, minus the `@SECREL32' into a malloc'd buffer for |
| 9948 | parsing by the calling routine. Return this buffer, and if ADJUST |
| 9949 | is non-null set it to the length of the string we removed from the |
| 9950 | input line. Otherwise return NULL. |
| 9951 | |
| 9952 | This function is copied from the ELF version above adjusted for PE targets. */ |
| 9953 | |
| 9954 | static char * |
| 9955 | lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, |
| 9956 | int *adjust ATTRIBUTE_UNUSED, |
| 9957 | i386_operand_type *types) |
| 9958 | { |
| 9959 | static const struct |
| 9960 | { |
| 9961 | const char *str; |
| 9962 | int len; |
| 9963 | const enum bfd_reloc_code_real rel[2]; |
| 9964 | const i386_operand_type types64; |
| 9965 | } |
| 9966 | gotrel[] = |
| 9967 | { |
| 9968 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, |
| 9969 | BFD_RELOC_32_SECREL }, |
| 9970 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
| 9971 | }; |
| 9972 | |
| 9973 | char *cp; |
| 9974 | unsigned j; |
| 9975 | |
| 9976 | for (cp = input_line_pointer; *cp != '@'; cp++) |
| 9977 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
| 9978 | return NULL; |
| 9979 | |
| 9980 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
| 9981 | { |
| 9982 | int len = gotrel[j].len; |
| 9983 | |
| 9984 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
| 9985 | { |
| 9986 | if (gotrel[j].rel[object_64bit] != 0) |
| 9987 | { |
| 9988 | int first, second; |
| 9989 | char *tmpbuf, *past_reloc; |
| 9990 | |
| 9991 | *rel = gotrel[j].rel[object_64bit]; |
| 9992 | if (adjust) |
| 9993 | *adjust = len; |
| 9994 | |
| 9995 | if (types) |
| 9996 | { |
| 9997 | if (flag_code != CODE_64BIT) |
| 9998 | { |
| 9999 | types->bitfield.imm32 = 1; |
| 10000 | types->bitfield.disp32 = 1; |
| 10001 | } |
| 10002 | else |
| 10003 | *types = gotrel[j].types64; |
| 10004 | } |
| 10005 | |
| 10006 | /* The length of the first part of our input line. */ |
| 10007 | first = cp - input_line_pointer; |
| 10008 | |
| 10009 | /* The second part goes from after the reloc token until |
| 10010 | (and including) an end_of_line char or comma. */ |
| 10011 | past_reloc = cp + 1 + len; |
| 10012 | cp = past_reloc; |
| 10013 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') |
| 10014 | ++cp; |
| 10015 | second = cp + 1 - past_reloc; |
| 10016 | |
| 10017 | /* Allocate and copy string. The trailing NUL shouldn't |
| 10018 | be necessary, but be safe. */ |
| 10019 | tmpbuf = XNEWVEC (char, first + second + 2); |
| 10020 | memcpy (tmpbuf, input_line_pointer, first); |
| 10021 | if (second != 0 && *past_reloc != ' ') |
| 10022 | /* Replace the relocation token with ' ', so that |
| 10023 | errors like foo@SECLREL321 will be detected. */ |
| 10024 | tmpbuf[first++] = ' '; |
| 10025 | memcpy (tmpbuf + first, past_reloc, second); |
| 10026 | tmpbuf[first + second] = '\0'; |
| 10027 | return tmpbuf; |
| 10028 | } |
| 10029 | |
| 10030 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
| 10031 | gotrel[j].str, 1 << (5 + object_64bit)); |
| 10032 | return NULL; |
| 10033 | } |
| 10034 | } |
| 10035 | |
| 10036 | /* Might be a symbol version string. Don't as_bad here. */ |
| 10037 | return NULL; |
| 10038 | } |
| 10039 | |
| 10040 | #endif /* TE_PE */ |
| 10041 | |
| 10042 | bfd_reloc_code_real_type |
| 10043 | x86_cons (expressionS *exp, int size) |
| 10044 | { |
| 10045 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
| 10046 | |
| 10047 | intel_syntax = -intel_syntax; |
| 10048 | |
| 10049 | exp->X_md = 0; |
| 10050 | if (size == 4 || (object_64bit && size == 8)) |
| 10051 | { |
| 10052 | /* Handle @GOTOFF and the like in an expression. */ |
| 10053 | char *save; |
| 10054 | char *gotfree_input_line; |
| 10055 | int adjust = 0; |
| 10056 | |
| 10057 | save = input_line_pointer; |
| 10058 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
| 10059 | if (gotfree_input_line) |
| 10060 | input_line_pointer = gotfree_input_line; |
| 10061 | |
| 10062 | expression (exp); |
| 10063 | |
| 10064 | if (gotfree_input_line) |
| 10065 | { |
| 10066 | /* expression () has merrily parsed up to the end of line, |
| 10067 | or a comma - in the wrong buffer. Transfer how far |
| 10068 | input_line_pointer has moved to the right buffer. */ |
| 10069 | input_line_pointer = (save |
| 10070 | + (input_line_pointer - gotfree_input_line) |
| 10071 | + adjust); |
| 10072 | free (gotfree_input_line); |
| 10073 | if (exp->X_op == O_constant |
| 10074 | || exp->X_op == O_absent |
| 10075 | || exp->X_op == O_illegal |
| 10076 | || exp->X_op == O_register |
| 10077 | || exp->X_op == O_big) |
| 10078 | { |
| 10079 | char c = *input_line_pointer; |
| 10080 | *input_line_pointer = 0; |
| 10081 | as_bad (_("missing or invalid expression `%s'"), save); |
| 10082 | *input_line_pointer = c; |
| 10083 | } |
| 10084 | else if ((got_reloc == BFD_RELOC_386_PLT32 |
| 10085 | || got_reloc == BFD_RELOC_X86_64_PLT32) |
| 10086 | && exp->X_op != O_symbol) |
| 10087 | { |
| 10088 | char c = *input_line_pointer; |
| 10089 | *input_line_pointer = 0; |
| 10090 | as_bad (_("invalid PLT expression `%s'"), save); |
| 10091 | *input_line_pointer = c; |
| 10092 | } |
| 10093 | } |
| 10094 | } |
| 10095 | else |
| 10096 | expression (exp); |
| 10097 | |
| 10098 | intel_syntax = -intel_syntax; |
| 10099 | |
| 10100 | if (intel_syntax) |
| 10101 | i386_intel_simplify (exp); |
| 10102 | |
| 10103 | return got_reloc; |
| 10104 | } |
| 10105 | |
| 10106 | static void |
| 10107 | signed_cons (int size) |
| 10108 | { |
| 10109 | if (flag_code == CODE_64BIT) |
| 10110 | cons_sign = 1; |
| 10111 | cons (size); |
| 10112 | cons_sign = -1; |
| 10113 | } |
| 10114 | |
| 10115 | #ifdef TE_PE |
| 10116 | static void |
| 10117 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
| 10118 | { |
| 10119 | expressionS exp; |
| 10120 | |
| 10121 | do |
| 10122 | { |
| 10123 | expression (&exp); |
| 10124 | if (exp.X_op == O_symbol) |
| 10125 | exp.X_op = O_secrel; |
| 10126 | |
| 10127 | emit_expr (&exp, 4); |
| 10128 | } |
| 10129 | while (*input_line_pointer++ == ','); |
| 10130 | |
| 10131 | input_line_pointer--; |
| 10132 | demand_empty_rest_of_line (); |
| 10133 | } |
| 10134 | #endif |
| 10135 | |
| 10136 | /* Handle Vector operations. */ |
| 10137 | |
| 10138 | static char * |
| 10139 | check_VecOperations (char *op_string, char *op_end) |
| 10140 | { |
| 10141 | const reg_entry *mask; |
| 10142 | const char *saved; |
| 10143 | char *end_op; |
| 10144 | |
| 10145 | while (*op_string |
| 10146 | && (op_end == NULL || op_string < op_end)) |
| 10147 | { |
| 10148 | saved = op_string; |
| 10149 | if (*op_string == '{') |
| 10150 | { |
| 10151 | op_string++; |
| 10152 | |
| 10153 | /* Check broadcasts. */ |
| 10154 | if (strncmp (op_string, "1to", 3) == 0) |
| 10155 | { |
| 10156 | int bcst_type; |
| 10157 | |
| 10158 | if (i.broadcast) |
| 10159 | goto duplicated_vec_op; |
| 10160 | |
| 10161 | op_string += 3; |
| 10162 | if (*op_string == '8') |
| 10163 | bcst_type = 8; |
| 10164 | else if (*op_string == '4') |
| 10165 | bcst_type = 4; |
| 10166 | else if (*op_string == '2') |
| 10167 | bcst_type = 2; |
| 10168 | else if (*op_string == '1' |
| 10169 | && *(op_string+1) == '6') |
| 10170 | { |
| 10171 | bcst_type = 16; |
| 10172 | op_string++; |
| 10173 | } |
| 10174 | else |
| 10175 | { |
| 10176 | as_bad (_("Unsupported broadcast: `%s'"), saved); |
| 10177 | return NULL; |
| 10178 | } |
| 10179 | op_string++; |
| 10180 | |
| 10181 | broadcast_op.type = bcst_type; |
| 10182 | broadcast_op.operand = this_operand; |
| 10183 | broadcast_op.bytes = 0; |
| 10184 | i.broadcast = &broadcast_op; |
| 10185 | } |
| 10186 | /* Check masking operation. */ |
| 10187 | else if ((mask = parse_register (op_string, &end_op)) != NULL) |
| 10188 | { |
| 10189 | /* k0 can't be used for write mask. */ |
| 10190 | if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num) |
| 10191 | { |
| 10192 | as_bad (_("`%s%s' can't be used for write mask"), |
| 10193 | register_prefix, mask->reg_name); |
| 10194 | return NULL; |
| 10195 | } |
| 10196 | |
| 10197 | if (!i.mask) |
| 10198 | { |
| 10199 | mask_op.mask = mask; |
| 10200 | mask_op.zeroing = 0; |
| 10201 | mask_op.operand = this_operand; |
| 10202 | i.mask = &mask_op; |
| 10203 | } |
| 10204 | else |
| 10205 | { |
| 10206 | if (i.mask->mask) |
| 10207 | goto duplicated_vec_op; |
| 10208 | |
| 10209 | i.mask->mask = mask; |
| 10210 | |
| 10211 | /* Only "{z}" is allowed here. No need to check |
| 10212 | zeroing mask explicitly. */ |
| 10213 | if (i.mask->operand != this_operand) |
| 10214 | { |
| 10215 | as_bad (_("invalid write mask `%s'"), saved); |
| 10216 | return NULL; |
| 10217 | } |
| 10218 | } |
| 10219 | |
| 10220 | op_string = end_op; |
| 10221 | } |
| 10222 | /* Check zeroing-flag for masking operation. */ |
| 10223 | else if (*op_string == 'z') |
| 10224 | { |
| 10225 | if (!i.mask) |
| 10226 | { |
| 10227 | mask_op.mask = NULL; |
| 10228 | mask_op.zeroing = 1; |
| 10229 | mask_op.operand = this_operand; |
| 10230 | i.mask = &mask_op; |
| 10231 | } |
| 10232 | else |
| 10233 | { |
| 10234 | if (i.mask->zeroing) |
| 10235 | { |
| 10236 | duplicated_vec_op: |
| 10237 | as_bad (_("duplicated `%s'"), saved); |
| 10238 | return NULL; |
| 10239 | } |
| 10240 | |
| 10241 | i.mask->zeroing = 1; |
| 10242 | |
| 10243 | /* Only "{%k}" is allowed here. No need to check mask |
| 10244 | register explicitly. */ |
| 10245 | if (i.mask->operand != this_operand) |
| 10246 | { |
| 10247 | as_bad (_("invalid zeroing-masking `%s'"), |
| 10248 | saved); |
| 10249 | return NULL; |
| 10250 | } |
| 10251 | } |
| 10252 | |
| 10253 | op_string++; |
| 10254 | } |
| 10255 | else |
| 10256 | goto unknown_vec_op; |
| 10257 | |
| 10258 | if (*op_string != '}') |
| 10259 | { |
| 10260 | as_bad (_("missing `}' in `%s'"), saved); |
| 10261 | return NULL; |
| 10262 | } |
| 10263 | op_string++; |
| 10264 | |
| 10265 | /* Strip whitespace since the addition of pseudo prefixes |
| 10266 | changed how the scrubber treats '{'. */ |
| 10267 | if (is_space_char (*op_string)) |
| 10268 | ++op_string; |
| 10269 | |
| 10270 | continue; |
| 10271 | } |
| 10272 | unknown_vec_op: |
| 10273 | /* We don't know this one. */ |
| 10274 | as_bad (_("unknown vector operation: `%s'"), saved); |
| 10275 | return NULL; |
| 10276 | } |
| 10277 | |
| 10278 | if (i.mask && i.mask->zeroing && !i.mask->mask) |
| 10279 | { |
| 10280 | as_bad (_("zeroing-masking only allowed with write mask")); |
| 10281 | return NULL; |
| 10282 | } |
| 10283 | |
| 10284 | return op_string; |
| 10285 | } |
| 10286 | |
| 10287 | static int |
| 10288 | i386_immediate (char *imm_start) |
| 10289 | { |
| 10290 | char *save_input_line_pointer; |
| 10291 | char *gotfree_input_line; |
| 10292 | segT exp_seg = 0; |
| 10293 | expressionS *exp; |
| 10294 | i386_operand_type types; |
| 10295 | |
| 10296 | operand_type_set (&types, ~0); |
| 10297 | |
| 10298 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) |
| 10299 | { |
| 10300 | as_bad (_("at most %d immediate operands are allowed"), |
| 10301 | MAX_IMMEDIATE_OPERANDS); |
| 10302 | return 0; |
| 10303 | } |
| 10304 | |
| 10305 | exp = &im_expressions[i.imm_operands++]; |
| 10306 | i.op[this_operand].imms = exp; |
| 10307 | |
| 10308 | if (is_space_char (*imm_start)) |
| 10309 | ++imm_start; |
| 10310 | |
| 10311 | save_input_line_pointer = input_line_pointer; |
| 10312 | input_line_pointer = imm_start; |
| 10313 | |
| 10314 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
| 10315 | if (gotfree_input_line) |
| 10316 | input_line_pointer = gotfree_input_line; |
| 10317 | |
| 10318 | exp_seg = expression (exp); |
| 10319 | |
| 10320 | SKIP_WHITESPACE (); |
| 10321 | |
| 10322 | /* Handle vector operations. */ |
| 10323 | if (*input_line_pointer == '{') |
| 10324 | { |
| 10325 | input_line_pointer = check_VecOperations (input_line_pointer, |
| 10326 | NULL); |
| 10327 | if (input_line_pointer == NULL) |
| 10328 | return 0; |
| 10329 | } |
| 10330 | |
| 10331 | if (*input_line_pointer) |
| 10332 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
| 10333 | |
| 10334 | input_line_pointer = save_input_line_pointer; |
| 10335 | if (gotfree_input_line) |
| 10336 | { |
| 10337 | free (gotfree_input_line); |
| 10338 | |
| 10339 | if (exp->X_op == O_constant || exp->X_op == O_register) |
| 10340 | exp->X_op = O_illegal; |
| 10341 | } |
| 10342 | |
| 10343 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); |
| 10344 | } |
| 10345 | |
| 10346 | static int |
| 10347 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, |
| 10348 | i386_operand_type types, const char *imm_start) |
| 10349 | { |
| 10350 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) |
| 10351 | { |
| 10352 | if (imm_start) |
| 10353 | as_bad (_("missing or invalid immediate expression `%s'"), |
| 10354 | imm_start); |
| 10355 | return 0; |
| 10356 | } |
| 10357 | else if (exp->X_op == O_constant) |
| 10358 | { |
| 10359 | /* Size it properly later. */ |
| 10360 | i.types[this_operand].bitfield.imm64 = 1; |
| 10361 | /* If not 64bit, sign extend val. */ |
| 10362 | if (flag_code != CODE_64BIT |
| 10363 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
| 10364 | exp->X_add_number |
| 10365 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); |
| 10366 | } |
| 10367 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
| 10368 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
| 10369 | && exp_seg != absolute_section |
| 10370 | && exp_seg != text_section |
| 10371 | && exp_seg != data_section |
| 10372 | && exp_seg != bss_section |
| 10373 | && exp_seg != undefined_section |
| 10374 | && !bfd_is_com_section (exp_seg)) |
| 10375 | { |
| 10376 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
| 10377 | return 0; |
| 10378 | } |
| 10379 | #endif |
| 10380 | else if (!intel_syntax && exp_seg == reg_section) |
| 10381 | { |
| 10382 | if (imm_start) |
| 10383 | as_bad (_("illegal immediate register operand %s"), imm_start); |
| 10384 | return 0; |
| 10385 | } |
| 10386 | else |
| 10387 | { |
| 10388 | /* This is an address. The size of the address will be |
| 10389 | determined later, depending on destination register, |
| 10390 | suffix, or the default for the section. */ |
| 10391 | i.types[this_operand].bitfield.imm8 = 1; |
| 10392 | i.types[this_operand].bitfield.imm16 = 1; |
| 10393 | i.types[this_operand].bitfield.imm32 = 1; |
| 10394 | i.types[this_operand].bitfield.imm32s = 1; |
| 10395 | i.types[this_operand].bitfield.imm64 = 1; |
| 10396 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
| 10397 | types); |
| 10398 | } |
| 10399 | |
| 10400 | return 1; |
| 10401 | } |
| 10402 | |
| 10403 | static char * |
| 10404 | i386_scale (char *scale) |
| 10405 | { |
| 10406 | offsetT val; |
| 10407 | char *save = input_line_pointer; |
| 10408 | |
| 10409 | input_line_pointer = scale; |
| 10410 | val = get_absolute_expression (); |
| 10411 | |
| 10412 | switch (val) |
| 10413 | { |
| 10414 | case 1: |
| 10415 | i.log2_scale_factor = 0; |
| 10416 | break; |
| 10417 | case 2: |
| 10418 | i.log2_scale_factor = 1; |
| 10419 | break; |
| 10420 | case 4: |
| 10421 | i.log2_scale_factor = 2; |
| 10422 | break; |
| 10423 | case 8: |
| 10424 | i.log2_scale_factor = 3; |
| 10425 | break; |
| 10426 | default: |
| 10427 | { |
| 10428 | char sep = *input_line_pointer; |
| 10429 | |
| 10430 | *input_line_pointer = '\0'; |
| 10431 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), |
| 10432 | scale); |
| 10433 | *input_line_pointer = sep; |
| 10434 | input_line_pointer = save; |
| 10435 | return NULL; |
| 10436 | } |
| 10437 | } |
| 10438 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
| 10439 | { |
| 10440 | as_warn (_("scale factor of %d without an index register"), |
| 10441 | 1 << i.log2_scale_factor); |
| 10442 | i.log2_scale_factor = 0; |
| 10443 | } |
| 10444 | scale = input_line_pointer; |
| 10445 | input_line_pointer = save; |
| 10446 | return scale; |
| 10447 | } |
| 10448 | |
| 10449 | static int |
| 10450 | i386_displacement (char *disp_start, char *disp_end) |
| 10451 | { |
| 10452 | expressionS *exp; |
| 10453 | segT exp_seg = 0; |
| 10454 | char *save_input_line_pointer; |
| 10455 | char *gotfree_input_line; |
| 10456 | int override; |
| 10457 | i386_operand_type bigdisp, types = anydisp; |
| 10458 | int ret; |
| 10459 | |
| 10460 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
| 10461 | { |
| 10462 | as_bad (_("at most %d displacement operands are allowed"), |
| 10463 | MAX_MEMORY_OPERANDS); |
| 10464 | return 0; |
| 10465 | } |
| 10466 | |
| 10467 | operand_type_set (&bigdisp, 0); |
| 10468 | if (i.jumpabsolute |
| 10469 | || i.types[this_operand].bitfield.baseindex |
| 10470 | || (current_templates->start->opcode_modifier.jump != JUMP |
| 10471 | && current_templates->start->opcode_modifier.jump != JUMP_DWORD)) |
| 10472 | { |
| 10473 | i386_addressing_mode (); |
| 10474 | override = (i.prefix[ADDR_PREFIX] != 0); |
| 10475 | if (flag_code == CODE_64BIT) |
| 10476 | { |
| 10477 | if (!override) |
| 10478 | { |
| 10479 | bigdisp.bitfield.disp32s = 1; |
| 10480 | bigdisp.bitfield.disp64 = 1; |
| 10481 | } |
| 10482 | else |
| 10483 | bigdisp.bitfield.disp32 = 1; |
| 10484 | } |
| 10485 | else if ((flag_code == CODE_16BIT) ^ override) |
| 10486 | bigdisp.bitfield.disp16 = 1; |
| 10487 | else |
| 10488 | bigdisp.bitfield.disp32 = 1; |
| 10489 | } |
| 10490 | else |
| 10491 | { |
| 10492 | /* For PC-relative branches, the width of the displacement may be |
| 10493 | dependent upon data size, but is never dependent upon address size. |
| 10494 | Also make sure to not unintentionally match against a non-PC-relative |
| 10495 | branch template. */ |
| 10496 | static templates aux_templates; |
| 10497 | const insn_template *t = current_templates->start; |
| 10498 | bfd_boolean has_intel64 = FALSE; |
| 10499 | |
| 10500 | aux_templates.start = t; |
| 10501 | while (++t < current_templates->end) |
| 10502 | { |
| 10503 | if (t->opcode_modifier.jump |
| 10504 | != current_templates->start->opcode_modifier.jump) |
| 10505 | break; |
| 10506 | if ((t->opcode_modifier.isa64 >= INTEL64)) |
| 10507 | has_intel64 = TRUE; |
| 10508 | } |
| 10509 | if (t < current_templates->end) |
| 10510 | { |
| 10511 | aux_templates.end = t; |
| 10512 | current_templates = &aux_templates; |
| 10513 | } |
| 10514 | |
| 10515 | override = (i.prefix[DATA_PREFIX] != 0); |
| 10516 | if (flag_code == CODE_64BIT) |
| 10517 | { |
| 10518 | if ((override || i.suffix == WORD_MNEM_SUFFIX) |
| 10519 | && (!intel64 || !has_intel64)) |
| 10520 | bigdisp.bitfield.disp16 = 1; |
| 10521 | else |
| 10522 | bigdisp.bitfield.disp32s = 1; |
| 10523 | } |
| 10524 | else |
| 10525 | { |
| 10526 | if (!override) |
| 10527 | override = (i.suffix == (flag_code != CODE_16BIT |
| 10528 | ? WORD_MNEM_SUFFIX |
| 10529 | : LONG_MNEM_SUFFIX)); |
| 10530 | bigdisp.bitfield.disp32 = 1; |
| 10531 | if ((flag_code == CODE_16BIT) ^ override) |
| 10532 | { |
| 10533 | bigdisp.bitfield.disp32 = 0; |
| 10534 | bigdisp.bitfield.disp16 = 1; |
| 10535 | } |
| 10536 | } |
| 10537 | } |
| 10538 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
| 10539 | bigdisp); |
| 10540 | |
| 10541 | exp = &disp_expressions[i.disp_operands]; |
| 10542 | i.op[this_operand].disps = exp; |
| 10543 | i.disp_operands++; |
| 10544 | save_input_line_pointer = input_line_pointer; |
| 10545 | input_line_pointer = disp_start; |
| 10546 | END_STRING_AND_SAVE (disp_end); |
| 10547 | |
| 10548 | #ifndef GCC_ASM_O_HACK |
| 10549 | #define GCC_ASM_O_HACK 0 |
| 10550 | #endif |
| 10551 | #if GCC_ASM_O_HACK |
| 10552 | END_STRING_AND_SAVE (disp_end + 1); |
| 10553 | if (i.types[this_operand].bitfield.baseIndex |
| 10554 | && displacement_string_end[-1] == '+') |
| 10555 | { |
| 10556 | /* This hack is to avoid a warning when using the "o" |
| 10557 | constraint within gcc asm statements. |
| 10558 | For instance: |
| 10559 | |
| 10560 | #define _set_tssldt_desc(n,addr,limit,type) \ |
| 10561 | __asm__ __volatile__ ( \ |
| 10562 | "movw %w2,%0\n\t" \ |
| 10563 | "movw %w1,2+%0\n\t" \ |
| 10564 | "rorl $16,%1\n\t" \ |
| 10565 | "movb %b1,4+%0\n\t" \ |
| 10566 | "movb %4,5+%0\n\t" \ |
| 10567 | "movb $0,6+%0\n\t" \ |
| 10568 | "movb %h1,7+%0\n\t" \ |
| 10569 | "rorl $16,%1" \ |
| 10570 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) |
| 10571 | |
| 10572 | This works great except that the output assembler ends |
| 10573 | up looking a bit weird if it turns out that there is |
| 10574 | no offset. You end up producing code that looks like: |
| 10575 | |
| 10576 | #APP |
| 10577 | movw $235,(%eax) |
| 10578 | movw %dx,2+(%eax) |
| 10579 | rorl $16,%edx |
| 10580 | movb %dl,4+(%eax) |
| 10581 | movb $137,5+(%eax) |
| 10582 | movb $0,6+(%eax) |
| 10583 | movb %dh,7+(%eax) |
| 10584 | rorl $16,%edx |
| 10585 | #NO_APP |
| 10586 | |
| 10587 | So here we provide the missing zero. */ |
| 10588 | |
| 10589 | *displacement_string_end = '0'; |
| 10590 | } |
| 10591 | #endif |
| 10592 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
| 10593 | if (gotfree_input_line) |
| 10594 | input_line_pointer = gotfree_input_line; |
| 10595 | |
| 10596 | exp_seg = expression (exp); |
| 10597 | |
| 10598 | SKIP_WHITESPACE (); |
| 10599 | if (*input_line_pointer) |
| 10600 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
| 10601 | #if GCC_ASM_O_HACK |
| 10602 | RESTORE_END_STRING (disp_end + 1); |
| 10603 | #endif |
| 10604 | input_line_pointer = save_input_line_pointer; |
| 10605 | if (gotfree_input_line) |
| 10606 | { |
| 10607 | free (gotfree_input_line); |
| 10608 | |
| 10609 | if (exp->X_op == O_constant || exp->X_op == O_register) |
| 10610 | exp->X_op = O_illegal; |
| 10611 | } |
| 10612 | |
| 10613 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); |
| 10614 | |
| 10615 | RESTORE_END_STRING (disp_end); |
| 10616 | |
| 10617 | return ret; |
| 10618 | } |
| 10619 | |
| 10620 | static int |
| 10621 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, |
| 10622 | i386_operand_type types, const char *disp_start) |
| 10623 | { |
| 10624 | i386_operand_type bigdisp; |
| 10625 | int ret = 1; |
| 10626 | |
| 10627 | /* We do this to make sure that the section symbol is in |
| 10628 | the symbol table. We will ultimately change the relocation |
| 10629 | to be relative to the beginning of the section. */ |
| 10630 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
| 10631 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
| 10632 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
| 10633 | { |
| 10634 | if (exp->X_op != O_symbol) |
| 10635 | goto inv_disp; |
| 10636 | |
| 10637 | if (S_IS_LOCAL (exp->X_add_symbol) |
| 10638 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
| 10639 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) |
| 10640 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
| 10641 | exp->X_op = O_subtract; |
| 10642 | exp->X_op_symbol = GOT_symbol; |
| 10643 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
| 10644 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
| 10645 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
| 10646 | i.reloc[this_operand] = BFD_RELOC_64; |
| 10647 | else |
| 10648 | i.reloc[this_operand] = BFD_RELOC_32; |
| 10649 | } |
| 10650 | |
| 10651 | else if (exp->X_op == O_absent |
| 10652 | || exp->X_op == O_illegal |
| 10653 | || exp->X_op == O_big) |
| 10654 | { |
| 10655 | inv_disp: |
| 10656 | as_bad (_("missing or invalid displacement expression `%s'"), |
| 10657 | disp_start); |
| 10658 | ret = 0; |
| 10659 | } |
| 10660 | |
| 10661 | else if (flag_code == CODE_64BIT |
| 10662 | && !i.prefix[ADDR_PREFIX] |
| 10663 | && exp->X_op == O_constant) |
| 10664 | { |
| 10665 | /* Since displacement is signed extended to 64bit, don't allow |
| 10666 | disp32 and turn off disp32s if they are out of range. */ |
| 10667 | i.types[this_operand].bitfield.disp32 = 0; |
| 10668 | if (!fits_in_signed_long (exp->X_add_number)) |
| 10669 | { |
| 10670 | i.types[this_operand].bitfield.disp32s = 0; |
| 10671 | if (i.types[this_operand].bitfield.baseindex) |
| 10672 | { |
| 10673 | as_bad (_("0x%lx out range of signed 32bit displacement"), |
| 10674 | (long) exp->X_add_number); |
| 10675 | ret = 0; |
| 10676 | } |
| 10677 | } |
| 10678 | } |
| 10679 | |
| 10680 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
| 10681 | else if (exp->X_op != O_constant |
| 10682 | && OUTPUT_FLAVOR == bfd_target_aout_flavour |
| 10683 | && exp_seg != absolute_section |
| 10684 | && exp_seg != text_section |
| 10685 | && exp_seg != data_section |
| 10686 | && exp_seg != bss_section |
| 10687 | && exp_seg != undefined_section |
| 10688 | && !bfd_is_com_section (exp_seg)) |
| 10689 | { |
| 10690 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
| 10691 | ret = 0; |
| 10692 | } |
| 10693 | #endif |
| 10694 | |
| 10695 | if (current_templates->start->opcode_modifier.jump == JUMP_BYTE |
| 10696 | /* Constants get taken care of by optimize_disp(). */ |
| 10697 | && exp->X_op != O_constant) |
| 10698 | i.types[this_operand].bitfield.disp8 = 1; |
| 10699 | |
| 10700 | /* Check if this is a displacement only operand. */ |
| 10701 | bigdisp = i.types[this_operand]; |
| 10702 | bigdisp.bitfield.disp8 = 0; |
| 10703 | bigdisp.bitfield.disp16 = 0; |
| 10704 | bigdisp.bitfield.disp32 = 0; |
| 10705 | bigdisp.bitfield.disp32s = 0; |
| 10706 | bigdisp.bitfield.disp64 = 0; |
| 10707 | if (operand_type_all_zero (&bigdisp)) |
| 10708 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
| 10709 | types); |
| 10710 | |
| 10711 | return ret; |
| 10712 | } |
| 10713 | |
| 10714 | /* Return the active addressing mode, taking address override and |
| 10715 | registers forming the address into consideration. Update the |
| 10716 | address override prefix if necessary. */ |
| 10717 | |
| 10718 | static enum flag_code |
| 10719 | i386_addressing_mode (void) |
| 10720 | { |
| 10721 | enum flag_code addr_mode; |
| 10722 | |
| 10723 | if (i.prefix[ADDR_PREFIX]) |
| 10724 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; |
| 10725 | else if (flag_code == CODE_16BIT |
| 10726 | && current_templates->start->cpu_flags.bitfield.cpumpx |
| 10727 | /* Avoid replacing the "16-bit addressing not allowed" diagnostic |
| 10728 | from md_assemble() by "is not a valid base/index expression" |
| 10729 | when there is a base and/or index. */ |
| 10730 | && !i.types[this_operand].bitfield.baseindex) |
| 10731 | { |
| 10732 | /* MPX insn memory operands with neither base nor index must be forced |
| 10733 | to use 32-bit addressing in 16-bit mode. */ |
| 10734 | addr_mode = CODE_32BIT; |
| 10735 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; |
| 10736 | ++i.prefixes; |
| 10737 | gas_assert (!i.types[this_operand].bitfield.disp16); |
| 10738 | gas_assert (!i.types[this_operand].bitfield.disp32); |
| 10739 | } |
| 10740 | else |
| 10741 | { |
| 10742 | addr_mode = flag_code; |
| 10743 | |
| 10744 | #if INFER_ADDR_PREFIX |
| 10745 | if (i.mem_operands == 0) |
| 10746 | { |
| 10747 | /* Infer address prefix from the first memory operand. */ |
| 10748 | const reg_entry *addr_reg = i.base_reg; |
| 10749 | |
| 10750 | if (addr_reg == NULL) |
| 10751 | addr_reg = i.index_reg; |
| 10752 | |
| 10753 | if (addr_reg) |
| 10754 | { |
| 10755 | if (addr_reg->reg_type.bitfield.dword) |
| 10756 | addr_mode = CODE_32BIT; |
| 10757 | else if (flag_code != CODE_64BIT |
| 10758 | && addr_reg->reg_type.bitfield.word) |
| 10759 | addr_mode = CODE_16BIT; |
| 10760 | |
| 10761 | if (addr_mode != flag_code) |
| 10762 | { |
| 10763 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; |
| 10764 | i.prefixes += 1; |
| 10765 | /* Change the size of any displacement too. At most one |
| 10766 | of Disp16 or Disp32 is set. |
| 10767 | FIXME. There doesn't seem to be any real need for |
| 10768 | separate Disp16 and Disp32 flags. The same goes for |
| 10769 | Imm16 and Imm32. Removing them would probably clean |
| 10770 | up the code quite a lot. */ |
| 10771 | if (flag_code != CODE_64BIT |
| 10772 | && (i.types[this_operand].bitfield.disp16 |
| 10773 | || i.types[this_operand].bitfield.disp32)) |
| 10774 | i.types[this_operand] |
| 10775 | = operand_type_xor (i.types[this_operand], disp16_32); |
| 10776 | } |
| 10777 | } |
| 10778 | } |
| 10779 | #endif |
| 10780 | } |
| 10781 | |
| 10782 | return addr_mode; |
| 10783 | } |
| 10784 | |
| 10785 | /* Make sure the memory operand we've been dealt is valid. |
| 10786 | Return 1 on success, 0 on a failure. */ |
| 10787 | |
| 10788 | static int |
| 10789 | i386_index_check (const char *operand_string) |
| 10790 | { |
| 10791 | const char *kind = "base/index"; |
| 10792 | enum flag_code addr_mode = i386_addressing_mode (); |
| 10793 | |
| 10794 | if (current_templates->start->opcode_modifier.isstring |
| 10795 | && !current_templates->start->cpu_flags.bitfield.cpupadlock |
| 10796 | && (current_templates->end[-1].opcode_modifier.isstring |
| 10797 | || i.mem_operands)) |
| 10798 | { |
| 10799 | /* Memory operands of string insns are special in that they only allow |
| 10800 | a single register (rDI, rSI, or rBX) as their memory address. */ |
| 10801 | const reg_entry *expected_reg; |
| 10802 | static const char *di_si[][2] = |
| 10803 | { |
| 10804 | { "esi", "edi" }, |
| 10805 | { "si", "di" }, |
| 10806 | { "rsi", "rdi" } |
| 10807 | }; |
| 10808 | static const char *bx[] = { "ebx", "bx", "rbx" }; |
| 10809 | |
| 10810 | kind = "string address"; |
| 10811 | |
| 10812 | if (current_templates->start->opcode_modifier.repprefixok) |
| 10813 | { |
| 10814 | int es_op = current_templates->end[-1].opcode_modifier.isstring |
| 10815 | - IS_STRING_ES_OP0; |
| 10816 | int op = 0; |
| 10817 | |
| 10818 | if (!current_templates->end[-1].operand_types[0].bitfield.baseindex |
| 10819 | || ((!i.mem_operands != !intel_syntax) |
| 10820 | && current_templates->end[-1].operand_types[1] |
| 10821 | .bitfield.baseindex)) |
| 10822 | op = 1; |
| 10823 | expected_reg = hash_find (reg_hash, di_si[addr_mode][op == es_op]); |
| 10824 | } |
| 10825 | else |
| 10826 | expected_reg = hash_find (reg_hash, bx[addr_mode]); |
| 10827 | |
| 10828 | if (i.base_reg != expected_reg |
| 10829 | || i.index_reg |
| 10830 | || operand_type_check (i.types[this_operand], disp)) |
| 10831 | { |
| 10832 | /* The second memory operand must have the same size as |
| 10833 | the first one. */ |
| 10834 | if (i.mem_operands |
| 10835 | && i.base_reg |
| 10836 | && !((addr_mode == CODE_64BIT |
| 10837 | && i.base_reg->reg_type.bitfield.qword) |
| 10838 | || (addr_mode == CODE_32BIT |
| 10839 | ? i.base_reg->reg_type.bitfield.dword |
| 10840 | : i.base_reg->reg_type.bitfield.word))) |
| 10841 | goto bad_address; |
| 10842 | |
| 10843 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
| 10844 | operand_string, |
| 10845 | intel_syntax ? '[' : '(', |
| 10846 | register_prefix, |
| 10847 | expected_reg->reg_name, |
| 10848 | intel_syntax ? ']' : ')'); |
| 10849 | return 1; |
| 10850 | } |
| 10851 | else |
| 10852 | return 1; |
| 10853 | |
| 10854 | bad_address: |
| 10855 | as_bad (_("`%s' is not a valid %s expression"), |
| 10856 | operand_string, kind); |
| 10857 | return 0; |
| 10858 | } |
| 10859 | else |
| 10860 | { |
| 10861 | if (addr_mode != CODE_16BIT) |
| 10862 | { |
| 10863 | /* 32-bit/64-bit checks. */ |
| 10864 | if ((i.base_reg |
| 10865 | && ((addr_mode == CODE_64BIT |
| 10866 | ? !i.base_reg->reg_type.bitfield.qword |
| 10867 | : !i.base_reg->reg_type.bitfield.dword) |
| 10868 | || (i.index_reg && i.base_reg->reg_num == RegIP) |
| 10869 | || i.base_reg->reg_num == RegIZ)) |
| 10870 | || (i.index_reg |
| 10871 | && !i.index_reg->reg_type.bitfield.xmmword |
| 10872 | && !i.index_reg->reg_type.bitfield.ymmword |
| 10873 | && !i.index_reg->reg_type.bitfield.zmmword |
| 10874 | && ((addr_mode == CODE_64BIT |
| 10875 | ? !i.index_reg->reg_type.bitfield.qword |
| 10876 | : !i.index_reg->reg_type.bitfield.dword) |
| 10877 | || !i.index_reg->reg_type.bitfield.baseindex))) |
| 10878 | goto bad_address; |
| 10879 | |
| 10880 | /* bndmk, bndldx, and bndstx have special restrictions. */ |
| 10881 | if (current_templates->start->base_opcode == 0xf30f1b |
| 10882 | || (current_templates->start->base_opcode & ~1) == 0x0f1a) |
| 10883 | { |
| 10884 | /* They cannot use RIP-relative addressing. */ |
| 10885 | if (i.base_reg && i.base_reg->reg_num == RegIP) |
| 10886 | { |
| 10887 | as_bad (_("`%s' cannot be used here"), operand_string); |
| 10888 | return 0; |
| 10889 | } |
| 10890 | |
| 10891 | /* bndldx and bndstx ignore their scale factor. */ |
| 10892 | if (current_templates->start->base_opcode != 0xf30f1b |
| 10893 | && i.log2_scale_factor) |
| 10894 | as_warn (_("register scaling is being ignored here")); |
| 10895 | } |
| 10896 | } |
| 10897 | else |
| 10898 | { |
| 10899 | /* 16-bit checks. */ |
| 10900 | if ((i.base_reg |
| 10901 | && (!i.base_reg->reg_type.bitfield.word |
| 10902 | || !i.base_reg->reg_type.bitfield.baseindex)) |
| 10903 | || (i.index_reg |
| 10904 | && (!i.index_reg->reg_type.bitfield.word |
| 10905 | || !i.index_reg->reg_type.bitfield.baseindex |
| 10906 | || !(i.base_reg |
| 10907 | && i.base_reg->reg_num < 6 |
| 10908 | && i.index_reg->reg_num >= 6 |
| 10909 | && i.log2_scale_factor == 0)))) |
| 10910 | goto bad_address; |
| 10911 | } |
| 10912 | } |
| 10913 | return 1; |
| 10914 | } |
| 10915 | |
| 10916 | /* Handle vector immediates. */ |
| 10917 | |
| 10918 | static int |
| 10919 | RC_SAE_immediate (const char *imm_start) |
| 10920 | { |
| 10921 | unsigned int match_found, j; |
| 10922 | const char *pstr = imm_start; |
| 10923 | expressionS *exp; |
| 10924 | |
| 10925 | if (*pstr != '{') |
| 10926 | return 0; |
| 10927 | |
| 10928 | pstr++; |
| 10929 | match_found = 0; |
| 10930 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) |
| 10931 | { |
| 10932 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) |
| 10933 | { |
| 10934 | if (!i.rounding) |
| 10935 | { |
| 10936 | rc_op.type = RC_NamesTable[j].type; |
| 10937 | rc_op.operand = this_operand; |
| 10938 | i.rounding = &rc_op; |
| 10939 | } |
| 10940 | else |
| 10941 | { |
| 10942 | as_bad (_("duplicated `%s'"), imm_start); |
| 10943 | return 0; |
| 10944 | } |
| 10945 | pstr += RC_NamesTable[j].len; |
| 10946 | match_found = 1; |
| 10947 | break; |
| 10948 | } |
| 10949 | } |
| 10950 | if (!match_found) |
| 10951 | return 0; |
| 10952 | |
| 10953 | if (*pstr++ != '}') |
| 10954 | { |
| 10955 | as_bad (_("Missing '}': '%s'"), imm_start); |
| 10956 | return 0; |
| 10957 | } |
| 10958 | /* RC/SAE immediate string should contain nothing more. */; |
| 10959 | if (*pstr != 0) |
| 10960 | { |
| 10961 | as_bad (_("Junk after '}': '%s'"), imm_start); |
| 10962 | return 0; |
| 10963 | } |
| 10964 | |
| 10965 | exp = &im_expressions[i.imm_operands++]; |
| 10966 | i.op[this_operand].imms = exp; |
| 10967 | |
| 10968 | exp->X_op = O_constant; |
| 10969 | exp->X_add_number = 0; |
| 10970 | exp->X_add_symbol = (symbolS *) 0; |
| 10971 | exp->X_op_symbol = (symbolS *) 0; |
| 10972 | |
| 10973 | i.types[this_operand].bitfield.imm8 = 1; |
| 10974 | return 1; |
| 10975 | } |
| 10976 | |
| 10977 | /* Only string instructions can have a second memory operand, so |
| 10978 | reduce current_templates to just those if it contains any. */ |
| 10979 | static int |
| 10980 | maybe_adjust_templates (void) |
| 10981 | { |
| 10982 | const insn_template *t; |
| 10983 | |
| 10984 | gas_assert (i.mem_operands == 1); |
| 10985 | |
| 10986 | for (t = current_templates->start; t < current_templates->end; ++t) |
| 10987 | if (t->opcode_modifier.isstring) |
| 10988 | break; |
| 10989 | |
| 10990 | if (t < current_templates->end) |
| 10991 | { |
| 10992 | static templates aux_templates; |
| 10993 | bfd_boolean recheck; |
| 10994 | |
| 10995 | aux_templates.start = t; |
| 10996 | for (; t < current_templates->end; ++t) |
| 10997 | if (!t->opcode_modifier.isstring) |
| 10998 | break; |
| 10999 | aux_templates.end = t; |
| 11000 | |
| 11001 | /* Determine whether to re-check the first memory operand. */ |
| 11002 | recheck = (aux_templates.start != current_templates->start |
| 11003 | || t != current_templates->end); |
| 11004 | |
| 11005 | current_templates = &aux_templates; |
| 11006 | |
| 11007 | if (recheck) |
| 11008 | { |
| 11009 | i.mem_operands = 0; |
| 11010 | if (i.memop1_string != NULL |
| 11011 | && i386_index_check (i.memop1_string) == 0) |
| 11012 | return 0; |
| 11013 | i.mem_operands = 1; |
| 11014 | } |
| 11015 | } |
| 11016 | |
| 11017 | return 1; |
| 11018 | } |
| 11019 | |
| 11020 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
| 11021 | on error. */ |
| 11022 | |
| 11023 | static int |
| 11024 | i386_att_operand (char *operand_string) |
| 11025 | { |
| 11026 | const reg_entry *r; |
| 11027 | char *end_op; |
| 11028 | char *op_string = operand_string; |
| 11029 | |
| 11030 | if (is_space_char (*op_string)) |
| 11031 | ++op_string; |
| 11032 | |
| 11033 | /* We check for an absolute prefix (differentiating, |
| 11034 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
| 11035 | if (*op_string == ABSOLUTE_PREFIX) |
| 11036 | { |
| 11037 | ++op_string; |
| 11038 | if (is_space_char (*op_string)) |
| 11039 | ++op_string; |
| 11040 | i.jumpabsolute = TRUE; |
| 11041 | } |
| 11042 | |
| 11043 | /* Check if operand is a register. */ |
| 11044 | if ((r = parse_register (op_string, &end_op)) != NULL) |
| 11045 | { |
| 11046 | i386_operand_type temp; |
| 11047 | |
| 11048 | /* Check for a segment override by searching for ':' after a |
| 11049 | segment register. */ |
| 11050 | op_string = end_op; |
| 11051 | if (is_space_char (*op_string)) |
| 11052 | ++op_string; |
| 11053 | if (*op_string == ':' && r->reg_type.bitfield.class == SReg) |
| 11054 | { |
| 11055 | switch (r->reg_num) |
| 11056 | { |
| 11057 | case 0: |
| 11058 | i.seg[i.mem_operands] = &es; |
| 11059 | break; |
| 11060 | case 1: |
| 11061 | i.seg[i.mem_operands] = &cs; |
| 11062 | break; |
| 11063 | case 2: |
| 11064 | i.seg[i.mem_operands] = &ss; |
| 11065 | break; |
| 11066 | case 3: |
| 11067 | i.seg[i.mem_operands] = &ds; |
| 11068 | break; |
| 11069 | case 4: |
| 11070 | i.seg[i.mem_operands] = &fs; |
| 11071 | break; |
| 11072 | case 5: |
| 11073 | i.seg[i.mem_operands] = &gs; |
| 11074 | break; |
| 11075 | } |
| 11076 | |
| 11077 | /* Skip the ':' and whitespace. */ |
| 11078 | ++op_string; |
| 11079 | if (is_space_char (*op_string)) |
| 11080 | ++op_string; |
| 11081 | |
| 11082 | if (!is_digit_char (*op_string) |
| 11083 | && !is_identifier_char (*op_string) |
| 11084 | && *op_string != '(' |
| 11085 | && *op_string != ABSOLUTE_PREFIX) |
| 11086 | { |
| 11087 | as_bad (_("bad memory operand `%s'"), op_string); |
| 11088 | return 0; |
| 11089 | } |
| 11090 | /* Handle case of %es:*foo. */ |
| 11091 | if (*op_string == ABSOLUTE_PREFIX) |
| 11092 | { |
| 11093 | ++op_string; |
| 11094 | if (is_space_char (*op_string)) |
| 11095 | ++op_string; |
| 11096 | i.jumpabsolute = TRUE; |
| 11097 | } |
| 11098 | goto do_memory_reference; |
| 11099 | } |
| 11100 | |
| 11101 | /* Handle vector operations. */ |
| 11102 | if (*op_string == '{') |
| 11103 | { |
| 11104 | op_string = check_VecOperations (op_string, NULL); |
| 11105 | if (op_string == NULL) |
| 11106 | return 0; |
| 11107 | } |
| 11108 | |
| 11109 | if (*op_string) |
| 11110 | { |
| 11111 | as_bad (_("junk `%s' after register"), op_string); |
| 11112 | return 0; |
| 11113 | } |
| 11114 | temp = r->reg_type; |
| 11115 | temp.bitfield.baseindex = 0; |
| 11116 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
| 11117 | temp); |
| 11118 | i.types[this_operand].bitfield.unspecified = 0; |
| 11119 | i.op[this_operand].regs = r; |
| 11120 | i.reg_operands++; |
| 11121 | } |
| 11122 | else if (*op_string == REGISTER_PREFIX) |
| 11123 | { |
| 11124 | as_bad (_("bad register name `%s'"), op_string); |
| 11125 | return 0; |
| 11126 | } |
| 11127 | else if (*op_string == IMMEDIATE_PREFIX) |
| 11128 | { |
| 11129 | ++op_string; |
| 11130 | if (i.jumpabsolute) |
| 11131 | { |
| 11132 | as_bad (_("immediate operand illegal with absolute jump")); |
| 11133 | return 0; |
| 11134 | } |
| 11135 | if (!i386_immediate (op_string)) |
| 11136 | return 0; |
| 11137 | } |
| 11138 | else if (RC_SAE_immediate (operand_string)) |
| 11139 | { |
| 11140 | /* If it is a RC or SAE immediate, do nothing. */ |
| 11141 | ; |
| 11142 | } |
| 11143 | else if (is_digit_char (*op_string) |
| 11144 | || is_identifier_char (*op_string) |
| 11145 | || *op_string == '"' |
| 11146 | || *op_string == '(') |
| 11147 | { |
| 11148 | /* This is a memory reference of some sort. */ |
| 11149 | char *base_string; |
| 11150 | |
| 11151 | /* Start and end of displacement string expression (if found). */ |
| 11152 | char *displacement_string_start; |
| 11153 | char *displacement_string_end; |
| 11154 | char *vop_start; |
| 11155 | |
| 11156 | do_memory_reference: |
| 11157 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
| 11158 | return 0; |
| 11159 | if ((i.mem_operands == 1 |
| 11160 | && !current_templates->start->opcode_modifier.isstring) |
| 11161 | || i.mem_operands == 2) |
| 11162 | { |
| 11163 | as_bad (_("too many memory references for `%s'"), |
| 11164 | current_templates->start->name); |
| 11165 | return 0; |
| 11166 | } |
| 11167 | |
| 11168 | /* Check for base index form. We detect the base index form by |
| 11169 | looking for an ')' at the end of the operand, searching |
| 11170 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' |
| 11171 | after the '('. */ |
| 11172 | base_string = op_string + strlen (op_string); |
| 11173 | |
| 11174 | /* Handle vector operations. */ |
| 11175 | vop_start = strchr (op_string, '{'); |
| 11176 | if (vop_start && vop_start < base_string) |
| 11177 | { |
| 11178 | if (check_VecOperations (vop_start, base_string) == NULL) |
| 11179 | return 0; |
| 11180 | base_string = vop_start; |
| 11181 | } |
| 11182 | |
| 11183 | --base_string; |
| 11184 | if (is_space_char (*base_string)) |
| 11185 | --base_string; |
| 11186 | |
| 11187 | /* If we only have a displacement, set-up for it to be parsed later. */ |
| 11188 | displacement_string_start = op_string; |
| 11189 | displacement_string_end = base_string + 1; |
| 11190 | |
| 11191 | if (*base_string == ')') |
| 11192 | { |
| 11193 | char *temp_string; |
| 11194 | unsigned int parens_balanced = 1; |
| 11195 | /* We've already checked that the number of left & right ()'s are |
| 11196 | equal, so this loop will not be infinite. */ |
| 11197 | do |
| 11198 | { |
| 11199 | base_string--; |
| 11200 | if (*base_string == ')') |
| 11201 | parens_balanced++; |
| 11202 | if (*base_string == '(') |
| 11203 | parens_balanced--; |
| 11204 | } |
| 11205 | while (parens_balanced); |
| 11206 | |
| 11207 | temp_string = base_string; |
| 11208 | |
| 11209 | /* Skip past '(' and whitespace. */ |
| 11210 | ++base_string; |
| 11211 | if (is_space_char (*base_string)) |
| 11212 | ++base_string; |
| 11213 | |
| 11214 | if (*base_string == ',' |
| 11215 | || ((i.base_reg = parse_register (base_string, &end_op)) |
| 11216 | != NULL)) |
| 11217 | { |
| 11218 | displacement_string_end = temp_string; |
| 11219 | |
| 11220 | i.types[this_operand].bitfield.baseindex = 1; |
| 11221 | |
| 11222 | if (i.base_reg) |
| 11223 | { |
| 11224 | base_string = end_op; |
| 11225 | if (is_space_char (*base_string)) |
| 11226 | ++base_string; |
| 11227 | } |
| 11228 | |
| 11229 | /* There may be an index reg or scale factor here. */ |
| 11230 | if (*base_string == ',') |
| 11231 | { |
| 11232 | ++base_string; |
| 11233 | if (is_space_char (*base_string)) |
| 11234 | ++base_string; |
| 11235 | |
| 11236 | if ((i.index_reg = parse_register (base_string, &end_op)) |
| 11237 | != NULL) |
| 11238 | { |
| 11239 | base_string = end_op; |
| 11240 | if (is_space_char (*base_string)) |
| 11241 | ++base_string; |
| 11242 | if (*base_string == ',') |
| 11243 | { |
| 11244 | ++base_string; |
| 11245 | if (is_space_char (*base_string)) |
| 11246 | ++base_string; |
| 11247 | } |
| 11248 | else if (*base_string != ')') |
| 11249 | { |
| 11250 | as_bad (_("expecting `,' or `)' " |
| 11251 | "after index register in `%s'"), |
| 11252 | operand_string); |
| 11253 | return 0; |
| 11254 | } |
| 11255 | } |
| 11256 | else if (*base_string == REGISTER_PREFIX) |
| 11257 | { |
| 11258 | end_op = strchr (base_string, ','); |
| 11259 | if (end_op) |
| 11260 | *end_op = '\0'; |
| 11261 | as_bad (_("bad register name `%s'"), base_string); |
| 11262 | return 0; |
| 11263 | } |
| 11264 | |
| 11265 | /* Check for scale factor. */ |
| 11266 | if (*base_string != ')') |
| 11267 | { |
| 11268 | char *end_scale = i386_scale (base_string); |
| 11269 | |
| 11270 | if (!end_scale) |
| 11271 | return 0; |
| 11272 | |
| 11273 | base_string = end_scale; |
| 11274 | if (is_space_char (*base_string)) |
| 11275 | ++base_string; |
| 11276 | if (*base_string != ')') |
| 11277 | { |
| 11278 | as_bad (_("expecting `)' " |
| 11279 | "after scale factor in `%s'"), |
| 11280 | operand_string); |
| 11281 | return 0; |
| 11282 | } |
| 11283 | } |
| 11284 | else if (!i.index_reg) |
| 11285 | { |
| 11286 | as_bad (_("expecting index register or scale factor " |
| 11287 | "after `,'; got '%c'"), |
| 11288 | *base_string); |
| 11289 | return 0; |
| 11290 | } |
| 11291 | } |
| 11292 | else if (*base_string != ')') |
| 11293 | { |
| 11294 | as_bad (_("expecting `,' or `)' " |
| 11295 | "after base register in `%s'"), |
| 11296 | operand_string); |
| 11297 | return 0; |
| 11298 | } |
| 11299 | } |
| 11300 | else if (*base_string == REGISTER_PREFIX) |
| 11301 | { |
| 11302 | end_op = strchr (base_string, ','); |
| 11303 | if (end_op) |
| 11304 | *end_op = '\0'; |
| 11305 | as_bad (_("bad register name `%s'"), base_string); |
| 11306 | return 0; |
| 11307 | } |
| 11308 | } |
| 11309 | |
| 11310 | /* If there's an expression beginning the operand, parse it, |
| 11311 | assuming displacement_string_start and |
| 11312 | displacement_string_end are meaningful. */ |
| 11313 | if (displacement_string_start != displacement_string_end) |
| 11314 | { |
| 11315 | if (!i386_displacement (displacement_string_start, |
| 11316 | displacement_string_end)) |
| 11317 | return 0; |
| 11318 | } |
| 11319 | |
| 11320 | /* Special case for (%dx) while doing input/output op. */ |
| 11321 | if (i.base_reg |
| 11322 | && i.base_reg->reg_type.bitfield.instance == RegD |
| 11323 | && i.base_reg->reg_type.bitfield.word |
| 11324 | && i.index_reg == 0 |
| 11325 | && i.log2_scale_factor == 0 |
| 11326 | && i.seg[i.mem_operands] == 0 |
| 11327 | && !operand_type_check (i.types[this_operand], disp)) |
| 11328 | { |
| 11329 | i.types[this_operand] = i.base_reg->reg_type; |
| 11330 | return 1; |
| 11331 | } |
| 11332 | |
| 11333 | if (i386_index_check (operand_string) == 0) |
| 11334 | return 0; |
| 11335 | i.flags[this_operand] |= Operand_Mem; |
| 11336 | if (i.mem_operands == 0) |
| 11337 | i.memop1_string = xstrdup (operand_string); |
| 11338 | i.mem_operands++; |
| 11339 | } |
| 11340 | else |
| 11341 | { |
| 11342 | /* It's not a memory operand; argh! */ |
| 11343 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
| 11344 | output_invalid (*op_string), |
| 11345 | this_operand + 1, |
| 11346 | op_string); |
| 11347 | return 0; |
| 11348 | } |
| 11349 | return 1; /* Normal return. */ |
| 11350 | } |
| 11351 | \f |
| 11352 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
| 11353 | that an rs_machine_dependent frag may reach. */ |
| 11354 | |
| 11355 | unsigned int |
| 11356 | i386_frag_max_var (fragS *frag) |
| 11357 | { |
| 11358 | /* The only relaxable frags are for jumps. |
| 11359 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ |
| 11360 | gas_assert (frag->fr_type == rs_machine_dependent); |
| 11361 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; |
| 11362 | } |
| 11363 | |
| 11364 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 11365 | static int |
| 11366 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
| 11367 | { |
| 11368 | /* STT_GNU_IFUNC symbol must go through PLT. */ |
| 11369 | if ((symbol_get_bfdsym (fr_symbol)->flags |
| 11370 | & BSF_GNU_INDIRECT_FUNCTION) != 0) |
| 11371 | return 0; |
| 11372 | |
| 11373 | if (!S_IS_EXTERNAL (fr_symbol)) |
| 11374 | /* Symbol may be weak or local. */ |
| 11375 | return !S_IS_WEAK (fr_symbol); |
| 11376 | |
| 11377 | /* Global symbols with non-default visibility can't be preempted. */ |
| 11378 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) |
| 11379 | return 1; |
| 11380 | |
| 11381 | if (fr_var != NO_RELOC) |
| 11382 | switch ((enum bfd_reloc_code_real) fr_var) |
| 11383 | { |
| 11384 | case BFD_RELOC_386_PLT32: |
| 11385 | case BFD_RELOC_X86_64_PLT32: |
| 11386 | /* Symbol with PLT relocation may be preempted. */ |
| 11387 | return 0; |
| 11388 | default: |
| 11389 | abort (); |
| 11390 | } |
| 11391 | |
| 11392 | /* Global symbols with default visibility in a shared library may be |
| 11393 | preempted by another definition. */ |
| 11394 | return !shared; |
| 11395 | } |
| 11396 | #endif |
| 11397 | |
| 11398 | /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture |
| 11399 | Note also work for Skylake and Cascadelake. |
| 11400 | --------------------------------------------------------------------- |
| 11401 | | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND | |
| 11402 | | ------ | ----------- | ------- | -------- | |
| 11403 | | Jo | N | N | Y | |
| 11404 | | Jno | N | N | Y | |
| 11405 | | Jc/Jb | Y | N | Y | |
| 11406 | | Jae/Jnb | Y | N | Y | |
| 11407 | | Je/Jz | Y | Y | Y | |
| 11408 | | Jne/Jnz | Y | Y | Y | |
| 11409 | | Jna/Jbe | Y | N | Y | |
| 11410 | | Ja/Jnbe | Y | N | Y | |
| 11411 | | Js | N | N | Y | |
| 11412 | | Jns | N | N | Y | |
| 11413 | | Jp/Jpe | N | N | Y | |
| 11414 | | Jnp/Jpo | N | N | Y | |
| 11415 | | Jl/Jnge | Y | Y | Y | |
| 11416 | | Jge/Jnl | Y | Y | Y | |
| 11417 | | Jle/Jng | Y | Y | Y | |
| 11418 | | Jg/Jnle | Y | Y | Y | |
| 11419 | --------------------------------------------------------------------- */ |
| 11420 | static int |
| 11421 | i386_macro_fusible_p (enum mf_cmp_kind mf_cmp, enum mf_jcc_kind mf_jcc) |
| 11422 | { |
| 11423 | if (mf_cmp == mf_cmp_alu_cmp) |
| 11424 | return ((mf_jcc >= mf_jcc_jc && mf_jcc <= mf_jcc_jna) |
| 11425 | || mf_jcc == mf_jcc_jl || mf_jcc == mf_jcc_jle); |
| 11426 | if (mf_cmp == mf_cmp_incdec) |
| 11427 | return (mf_jcc == mf_jcc_je || mf_jcc == mf_jcc_jl |
| 11428 | || mf_jcc == mf_jcc_jle); |
| 11429 | if (mf_cmp == mf_cmp_test_and) |
| 11430 | return 1; |
| 11431 | return 0; |
| 11432 | } |
| 11433 | |
| 11434 | /* Return the next non-empty frag. */ |
| 11435 | |
| 11436 | static fragS * |
| 11437 | i386_next_non_empty_frag (fragS *fragP) |
| 11438 | { |
| 11439 | /* There may be a frag with a ".fill 0" when there is no room in |
| 11440 | the current frag for frag_grow in output_insn. */ |
| 11441 | for (fragP = fragP->fr_next; |
| 11442 | (fragP != NULL |
| 11443 | && fragP->fr_type == rs_fill |
| 11444 | && fragP->fr_fix == 0); |
| 11445 | fragP = fragP->fr_next) |
| 11446 | ; |
| 11447 | return fragP; |
| 11448 | } |
| 11449 | |
| 11450 | /* Return the next jcc frag after BRANCH_PADDING. */ |
| 11451 | |
| 11452 | static fragS * |
| 11453 | i386_next_fusible_jcc_frag (fragS *maybe_cmp_fragP, fragS *pad_fragP) |
| 11454 | { |
| 11455 | fragS *branch_fragP; |
| 11456 | if (!pad_fragP) |
| 11457 | return NULL; |
| 11458 | |
| 11459 | if (pad_fragP->fr_type == rs_machine_dependent |
| 11460 | && (TYPE_FROM_RELAX_STATE (pad_fragP->fr_subtype) |
| 11461 | == BRANCH_PADDING)) |
| 11462 | { |
| 11463 | branch_fragP = i386_next_non_empty_frag (pad_fragP); |
| 11464 | if (branch_fragP->fr_type != rs_machine_dependent) |
| 11465 | return NULL; |
| 11466 | if (TYPE_FROM_RELAX_STATE (branch_fragP->fr_subtype) == COND_JUMP |
| 11467 | && i386_macro_fusible_p (maybe_cmp_fragP->tc_frag_data.mf_type, |
| 11468 | pad_fragP->tc_frag_data.mf_type)) |
| 11469 | return branch_fragP; |
| 11470 | } |
| 11471 | |
| 11472 | return NULL; |
| 11473 | } |
| 11474 | |
| 11475 | /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */ |
| 11476 | |
| 11477 | static void |
| 11478 | i386_classify_machine_dependent_frag (fragS *fragP) |
| 11479 | { |
| 11480 | fragS *cmp_fragP; |
| 11481 | fragS *pad_fragP; |
| 11482 | fragS *branch_fragP; |
| 11483 | fragS *next_fragP; |
| 11484 | unsigned int max_prefix_length; |
| 11485 | |
| 11486 | if (fragP->tc_frag_data.classified) |
| 11487 | return; |
| 11488 | |
| 11489 | /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert |
| 11490 | FUSED_JCC_PADDING and merge BRANCH_PADDING. */ |
| 11491 | for (next_fragP = fragP; |
| 11492 | next_fragP != NULL; |
| 11493 | next_fragP = next_fragP->fr_next) |
| 11494 | { |
| 11495 | next_fragP->tc_frag_data.classified = 1; |
| 11496 | if (next_fragP->fr_type == rs_machine_dependent) |
| 11497 | switch (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)) |
| 11498 | { |
| 11499 | case BRANCH_PADDING: |
| 11500 | /* The BRANCH_PADDING frag must be followed by a branch |
| 11501 | frag. */ |
| 11502 | branch_fragP = i386_next_non_empty_frag (next_fragP); |
| 11503 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; |
| 11504 | break; |
| 11505 | case FUSED_JCC_PADDING: |
| 11506 | /* Check if this is a fused jcc: |
| 11507 | FUSED_JCC_PADDING |
| 11508 | CMP like instruction |
| 11509 | BRANCH_PADDING |
| 11510 | COND_JUMP |
| 11511 | */ |
| 11512 | cmp_fragP = i386_next_non_empty_frag (next_fragP); |
| 11513 | pad_fragP = i386_next_non_empty_frag (cmp_fragP); |
| 11514 | branch_fragP = i386_next_fusible_jcc_frag (next_fragP, pad_fragP); |
| 11515 | if (branch_fragP) |
| 11516 | { |
| 11517 | /* The BRANCH_PADDING frag is merged with the |
| 11518 | FUSED_JCC_PADDING frag. */ |
| 11519 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; |
| 11520 | /* CMP like instruction size. */ |
| 11521 | next_fragP->tc_frag_data.cmp_size = cmp_fragP->fr_fix; |
| 11522 | frag_wane (pad_fragP); |
| 11523 | /* Skip to branch_fragP. */ |
| 11524 | next_fragP = branch_fragP; |
| 11525 | } |
| 11526 | else if (next_fragP->tc_frag_data.max_prefix_length) |
| 11527 | { |
| 11528 | /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't |
| 11529 | a fused jcc. */ |
| 11530 | next_fragP->fr_subtype |
| 11531 | = ENCODE_RELAX_STATE (BRANCH_PREFIX, 0); |
| 11532 | next_fragP->tc_frag_data.max_bytes |
| 11533 | = next_fragP->tc_frag_data.max_prefix_length; |
| 11534 | /* This will be updated in the BRANCH_PREFIX scan. */ |
| 11535 | next_fragP->tc_frag_data.max_prefix_length = 0; |
| 11536 | } |
| 11537 | else |
| 11538 | frag_wane (next_fragP); |
| 11539 | break; |
| 11540 | } |
| 11541 | } |
| 11542 | |
| 11543 | /* Stop if there is no BRANCH_PREFIX. */ |
| 11544 | if (!align_branch_prefix_size) |
| 11545 | return; |
| 11546 | |
| 11547 | /* Scan for BRANCH_PREFIX. */ |
| 11548 | for (; fragP != NULL; fragP = fragP->fr_next) |
| 11549 | { |
| 11550 | if (fragP->fr_type != rs_machine_dependent |
| 11551 | || (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) |
| 11552 | != BRANCH_PREFIX)) |
| 11553 | continue; |
| 11554 | |
| 11555 | /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and |
| 11556 | COND_JUMP_PREFIX. */ |
| 11557 | max_prefix_length = 0; |
| 11558 | for (next_fragP = fragP; |
| 11559 | next_fragP != NULL; |
| 11560 | next_fragP = next_fragP->fr_next) |
| 11561 | { |
| 11562 | if (next_fragP->fr_type == rs_fill) |
| 11563 | /* Skip rs_fill frags. */ |
| 11564 | continue; |
| 11565 | else if (next_fragP->fr_type != rs_machine_dependent) |
| 11566 | /* Stop for all other frags. */ |
| 11567 | break; |
| 11568 | |
| 11569 | /* rs_machine_dependent frags. */ |
| 11570 | if (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) |
| 11571 | == BRANCH_PREFIX) |
| 11572 | { |
| 11573 | /* Count BRANCH_PREFIX frags. */ |
| 11574 | if (max_prefix_length >= MAX_FUSED_JCC_PADDING_SIZE) |
| 11575 | { |
| 11576 | max_prefix_length = MAX_FUSED_JCC_PADDING_SIZE; |
| 11577 | frag_wane (next_fragP); |
| 11578 | } |
| 11579 | else |
| 11580 | max_prefix_length |
| 11581 | += next_fragP->tc_frag_data.max_bytes; |
| 11582 | } |
| 11583 | else if ((TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) |
| 11584 | == BRANCH_PADDING) |
| 11585 | || (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) |
| 11586 | == FUSED_JCC_PADDING)) |
| 11587 | { |
| 11588 | /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */ |
| 11589 | fragP->tc_frag_data.u.padding_fragP = next_fragP; |
| 11590 | break; |
| 11591 | } |
| 11592 | else |
| 11593 | /* Stop for other rs_machine_dependent frags. */ |
| 11594 | break; |
| 11595 | } |
| 11596 | |
| 11597 | fragP->tc_frag_data.max_prefix_length = max_prefix_length; |
| 11598 | |
| 11599 | /* Skip to the next frag. */ |
| 11600 | fragP = next_fragP; |
| 11601 | } |
| 11602 | } |
| 11603 | |
| 11604 | /* Compute padding size for |
| 11605 | |
| 11606 | FUSED_JCC_PADDING |
| 11607 | CMP like instruction |
| 11608 | BRANCH_PADDING |
| 11609 | COND_JUMP/UNCOND_JUMP |
| 11610 | |
| 11611 | or |
| 11612 | |
| 11613 | BRANCH_PADDING |
| 11614 | COND_JUMP/UNCOND_JUMP |
| 11615 | */ |
| 11616 | |
| 11617 | static int |
| 11618 | i386_branch_padding_size (fragS *fragP, offsetT address) |
| 11619 | { |
| 11620 | unsigned int offset, size, padding_size; |
| 11621 | fragS *branch_fragP = fragP->tc_frag_data.u.branch_fragP; |
| 11622 | |
| 11623 | /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */ |
| 11624 | if (!address) |
| 11625 | address = fragP->fr_address; |
| 11626 | address += fragP->fr_fix; |
| 11627 | |
| 11628 | /* CMP like instrunction size. */ |
| 11629 | size = fragP->tc_frag_data.cmp_size; |
| 11630 | |
| 11631 | /* The base size of the branch frag. */ |
| 11632 | size += branch_fragP->fr_fix; |
| 11633 | |
| 11634 | /* Add opcode and displacement bytes for the rs_machine_dependent |
| 11635 | branch frag. */ |
| 11636 | if (branch_fragP->fr_type == rs_machine_dependent) |
| 11637 | size += md_relax_table[branch_fragP->fr_subtype].rlx_length; |
| 11638 | |
| 11639 | /* Check if branch is within boundary and doesn't end at the last |
| 11640 | byte. */ |
| 11641 | offset = address & ((1U << align_branch_power) - 1); |
| 11642 | if ((offset + size) >= (1U << align_branch_power)) |
| 11643 | /* Padding needed to avoid crossing boundary. */ |
| 11644 | padding_size = (1U << align_branch_power) - offset; |
| 11645 | else |
| 11646 | /* No padding needed. */ |
| 11647 | padding_size = 0; |
| 11648 | |
| 11649 | /* The return value may be saved in tc_frag_data.length which is |
| 11650 | unsigned byte. */ |
| 11651 | if (!fits_in_unsigned_byte (padding_size)) |
| 11652 | abort (); |
| 11653 | |
| 11654 | return padding_size; |
| 11655 | } |
| 11656 | |
| 11657 | /* i386_generic_table_relax_frag() |
| 11658 | |
| 11659 | Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to |
| 11660 | grow/shrink padding to align branch frags. Hand others to |
| 11661 | relax_frag(). */ |
| 11662 | |
| 11663 | long |
| 11664 | i386_generic_table_relax_frag (segT segment, fragS *fragP, long stretch) |
| 11665 | { |
| 11666 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
| 11667 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) |
| 11668 | { |
| 11669 | long padding_size = i386_branch_padding_size (fragP, 0); |
| 11670 | long grow = padding_size - fragP->tc_frag_data.length; |
| 11671 | |
| 11672 | /* When the BRANCH_PREFIX frag is used, the computed address |
| 11673 | must match the actual address and there should be no padding. */ |
| 11674 | if (fragP->tc_frag_data.padding_address |
| 11675 | && (fragP->tc_frag_data.padding_address != fragP->fr_address |
| 11676 | || padding_size)) |
| 11677 | abort (); |
| 11678 | |
| 11679 | /* Update the padding size. */ |
| 11680 | if (grow) |
| 11681 | fragP->tc_frag_data.length = padding_size; |
| 11682 | |
| 11683 | return grow; |
| 11684 | } |
| 11685 | else if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) |
| 11686 | { |
| 11687 | fragS *padding_fragP, *next_fragP; |
| 11688 | long padding_size, left_size, last_size; |
| 11689 | |
| 11690 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; |
| 11691 | if (!padding_fragP) |
| 11692 | /* Use the padding set by the leading BRANCH_PREFIX frag. */ |
| 11693 | return (fragP->tc_frag_data.length |
| 11694 | - fragP->tc_frag_data.last_length); |
| 11695 | |
| 11696 | /* Compute the relative address of the padding frag in the very |
| 11697 | first time where the BRANCH_PREFIX frag sizes are zero. */ |
| 11698 | if (!fragP->tc_frag_data.padding_address) |
| 11699 | fragP->tc_frag_data.padding_address |
| 11700 | = padding_fragP->fr_address - (fragP->fr_address - stretch); |
| 11701 | |
| 11702 | /* First update the last length from the previous interation. */ |
| 11703 | left_size = fragP->tc_frag_data.prefix_length; |
| 11704 | for (next_fragP = fragP; |
| 11705 | next_fragP != padding_fragP; |
| 11706 | next_fragP = next_fragP->fr_next) |
| 11707 | if (next_fragP->fr_type == rs_machine_dependent |
| 11708 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) |
| 11709 | == BRANCH_PREFIX)) |
| 11710 | { |
| 11711 | if (left_size) |
| 11712 | { |
| 11713 | int max = next_fragP->tc_frag_data.max_bytes; |
| 11714 | if (max) |
| 11715 | { |
| 11716 | int size; |
| 11717 | if (max > left_size) |
| 11718 | size = left_size; |
| 11719 | else |
| 11720 | size = max; |
| 11721 | left_size -= size; |
| 11722 | next_fragP->tc_frag_data.last_length = size; |
| 11723 | } |
| 11724 | } |
| 11725 | else |
| 11726 | next_fragP->tc_frag_data.last_length = 0; |
| 11727 | } |
| 11728 | |
| 11729 | /* Check the padding size for the padding frag. */ |
| 11730 | padding_size = i386_branch_padding_size |
| 11731 | (padding_fragP, (fragP->fr_address |
| 11732 | + fragP->tc_frag_data.padding_address)); |
| 11733 | |
| 11734 | last_size = fragP->tc_frag_data.prefix_length; |
| 11735 | /* Check if there is change from the last interation. */ |
| 11736 | if (padding_size == last_size) |
| 11737 | { |
| 11738 | /* Update the expected address of the padding frag. */ |
| 11739 | padding_fragP->tc_frag_data.padding_address |
| 11740 | = (fragP->fr_address + padding_size |
| 11741 | + fragP->tc_frag_data.padding_address); |
| 11742 | return 0; |
| 11743 | } |
| 11744 | |
| 11745 | if (padding_size > fragP->tc_frag_data.max_prefix_length) |
| 11746 | { |
| 11747 | /* No padding if there is no sufficient room. Clear the |
| 11748 | expected address of the padding frag. */ |
| 11749 | padding_fragP->tc_frag_data.padding_address = 0; |
| 11750 | padding_size = 0; |
| 11751 | } |
| 11752 | else |
| 11753 | /* Store the expected address of the padding frag. */ |
| 11754 | padding_fragP->tc_frag_data.padding_address |
| 11755 | = (fragP->fr_address + padding_size |
| 11756 | + fragP->tc_frag_data.padding_address); |
| 11757 | |
| 11758 | fragP->tc_frag_data.prefix_length = padding_size; |
| 11759 | |
| 11760 | /* Update the length for the current interation. */ |
| 11761 | left_size = padding_size; |
| 11762 | for (next_fragP = fragP; |
| 11763 | next_fragP != padding_fragP; |
| 11764 | next_fragP = next_fragP->fr_next) |
| 11765 | if (next_fragP->fr_type == rs_machine_dependent |
| 11766 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) |
| 11767 | == BRANCH_PREFIX)) |
| 11768 | { |
| 11769 | if (left_size) |
| 11770 | { |
| 11771 | int max = next_fragP->tc_frag_data.max_bytes; |
| 11772 | if (max) |
| 11773 | { |
| 11774 | int size; |
| 11775 | if (max > left_size) |
| 11776 | size = left_size; |
| 11777 | else |
| 11778 | size = max; |
| 11779 | left_size -= size; |
| 11780 | next_fragP->tc_frag_data.length = size; |
| 11781 | } |
| 11782 | } |
| 11783 | else |
| 11784 | next_fragP->tc_frag_data.length = 0; |
| 11785 | } |
| 11786 | |
| 11787 | return (fragP->tc_frag_data.length |
| 11788 | - fragP->tc_frag_data.last_length); |
| 11789 | } |
| 11790 | return relax_frag (segment, fragP, stretch); |
| 11791 | } |
| 11792 | |
| 11793 | /* md_estimate_size_before_relax() |
| 11794 | |
| 11795 | Called just before relax() for rs_machine_dependent frags. The x86 |
| 11796 | assembler uses these frags to handle variable size jump |
| 11797 | instructions. |
| 11798 | |
| 11799 | Any symbol that is now undefined will not become defined. |
| 11800 | Return the correct fr_subtype in the frag. |
| 11801 | Return the initial "guess for variable size of frag" to caller. |
| 11802 | The guess is actually the growth beyond the fixed part. Whatever |
| 11803 | we do to grow the fixed or variable part contributes to our |
| 11804 | returned value. */ |
| 11805 | |
| 11806 | int |
| 11807 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
| 11808 | { |
| 11809 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
| 11810 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX |
| 11811 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) |
| 11812 | { |
| 11813 | i386_classify_machine_dependent_frag (fragP); |
| 11814 | return fragP->tc_frag_data.length; |
| 11815 | } |
| 11816 | |
| 11817 | /* We've already got fragP->fr_subtype right; all we have to do is |
| 11818 | check for un-relaxable symbols. On an ELF system, we can't relax |
| 11819 | an externally visible symbol, because it may be overridden by a |
| 11820 | shared library. */ |
| 11821 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment |
| 11822 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 11823 | || (IS_ELF |
| 11824 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
| 11825 | fragP->fr_var)) |
| 11826 | #endif |
| 11827 | #if defined (OBJ_COFF) && defined (TE_PE) |
| 11828 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
| 11829 | && S_IS_WEAK (fragP->fr_symbol)) |
| 11830 | #endif |
| 11831 | ) |
| 11832 | { |
| 11833 | /* Symbol is undefined in this segment, or we need to keep a |
| 11834 | reloc so that weak symbols can be overridden. */ |
| 11835 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; |
| 11836 | enum bfd_reloc_code_real reloc_type; |
| 11837 | unsigned char *opcode; |
| 11838 | int old_fr_fix; |
| 11839 | |
| 11840 | if (fragP->fr_var != NO_RELOC) |
| 11841 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
| 11842 | else if (size == 2) |
| 11843 | reloc_type = BFD_RELOC_16_PCREL; |
| 11844 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 11845 | else if (need_plt32_p (fragP->fr_symbol)) |
| 11846 | reloc_type = BFD_RELOC_X86_64_PLT32; |
| 11847 | #endif |
| 11848 | else |
| 11849 | reloc_type = BFD_RELOC_32_PCREL; |
| 11850 | |
| 11851 | old_fr_fix = fragP->fr_fix; |
| 11852 | opcode = (unsigned char *) fragP->fr_opcode; |
| 11853 | |
| 11854 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
| 11855 | { |
| 11856 | case UNCOND_JUMP: |
| 11857 | /* Make jmp (0xeb) a (d)word displacement jump. */ |
| 11858 | opcode[0] = 0xe9; |
| 11859 | fragP->fr_fix += size; |
| 11860 | fix_new (fragP, old_fr_fix, size, |
| 11861 | fragP->fr_symbol, |
| 11862 | fragP->fr_offset, 1, |
| 11863 | reloc_type); |
| 11864 | break; |
| 11865 | |
| 11866 | case COND_JUMP86: |
| 11867 | if (size == 2 |
| 11868 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) |
| 11869 | { |
| 11870 | /* Negate the condition, and branch past an |
| 11871 | unconditional jump. */ |
| 11872 | opcode[0] ^= 1; |
| 11873 | opcode[1] = 3; |
| 11874 | /* Insert an unconditional jump. */ |
| 11875 | opcode[2] = 0xe9; |
| 11876 | /* We added two extra opcode bytes, and have a two byte |
| 11877 | offset. */ |
| 11878 | fragP->fr_fix += 2 + 2; |
| 11879 | fix_new (fragP, old_fr_fix + 2, 2, |
| 11880 | fragP->fr_symbol, |
| 11881 | fragP->fr_offset, 1, |
| 11882 | reloc_type); |
| 11883 | break; |
| 11884 | } |
| 11885 | /* Fall through. */ |
| 11886 | |
| 11887 | case COND_JUMP: |
| 11888 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
| 11889 | { |
| 11890 | fixS *fixP; |
| 11891 | |
| 11892 | fragP->fr_fix += 1; |
| 11893 | fixP = fix_new (fragP, old_fr_fix, 1, |
| 11894 | fragP->fr_symbol, |
| 11895 | fragP->fr_offset, 1, |
| 11896 | BFD_RELOC_8_PCREL); |
| 11897 | fixP->fx_signed = 1; |
| 11898 | break; |
| 11899 | } |
| 11900 | |
| 11901 | /* This changes the byte-displacement jump 0x7N |
| 11902 | to the (d)word-displacement jump 0x0f,0x8N. */ |
| 11903 | opcode[1] = opcode[0] + 0x10; |
| 11904 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
| 11905 | /* We've added an opcode byte. */ |
| 11906 | fragP->fr_fix += 1 + size; |
| 11907 | fix_new (fragP, old_fr_fix + 1, size, |
| 11908 | fragP->fr_symbol, |
| 11909 | fragP->fr_offset, 1, |
| 11910 | reloc_type); |
| 11911 | break; |
| 11912 | |
| 11913 | default: |
| 11914 | BAD_CASE (fragP->fr_subtype); |
| 11915 | break; |
| 11916 | } |
| 11917 | frag_wane (fragP); |
| 11918 | return fragP->fr_fix - old_fr_fix; |
| 11919 | } |
| 11920 | |
| 11921 | /* Guess size depending on current relax state. Initially the relax |
| 11922 | state will correspond to a short jump and we return 1, because |
| 11923 | the variable part of the frag (the branch offset) is one byte |
| 11924 | long. However, we can relax a section more than once and in that |
| 11925 | case we must either set fr_subtype back to the unrelaxed state, |
| 11926 | or return the value for the appropriate branch. */ |
| 11927 | return md_relax_table[fragP->fr_subtype].rlx_length; |
| 11928 | } |
| 11929 | |
| 11930 | /* Called after relax() is finished. |
| 11931 | |
| 11932 | In: Address of frag. |
| 11933 | fr_type == rs_machine_dependent. |
| 11934 | fr_subtype is what the address relaxed to. |
| 11935 | |
| 11936 | Out: Any fixSs and constants are set up. |
| 11937 | Caller will turn frag into a ".space 0". */ |
| 11938 | |
| 11939 | void |
| 11940 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
| 11941 | fragS *fragP) |
| 11942 | { |
| 11943 | unsigned char *opcode; |
| 11944 | unsigned char *where_to_put_displacement = NULL; |
| 11945 | offsetT target_address; |
| 11946 | offsetT opcode_address; |
| 11947 | unsigned int extension = 0; |
| 11948 | offsetT displacement_from_opcode_start; |
| 11949 | |
| 11950 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
| 11951 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING |
| 11952 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) |
| 11953 | { |
| 11954 | /* Generate nop padding. */ |
| 11955 | unsigned int size = fragP->tc_frag_data.length; |
| 11956 | if (size) |
| 11957 | { |
| 11958 | if (size > fragP->tc_frag_data.max_bytes) |
| 11959 | abort (); |
| 11960 | |
| 11961 | if (flag_debug) |
| 11962 | { |
| 11963 | const char *msg; |
| 11964 | const char *branch = "branch"; |
| 11965 | const char *prefix = ""; |
| 11966 | fragS *padding_fragP; |
| 11967 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) |
| 11968 | == BRANCH_PREFIX) |
| 11969 | { |
| 11970 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; |
| 11971 | switch (fragP->tc_frag_data.default_prefix) |
| 11972 | { |
| 11973 | default: |
| 11974 | abort (); |
| 11975 | break; |
| 11976 | case CS_PREFIX_OPCODE: |
| 11977 | prefix = " cs"; |
| 11978 | break; |
| 11979 | case DS_PREFIX_OPCODE: |
| 11980 | prefix = " ds"; |
| 11981 | break; |
| 11982 | case ES_PREFIX_OPCODE: |
| 11983 | prefix = " es"; |
| 11984 | break; |
| 11985 | case FS_PREFIX_OPCODE: |
| 11986 | prefix = " fs"; |
| 11987 | break; |
| 11988 | case GS_PREFIX_OPCODE: |
| 11989 | prefix = " gs"; |
| 11990 | break; |
| 11991 | case SS_PREFIX_OPCODE: |
| 11992 | prefix = " ss"; |
| 11993 | break; |
| 11994 | } |
| 11995 | if (padding_fragP) |
| 11996 | msg = _("%s:%u: add %d%s at 0x%llx to align " |
| 11997 | "%s within %d-byte boundary\n"); |
| 11998 | else |
| 11999 | msg = _("%s:%u: add additional %d%s at 0x%llx to " |
| 12000 | "align %s within %d-byte boundary\n"); |
| 12001 | } |
| 12002 | else |
| 12003 | { |
| 12004 | padding_fragP = fragP; |
| 12005 | msg = _("%s:%u: add %d%s-byte nop at 0x%llx to align " |
| 12006 | "%s within %d-byte boundary\n"); |
| 12007 | } |
| 12008 | |
| 12009 | if (padding_fragP) |
| 12010 | switch (padding_fragP->tc_frag_data.branch_type) |
| 12011 | { |
| 12012 | case align_branch_jcc: |
| 12013 | branch = "jcc"; |
| 12014 | break; |
| 12015 | case align_branch_fused: |
| 12016 | branch = "fused jcc"; |
| 12017 | break; |
| 12018 | case align_branch_jmp: |
| 12019 | branch = "jmp"; |
| 12020 | break; |
| 12021 | case align_branch_call: |
| 12022 | branch = "call"; |
| 12023 | break; |
| 12024 | case align_branch_indirect: |
| 12025 | branch = "indiret branch"; |
| 12026 | break; |
| 12027 | case align_branch_ret: |
| 12028 | branch = "ret"; |
| 12029 | break; |
| 12030 | default: |
| 12031 | break; |
| 12032 | } |
| 12033 | |
| 12034 | fprintf (stdout, msg, |
| 12035 | fragP->fr_file, fragP->fr_line, size, prefix, |
| 12036 | (long long) fragP->fr_address, branch, |
| 12037 | 1 << align_branch_power); |
| 12038 | } |
| 12039 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) |
| 12040 | memset (fragP->fr_opcode, |
| 12041 | fragP->tc_frag_data.default_prefix, size); |
| 12042 | else |
| 12043 | i386_generate_nops (fragP, (char *) fragP->fr_opcode, |
| 12044 | size, 0); |
| 12045 | fragP->fr_fix += size; |
| 12046 | } |
| 12047 | return; |
| 12048 | } |
| 12049 | |
| 12050 | opcode = (unsigned char *) fragP->fr_opcode; |
| 12051 | |
| 12052 | /* Address we want to reach in file space. */ |
| 12053 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
| 12054 | |
| 12055 | /* Address opcode resides at in file space. */ |
| 12056 | opcode_address = fragP->fr_address + fragP->fr_fix; |
| 12057 | |
| 12058 | /* Displacement from opcode start to fill into instruction. */ |
| 12059 | displacement_from_opcode_start = target_address - opcode_address; |
| 12060 | |
| 12061 | if ((fragP->fr_subtype & BIG) == 0) |
| 12062 | { |
| 12063 | /* Don't have to change opcode. */ |
| 12064 | extension = 1; /* 1 opcode + 1 displacement */ |
| 12065 | where_to_put_displacement = &opcode[1]; |
| 12066 | } |
| 12067 | else |
| 12068 | { |
| 12069 | if (no_cond_jump_promotion |
| 12070 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) |
| 12071 | as_warn_where (fragP->fr_file, fragP->fr_line, |
| 12072 | _("long jump required")); |
| 12073 | |
| 12074 | switch (fragP->fr_subtype) |
| 12075 | { |
| 12076 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): |
| 12077 | extension = 4; /* 1 opcode + 4 displacement */ |
| 12078 | opcode[0] = 0xe9; |
| 12079 | where_to_put_displacement = &opcode[1]; |
| 12080 | break; |
| 12081 | |
| 12082 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
| 12083 | extension = 2; /* 1 opcode + 2 displacement */ |
| 12084 | opcode[0] = 0xe9; |
| 12085 | where_to_put_displacement = &opcode[1]; |
| 12086 | break; |
| 12087 | |
| 12088 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
| 12089 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): |
| 12090 | extension = 5; /* 2 opcode + 4 displacement */ |
| 12091 | opcode[1] = opcode[0] + 0x10; |
| 12092 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
| 12093 | where_to_put_displacement = &opcode[2]; |
| 12094 | break; |
| 12095 | |
| 12096 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
| 12097 | extension = 3; /* 2 opcode + 2 displacement */ |
| 12098 | opcode[1] = opcode[0] + 0x10; |
| 12099 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
| 12100 | where_to_put_displacement = &opcode[2]; |
| 12101 | break; |
| 12102 | |
| 12103 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
| 12104 | extension = 4; |
| 12105 | opcode[0] ^= 1; |
| 12106 | opcode[1] = 3; |
| 12107 | opcode[2] = 0xe9; |
| 12108 | where_to_put_displacement = &opcode[3]; |
| 12109 | break; |
| 12110 | |
| 12111 | default: |
| 12112 | BAD_CASE (fragP->fr_subtype); |
| 12113 | break; |
| 12114 | } |
| 12115 | } |
| 12116 | |
| 12117 | /* If size if less then four we are sure that the operand fits, |
| 12118 | but if it's 4, then it could be that the displacement is larger |
| 12119 | then -/+ 2GB. */ |
| 12120 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 |
| 12121 | && object_64bit |
| 12122 | && ((addressT) (displacement_from_opcode_start - extension |
| 12123 | + ((addressT) 1 << 31)) |
| 12124 | > (((addressT) 2 << 31) - 1))) |
| 12125 | { |
| 12126 | as_bad_where (fragP->fr_file, fragP->fr_line, |
| 12127 | _("jump target out of range")); |
| 12128 | /* Make us emit 0. */ |
| 12129 | displacement_from_opcode_start = extension; |
| 12130 | } |
| 12131 | /* Now put displacement after opcode. */ |
| 12132 | md_number_to_chars ((char *) where_to_put_displacement, |
| 12133 | (valueT) (displacement_from_opcode_start - extension), |
| 12134 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
| 12135 | fragP->fr_fix += extension; |
| 12136 | } |
| 12137 | \f |
| 12138 | /* Apply a fixup (fixP) to segment data, once it has been determined |
| 12139 | by our caller that we have all the info we need to fix it up. |
| 12140 | |
| 12141 | Parameter valP is the pointer to the value of the bits. |
| 12142 | |
| 12143 | On the 386, immediates, displacements, and data pointers are all in |
| 12144 | the same (little-endian) format, so we don't need to care about which |
| 12145 | we are handling. */ |
| 12146 | |
| 12147 | void |
| 12148 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
| 12149 | { |
| 12150 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
| 12151 | valueT value = *valP; |
| 12152 | |
| 12153 | #if !defined (TE_Mach) |
| 12154 | if (fixP->fx_pcrel) |
| 12155 | { |
| 12156 | switch (fixP->fx_r_type) |
| 12157 | { |
| 12158 | default: |
| 12159 | break; |
| 12160 | |
| 12161 | case BFD_RELOC_64: |
| 12162 | fixP->fx_r_type = BFD_RELOC_64_PCREL; |
| 12163 | break; |
| 12164 | case BFD_RELOC_32: |
| 12165 | case BFD_RELOC_X86_64_32S: |
| 12166 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
| 12167 | break; |
| 12168 | case BFD_RELOC_16: |
| 12169 | fixP->fx_r_type = BFD_RELOC_16_PCREL; |
| 12170 | break; |
| 12171 | case BFD_RELOC_8: |
| 12172 | fixP->fx_r_type = BFD_RELOC_8_PCREL; |
| 12173 | break; |
| 12174 | } |
| 12175 | } |
| 12176 | |
| 12177 | if (fixP->fx_addsy != NULL |
| 12178 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
| 12179 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
| 12180 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
| 12181 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
| 12182 | && !use_rela_relocations) |
| 12183 | { |
| 12184 | /* This is a hack. There should be a better way to handle this. |
| 12185 | This covers for the fact that bfd_install_relocation will |
| 12186 | subtract the current location (for partial_inplace, PC relative |
| 12187 | relocations); see more below. */ |
| 12188 | #ifndef OBJ_AOUT |
| 12189 | if (IS_ELF |
| 12190 | #ifdef TE_PE |
| 12191 | || OUTPUT_FLAVOR == bfd_target_coff_flavour |
| 12192 | #endif |
| 12193 | ) |
| 12194 | value += fixP->fx_where + fixP->fx_frag->fr_address; |
| 12195 | #endif |
| 12196 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 12197 | if (IS_ELF) |
| 12198 | { |
| 12199 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
| 12200 | |
| 12201 | if ((sym_seg == seg |
| 12202 | || (symbol_section_p (fixP->fx_addsy) |
| 12203 | && sym_seg != absolute_section)) |
| 12204 | && !generic_force_reloc (fixP)) |
| 12205 | { |
| 12206 | /* Yes, we add the values in twice. This is because |
| 12207 | bfd_install_relocation subtracts them out again. I think |
| 12208 | bfd_install_relocation is broken, but I don't dare change |
| 12209 | it. FIXME. */ |
| 12210 | value += fixP->fx_where + fixP->fx_frag->fr_address; |
| 12211 | } |
| 12212 | } |
| 12213 | #endif |
| 12214 | #if defined (OBJ_COFF) && defined (TE_PE) |
| 12215 | /* For some reason, the PE format does not store a |
| 12216 | section address offset for a PC relative symbol. */ |
| 12217 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg |
| 12218 | || S_IS_WEAK (fixP->fx_addsy)) |
| 12219 | value += md_pcrel_from (fixP); |
| 12220 | #endif |
| 12221 | } |
| 12222 | #if defined (OBJ_COFF) && defined (TE_PE) |
| 12223 | if (fixP->fx_addsy != NULL |
| 12224 | && S_IS_WEAK (fixP->fx_addsy) |
| 12225 | /* PR 16858: Do not modify weak function references. */ |
| 12226 | && ! fixP->fx_pcrel) |
| 12227 | { |
| 12228 | #if !defined (TE_PEP) |
| 12229 | /* For x86 PE weak function symbols are neither PC-relative |
| 12230 | nor do they set S_IS_FUNCTION. So the only reliable way |
| 12231 | to detect them is to check the flags of their containing |
| 12232 | section. */ |
| 12233 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL |
| 12234 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) |
| 12235 | ; |
| 12236 | else |
| 12237 | #endif |
| 12238 | value -= S_GET_VALUE (fixP->fx_addsy); |
| 12239 | } |
| 12240 | #endif |
| 12241 | |
| 12242 | /* Fix a few things - the dynamic linker expects certain values here, |
| 12243 | and we must not disappoint it. */ |
| 12244 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 12245 | if (IS_ELF && fixP->fx_addsy) |
| 12246 | switch (fixP->fx_r_type) |
| 12247 | { |
| 12248 | case BFD_RELOC_386_PLT32: |
| 12249 | case BFD_RELOC_X86_64_PLT32: |
| 12250 | /* Make the jump instruction point to the address of the operand. |
| 12251 | At runtime we merely add the offset to the actual PLT entry. |
| 12252 | NB: Subtract the offset size only for jump instructions. */ |
| 12253 | if (fixP->fx_pcrel) |
| 12254 | value = -4; |
| 12255 | break; |
| 12256 | |
| 12257 | case BFD_RELOC_386_TLS_GD: |
| 12258 | case BFD_RELOC_386_TLS_LDM: |
| 12259 | case BFD_RELOC_386_TLS_IE_32: |
| 12260 | case BFD_RELOC_386_TLS_IE: |
| 12261 | case BFD_RELOC_386_TLS_GOTIE: |
| 12262 | case BFD_RELOC_386_TLS_GOTDESC: |
| 12263 | case BFD_RELOC_X86_64_TLSGD: |
| 12264 | case BFD_RELOC_X86_64_TLSLD: |
| 12265 | case BFD_RELOC_X86_64_GOTTPOFF: |
| 12266 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
| 12267 | value = 0; /* Fully resolved at runtime. No addend. */ |
| 12268 | /* Fallthrough */ |
| 12269 | case BFD_RELOC_386_TLS_LE: |
| 12270 | case BFD_RELOC_386_TLS_LDO_32: |
| 12271 | case BFD_RELOC_386_TLS_LE_32: |
| 12272 | case BFD_RELOC_X86_64_DTPOFF32: |
| 12273 | case BFD_RELOC_X86_64_DTPOFF64: |
| 12274 | case BFD_RELOC_X86_64_TPOFF32: |
| 12275 | case BFD_RELOC_X86_64_TPOFF64: |
| 12276 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
| 12277 | break; |
| 12278 | |
| 12279 | case BFD_RELOC_386_TLS_DESC_CALL: |
| 12280 | case BFD_RELOC_X86_64_TLSDESC_CALL: |
| 12281 | value = 0; /* Fully resolved at runtime. No addend. */ |
| 12282 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
| 12283 | fixP->fx_done = 0; |
| 12284 | return; |
| 12285 | |
| 12286 | case BFD_RELOC_VTABLE_INHERIT: |
| 12287 | case BFD_RELOC_VTABLE_ENTRY: |
| 12288 | fixP->fx_done = 0; |
| 12289 | return; |
| 12290 | |
| 12291 | default: |
| 12292 | break; |
| 12293 | } |
| 12294 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ |
| 12295 | *valP = value; |
| 12296 | #endif /* !defined (TE_Mach) */ |
| 12297 | |
| 12298 | /* Are we finished with this relocation now? */ |
| 12299 | if (fixP->fx_addsy == NULL) |
| 12300 | fixP->fx_done = 1; |
| 12301 | #if defined (OBJ_COFF) && defined (TE_PE) |
| 12302 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) |
| 12303 | { |
| 12304 | fixP->fx_done = 0; |
| 12305 | /* Remember value for tc_gen_reloc. */ |
| 12306 | fixP->fx_addnumber = value; |
| 12307 | /* Clear out the frag for now. */ |
| 12308 | value = 0; |
| 12309 | } |
| 12310 | #endif |
| 12311 | else if (use_rela_relocations) |
| 12312 | { |
| 12313 | fixP->fx_no_overflow = 1; |
| 12314 | /* Remember value for tc_gen_reloc. */ |
| 12315 | fixP->fx_addnumber = value; |
| 12316 | value = 0; |
| 12317 | } |
| 12318 | |
| 12319 | md_number_to_chars (p, value, fixP->fx_size); |
| 12320 | } |
| 12321 | \f |
| 12322 | const char * |
| 12323 | md_atof (int type, char *litP, int *sizeP) |
| 12324 | { |
| 12325 | /* This outputs the LITTLENUMs in REVERSE order; |
| 12326 | in accord with the bigendian 386. */ |
| 12327 | return ieee_md_atof (type, litP, sizeP, FALSE); |
| 12328 | } |
| 12329 | \f |
| 12330 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
| 12331 | |
| 12332 | static char * |
| 12333 | output_invalid (int c) |
| 12334 | { |
| 12335 | if (ISPRINT (c)) |
| 12336 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
| 12337 | "'%c'", c); |
| 12338 | else |
| 12339 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
| 12340 | "(0x%x)", (unsigned char) c); |
| 12341 | return output_invalid_buf; |
| 12342 | } |
| 12343 | |
| 12344 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
| 12345 | |
| 12346 | static const reg_entry * |
| 12347 | parse_real_register (char *reg_string, char **end_op) |
| 12348 | { |
| 12349 | char *s = reg_string; |
| 12350 | char *p; |
| 12351 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
| 12352 | const reg_entry *r; |
| 12353 | |
| 12354 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ |
| 12355 | if (*s == REGISTER_PREFIX) |
| 12356 | ++s; |
| 12357 | |
| 12358 | if (is_space_char (*s)) |
| 12359 | ++s; |
| 12360 | |
| 12361 | p = reg_name_given; |
| 12362 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
| 12363 | { |
| 12364 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) |
| 12365 | return (const reg_entry *) NULL; |
| 12366 | s++; |
| 12367 | } |
| 12368 | |
| 12369 | /* For naked regs, make sure that we are not dealing with an identifier. |
| 12370 | This prevents confusing an identifier like `eax_var' with register |
| 12371 | `eax'. */ |
| 12372 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) |
| 12373 | return (const reg_entry *) NULL; |
| 12374 | |
| 12375 | *end_op = s; |
| 12376 | |
| 12377 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); |
| 12378 | |
| 12379 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
| 12380 | if (r == i386_regtab /* %st is first entry of table */) |
| 12381 | { |
| 12382 | if (!cpu_arch_flags.bitfield.cpu8087 |
| 12383 | && !cpu_arch_flags.bitfield.cpu287 |
| 12384 | && !cpu_arch_flags.bitfield.cpu387) |
| 12385 | return (const reg_entry *) NULL; |
| 12386 | |
| 12387 | if (is_space_char (*s)) |
| 12388 | ++s; |
| 12389 | if (*s == '(') |
| 12390 | { |
| 12391 | ++s; |
| 12392 | if (is_space_char (*s)) |
| 12393 | ++s; |
| 12394 | if (*s >= '0' && *s <= '7') |
| 12395 | { |
| 12396 | int fpr = *s - '0'; |
| 12397 | ++s; |
| 12398 | if (is_space_char (*s)) |
| 12399 | ++s; |
| 12400 | if (*s == ')') |
| 12401 | { |
| 12402 | *end_op = s + 1; |
| 12403 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
| 12404 | know (r); |
| 12405 | return r + fpr; |
| 12406 | } |
| 12407 | } |
| 12408 | /* We have "%st(" then garbage. */ |
| 12409 | return (const reg_entry *) NULL; |
| 12410 | } |
| 12411 | } |
| 12412 | |
| 12413 | if (r == NULL || allow_pseudo_reg) |
| 12414 | return r; |
| 12415 | |
| 12416 | if (operand_type_all_zero (&r->reg_type)) |
| 12417 | return (const reg_entry *) NULL; |
| 12418 | |
| 12419 | if ((r->reg_type.bitfield.dword |
| 12420 | || (r->reg_type.bitfield.class == SReg && r->reg_num > 3) |
| 12421 | || r->reg_type.bitfield.class == RegCR |
| 12422 | || r->reg_type.bitfield.class == RegDR |
| 12423 | || r->reg_type.bitfield.class == RegTR) |
| 12424 | && !cpu_arch_flags.bitfield.cpui386) |
| 12425 | return (const reg_entry *) NULL; |
| 12426 | |
| 12427 | if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx) |
| 12428 | return (const reg_entry *) NULL; |
| 12429 | |
| 12430 | if (!cpu_arch_flags.bitfield.cpuavx512f) |
| 12431 | { |
| 12432 | if (r->reg_type.bitfield.zmmword |
| 12433 | || r->reg_type.bitfield.class == RegMask) |
| 12434 | return (const reg_entry *) NULL; |
| 12435 | |
| 12436 | if (!cpu_arch_flags.bitfield.cpuavx) |
| 12437 | { |
| 12438 | if (r->reg_type.bitfield.ymmword) |
| 12439 | return (const reg_entry *) NULL; |
| 12440 | |
| 12441 | if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword) |
| 12442 | return (const reg_entry *) NULL; |
| 12443 | } |
| 12444 | } |
| 12445 | |
| 12446 | if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx) |
| 12447 | return (const reg_entry *) NULL; |
| 12448 | |
| 12449 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
| 12450 | if (!allow_index_reg && r->reg_num == RegIZ) |
| 12451 | return (const reg_entry *) NULL; |
| 12452 | |
| 12453 | /* Upper 16 vector registers are only available with VREX in 64bit |
| 12454 | mode, and require EVEX encoding. */ |
| 12455 | if (r->reg_flags & RegVRex) |
| 12456 | { |
| 12457 | if (!cpu_arch_flags.bitfield.cpuavx512f |
| 12458 | || flag_code != CODE_64BIT) |
| 12459 | return (const reg_entry *) NULL; |
| 12460 | |
| 12461 | i.vec_encoding = vex_encoding_evex; |
| 12462 | } |
| 12463 | |
| 12464 | if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword) |
| 12465 | && (!cpu_arch_flags.bitfield.cpulm || r->reg_type.bitfield.class != RegCR) |
| 12466 | && flag_code != CODE_64BIT) |
| 12467 | return (const reg_entry *) NULL; |
| 12468 | |
| 12469 | if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat |
| 12470 | && !intel_syntax) |
| 12471 | return (const reg_entry *) NULL; |
| 12472 | |
| 12473 | return r; |
| 12474 | } |
| 12475 | |
| 12476 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
| 12477 | |
| 12478 | static const reg_entry * |
| 12479 | parse_register (char *reg_string, char **end_op) |
| 12480 | { |
| 12481 | const reg_entry *r; |
| 12482 | |
| 12483 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) |
| 12484 | r = parse_real_register (reg_string, end_op); |
| 12485 | else |
| 12486 | r = NULL; |
| 12487 | if (!r) |
| 12488 | { |
| 12489 | char *save = input_line_pointer; |
| 12490 | char c; |
| 12491 | symbolS *symbolP; |
| 12492 | |
| 12493 | input_line_pointer = reg_string; |
| 12494 | c = get_symbol_name (®_string); |
| 12495 | symbolP = symbol_find (reg_string); |
| 12496 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) |
| 12497 | { |
| 12498 | const expressionS *e = symbol_get_value_expression (symbolP); |
| 12499 | |
| 12500 | know (e->X_op == O_register); |
| 12501 | know (e->X_add_number >= 0 |
| 12502 | && (valueT) e->X_add_number < i386_regtab_size); |
| 12503 | r = i386_regtab + e->X_add_number; |
| 12504 | if ((r->reg_flags & RegVRex)) |
| 12505 | i.vec_encoding = vex_encoding_evex; |
| 12506 | *end_op = input_line_pointer; |
| 12507 | } |
| 12508 | *input_line_pointer = c; |
| 12509 | input_line_pointer = save; |
| 12510 | } |
| 12511 | return r; |
| 12512 | } |
| 12513 | |
| 12514 | int |
| 12515 | i386_parse_name (char *name, expressionS *e, char *nextcharP) |
| 12516 | { |
| 12517 | const reg_entry *r; |
| 12518 | char *end = input_line_pointer; |
| 12519 | |
| 12520 | *end = *nextcharP; |
| 12521 | r = parse_register (name, &input_line_pointer); |
| 12522 | if (r && end <= input_line_pointer) |
| 12523 | { |
| 12524 | *nextcharP = *input_line_pointer; |
| 12525 | *input_line_pointer = 0; |
| 12526 | e->X_op = O_register; |
| 12527 | e->X_add_number = r - i386_regtab; |
| 12528 | return 1; |
| 12529 | } |
| 12530 | input_line_pointer = end; |
| 12531 | *end = 0; |
| 12532 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
| 12533 | } |
| 12534 | |
| 12535 | void |
| 12536 | md_operand (expressionS *e) |
| 12537 | { |
| 12538 | char *end; |
| 12539 | const reg_entry *r; |
| 12540 | |
| 12541 | switch (*input_line_pointer) |
| 12542 | { |
| 12543 | case REGISTER_PREFIX: |
| 12544 | r = parse_real_register (input_line_pointer, &end); |
| 12545 | if (r) |
| 12546 | { |
| 12547 | e->X_op = O_register; |
| 12548 | e->X_add_number = r - i386_regtab; |
| 12549 | input_line_pointer = end; |
| 12550 | } |
| 12551 | break; |
| 12552 | |
| 12553 | case '[': |
| 12554 | gas_assert (intel_syntax); |
| 12555 | end = input_line_pointer++; |
| 12556 | expression (e); |
| 12557 | if (*input_line_pointer == ']') |
| 12558 | { |
| 12559 | ++input_line_pointer; |
| 12560 | e->X_op_symbol = make_expr_symbol (e); |
| 12561 | e->X_add_symbol = NULL; |
| 12562 | e->X_add_number = 0; |
| 12563 | e->X_op = O_index; |
| 12564 | } |
| 12565 | else |
| 12566 | { |
| 12567 | e->X_op = O_absent; |
| 12568 | input_line_pointer = end; |
| 12569 | } |
| 12570 | break; |
| 12571 | } |
| 12572 | } |
| 12573 | |
| 12574 | \f |
| 12575 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 12576 | const char *md_shortopts = "kVQ:sqnO::"; |
| 12577 | #else |
| 12578 | const char *md_shortopts = "qnO::"; |
| 12579 | #endif |
| 12580 | |
| 12581 | #define OPTION_32 (OPTION_MD_BASE + 0) |
| 12582 | #define OPTION_64 (OPTION_MD_BASE + 1) |
| 12583 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) |
| 12584 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
| 12585 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) |
| 12586 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
| 12587 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) |
| 12588 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) |
| 12589 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) |
| 12590 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9) |
| 12591 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
| 12592 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
| 12593 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
| 12594 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) |
| 12595 | #define OPTION_X32 (OPTION_MD_BASE + 14) |
| 12596 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
| 12597 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
| 12598 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) |
| 12599 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
| 12600 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
| 12601 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
| 12602 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
| 12603 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
| 12604 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) |
| 12605 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
| 12606 | #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25) |
| 12607 | #define OPTION_MVEXWIG (OPTION_MD_BASE + 26) |
| 12608 | #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27) |
| 12609 | #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28) |
| 12610 | #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29) |
| 12611 | #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30) |
| 12612 | #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31) |
| 12613 | #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32) |
| 12614 | #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33) |
| 12615 | |
| 12616 | struct option md_longopts[] = |
| 12617 | { |
| 12618 | {"32", no_argument, NULL, OPTION_32}, |
| 12619 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
| 12620 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
| 12621 | {"64", no_argument, NULL, OPTION_64}, |
| 12622 | #endif |
| 12623 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 12624 | {"x32", no_argument, NULL, OPTION_X32}, |
| 12625 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
| 12626 | {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE}, |
| 12627 | #endif |
| 12628 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
| 12629 | {"march", required_argument, NULL, OPTION_MARCH}, |
| 12630 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
| 12631 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
| 12632 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, |
| 12633 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, |
| 12634 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, |
| 12635 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
| 12636 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
| 12637 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
| 12638 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
| 12639 | {"mvexwig", required_argument, NULL, OPTION_MVEXWIG}, |
| 12640 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
| 12641 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
| 12642 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, |
| 12643 | # if defined (TE_PE) || defined (TE_PEP) |
| 12644 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, |
| 12645 | #endif |
| 12646 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
| 12647 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
| 12648 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
| 12649 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
| 12650 | {"malign-branch-boundary", required_argument, NULL, OPTION_MALIGN_BRANCH_BOUNDARY}, |
| 12651 | {"malign-branch-prefix-size", required_argument, NULL, OPTION_MALIGN_BRANCH_PREFIX_SIZE}, |
| 12652 | {"malign-branch", required_argument, NULL, OPTION_MALIGN_BRANCH}, |
| 12653 | {"mbranches-within-32B-boundaries", no_argument, NULL, OPTION_MBRANCHES_WITH_32B_BOUNDARIES}, |
| 12654 | {"mlfence-after-load", required_argument, NULL, OPTION_MLFENCE_AFTER_LOAD}, |
| 12655 | {"mlfence-before-indirect-branch", required_argument, NULL, |
| 12656 | OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH}, |
| 12657 | {"mlfence-before-ret", required_argument, NULL, OPTION_MLFENCE_BEFORE_RET}, |
| 12658 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
| 12659 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, |
| 12660 | {NULL, no_argument, NULL, 0} |
| 12661 | }; |
| 12662 | size_t md_longopts_size = sizeof (md_longopts); |
| 12663 | |
| 12664 | int |
| 12665 | md_parse_option (int c, const char *arg) |
| 12666 | { |
| 12667 | unsigned int j; |
| 12668 | char *arch, *next, *saved, *type; |
| 12669 | |
| 12670 | switch (c) |
| 12671 | { |
| 12672 | case 'n': |
| 12673 | optimize_align_code = 0; |
| 12674 | break; |
| 12675 | |
| 12676 | case 'q': |
| 12677 | quiet_warnings = 1; |
| 12678 | break; |
| 12679 | |
| 12680 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 12681 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
| 12682 | should be emitted or not. FIXME: Not implemented. */ |
| 12683 | case 'Q': |
| 12684 | if ((arg[0] != 'y' && arg[0] != 'n') || arg[1]) |
| 12685 | return 0; |
| 12686 | break; |
| 12687 | |
| 12688 | /* -V: SVR4 argument to print version ID. */ |
| 12689 | case 'V': |
| 12690 | print_version_id (); |
| 12691 | break; |
| 12692 | |
| 12693 | /* -k: Ignore for FreeBSD compatibility. */ |
| 12694 | case 'k': |
| 12695 | break; |
| 12696 | |
| 12697 | case 's': |
| 12698 | /* -s: On i386 Solaris, this tells the native assembler to use |
| 12699 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
| 12700 | break; |
| 12701 | |
| 12702 | case OPTION_MSHARED: |
| 12703 | shared = 1; |
| 12704 | break; |
| 12705 | |
| 12706 | case OPTION_X86_USED_NOTE: |
| 12707 | if (strcasecmp (arg, "yes") == 0) |
| 12708 | x86_used_note = 1; |
| 12709 | else if (strcasecmp (arg, "no") == 0) |
| 12710 | x86_used_note = 0; |
| 12711 | else |
| 12712 | as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg); |
| 12713 | break; |
| 12714 | |
| 12715 | |
| 12716 | #endif |
| 12717 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
| 12718 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
| 12719 | case OPTION_64: |
| 12720 | { |
| 12721 | const char **list, **l; |
| 12722 | |
| 12723 | list = bfd_target_list (); |
| 12724 | for (l = list; *l != NULL; l++) |
| 12725 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
| 12726 | || strcmp (*l, "coff-x86-64") == 0 |
| 12727 | || strcmp (*l, "pe-x86-64") == 0 |
| 12728 | || strcmp (*l, "pei-x86-64") == 0 |
| 12729 | || strcmp (*l, "mach-o-x86-64") == 0) |
| 12730 | { |
| 12731 | default_arch = "x86_64"; |
| 12732 | break; |
| 12733 | } |
| 12734 | if (*l == NULL) |
| 12735 | as_fatal (_("no compiled in support for x86_64")); |
| 12736 | free (list); |
| 12737 | } |
| 12738 | break; |
| 12739 | #endif |
| 12740 | |
| 12741 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 12742 | case OPTION_X32: |
| 12743 | if (IS_ELF) |
| 12744 | { |
| 12745 | const char **list, **l; |
| 12746 | |
| 12747 | list = bfd_target_list (); |
| 12748 | for (l = list; *l != NULL; l++) |
| 12749 | if (CONST_STRNEQ (*l, "elf32-x86-64")) |
| 12750 | { |
| 12751 | default_arch = "x86_64:32"; |
| 12752 | break; |
| 12753 | } |
| 12754 | if (*l == NULL) |
| 12755 | as_fatal (_("no compiled in support for 32bit x86_64")); |
| 12756 | free (list); |
| 12757 | } |
| 12758 | else |
| 12759 | as_fatal (_("32bit x86_64 is only supported for ELF")); |
| 12760 | break; |
| 12761 | #endif |
| 12762 | |
| 12763 | case OPTION_32: |
| 12764 | default_arch = "i386"; |
| 12765 | break; |
| 12766 | |
| 12767 | case OPTION_DIVIDE: |
| 12768 | #ifdef SVR4_COMMENT_CHARS |
| 12769 | { |
| 12770 | char *n, *t; |
| 12771 | const char *s; |
| 12772 | |
| 12773 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
| 12774 | t = n; |
| 12775 | for (s = i386_comment_chars; *s != '\0'; s++) |
| 12776 | if (*s != '/') |
| 12777 | *t++ = *s; |
| 12778 | *t = '\0'; |
| 12779 | i386_comment_chars = n; |
| 12780 | } |
| 12781 | #endif |
| 12782 | break; |
| 12783 | |
| 12784 | case OPTION_MARCH: |
| 12785 | saved = xstrdup (arg); |
| 12786 | arch = saved; |
| 12787 | /* Allow -march=+nosse. */ |
| 12788 | if (*arch == '+') |
| 12789 | arch++; |
| 12790 | do |
| 12791 | { |
| 12792 | if (*arch == '.') |
| 12793 | as_fatal (_("invalid -march= option: `%s'"), arg); |
| 12794 | next = strchr (arch, '+'); |
| 12795 | if (next) |
| 12796 | *next++ = '\0'; |
| 12797 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
| 12798 | { |
| 12799 | if (strcmp (arch, cpu_arch [j].name) == 0) |
| 12800 | { |
| 12801 | /* Processor. */ |
| 12802 | if (! cpu_arch[j].flags.bitfield.cpui386) |
| 12803 | continue; |
| 12804 | |
| 12805 | cpu_arch_name = cpu_arch[j].name; |
| 12806 | cpu_sub_arch_name = NULL; |
| 12807 | cpu_arch_flags = cpu_arch[j].flags; |
| 12808 | cpu_arch_isa = cpu_arch[j].type; |
| 12809 | cpu_arch_isa_flags = cpu_arch[j].flags; |
| 12810 | if (!cpu_arch_tune_set) |
| 12811 | { |
| 12812 | cpu_arch_tune = cpu_arch_isa; |
| 12813 | cpu_arch_tune_flags = cpu_arch_isa_flags; |
| 12814 | } |
| 12815 | break; |
| 12816 | } |
| 12817 | else if (*cpu_arch [j].name == '.' |
| 12818 | && strcmp (arch, cpu_arch [j].name + 1) == 0) |
| 12819 | { |
| 12820 | /* ISA extension. */ |
| 12821 | i386_cpu_flags flags; |
| 12822 | |
| 12823 | flags = cpu_flags_or (cpu_arch_flags, |
| 12824 | cpu_arch[j].flags); |
| 12825 | |
| 12826 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
| 12827 | { |
| 12828 | if (cpu_sub_arch_name) |
| 12829 | { |
| 12830 | char *name = cpu_sub_arch_name; |
| 12831 | cpu_sub_arch_name = concat (name, |
| 12832 | cpu_arch[j].name, |
| 12833 | (const char *) NULL); |
| 12834 | free (name); |
| 12835 | } |
| 12836 | else |
| 12837 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
| 12838 | cpu_arch_flags = flags; |
| 12839 | cpu_arch_isa_flags = flags; |
| 12840 | } |
| 12841 | else |
| 12842 | cpu_arch_isa_flags |
| 12843 | = cpu_flags_or (cpu_arch_isa_flags, |
| 12844 | cpu_arch[j].flags); |
| 12845 | break; |
| 12846 | } |
| 12847 | } |
| 12848 | |
| 12849 | if (j >= ARRAY_SIZE (cpu_arch)) |
| 12850 | { |
| 12851 | /* Disable an ISA extension. */ |
| 12852 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
| 12853 | if (strcmp (arch, cpu_noarch [j].name) == 0) |
| 12854 | { |
| 12855 | i386_cpu_flags flags; |
| 12856 | |
| 12857 | flags = cpu_flags_and_not (cpu_arch_flags, |
| 12858 | cpu_noarch[j].flags); |
| 12859 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
| 12860 | { |
| 12861 | if (cpu_sub_arch_name) |
| 12862 | { |
| 12863 | char *name = cpu_sub_arch_name; |
| 12864 | cpu_sub_arch_name = concat (arch, |
| 12865 | (const char *) NULL); |
| 12866 | free (name); |
| 12867 | } |
| 12868 | else |
| 12869 | cpu_sub_arch_name = xstrdup (arch); |
| 12870 | cpu_arch_flags = flags; |
| 12871 | cpu_arch_isa_flags = flags; |
| 12872 | } |
| 12873 | break; |
| 12874 | } |
| 12875 | |
| 12876 | if (j >= ARRAY_SIZE (cpu_noarch)) |
| 12877 | j = ARRAY_SIZE (cpu_arch); |
| 12878 | } |
| 12879 | |
| 12880 | if (j >= ARRAY_SIZE (cpu_arch)) |
| 12881 | as_fatal (_("invalid -march= option: `%s'"), arg); |
| 12882 | |
| 12883 | arch = next; |
| 12884 | } |
| 12885 | while (next != NULL); |
| 12886 | free (saved); |
| 12887 | break; |
| 12888 | |
| 12889 | case OPTION_MTUNE: |
| 12890 | if (*arg == '.') |
| 12891 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
| 12892 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
| 12893 | { |
| 12894 | if (strcmp (arg, cpu_arch [j].name) == 0) |
| 12895 | { |
| 12896 | cpu_arch_tune_set = 1; |
| 12897 | cpu_arch_tune = cpu_arch [j].type; |
| 12898 | cpu_arch_tune_flags = cpu_arch[j].flags; |
| 12899 | break; |
| 12900 | } |
| 12901 | } |
| 12902 | if (j >= ARRAY_SIZE (cpu_arch)) |
| 12903 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
| 12904 | break; |
| 12905 | |
| 12906 | case OPTION_MMNEMONIC: |
| 12907 | if (strcasecmp (arg, "att") == 0) |
| 12908 | intel_mnemonic = 0; |
| 12909 | else if (strcasecmp (arg, "intel") == 0) |
| 12910 | intel_mnemonic = 1; |
| 12911 | else |
| 12912 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
| 12913 | break; |
| 12914 | |
| 12915 | case OPTION_MSYNTAX: |
| 12916 | if (strcasecmp (arg, "att") == 0) |
| 12917 | intel_syntax = 0; |
| 12918 | else if (strcasecmp (arg, "intel") == 0) |
| 12919 | intel_syntax = 1; |
| 12920 | else |
| 12921 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
| 12922 | break; |
| 12923 | |
| 12924 | case OPTION_MINDEX_REG: |
| 12925 | allow_index_reg = 1; |
| 12926 | break; |
| 12927 | |
| 12928 | case OPTION_MNAKED_REG: |
| 12929 | allow_naked_reg = 1; |
| 12930 | break; |
| 12931 | |
| 12932 | case OPTION_MSSE2AVX: |
| 12933 | sse2avx = 1; |
| 12934 | break; |
| 12935 | |
| 12936 | case OPTION_MSSE_CHECK: |
| 12937 | if (strcasecmp (arg, "error") == 0) |
| 12938 | sse_check = check_error; |
| 12939 | else if (strcasecmp (arg, "warning") == 0) |
| 12940 | sse_check = check_warning; |
| 12941 | else if (strcasecmp (arg, "none") == 0) |
| 12942 | sse_check = check_none; |
| 12943 | else |
| 12944 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
| 12945 | break; |
| 12946 | |
| 12947 | case OPTION_MOPERAND_CHECK: |
| 12948 | if (strcasecmp (arg, "error") == 0) |
| 12949 | operand_check = check_error; |
| 12950 | else if (strcasecmp (arg, "warning") == 0) |
| 12951 | operand_check = check_warning; |
| 12952 | else if (strcasecmp (arg, "none") == 0) |
| 12953 | operand_check = check_none; |
| 12954 | else |
| 12955 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); |
| 12956 | break; |
| 12957 | |
| 12958 | case OPTION_MAVXSCALAR: |
| 12959 | if (strcasecmp (arg, "128") == 0) |
| 12960 | avxscalar = vex128; |
| 12961 | else if (strcasecmp (arg, "256") == 0) |
| 12962 | avxscalar = vex256; |
| 12963 | else |
| 12964 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
| 12965 | break; |
| 12966 | |
| 12967 | case OPTION_MVEXWIG: |
| 12968 | if (strcmp (arg, "0") == 0) |
| 12969 | vexwig = vexw0; |
| 12970 | else if (strcmp (arg, "1") == 0) |
| 12971 | vexwig = vexw1; |
| 12972 | else |
| 12973 | as_fatal (_("invalid -mvexwig= option: `%s'"), arg); |
| 12974 | break; |
| 12975 | |
| 12976 | case OPTION_MADD_BND_PREFIX: |
| 12977 | add_bnd_prefix = 1; |
| 12978 | break; |
| 12979 | |
| 12980 | case OPTION_MEVEXLIG: |
| 12981 | if (strcmp (arg, "128") == 0) |
| 12982 | evexlig = evexl128; |
| 12983 | else if (strcmp (arg, "256") == 0) |
| 12984 | evexlig = evexl256; |
| 12985 | else if (strcmp (arg, "512") == 0) |
| 12986 | evexlig = evexl512; |
| 12987 | else |
| 12988 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); |
| 12989 | break; |
| 12990 | |
| 12991 | case OPTION_MEVEXRCIG: |
| 12992 | if (strcmp (arg, "rne") == 0) |
| 12993 | evexrcig = rne; |
| 12994 | else if (strcmp (arg, "rd") == 0) |
| 12995 | evexrcig = rd; |
| 12996 | else if (strcmp (arg, "ru") == 0) |
| 12997 | evexrcig = ru; |
| 12998 | else if (strcmp (arg, "rz") == 0) |
| 12999 | evexrcig = rz; |
| 13000 | else |
| 13001 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); |
| 13002 | break; |
| 13003 | |
| 13004 | case OPTION_MEVEXWIG: |
| 13005 | if (strcmp (arg, "0") == 0) |
| 13006 | evexwig = evexw0; |
| 13007 | else if (strcmp (arg, "1") == 0) |
| 13008 | evexwig = evexw1; |
| 13009 | else |
| 13010 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); |
| 13011 | break; |
| 13012 | |
| 13013 | # if defined (TE_PE) || defined (TE_PEP) |
| 13014 | case OPTION_MBIG_OBJ: |
| 13015 | use_big_obj = 1; |
| 13016 | break; |
| 13017 | #endif |
| 13018 | |
| 13019 | case OPTION_MOMIT_LOCK_PREFIX: |
| 13020 | if (strcasecmp (arg, "yes") == 0) |
| 13021 | omit_lock_prefix = 1; |
| 13022 | else if (strcasecmp (arg, "no") == 0) |
| 13023 | omit_lock_prefix = 0; |
| 13024 | else |
| 13025 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); |
| 13026 | break; |
| 13027 | |
| 13028 | case OPTION_MFENCE_AS_LOCK_ADD: |
| 13029 | if (strcasecmp (arg, "yes") == 0) |
| 13030 | avoid_fence = 1; |
| 13031 | else if (strcasecmp (arg, "no") == 0) |
| 13032 | avoid_fence = 0; |
| 13033 | else |
| 13034 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); |
| 13035 | break; |
| 13036 | |
| 13037 | case OPTION_MLFENCE_AFTER_LOAD: |
| 13038 | if (strcasecmp (arg, "yes") == 0) |
| 13039 | lfence_after_load = 1; |
| 13040 | else if (strcasecmp (arg, "no") == 0) |
| 13041 | lfence_after_load = 0; |
| 13042 | else |
| 13043 | as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg); |
| 13044 | break; |
| 13045 | |
| 13046 | case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH: |
| 13047 | if (strcasecmp (arg, "all") == 0) |
| 13048 | { |
| 13049 | lfence_before_indirect_branch = lfence_branch_all; |
| 13050 | if (lfence_before_ret == lfence_before_ret_none) |
| 13051 | lfence_before_ret = lfence_before_ret_shl; |
| 13052 | } |
| 13053 | else if (strcasecmp (arg, "memory") == 0) |
| 13054 | lfence_before_indirect_branch = lfence_branch_memory; |
| 13055 | else if (strcasecmp (arg, "register") == 0) |
| 13056 | lfence_before_indirect_branch = lfence_branch_register; |
| 13057 | else if (strcasecmp (arg, "none") == 0) |
| 13058 | lfence_before_indirect_branch = lfence_branch_none; |
| 13059 | else |
| 13060 | as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"), |
| 13061 | arg); |
| 13062 | break; |
| 13063 | |
| 13064 | case OPTION_MLFENCE_BEFORE_RET: |
| 13065 | if (strcasecmp (arg, "or") == 0) |
| 13066 | lfence_before_ret = lfence_before_ret_or; |
| 13067 | else if (strcasecmp (arg, "not") == 0) |
| 13068 | lfence_before_ret = lfence_before_ret_not; |
| 13069 | else if (strcasecmp (arg, "shl") == 0 || strcasecmp (arg, "yes") == 0) |
| 13070 | lfence_before_ret = lfence_before_ret_shl; |
| 13071 | else if (strcasecmp (arg, "none") == 0) |
| 13072 | lfence_before_ret = lfence_before_ret_none; |
| 13073 | else |
| 13074 | as_fatal (_("invalid -mlfence-before-ret= option: `%s'"), |
| 13075 | arg); |
| 13076 | break; |
| 13077 | |
| 13078 | case OPTION_MRELAX_RELOCATIONS: |
| 13079 | if (strcasecmp (arg, "yes") == 0) |
| 13080 | generate_relax_relocations = 1; |
| 13081 | else if (strcasecmp (arg, "no") == 0) |
| 13082 | generate_relax_relocations = 0; |
| 13083 | else |
| 13084 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); |
| 13085 | break; |
| 13086 | |
| 13087 | case OPTION_MALIGN_BRANCH_BOUNDARY: |
| 13088 | { |
| 13089 | char *end; |
| 13090 | long int align = strtoul (arg, &end, 0); |
| 13091 | if (*end == '\0') |
| 13092 | { |
| 13093 | if (align == 0) |
| 13094 | { |
| 13095 | align_branch_power = 0; |
| 13096 | break; |
| 13097 | } |
| 13098 | else if (align >= 16) |
| 13099 | { |
| 13100 | int align_power; |
| 13101 | for (align_power = 0; |
| 13102 | (align & 1) == 0; |
| 13103 | align >>= 1, align_power++) |
| 13104 | continue; |
| 13105 | /* Limit alignment power to 31. */ |
| 13106 | if (align == 1 && align_power < 32) |
| 13107 | { |
| 13108 | align_branch_power = align_power; |
| 13109 | break; |
| 13110 | } |
| 13111 | } |
| 13112 | } |
| 13113 | as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg); |
| 13114 | } |
| 13115 | break; |
| 13116 | |
| 13117 | case OPTION_MALIGN_BRANCH_PREFIX_SIZE: |
| 13118 | { |
| 13119 | char *end; |
| 13120 | int align = strtoul (arg, &end, 0); |
| 13121 | /* Some processors only support 5 prefixes. */ |
| 13122 | if (*end == '\0' && align >= 0 && align < 6) |
| 13123 | { |
| 13124 | align_branch_prefix_size = align; |
| 13125 | break; |
| 13126 | } |
| 13127 | as_fatal (_("invalid -malign-branch-prefix-size= value: %s"), |
| 13128 | arg); |
| 13129 | } |
| 13130 | break; |
| 13131 | |
| 13132 | case OPTION_MALIGN_BRANCH: |
| 13133 | align_branch = 0; |
| 13134 | saved = xstrdup (arg); |
| 13135 | type = saved; |
| 13136 | do |
| 13137 | { |
| 13138 | next = strchr (type, '+'); |
| 13139 | if (next) |
| 13140 | *next++ = '\0'; |
| 13141 | if (strcasecmp (type, "jcc") == 0) |
| 13142 | align_branch |= align_branch_jcc_bit; |
| 13143 | else if (strcasecmp (type, "fused") == 0) |
| 13144 | align_branch |= align_branch_fused_bit; |
| 13145 | else if (strcasecmp (type, "jmp") == 0) |
| 13146 | align_branch |= align_branch_jmp_bit; |
| 13147 | else if (strcasecmp (type, "call") == 0) |
| 13148 | align_branch |= align_branch_call_bit; |
| 13149 | else if (strcasecmp (type, "ret") == 0) |
| 13150 | align_branch |= align_branch_ret_bit; |
| 13151 | else if (strcasecmp (type, "indirect") == 0) |
| 13152 | align_branch |= align_branch_indirect_bit; |
| 13153 | else |
| 13154 | as_fatal (_("invalid -malign-branch= option: `%s'"), arg); |
| 13155 | type = next; |
| 13156 | } |
| 13157 | while (next != NULL); |
| 13158 | free (saved); |
| 13159 | break; |
| 13160 | |
| 13161 | case OPTION_MBRANCHES_WITH_32B_BOUNDARIES: |
| 13162 | align_branch_power = 5; |
| 13163 | align_branch_prefix_size = 5; |
| 13164 | align_branch = (align_branch_jcc_bit |
| 13165 | | align_branch_fused_bit |
| 13166 | | align_branch_jmp_bit); |
| 13167 | break; |
| 13168 | |
| 13169 | case OPTION_MAMD64: |
| 13170 | isa64 = amd64; |
| 13171 | break; |
| 13172 | |
| 13173 | case OPTION_MINTEL64: |
| 13174 | isa64 = intel64; |
| 13175 | break; |
| 13176 | |
| 13177 | case 'O': |
| 13178 | if (arg == NULL) |
| 13179 | { |
| 13180 | optimize = 1; |
| 13181 | /* Turn off -Os. */ |
| 13182 | optimize_for_space = 0; |
| 13183 | } |
| 13184 | else if (*arg == 's') |
| 13185 | { |
| 13186 | optimize_for_space = 1; |
| 13187 | /* Turn on all encoding optimizations. */ |
| 13188 | optimize = INT_MAX; |
| 13189 | } |
| 13190 | else |
| 13191 | { |
| 13192 | optimize = atoi (arg); |
| 13193 | /* Turn off -Os. */ |
| 13194 | optimize_for_space = 0; |
| 13195 | } |
| 13196 | break; |
| 13197 | |
| 13198 | default: |
| 13199 | return 0; |
| 13200 | } |
| 13201 | return 1; |
| 13202 | } |
| 13203 | |
| 13204 | #define MESSAGE_TEMPLATE \ |
| 13205 | " " |
| 13206 | |
| 13207 | static char * |
| 13208 | output_message (FILE *stream, char *p, char *message, char *start, |
| 13209 | int *left_p, const char *name, int len) |
| 13210 | { |
| 13211 | int size = sizeof (MESSAGE_TEMPLATE); |
| 13212 | int left = *left_p; |
| 13213 | |
| 13214 | /* Reserve 2 spaces for ", " or ",\0" */ |
| 13215 | left -= len + 2; |
| 13216 | |
| 13217 | /* Check if there is any room. */ |
| 13218 | if (left >= 0) |
| 13219 | { |
| 13220 | if (p != start) |
| 13221 | { |
| 13222 | *p++ = ','; |
| 13223 | *p++ = ' '; |
| 13224 | } |
| 13225 | p = mempcpy (p, name, len); |
| 13226 | } |
| 13227 | else |
| 13228 | { |
| 13229 | /* Output the current message now and start a new one. */ |
| 13230 | *p++ = ','; |
| 13231 | *p = '\0'; |
| 13232 | fprintf (stream, "%s\n", message); |
| 13233 | p = start; |
| 13234 | left = size - (start - message) - len - 2; |
| 13235 | |
| 13236 | gas_assert (left >= 0); |
| 13237 | |
| 13238 | p = mempcpy (p, name, len); |
| 13239 | } |
| 13240 | |
| 13241 | *left_p = left; |
| 13242 | return p; |
| 13243 | } |
| 13244 | |
| 13245 | static void |
| 13246 | show_arch (FILE *stream, int ext, int check) |
| 13247 | { |
| 13248 | static char message[] = MESSAGE_TEMPLATE; |
| 13249 | char *start = message + 27; |
| 13250 | char *p; |
| 13251 | int size = sizeof (MESSAGE_TEMPLATE); |
| 13252 | int left; |
| 13253 | const char *name; |
| 13254 | int len; |
| 13255 | unsigned int j; |
| 13256 | |
| 13257 | p = start; |
| 13258 | left = size - (start - message); |
| 13259 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
| 13260 | { |
| 13261 | /* Should it be skipped? */ |
| 13262 | if (cpu_arch [j].skip) |
| 13263 | continue; |
| 13264 | |
| 13265 | name = cpu_arch [j].name; |
| 13266 | len = cpu_arch [j].len; |
| 13267 | if (*name == '.') |
| 13268 | { |
| 13269 | /* It is an extension. Skip if we aren't asked to show it. */ |
| 13270 | if (ext) |
| 13271 | { |
| 13272 | name++; |
| 13273 | len--; |
| 13274 | } |
| 13275 | else |
| 13276 | continue; |
| 13277 | } |
| 13278 | else if (ext) |
| 13279 | { |
| 13280 | /* It is an processor. Skip if we show only extension. */ |
| 13281 | continue; |
| 13282 | } |
| 13283 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
| 13284 | { |
| 13285 | /* It is an impossible processor - skip. */ |
| 13286 | continue; |
| 13287 | } |
| 13288 | |
| 13289 | p = output_message (stream, p, message, start, &left, name, len); |
| 13290 | } |
| 13291 | |
| 13292 | /* Display disabled extensions. */ |
| 13293 | if (ext) |
| 13294 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
| 13295 | { |
| 13296 | name = cpu_noarch [j].name; |
| 13297 | len = cpu_noarch [j].len; |
| 13298 | p = output_message (stream, p, message, start, &left, name, |
| 13299 | len); |
| 13300 | } |
| 13301 | |
| 13302 | *p = '\0'; |
| 13303 | fprintf (stream, "%s\n", message); |
| 13304 | } |
| 13305 | |
| 13306 | void |
| 13307 | md_show_usage (FILE *stream) |
| 13308 | { |
| 13309 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 13310 | fprintf (stream, _("\ |
| 13311 | -Qy, -Qn ignored\n\ |
| 13312 | -V print assembler version number\n\ |
| 13313 | -k ignored\n")); |
| 13314 | #endif |
| 13315 | fprintf (stream, _("\ |
| 13316 | -n Do not optimize code alignment\n\ |
| 13317 | -q quieten some warnings\n")); |
| 13318 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 13319 | fprintf (stream, _("\ |
| 13320 | -s ignored\n")); |
| 13321 | #endif |
| 13322 | #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
| 13323 | || defined (TE_PE) || defined (TE_PEP)) |
| 13324 | fprintf (stream, _("\ |
| 13325 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
| 13326 | #endif |
| 13327 | #ifdef SVR4_COMMENT_CHARS |
| 13328 | fprintf (stream, _("\ |
| 13329 | --divide do not treat `/' as a comment character\n")); |
| 13330 | #else |
| 13331 | fprintf (stream, _("\ |
| 13332 | --divide ignored\n")); |
| 13333 | #endif |
| 13334 | fprintf (stream, _("\ |
| 13335 | -march=CPU[,+EXTENSION...]\n\ |
| 13336 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
| 13337 | show_arch (stream, 0, 1); |
| 13338 | fprintf (stream, _("\ |
| 13339 | EXTENSION is combination of:\n")); |
| 13340 | show_arch (stream, 1, 0); |
| 13341 | fprintf (stream, _("\ |
| 13342 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
| 13343 | show_arch (stream, 0, 0); |
| 13344 | fprintf (stream, _("\ |
| 13345 | -msse2avx encode SSE instructions with VEX prefix\n")); |
| 13346 | fprintf (stream, _("\ |
| 13347 | -msse-check=[none|error|warning] (default: warning)\n\ |
| 13348 | check SSE instructions\n")); |
| 13349 | fprintf (stream, _("\ |
| 13350 | -moperand-check=[none|error|warning] (default: warning)\n\ |
| 13351 | check operand combinations for validity\n")); |
| 13352 | fprintf (stream, _("\ |
| 13353 | -mavxscalar=[128|256] (default: 128)\n\ |
| 13354 | encode scalar AVX instructions with specific vector\n\ |
| 13355 | length\n")); |
| 13356 | fprintf (stream, _("\ |
| 13357 | -mvexwig=[0|1] (default: 0)\n\ |
| 13358 | encode VEX instructions with specific VEX.W value\n\ |
| 13359 | for VEX.W bit ignored instructions\n")); |
| 13360 | fprintf (stream, _("\ |
| 13361 | -mevexlig=[128|256|512] (default: 128)\n\ |
| 13362 | encode scalar EVEX instructions with specific vector\n\ |
| 13363 | length\n")); |
| 13364 | fprintf (stream, _("\ |
| 13365 | -mevexwig=[0|1] (default: 0)\n\ |
| 13366 | encode EVEX instructions with specific EVEX.W value\n\ |
| 13367 | for EVEX.W bit ignored instructions\n")); |
| 13368 | fprintf (stream, _("\ |
| 13369 | -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\ |
| 13370 | encode EVEX instructions with specific EVEX.RC value\n\ |
| 13371 | for SAE-only ignored instructions\n")); |
| 13372 | fprintf (stream, _("\ |
| 13373 | -mmnemonic=[att|intel] ")); |
| 13374 | if (SYSV386_COMPAT) |
| 13375 | fprintf (stream, _("(default: att)\n")); |
| 13376 | else |
| 13377 | fprintf (stream, _("(default: intel)\n")); |
| 13378 | fprintf (stream, _("\ |
| 13379 | use AT&T/Intel mnemonic\n")); |
| 13380 | fprintf (stream, _("\ |
| 13381 | -msyntax=[att|intel] (default: att)\n\ |
| 13382 | use AT&T/Intel syntax\n")); |
| 13383 | fprintf (stream, _("\ |
| 13384 | -mindex-reg support pseudo index registers\n")); |
| 13385 | fprintf (stream, _("\ |
| 13386 | -mnaked-reg don't require `%%' prefix for registers\n")); |
| 13387 | fprintf (stream, _("\ |
| 13388 | -madd-bnd-prefix add BND prefix for all valid branches\n")); |
| 13389 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 13390 | fprintf (stream, _("\ |
| 13391 | -mshared disable branch optimization for shared code\n")); |
| 13392 | fprintf (stream, _("\ |
| 13393 | -mx86-used-note=[no|yes] ")); |
| 13394 | if (DEFAULT_X86_USED_NOTE) |
| 13395 | fprintf (stream, _("(default: yes)\n")); |
| 13396 | else |
| 13397 | fprintf (stream, _("(default: no)\n")); |
| 13398 | fprintf (stream, _("\ |
| 13399 | generate x86 used ISA and feature properties\n")); |
| 13400 | #endif |
| 13401 | #if defined (TE_PE) || defined (TE_PEP) |
| 13402 | fprintf (stream, _("\ |
| 13403 | -mbig-obj generate big object files\n")); |
| 13404 | #endif |
| 13405 | fprintf (stream, _("\ |
| 13406 | -momit-lock-prefix=[no|yes] (default: no)\n\ |
| 13407 | strip all lock prefixes\n")); |
| 13408 | fprintf (stream, _("\ |
| 13409 | -mfence-as-lock-add=[no|yes] (default: no)\n\ |
| 13410 | encode lfence, mfence and sfence as\n\ |
| 13411 | lock addl $0x0, (%%{re}sp)\n")); |
| 13412 | fprintf (stream, _("\ |
| 13413 | -mrelax-relocations=[no|yes] ")); |
| 13414 | if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS) |
| 13415 | fprintf (stream, _("(default: yes)\n")); |
| 13416 | else |
| 13417 | fprintf (stream, _("(default: no)\n")); |
| 13418 | fprintf (stream, _("\ |
| 13419 | generate relax relocations\n")); |
| 13420 | fprintf (stream, _("\ |
| 13421 | -malign-branch-boundary=NUM (default: 0)\n\ |
| 13422 | align branches within NUM byte boundary\n")); |
| 13423 | fprintf (stream, _("\ |
| 13424 | -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\ |
| 13425 | TYPE is combination of jcc, fused, jmp, call, ret,\n\ |
| 13426 | indirect\n\ |
| 13427 | specify types of branches to align\n")); |
| 13428 | fprintf (stream, _("\ |
| 13429 | -malign-branch-prefix-size=NUM (default: 5)\n\ |
| 13430 | align branches with NUM prefixes per instruction\n")); |
| 13431 | fprintf (stream, _("\ |
| 13432 | -mbranches-within-32B-boundaries\n\ |
| 13433 | align branches within 32 byte boundary\n")); |
| 13434 | fprintf (stream, _("\ |
| 13435 | -mlfence-after-load=[no|yes] (default: no)\n\ |
| 13436 | generate lfence after load\n")); |
| 13437 | fprintf (stream, _("\ |
| 13438 | -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\ |
| 13439 | generate lfence before indirect near branch\n")); |
| 13440 | fprintf (stream, _("\ |
| 13441 | -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\ |
| 13442 | generate lfence before ret\n")); |
| 13443 | fprintf (stream, _("\ |
| 13444 | -mamd64 accept only AMD64 ISA [default]\n")); |
| 13445 | fprintf (stream, _("\ |
| 13446 | -mintel64 accept only Intel64 ISA\n")); |
| 13447 | } |
| 13448 | |
| 13449 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
| 13450 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
| 13451 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
| 13452 | |
| 13453 | /* Pick the target format to use. */ |
| 13454 | |
| 13455 | const char * |
| 13456 | i386_target_format (void) |
| 13457 | { |
| 13458 | if (!strncmp (default_arch, "x86_64", 6)) |
| 13459 | { |
| 13460 | update_code_flag (CODE_64BIT, 1); |
| 13461 | if (default_arch[6] == '\0') |
| 13462 | x86_elf_abi = X86_64_ABI; |
| 13463 | else |
| 13464 | x86_elf_abi = X86_64_X32_ABI; |
| 13465 | } |
| 13466 | else if (!strcmp (default_arch, "i386")) |
| 13467 | update_code_flag (CODE_32BIT, 1); |
| 13468 | else if (!strcmp (default_arch, "iamcu")) |
| 13469 | { |
| 13470 | update_code_flag (CODE_32BIT, 1); |
| 13471 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) |
| 13472 | { |
| 13473 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; |
| 13474 | cpu_arch_name = "iamcu"; |
| 13475 | cpu_sub_arch_name = NULL; |
| 13476 | cpu_arch_flags = iamcu_flags; |
| 13477 | cpu_arch_isa = PROCESSOR_IAMCU; |
| 13478 | cpu_arch_isa_flags = iamcu_flags; |
| 13479 | if (!cpu_arch_tune_set) |
| 13480 | { |
| 13481 | cpu_arch_tune = cpu_arch_isa; |
| 13482 | cpu_arch_tune_flags = cpu_arch_isa_flags; |
| 13483 | } |
| 13484 | } |
| 13485 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
| 13486 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
| 13487 | cpu_arch_name); |
| 13488 | } |
| 13489 | else |
| 13490 | as_fatal (_("unknown architecture")); |
| 13491 | |
| 13492 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) |
| 13493 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; |
| 13494 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) |
| 13495 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; |
| 13496 | |
| 13497 | switch (OUTPUT_FLAVOR) |
| 13498 | { |
| 13499 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
| 13500 | case bfd_target_aout_flavour: |
| 13501 | return AOUT_TARGET_FORMAT; |
| 13502 | #endif |
| 13503 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
| 13504 | # if defined (TE_PE) || defined (TE_PEP) |
| 13505 | case bfd_target_coff_flavour: |
| 13506 | if (flag_code == CODE_64BIT) |
| 13507 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; |
| 13508 | else |
| 13509 | return use_big_obj ? "pe-bigobj-i386" : "pe-i386"; |
| 13510 | # elif defined (TE_GO32) |
| 13511 | case bfd_target_coff_flavour: |
| 13512 | return "coff-go32"; |
| 13513 | # else |
| 13514 | case bfd_target_coff_flavour: |
| 13515 | return "coff-i386"; |
| 13516 | # endif |
| 13517 | #endif |
| 13518 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
| 13519 | case bfd_target_elf_flavour: |
| 13520 | { |
| 13521 | const char *format; |
| 13522 | |
| 13523 | switch (x86_elf_abi) |
| 13524 | { |
| 13525 | default: |
| 13526 | format = ELF_TARGET_FORMAT; |
| 13527 | #ifndef TE_SOLARIS |
| 13528 | tls_get_addr = "___tls_get_addr"; |
| 13529 | #endif |
| 13530 | break; |
| 13531 | case X86_64_ABI: |
| 13532 | use_rela_relocations = 1; |
| 13533 | object_64bit = 1; |
| 13534 | #ifndef TE_SOLARIS |
| 13535 | tls_get_addr = "__tls_get_addr"; |
| 13536 | #endif |
| 13537 | format = ELF_TARGET_FORMAT64; |
| 13538 | break; |
| 13539 | case X86_64_X32_ABI: |
| 13540 | use_rela_relocations = 1; |
| 13541 | object_64bit = 1; |
| 13542 | #ifndef TE_SOLARIS |
| 13543 | tls_get_addr = "__tls_get_addr"; |
| 13544 | #endif |
| 13545 | disallow_64bit_reloc = 1; |
| 13546 | format = ELF_TARGET_FORMAT32; |
| 13547 | break; |
| 13548 | } |
| 13549 | if (cpu_arch_isa == PROCESSOR_L1OM) |
| 13550 | { |
| 13551 | if (x86_elf_abi != X86_64_ABI) |
| 13552 | as_fatal (_("Intel L1OM is 64bit only")); |
| 13553 | return ELF_TARGET_L1OM_FORMAT; |
| 13554 | } |
| 13555 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
| 13556 | { |
| 13557 | if (x86_elf_abi != X86_64_ABI) |
| 13558 | as_fatal (_("Intel K1OM is 64bit only")); |
| 13559 | return ELF_TARGET_K1OM_FORMAT; |
| 13560 | } |
| 13561 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
| 13562 | { |
| 13563 | if (x86_elf_abi != I386_ABI) |
| 13564 | as_fatal (_("Intel MCU is 32bit only")); |
| 13565 | return ELF_TARGET_IAMCU_FORMAT; |
| 13566 | } |
| 13567 | else |
| 13568 | return format; |
| 13569 | } |
| 13570 | #endif |
| 13571 | #if defined (OBJ_MACH_O) |
| 13572 | case bfd_target_mach_o_flavour: |
| 13573 | if (flag_code == CODE_64BIT) |
| 13574 | { |
| 13575 | use_rela_relocations = 1; |
| 13576 | object_64bit = 1; |
| 13577 | return "mach-o-x86-64"; |
| 13578 | } |
| 13579 | else |
| 13580 | return "mach-o-i386"; |
| 13581 | #endif |
| 13582 | default: |
| 13583 | abort (); |
| 13584 | return NULL; |
| 13585 | } |
| 13586 | } |
| 13587 | |
| 13588 | #endif /* OBJ_MAYBE_ more than one */ |
| 13589 | \f |
| 13590 | symbolS * |
| 13591 | md_undefined_symbol (char *name) |
| 13592 | { |
| 13593 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
| 13594 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] |
| 13595 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] |
| 13596 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) |
| 13597 | { |
| 13598 | if (!GOT_symbol) |
| 13599 | { |
| 13600 | if (symbol_find (name)) |
| 13601 | as_bad (_("GOT already in symbol table")); |
| 13602 | GOT_symbol = symbol_new (name, undefined_section, |
| 13603 | (valueT) 0, &zero_address_frag); |
| 13604 | }; |
| 13605 | return GOT_symbol; |
| 13606 | } |
| 13607 | return 0; |
| 13608 | } |
| 13609 | |
| 13610 | /* Round up a section size to the appropriate boundary. */ |
| 13611 | |
| 13612 | valueT |
| 13613 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
| 13614 | { |
| 13615 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
| 13616 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) |
| 13617 | { |
| 13618 | /* For a.out, force the section size to be aligned. If we don't do |
| 13619 | this, BFD will align it for us, but it will not write out the |
| 13620 | final bytes of the section. This may be a bug in BFD, but it is |
| 13621 | easier to fix it here since that is how the other a.out targets |
| 13622 | work. */ |
| 13623 | int align; |
| 13624 | |
| 13625 | align = bfd_section_alignment (segment); |
| 13626 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
| 13627 | } |
| 13628 | #endif |
| 13629 | |
| 13630 | return size; |
| 13631 | } |
| 13632 | |
| 13633 | /* On the i386, PC-relative offsets are relative to the start of the |
| 13634 | next instruction. That is, the address of the offset, plus its |
| 13635 | size, since the offset is always the last part of the insn. */ |
| 13636 | |
| 13637 | long |
| 13638 | md_pcrel_from (fixS *fixP) |
| 13639 | { |
| 13640 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; |
| 13641 | } |
| 13642 | |
| 13643 | #ifndef I386COFF |
| 13644 | |
| 13645 | static void |
| 13646 | s_bss (int ignore ATTRIBUTE_UNUSED) |
| 13647 | { |
| 13648 | int temp; |
| 13649 | |
| 13650 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 13651 | if (IS_ELF) |
| 13652 | obj_elf_section_change_hook (); |
| 13653 | #endif |
| 13654 | temp = get_absolute_expression (); |
| 13655 | subseg_set (bss_section, (subsegT) temp); |
| 13656 | demand_empty_rest_of_line (); |
| 13657 | } |
| 13658 | |
| 13659 | #endif |
| 13660 | |
| 13661 | /* Remember constant directive. */ |
| 13662 | |
| 13663 | void |
| 13664 | i386_cons_align (int ignore ATTRIBUTE_UNUSED) |
| 13665 | { |
| 13666 | if (last_insn.kind != last_insn_directive |
| 13667 | && (bfd_section_flags (now_seg) & SEC_CODE)) |
| 13668 | { |
| 13669 | last_insn.seg = now_seg; |
| 13670 | last_insn.kind = last_insn_directive; |
| 13671 | last_insn.name = "constant directive"; |
| 13672 | last_insn.file = as_where (&last_insn.line); |
| 13673 | if (lfence_before_ret != lfence_before_ret_none) |
| 13674 | { |
| 13675 | if (lfence_before_indirect_branch != lfence_branch_none) |
| 13676 | as_warn (_("constant directive skips -mlfence-before-ret " |
| 13677 | "and -mlfence-before-indirect-branch")); |
| 13678 | else |
| 13679 | as_warn (_("constant directive skips -mlfence-before-ret")); |
| 13680 | } |
| 13681 | else if (lfence_before_indirect_branch != lfence_branch_none) |
| 13682 | as_warn (_("constant directive skips -mlfence-before-indirect-branch")); |
| 13683 | } |
| 13684 | } |
| 13685 | |
| 13686 | void |
| 13687 | i386_validate_fix (fixS *fixp) |
| 13688 | { |
| 13689 | if (fixp->fx_subsy) |
| 13690 | { |
| 13691 | if (fixp->fx_subsy == GOT_symbol) |
| 13692 | { |
| 13693 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
| 13694 | { |
| 13695 | if (!object_64bit) |
| 13696 | abort (); |
| 13697 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 13698 | if (fixp->fx_tcbit2) |
| 13699 | fixp->fx_r_type = (fixp->fx_tcbit |
| 13700 | ? BFD_RELOC_X86_64_REX_GOTPCRELX |
| 13701 | : BFD_RELOC_X86_64_GOTPCRELX); |
| 13702 | else |
| 13703 | #endif |
| 13704 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; |
| 13705 | } |
| 13706 | else |
| 13707 | { |
| 13708 | if (!object_64bit) |
| 13709 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; |
| 13710 | else |
| 13711 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; |
| 13712 | } |
| 13713 | fixp->fx_subsy = 0; |
| 13714 | } |
| 13715 | } |
| 13716 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 13717 | else if (!object_64bit) |
| 13718 | { |
| 13719 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 |
| 13720 | && fixp->fx_tcbit2) |
| 13721 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; |
| 13722 | } |
| 13723 | #endif |
| 13724 | } |
| 13725 | |
| 13726 | arelent * |
| 13727 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
| 13728 | { |
| 13729 | arelent *rel; |
| 13730 | bfd_reloc_code_real_type code; |
| 13731 | |
| 13732 | switch (fixp->fx_r_type) |
| 13733 | { |
| 13734 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 13735 | case BFD_RELOC_SIZE32: |
| 13736 | case BFD_RELOC_SIZE64: |
| 13737 | if (S_IS_DEFINED (fixp->fx_addsy) |
| 13738 | && !S_IS_EXTERNAL (fixp->fx_addsy)) |
| 13739 | { |
| 13740 | /* Resolve size relocation against local symbol to size of |
| 13741 | the symbol plus addend. */ |
| 13742 | valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset; |
| 13743 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 |
| 13744 | && !fits_in_unsigned_long (value)) |
| 13745 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 13746 | _("symbol size computation overflow")); |
| 13747 | fixp->fx_addsy = NULL; |
| 13748 | fixp->fx_subsy = NULL; |
| 13749 | md_apply_fix (fixp, (valueT *) &value, NULL); |
| 13750 | return NULL; |
| 13751 | } |
| 13752 | #endif |
| 13753 | /* Fall through. */ |
| 13754 | |
| 13755 | case BFD_RELOC_X86_64_PLT32: |
| 13756 | case BFD_RELOC_X86_64_GOT32: |
| 13757 | case BFD_RELOC_X86_64_GOTPCREL: |
| 13758 | case BFD_RELOC_X86_64_GOTPCRELX: |
| 13759 | case BFD_RELOC_X86_64_REX_GOTPCRELX: |
| 13760 | case BFD_RELOC_386_PLT32: |
| 13761 | case BFD_RELOC_386_GOT32: |
| 13762 | case BFD_RELOC_386_GOT32X: |
| 13763 | case BFD_RELOC_386_GOTOFF: |
| 13764 | case BFD_RELOC_386_GOTPC: |
| 13765 | case BFD_RELOC_386_TLS_GD: |
| 13766 | case BFD_RELOC_386_TLS_LDM: |
| 13767 | case BFD_RELOC_386_TLS_LDO_32: |
| 13768 | case BFD_RELOC_386_TLS_IE_32: |
| 13769 | case BFD_RELOC_386_TLS_IE: |
| 13770 | case BFD_RELOC_386_TLS_GOTIE: |
| 13771 | case BFD_RELOC_386_TLS_LE_32: |
| 13772 | case BFD_RELOC_386_TLS_LE: |
| 13773 | case BFD_RELOC_386_TLS_GOTDESC: |
| 13774 | case BFD_RELOC_386_TLS_DESC_CALL: |
| 13775 | case BFD_RELOC_X86_64_TLSGD: |
| 13776 | case BFD_RELOC_X86_64_TLSLD: |
| 13777 | case BFD_RELOC_X86_64_DTPOFF32: |
| 13778 | case BFD_RELOC_X86_64_DTPOFF64: |
| 13779 | case BFD_RELOC_X86_64_GOTTPOFF: |
| 13780 | case BFD_RELOC_X86_64_TPOFF32: |
| 13781 | case BFD_RELOC_X86_64_TPOFF64: |
| 13782 | case BFD_RELOC_X86_64_GOTOFF64: |
| 13783 | case BFD_RELOC_X86_64_GOTPC32: |
| 13784 | case BFD_RELOC_X86_64_GOT64: |
| 13785 | case BFD_RELOC_X86_64_GOTPCREL64: |
| 13786 | case BFD_RELOC_X86_64_GOTPC64: |
| 13787 | case BFD_RELOC_X86_64_GOTPLT64: |
| 13788 | case BFD_RELOC_X86_64_PLTOFF64: |
| 13789 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
| 13790 | case BFD_RELOC_X86_64_TLSDESC_CALL: |
| 13791 | case BFD_RELOC_RVA: |
| 13792 | case BFD_RELOC_VTABLE_ENTRY: |
| 13793 | case BFD_RELOC_VTABLE_INHERIT: |
| 13794 | #ifdef TE_PE |
| 13795 | case BFD_RELOC_32_SECREL: |
| 13796 | #endif |
| 13797 | code = fixp->fx_r_type; |
| 13798 | break; |
| 13799 | case BFD_RELOC_X86_64_32S: |
| 13800 | if (!fixp->fx_pcrel) |
| 13801 | { |
| 13802 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ |
| 13803 | code = fixp->fx_r_type; |
| 13804 | break; |
| 13805 | } |
| 13806 | /* Fall through. */ |
| 13807 | default: |
| 13808 | if (fixp->fx_pcrel) |
| 13809 | { |
| 13810 | switch (fixp->fx_size) |
| 13811 | { |
| 13812 | default: |
| 13813 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 13814 | _("can not do %d byte pc-relative relocation"), |
| 13815 | fixp->fx_size); |
| 13816 | code = BFD_RELOC_32_PCREL; |
| 13817 | break; |
| 13818 | case 1: code = BFD_RELOC_8_PCREL; break; |
| 13819 | case 2: code = BFD_RELOC_16_PCREL; break; |
| 13820 | case 4: code = BFD_RELOC_32_PCREL; break; |
| 13821 | #ifdef BFD64 |
| 13822 | case 8: code = BFD_RELOC_64_PCREL; break; |
| 13823 | #endif |
| 13824 | } |
| 13825 | } |
| 13826 | else |
| 13827 | { |
| 13828 | switch (fixp->fx_size) |
| 13829 | { |
| 13830 | default: |
| 13831 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 13832 | _("can not do %d byte relocation"), |
| 13833 | fixp->fx_size); |
| 13834 | code = BFD_RELOC_32; |
| 13835 | break; |
| 13836 | case 1: code = BFD_RELOC_8; break; |
| 13837 | case 2: code = BFD_RELOC_16; break; |
| 13838 | case 4: code = BFD_RELOC_32; break; |
| 13839 | #ifdef BFD64 |
| 13840 | case 8: code = BFD_RELOC_64; break; |
| 13841 | #endif |
| 13842 | } |
| 13843 | } |
| 13844 | break; |
| 13845 | } |
| 13846 | |
| 13847 | if ((code == BFD_RELOC_32 |
| 13848 | || code == BFD_RELOC_32_PCREL |
| 13849 | || code == BFD_RELOC_X86_64_32S) |
| 13850 | && GOT_symbol |
| 13851 | && fixp->fx_addsy == GOT_symbol) |
| 13852 | { |
| 13853 | if (!object_64bit) |
| 13854 | code = BFD_RELOC_386_GOTPC; |
| 13855 | else |
| 13856 | code = BFD_RELOC_X86_64_GOTPC32; |
| 13857 | } |
| 13858 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
| 13859 | && GOT_symbol |
| 13860 | && fixp->fx_addsy == GOT_symbol) |
| 13861 | { |
| 13862 | code = BFD_RELOC_X86_64_GOTPC64; |
| 13863 | } |
| 13864 | |
| 13865 | rel = XNEW (arelent); |
| 13866 | rel->sym_ptr_ptr = XNEW (asymbol *); |
| 13867 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
| 13868 | |
| 13869 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; |
| 13870 | |
| 13871 | if (!use_rela_relocations) |
| 13872 | { |
| 13873 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the |
| 13874 | vtable entry to be used in the relocation's section offset. */ |
| 13875 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
| 13876 | rel->address = fixp->fx_offset; |
| 13877 | #if defined (OBJ_COFF) && defined (TE_PE) |
| 13878 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) |
| 13879 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); |
| 13880 | else |
| 13881 | #endif |
| 13882 | rel->addend = 0; |
| 13883 | } |
| 13884 | /* Use the rela in 64bit mode. */ |
| 13885 | else |
| 13886 | { |
| 13887 | if (disallow_64bit_reloc) |
| 13888 | switch (code) |
| 13889 | { |
| 13890 | case BFD_RELOC_X86_64_DTPOFF64: |
| 13891 | case BFD_RELOC_X86_64_TPOFF64: |
| 13892 | case BFD_RELOC_64_PCREL: |
| 13893 | case BFD_RELOC_X86_64_GOTOFF64: |
| 13894 | case BFD_RELOC_X86_64_GOT64: |
| 13895 | case BFD_RELOC_X86_64_GOTPCREL64: |
| 13896 | case BFD_RELOC_X86_64_GOTPC64: |
| 13897 | case BFD_RELOC_X86_64_GOTPLT64: |
| 13898 | case BFD_RELOC_X86_64_PLTOFF64: |
| 13899 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 13900 | _("cannot represent relocation type %s in x32 mode"), |
| 13901 | bfd_get_reloc_code_name (code)); |
| 13902 | break; |
| 13903 | default: |
| 13904 | break; |
| 13905 | } |
| 13906 | |
| 13907 | if (!fixp->fx_pcrel) |
| 13908 | rel->addend = fixp->fx_offset; |
| 13909 | else |
| 13910 | switch (code) |
| 13911 | { |
| 13912 | case BFD_RELOC_X86_64_PLT32: |
| 13913 | case BFD_RELOC_X86_64_GOT32: |
| 13914 | case BFD_RELOC_X86_64_GOTPCREL: |
| 13915 | case BFD_RELOC_X86_64_GOTPCRELX: |
| 13916 | case BFD_RELOC_X86_64_REX_GOTPCRELX: |
| 13917 | case BFD_RELOC_X86_64_TLSGD: |
| 13918 | case BFD_RELOC_X86_64_TLSLD: |
| 13919 | case BFD_RELOC_X86_64_GOTTPOFF: |
| 13920 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
| 13921 | case BFD_RELOC_X86_64_TLSDESC_CALL: |
| 13922 | rel->addend = fixp->fx_offset - fixp->fx_size; |
| 13923 | break; |
| 13924 | default: |
| 13925 | rel->addend = (section->vma |
| 13926 | - fixp->fx_size |
| 13927 | + fixp->fx_addnumber |
| 13928 | + md_pcrel_from (fixp)); |
| 13929 | break; |
| 13930 | } |
| 13931 | } |
| 13932 | |
| 13933 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
| 13934 | if (rel->howto == NULL) |
| 13935 | { |
| 13936 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 13937 | _("cannot represent relocation type %s"), |
| 13938 | bfd_get_reloc_code_name (code)); |
| 13939 | /* Set howto to a garbage value so that we can keep going. */ |
| 13940 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); |
| 13941 | gas_assert (rel->howto != NULL); |
| 13942 | } |
| 13943 | |
| 13944 | return rel; |
| 13945 | } |
| 13946 | |
| 13947 | #include "tc-i386-intel.c" |
| 13948 | |
| 13949 | void |
| 13950 | tc_x86_parse_to_dw2regnum (expressionS *exp) |
| 13951 | { |
| 13952 | int saved_naked_reg; |
| 13953 | char saved_register_dot; |
| 13954 | |
| 13955 | saved_naked_reg = allow_naked_reg; |
| 13956 | allow_naked_reg = 1; |
| 13957 | saved_register_dot = register_chars['.']; |
| 13958 | register_chars['.'] = '.'; |
| 13959 | allow_pseudo_reg = 1; |
| 13960 | expression_and_evaluate (exp); |
| 13961 | allow_pseudo_reg = 0; |
| 13962 | register_chars['.'] = saved_register_dot; |
| 13963 | allow_naked_reg = saved_naked_reg; |
| 13964 | |
| 13965 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
| 13966 | { |
| 13967 | if ((addressT) exp->X_add_number < i386_regtab_size) |
| 13968 | { |
| 13969 | exp->X_op = O_constant; |
| 13970 | exp->X_add_number = i386_regtab[exp->X_add_number] |
| 13971 | .dw2_regnum[flag_code >> 1]; |
| 13972 | } |
| 13973 | else |
| 13974 | exp->X_op = O_illegal; |
| 13975 | } |
| 13976 | } |
| 13977 | |
| 13978 | void |
| 13979 | tc_x86_frame_initial_instructions (void) |
| 13980 | { |
| 13981 | static unsigned int sp_regno[2]; |
| 13982 | |
| 13983 | if (!sp_regno[flag_code >> 1]) |
| 13984 | { |
| 13985 | char *saved_input = input_line_pointer; |
| 13986 | char sp[][4] = {"esp", "rsp"}; |
| 13987 | expressionS exp; |
| 13988 | |
| 13989 | input_line_pointer = sp[flag_code >> 1]; |
| 13990 | tc_x86_parse_to_dw2regnum (&exp); |
| 13991 | gas_assert (exp.X_op == O_constant); |
| 13992 | sp_regno[flag_code >> 1] = exp.X_add_number; |
| 13993 | input_line_pointer = saved_input; |
| 13994 | } |
| 13995 | |
| 13996 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
| 13997 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); |
| 13998 | } |
| 13999 | |
| 14000 | int |
| 14001 | x86_dwarf2_addr_size (void) |
| 14002 | { |
| 14003 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
| 14004 | if (x86_elf_abi == X86_64_X32_ABI) |
| 14005 | return 4; |
| 14006 | #endif |
| 14007 | return bfd_arch_bits_per_address (stdoutput) / 8; |
| 14008 | } |
| 14009 | |
| 14010 | int |
| 14011 | i386_elf_section_type (const char *str, size_t len) |
| 14012 | { |
| 14013 | if (flag_code == CODE_64BIT |
| 14014 | && len == sizeof ("unwind") - 1 |
| 14015 | && strncmp (str, "unwind", 6) == 0) |
| 14016 | return SHT_X86_64_UNWIND; |
| 14017 | |
| 14018 | return -1; |
| 14019 | } |
| 14020 | |
| 14021 | #ifdef TE_SOLARIS |
| 14022 | void |
| 14023 | i386_solaris_fix_up_eh_frame (segT sec) |
| 14024 | { |
| 14025 | if (flag_code == CODE_64BIT) |
| 14026 | elf_section_type (sec) = SHT_X86_64_UNWIND; |
| 14027 | } |
| 14028 | #endif |
| 14029 | |
| 14030 | #ifdef TE_PE |
| 14031 | void |
| 14032 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) |
| 14033 | { |
| 14034 | expressionS exp; |
| 14035 | |
| 14036 | exp.X_op = O_secrel; |
| 14037 | exp.X_add_symbol = symbol; |
| 14038 | exp.X_add_number = 0; |
| 14039 | emit_expr (&exp, size); |
| 14040 | } |
| 14041 | #endif |
| 14042 | |
| 14043 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 14044 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ |
| 14045 | |
| 14046 | bfd_vma |
| 14047 | x86_64_section_letter (int letter, const char **ptr_msg) |
| 14048 | { |
| 14049 | if (flag_code == CODE_64BIT) |
| 14050 | { |
| 14051 | if (letter == 'l') |
| 14052 | return SHF_X86_64_LARGE; |
| 14053 | |
| 14054 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
| 14055 | } |
| 14056 | else |
| 14057 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
| 14058 | return -1; |
| 14059 | } |
| 14060 | |
| 14061 | bfd_vma |
| 14062 | x86_64_section_word (char *str, size_t len) |
| 14063 | { |
| 14064 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
| 14065 | return SHF_X86_64_LARGE; |
| 14066 | |
| 14067 | return -1; |
| 14068 | } |
| 14069 | |
| 14070 | static void |
| 14071 | handle_large_common (int small ATTRIBUTE_UNUSED) |
| 14072 | { |
| 14073 | if (flag_code != CODE_64BIT) |
| 14074 | { |
| 14075 | s_comm_internal (0, elf_common_parse); |
| 14076 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); |
| 14077 | } |
| 14078 | else |
| 14079 | { |
| 14080 | static segT lbss_section; |
| 14081 | asection *saved_com_section_ptr = elf_com_section_ptr; |
| 14082 | asection *saved_bss_section = bss_section; |
| 14083 | |
| 14084 | if (lbss_section == NULL) |
| 14085 | { |
| 14086 | flagword applicable; |
| 14087 | segT seg = now_seg; |
| 14088 | subsegT subseg = now_subseg; |
| 14089 | |
| 14090 | /* The .lbss section is for local .largecomm symbols. */ |
| 14091 | lbss_section = subseg_new (".lbss", 0); |
| 14092 | applicable = bfd_applicable_section_flags (stdoutput); |
| 14093 | bfd_set_section_flags (lbss_section, applicable & SEC_ALLOC); |
| 14094 | seg_info (lbss_section)->bss = 1; |
| 14095 | |
| 14096 | subseg_set (seg, subseg); |
| 14097 | } |
| 14098 | |
| 14099 | elf_com_section_ptr = &_bfd_elf_large_com_section; |
| 14100 | bss_section = lbss_section; |
| 14101 | |
| 14102 | s_comm_internal (0, elf_common_parse); |
| 14103 | |
| 14104 | elf_com_section_ptr = saved_com_section_ptr; |
| 14105 | bss_section = saved_bss_section; |
| 14106 | } |
| 14107 | } |
| 14108 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |