| 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
| 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
| 3 | 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
| 4 | Free Software Foundation, Inc. |
| 5 | |
| 6 | This file is part of GAS, the GNU Assembler. |
| 7 | |
| 8 | GAS is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU General Public License as published by |
| 10 | the Free Software Foundation; either version 3, or (at your option) |
| 11 | any later version. |
| 12 | |
| 13 | GAS is distributed in the hope that it will be useful, |
| 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | GNU General Public License for more details. |
| 17 | |
| 18 | You should have received a copy of the GNU General Public License |
| 19 | along with GAS; see the file COPYING. If not, write to the Free |
| 20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
| 21 | 02110-1301, USA. */ |
| 22 | |
| 23 | /* Intel 80386 machine specific gas. |
| 24 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). |
| 25 | x86_64 support by Jan Hubicka (jh@suse.cz) |
| 26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
| 27 | Bugs & suggestions are completely welcome. This is free software. |
| 28 | Please help us make it better. */ |
| 29 | |
| 30 | #include "as.h" |
| 31 | #include "safe-ctype.h" |
| 32 | #include "subsegs.h" |
| 33 | #include "dwarf2dbg.h" |
| 34 | #include "dw2gencfi.h" |
| 35 | #include "elf/x86-64.h" |
| 36 | #include "opcodes/i386-init.h" |
| 37 | |
| 38 | #ifndef REGISTER_WARNINGS |
| 39 | #define REGISTER_WARNINGS 1 |
| 40 | #endif |
| 41 | |
| 42 | #ifndef INFER_ADDR_PREFIX |
| 43 | #define INFER_ADDR_PREFIX 1 |
| 44 | #endif |
| 45 | |
| 46 | #ifndef DEFAULT_ARCH |
| 47 | #define DEFAULT_ARCH "i386" |
| 48 | #endif |
| 49 | |
| 50 | #ifndef INLINE |
| 51 | #if __GNUC__ >= 2 |
| 52 | #define INLINE __inline__ |
| 53 | #else |
| 54 | #define INLINE |
| 55 | #endif |
| 56 | #endif |
| 57 | |
| 58 | /* Prefixes will be emitted in the order defined below. |
| 59 | WAIT_PREFIX must be the first prefix since FWAIT is really is an |
| 60 | instruction, and so must come before any prefixes. |
| 61 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, |
| 62 | REP_PREFIX, LOCK_PREFIX. */ |
| 63 | #define WAIT_PREFIX 0 |
| 64 | #define SEG_PREFIX 1 |
| 65 | #define ADDR_PREFIX 2 |
| 66 | #define DATA_PREFIX 3 |
| 67 | #define REP_PREFIX 4 |
| 68 | #define LOCK_PREFIX 5 |
| 69 | #define REX_PREFIX 6 /* must come last. */ |
| 70 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ |
| 71 | |
| 72 | /* we define the syntax here (modulo base,index,scale syntax) */ |
| 73 | #define REGISTER_PREFIX '%' |
| 74 | #define IMMEDIATE_PREFIX '$' |
| 75 | #define ABSOLUTE_PREFIX '*' |
| 76 | |
| 77 | /* these are the instruction mnemonic suffixes in AT&T syntax or |
| 78 | memory operand size in Intel syntax. */ |
| 79 | #define WORD_MNEM_SUFFIX 'w' |
| 80 | #define BYTE_MNEM_SUFFIX 'b' |
| 81 | #define SHORT_MNEM_SUFFIX 's' |
| 82 | #define LONG_MNEM_SUFFIX 'l' |
| 83 | #define QWORD_MNEM_SUFFIX 'q' |
| 84 | #define XMMWORD_MNEM_SUFFIX 'x' |
| 85 | #define YMMWORD_MNEM_SUFFIX 'y' |
| 86 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
| 87 | in instructions. */ |
| 88 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' |
| 89 | |
| 90 | #define END_OF_INSN '\0' |
| 91 | |
| 92 | /* |
| 93 | 'templates' is for grouping together 'template' structures for opcodes |
| 94 | of the same name. This is only used for storing the insns in the grand |
| 95 | ole hash table of insns. |
| 96 | The templates themselves start at START and range up to (but not including) |
| 97 | END. |
| 98 | */ |
| 99 | typedef struct |
| 100 | { |
| 101 | const insn_template *start; |
| 102 | const insn_template *end; |
| 103 | } |
| 104 | templates; |
| 105 | |
| 106 | /* 386 operand encoding bytes: see 386 book for details of this. */ |
| 107 | typedef struct |
| 108 | { |
| 109 | unsigned int regmem; /* codes register or memory operand */ |
| 110 | unsigned int reg; /* codes register operand (or extended opcode) */ |
| 111 | unsigned int mode; /* how to interpret regmem & reg */ |
| 112 | } |
| 113 | modrm_byte; |
| 114 | |
| 115 | /* x86-64 extension prefix. */ |
| 116 | typedef int rex_byte; |
| 117 | |
| 118 | /* 386 opcode byte to code indirect addressing. */ |
| 119 | typedef struct |
| 120 | { |
| 121 | unsigned base; |
| 122 | unsigned index; |
| 123 | unsigned scale; |
| 124 | } |
| 125 | sib_byte; |
| 126 | |
| 127 | /* x86 arch names, types and features */ |
| 128 | typedef struct |
| 129 | { |
| 130 | const char *name; /* arch name */ |
| 131 | unsigned int len; /* arch string length */ |
| 132 | enum processor_type type; /* arch type */ |
| 133 | i386_cpu_flags flags; /* cpu feature flags */ |
| 134 | unsigned int skip; /* show_arch should skip this. */ |
| 135 | unsigned int negated; /* turn off indicated flags. */ |
| 136 | } |
| 137 | arch_entry; |
| 138 | |
| 139 | static void update_code_flag (int, int); |
| 140 | static void set_code_flag (int); |
| 141 | static void set_16bit_gcc_code_flag (int); |
| 142 | static void set_intel_syntax (int); |
| 143 | static void set_intel_mnemonic (int); |
| 144 | static void set_allow_index_reg (int); |
| 145 | static void set_sse_check (int); |
| 146 | static void set_cpu_arch (int); |
| 147 | #ifdef TE_PE |
| 148 | static void pe_directive_secrel (int); |
| 149 | #endif |
| 150 | static void signed_cons (int); |
| 151 | static char *output_invalid (int c); |
| 152 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
| 153 | const char *); |
| 154 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, |
| 155 | const char *); |
| 156 | static int i386_att_operand (char *); |
| 157 | static int i386_intel_operand (char *, int); |
| 158 | static int i386_intel_simplify (expressionS *); |
| 159 | static int i386_intel_parse_name (const char *, expressionS *); |
| 160 | static const reg_entry *parse_register (char *, char **); |
| 161 | static char *parse_insn (char *, char *); |
| 162 | static char *parse_operands (char *, const char *); |
| 163 | static void swap_operands (void); |
| 164 | static void swap_2_operands (int, int); |
| 165 | static void optimize_imm (void); |
| 166 | static void optimize_disp (void); |
| 167 | static const insn_template *match_template (void); |
| 168 | static int check_string (void); |
| 169 | static int process_suffix (void); |
| 170 | static int check_byte_reg (void); |
| 171 | static int check_long_reg (void); |
| 172 | static int check_qword_reg (void); |
| 173 | static int check_word_reg (void); |
| 174 | static int finalize_imm (void); |
| 175 | static int process_operands (void); |
| 176 | static const seg_entry *build_modrm_byte (void); |
| 177 | static void output_insn (void); |
| 178 | static void output_imm (fragS *, offsetT); |
| 179 | static void output_disp (fragS *, offsetT); |
| 180 | #ifndef I386COFF |
| 181 | static void s_bss (int); |
| 182 | #endif |
| 183 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 184 | static void handle_large_common (int small ATTRIBUTE_UNUSED); |
| 185 | #endif |
| 186 | |
| 187 | static const char *default_arch = DEFAULT_ARCH; |
| 188 | |
| 189 | /* VEX prefix. */ |
| 190 | typedef struct |
| 191 | { |
| 192 | /* VEX prefix is either 2 byte or 3 byte. */ |
| 193 | unsigned char bytes[3]; |
| 194 | unsigned int length; |
| 195 | /* Destination or source register specifier. */ |
| 196 | const reg_entry *register_specifier; |
| 197 | } vex_prefix; |
| 198 | |
| 199 | /* 'md_assemble ()' gathers together information and puts it into a |
| 200 | i386_insn. */ |
| 201 | |
| 202 | union i386_op |
| 203 | { |
| 204 | expressionS *disps; |
| 205 | expressionS *imms; |
| 206 | const reg_entry *regs; |
| 207 | }; |
| 208 | |
| 209 | enum i386_error |
| 210 | { |
| 211 | operand_size_mismatch, |
| 212 | operand_type_mismatch, |
| 213 | register_type_mismatch, |
| 214 | number_of_operands_mismatch, |
| 215 | invalid_instruction_suffix, |
| 216 | bad_imm4, |
| 217 | old_gcc_only, |
| 218 | unsupported_with_intel_mnemonic, |
| 219 | unsupported_syntax, |
| 220 | unsupported |
| 221 | }; |
| 222 | |
| 223 | struct _i386_insn |
| 224 | { |
| 225 | /* TM holds the template for the insn were currently assembling. */ |
| 226 | insn_template tm; |
| 227 | |
| 228 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
| 229 | or qword, if given. */ |
| 230 | char suffix; |
| 231 | |
| 232 | /* OPERANDS gives the number of given operands. */ |
| 233 | unsigned int operands; |
| 234 | |
| 235 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number |
| 236 | of given register, displacement, memory operands and immediate |
| 237 | operands. */ |
| 238 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
| 239 | |
| 240 | /* TYPES [i] is the type (see above #defines) which tells us how to |
| 241 | use OP[i] for the corresponding operand. */ |
| 242 | i386_operand_type types[MAX_OPERANDS]; |
| 243 | |
| 244 | /* Displacement expression, immediate expression, or register for each |
| 245 | operand. */ |
| 246 | union i386_op op[MAX_OPERANDS]; |
| 247 | |
| 248 | /* Flags for operands. */ |
| 249 | unsigned int flags[MAX_OPERANDS]; |
| 250 | #define Operand_PCrel 1 |
| 251 | |
| 252 | /* Relocation type for operand */ |
| 253 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
| 254 | |
| 255 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
| 256 | the base index byte below. */ |
| 257 | const reg_entry *base_reg; |
| 258 | const reg_entry *index_reg; |
| 259 | unsigned int log2_scale_factor; |
| 260 | |
| 261 | /* SEG gives the seg_entries of this insn. They are zero unless |
| 262 | explicit segment overrides are given. */ |
| 263 | const seg_entry *seg[2]; |
| 264 | |
| 265 | /* PREFIX holds all the given prefix opcodes (usually null). |
| 266 | PREFIXES is the number of prefix opcodes. */ |
| 267 | unsigned int prefixes; |
| 268 | unsigned char prefix[MAX_PREFIXES]; |
| 269 | |
| 270 | /* RM and SIB are the modrm byte and the sib byte where the |
| 271 | addressing modes of this insn are encoded. */ |
| 272 | modrm_byte rm; |
| 273 | rex_byte rex; |
| 274 | sib_byte sib; |
| 275 | vex_prefix vex; |
| 276 | |
| 277 | /* Swap operand in encoding. */ |
| 278 | unsigned int swap_operand; |
| 279 | |
| 280 | /* Force 32bit displacement in encoding. */ |
| 281 | unsigned int disp32_encoding; |
| 282 | |
| 283 | /* Error message. */ |
| 284 | enum i386_error error; |
| 285 | }; |
| 286 | |
| 287 | typedef struct _i386_insn i386_insn; |
| 288 | |
| 289 | /* List of chars besides those in app.c:symbol_chars that can start an |
| 290 | operand. Used to prevent the scrubber eating vital white-space. */ |
| 291 | const char extra_symbol_chars[] = "*%-([" |
| 292 | #ifdef LEX_AT |
| 293 | "@" |
| 294 | #endif |
| 295 | #ifdef LEX_QM |
| 296 | "?" |
| 297 | #endif |
| 298 | ; |
| 299 | |
| 300 | #if (defined (TE_I386AIX) \ |
| 301 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ |
| 302 | && !defined (TE_GNU) \ |
| 303 | && !defined (TE_LINUX) \ |
| 304 | && !defined (TE_NETWARE) \ |
| 305 | && !defined (TE_FreeBSD) \ |
| 306 | && !defined (TE_NetBSD))) |
| 307 | /* This array holds the chars that always start a comment. If the |
| 308 | pre-processor is disabled, these aren't very useful. The option |
| 309 | --divide will remove '/' from this list. */ |
| 310 | const char *i386_comment_chars = "#/"; |
| 311 | #define SVR4_COMMENT_CHARS 1 |
| 312 | #define PREFIX_SEPARATOR '\\' |
| 313 | |
| 314 | #else |
| 315 | const char *i386_comment_chars = "#"; |
| 316 | #define PREFIX_SEPARATOR '/' |
| 317 | #endif |
| 318 | |
| 319 | /* This array holds the chars that only start a comment at the beginning of |
| 320 | a line. If the line seems to have the form '# 123 filename' |
| 321 | .line and .file directives will appear in the pre-processed output. |
| 322 | Note that input_file.c hand checks for '#' at the beginning of the |
| 323 | first line of the input file. This is because the compiler outputs |
| 324 | #NO_APP at the beginning of its output. |
| 325 | Also note that comments started like this one will always work if |
| 326 | '/' isn't otherwise defined. */ |
| 327 | const char line_comment_chars[] = "#/"; |
| 328 | |
| 329 | const char line_separator_chars[] = ";"; |
| 330 | |
| 331 | /* Chars that can be used to separate mant from exp in floating point |
| 332 | nums. */ |
| 333 | const char EXP_CHARS[] = "eE"; |
| 334 | |
| 335 | /* Chars that mean this number is a floating point constant |
| 336 | As in 0f12.456 |
| 337 | or 0d1.2345e12. */ |
| 338 | const char FLT_CHARS[] = "fFdDxX"; |
| 339 | |
| 340 | /* Tables for lexical analysis. */ |
| 341 | static char mnemonic_chars[256]; |
| 342 | static char register_chars[256]; |
| 343 | static char operand_chars[256]; |
| 344 | static char identifier_chars[256]; |
| 345 | static char digit_chars[256]; |
| 346 | |
| 347 | /* Lexical macros. */ |
| 348 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
| 349 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) |
| 350 | #define is_register_char(x) (register_chars[(unsigned char) x]) |
| 351 | #define is_space_char(x) ((x) == ' ') |
| 352 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) |
| 353 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) |
| 354 | |
| 355 | /* All non-digit non-letter characters that may occur in an operand. */ |
| 356 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
| 357 | |
| 358 | /* md_assemble() always leaves the strings it's passed unaltered. To |
| 359 | effect this we maintain a stack of saved characters that we've smashed |
| 360 | with '\0's (indicating end of strings for various sub-fields of the |
| 361 | assembler instruction). */ |
| 362 | static char save_stack[32]; |
| 363 | static char *save_stack_p; |
| 364 | #define END_STRING_AND_SAVE(s) \ |
| 365 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) |
| 366 | #define RESTORE_END_STRING(s) \ |
| 367 | do { *(s) = *--save_stack_p; } while (0) |
| 368 | |
| 369 | /* The instruction we're assembling. */ |
| 370 | static i386_insn i; |
| 371 | |
| 372 | /* Possible templates for current insn. */ |
| 373 | static const templates *current_templates; |
| 374 | |
| 375 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
| 376 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; |
| 377 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; |
| 378 | |
| 379 | /* Current operand we are working on. */ |
| 380 | static int this_operand = -1; |
| 381 | |
| 382 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
| 383 | these. */ |
| 384 | |
| 385 | enum flag_code { |
| 386 | CODE_32BIT, |
| 387 | CODE_16BIT, |
| 388 | CODE_64BIT }; |
| 389 | |
| 390 | static enum flag_code flag_code; |
| 391 | static unsigned int object_64bit; |
| 392 | static unsigned int disallow_64bit_reloc; |
| 393 | static int use_rela_relocations = 0; |
| 394 | |
| 395 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
| 396 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
| 397 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
| 398 | |
| 399 | /* The ELF ABI to use. */ |
| 400 | enum x86_elf_abi |
| 401 | { |
| 402 | I386_ABI, |
| 403 | X86_64_ABI, |
| 404 | X86_64_X32_ABI |
| 405 | }; |
| 406 | |
| 407 | static enum x86_elf_abi x86_elf_abi = I386_ABI; |
| 408 | #endif |
| 409 | |
| 410 | /* The names used to print error messages. */ |
| 411 | static const char *flag_code_names[] = |
| 412 | { |
| 413 | "32", |
| 414 | "16", |
| 415 | "64" |
| 416 | }; |
| 417 | |
| 418 | /* 1 for intel syntax, |
| 419 | 0 if att syntax. */ |
| 420 | static int intel_syntax = 0; |
| 421 | |
| 422 | /* 1 for intel mnemonic, |
| 423 | 0 if att mnemonic. */ |
| 424 | static int intel_mnemonic = !SYSV386_COMPAT; |
| 425 | |
| 426 | /* 1 if support old (<= 2.8.1) versions of gcc. */ |
| 427 | static int old_gcc = OLDGCC_COMPAT; |
| 428 | |
| 429 | /* 1 if pseudo registers are permitted. */ |
| 430 | static int allow_pseudo_reg = 0; |
| 431 | |
| 432 | /* 1 if register prefix % not required. */ |
| 433 | static int allow_naked_reg = 0; |
| 434 | |
| 435 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
| 436 | static int allow_index_reg = 0; |
| 437 | |
| 438 | static enum |
| 439 | { |
| 440 | sse_check_none = 0, |
| 441 | sse_check_warning, |
| 442 | sse_check_error |
| 443 | } |
| 444 | sse_check; |
| 445 | |
| 446 | /* Register prefix used for error message. */ |
| 447 | static const char *register_prefix = "%"; |
| 448 | |
| 449 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
| 450 | leave, push, and pop instructions so that gcc has the same stack |
| 451 | frame as in 32 bit mode. */ |
| 452 | static char stackop_size = '\0'; |
| 453 | |
| 454 | /* Non-zero to optimize code alignment. */ |
| 455 | int optimize_align_code = 1; |
| 456 | |
| 457 | /* Non-zero to quieten some warnings. */ |
| 458 | static int quiet_warnings = 0; |
| 459 | |
| 460 | /* CPU name. */ |
| 461 | static const char *cpu_arch_name = NULL; |
| 462 | static char *cpu_sub_arch_name = NULL; |
| 463 | |
| 464 | /* CPU feature flags. */ |
| 465 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
| 466 | |
| 467 | /* If we have selected a cpu we are generating instructions for. */ |
| 468 | static int cpu_arch_tune_set = 0; |
| 469 | |
| 470 | /* Cpu we are generating instructions for. */ |
| 471 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
| 472 | |
| 473 | /* CPU feature flags of cpu we are generating instructions for. */ |
| 474 | static i386_cpu_flags cpu_arch_tune_flags; |
| 475 | |
| 476 | /* CPU instruction set architecture used. */ |
| 477 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
| 478 | |
| 479 | /* CPU feature flags of instruction set architecture used. */ |
| 480 | i386_cpu_flags cpu_arch_isa_flags; |
| 481 | |
| 482 | /* If set, conditional jumps are not automatically promoted to handle |
| 483 | larger than a byte offset. */ |
| 484 | static unsigned int no_cond_jump_promotion = 0; |
| 485 | |
| 486 | /* Encode SSE instructions with VEX prefix. */ |
| 487 | static unsigned int sse2avx; |
| 488 | |
| 489 | /* Encode scalar AVX instructions with specific vector length. */ |
| 490 | static enum |
| 491 | { |
| 492 | vex128 = 0, |
| 493 | vex256 |
| 494 | } avxscalar; |
| 495 | |
| 496 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
| 497 | static symbolS *GOT_symbol; |
| 498 | |
| 499 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
| 500 | unsigned int x86_dwarf2_return_column; |
| 501 | |
| 502 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ |
| 503 | int x86_cie_data_alignment; |
| 504 | |
| 505 | /* Interface to relax_segment. |
| 506 | There are 3 major relax states for 386 jump insns because the |
| 507 | different types of jumps add different sizes to frags when we're |
| 508 | figuring out what sort of jump to choose to reach a given label. */ |
| 509 | |
| 510 | /* Types. */ |
| 511 | #define UNCOND_JUMP 0 |
| 512 | #define COND_JUMP 1 |
| 513 | #define COND_JUMP86 2 |
| 514 | |
| 515 | /* Sizes. */ |
| 516 | #define CODE16 1 |
| 517 | #define SMALL 0 |
| 518 | #define SMALL16 (SMALL | CODE16) |
| 519 | #define BIG 2 |
| 520 | #define BIG16 (BIG | CODE16) |
| 521 | |
| 522 | #ifndef INLINE |
| 523 | #ifdef __GNUC__ |
| 524 | #define INLINE __inline__ |
| 525 | #else |
| 526 | #define INLINE |
| 527 | #endif |
| 528 | #endif |
| 529 | |
| 530 | #define ENCODE_RELAX_STATE(type, size) \ |
| 531 | ((relax_substateT) (((type) << 2) | (size))) |
| 532 | #define TYPE_FROM_RELAX_STATE(s) \ |
| 533 | ((s) >> 2) |
| 534 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ |
| 535 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) |
| 536 | |
| 537 | /* This table is used by relax_frag to promote short jumps to long |
| 538 | ones where necessary. SMALL (short) jumps may be promoted to BIG |
| 539 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We |
| 540 | don't allow a short jump in a 32 bit code segment to be promoted to |
| 541 | a 16 bit offset jump because it's slower (requires data size |
| 542 | prefix), and doesn't work, unless the destination is in the bottom |
| 543 | 64k of the code segment (The top 16 bits of eip are zeroed). */ |
| 544 | |
| 545 | const relax_typeS md_relax_table[] = |
| 546 | { |
| 547 | /* The fields are: |
| 548 | 1) most positive reach of this state, |
| 549 | 2) most negative reach of this state, |
| 550 | 3) how many bytes this mode will have in the variable part of the frag |
| 551 | 4) which index into the table to try if we can't fit into this one. */ |
| 552 | |
| 553 | /* UNCOND_JUMP states. */ |
| 554 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
| 555 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, |
| 556 | /* dword jmp adds 4 bytes to frag: |
| 557 | 0 extra opcode bytes, 4 displacement bytes. */ |
| 558 | {0, 0, 4, 0}, |
| 559 | /* word jmp adds 2 byte2 to frag: |
| 560 | 0 extra opcode bytes, 2 displacement bytes. */ |
| 561 | {0, 0, 2, 0}, |
| 562 | |
| 563 | /* COND_JUMP states. */ |
| 564 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, |
| 565 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, |
| 566 | /* dword conditionals adds 5 bytes to frag: |
| 567 | 1 extra opcode byte, 4 displacement bytes. */ |
| 568 | {0, 0, 5, 0}, |
| 569 | /* word conditionals add 3 bytes to frag: |
| 570 | 1 extra opcode byte, 2 displacement bytes. */ |
| 571 | {0, 0, 3, 0}, |
| 572 | |
| 573 | /* COND_JUMP86 states. */ |
| 574 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, |
| 575 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, |
| 576 | /* dword conditionals adds 5 bytes to frag: |
| 577 | 1 extra opcode byte, 4 displacement bytes. */ |
| 578 | {0, 0, 5, 0}, |
| 579 | /* word conditionals add 4 bytes to frag: |
| 580 | 1 displacement byte and a 3 byte long branch insn. */ |
| 581 | {0, 0, 4, 0} |
| 582 | }; |
| 583 | |
| 584 | static const arch_entry cpu_arch[] = |
| 585 | { |
| 586 | /* Do not replace the first two entries - i386_target_format() |
| 587 | relies on them being there in this order. */ |
| 588 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
| 589 | CPU_GENERIC32_FLAGS, 0, 0 }, |
| 590 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
| 591 | CPU_GENERIC64_FLAGS, 0, 0 }, |
| 592 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
| 593 | CPU_NONE_FLAGS, 0, 0 }, |
| 594 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
| 595 | CPU_I186_FLAGS, 0, 0 }, |
| 596 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
| 597 | CPU_I286_FLAGS, 0, 0 }, |
| 598 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
| 599 | CPU_I386_FLAGS, 0, 0 }, |
| 600 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
| 601 | CPU_I486_FLAGS, 0, 0 }, |
| 602 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
| 603 | CPU_I586_FLAGS, 0, 0 }, |
| 604 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
| 605 | CPU_I686_FLAGS, 0, 0 }, |
| 606 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
| 607 | CPU_I586_FLAGS, 0, 0 }, |
| 608 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
| 609 | CPU_PENTIUMPRO_FLAGS, 0, 0 }, |
| 610 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
| 611 | CPU_P2_FLAGS, 0, 0 }, |
| 612 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
| 613 | CPU_P3_FLAGS, 0, 0 }, |
| 614 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
| 615 | CPU_P4_FLAGS, 0, 0 }, |
| 616 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
| 617 | CPU_CORE_FLAGS, 0, 0 }, |
| 618 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
| 619 | CPU_NOCONA_FLAGS, 0, 0 }, |
| 620 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
| 621 | CPU_CORE_FLAGS, 1, 0 }, |
| 622 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
| 623 | CPU_CORE_FLAGS, 0, 0 }, |
| 624 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
| 625 | CPU_CORE2_FLAGS, 1, 0 }, |
| 626 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
| 627 | CPU_CORE2_FLAGS, 0, 0 }, |
| 628 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
| 629 | CPU_COREI7_FLAGS, 0, 0 }, |
| 630 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
| 631 | CPU_L1OM_FLAGS, 0, 0 }, |
| 632 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
| 633 | CPU_K6_FLAGS, 0, 0 }, |
| 634 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
| 635 | CPU_K6_2_FLAGS, 0, 0 }, |
| 636 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
| 637 | CPU_ATHLON_FLAGS, 0, 0 }, |
| 638 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
| 639 | CPU_K8_FLAGS, 1, 0 }, |
| 640 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
| 641 | CPU_K8_FLAGS, 0, 0 }, |
| 642 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
| 643 | CPU_K8_FLAGS, 0, 0 }, |
| 644 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
| 645 | CPU_AMDFAM10_FLAGS, 0, 0 }, |
| 646 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1, |
| 647 | CPU_BDVER1_FLAGS, 0, 0 }, |
| 648 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
| 649 | CPU_8087_FLAGS, 0, 0 }, |
| 650 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
| 651 | CPU_287_FLAGS, 0, 0 }, |
| 652 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
| 653 | CPU_387_FLAGS, 0, 0 }, |
| 654 | { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN, |
| 655 | CPU_ANY87_FLAGS, 0, 1 }, |
| 656 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
| 657 | CPU_MMX_FLAGS, 0, 0 }, |
| 658 | { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN, |
| 659 | CPU_3DNOWA_FLAGS, 0, 1 }, |
| 660 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
| 661 | CPU_SSE_FLAGS, 0, 0 }, |
| 662 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
| 663 | CPU_SSE2_FLAGS, 0, 0 }, |
| 664 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
| 665 | CPU_SSE3_FLAGS, 0, 0 }, |
| 666 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
| 667 | CPU_SSSE3_FLAGS, 0, 0 }, |
| 668 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
| 669 | CPU_SSE4_1_FLAGS, 0, 0 }, |
| 670 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
| 671 | CPU_SSE4_2_FLAGS, 0, 0 }, |
| 672 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
| 673 | CPU_SSE4_2_FLAGS, 0, 0 }, |
| 674 | { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN, |
| 675 | CPU_ANY_SSE_FLAGS, 0, 1 }, |
| 676 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
| 677 | CPU_AVX_FLAGS, 0, 0 }, |
| 678 | { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN, |
| 679 | CPU_ANY_AVX_FLAGS, 0, 1 }, |
| 680 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
| 681 | CPU_VMX_FLAGS, 0, 0 }, |
| 682 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
| 683 | CPU_SMX_FLAGS, 0, 0 }, |
| 684 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
| 685 | CPU_XSAVE_FLAGS, 0, 0 }, |
| 686 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
| 687 | CPU_XSAVEOPT_FLAGS, 0, 0 }, |
| 688 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
| 689 | CPU_AES_FLAGS, 0, 0 }, |
| 690 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
| 691 | CPU_PCLMUL_FLAGS, 0, 0 }, |
| 692 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
| 693 | CPU_PCLMUL_FLAGS, 1, 0 }, |
| 694 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
| 695 | CPU_FSGSBASE_FLAGS, 0, 0 }, |
| 696 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
| 697 | CPU_RDRND_FLAGS, 0, 0 }, |
| 698 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
| 699 | CPU_F16C_FLAGS, 0, 0 }, |
| 700 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
| 701 | CPU_FMA_FLAGS, 0, 0 }, |
| 702 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
| 703 | CPU_FMA4_FLAGS, 0, 0 }, |
| 704 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
| 705 | CPU_XOP_FLAGS, 0, 0 }, |
| 706 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
| 707 | CPU_LWP_FLAGS, 0, 0 }, |
| 708 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
| 709 | CPU_MOVBE_FLAGS, 0, 0 }, |
| 710 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
| 711 | CPU_EPT_FLAGS, 0, 0 }, |
| 712 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
| 713 | CPU_CLFLUSH_FLAGS, 0, 0 }, |
| 714 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
| 715 | CPU_NOP_FLAGS, 0, 0 }, |
| 716 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
| 717 | CPU_SYSCALL_FLAGS, 0, 0 }, |
| 718 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
| 719 | CPU_RDTSCP_FLAGS, 0, 0 }, |
| 720 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
| 721 | CPU_3DNOW_FLAGS, 0, 0 }, |
| 722 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
| 723 | CPU_3DNOWA_FLAGS, 0, 0 }, |
| 724 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
| 725 | CPU_PADLOCK_FLAGS, 0, 0 }, |
| 726 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
| 727 | CPU_SVME_FLAGS, 1, 0 }, |
| 728 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
| 729 | CPU_SVME_FLAGS, 0, 0 }, |
| 730 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
| 731 | CPU_SSE4A_FLAGS, 0, 0 }, |
| 732 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
| 733 | CPU_ABM_FLAGS, 0, 0 }, |
| 734 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
| 735 | CPU_BMI_FLAGS, 0, 0 }, |
| 736 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
| 737 | CPU_TBM_FLAGS, 0, 0 }, |
| 738 | }; |
| 739 | |
| 740 | #ifdef I386COFF |
| 741 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
| 742 | is allowed to be optional. */ |
| 743 | |
| 744 | static symbolS * |
| 745 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) |
| 746 | { |
| 747 | addressT align = 0; |
| 748 | |
| 749 | SKIP_WHITESPACE (); |
| 750 | |
| 751 | if (needs_align |
| 752 | && *input_line_pointer == ',') |
| 753 | { |
| 754 | align = parse_align (needs_align - 1); |
| 755 | |
| 756 | if (align == (addressT) -1) |
| 757 | return NULL; |
| 758 | } |
| 759 | else |
| 760 | { |
| 761 | if (size >= 8) |
| 762 | align = 3; |
| 763 | else if (size >= 4) |
| 764 | align = 2; |
| 765 | else if (size >= 2) |
| 766 | align = 1; |
| 767 | else |
| 768 | align = 0; |
| 769 | } |
| 770 | |
| 771 | bss_alloc (symbolP, size, align); |
| 772 | return symbolP; |
| 773 | } |
| 774 | |
| 775 | static void |
| 776 | pe_lcomm (int needs_align) |
| 777 | { |
| 778 | s_comm_internal (needs_align * 2, pe_lcomm_internal); |
| 779 | } |
| 780 | #endif |
| 781 | |
| 782 | const pseudo_typeS md_pseudo_table[] = |
| 783 | { |
| 784 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) |
| 785 | {"align", s_align_bytes, 0}, |
| 786 | #else |
| 787 | {"align", s_align_ptwo, 0}, |
| 788 | #endif |
| 789 | {"arch", set_cpu_arch, 0}, |
| 790 | #ifndef I386COFF |
| 791 | {"bss", s_bss, 0}, |
| 792 | #else |
| 793 | {"lcomm", pe_lcomm, 1}, |
| 794 | #endif |
| 795 | {"ffloat", float_cons, 'f'}, |
| 796 | {"dfloat", float_cons, 'd'}, |
| 797 | {"tfloat", float_cons, 'x'}, |
| 798 | {"value", cons, 2}, |
| 799 | {"slong", signed_cons, 4}, |
| 800 | {"noopt", s_ignore, 0}, |
| 801 | {"optim", s_ignore, 0}, |
| 802 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, |
| 803 | {"code16", set_code_flag, CODE_16BIT}, |
| 804 | {"code32", set_code_flag, CODE_32BIT}, |
| 805 | {"code64", set_code_flag, CODE_64BIT}, |
| 806 | {"intel_syntax", set_intel_syntax, 1}, |
| 807 | {"att_syntax", set_intel_syntax, 0}, |
| 808 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
| 809 | {"att_mnemonic", set_intel_mnemonic, 0}, |
| 810 | {"allow_index_reg", set_allow_index_reg, 1}, |
| 811 | {"disallow_index_reg", set_allow_index_reg, 0}, |
| 812 | {"sse_check", set_sse_check, 0}, |
| 813 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 814 | {"largecomm", handle_large_common, 0}, |
| 815 | #else |
| 816 | {"file", (void (*) (int)) dwarf2_directive_file, 0}, |
| 817 | {"loc", dwarf2_directive_loc, 0}, |
| 818 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, |
| 819 | #endif |
| 820 | #ifdef TE_PE |
| 821 | {"secrel32", pe_directive_secrel, 0}, |
| 822 | #endif |
| 823 | {0, 0, 0} |
| 824 | }; |
| 825 | |
| 826 | /* For interface with expression (). */ |
| 827 | extern char *input_line_pointer; |
| 828 | |
| 829 | /* Hash table for instruction mnemonic lookup. */ |
| 830 | static struct hash_control *op_hash; |
| 831 | |
| 832 | /* Hash table for register lookup. */ |
| 833 | static struct hash_control *reg_hash; |
| 834 | \f |
| 835 | void |
| 836 | i386_align_code (fragS *fragP, int count) |
| 837 | { |
| 838 | /* Various efficient no-op patterns for aligning code labels. |
| 839 | Note: Don't try to assemble the instructions in the comments. |
| 840 | 0L and 0w are not legal. */ |
| 841 | static const char f32_1[] = |
| 842 | {0x90}; /* nop */ |
| 843 | static const char f32_2[] = |
| 844 | {0x66,0x90}; /* xchg %ax,%ax */ |
| 845 | static const char f32_3[] = |
| 846 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ |
| 847 | static const char f32_4[] = |
| 848 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ |
| 849 | static const char f32_5[] = |
| 850 | {0x90, /* nop */ |
| 851 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ |
| 852 | static const char f32_6[] = |
| 853 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ |
| 854 | static const char f32_7[] = |
| 855 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ |
| 856 | static const char f32_8[] = |
| 857 | {0x90, /* nop */ |
| 858 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ |
| 859 | static const char f32_9[] = |
| 860 | {0x89,0xf6, /* movl %esi,%esi */ |
| 861 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ |
| 862 | static const char f32_10[] = |
| 863 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ |
| 864 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ |
| 865 | static const char f32_11[] = |
| 866 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ |
| 867 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ |
| 868 | static const char f32_12[] = |
| 869 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ |
| 870 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ |
| 871 | static const char f32_13[] = |
| 872 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ |
| 873 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ |
| 874 | static const char f32_14[] = |
| 875 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ |
| 876 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ |
| 877 | static const char f16_3[] = |
| 878 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ |
| 879 | static const char f16_4[] = |
| 880 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ |
| 881 | static const char f16_5[] = |
| 882 | {0x90, /* nop */ |
| 883 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ |
| 884 | static const char f16_6[] = |
| 885 | {0x89,0xf6, /* mov %si,%si */ |
| 886 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ |
| 887 | static const char f16_7[] = |
| 888 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ |
| 889 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ |
| 890 | static const char f16_8[] = |
| 891 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ |
| 892 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ |
| 893 | static const char jump_31[] = |
| 894 | {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */ |
| 895 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, |
| 896 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, |
| 897 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; |
| 898 | static const char *const f32_patt[] = { |
| 899 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, |
| 900 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14 |
| 901 | }; |
| 902 | static const char *const f16_patt[] = { |
| 903 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8 |
| 904 | }; |
| 905 | /* nopl (%[re]ax) */ |
| 906 | static const char alt_3[] = |
| 907 | {0x0f,0x1f,0x00}; |
| 908 | /* nopl 0(%[re]ax) */ |
| 909 | static const char alt_4[] = |
| 910 | {0x0f,0x1f,0x40,0x00}; |
| 911 | /* nopl 0(%[re]ax,%[re]ax,1) */ |
| 912 | static const char alt_5[] = |
| 913 | {0x0f,0x1f,0x44,0x00,0x00}; |
| 914 | /* nopw 0(%[re]ax,%[re]ax,1) */ |
| 915 | static const char alt_6[] = |
| 916 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; |
| 917 | /* nopl 0L(%[re]ax) */ |
| 918 | static const char alt_7[] = |
| 919 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; |
| 920 | /* nopl 0L(%[re]ax,%[re]ax,1) */ |
| 921 | static const char alt_8[] = |
| 922 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
| 923 | /* nopw 0L(%[re]ax,%[re]ax,1) */ |
| 924 | static const char alt_9[] = |
| 925 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
| 926 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ |
| 927 | static const char alt_10[] = |
| 928 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
| 929 | /* data16 |
| 930 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ |
| 931 | static const char alt_long_11[] = |
| 932 | {0x66, |
| 933 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
| 934 | /* data16 |
| 935 | data16 |
| 936 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ |
| 937 | static const char alt_long_12[] = |
| 938 | {0x66, |
| 939 | 0x66, |
| 940 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
| 941 | /* data16 |
| 942 | data16 |
| 943 | data16 |
| 944 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ |
| 945 | static const char alt_long_13[] = |
| 946 | {0x66, |
| 947 | 0x66, |
| 948 | 0x66, |
| 949 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
| 950 | /* data16 |
| 951 | data16 |
| 952 | data16 |
| 953 | data16 |
| 954 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ |
| 955 | static const char alt_long_14[] = |
| 956 | {0x66, |
| 957 | 0x66, |
| 958 | 0x66, |
| 959 | 0x66, |
| 960 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
| 961 | /* data16 |
| 962 | data16 |
| 963 | data16 |
| 964 | data16 |
| 965 | data16 |
| 966 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ |
| 967 | static const char alt_long_15[] = |
| 968 | {0x66, |
| 969 | 0x66, |
| 970 | 0x66, |
| 971 | 0x66, |
| 972 | 0x66, |
| 973 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
| 974 | /* nopl 0(%[re]ax,%[re]ax,1) |
| 975 | nopw 0(%[re]ax,%[re]ax,1) */ |
| 976 | static const char alt_short_11[] = |
| 977 | {0x0f,0x1f,0x44,0x00,0x00, |
| 978 | 0x66,0x0f,0x1f,0x44,0x00,0x00}; |
| 979 | /* nopw 0(%[re]ax,%[re]ax,1) |
| 980 | nopw 0(%[re]ax,%[re]ax,1) */ |
| 981 | static const char alt_short_12[] = |
| 982 | {0x66,0x0f,0x1f,0x44,0x00,0x00, |
| 983 | 0x66,0x0f,0x1f,0x44,0x00,0x00}; |
| 984 | /* nopw 0(%[re]ax,%[re]ax,1) |
| 985 | nopl 0L(%[re]ax) */ |
| 986 | static const char alt_short_13[] = |
| 987 | {0x66,0x0f,0x1f,0x44,0x00,0x00, |
| 988 | 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; |
| 989 | /* nopl 0L(%[re]ax) |
| 990 | nopl 0L(%[re]ax) */ |
| 991 | static const char alt_short_14[] = |
| 992 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, |
| 993 | 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; |
| 994 | /* nopl 0L(%[re]ax) |
| 995 | nopl 0L(%[re]ax,%[re]ax,1) */ |
| 996 | static const char alt_short_15[] = |
| 997 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, |
| 998 | 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
| 999 | static const char *const alt_short_patt[] = { |
| 1000 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, |
| 1001 | alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13, |
| 1002 | alt_short_14, alt_short_15 |
| 1003 | }; |
| 1004 | static const char *const alt_long_patt[] = { |
| 1005 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, |
| 1006 | alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13, |
| 1007 | alt_long_14, alt_long_15 |
| 1008 | }; |
| 1009 | |
| 1010 | /* Only align for at least a positive non-zero boundary. */ |
| 1011 | if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE) |
| 1012 | return; |
| 1013 | |
| 1014 | /* We need to decide which NOP sequence to use for 32bit and |
| 1015 | 64bit. When -mtune= is used: |
| 1016 | |
| 1017 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
| 1018 | PROCESSOR_GENERIC32, f32_patt will be used. |
| 1019 | 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA, |
| 1020 | PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and |
| 1021 | PROCESSOR_GENERIC64, alt_long_patt will be used. |
| 1022 | 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and |
| 1023 | PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt |
| 1024 | will be used. |
| 1025 | |
| 1026 | When -mtune= isn't used, alt_long_patt will be used if |
| 1027 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
| 1028 | be used. |
| 1029 | |
| 1030 | When -march= or .arch is used, we can't use anything beyond |
| 1031 | cpu_arch_isa_flags. */ |
| 1032 | |
| 1033 | if (flag_code == CODE_16BIT) |
| 1034 | { |
| 1035 | if (count > 8) |
| 1036 | { |
| 1037 | memcpy (fragP->fr_literal + fragP->fr_fix, |
| 1038 | jump_31, count); |
| 1039 | /* Adjust jump offset. */ |
| 1040 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; |
| 1041 | } |
| 1042 | else |
| 1043 | memcpy (fragP->fr_literal + fragP->fr_fix, |
| 1044 | f16_patt[count - 1], count); |
| 1045 | } |
| 1046 | else |
| 1047 | { |
| 1048 | const char *const *patt = NULL; |
| 1049 | |
| 1050 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
| 1051 | { |
| 1052 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ |
| 1053 | switch (cpu_arch_tune) |
| 1054 | { |
| 1055 | case PROCESSOR_UNKNOWN: |
| 1056 | /* We use cpu_arch_isa_flags to check if we SHOULD |
| 1057 | optimize with nops. */ |
| 1058 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
| 1059 | patt = alt_long_patt; |
| 1060 | else |
| 1061 | patt = f32_patt; |
| 1062 | break; |
| 1063 | case PROCESSOR_PENTIUMPRO: |
| 1064 | case PROCESSOR_PENTIUM4: |
| 1065 | case PROCESSOR_NOCONA: |
| 1066 | case PROCESSOR_CORE: |
| 1067 | case PROCESSOR_CORE2: |
| 1068 | case PROCESSOR_COREI7: |
| 1069 | case PROCESSOR_L1OM: |
| 1070 | case PROCESSOR_GENERIC64: |
| 1071 | patt = alt_long_patt; |
| 1072 | break; |
| 1073 | case PROCESSOR_K6: |
| 1074 | case PROCESSOR_ATHLON: |
| 1075 | case PROCESSOR_K8: |
| 1076 | case PROCESSOR_AMDFAM10: |
| 1077 | case PROCESSOR_BDVER1: |
| 1078 | patt = alt_short_patt; |
| 1079 | break; |
| 1080 | case PROCESSOR_I386: |
| 1081 | case PROCESSOR_I486: |
| 1082 | case PROCESSOR_PENTIUM: |
| 1083 | case PROCESSOR_GENERIC32: |
| 1084 | patt = f32_patt; |
| 1085 | break; |
| 1086 | } |
| 1087 | } |
| 1088 | else |
| 1089 | { |
| 1090 | switch (fragP->tc_frag_data.tune) |
| 1091 | { |
| 1092 | case PROCESSOR_UNKNOWN: |
| 1093 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
| 1094 | PROCESSOR_UNKNOWN. */ |
| 1095 | abort (); |
| 1096 | break; |
| 1097 | |
| 1098 | case PROCESSOR_I386: |
| 1099 | case PROCESSOR_I486: |
| 1100 | case PROCESSOR_PENTIUM: |
| 1101 | case PROCESSOR_K6: |
| 1102 | case PROCESSOR_ATHLON: |
| 1103 | case PROCESSOR_K8: |
| 1104 | case PROCESSOR_AMDFAM10: |
| 1105 | case PROCESSOR_BDVER1: |
| 1106 | case PROCESSOR_GENERIC32: |
| 1107 | /* We use cpu_arch_isa_flags to check if we CAN optimize |
| 1108 | with nops. */ |
| 1109 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
| 1110 | patt = alt_short_patt; |
| 1111 | else |
| 1112 | patt = f32_patt; |
| 1113 | break; |
| 1114 | case PROCESSOR_PENTIUMPRO: |
| 1115 | case PROCESSOR_PENTIUM4: |
| 1116 | case PROCESSOR_NOCONA: |
| 1117 | case PROCESSOR_CORE: |
| 1118 | case PROCESSOR_CORE2: |
| 1119 | case PROCESSOR_COREI7: |
| 1120 | case PROCESSOR_L1OM: |
| 1121 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
| 1122 | patt = alt_long_patt; |
| 1123 | else |
| 1124 | patt = f32_patt; |
| 1125 | break; |
| 1126 | case PROCESSOR_GENERIC64: |
| 1127 | patt = alt_long_patt; |
| 1128 | break; |
| 1129 | } |
| 1130 | } |
| 1131 | |
| 1132 | if (patt == f32_patt) |
| 1133 | { |
| 1134 | /* If the padding is less than 15 bytes, we use the normal |
| 1135 | ones. Otherwise, we use a jump instruction and adjust |
| 1136 | its offset. */ |
| 1137 | int limit; |
| 1138 | |
| 1139 | /* For 64bit, the limit is 3 bytes. */ |
| 1140 | if (flag_code == CODE_64BIT |
| 1141 | && fragP->tc_frag_data.isa_flags.bitfield.cpulm) |
| 1142 | limit = 3; |
| 1143 | else |
| 1144 | limit = 15; |
| 1145 | if (count < limit) |
| 1146 | memcpy (fragP->fr_literal + fragP->fr_fix, |
| 1147 | patt[count - 1], count); |
| 1148 | else |
| 1149 | { |
| 1150 | memcpy (fragP->fr_literal + fragP->fr_fix, |
| 1151 | jump_31, count); |
| 1152 | /* Adjust jump offset. */ |
| 1153 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; |
| 1154 | } |
| 1155 | } |
| 1156 | else |
| 1157 | { |
| 1158 | /* Maximum length of an instruction is 15 byte. If the |
| 1159 | padding is greater than 15 bytes and we don't use jump, |
| 1160 | we have to break it into smaller pieces. */ |
| 1161 | int padding = count; |
| 1162 | while (padding > 15) |
| 1163 | { |
| 1164 | padding -= 15; |
| 1165 | memcpy (fragP->fr_literal + fragP->fr_fix + padding, |
| 1166 | patt [14], 15); |
| 1167 | } |
| 1168 | |
| 1169 | if (padding) |
| 1170 | memcpy (fragP->fr_literal + fragP->fr_fix, |
| 1171 | patt [padding - 1], padding); |
| 1172 | } |
| 1173 | } |
| 1174 | fragP->fr_var = count; |
| 1175 | } |
| 1176 | |
| 1177 | static INLINE int |
| 1178 | operand_type_all_zero (const union i386_operand_type *x) |
| 1179 | { |
| 1180 | switch (ARRAY_SIZE(x->array)) |
| 1181 | { |
| 1182 | case 3: |
| 1183 | if (x->array[2]) |
| 1184 | return 0; |
| 1185 | case 2: |
| 1186 | if (x->array[1]) |
| 1187 | return 0; |
| 1188 | case 1: |
| 1189 | return !x->array[0]; |
| 1190 | default: |
| 1191 | abort (); |
| 1192 | } |
| 1193 | } |
| 1194 | |
| 1195 | static INLINE void |
| 1196 | operand_type_set (union i386_operand_type *x, unsigned int v) |
| 1197 | { |
| 1198 | switch (ARRAY_SIZE(x->array)) |
| 1199 | { |
| 1200 | case 3: |
| 1201 | x->array[2] = v; |
| 1202 | case 2: |
| 1203 | x->array[1] = v; |
| 1204 | case 1: |
| 1205 | x->array[0] = v; |
| 1206 | break; |
| 1207 | default: |
| 1208 | abort (); |
| 1209 | } |
| 1210 | } |
| 1211 | |
| 1212 | static INLINE int |
| 1213 | operand_type_equal (const union i386_operand_type *x, |
| 1214 | const union i386_operand_type *y) |
| 1215 | { |
| 1216 | switch (ARRAY_SIZE(x->array)) |
| 1217 | { |
| 1218 | case 3: |
| 1219 | if (x->array[2] != y->array[2]) |
| 1220 | return 0; |
| 1221 | case 2: |
| 1222 | if (x->array[1] != y->array[1]) |
| 1223 | return 0; |
| 1224 | case 1: |
| 1225 | return x->array[0] == y->array[0]; |
| 1226 | break; |
| 1227 | default: |
| 1228 | abort (); |
| 1229 | } |
| 1230 | } |
| 1231 | |
| 1232 | static INLINE int |
| 1233 | cpu_flags_all_zero (const union i386_cpu_flags *x) |
| 1234 | { |
| 1235 | switch (ARRAY_SIZE(x->array)) |
| 1236 | { |
| 1237 | case 3: |
| 1238 | if (x->array[2]) |
| 1239 | return 0; |
| 1240 | case 2: |
| 1241 | if (x->array[1]) |
| 1242 | return 0; |
| 1243 | case 1: |
| 1244 | return !x->array[0]; |
| 1245 | default: |
| 1246 | abort (); |
| 1247 | } |
| 1248 | } |
| 1249 | |
| 1250 | static INLINE void |
| 1251 | cpu_flags_set (union i386_cpu_flags *x, unsigned int v) |
| 1252 | { |
| 1253 | switch (ARRAY_SIZE(x->array)) |
| 1254 | { |
| 1255 | case 3: |
| 1256 | x->array[2] = v; |
| 1257 | case 2: |
| 1258 | x->array[1] = v; |
| 1259 | case 1: |
| 1260 | x->array[0] = v; |
| 1261 | break; |
| 1262 | default: |
| 1263 | abort (); |
| 1264 | } |
| 1265 | } |
| 1266 | |
| 1267 | static INLINE int |
| 1268 | cpu_flags_equal (const union i386_cpu_flags *x, |
| 1269 | const union i386_cpu_flags *y) |
| 1270 | { |
| 1271 | switch (ARRAY_SIZE(x->array)) |
| 1272 | { |
| 1273 | case 3: |
| 1274 | if (x->array[2] != y->array[2]) |
| 1275 | return 0; |
| 1276 | case 2: |
| 1277 | if (x->array[1] != y->array[1]) |
| 1278 | return 0; |
| 1279 | case 1: |
| 1280 | return x->array[0] == y->array[0]; |
| 1281 | break; |
| 1282 | default: |
| 1283 | abort (); |
| 1284 | } |
| 1285 | } |
| 1286 | |
| 1287 | static INLINE int |
| 1288 | cpu_flags_check_cpu64 (i386_cpu_flags f) |
| 1289 | { |
| 1290 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) |
| 1291 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); |
| 1292 | } |
| 1293 | |
| 1294 | static INLINE i386_cpu_flags |
| 1295 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) |
| 1296 | { |
| 1297 | switch (ARRAY_SIZE (x.array)) |
| 1298 | { |
| 1299 | case 3: |
| 1300 | x.array [2] &= y.array [2]; |
| 1301 | case 2: |
| 1302 | x.array [1] &= y.array [1]; |
| 1303 | case 1: |
| 1304 | x.array [0] &= y.array [0]; |
| 1305 | break; |
| 1306 | default: |
| 1307 | abort (); |
| 1308 | } |
| 1309 | return x; |
| 1310 | } |
| 1311 | |
| 1312 | static INLINE i386_cpu_flags |
| 1313 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) |
| 1314 | { |
| 1315 | switch (ARRAY_SIZE (x.array)) |
| 1316 | { |
| 1317 | case 3: |
| 1318 | x.array [2] |= y.array [2]; |
| 1319 | case 2: |
| 1320 | x.array [1] |= y.array [1]; |
| 1321 | case 1: |
| 1322 | x.array [0] |= y.array [0]; |
| 1323 | break; |
| 1324 | default: |
| 1325 | abort (); |
| 1326 | } |
| 1327 | return x; |
| 1328 | } |
| 1329 | |
| 1330 | static INLINE i386_cpu_flags |
| 1331 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) |
| 1332 | { |
| 1333 | switch (ARRAY_SIZE (x.array)) |
| 1334 | { |
| 1335 | case 3: |
| 1336 | x.array [2] &= ~y.array [2]; |
| 1337 | case 2: |
| 1338 | x.array [1] &= ~y.array [1]; |
| 1339 | case 1: |
| 1340 | x.array [0] &= ~y.array [0]; |
| 1341 | break; |
| 1342 | default: |
| 1343 | abort (); |
| 1344 | } |
| 1345 | return x; |
| 1346 | } |
| 1347 | |
| 1348 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
| 1349 | #define CPU_FLAGS_64BIT_MATCH 0x2 |
| 1350 | #define CPU_FLAGS_AES_MATCH 0x4 |
| 1351 | #define CPU_FLAGS_PCLMUL_MATCH 0x8 |
| 1352 | #define CPU_FLAGS_AVX_MATCH 0x10 |
| 1353 | |
| 1354 | #define CPU_FLAGS_32BIT_MATCH \ |
| 1355 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \ |
| 1356 | | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH) |
| 1357 | #define CPU_FLAGS_PERFECT_MATCH \ |
| 1358 | (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH) |
| 1359 | |
| 1360 | /* Return CPU flags match bits. */ |
| 1361 | |
| 1362 | static int |
| 1363 | cpu_flags_match (const insn_template *t) |
| 1364 | { |
| 1365 | i386_cpu_flags x = t->cpu_flags; |
| 1366 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; |
| 1367 | |
| 1368 | x.bitfield.cpu64 = 0; |
| 1369 | x.bitfield.cpuno64 = 0; |
| 1370 | |
| 1371 | if (cpu_flags_all_zero (&x)) |
| 1372 | { |
| 1373 | /* This instruction is available on all archs. */ |
| 1374 | match |= CPU_FLAGS_32BIT_MATCH; |
| 1375 | } |
| 1376 | else |
| 1377 | { |
| 1378 | /* This instruction is available only on some archs. */ |
| 1379 | i386_cpu_flags cpu = cpu_arch_flags; |
| 1380 | |
| 1381 | cpu.bitfield.cpu64 = 0; |
| 1382 | cpu.bitfield.cpuno64 = 0; |
| 1383 | cpu = cpu_flags_and (x, cpu); |
| 1384 | if (!cpu_flags_all_zero (&cpu)) |
| 1385 | { |
| 1386 | if (x.bitfield.cpuavx) |
| 1387 | { |
| 1388 | /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */ |
| 1389 | if (cpu.bitfield.cpuavx) |
| 1390 | { |
| 1391 | /* Check SSE2AVX. */ |
| 1392 | if (!t->opcode_modifier.sse2avx|| sse2avx) |
| 1393 | { |
| 1394 | match |= (CPU_FLAGS_ARCH_MATCH |
| 1395 | | CPU_FLAGS_AVX_MATCH); |
| 1396 | /* Check AES. */ |
| 1397 | if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) |
| 1398 | match |= CPU_FLAGS_AES_MATCH; |
| 1399 | /* Check PCLMUL. */ |
| 1400 | if (!x.bitfield.cpupclmul |
| 1401 | || cpu.bitfield.cpupclmul) |
| 1402 | match |= CPU_FLAGS_PCLMUL_MATCH; |
| 1403 | } |
| 1404 | } |
| 1405 | else |
| 1406 | match |= CPU_FLAGS_ARCH_MATCH; |
| 1407 | } |
| 1408 | else |
| 1409 | match |= CPU_FLAGS_32BIT_MATCH; |
| 1410 | } |
| 1411 | } |
| 1412 | return match; |
| 1413 | } |
| 1414 | |
| 1415 | static INLINE i386_operand_type |
| 1416 | operand_type_and (i386_operand_type x, i386_operand_type y) |
| 1417 | { |
| 1418 | switch (ARRAY_SIZE (x.array)) |
| 1419 | { |
| 1420 | case 3: |
| 1421 | x.array [2] &= y.array [2]; |
| 1422 | case 2: |
| 1423 | x.array [1] &= y.array [1]; |
| 1424 | case 1: |
| 1425 | x.array [0] &= y.array [0]; |
| 1426 | break; |
| 1427 | default: |
| 1428 | abort (); |
| 1429 | } |
| 1430 | return x; |
| 1431 | } |
| 1432 | |
| 1433 | static INLINE i386_operand_type |
| 1434 | operand_type_or (i386_operand_type x, i386_operand_type y) |
| 1435 | { |
| 1436 | switch (ARRAY_SIZE (x.array)) |
| 1437 | { |
| 1438 | case 3: |
| 1439 | x.array [2] |= y.array [2]; |
| 1440 | case 2: |
| 1441 | x.array [1] |= y.array [1]; |
| 1442 | case 1: |
| 1443 | x.array [0] |= y.array [0]; |
| 1444 | break; |
| 1445 | default: |
| 1446 | abort (); |
| 1447 | } |
| 1448 | return x; |
| 1449 | } |
| 1450 | |
| 1451 | static INLINE i386_operand_type |
| 1452 | operand_type_xor (i386_operand_type x, i386_operand_type y) |
| 1453 | { |
| 1454 | switch (ARRAY_SIZE (x.array)) |
| 1455 | { |
| 1456 | case 3: |
| 1457 | x.array [2] ^= y.array [2]; |
| 1458 | case 2: |
| 1459 | x.array [1] ^= y.array [1]; |
| 1460 | case 1: |
| 1461 | x.array [0] ^= y.array [0]; |
| 1462 | break; |
| 1463 | default: |
| 1464 | abort (); |
| 1465 | } |
| 1466 | return x; |
| 1467 | } |
| 1468 | |
| 1469 | static const i386_operand_type acc32 = OPERAND_TYPE_ACC32; |
| 1470 | static const i386_operand_type acc64 = OPERAND_TYPE_ACC64; |
| 1471 | static const i386_operand_type control = OPERAND_TYPE_CONTROL; |
| 1472 | static const i386_operand_type inoutportreg |
| 1473 | = OPERAND_TYPE_INOUTPORTREG; |
| 1474 | static const i386_operand_type reg16_inoutportreg |
| 1475 | = OPERAND_TYPE_REG16_INOUTPORTREG; |
| 1476 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; |
| 1477 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; |
| 1478 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; |
| 1479 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; |
| 1480 | static const i386_operand_type anydisp |
| 1481 | = OPERAND_TYPE_ANYDISP; |
| 1482 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
| 1483 | static const i386_operand_type regymm = OPERAND_TYPE_REGYMM; |
| 1484 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
| 1485 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; |
| 1486 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; |
| 1487 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; |
| 1488 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; |
| 1489 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; |
| 1490 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; |
| 1491 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; |
| 1492 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; |
| 1493 | static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4; |
| 1494 | |
| 1495 | enum operand_type |
| 1496 | { |
| 1497 | reg, |
| 1498 | imm, |
| 1499 | disp, |
| 1500 | anymem |
| 1501 | }; |
| 1502 | |
| 1503 | static INLINE int |
| 1504 | operand_type_check (i386_operand_type t, enum operand_type c) |
| 1505 | { |
| 1506 | switch (c) |
| 1507 | { |
| 1508 | case reg: |
| 1509 | return (t.bitfield.reg8 |
| 1510 | || t.bitfield.reg16 |
| 1511 | || t.bitfield.reg32 |
| 1512 | || t.bitfield.reg64); |
| 1513 | |
| 1514 | case imm: |
| 1515 | return (t.bitfield.imm8 |
| 1516 | || t.bitfield.imm8s |
| 1517 | || t.bitfield.imm16 |
| 1518 | || t.bitfield.imm32 |
| 1519 | || t.bitfield.imm32s |
| 1520 | || t.bitfield.imm64); |
| 1521 | |
| 1522 | case disp: |
| 1523 | return (t.bitfield.disp8 |
| 1524 | || t.bitfield.disp16 |
| 1525 | || t.bitfield.disp32 |
| 1526 | || t.bitfield.disp32s |
| 1527 | || t.bitfield.disp64); |
| 1528 | |
| 1529 | case anymem: |
| 1530 | return (t.bitfield.disp8 |
| 1531 | || t.bitfield.disp16 |
| 1532 | || t.bitfield.disp32 |
| 1533 | || t.bitfield.disp32s |
| 1534 | || t.bitfield.disp64 |
| 1535 | || t.bitfield.baseindex); |
| 1536 | |
| 1537 | default: |
| 1538 | abort (); |
| 1539 | } |
| 1540 | |
| 1541 | return 0; |
| 1542 | } |
| 1543 | |
| 1544 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on |
| 1545 | operand J for instruction template T. */ |
| 1546 | |
| 1547 | static INLINE int |
| 1548 | match_reg_size (const insn_template *t, unsigned int j) |
| 1549 | { |
| 1550 | return !((i.types[j].bitfield.byte |
| 1551 | && !t->operand_types[j].bitfield.byte) |
| 1552 | || (i.types[j].bitfield.word |
| 1553 | && !t->operand_types[j].bitfield.word) |
| 1554 | || (i.types[j].bitfield.dword |
| 1555 | && !t->operand_types[j].bitfield.dword) |
| 1556 | || (i.types[j].bitfield.qword |
| 1557 | && !t->operand_types[j].bitfield.qword)); |
| 1558 | } |
| 1559 | |
| 1560 | /* Return 1 if there is no conflict in any size on operand J for |
| 1561 | instruction template T. */ |
| 1562 | |
| 1563 | static INLINE int |
| 1564 | match_mem_size (const insn_template *t, unsigned int j) |
| 1565 | { |
| 1566 | return (match_reg_size (t, j) |
| 1567 | && !((i.types[j].bitfield.unspecified |
| 1568 | && !t->operand_types[j].bitfield.unspecified) |
| 1569 | || (i.types[j].bitfield.fword |
| 1570 | && !t->operand_types[j].bitfield.fword) |
| 1571 | || (i.types[j].bitfield.tbyte |
| 1572 | && !t->operand_types[j].bitfield.tbyte) |
| 1573 | || (i.types[j].bitfield.xmmword |
| 1574 | && !t->operand_types[j].bitfield.xmmword) |
| 1575 | || (i.types[j].bitfield.ymmword |
| 1576 | && !t->operand_types[j].bitfield.ymmword))); |
| 1577 | } |
| 1578 | |
| 1579 | /* Return 1 if there is no size conflict on any operands for |
| 1580 | instruction template T. */ |
| 1581 | |
| 1582 | static INLINE int |
| 1583 | operand_size_match (const insn_template *t) |
| 1584 | { |
| 1585 | unsigned int j; |
| 1586 | int match = 1; |
| 1587 | |
| 1588 | /* Don't check jump instructions. */ |
| 1589 | if (t->opcode_modifier.jump |
| 1590 | || t->opcode_modifier.jumpbyte |
| 1591 | || t->opcode_modifier.jumpdword |
| 1592 | || t->opcode_modifier.jumpintersegment) |
| 1593 | return match; |
| 1594 | |
| 1595 | /* Check memory and accumulator operand size. */ |
| 1596 | for (j = 0; j < i.operands; j++) |
| 1597 | { |
| 1598 | if (t->operand_types[j].bitfield.anysize) |
| 1599 | continue; |
| 1600 | |
| 1601 | if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j)) |
| 1602 | { |
| 1603 | match = 0; |
| 1604 | break; |
| 1605 | } |
| 1606 | |
| 1607 | if (i.types[j].bitfield.mem && !match_mem_size (t, j)) |
| 1608 | { |
| 1609 | match = 0; |
| 1610 | break; |
| 1611 | } |
| 1612 | } |
| 1613 | |
| 1614 | if (match) |
| 1615 | return match; |
| 1616 | else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
| 1617 | { |
| 1618 | mismatch: |
| 1619 | i.error = operand_size_mismatch; |
| 1620 | return 0; |
| 1621 | } |
| 1622 | |
| 1623 | /* Check reverse. */ |
| 1624 | gas_assert (i.operands == 2); |
| 1625 | |
| 1626 | match = 1; |
| 1627 | for (j = 0; j < 2; j++) |
| 1628 | { |
| 1629 | if (t->operand_types[j].bitfield.acc |
| 1630 | && !match_reg_size (t, j ? 0 : 1)) |
| 1631 | goto mismatch; |
| 1632 | |
| 1633 | if (i.types[j].bitfield.mem |
| 1634 | && !match_mem_size (t, j ? 0 : 1)) |
| 1635 | goto mismatch; |
| 1636 | } |
| 1637 | |
| 1638 | return match; |
| 1639 | } |
| 1640 | |
| 1641 | static INLINE int |
| 1642 | operand_type_match (i386_operand_type overlap, |
| 1643 | i386_operand_type given) |
| 1644 | { |
| 1645 | i386_operand_type temp = overlap; |
| 1646 | |
| 1647 | temp.bitfield.jumpabsolute = 0; |
| 1648 | temp.bitfield.unspecified = 0; |
| 1649 | temp.bitfield.byte = 0; |
| 1650 | temp.bitfield.word = 0; |
| 1651 | temp.bitfield.dword = 0; |
| 1652 | temp.bitfield.fword = 0; |
| 1653 | temp.bitfield.qword = 0; |
| 1654 | temp.bitfield.tbyte = 0; |
| 1655 | temp.bitfield.xmmword = 0; |
| 1656 | temp.bitfield.ymmword = 0; |
| 1657 | if (operand_type_all_zero (&temp)) |
| 1658 | goto mismatch; |
| 1659 | |
| 1660 | if (given.bitfield.baseindex == overlap.bitfield.baseindex |
| 1661 | && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute) |
| 1662 | return 1; |
| 1663 | |
| 1664 | mismatch: |
| 1665 | i.error = operand_type_mismatch; |
| 1666 | return 0; |
| 1667 | } |
| 1668 | |
| 1669 | /* If given types g0 and g1 are registers they must be of the same type |
| 1670 | unless the expected operand type register overlap is null. |
| 1671 | Note that Acc in a template matches every size of reg. */ |
| 1672 | |
| 1673 | static INLINE int |
| 1674 | operand_type_register_match (i386_operand_type m0, |
| 1675 | i386_operand_type g0, |
| 1676 | i386_operand_type t0, |
| 1677 | i386_operand_type m1, |
| 1678 | i386_operand_type g1, |
| 1679 | i386_operand_type t1) |
| 1680 | { |
| 1681 | if (!operand_type_check (g0, reg)) |
| 1682 | return 1; |
| 1683 | |
| 1684 | if (!operand_type_check (g1, reg)) |
| 1685 | return 1; |
| 1686 | |
| 1687 | if (g0.bitfield.reg8 == g1.bitfield.reg8 |
| 1688 | && g0.bitfield.reg16 == g1.bitfield.reg16 |
| 1689 | && g0.bitfield.reg32 == g1.bitfield.reg32 |
| 1690 | && g0.bitfield.reg64 == g1.bitfield.reg64) |
| 1691 | return 1; |
| 1692 | |
| 1693 | if (m0.bitfield.acc) |
| 1694 | { |
| 1695 | t0.bitfield.reg8 = 1; |
| 1696 | t0.bitfield.reg16 = 1; |
| 1697 | t0.bitfield.reg32 = 1; |
| 1698 | t0.bitfield.reg64 = 1; |
| 1699 | } |
| 1700 | |
| 1701 | if (m1.bitfield.acc) |
| 1702 | { |
| 1703 | t1.bitfield.reg8 = 1; |
| 1704 | t1.bitfield.reg16 = 1; |
| 1705 | t1.bitfield.reg32 = 1; |
| 1706 | t1.bitfield.reg64 = 1; |
| 1707 | } |
| 1708 | |
| 1709 | if (!(t0.bitfield.reg8 & t1.bitfield.reg8) |
| 1710 | && !(t0.bitfield.reg16 & t1.bitfield.reg16) |
| 1711 | && !(t0.bitfield.reg32 & t1.bitfield.reg32) |
| 1712 | && !(t0.bitfield.reg64 & t1.bitfield.reg64)) |
| 1713 | return 1; |
| 1714 | |
| 1715 | i.error = register_type_mismatch; |
| 1716 | |
| 1717 | return 0; |
| 1718 | } |
| 1719 | |
| 1720 | static INLINE unsigned int |
| 1721 | mode_from_disp_size (i386_operand_type t) |
| 1722 | { |
| 1723 | if (t.bitfield.disp8) |
| 1724 | return 1; |
| 1725 | else if (t.bitfield.disp16 |
| 1726 | || t.bitfield.disp32 |
| 1727 | || t.bitfield.disp32s) |
| 1728 | return 2; |
| 1729 | else |
| 1730 | return 0; |
| 1731 | } |
| 1732 | |
| 1733 | static INLINE int |
| 1734 | fits_in_signed_byte (offsetT num) |
| 1735 | { |
| 1736 | return (num >= -128) && (num <= 127); |
| 1737 | } |
| 1738 | |
| 1739 | static INLINE int |
| 1740 | fits_in_unsigned_byte (offsetT num) |
| 1741 | { |
| 1742 | return (num & 0xff) == num; |
| 1743 | } |
| 1744 | |
| 1745 | static INLINE int |
| 1746 | fits_in_unsigned_word (offsetT num) |
| 1747 | { |
| 1748 | return (num & 0xffff) == num; |
| 1749 | } |
| 1750 | |
| 1751 | static INLINE int |
| 1752 | fits_in_signed_word (offsetT num) |
| 1753 | { |
| 1754 | return (-32768 <= num) && (num <= 32767); |
| 1755 | } |
| 1756 | |
| 1757 | static INLINE int |
| 1758 | fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED) |
| 1759 | { |
| 1760 | #ifndef BFD64 |
| 1761 | return 1; |
| 1762 | #else |
| 1763 | return (!(((offsetT) -1 << 31) & num) |
| 1764 | || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); |
| 1765 | #endif |
| 1766 | } /* fits_in_signed_long() */ |
| 1767 | |
| 1768 | static INLINE int |
| 1769 | fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED) |
| 1770 | { |
| 1771 | #ifndef BFD64 |
| 1772 | return 1; |
| 1773 | #else |
| 1774 | return (num & (((offsetT) 2 << 31) - 1)) == num; |
| 1775 | #endif |
| 1776 | } /* fits_in_unsigned_long() */ |
| 1777 | |
| 1778 | static INLINE int |
| 1779 | fits_in_imm4 (offsetT num) |
| 1780 | { |
| 1781 | return (num & 0xf) == num; |
| 1782 | } |
| 1783 | |
| 1784 | static i386_operand_type |
| 1785 | smallest_imm_type (offsetT num) |
| 1786 | { |
| 1787 | i386_operand_type t; |
| 1788 | |
| 1789 | operand_type_set (&t, 0); |
| 1790 | t.bitfield.imm64 = 1; |
| 1791 | |
| 1792 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) |
| 1793 | { |
| 1794 | /* This code is disabled on the 486 because all the Imm1 forms |
| 1795 | in the opcode table are slower on the i486. They're the |
| 1796 | versions with the implicitly specified single-position |
| 1797 | displacement, which has another syntax if you really want to |
| 1798 | use that form. */ |
| 1799 | t.bitfield.imm1 = 1; |
| 1800 | t.bitfield.imm8 = 1; |
| 1801 | t.bitfield.imm8s = 1; |
| 1802 | t.bitfield.imm16 = 1; |
| 1803 | t.bitfield.imm32 = 1; |
| 1804 | t.bitfield.imm32s = 1; |
| 1805 | } |
| 1806 | else if (fits_in_signed_byte (num)) |
| 1807 | { |
| 1808 | t.bitfield.imm8 = 1; |
| 1809 | t.bitfield.imm8s = 1; |
| 1810 | t.bitfield.imm16 = 1; |
| 1811 | t.bitfield.imm32 = 1; |
| 1812 | t.bitfield.imm32s = 1; |
| 1813 | } |
| 1814 | else if (fits_in_unsigned_byte (num)) |
| 1815 | { |
| 1816 | t.bitfield.imm8 = 1; |
| 1817 | t.bitfield.imm16 = 1; |
| 1818 | t.bitfield.imm32 = 1; |
| 1819 | t.bitfield.imm32s = 1; |
| 1820 | } |
| 1821 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) |
| 1822 | { |
| 1823 | t.bitfield.imm16 = 1; |
| 1824 | t.bitfield.imm32 = 1; |
| 1825 | t.bitfield.imm32s = 1; |
| 1826 | } |
| 1827 | else if (fits_in_signed_long (num)) |
| 1828 | { |
| 1829 | t.bitfield.imm32 = 1; |
| 1830 | t.bitfield.imm32s = 1; |
| 1831 | } |
| 1832 | else if (fits_in_unsigned_long (num)) |
| 1833 | t.bitfield.imm32 = 1; |
| 1834 | |
| 1835 | return t; |
| 1836 | } |
| 1837 | |
| 1838 | static offsetT |
| 1839 | offset_in_range (offsetT val, int size) |
| 1840 | { |
| 1841 | addressT mask; |
| 1842 | |
| 1843 | switch (size) |
| 1844 | { |
| 1845 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
| 1846 | case 2: mask = ((addressT) 1 << 16) - 1; break; |
| 1847 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
| 1848 | #ifdef BFD64 |
| 1849 | case 8: mask = ((addressT) 2 << 63) - 1; break; |
| 1850 | #endif |
| 1851 | default: abort (); |
| 1852 | } |
| 1853 | |
| 1854 | #ifdef BFD64 |
| 1855 | /* If BFD64, sign extend val for 32bit address mode. */ |
| 1856 | if (flag_code != CODE_64BIT |
| 1857 | || i.prefix[ADDR_PREFIX]) |
| 1858 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
| 1859 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); |
| 1860 | #endif |
| 1861 | |
| 1862 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
| 1863 | { |
| 1864 | char buf1[40], buf2[40]; |
| 1865 | |
| 1866 | sprint_value (buf1, val); |
| 1867 | sprint_value (buf2, val & mask); |
| 1868 | as_warn (_("%s shortened to %s"), buf1, buf2); |
| 1869 | } |
| 1870 | return val & mask; |
| 1871 | } |
| 1872 | |
| 1873 | enum PREFIX_GROUP |
| 1874 | { |
| 1875 | PREFIX_EXIST = 0, |
| 1876 | PREFIX_LOCK, |
| 1877 | PREFIX_REP, |
| 1878 | PREFIX_OTHER |
| 1879 | }; |
| 1880 | |
| 1881 | /* Returns |
| 1882 | a. PREFIX_EXIST if attempting to add a prefix where one from the |
| 1883 | same class already exists. |
| 1884 | b. PREFIX_LOCK if lock prefix is added. |
| 1885 | c. PREFIX_REP if rep/repne prefix is added. |
| 1886 | d. PREFIX_OTHER if other prefix is added. |
| 1887 | */ |
| 1888 | |
| 1889 | static enum PREFIX_GROUP |
| 1890 | add_prefix (unsigned int prefix) |
| 1891 | { |
| 1892 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
| 1893 | unsigned int q; |
| 1894 | |
| 1895 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
| 1896 | && flag_code == CODE_64BIT) |
| 1897 | { |
| 1898 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
| 1899 | || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B)) |
| 1900 | && (prefix & (REX_R | REX_X | REX_B)))) |
| 1901 | ret = PREFIX_EXIST; |
| 1902 | q = REX_PREFIX; |
| 1903 | } |
| 1904 | else |
| 1905 | { |
| 1906 | switch (prefix) |
| 1907 | { |
| 1908 | default: |
| 1909 | abort (); |
| 1910 | |
| 1911 | case CS_PREFIX_OPCODE: |
| 1912 | case DS_PREFIX_OPCODE: |
| 1913 | case ES_PREFIX_OPCODE: |
| 1914 | case FS_PREFIX_OPCODE: |
| 1915 | case GS_PREFIX_OPCODE: |
| 1916 | case SS_PREFIX_OPCODE: |
| 1917 | q = SEG_PREFIX; |
| 1918 | break; |
| 1919 | |
| 1920 | case REPNE_PREFIX_OPCODE: |
| 1921 | case REPE_PREFIX_OPCODE: |
| 1922 | q = REP_PREFIX; |
| 1923 | ret = PREFIX_REP; |
| 1924 | break; |
| 1925 | |
| 1926 | case LOCK_PREFIX_OPCODE: |
| 1927 | q = LOCK_PREFIX; |
| 1928 | ret = PREFIX_LOCK; |
| 1929 | break; |
| 1930 | |
| 1931 | case FWAIT_OPCODE: |
| 1932 | q = WAIT_PREFIX; |
| 1933 | break; |
| 1934 | |
| 1935 | case ADDR_PREFIX_OPCODE: |
| 1936 | q = ADDR_PREFIX; |
| 1937 | break; |
| 1938 | |
| 1939 | case DATA_PREFIX_OPCODE: |
| 1940 | q = DATA_PREFIX; |
| 1941 | break; |
| 1942 | } |
| 1943 | if (i.prefix[q] != 0) |
| 1944 | ret = PREFIX_EXIST; |
| 1945 | } |
| 1946 | |
| 1947 | if (ret) |
| 1948 | { |
| 1949 | if (!i.prefix[q]) |
| 1950 | ++i.prefixes; |
| 1951 | i.prefix[q] |= prefix; |
| 1952 | } |
| 1953 | else |
| 1954 | as_bad (_("same type of prefix used twice")); |
| 1955 | |
| 1956 | return ret; |
| 1957 | } |
| 1958 | |
| 1959 | static void |
| 1960 | update_code_flag (int value, int check) |
| 1961 | { |
| 1962 | PRINTF_LIKE ((*as_error)); |
| 1963 | |
| 1964 | flag_code = (enum flag_code) value; |
| 1965 | if (flag_code == CODE_64BIT) |
| 1966 | { |
| 1967 | cpu_arch_flags.bitfield.cpu64 = 1; |
| 1968 | cpu_arch_flags.bitfield.cpuno64 = 0; |
| 1969 | } |
| 1970 | else |
| 1971 | { |
| 1972 | cpu_arch_flags.bitfield.cpu64 = 0; |
| 1973 | cpu_arch_flags.bitfield.cpuno64 = 1; |
| 1974 | } |
| 1975 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) |
| 1976 | { |
| 1977 | if (check) |
| 1978 | as_error = as_fatal; |
| 1979 | else |
| 1980 | as_error = as_bad; |
| 1981 | (*as_error) (_("64bit mode not supported on `%s'."), |
| 1982 | cpu_arch_name ? cpu_arch_name : default_arch); |
| 1983 | } |
| 1984 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
| 1985 | { |
| 1986 | if (check) |
| 1987 | as_error = as_fatal; |
| 1988 | else |
| 1989 | as_error = as_bad; |
| 1990 | (*as_error) (_("32bit mode not supported on `%s'."), |
| 1991 | cpu_arch_name ? cpu_arch_name : default_arch); |
| 1992 | } |
| 1993 | stackop_size = '\0'; |
| 1994 | } |
| 1995 | |
| 1996 | static void |
| 1997 | set_code_flag (int value) |
| 1998 | { |
| 1999 | update_code_flag (value, 0); |
| 2000 | } |
| 2001 | |
| 2002 | static void |
| 2003 | set_16bit_gcc_code_flag (int new_code_flag) |
| 2004 | { |
| 2005 | flag_code = (enum flag_code) new_code_flag; |
| 2006 | if (flag_code != CODE_16BIT) |
| 2007 | abort (); |
| 2008 | cpu_arch_flags.bitfield.cpu64 = 0; |
| 2009 | cpu_arch_flags.bitfield.cpuno64 = 1; |
| 2010 | stackop_size = LONG_MNEM_SUFFIX; |
| 2011 | } |
| 2012 | |
| 2013 | static void |
| 2014 | set_intel_syntax (int syntax_flag) |
| 2015 | { |
| 2016 | /* Find out if register prefixing is specified. */ |
| 2017 | int ask_naked_reg = 0; |
| 2018 | |
| 2019 | SKIP_WHITESPACE (); |
| 2020 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
| 2021 | { |
| 2022 | char *string = input_line_pointer; |
| 2023 | int e = get_symbol_end (); |
| 2024 | |
| 2025 | if (strcmp (string, "prefix") == 0) |
| 2026 | ask_naked_reg = 1; |
| 2027 | else if (strcmp (string, "noprefix") == 0) |
| 2028 | ask_naked_reg = -1; |
| 2029 | else |
| 2030 | as_bad (_("bad argument to syntax directive.")); |
| 2031 | *input_line_pointer = e; |
| 2032 | } |
| 2033 | demand_empty_rest_of_line (); |
| 2034 | |
| 2035 | intel_syntax = syntax_flag; |
| 2036 | |
| 2037 | if (ask_naked_reg == 0) |
| 2038 | allow_naked_reg = (intel_syntax |
| 2039 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); |
| 2040 | else |
| 2041 | allow_naked_reg = (ask_naked_reg < 0); |
| 2042 | |
| 2043 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
| 2044 | |
| 2045 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
| 2046 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
| 2047 | register_prefix = allow_naked_reg ? "" : "%"; |
| 2048 | } |
| 2049 | |
| 2050 | static void |
| 2051 | set_intel_mnemonic (int mnemonic_flag) |
| 2052 | { |
| 2053 | intel_mnemonic = mnemonic_flag; |
| 2054 | } |
| 2055 | |
| 2056 | static void |
| 2057 | set_allow_index_reg (int flag) |
| 2058 | { |
| 2059 | allow_index_reg = flag; |
| 2060 | } |
| 2061 | |
| 2062 | static void |
| 2063 | set_sse_check (int dummy ATTRIBUTE_UNUSED) |
| 2064 | { |
| 2065 | SKIP_WHITESPACE (); |
| 2066 | |
| 2067 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
| 2068 | { |
| 2069 | char *string = input_line_pointer; |
| 2070 | int e = get_symbol_end (); |
| 2071 | |
| 2072 | if (strcmp (string, "none") == 0) |
| 2073 | sse_check = sse_check_none; |
| 2074 | else if (strcmp (string, "warning") == 0) |
| 2075 | sse_check = sse_check_warning; |
| 2076 | else if (strcmp (string, "error") == 0) |
| 2077 | sse_check = sse_check_error; |
| 2078 | else |
| 2079 | as_bad (_("bad argument to sse_check directive.")); |
| 2080 | *input_line_pointer = e; |
| 2081 | } |
| 2082 | else |
| 2083 | as_bad (_("missing argument for sse_check directive")); |
| 2084 | |
| 2085 | demand_empty_rest_of_line (); |
| 2086 | } |
| 2087 | |
| 2088 | static void |
| 2089 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, |
| 2090 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
| 2091 | { |
| 2092 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 2093 | static const char *arch; |
| 2094 | |
| 2095 | /* Intel LIOM is only supported on ELF. */ |
| 2096 | if (!IS_ELF) |
| 2097 | return; |
| 2098 | |
| 2099 | if (!arch) |
| 2100 | { |
| 2101 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise |
| 2102 | use default_arch. */ |
| 2103 | arch = cpu_arch_name; |
| 2104 | if (!arch) |
| 2105 | arch = default_arch; |
| 2106 | } |
| 2107 | |
| 2108 | /* If we are targeting Intel L1OM, we must enable it. */ |
| 2109 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
| 2110 | || new_flag.bitfield.cpul1om) |
| 2111 | return; |
| 2112 | |
| 2113 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
| 2114 | #endif |
| 2115 | } |
| 2116 | |
| 2117 | static void |
| 2118 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
| 2119 | { |
| 2120 | SKIP_WHITESPACE (); |
| 2121 | |
| 2122 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
| 2123 | { |
| 2124 | char *string = input_line_pointer; |
| 2125 | int e = get_symbol_end (); |
| 2126 | unsigned int j; |
| 2127 | i386_cpu_flags flags; |
| 2128 | |
| 2129 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
| 2130 | { |
| 2131 | if (strcmp (string, cpu_arch[j].name) == 0) |
| 2132 | { |
| 2133 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
| 2134 | |
| 2135 | if (*string != '.') |
| 2136 | { |
| 2137 | cpu_arch_name = cpu_arch[j].name; |
| 2138 | cpu_sub_arch_name = NULL; |
| 2139 | cpu_arch_flags = cpu_arch[j].flags; |
| 2140 | if (flag_code == CODE_64BIT) |
| 2141 | { |
| 2142 | cpu_arch_flags.bitfield.cpu64 = 1; |
| 2143 | cpu_arch_flags.bitfield.cpuno64 = 0; |
| 2144 | } |
| 2145 | else |
| 2146 | { |
| 2147 | cpu_arch_flags.bitfield.cpu64 = 0; |
| 2148 | cpu_arch_flags.bitfield.cpuno64 = 1; |
| 2149 | } |
| 2150 | cpu_arch_isa = cpu_arch[j].type; |
| 2151 | cpu_arch_isa_flags = cpu_arch[j].flags; |
| 2152 | if (!cpu_arch_tune_set) |
| 2153 | { |
| 2154 | cpu_arch_tune = cpu_arch_isa; |
| 2155 | cpu_arch_tune_flags = cpu_arch_isa_flags; |
| 2156 | } |
| 2157 | break; |
| 2158 | } |
| 2159 | |
| 2160 | if (!cpu_arch[j].negated) |
| 2161 | flags = cpu_flags_or (cpu_arch_flags, |
| 2162 | cpu_arch[j].flags); |
| 2163 | else |
| 2164 | flags = cpu_flags_and_not (cpu_arch_flags, |
| 2165 | cpu_arch[j].flags); |
| 2166 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
| 2167 | { |
| 2168 | if (cpu_sub_arch_name) |
| 2169 | { |
| 2170 | char *name = cpu_sub_arch_name; |
| 2171 | cpu_sub_arch_name = concat (name, |
| 2172 | cpu_arch[j].name, |
| 2173 | (const char *) NULL); |
| 2174 | free (name); |
| 2175 | } |
| 2176 | else |
| 2177 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
| 2178 | cpu_arch_flags = flags; |
| 2179 | } |
| 2180 | *input_line_pointer = e; |
| 2181 | demand_empty_rest_of_line (); |
| 2182 | return; |
| 2183 | } |
| 2184 | } |
| 2185 | if (j >= ARRAY_SIZE (cpu_arch)) |
| 2186 | as_bad (_("no such architecture: `%s'"), string); |
| 2187 | |
| 2188 | *input_line_pointer = e; |
| 2189 | } |
| 2190 | else |
| 2191 | as_bad (_("missing cpu architecture")); |
| 2192 | |
| 2193 | no_cond_jump_promotion = 0; |
| 2194 | if (*input_line_pointer == ',' |
| 2195 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
| 2196 | { |
| 2197 | char *string = ++input_line_pointer; |
| 2198 | int e = get_symbol_end (); |
| 2199 | |
| 2200 | if (strcmp (string, "nojumps") == 0) |
| 2201 | no_cond_jump_promotion = 1; |
| 2202 | else if (strcmp (string, "jumps") == 0) |
| 2203 | ; |
| 2204 | else |
| 2205 | as_bad (_("no such architecture modifier: `%s'"), string); |
| 2206 | |
| 2207 | *input_line_pointer = e; |
| 2208 | } |
| 2209 | |
| 2210 | demand_empty_rest_of_line (); |
| 2211 | } |
| 2212 | |
| 2213 | enum bfd_architecture |
| 2214 | i386_arch (void) |
| 2215 | { |
| 2216 | if (cpu_arch_isa == PROCESSOR_L1OM) |
| 2217 | { |
| 2218 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
| 2219 | || flag_code != CODE_64BIT) |
| 2220 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
| 2221 | return bfd_arch_l1om; |
| 2222 | } |
| 2223 | else |
| 2224 | return bfd_arch_i386; |
| 2225 | } |
| 2226 | |
| 2227 | unsigned long |
| 2228 | i386_mach () |
| 2229 | { |
| 2230 | if (!strncmp (default_arch, "x86_64", 6)) |
| 2231 | { |
| 2232 | if (cpu_arch_isa == PROCESSOR_L1OM) |
| 2233 | { |
| 2234 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
| 2235 | || default_arch[6] != '\0') |
| 2236 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
| 2237 | return bfd_mach_l1om; |
| 2238 | } |
| 2239 | else if (default_arch[6] == '\0') |
| 2240 | return bfd_mach_x86_64; |
| 2241 | else |
| 2242 | return bfd_mach_x64_32; |
| 2243 | } |
| 2244 | else if (!strcmp (default_arch, "i386")) |
| 2245 | return bfd_mach_i386_i386; |
| 2246 | else |
| 2247 | as_fatal (_("Unknown architecture")); |
| 2248 | } |
| 2249 | \f |
| 2250 | void |
| 2251 | md_begin () |
| 2252 | { |
| 2253 | const char *hash_err; |
| 2254 | |
| 2255 | /* Initialize op_hash hash table. */ |
| 2256 | op_hash = hash_new (); |
| 2257 | |
| 2258 | { |
| 2259 | const insn_template *optab; |
| 2260 | templates *core_optab; |
| 2261 | |
| 2262 | /* Setup for loop. */ |
| 2263 | optab = i386_optab; |
| 2264 | core_optab = (templates *) xmalloc (sizeof (templates)); |
| 2265 | core_optab->start = optab; |
| 2266 | |
| 2267 | while (1) |
| 2268 | { |
| 2269 | ++optab; |
| 2270 | if (optab->name == NULL |
| 2271 | || strcmp (optab->name, (optab - 1)->name) != 0) |
| 2272 | { |
| 2273 | /* different name --> ship out current template list; |
| 2274 | add to hash table; & begin anew. */ |
| 2275 | core_optab->end = optab; |
| 2276 | hash_err = hash_insert (op_hash, |
| 2277 | (optab - 1)->name, |
| 2278 | (void *) core_optab); |
| 2279 | if (hash_err) |
| 2280 | { |
| 2281 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
| 2282 | (optab - 1)->name, |
| 2283 | hash_err); |
| 2284 | } |
| 2285 | if (optab->name == NULL) |
| 2286 | break; |
| 2287 | core_optab = (templates *) xmalloc (sizeof (templates)); |
| 2288 | core_optab->start = optab; |
| 2289 | } |
| 2290 | } |
| 2291 | } |
| 2292 | |
| 2293 | /* Initialize reg_hash hash table. */ |
| 2294 | reg_hash = hash_new (); |
| 2295 | { |
| 2296 | const reg_entry *regtab; |
| 2297 | unsigned int regtab_size = i386_regtab_size; |
| 2298 | |
| 2299 | for (regtab = i386_regtab; regtab_size--; regtab++) |
| 2300 | { |
| 2301 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
| 2302 | if (hash_err) |
| 2303 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
| 2304 | regtab->reg_name, |
| 2305 | hash_err); |
| 2306 | } |
| 2307 | } |
| 2308 | |
| 2309 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
| 2310 | { |
| 2311 | int c; |
| 2312 | char *p; |
| 2313 | |
| 2314 | for (c = 0; c < 256; c++) |
| 2315 | { |
| 2316 | if (ISDIGIT (c)) |
| 2317 | { |
| 2318 | digit_chars[c] = c; |
| 2319 | mnemonic_chars[c] = c; |
| 2320 | register_chars[c] = c; |
| 2321 | operand_chars[c] = c; |
| 2322 | } |
| 2323 | else if (ISLOWER (c)) |
| 2324 | { |
| 2325 | mnemonic_chars[c] = c; |
| 2326 | register_chars[c] = c; |
| 2327 | operand_chars[c] = c; |
| 2328 | } |
| 2329 | else if (ISUPPER (c)) |
| 2330 | { |
| 2331 | mnemonic_chars[c] = TOLOWER (c); |
| 2332 | register_chars[c] = mnemonic_chars[c]; |
| 2333 | operand_chars[c] = c; |
| 2334 | } |
| 2335 | |
| 2336 | if (ISALPHA (c) || ISDIGIT (c)) |
| 2337 | identifier_chars[c] = c; |
| 2338 | else if (c >= 128) |
| 2339 | { |
| 2340 | identifier_chars[c] = c; |
| 2341 | operand_chars[c] = c; |
| 2342 | } |
| 2343 | } |
| 2344 | |
| 2345 | #ifdef LEX_AT |
| 2346 | identifier_chars['@'] = '@'; |
| 2347 | #endif |
| 2348 | #ifdef LEX_QM |
| 2349 | identifier_chars['?'] = '?'; |
| 2350 | operand_chars['?'] = '?'; |
| 2351 | #endif |
| 2352 | digit_chars['-'] = '-'; |
| 2353 | mnemonic_chars['_'] = '_'; |
| 2354 | mnemonic_chars['-'] = '-'; |
| 2355 | mnemonic_chars['.'] = '.'; |
| 2356 | identifier_chars['_'] = '_'; |
| 2357 | identifier_chars['.'] = '.'; |
| 2358 | |
| 2359 | for (p = operand_special_chars; *p != '\0'; p++) |
| 2360 | operand_chars[(unsigned char) *p] = *p; |
| 2361 | } |
| 2362 | |
| 2363 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 2364 | if (IS_ELF) |
| 2365 | { |
| 2366 | record_alignment (text_section, 2); |
| 2367 | record_alignment (data_section, 2); |
| 2368 | record_alignment (bss_section, 2); |
| 2369 | } |
| 2370 | #endif |
| 2371 | |
| 2372 | if (flag_code == CODE_64BIT) |
| 2373 | { |
| 2374 | #if defined (OBJ_COFF) && defined (TE_PE) |
| 2375 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour |
| 2376 | ? 32 : 16); |
| 2377 | #else |
| 2378 | x86_dwarf2_return_column = 16; |
| 2379 | #endif |
| 2380 | x86_cie_data_alignment = -8; |
| 2381 | } |
| 2382 | else |
| 2383 | { |
| 2384 | x86_dwarf2_return_column = 8; |
| 2385 | x86_cie_data_alignment = -4; |
| 2386 | } |
| 2387 | } |
| 2388 | |
| 2389 | void |
| 2390 | i386_print_statistics (FILE *file) |
| 2391 | { |
| 2392 | hash_print_statistics (file, "i386 opcode", op_hash); |
| 2393 | hash_print_statistics (file, "i386 register", reg_hash); |
| 2394 | } |
| 2395 | \f |
| 2396 | #ifdef DEBUG386 |
| 2397 | |
| 2398 | /* Debugging routines for md_assemble. */ |
| 2399 | static void pte (insn_template *); |
| 2400 | static void pt (i386_operand_type); |
| 2401 | static void pe (expressionS *); |
| 2402 | static void ps (symbolS *); |
| 2403 | |
| 2404 | static void |
| 2405 | pi (char *line, i386_insn *x) |
| 2406 | { |
| 2407 | unsigned int j; |
| 2408 | |
| 2409 | fprintf (stdout, "%s: template ", line); |
| 2410 | pte (&x->tm); |
| 2411 | fprintf (stdout, " address: base %s index %s scale %x\n", |
| 2412 | x->base_reg ? x->base_reg->reg_name : "none", |
| 2413 | x->index_reg ? x->index_reg->reg_name : "none", |
| 2414 | x->log2_scale_factor); |
| 2415 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", |
| 2416 | x->rm.mode, x->rm.reg, x->rm.regmem); |
| 2417 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
| 2418 | x->sib.base, x->sib.index, x->sib.scale); |
| 2419 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", |
| 2420 | (x->rex & REX_W) != 0, |
| 2421 | (x->rex & REX_R) != 0, |
| 2422 | (x->rex & REX_X) != 0, |
| 2423 | (x->rex & REX_B) != 0); |
| 2424 | for (j = 0; j < x->operands; j++) |
| 2425 | { |
| 2426 | fprintf (stdout, " #%d: ", j + 1); |
| 2427 | pt (x->types[j]); |
| 2428 | fprintf (stdout, "\n"); |
| 2429 | if (x->types[j].bitfield.reg8 |
| 2430 | || x->types[j].bitfield.reg16 |
| 2431 | || x->types[j].bitfield.reg32 |
| 2432 | || x->types[j].bitfield.reg64 |
| 2433 | || x->types[j].bitfield.regmmx |
| 2434 | || x->types[j].bitfield.regxmm |
| 2435 | || x->types[j].bitfield.regymm |
| 2436 | || x->types[j].bitfield.sreg2 |
| 2437 | || x->types[j].bitfield.sreg3 |
| 2438 | || x->types[j].bitfield.control |
| 2439 | || x->types[j].bitfield.debug |
| 2440 | || x->types[j].bitfield.test) |
| 2441 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); |
| 2442 | if (operand_type_check (x->types[j], imm)) |
| 2443 | pe (x->op[j].imms); |
| 2444 | if (operand_type_check (x->types[j], disp)) |
| 2445 | pe (x->op[j].disps); |
| 2446 | } |
| 2447 | } |
| 2448 | |
| 2449 | static void |
| 2450 | pte (insn_template *t) |
| 2451 | { |
| 2452 | unsigned int j; |
| 2453 | fprintf (stdout, " %d operands ", t->operands); |
| 2454 | fprintf (stdout, "opcode %x ", t->base_opcode); |
| 2455 | if (t->extension_opcode != None) |
| 2456 | fprintf (stdout, "ext %x ", t->extension_opcode); |
| 2457 | if (t->opcode_modifier.d) |
| 2458 | fprintf (stdout, "D"); |
| 2459 | if (t->opcode_modifier.w) |
| 2460 | fprintf (stdout, "W"); |
| 2461 | fprintf (stdout, "\n"); |
| 2462 | for (j = 0; j < t->operands; j++) |
| 2463 | { |
| 2464 | fprintf (stdout, " #%d type ", j + 1); |
| 2465 | pt (t->operand_types[j]); |
| 2466 | fprintf (stdout, "\n"); |
| 2467 | } |
| 2468 | } |
| 2469 | |
| 2470 | static void |
| 2471 | pe (expressionS *e) |
| 2472 | { |
| 2473 | fprintf (stdout, " operation %d\n", e->X_op); |
| 2474 | fprintf (stdout, " add_number %ld (%lx)\n", |
| 2475 | (long) e->X_add_number, (long) e->X_add_number); |
| 2476 | if (e->X_add_symbol) |
| 2477 | { |
| 2478 | fprintf (stdout, " add_symbol "); |
| 2479 | ps (e->X_add_symbol); |
| 2480 | fprintf (stdout, "\n"); |
| 2481 | } |
| 2482 | if (e->X_op_symbol) |
| 2483 | { |
| 2484 | fprintf (stdout, " op_symbol "); |
| 2485 | ps (e->X_op_symbol); |
| 2486 | fprintf (stdout, "\n"); |
| 2487 | } |
| 2488 | } |
| 2489 | |
| 2490 | static void |
| 2491 | ps (symbolS *s) |
| 2492 | { |
| 2493 | fprintf (stdout, "%s type %s%s", |
| 2494 | S_GET_NAME (s), |
| 2495 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", |
| 2496 | segment_name (S_GET_SEGMENT (s))); |
| 2497 | } |
| 2498 | |
| 2499 | static struct type_name |
| 2500 | { |
| 2501 | i386_operand_type mask; |
| 2502 | const char *name; |
| 2503 | } |
| 2504 | const type_names[] = |
| 2505 | { |
| 2506 | { OPERAND_TYPE_REG8, "r8" }, |
| 2507 | { OPERAND_TYPE_REG16, "r16" }, |
| 2508 | { OPERAND_TYPE_REG32, "r32" }, |
| 2509 | { OPERAND_TYPE_REG64, "r64" }, |
| 2510 | { OPERAND_TYPE_IMM8, "i8" }, |
| 2511 | { OPERAND_TYPE_IMM8, "i8s" }, |
| 2512 | { OPERAND_TYPE_IMM16, "i16" }, |
| 2513 | { OPERAND_TYPE_IMM32, "i32" }, |
| 2514 | { OPERAND_TYPE_IMM32S, "i32s" }, |
| 2515 | { OPERAND_TYPE_IMM64, "i64" }, |
| 2516 | { OPERAND_TYPE_IMM1, "i1" }, |
| 2517 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, |
| 2518 | { OPERAND_TYPE_DISP8, "d8" }, |
| 2519 | { OPERAND_TYPE_DISP16, "d16" }, |
| 2520 | { OPERAND_TYPE_DISP32, "d32" }, |
| 2521 | { OPERAND_TYPE_DISP32S, "d32s" }, |
| 2522 | { OPERAND_TYPE_DISP64, "d64" }, |
| 2523 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, |
| 2524 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, |
| 2525 | { OPERAND_TYPE_CONTROL, "control reg" }, |
| 2526 | { OPERAND_TYPE_TEST, "test reg" }, |
| 2527 | { OPERAND_TYPE_DEBUG, "debug reg" }, |
| 2528 | { OPERAND_TYPE_FLOATREG, "FReg" }, |
| 2529 | { OPERAND_TYPE_FLOATACC, "FAcc" }, |
| 2530 | { OPERAND_TYPE_SREG2, "SReg2" }, |
| 2531 | { OPERAND_TYPE_SREG3, "SReg3" }, |
| 2532 | { OPERAND_TYPE_ACC, "Acc" }, |
| 2533 | { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, |
| 2534 | { OPERAND_TYPE_REGMMX, "rMMX" }, |
| 2535 | { OPERAND_TYPE_REGXMM, "rXMM" }, |
| 2536 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
| 2537 | { OPERAND_TYPE_ESSEG, "es" }, |
| 2538 | }; |
| 2539 | |
| 2540 | static void |
| 2541 | pt (i386_operand_type t) |
| 2542 | { |
| 2543 | unsigned int j; |
| 2544 | i386_operand_type a; |
| 2545 | |
| 2546 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
| 2547 | { |
| 2548 | a = operand_type_and (t, type_names[j].mask); |
| 2549 | if (!operand_type_all_zero (&a)) |
| 2550 | fprintf (stdout, "%s, ", type_names[j].name); |
| 2551 | } |
| 2552 | fflush (stdout); |
| 2553 | } |
| 2554 | |
| 2555 | #endif /* DEBUG386 */ |
| 2556 | \f |
| 2557 | static bfd_reloc_code_real_type |
| 2558 | reloc (unsigned int size, |
| 2559 | int pcrel, |
| 2560 | int sign, |
| 2561 | bfd_reloc_code_real_type other) |
| 2562 | { |
| 2563 | if (other != NO_RELOC) |
| 2564 | { |
| 2565 | reloc_howto_type *rel; |
| 2566 | |
| 2567 | if (size == 8) |
| 2568 | switch (other) |
| 2569 | { |
| 2570 | case BFD_RELOC_X86_64_GOT32: |
| 2571 | return BFD_RELOC_X86_64_GOT64; |
| 2572 | break; |
| 2573 | case BFD_RELOC_X86_64_PLTOFF64: |
| 2574 | return BFD_RELOC_X86_64_PLTOFF64; |
| 2575 | break; |
| 2576 | case BFD_RELOC_X86_64_GOTPC32: |
| 2577 | other = BFD_RELOC_X86_64_GOTPC64; |
| 2578 | break; |
| 2579 | case BFD_RELOC_X86_64_GOTPCREL: |
| 2580 | other = BFD_RELOC_X86_64_GOTPCREL64; |
| 2581 | break; |
| 2582 | case BFD_RELOC_X86_64_TPOFF32: |
| 2583 | other = BFD_RELOC_X86_64_TPOFF64; |
| 2584 | break; |
| 2585 | case BFD_RELOC_X86_64_DTPOFF32: |
| 2586 | other = BFD_RELOC_X86_64_DTPOFF64; |
| 2587 | break; |
| 2588 | default: |
| 2589 | break; |
| 2590 | } |
| 2591 | |
| 2592 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
| 2593 | if (size == 4 && flag_code != CODE_64BIT) |
| 2594 | sign = -1; |
| 2595 | |
| 2596 | rel = bfd_reloc_type_lookup (stdoutput, other); |
| 2597 | if (!rel) |
| 2598 | as_bad (_("unknown relocation (%u)"), other); |
| 2599 | else if (size != bfd_get_reloc_size (rel)) |
| 2600 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
| 2601 | bfd_get_reloc_size (rel), |
| 2602 | size); |
| 2603 | else if (pcrel && !rel->pc_relative) |
| 2604 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
| 2605 | else if ((rel->complain_on_overflow == complain_overflow_signed |
| 2606 | && !sign) |
| 2607 | || (rel->complain_on_overflow == complain_overflow_unsigned |
| 2608 | && sign > 0)) |
| 2609 | as_bad (_("relocated field and relocation type differ in signedness")); |
| 2610 | else |
| 2611 | return other; |
| 2612 | return NO_RELOC; |
| 2613 | } |
| 2614 | |
| 2615 | if (pcrel) |
| 2616 | { |
| 2617 | if (!sign) |
| 2618 | as_bad (_("there are no unsigned pc-relative relocations")); |
| 2619 | switch (size) |
| 2620 | { |
| 2621 | case 1: return BFD_RELOC_8_PCREL; |
| 2622 | case 2: return BFD_RELOC_16_PCREL; |
| 2623 | case 4: return BFD_RELOC_32_PCREL; |
| 2624 | case 8: return BFD_RELOC_64_PCREL; |
| 2625 | } |
| 2626 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
| 2627 | } |
| 2628 | else |
| 2629 | { |
| 2630 | if (sign > 0) |
| 2631 | switch (size) |
| 2632 | { |
| 2633 | case 4: return BFD_RELOC_X86_64_32S; |
| 2634 | } |
| 2635 | else |
| 2636 | switch (size) |
| 2637 | { |
| 2638 | case 1: return BFD_RELOC_8; |
| 2639 | case 2: return BFD_RELOC_16; |
| 2640 | case 4: return BFD_RELOC_32; |
| 2641 | case 8: return BFD_RELOC_64; |
| 2642 | } |
| 2643 | as_bad (_("cannot do %s %u byte relocation"), |
| 2644 | sign > 0 ? "signed" : "unsigned", size); |
| 2645 | } |
| 2646 | |
| 2647 | return NO_RELOC; |
| 2648 | } |
| 2649 | |
| 2650 | /* Here we decide which fixups can be adjusted to make them relative to |
| 2651 | the beginning of the section instead of the symbol. Basically we need |
| 2652 | to make sure that the dynamic relocations are done correctly, so in |
| 2653 | some cases we force the original symbol to be used. */ |
| 2654 | |
| 2655 | int |
| 2656 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
| 2657 | { |
| 2658 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 2659 | if (!IS_ELF) |
| 2660 | return 1; |
| 2661 | |
| 2662 | /* Don't adjust pc-relative references to merge sections in 64-bit |
| 2663 | mode. */ |
| 2664 | if (use_rela_relocations |
| 2665 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 |
| 2666 | && fixP->fx_pcrel) |
| 2667 | return 0; |
| 2668 | |
| 2669 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
| 2670 | and changed later by validate_fix. */ |
| 2671 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol |
| 2672 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) |
| 2673 | return 0; |
| 2674 | |
| 2675 | /* adjust_reloc_syms doesn't know about the GOT. */ |
| 2676 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
| 2677 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 |
| 2678 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 |
| 2679 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
| 2680 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM |
| 2681 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 |
| 2682 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 |
| 2683 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
| 2684 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE |
| 2685 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
| 2686 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE |
| 2687 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
| 2688 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL |
| 2689 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
| 2690 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 |
| 2691 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
| 2692 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
| 2693 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD |
| 2694 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 |
| 2695 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
| 2696 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
| 2697 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 |
| 2698 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
| 2699 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 |
| 2700 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
| 2701 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL |
| 2702 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
| 2703 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
| 2704 | return 0; |
| 2705 | #endif |
| 2706 | return 1; |
| 2707 | } |
| 2708 | |
| 2709 | static int |
| 2710 | intel_float_operand (const char *mnemonic) |
| 2711 | { |
| 2712 | /* Note that the value returned is meaningful only for opcodes with (memory) |
| 2713 | operands, hence the code here is free to improperly handle opcodes that |
| 2714 | have no operands (for better performance and smaller code). */ |
| 2715 | |
| 2716 | if (mnemonic[0] != 'f') |
| 2717 | return 0; /* non-math */ |
| 2718 | |
| 2719 | switch (mnemonic[1]) |
| 2720 | { |
| 2721 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and |
| 2722 | the fs segment override prefix not currently handled because no |
| 2723 | call path can make opcodes without operands get here */ |
| 2724 | case 'i': |
| 2725 | return 2 /* integer op */; |
| 2726 | case 'l': |
| 2727 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) |
| 2728 | return 3; /* fldcw/fldenv */ |
| 2729 | break; |
| 2730 | case 'n': |
| 2731 | if (mnemonic[2] != 'o' /* fnop */) |
| 2732 | return 3; /* non-waiting control op */ |
| 2733 | break; |
| 2734 | case 'r': |
| 2735 | if (mnemonic[2] == 's') |
| 2736 | return 3; /* frstor/frstpm */ |
| 2737 | break; |
| 2738 | case 's': |
| 2739 | if (mnemonic[2] == 'a') |
| 2740 | return 3; /* fsave */ |
| 2741 | if (mnemonic[2] == 't') |
| 2742 | { |
| 2743 | switch (mnemonic[3]) |
| 2744 | { |
| 2745 | case 'c': /* fstcw */ |
| 2746 | case 'd': /* fstdw */ |
| 2747 | case 'e': /* fstenv */ |
| 2748 | case 's': /* fsts[gw] */ |
| 2749 | return 3; |
| 2750 | } |
| 2751 | } |
| 2752 | break; |
| 2753 | case 'x': |
| 2754 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') |
| 2755 | return 0; /* fxsave/fxrstor are not really math ops */ |
| 2756 | break; |
| 2757 | } |
| 2758 | |
| 2759 | return 1; |
| 2760 | } |
| 2761 | |
| 2762 | /* Build the VEX prefix. */ |
| 2763 | |
| 2764 | static void |
| 2765 | build_vex_prefix (const insn_template *t) |
| 2766 | { |
| 2767 | unsigned int register_specifier; |
| 2768 | unsigned int implied_prefix; |
| 2769 | unsigned int vector_length; |
| 2770 | |
| 2771 | /* Check register specifier. */ |
| 2772 | if (i.vex.register_specifier) |
| 2773 | { |
| 2774 | register_specifier = i.vex.register_specifier->reg_num; |
| 2775 | if ((i.vex.register_specifier->reg_flags & RegRex)) |
| 2776 | register_specifier += 8; |
| 2777 | register_specifier = ~register_specifier & 0xf; |
| 2778 | } |
| 2779 | else |
| 2780 | register_specifier = 0xf; |
| 2781 | |
| 2782 | /* Use 2-byte VEX prefix by swappping destination and source |
| 2783 | operand. */ |
| 2784 | if (!i.swap_operand |
| 2785 | && i.operands == i.reg_operands |
| 2786 | && i.tm.opcode_modifier.vexopcode == VEX0F |
| 2787 | && i.tm.opcode_modifier.s |
| 2788 | && i.rex == REX_B) |
| 2789 | { |
| 2790 | unsigned int xchg = i.operands - 1; |
| 2791 | union i386_op temp_op; |
| 2792 | i386_operand_type temp_type; |
| 2793 | |
| 2794 | temp_type = i.types[xchg]; |
| 2795 | i.types[xchg] = i.types[0]; |
| 2796 | i.types[0] = temp_type; |
| 2797 | temp_op = i.op[xchg]; |
| 2798 | i.op[xchg] = i.op[0]; |
| 2799 | i.op[0] = temp_op; |
| 2800 | |
| 2801 | gas_assert (i.rm.mode == 3); |
| 2802 | |
| 2803 | i.rex = REX_R; |
| 2804 | xchg = i.rm.regmem; |
| 2805 | i.rm.regmem = i.rm.reg; |
| 2806 | i.rm.reg = xchg; |
| 2807 | |
| 2808 | /* Use the next insn. */ |
| 2809 | i.tm = t[1]; |
| 2810 | } |
| 2811 | |
| 2812 | if (i.tm.opcode_modifier.vex == VEXScalar) |
| 2813 | vector_length = avxscalar; |
| 2814 | else |
| 2815 | vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0; |
| 2816 | |
| 2817 | switch ((i.tm.base_opcode >> 8) & 0xff) |
| 2818 | { |
| 2819 | case 0: |
| 2820 | implied_prefix = 0; |
| 2821 | break; |
| 2822 | case DATA_PREFIX_OPCODE: |
| 2823 | implied_prefix = 1; |
| 2824 | break; |
| 2825 | case REPE_PREFIX_OPCODE: |
| 2826 | implied_prefix = 2; |
| 2827 | break; |
| 2828 | case REPNE_PREFIX_OPCODE: |
| 2829 | implied_prefix = 3; |
| 2830 | break; |
| 2831 | default: |
| 2832 | abort (); |
| 2833 | } |
| 2834 | |
| 2835 | /* Use 2-byte VEX prefix if possible. */ |
| 2836 | if (i.tm.opcode_modifier.vexopcode == VEX0F |
| 2837 | && i.tm.opcode_modifier.vexw != VEXW1 |
| 2838 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
| 2839 | { |
| 2840 | /* 2-byte VEX prefix. */ |
| 2841 | unsigned int r; |
| 2842 | |
| 2843 | i.vex.length = 2; |
| 2844 | i.vex.bytes[0] = 0xc5; |
| 2845 | |
| 2846 | /* Check the REX.R bit. */ |
| 2847 | r = (i.rex & REX_R) ? 0 : 1; |
| 2848 | i.vex.bytes[1] = (r << 7 |
| 2849 | | register_specifier << 3 |
| 2850 | | vector_length << 2 |
| 2851 | | implied_prefix); |
| 2852 | } |
| 2853 | else |
| 2854 | { |
| 2855 | /* 3-byte VEX prefix. */ |
| 2856 | unsigned int m, w; |
| 2857 | |
| 2858 | i.vex.length = 3; |
| 2859 | |
| 2860 | switch (i.tm.opcode_modifier.vexopcode) |
| 2861 | { |
| 2862 | case VEX0F: |
| 2863 | m = 0x1; |
| 2864 | i.vex.bytes[0] = 0xc4; |
| 2865 | break; |
| 2866 | case VEX0F38: |
| 2867 | m = 0x2; |
| 2868 | i.vex.bytes[0] = 0xc4; |
| 2869 | break; |
| 2870 | case VEX0F3A: |
| 2871 | m = 0x3; |
| 2872 | i.vex.bytes[0] = 0xc4; |
| 2873 | break; |
| 2874 | case XOP08: |
| 2875 | m = 0x8; |
| 2876 | i.vex.bytes[0] = 0x8f; |
| 2877 | break; |
| 2878 | case XOP09: |
| 2879 | m = 0x9; |
| 2880 | i.vex.bytes[0] = 0x8f; |
| 2881 | break; |
| 2882 | case XOP0A: |
| 2883 | m = 0xa; |
| 2884 | i.vex.bytes[0] = 0x8f; |
| 2885 | break; |
| 2886 | default: |
| 2887 | abort (); |
| 2888 | } |
| 2889 | |
| 2890 | /* The high 3 bits of the second VEX byte are 1's compliment |
| 2891 | of RXB bits from REX. */ |
| 2892 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; |
| 2893 | |
| 2894 | /* Check the REX.W bit. */ |
| 2895 | w = (i.rex & REX_W) ? 1 : 0; |
| 2896 | if (i.tm.opcode_modifier.vexw) |
| 2897 | { |
| 2898 | if (w) |
| 2899 | abort (); |
| 2900 | |
| 2901 | if (i.tm.opcode_modifier.vexw == VEXW1) |
| 2902 | w = 1; |
| 2903 | } |
| 2904 | |
| 2905 | i.vex.bytes[2] = (w << 7 |
| 2906 | | register_specifier << 3 |
| 2907 | | vector_length << 2 |
| 2908 | | implied_prefix); |
| 2909 | } |
| 2910 | } |
| 2911 | |
| 2912 | static void |
| 2913 | process_immext (void) |
| 2914 | { |
| 2915 | expressionS *exp; |
| 2916 | |
| 2917 | if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0) |
| 2918 | { |
| 2919 | /* SSE3 Instructions have the fixed operands with an opcode |
| 2920 | suffix which is coded in the same place as an 8-bit immediate |
| 2921 | field would be. Here we check those operands and remove them |
| 2922 | afterwards. */ |
| 2923 | unsigned int x; |
| 2924 | |
| 2925 | for (x = 0; x < i.operands; x++) |
| 2926 | if (i.op[x].regs->reg_num != x) |
| 2927 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), |
| 2928 | register_prefix, i.op[x].regs->reg_name, x + 1, |
| 2929 | i.tm.name); |
| 2930 | |
| 2931 | i.operands = 0; |
| 2932 | } |
| 2933 | |
| 2934 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
| 2935 | which is coded in the same place as an 8-bit immediate field |
| 2936 | would be. Here we fake an 8-bit immediate operand from the |
| 2937 | opcode suffix stored in tm.extension_opcode. |
| 2938 | |
| 2939 | AVX instructions also use this encoding, for some of |
| 2940 | 3 argument instructions. */ |
| 2941 | |
| 2942 | gas_assert (i.imm_operands == 0 |
| 2943 | && (i.operands <= 2 |
| 2944 | || (i.tm.opcode_modifier.vex |
| 2945 | && i.operands <= 4))); |
| 2946 | |
| 2947 | exp = &im_expressions[i.imm_operands++]; |
| 2948 | i.op[i.operands].imms = exp; |
| 2949 | i.types[i.operands] = imm8; |
| 2950 | i.operands++; |
| 2951 | exp->X_op = O_constant; |
| 2952 | exp->X_add_number = i.tm.extension_opcode; |
| 2953 | i.tm.extension_opcode = None; |
| 2954 | } |
| 2955 | |
| 2956 | /* This is the guts of the machine-dependent assembler. LINE points to a |
| 2957 | machine dependent instruction. This function is supposed to emit |
| 2958 | the frags/bytes it assembles to. */ |
| 2959 | |
| 2960 | void |
| 2961 | md_assemble (char *line) |
| 2962 | { |
| 2963 | unsigned int j; |
| 2964 | char mnemonic[MAX_MNEM_SIZE]; |
| 2965 | const insn_template *t; |
| 2966 | |
| 2967 | /* Initialize globals. */ |
| 2968 | memset (&i, '\0', sizeof (i)); |
| 2969 | for (j = 0; j < MAX_OPERANDS; j++) |
| 2970 | i.reloc[j] = NO_RELOC; |
| 2971 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
| 2972 | memset (im_expressions, '\0', sizeof (im_expressions)); |
| 2973 | save_stack_p = save_stack; |
| 2974 | |
| 2975 | /* First parse an instruction mnemonic & call i386_operand for the operands. |
| 2976 | We assume that the scrubber has arranged it so that line[0] is the valid |
| 2977 | start of a (possibly prefixed) mnemonic. */ |
| 2978 | |
| 2979 | line = parse_insn (line, mnemonic); |
| 2980 | if (line == NULL) |
| 2981 | return; |
| 2982 | |
| 2983 | line = parse_operands (line, mnemonic); |
| 2984 | this_operand = -1; |
| 2985 | if (line == NULL) |
| 2986 | return; |
| 2987 | |
| 2988 | /* Now we've parsed the mnemonic into a set of templates, and have the |
| 2989 | operands at hand. */ |
| 2990 | |
| 2991 | /* All intel opcodes have reversed operands except for "bound" and |
| 2992 | "enter". We also don't reverse intersegment "jmp" and "call" |
| 2993 | instructions with 2 immediate operands so that the immediate segment |
| 2994 | precedes the offset, as it does when in AT&T mode. */ |
| 2995 | if (intel_syntax |
| 2996 | && i.operands > 1 |
| 2997 | && (strcmp (mnemonic, "bound") != 0) |
| 2998 | && (strcmp (mnemonic, "invlpga") != 0) |
| 2999 | && !(operand_type_check (i.types[0], imm) |
| 3000 | && operand_type_check (i.types[1], imm))) |
| 3001 | swap_operands (); |
| 3002 | |
| 3003 | /* The order of the immediates should be reversed |
| 3004 | for 2 immediates extrq and insertq instructions */ |
| 3005 | if (i.imm_operands == 2 |
| 3006 | && (strcmp (mnemonic, "extrq") == 0 |
| 3007 | || strcmp (mnemonic, "insertq") == 0)) |
| 3008 | swap_2_operands (0, 1); |
| 3009 | |
| 3010 | if (i.imm_operands) |
| 3011 | optimize_imm (); |
| 3012 | |
| 3013 | /* Don't optimize displacement for movabs since it only takes 64bit |
| 3014 | displacement. */ |
| 3015 | if (i.disp_operands |
| 3016 | && !i.disp32_encoding |
| 3017 | && (flag_code != CODE_64BIT |
| 3018 | || strcmp (mnemonic, "movabs") != 0)) |
| 3019 | optimize_disp (); |
| 3020 | |
| 3021 | /* Next, we find a template that matches the given insn, |
| 3022 | making sure the overlap of the given operands types is consistent |
| 3023 | with the template operand types. */ |
| 3024 | |
| 3025 | if (!(t = match_template ())) |
| 3026 | return; |
| 3027 | |
| 3028 | if (sse_check != sse_check_none |
| 3029 | && !i.tm.opcode_modifier.noavx |
| 3030 | && (i.tm.cpu_flags.bitfield.cpusse |
| 3031 | || i.tm.cpu_flags.bitfield.cpusse2 |
| 3032 | || i.tm.cpu_flags.bitfield.cpusse3 |
| 3033 | || i.tm.cpu_flags.bitfield.cpussse3 |
| 3034 | || i.tm.cpu_flags.bitfield.cpusse4_1 |
| 3035 | || i.tm.cpu_flags.bitfield.cpusse4_2)) |
| 3036 | { |
| 3037 | (sse_check == sse_check_warning |
| 3038 | ? as_warn |
| 3039 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); |
| 3040 | } |
| 3041 | |
| 3042 | /* Zap movzx and movsx suffix. The suffix has been set from |
| 3043 | "word ptr" or "byte ptr" on the source operand in Intel syntax |
| 3044 | or extracted from mnemonic in AT&T syntax. But we'll use |
| 3045 | the destination register to choose the suffix for encoding. */ |
| 3046 | if ((i.tm.base_opcode & ~9) == 0x0fb6) |
| 3047 | { |
| 3048 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
| 3049 | there is no suffix, the default will be byte extension. */ |
| 3050 | if (i.reg_operands != 2 |
| 3051 | && !i.suffix |
| 3052 | && intel_syntax) |
| 3053 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
| 3054 | |
| 3055 | i.suffix = 0; |
| 3056 | } |
| 3057 | |
| 3058 | if (i.tm.opcode_modifier.fwait) |
| 3059 | if (!add_prefix (FWAIT_OPCODE)) |
| 3060 | return; |
| 3061 | |
| 3062 | /* Check for lock without a lockable instruction. Destination operand |
| 3063 | must be memory unless it is xchg (0x86). */ |
| 3064 | if (i.prefix[LOCK_PREFIX] |
| 3065 | && (!i.tm.opcode_modifier.islockable |
| 3066 | || i.mem_operands == 0 |
| 3067 | || (i.tm.base_opcode != 0x86 |
| 3068 | && !operand_type_check (i.types[i.operands - 1], anymem)))) |
| 3069 | { |
| 3070 | as_bad (_("expecting lockable instruction after `lock'")); |
| 3071 | return; |
| 3072 | } |
| 3073 | |
| 3074 | /* Check string instruction segment overrides. */ |
| 3075 | if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) |
| 3076 | { |
| 3077 | if (!check_string ()) |
| 3078 | return; |
| 3079 | i.disp_operands = 0; |
| 3080 | } |
| 3081 | |
| 3082 | if (!process_suffix ()) |
| 3083 | return; |
| 3084 | |
| 3085 | /* Update operand types. */ |
| 3086 | for (j = 0; j < i.operands; j++) |
| 3087 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); |
| 3088 | |
| 3089 | /* Make still unresolved immediate matches conform to size of immediate |
| 3090 | given in i.suffix. */ |
| 3091 | if (!finalize_imm ()) |
| 3092 | return; |
| 3093 | |
| 3094 | if (i.types[0].bitfield.imm1) |
| 3095 | i.imm_operands = 0; /* kludge for shift insns. */ |
| 3096 | |
| 3097 | /* We only need to check those implicit registers for instructions |
| 3098 | with 3 operands or less. */ |
| 3099 | if (i.operands <= 3) |
| 3100 | for (j = 0; j < i.operands; j++) |
| 3101 | if (i.types[j].bitfield.inoutportreg |
| 3102 | || i.types[j].bitfield.shiftcount |
| 3103 | || i.types[j].bitfield.acc |
| 3104 | || i.types[j].bitfield.floatacc) |
| 3105 | i.reg_operands--; |
| 3106 | |
| 3107 | /* ImmExt should be processed after SSE2AVX. */ |
| 3108 | if (!i.tm.opcode_modifier.sse2avx |
| 3109 | && i.tm.opcode_modifier.immext) |
| 3110 | process_immext (); |
| 3111 | |
| 3112 | /* For insns with operands there are more diddles to do to the opcode. */ |
| 3113 | if (i.operands) |
| 3114 | { |
| 3115 | if (!process_operands ()) |
| 3116 | return; |
| 3117 | } |
| 3118 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
| 3119 | { |
| 3120 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ |
| 3121 | as_warn (_("translating to `%sp'"), i.tm.name); |
| 3122 | } |
| 3123 | |
| 3124 | if (i.tm.opcode_modifier.vex) |
| 3125 | build_vex_prefix (t); |
| 3126 | |
| 3127 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
| 3128 | instructions may define INT_OPCODE as well, so avoid this corner |
| 3129 | case for those instructions that use MODRM. */ |
| 3130 | if (i.tm.base_opcode == INT_OPCODE |
| 3131 | && !i.tm.opcode_modifier.modrm |
| 3132 | && i.op[0].imms->X_add_number == 3) |
| 3133 | { |
| 3134 | i.tm.base_opcode = INT3_OPCODE; |
| 3135 | i.imm_operands = 0; |
| 3136 | } |
| 3137 | |
| 3138 | if ((i.tm.opcode_modifier.jump |
| 3139 | || i.tm.opcode_modifier.jumpbyte |
| 3140 | || i.tm.opcode_modifier.jumpdword) |
| 3141 | && i.op[0].disps->X_op == O_constant) |
| 3142 | { |
| 3143 | /* Convert "jmp constant" (and "call constant") to a jump (call) to |
| 3144 | the absolute address given by the constant. Since ix86 jumps and |
| 3145 | calls are pc relative, we need to generate a reloc. */ |
| 3146 | i.op[0].disps->X_add_symbol = &abs_symbol; |
| 3147 | i.op[0].disps->X_op = O_symbol; |
| 3148 | } |
| 3149 | |
| 3150 | if (i.tm.opcode_modifier.rex64) |
| 3151 | i.rex |= REX_W; |
| 3152 | |
| 3153 | /* For 8 bit registers we need an empty rex prefix. Also if the |
| 3154 | instruction already has a prefix, we need to convert old |
| 3155 | registers to new ones. */ |
| 3156 | |
| 3157 | if ((i.types[0].bitfield.reg8 |
| 3158 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
| 3159 | || (i.types[1].bitfield.reg8 |
| 3160 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
| 3161 | || ((i.types[0].bitfield.reg8 |
| 3162 | || i.types[1].bitfield.reg8) |
| 3163 | && i.rex != 0)) |
| 3164 | { |
| 3165 | int x; |
| 3166 | |
| 3167 | i.rex |= REX_OPCODE; |
| 3168 | for (x = 0; x < 2; x++) |
| 3169 | { |
| 3170 | /* Look for 8 bit operand that uses old registers. */ |
| 3171 | if (i.types[x].bitfield.reg8 |
| 3172 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
| 3173 | { |
| 3174 | /* In case it is "hi" register, give up. */ |
| 3175 | if (i.op[x].regs->reg_num > 3) |
| 3176 | as_bad (_("can't encode register '%s%s' in an " |
| 3177 | "instruction requiring REX prefix."), |
| 3178 | register_prefix, i.op[x].regs->reg_name); |
| 3179 | |
| 3180 | /* Otherwise it is equivalent to the extended register. |
| 3181 | Since the encoding doesn't change this is merely |
| 3182 | cosmetic cleanup for debug output. */ |
| 3183 | |
| 3184 | i.op[x].regs = i.op[x].regs + 8; |
| 3185 | } |
| 3186 | } |
| 3187 | } |
| 3188 | |
| 3189 | if (i.rex != 0) |
| 3190 | add_prefix (REX_OPCODE | i.rex); |
| 3191 | |
| 3192 | /* We are ready to output the insn. */ |
| 3193 | output_insn (); |
| 3194 | } |
| 3195 | |
| 3196 | static char * |
| 3197 | parse_insn (char *line, char *mnemonic) |
| 3198 | { |
| 3199 | char *l = line; |
| 3200 | char *token_start = l; |
| 3201 | char *mnem_p; |
| 3202 | int supported; |
| 3203 | const insn_template *t; |
| 3204 | char *dot_p = NULL; |
| 3205 | |
| 3206 | /* Non-zero if we found a prefix only acceptable with string insns. */ |
| 3207 | const char *expecting_string_instruction = NULL; |
| 3208 | |
| 3209 | while (1) |
| 3210 | { |
| 3211 | mnem_p = mnemonic; |
| 3212 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) |
| 3213 | { |
| 3214 | if (*mnem_p == '.') |
| 3215 | dot_p = mnem_p; |
| 3216 | mnem_p++; |
| 3217 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) |
| 3218 | { |
| 3219 | as_bad (_("no such instruction: `%s'"), token_start); |
| 3220 | return NULL; |
| 3221 | } |
| 3222 | l++; |
| 3223 | } |
| 3224 | if (!is_space_char (*l) |
| 3225 | && *l != END_OF_INSN |
| 3226 | && (intel_syntax |
| 3227 | || (*l != PREFIX_SEPARATOR |
| 3228 | && *l != ','))) |
| 3229 | { |
| 3230 | as_bad (_("invalid character %s in mnemonic"), |
| 3231 | output_invalid (*l)); |
| 3232 | return NULL; |
| 3233 | } |
| 3234 | if (token_start == l) |
| 3235 | { |
| 3236 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
| 3237 | as_bad (_("expecting prefix; got nothing")); |
| 3238 | else |
| 3239 | as_bad (_("expecting mnemonic; got nothing")); |
| 3240 | return NULL; |
| 3241 | } |
| 3242 | |
| 3243 | /* Look up instruction (or prefix) via hash table. */ |
| 3244 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
| 3245 | |
| 3246 | if (*l != END_OF_INSN |
| 3247 | && (!is_space_char (*l) || l[1] != END_OF_INSN) |
| 3248 | && current_templates |
| 3249 | && current_templates->start->opcode_modifier.isprefix) |
| 3250 | { |
| 3251 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
| 3252 | { |
| 3253 | as_bad ((flag_code != CODE_64BIT |
| 3254 | ? _("`%s' is only supported in 64-bit mode") |
| 3255 | : _("`%s' is not supported in 64-bit mode")), |
| 3256 | current_templates->start->name); |
| 3257 | return NULL; |
| 3258 | } |
| 3259 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
| 3260 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ |
| 3261 | if ((current_templates->start->opcode_modifier.size16 |
| 3262 | || current_templates->start->opcode_modifier.size32) |
| 3263 | && flag_code != CODE_64BIT |
| 3264 | && (current_templates->start->opcode_modifier.size32 |
| 3265 | ^ (flag_code == CODE_16BIT))) |
| 3266 | { |
| 3267 | as_bad (_("redundant %s prefix"), |
| 3268 | current_templates->start->name); |
| 3269 | return NULL; |
| 3270 | } |
| 3271 | /* Add prefix, checking for repeated prefixes. */ |
| 3272 | switch (add_prefix (current_templates->start->base_opcode)) |
| 3273 | { |
| 3274 | case PREFIX_EXIST: |
| 3275 | return NULL; |
| 3276 | case PREFIX_REP: |
| 3277 | expecting_string_instruction = current_templates->start->name; |
| 3278 | break; |
| 3279 | default: |
| 3280 | break; |
| 3281 | } |
| 3282 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ |
| 3283 | token_start = ++l; |
| 3284 | } |
| 3285 | else |
| 3286 | break; |
| 3287 | } |
| 3288 | |
| 3289 | if (!current_templates) |
| 3290 | { |
| 3291 | /* Check if we should swap operand or force 32bit displacement in |
| 3292 | encoding. */ |
| 3293 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
| 3294 | i.swap_operand = 1; |
| 3295 | else if (mnem_p - 4 == dot_p |
| 3296 | && dot_p[1] == 'd' |
| 3297 | && dot_p[2] == '3' |
| 3298 | && dot_p[3] == '2') |
| 3299 | i.disp32_encoding = 1; |
| 3300 | else |
| 3301 | goto check_suffix; |
| 3302 | mnem_p = dot_p; |
| 3303 | *dot_p = '\0'; |
| 3304 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
| 3305 | } |
| 3306 | |
| 3307 | if (!current_templates) |
| 3308 | { |
| 3309 | check_suffix: |
| 3310 | /* See if we can get a match by trimming off a suffix. */ |
| 3311 | switch (mnem_p[-1]) |
| 3312 | { |
| 3313 | case WORD_MNEM_SUFFIX: |
| 3314 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) |
| 3315 | i.suffix = SHORT_MNEM_SUFFIX; |
| 3316 | else |
| 3317 | case BYTE_MNEM_SUFFIX: |
| 3318 | case QWORD_MNEM_SUFFIX: |
| 3319 | i.suffix = mnem_p[-1]; |
| 3320 | mnem_p[-1] = '\0'; |
| 3321 | current_templates = (const templates *) hash_find (op_hash, |
| 3322 | mnemonic); |
| 3323 | break; |
| 3324 | case SHORT_MNEM_SUFFIX: |
| 3325 | case LONG_MNEM_SUFFIX: |
| 3326 | if (!intel_syntax) |
| 3327 | { |
| 3328 | i.suffix = mnem_p[-1]; |
| 3329 | mnem_p[-1] = '\0'; |
| 3330 | current_templates = (const templates *) hash_find (op_hash, |
| 3331 | mnemonic); |
| 3332 | } |
| 3333 | break; |
| 3334 | |
| 3335 | /* Intel Syntax. */ |
| 3336 | case 'd': |
| 3337 | if (intel_syntax) |
| 3338 | { |
| 3339 | if (intel_float_operand (mnemonic) == 1) |
| 3340 | i.suffix = SHORT_MNEM_SUFFIX; |
| 3341 | else |
| 3342 | i.suffix = LONG_MNEM_SUFFIX; |
| 3343 | mnem_p[-1] = '\0'; |
| 3344 | current_templates = (const templates *) hash_find (op_hash, |
| 3345 | mnemonic); |
| 3346 | } |
| 3347 | break; |
| 3348 | } |
| 3349 | if (!current_templates) |
| 3350 | { |
| 3351 | as_bad (_("no such instruction: `%s'"), token_start); |
| 3352 | return NULL; |
| 3353 | } |
| 3354 | } |
| 3355 | |
| 3356 | if (current_templates->start->opcode_modifier.jump |
| 3357 | || current_templates->start->opcode_modifier.jumpbyte) |
| 3358 | { |
| 3359 | /* Check for a branch hint. We allow ",pt" and ",pn" for |
| 3360 | predict taken and predict not taken respectively. |
| 3361 | I'm not sure that branch hints actually do anything on loop |
| 3362 | and jcxz insns (JumpByte) for current Pentium4 chips. They |
| 3363 | may work in the future and it doesn't hurt to accept them |
| 3364 | now. */ |
| 3365 | if (l[0] == ',' && l[1] == 'p') |
| 3366 | { |
| 3367 | if (l[2] == 't') |
| 3368 | { |
| 3369 | if (!add_prefix (DS_PREFIX_OPCODE)) |
| 3370 | return NULL; |
| 3371 | l += 3; |
| 3372 | } |
| 3373 | else if (l[2] == 'n') |
| 3374 | { |
| 3375 | if (!add_prefix (CS_PREFIX_OPCODE)) |
| 3376 | return NULL; |
| 3377 | l += 3; |
| 3378 | } |
| 3379 | } |
| 3380 | } |
| 3381 | /* Any other comma loses. */ |
| 3382 | if (*l == ',') |
| 3383 | { |
| 3384 | as_bad (_("invalid character %s in mnemonic"), |
| 3385 | output_invalid (*l)); |
| 3386 | return NULL; |
| 3387 | } |
| 3388 | |
| 3389 | /* Check if instruction is supported on specified architecture. */ |
| 3390 | supported = 0; |
| 3391 | for (t = current_templates->start; t < current_templates->end; ++t) |
| 3392 | { |
| 3393 | supported |= cpu_flags_match (t); |
| 3394 | if (supported == CPU_FLAGS_PERFECT_MATCH) |
| 3395 | goto skip; |
| 3396 | } |
| 3397 | |
| 3398 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
| 3399 | { |
| 3400 | as_bad (flag_code == CODE_64BIT |
| 3401 | ? _("`%s' is not supported in 64-bit mode") |
| 3402 | : _("`%s' is only supported in 64-bit mode"), |
| 3403 | current_templates->start->name); |
| 3404 | return NULL; |
| 3405 | } |
| 3406 | if (supported != CPU_FLAGS_PERFECT_MATCH) |
| 3407 | { |
| 3408 | as_bad (_("`%s' is not supported on `%s%s'"), |
| 3409 | current_templates->start->name, |
| 3410 | cpu_arch_name ? cpu_arch_name : default_arch, |
| 3411 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); |
| 3412 | return NULL; |
| 3413 | } |
| 3414 | |
| 3415 | skip: |
| 3416 | if (!cpu_arch_flags.bitfield.cpui386 |
| 3417 | && (flag_code != CODE_16BIT)) |
| 3418 | { |
| 3419 | as_warn (_("use .code16 to ensure correct addressing mode")); |
| 3420 | } |
| 3421 | |
| 3422 | /* Check for rep/repne without a string instruction. */ |
| 3423 | if (expecting_string_instruction) |
| 3424 | { |
| 3425 | static templates override; |
| 3426 | |
| 3427 | for (t = current_templates->start; t < current_templates->end; ++t) |
| 3428 | if (t->opcode_modifier.isstring) |
| 3429 | break; |
| 3430 | if (t >= current_templates->end) |
| 3431 | { |
| 3432 | as_bad (_("expecting string instruction after `%s'"), |
| 3433 | expecting_string_instruction); |
| 3434 | return NULL; |
| 3435 | } |
| 3436 | for (override.start = t; t < current_templates->end; ++t) |
| 3437 | if (!t->opcode_modifier.isstring) |
| 3438 | break; |
| 3439 | override.end = t; |
| 3440 | current_templates = &override; |
| 3441 | } |
| 3442 | |
| 3443 | return l; |
| 3444 | } |
| 3445 | |
| 3446 | static char * |
| 3447 | parse_operands (char *l, const char *mnemonic) |
| 3448 | { |
| 3449 | char *token_start; |
| 3450 | |
| 3451 | /* 1 if operand is pending after ','. */ |
| 3452 | unsigned int expecting_operand = 0; |
| 3453 | |
| 3454 | /* Non-zero if operand parens not balanced. */ |
| 3455 | unsigned int paren_not_balanced; |
| 3456 | |
| 3457 | while (*l != END_OF_INSN) |
| 3458 | { |
| 3459 | /* Skip optional white space before operand. */ |
| 3460 | if (is_space_char (*l)) |
| 3461 | ++l; |
| 3462 | if (!is_operand_char (*l) && *l != END_OF_INSN) |
| 3463 | { |
| 3464 | as_bad (_("invalid character %s before operand %d"), |
| 3465 | output_invalid (*l), |
| 3466 | i.operands + 1); |
| 3467 | return NULL; |
| 3468 | } |
| 3469 | token_start = l; /* after white space */ |
| 3470 | paren_not_balanced = 0; |
| 3471 | while (paren_not_balanced || *l != ',') |
| 3472 | { |
| 3473 | if (*l == END_OF_INSN) |
| 3474 | { |
| 3475 | if (paren_not_balanced) |
| 3476 | { |
| 3477 | if (!intel_syntax) |
| 3478 | as_bad (_("unbalanced parenthesis in operand %d."), |
| 3479 | i.operands + 1); |
| 3480 | else |
| 3481 | as_bad (_("unbalanced brackets in operand %d."), |
| 3482 | i.operands + 1); |
| 3483 | return NULL; |
| 3484 | } |
| 3485 | else |
| 3486 | break; /* we are done */ |
| 3487 | } |
| 3488 | else if (!is_operand_char (*l) && !is_space_char (*l)) |
| 3489 | { |
| 3490 | as_bad (_("invalid character %s in operand %d"), |
| 3491 | output_invalid (*l), |
| 3492 | i.operands + 1); |
| 3493 | return NULL; |
| 3494 | } |
| 3495 | if (!intel_syntax) |
| 3496 | { |
| 3497 | if (*l == '(') |
| 3498 | ++paren_not_balanced; |
| 3499 | if (*l == ')') |
| 3500 | --paren_not_balanced; |
| 3501 | } |
| 3502 | else |
| 3503 | { |
| 3504 | if (*l == '[') |
| 3505 | ++paren_not_balanced; |
| 3506 | if (*l == ']') |
| 3507 | --paren_not_balanced; |
| 3508 | } |
| 3509 | l++; |
| 3510 | } |
| 3511 | if (l != token_start) |
| 3512 | { /* Yes, we've read in another operand. */ |
| 3513 | unsigned int operand_ok; |
| 3514 | this_operand = i.operands++; |
| 3515 | i.types[this_operand].bitfield.unspecified = 1; |
| 3516 | if (i.operands > MAX_OPERANDS) |
| 3517 | { |
| 3518 | as_bad (_("spurious operands; (%d operands/instruction max)"), |
| 3519 | MAX_OPERANDS); |
| 3520 | return NULL; |
| 3521 | } |
| 3522 | /* Now parse operand adding info to 'i' as we go along. */ |
| 3523 | END_STRING_AND_SAVE (l); |
| 3524 | |
| 3525 | if (intel_syntax) |
| 3526 | operand_ok = |
| 3527 | i386_intel_operand (token_start, |
| 3528 | intel_float_operand (mnemonic)); |
| 3529 | else |
| 3530 | operand_ok = i386_att_operand (token_start); |
| 3531 | |
| 3532 | RESTORE_END_STRING (l); |
| 3533 | if (!operand_ok) |
| 3534 | return NULL; |
| 3535 | } |
| 3536 | else |
| 3537 | { |
| 3538 | if (expecting_operand) |
| 3539 | { |
| 3540 | expecting_operand_after_comma: |
| 3541 | as_bad (_("expecting operand after ','; got nothing")); |
| 3542 | return NULL; |
| 3543 | } |
| 3544 | if (*l == ',') |
| 3545 | { |
| 3546 | as_bad (_("expecting operand before ','; got nothing")); |
| 3547 | return NULL; |
| 3548 | } |
| 3549 | } |
| 3550 | |
| 3551 | /* Now *l must be either ',' or END_OF_INSN. */ |
| 3552 | if (*l == ',') |
| 3553 | { |
| 3554 | if (*++l == END_OF_INSN) |
| 3555 | { |
| 3556 | /* Just skip it, if it's \n complain. */ |
| 3557 | goto expecting_operand_after_comma; |
| 3558 | } |
| 3559 | expecting_operand = 1; |
| 3560 | } |
| 3561 | } |
| 3562 | return l; |
| 3563 | } |
| 3564 | |
| 3565 | static void |
| 3566 | swap_2_operands (int xchg1, int xchg2) |
| 3567 | { |
| 3568 | union i386_op temp_op; |
| 3569 | i386_operand_type temp_type; |
| 3570 | enum bfd_reloc_code_real temp_reloc; |
| 3571 | |
| 3572 | temp_type = i.types[xchg2]; |
| 3573 | i.types[xchg2] = i.types[xchg1]; |
| 3574 | i.types[xchg1] = temp_type; |
| 3575 | temp_op = i.op[xchg2]; |
| 3576 | i.op[xchg2] = i.op[xchg1]; |
| 3577 | i.op[xchg1] = temp_op; |
| 3578 | temp_reloc = i.reloc[xchg2]; |
| 3579 | i.reloc[xchg2] = i.reloc[xchg1]; |
| 3580 | i.reloc[xchg1] = temp_reloc; |
| 3581 | } |
| 3582 | |
| 3583 | static void |
| 3584 | swap_operands (void) |
| 3585 | { |
| 3586 | switch (i.operands) |
| 3587 | { |
| 3588 | case 5: |
| 3589 | case 4: |
| 3590 | swap_2_operands (1, i.operands - 2); |
| 3591 | case 3: |
| 3592 | case 2: |
| 3593 | swap_2_operands (0, i.operands - 1); |
| 3594 | break; |
| 3595 | default: |
| 3596 | abort (); |
| 3597 | } |
| 3598 | |
| 3599 | if (i.mem_operands == 2) |
| 3600 | { |
| 3601 | const seg_entry *temp_seg; |
| 3602 | temp_seg = i.seg[0]; |
| 3603 | i.seg[0] = i.seg[1]; |
| 3604 | i.seg[1] = temp_seg; |
| 3605 | } |
| 3606 | } |
| 3607 | |
| 3608 | /* Try to ensure constant immediates are represented in the smallest |
| 3609 | opcode possible. */ |
| 3610 | static void |
| 3611 | optimize_imm (void) |
| 3612 | { |
| 3613 | char guess_suffix = 0; |
| 3614 | int op; |
| 3615 | |
| 3616 | if (i.suffix) |
| 3617 | guess_suffix = i.suffix; |
| 3618 | else if (i.reg_operands) |
| 3619 | { |
| 3620 | /* Figure out a suffix from the last register operand specified. |
| 3621 | We can't do this properly yet, ie. excluding InOutPortReg, |
| 3622 | but the following works for instructions with immediates. |
| 3623 | In any case, we can't set i.suffix yet. */ |
| 3624 | for (op = i.operands; --op >= 0;) |
| 3625 | if (i.types[op].bitfield.reg8) |
| 3626 | { |
| 3627 | guess_suffix = BYTE_MNEM_SUFFIX; |
| 3628 | break; |
| 3629 | } |
| 3630 | else if (i.types[op].bitfield.reg16) |
| 3631 | { |
| 3632 | guess_suffix = WORD_MNEM_SUFFIX; |
| 3633 | break; |
| 3634 | } |
| 3635 | else if (i.types[op].bitfield.reg32) |
| 3636 | { |
| 3637 | guess_suffix = LONG_MNEM_SUFFIX; |
| 3638 | break; |
| 3639 | } |
| 3640 | else if (i.types[op].bitfield.reg64) |
| 3641 | { |
| 3642 | guess_suffix = QWORD_MNEM_SUFFIX; |
| 3643 | break; |
| 3644 | } |
| 3645 | } |
| 3646 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
| 3647 | guess_suffix = WORD_MNEM_SUFFIX; |
| 3648 | |
| 3649 | for (op = i.operands; --op >= 0;) |
| 3650 | if (operand_type_check (i.types[op], imm)) |
| 3651 | { |
| 3652 | switch (i.op[op].imms->X_op) |
| 3653 | { |
| 3654 | case O_constant: |
| 3655 | /* If a suffix is given, this operand may be shortened. */ |
| 3656 | switch (guess_suffix) |
| 3657 | { |
| 3658 | case LONG_MNEM_SUFFIX: |
| 3659 | i.types[op].bitfield.imm32 = 1; |
| 3660 | i.types[op].bitfield.imm64 = 1; |
| 3661 | break; |
| 3662 | case WORD_MNEM_SUFFIX: |
| 3663 | i.types[op].bitfield.imm16 = 1; |
| 3664 | i.types[op].bitfield.imm32 = 1; |
| 3665 | i.types[op].bitfield.imm32s = 1; |
| 3666 | i.types[op].bitfield.imm64 = 1; |
| 3667 | break; |
| 3668 | case BYTE_MNEM_SUFFIX: |
| 3669 | i.types[op].bitfield.imm8 = 1; |
| 3670 | i.types[op].bitfield.imm8s = 1; |
| 3671 | i.types[op].bitfield.imm16 = 1; |
| 3672 | i.types[op].bitfield.imm32 = 1; |
| 3673 | i.types[op].bitfield.imm32s = 1; |
| 3674 | i.types[op].bitfield.imm64 = 1; |
| 3675 | break; |
| 3676 | } |
| 3677 | |
| 3678 | /* If this operand is at most 16 bits, convert it |
| 3679 | to a signed 16 bit number before trying to see |
| 3680 | whether it will fit in an even smaller size. |
| 3681 | This allows a 16-bit operand such as $0xffe0 to |
| 3682 | be recognised as within Imm8S range. */ |
| 3683 | if ((i.types[op].bitfield.imm16) |
| 3684 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
| 3685 | { |
| 3686 | i.op[op].imms->X_add_number = |
| 3687 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); |
| 3688 | } |
| 3689 | if ((i.types[op].bitfield.imm32) |
| 3690 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
| 3691 | == 0)) |
| 3692 | { |
| 3693 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number |
| 3694 | ^ ((offsetT) 1 << 31)) |
| 3695 | - ((offsetT) 1 << 31)); |
| 3696 | } |
| 3697 | i.types[op] |
| 3698 | = operand_type_or (i.types[op], |
| 3699 | smallest_imm_type (i.op[op].imms->X_add_number)); |
| 3700 | |
| 3701 | /* We must avoid matching of Imm32 templates when 64bit |
| 3702 | only immediate is available. */ |
| 3703 | if (guess_suffix == QWORD_MNEM_SUFFIX) |
| 3704 | i.types[op].bitfield.imm32 = 0; |
| 3705 | break; |
| 3706 | |
| 3707 | case O_absent: |
| 3708 | case O_register: |
| 3709 | abort (); |
| 3710 | |
| 3711 | /* Symbols and expressions. */ |
| 3712 | default: |
| 3713 | /* Convert symbolic operand to proper sizes for matching, but don't |
| 3714 | prevent matching a set of insns that only supports sizes other |
| 3715 | than those matching the insn suffix. */ |
| 3716 | { |
| 3717 | i386_operand_type mask, allowed; |
| 3718 | const insn_template *t; |
| 3719 | |
| 3720 | operand_type_set (&mask, 0); |
| 3721 | operand_type_set (&allowed, 0); |
| 3722 | |
| 3723 | for (t = current_templates->start; |
| 3724 | t < current_templates->end; |
| 3725 | ++t) |
| 3726 | allowed = operand_type_or (allowed, |
| 3727 | t->operand_types[op]); |
| 3728 | switch (guess_suffix) |
| 3729 | { |
| 3730 | case QWORD_MNEM_SUFFIX: |
| 3731 | mask.bitfield.imm64 = 1; |
| 3732 | mask.bitfield.imm32s = 1; |
| 3733 | break; |
| 3734 | case LONG_MNEM_SUFFIX: |
| 3735 | mask.bitfield.imm32 = 1; |
| 3736 | break; |
| 3737 | case WORD_MNEM_SUFFIX: |
| 3738 | mask.bitfield.imm16 = 1; |
| 3739 | break; |
| 3740 | case BYTE_MNEM_SUFFIX: |
| 3741 | mask.bitfield.imm8 = 1; |
| 3742 | break; |
| 3743 | default: |
| 3744 | break; |
| 3745 | } |
| 3746 | allowed = operand_type_and (mask, allowed); |
| 3747 | if (!operand_type_all_zero (&allowed)) |
| 3748 | i.types[op] = operand_type_and (i.types[op], mask); |
| 3749 | } |
| 3750 | break; |
| 3751 | } |
| 3752 | } |
| 3753 | } |
| 3754 | |
| 3755 | /* Try to use the smallest displacement type too. */ |
| 3756 | static void |
| 3757 | optimize_disp (void) |
| 3758 | { |
| 3759 | int op; |
| 3760 | |
| 3761 | for (op = i.operands; --op >= 0;) |
| 3762 | if (operand_type_check (i.types[op], disp)) |
| 3763 | { |
| 3764 | if (i.op[op].disps->X_op == O_constant) |
| 3765 | { |
| 3766 | offsetT op_disp = i.op[op].disps->X_add_number; |
| 3767 | |
| 3768 | if (i.types[op].bitfield.disp16 |
| 3769 | && (op_disp & ~(offsetT) 0xffff) == 0) |
| 3770 | { |
| 3771 | /* If this operand is at most 16 bits, convert |
| 3772 | to a signed 16 bit number and don't use 64bit |
| 3773 | displacement. */ |
| 3774 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
| 3775 | i.types[op].bitfield.disp64 = 0; |
| 3776 | } |
| 3777 | if (i.types[op].bitfield.disp32 |
| 3778 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
| 3779 | { |
| 3780 | /* If this operand is at most 32 bits, convert |
| 3781 | to a signed 32 bit number and don't use 64bit |
| 3782 | displacement. */ |
| 3783 | op_disp &= (((offsetT) 2 << 31) - 1); |
| 3784 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); |
| 3785 | i.types[op].bitfield.disp64 = 0; |
| 3786 | } |
| 3787 | if (!op_disp && i.types[op].bitfield.baseindex) |
| 3788 | { |
| 3789 | i.types[op].bitfield.disp8 = 0; |
| 3790 | i.types[op].bitfield.disp16 = 0; |
| 3791 | i.types[op].bitfield.disp32 = 0; |
| 3792 | i.types[op].bitfield.disp32s = 0; |
| 3793 | i.types[op].bitfield.disp64 = 0; |
| 3794 | i.op[op].disps = 0; |
| 3795 | i.disp_operands--; |
| 3796 | } |
| 3797 | else if (flag_code == CODE_64BIT) |
| 3798 | { |
| 3799 | if (fits_in_signed_long (op_disp)) |
| 3800 | { |
| 3801 | i.types[op].bitfield.disp64 = 0; |
| 3802 | i.types[op].bitfield.disp32s = 1; |
| 3803 | } |
| 3804 | if (i.prefix[ADDR_PREFIX] |
| 3805 | && fits_in_unsigned_long (op_disp)) |
| 3806 | i.types[op].bitfield.disp32 = 1; |
| 3807 | } |
| 3808 | if ((i.types[op].bitfield.disp32 |
| 3809 | || i.types[op].bitfield.disp32s |
| 3810 | || i.types[op].bitfield.disp16) |
| 3811 | && fits_in_signed_byte (op_disp)) |
| 3812 | i.types[op].bitfield.disp8 = 1; |
| 3813 | } |
| 3814 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
| 3815 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) |
| 3816 | { |
| 3817 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, |
| 3818 | i.op[op].disps, 0, i.reloc[op]); |
| 3819 | i.types[op].bitfield.disp8 = 0; |
| 3820 | i.types[op].bitfield.disp16 = 0; |
| 3821 | i.types[op].bitfield.disp32 = 0; |
| 3822 | i.types[op].bitfield.disp32s = 0; |
| 3823 | i.types[op].bitfield.disp64 = 0; |
| 3824 | } |
| 3825 | else |
| 3826 | /* We only support 64bit displacement on constants. */ |
| 3827 | i.types[op].bitfield.disp64 = 0; |
| 3828 | } |
| 3829 | } |
| 3830 | |
| 3831 | /* Check if operands are valid for the instruction. Update VEX |
| 3832 | operand types. */ |
| 3833 | |
| 3834 | static int |
| 3835 | VEX_check_operands (const insn_template *t) |
| 3836 | { |
| 3837 | if (!t->opcode_modifier.vex) |
| 3838 | return 0; |
| 3839 | |
| 3840 | /* Only check VEX_Imm4, which must be the first operand. */ |
| 3841 | if (t->operand_types[0].bitfield.vec_imm4) |
| 3842 | { |
| 3843 | if (i.op[0].imms->X_op != O_constant |
| 3844 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) |
| 3845 | { |
| 3846 | i.error = bad_imm4; |
| 3847 | return 1; |
| 3848 | } |
| 3849 | |
| 3850 | /* Turn off Imm8 so that update_imm won't complain. */ |
| 3851 | i.types[0] = vec_imm4; |
| 3852 | } |
| 3853 | |
| 3854 | return 0; |
| 3855 | } |
| 3856 | |
| 3857 | static const insn_template * |
| 3858 | match_template (void) |
| 3859 | { |
| 3860 | /* Points to template once we've found it. */ |
| 3861 | const insn_template *t; |
| 3862 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
| 3863 | i386_operand_type overlap4; |
| 3864 | unsigned int found_reverse_match; |
| 3865 | i386_opcode_modifier suffix_check; |
| 3866 | i386_operand_type operand_types [MAX_OPERANDS]; |
| 3867 | int addr_prefix_disp; |
| 3868 | unsigned int j; |
| 3869 | unsigned int found_cpu_match; |
| 3870 | unsigned int check_register; |
| 3871 | |
| 3872 | #if MAX_OPERANDS != 5 |
| 3873 | # error "MAX_OPERANDS must be 5." |
| 3874 | #endif |
| 3875 | |
| 3876 | found_reverse_match = 0; |
| 3877 | addr_prefix_disp = -1; |
| 3878 | |
| 3879 | memset (&suffix_check, 0, sizeof (suffix_check)); |
| 3880 | if (i.suffix == BYTE_MNEM_SUFFIX) |
| 3881 | suffix_check.no_bsuf = 1; |
| 3882 | else if (i.suffix == WORD_MNEM_SUFFIX) |
| 3883 | suffix_check.no_wsuf = 1; |
| 3884 | else if (i.suffix == SHORT_MNEM_SUFFIX) |
| 3885 | suffix_check.no_ssuf = 1; |
| 3886 | else if (i.suffix == LONG_MNEM_SUFFIX) |
| 3887 | suffix_check.no_lsuf = 1; |
| 3888 | else if (i.suffix == QWORD_MNEM_SUFFIX) |
| 3889 | suffix_check.no_qsuf = 1; |
| 3890 | else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) |
| 3891 | suffix_check.no_ldsuf = 1; |
| 3892 | |
| 3893 | /* Must have right number of operands. */ |
| 3894 | i.error = number_of_operands_mismatch; |
| 3895 | |
| 3896 | for (t = current_templates->start; t < current_templates->end; t++) |
| 3897 | { |
| 3898 | addr_prefix_disp = -1; |
| 3899 | |
| 3900 | if (i.operands != t->operands) |
| 3901 | continue; |
| 3902 | |
| 3903 | /* Check processor support. */ |
| 3904 | i.error = unsupported; |
| 3905 | found_cpu_match = (cpu_flags_match (t) |
| 3906 | == CPU_FLAGS_PERFECT_MATCH); |
| 3907 | if (!found_cpu_match) |
| 3908 | continue; |
| 3909 | |
| 3910 | /* Check old gcc support. */ |
| 3911 | i.error = old_gcc_only; |
| 3912 | if (!old_gcc && t->opcode_modifier.oldgcc) |
| 3913 | continue; |
| 3914 | |
| 3915 | /* Check AT&T mnemonic. */ |
| 3916 | i.error = unsupported_with_intel_mnemonic; |
| 3917 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
| 3918 | continue; |
| 3919 | |
| 3920 | /* Check AT&T/Intel syntax. */ |
| 3921 | i.error = unsupported_syntax; |
| 3922 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
| 3923 | || (!intel_syntax && t->opcode_modifier.intelsyntax)) |
| 3924 | continue; |
| 3925 | |
| 3926 | /* Check the suffix, except for some instructions in intel mode. */ |
| 3927 | i.error = invalid_instruction_suffix; |
| 3928 | if ((!intel_syntax || !t->opcode_modifier.ignoresize) |
| 3929 | && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) |
| 3930 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) |
| 3931 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) |
| 3932 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) |
| 3933 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) |
| 3934 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) |
| 3935 | continue; |
| 3936 | |
| 3937 | if (!operand_size_match (t)) |
| 3938 | continue; |
| 3939 | |
| 3940 | for (j = 0; j < MAX_OPERANDS; j++) |
| 3941 | operand_types[j] = t->operand_types[j]; |
| 3942 | |
| 3943 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
| 3944 | if (i.suffix == QWORD_MNEM_SUFFIX |
| 3945 | && flag_code != CODE_64BIT |
| 3946 | && (intel_syntax |
| 3947 | ? (!t->opcode_modifier.ignoresize |
| 3948 | && !intel_float_operand (t->name)) |
| 3949 | : intel_float_operand (t->name) != 2) |
| 3950 | && ((!operand_types[0].bitfield.regmmx |
| 3951 | && !operand_types[0].bitfield.regxmm |
| 3952 | && !operand_types[0].bitfield.regymm) |
| 3953 | || (!operand_types[t->operands > 1].bitfield.regmmx |
| 3954 | && !!operand_types[t->operands > 1].bitfield.regxmm |
| 3955 | && !!operand_types[t->operands > 1].bitfield.regymm)) |
| 3956 | && (t->base_opcode != 0x0fc7 |
| 3957 | || t->extension_opcode != 1 /* cmpxchg8b */)) |
| 3958 | continue; |
| 3959 | |
| 3960 | /* In general, don't allow 32-bit operands on pre-386. */ |
| 3961 | else if (i.suffix == LONG_MNEM_SUFFIX |
| 3962 | && !cpu_arch_flags.bitfield.cpui386 |
| 3963 | && (intel_syntax |
| 3964 | ? (!t->opcode_modifier.ignoresize |
| 3965 | && !intel_float_operand (t->name)) |
| 3966 | : intel_float_operand (t->name) != 2) |
| 3967 | && ((!operand_types[0].bitfield.regmmx |
| 3968 | && !operand_types[0].bitfield.regxmm) |
| 3969 | || (!operand_types[t->operands > 1].bitfield.regmmx |
| 3970 | && !!operand_types[t->operands > 1].bitfield.regxmm))) |
| 3971 | continue; |
| 3972 | |
| 3973 | /* Do not verify operands when there are none. */ |
| 3974 | else |
| 3975 | { |
| 3976 | if (!t->operands) |
| 3977 | /* We've found a match; break out of loop. */ |
| 3978 | break; |
| 3979 | } |
| 3980 | |
| 3981 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
| 3982 | into Disp32/Disp16/Disp32 operand. */ |
| 3983 | if (i.prefix[ADDR_PREFIX] != 0) |
| 3984 | { |
| 3985 | /* There should be only one Disp operand. */ |
| 3986 | switch (flag_code) |
| 3987 | { |
| 3988 | case CODE_16BIT: |
| 3989 | for (j = 0; j < MAX_OPERANDS; j++) |
| 3990 | { |
| 3991 | if (operand_types[j].bitfield.disp16) |
| 3992 | { |
| 3993 | addr_prefix_disp = j; |
| 3994 | operand_types[j].bitfield.disp32 = 1; |
| 3995 | operand_types[j].bitfield.disp16 = 0; |
| 3996 | break; |
| 3997 | } |
| 3998 | } |
| 3999 | break; |
| 4000 | case CODE_32BIT: |
| 4001 | for (j = 0; j < MAX_OPERANDS; j++) |
| 4002 | { |
| 4003 | if (operand_types[j].bitfield.disp32) |
| 4004 | { |
| 4005 | addr_prefix_disp = j; |
| 4006 | operand_types[j].bitfield.disp32 = 0; |
| 4007 | operand_types[j].bitfield.disp16 = 1; |
| 4008 | break; |
| 4009 | } |
| 4010 | } |
| 4011 | break; |
| 4012 | case CODE_64BIT: |
| 4013 | for (j = 0; j < MAX_OPERANDS; j++) |
| 4014 | { |
| 4015 | if (operand_types[j].bitfield.disp64) |
| 4016 | { |
| 4017 | addr_prefix_disp = j; |
| 4018 | operand_types[j].bitfield.disp64 = 0; |
| 4019 | operand_types[j].bitfield.disp32 = 1; |
| 4020 | break; |
| 4021 | } |
| 4022 | } |
| 4023 | break; |
| 4024 | } |
| 4025 | } |
| 4026 | |
| 4027 | /* We check register size if needed. */ |
| 4028 | check_register = t->opcode_modifier.checkregsize; |
| 4029 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
| 4030 | switch (t->operands) |
| 4031 | { |
| 4032 | case 1: |
| 4033 | if (!operand_type_match (overlap0, i.types[0])) |
| 4034 | continue; |
| 4035 | break; |
| 4036 | case 2: |
| 4037 | /* xchg %eax, %eax is a special case. It is an aliase for nop |
| 4038 | only in 32bit mode and we can use opcode 0x90. In 64bit |
| 4039 | mode, we can't use 0x90 for xchg %eax, %eax since it should |
| 4040 | zero-extend %eax to %rax. */ |
| 4041 | if (flag_code == CODE_64BIT |
| 4042 | && t->base_opcode == 0x90 |
| 4043 | && operand_type_equal (&i.types [0], &acc32) |
| 4044 | && operand_type_equal (&i.types [1], &acc32)) |
| 4045 | continue; |
| 4046 | if (i.swap_operand) |
| 4047 | { |
| 4048 | /* If we swap operand in encoding, we either match |
| 4049 | the next one or reverse direction of operands. */ |
| 4050 | if (t->opcode_modifier.s) |
| 4051 | continue; |
| 4052 | else if (t->opcode_modifier.d) |
| 4053 | goto check_reverse; |
| 4054 | } |
| 4055 | |
| 4056 | case 3: |
| 4057 | /* If we swap operand in encoding, we match the next one. */ |
| 4058 | if (i.swap_operand && t->opcode_modifier.s) |
| 4059 | continue; |
| 4060 | case 4: |
| 4061 | case 5: |
| 4062 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
| 4063 | if (!operand_type_match (overlap0, i.types[0]) |
| 4064 | || !operand_type_match (overlap1, i.types[1]) |
| 4065 | || (check_register |
| 4066 | && !operand_type_register_match (overlap0, i.types[0], |
| 4067 | operand_types[0], |
| 4068 | overlap1, i.types[1], |
| 4069 | operand_types[1]))) |
| 4070 | { |
| 4071 | /* Check if other direction is valid ... */ |
| 4072 | if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
| 4073 | continue; |
| 4074 | |
| 4075 | check_reverse: |
| 4076 | /* Try reversing direction of operands. */ |
| 4077 | overlap0 = operand_type_and (i.types[0], operand_types[1]); |
| 4078 | overlap1 = operand_type_and (i.types[1], operand_types[0]); |
| 4079 | if (!operand_type_match (overlap0, i.types[0]) |
| 4080 | || !operand_type_match (overlap1, i.types[1]) |
| 4081 | || (check_register |
| 4082 | && !operand_type_register_match (overlap0, |
| 4083 | i.types[0], |
| 4084 | operand_types[1], |
| 4085 | overlap1, |
| 4086 | i.types[1], |
| 4087 | operand_types[0]))) |
| 4088 | { |
| 4089 | /* Does not match either direction. */ |
| 4090 | continue; |
| 4091 | } |
| 4092 | /* found_reverse_match holds which of D or FloatDR |
| 4093 | we've found. */ |
| 4094 | if (t->opcode_modifier.d) |
| 4095 | found_reverse_match = Opcode_D; |
| 4096 | else if (t->opcode_modifier.floatd) |
| 4097 | found_reverse_match = Opcode_FloatD; |
| 4098 | else |
| 4099 | found_reverse_match = 0; |
| 4100 | if (t->opcode_modifier.floatr) |
| 4101 | found_reverse_match |= Opcode_FloatR; |
| 4102 | } |
| 4103 | else |
| 4104 | { |
| 4105 | /* Found a forward 2 operand match here. */ |
| 4106 | switch (t->operands) |
| 4107 | { |
| 4108 | case 5: |
| 4109 | overlap4 = operand_type_and (i.types[4], |
| 4110 | operand_types[4]); |
| 4111 | case 4: |
| 4112 | overlap3 = operand_type_and (i.types[3], |
| 4113 | operand_types[3]); |
| 4114 | case 3: |
| 4115 | overlap2 = operand_type_and (i.types[2], |
| 4116 | operand_types[2]); |
| 4117 | break; |
| 4118 | } |
| 4119 | |
| 4120 | switch (t->operands) |
| 4121 | { |
| 4122 | case 5: |
| 4123 | if (!operand_type_match (overlap4, i.types[4]) |
| 4124 | || !operand_type_register_match (overlap3, |
| 4125 | i.types[3], |
| 4126 | operand_types[3], |
| 4127 | overlap4, |
| 4128 | i.types[4], |
| 4129 | operand_types[4])) |
| 4130 | continue; |
| 4131 | case 4: |
| 4132 | if (!operand_type_match (overlap3, i.types[3]) |
| 4133 | || (check_register |
| 4134 | && !operand_type_register_match (overlap2, |
| 4135 | i.types[2], |
| 4136 | operand_types[2], |
| 4137 | overlap3, |
| 4138 | i.types[3], |
| 4139 | operand_types[3]))) |
| 4140 | continue; |
| 4141 | case 3: |
| 4142 | /* Here we make use of the fact that there are no |
| 4143 | reverse match 3 operand instructions, and all 3 |
| 4144 | operand instructions only need to be checked for |
| 4145 | register consistency between operands 2 and 3. */ |
| 4146 | if (!operand_type_match (overlap2, i.types[2]) |
| 4147 | || (check_register |
| 4148 | && !operand_type_register_match (overlap1, |
| 4149 | i.types[1], |
| 4150 | operand_types[1], |
| 4151 | overlap2, |
| 4152 | i.types[2], |
| 4153 | operand_types[2]))) |
| 4154 | continue; |
| 4155 | break; |
| 4156 | } |
| 4157 | } |
| 4158 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
| 4159 | slip through to break. */ |
| 4160 | } |
| 4161 | if (!found_cpu_match) |
| 4162 | { |
| 4163 | found_reverse_match = 0; |
| 4164 | continue; |
| 4165 | } |
| 4166 | |
| 4167 | /* Check if VEX operands are valid. */ |
| 4168 | if (VEX_check_operands (t)) |
| 4169 | continue; |
| 4170 | |
| 4171 | /* We've found a match; break out of loop. */ |
| 4172 | break; |
| 4173 | } |
| 4174 | |
| 4175 | if (t == current_templates->end) |
| 4176 | { |
| 4177 | /* We found no match. */ |
| 4178 | const char *err_msg; |
| 4179 | switch (i.error) |
| 4180 | { |
| 4181 | default: |
| 4182 | abort (); |
| 4183 | case operand_size_mismatch: |
| 4184 | err_msg = _("operand size mismatch"); |
| 4185 | break; |
| 4186 | case operand_type_mismatch: |
| 4187 | err_msg = _("operand type mismatch"); |
| 4188 | break; |
| 4189 | case register_type_mismatch: |
| 4190 | err_msg = _("register type mismatch"); |
| 4191 | break; |
| 4192 | case number_of_operands_mismatch: |
| 4193 | err_msg = _("number of operands mismatch"); |
| 4194 | break; |
| 4195 | case invalid_instruction_suffix: |
| 4196 | err_msg = _("invalid instruction suffix"); |
| 4197 | break; |
| 4198 | case bad_imm4: |
| 4199 | err_msg = _("Imm4 isn't the first operand"); |
| 4200 | break; |
| 4201 | case old_gcc_only: |
| 4202 | err_msg = _("only supported with old gcc"); |
| 4203 | break; |
| 4204 | case unsupported_with_intel_mnemonic: |
| 4205 | err_msg = _("unsupported with Intel mnemonic"); |
| 4206 | break; |
| 4207 | case unsupported_syntax: |
| 4208 | err_msg = _("unsupported syntax"); |
| 4209 | break; |
| 4210 | case unsupported: |
| 4211 | err_msg = _("unsupported"); |
| 4212 | break; |
| 4213 | } |
| 4214 | as_bad (_("%s for `%s'"), err_msg, |
| 4215 | current_templates->start->name); |
| 4216 | return NULL; |
| 4217 | } |
| 4218 | |
| 4219 | if (!quiet_warnings) |
| 4220 | { |
| 4221 | if (!intel_syntax |
| 4222 | && (i.types[0].bitfield.jumpabsolute |
| 4223 | != operand_types[0].bitfield.jumpabsolute)) |
| 4224 | { |
| 4225 | as_warn (_("indirect %s without `*'"), t->name); |
| 4226 | } |
| 4227 | |
| 4228 | if (t->opcode_modifier.isprefix |
| 4229 | && t->opcode_modifier.ignoresize) |
| 4230 | { |
| 4231 | /* Warn them that a data or address size prefix doesn't |
| 4232 | affect assembly of the next line of code. */ |
| 4233 | as_warn (_("stand-alone `%s' prefix"), t->name); |
| 4234 | } |
| 4235 | } |
| 4236 | |
| 4237 | /* Copy the template we found. */ |
| 4238 | i.tm = *t; |
| 4239 | |
| 4240 | if (addr_prefix_disp != -1) |
| 4241 | i.tm.operand_types[addr_prefix_disp] |
| 4242 | = operand_types[addr_prefix_disp]; |
| 4243 | |
| 4244 | if (found_reverse_match) |
| 4245 | { |
| 4246 | /* If we found a reverse match we must alter the opcode |
| 4247 | direction bit. found_reverse_match holds bits to change |
| 4248 | (different for int & float insns). */ |
| 4249 | |
| 4250 | i.tm.base_opcode ^= found_reverse_match; |
| 4251 | |
| 4252 | i.tm.operand_types[0] = operand_types[1]; |
| 4253 | i.tm.operand_types[1] = operand_types[0]; |
| 4254 | } |
| 4255 | |
| 4256 | return t; |
| 4257 | } |
| 4258 | |
| 4259 | static int |
| 4260 | check_string (void) |
| 4261 | { |
| 4262 | int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; |
| 4263 | if (i.tm.operand_types[mem_op].bitfield.esseg) |
| 4264 | { |
| 4265 | if (i.seg[0] != NULL && i.seg[0] != &es) |
| 4266 | { |
| 4267 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
| 4268 | i.tm.name, |
| 4269 | mem_op + 1, |
| 4270 | register_prefix); |
| 4271 | return 0; |
| 4272 | } |
| 4273 | /* There's only ever one segment override allowed per instruction. |
| 4274 | This instruction possibly has a legal segment override on the |
| 4275 | second operand, so copy the segment to where non-string |
| 4276 | instructions store it, allowing common code. */ |
| 4277 | i.seg[0] = i.seg[1]; |
| 4278 | } |
| 4279 | else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) |
| 4280 | { |
| 4281 | if (i.seg[1] != NULL && i.seg[1] != &es) |
| 4282 | { |
| 4283 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
| 4284 | i.tm.name, |
| 4285 | mem_op + 2, |
| 4286 | register_prefix); |
| 4287 | return 0; |
| 4288 | } |
| 4289 | } |
| 4290 | return 1; |
| 4291 | } |
| 4292 | |
| 4293 | static int |
| 4294 | process_suffix (void) |
| 4295 | { |
| 4296 | /* If matched instruction specifies an explicit instruction mnemonic |
| 4297 | suffix, use it. */ |
| 4298 | if (i.tm.opcode_modifier.size16) |
| 4299 | i.suffix = WORD_MNEM_SUFFIX; |
| 4300 | else if (i.tm.opcode_modifier.size32) |
| 4301 | i.suffix = LONG_MNEM_SUFFIX; |
| 4302 | else if (i.tm.opcode_modifier.size64) |
| 4303 | i.suffix = QWORD_MNEM_SUFFIX; |
| 4304 | else if (i.reg_operands) |
| 4305 | { |
| 4306 | /* If there's no instruction mnemonic suffix we try to invent one |
| 4307 | based on register operands. */ |
| 4308 | if (!i.suffix) |
| 4309 | { |
| 4310 | /* We take i.suffix from the last register operand specified, |
| 4311 | Destination register type is more significant than source |
| 4312 | register type. crc32 in SSE4.2 prefers source register |
| 4313 | type. */ |
| 4314 | if (i.tm.base_opcode == 0xf20f38f1) |
| 4315 | { |
| 4316 | if (i.types[0].bitfield.reg16) |
| 4317 | i.suffix = WORD_MNEM_SUFFIX; |
| 4318 | else if (i.types[0].bitfield.reg32) |
| 4319 | i.suffix = LONG_MNEM_SUFFIX; |
| 4320 | else if (i.types[0].bitfield.reg64) |
| 4321 | i.suffix = QWORD_MNEM_SUFFIX; |
| 4322 | } |
| 4323 | else if (i.tm.base_opcode == 0xf20f38f0) |
| 4324 | { |
| 4325 | if (i.types[0].bitfield.reg8) |
| 4326 | i.suffix = BYTE_MNEM_SUFFIX; |
| 4327 | } |
| 4328 | |
| 4329 | if (!i.suffix) |
| 4330 | { |
| 4331 | int op; |
| 4332 | |
| 4333 | if (i.tm.base_opcode == 0xf20f38f1 |
| 4334 | || i.tm.base_opcode == 0xf20f38f0) |
| 4335 | { |
| 4336 | /* We have to know the operand size for crc32. */ |
| 4337 | as_bad (_("ambiguous memory operand size for `%s`"), |
| 4338 | i.tm.name); |
| 4339 | return 0; |
| 4340 | } |
| 4341 | |
| 4342 | for (op = i.operands; --op >= 0;) |
| 4343 | if (!i.tm.operand_types[op].bitfield.inoutportreg) |
| 4344 | { |
| 4345 | if (i.types[op].bitfield.reg8) |
| 4346 | { |
| 4347 | i.suffix = BYTE_MNEM_SUFFIX; |
| 4348 | break; |
| 4349 | } |
| 4350 | else if (i.types[op].bitfield.reg16) |
| 4351 | { |
| 4352 | i.suffix = WORD_MNEM_SUFFIX; |
| 4353 | break; |
| 4354 | } |
| 4355 | else if (i.types[op].bitfield.reg32) |
| 4356 | { |
| 4357 | i.suffix = LONG_MNEM_SUFFIX; |
| 4358 | break; |
| 4359 | } |
| 4360 | else if (i.types[op].bitfield.reg64) |
| 4361 | { |
| 4362 | i.suffix = QWORD_MNEM_SUFFIX; |
| 4363 | break; |
| 4364 | } |
| 4365 | } |
| 4366 | } |
| 4367 | } |
| 4368 | else if (i.suffix == BYTE_MNEM_SUFFIX) |
| 4369 | { |
| 4370 | if (intel_syntax |
| 4371 | && i.tm.opcode_modifier.ignoresize |
| 4372 | && i.tm.opcode_modifier.no_bsuf) |
| 4373 | i.suffix = 0; |
| 4374 | else if (!check_byte_reg ()) |
| 4375 | return 0; |
| 4376 | } |
| 4377 | else if (i.suffix == LONG_MNEM_SUFFIX) |
| 4378 | { |
| 4379 | if (intel_syntax |
| 4380 | && i.tm.opcode_modifier.ignoresize |
| 4381 | && i.tm.opcode_modifier.no_lsuf) |
| 4382 | i.suffix = 0; |
| 4383 | else if (!check_long_reg ()) |
| 4384 | return 0; |
| 4385 | } |
| 4386 | else if (i.suffix == QWORD_MNEM_SUFFIX) |
| 4387 | { |
| 4388 | if (intel_syntax |
| 4389 | && i.tm.opcode_modifier.ignoresize |
| 4390 | && i.tm.opcode_modifier.no_qsuf) |
| 4391 | i.suffix = 0; |
| 4392 | else if (!check_qword_reg ()) |
| 4393 | return 0; |
| 4394 | } |
| 4395 | else if (i.suffix == WORD_MNEM_SUFFIX) |
| 4396 | { |
| 4397 | if (intel_syntax |
| 4398 | && i.tm.opcode_modifier.ignoresize |
| 4399 | && i.tm.opcode_modifier.no_wsuf) |
| 4400 | i.suffix = 0; |
| 4401 | else if (!check_word_reg ()) |
| 4402 | return 0; |
| 4403 | } |
| 4404 | else if (i.suffix == XMMWORD_MNEM_SUFFIX |
| 4405 | || i.suffix == YMMWORD_MNEM_SUFFIX) |
| 4406 | { |
| 4407 | /* Skip if the instruction has x/y suffix. match_template |
| 4408 | should check if it is a valid suffix. */ |
| 4409 | } |
| 4410 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
| 4411 | /* Do nothing if the instruction is going to ignore the prefix. */ |
| 4412 | ; |
| 4413 | else |
| 4414 | abort (); |
| 4415 | } |
| 4416 | else if (i.tm.opcode_modifier.defaultsize |
| 4417 | && !i.suffix |
| 4418 | /* exclude fldenv/frstor/fsave/fstenv */ |
| 4419 | && i.tm.opcode_modifier.no_ssuf) |
| 4420 | { |
| 4421 | i.suffix = stackop_size; |
| 4422 | } |
| 4423 | else if (intel_syntax |
| 4424 | && !i.suffix |
| 4425 | && (i.tm.operand_types[0].bitfield.jumpabsolute |
| 4426 | || i.tm.opcode_modifier.jumpbyte |
| 4427 | || i.tm.opcode_modifier.jumpintersegment |
| 4428 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
| 4429 | && i.tm.extension_opcode <= 3))) |
| 4430 | { |
| 4431 | switch (flag_code) |
| 4432 | { |
| 4433 | case CODE_64BIT: |
| 4434 | if (!i.tm.opcode_modifier.no_qsuf) |
| 4435 | { |
| 4436 | i.suffix = QWORD_MNEM_SUFFIX; |
| 4437 | break; |
| 4438 | } |
| 4439 | case CODE_32BIT: |
| 4440 | if (!i.tm.opcode_modifier.no_lsuf) |
| 4441 | i.suffix = LONG_MNEM_SUFFIX; |
| 4442 | break; |
| 4443 | case CODE_16BIT: |
| 4444 | if (!i.tm.opcode_modifier.no_wsuf) |
| 4445 | i.suffix = WORD_MNEM_SUFFIX; |
| 4446 | break; |
| 4447 | } |
| 4448 | } |
| 4449 | |
| 4450 | if (!i.suffix) |
| 4451 | { |
| 4452 | if (!intel_syntax) |
| 4453 | { |
| 4454 | if (i.tm.opcode_modifier.w) |
| 4455 | { |
| 4456 | as_bad (_("no instruction mnemonic suffix given and " |
| 4457 | "no register operands; can't size instruction")); |
| 4458 | return 0; |
| 4459 | } |
| 4460 | } |
| 4461 | else |
| 4462 | { |
| 4463 | unsigned int suffixes; |
| 4464 | |
| 4465 | suffixes = !i.tm.opcode_modifier.no_bsuf; |
| 4466 | if (!i.tm.opcode_modifier.no_wsuf) |
| 4467 | suffixes |= 1 << 1; |
| 4468 | if (!i.tm.opcode_modifier.no_lsuf) |
| 4469 | suffixes |= 1 << 2; |
| 4470 | if (!i.tm.opcode_modifier.no_ldsuf) |
| 4471 | suffixes |= 1 << 3; |
| 4472 | if (!i.tm.opcode_modifier.no_ssuf) |
| 4473 | suffixes |= 1 << 4; |
| 4474 | if (!i.tm.opcode_modifier.no_qsuf) |
| 4475 | suffixes |= 1 << 5; |
| 4476 | |
| 4477 | /* There are more than suffix matches. */ |
| 4478 | if (i.tm.opcode_modifier.w |
| 4479 | || ((suffixes & (suffixes - 1)) |
| 4480 | && !i.tm.opcode_modifier.defaultsize |
| 4481 | && !i.tm.opcode_modifier.ignoresize)) |
| 4482 | { |
| 4483 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
| 4484 | return 0; |
| 4485 | } |
| 4486 | } |
| 4487 | } |
| 4488 | |
| 4489 | /* Change the opcode based on the operand size given by i.suffix; |
| 4490 | We don't need to change things for byte insns. */ |
| 4491 | |
| 4492 | if (i.suffix |
| 4493 | && i.suffix != BYTE_MNEM_SUFFIX |
| 4494 | && i.suffix != XMMWORD_MNEM_SUFFIX |
| 4495 | && i.suffix != YMMWORD_MNEM_SUFFIX) |
| 4496 | { |
| 4497 | /* It's not a byte, select word/dword operation. */ |
| 4498 | if (i.tm.opcode_modifier.w) |
| 4499 | { |
| 4500 | if (i.tm.opcode_modifier.shortform) |
| 4501 | i.tm.base_opcode |= 8; |
| 4502 | else |
| 4503 | i.tm.base_opcode |= 1; |
| 4504 | } |
| 4505 | |
| 4506 | /* Now select between word & dword operations via the operand |
| 4507 | size prefix, except for instructions that will ignore this |
| 4508 | prefix anyway. */ |
| 4509 | if (i.tm.opcode_modifier.addrprefixop0) |
| 4510 | { |
| 4511 | /* The address size override prefix changes the size of the |
| 4512 | first operand. */ |
| 4513 | if ((flag_code == CODE_32BIT |
| 4514 | && i.op->regs[0].reg_type.bitfield.reg16) |
| 4515 | || (flag_code != CODE_32BIT |
| 4516 | && i.op->regs[0].reg_type.bitfield.reg32)) |
| 4517 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
| 4518 | return 0; |
| 4519 | } |
| 4520 | else if (i.suffix != QWORD_MNEM_SUFFIX |
| 4521 | && i.suffix != LONG_DOUBLE_MNEM_SUFFIX |
| 4522 | && !i.tm.opcode_modifier.ignoresize |
| 4523 | && !i.tm.opcode_modifier.floatmf |
| 4524 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
| 4525 | || (flag_code == CODE_64BIT |
| 4526 | && i.tm.opcode_modifier.jumpbyte))) |
| 4527 | { |
| 4528 | unsigned int prefix = DATA_PREFIX_OPCODE; |
| 4529 | |
| 4530 | if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ |
| 4531 | prefix = ADDR_PREFIX_OPCODE; |
| 4532 | |
| 4533 | if (!add_prefix (prefix)) |
| 4534 | return 0; |
| 4535 | } |
| 4536 | |
| 4537 | /* Set mode64 for an operand. */ |
| 4538 | if (i.suffix == QWORD_MNEM_SUFFIX |
| 4539 | && flag_code == CODE_64BIT |
| 4540 | && !i.tm.opcode_modifier.norex64) |
| 4541 | { |
| 4542 | /* Special case for xchg %rax,%rax. It is NOP and doesn't |
| 4543 | need rex64. cmpxchg8b is also a special case. */ |
| 4544 | if (! (i.operands == 2 |
| 4545 | && i.tm.base_opcode == 0x90 |
| 4546 | && i.tm.extension_opcode == None |
| 4547 | && operand_type_equal (&i.types [0], &acc64) |
| 4548 | && operand_type_equal (&i.types [1], &acc64)) |
| 4549 | && ! (i.operands == 1 |
| 4550 | && i.tm.base_opcode == 0xfc7 |
| 4551 | && i.tm.extension_opcode == 1 |
| 4552 | && !operand_type_check (i.types [0], reg) |
| 4553 | && operand_type_check (i.types [0], anymem))) |
| 4554 | i.rex |= REX_W; |
| 4555 | } |
| 4556 | |
| 4557 | /* Size floating point instruction. */ |
| 4558 | if (i.suffix == LONG_MNEM_SUFFIX) |
| 4559 | if (i.tm.opcode_modifier.floatmf) |
| 4560 | i.tm.base_opcode ^= 4; |
| 4561 | } |
| 4562 | |
| 4563 | return 1; |
| 4564 | } |
| 4565 | |
| 4566 | static int |
| 4567 | check_byte_reg (void) |
| 4568 | { |
| 4569 | int op; |
| 4570 | |
| 4571 | for (op = i.operands; --op >= 0;) |
| 4572 | { |
| 4573 | /* If this is an eight bit register, it's OK. If it's the 16 or |
| 4574 | 32 bit version of an eight bit register, we will just use the |
| 4575 | low portion, and that's OK too. */ |
| 4576 | if (i.types[op].bitfield.reg8) |
| 4577 | continue; |
| 4578 | |
| 4579 | /* crc32 doesn't generate this warning. */ |
| 4580 | if (i.tm.base_opcode == 0xf20f38f0) |
| 4581 | continue; |
| 4582 | |
| 4583 | if ((i.types[op].bitfield.reg16 |
| 4584 | || i.types[op].bitfield.reg32 |
| 4585 | || i.types[op].bitfield.reg64) |
| 4586 | && i.op[op].regs->reg_num < 4) |
| 4587 | { |
| 4588 | /* Prohibit these changes in the 64bit mode, since the |
| 4589 | lowering is more complicated. */ |
| 4590 | if (flag_code == CODE_64BIT |
| 4591 | && !i.tm.operand_types[op].bitfield.inoutportreg) |
| 4592 | { |
| 4593 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
| 4594 | register_prefix, i.op[op].regs->reg_name, |
| 4595 | i.suffix); |
| 4596 | return 0; |
| 4597 | } |
| 4598 | #if REGISTER_WARNINGS |
| 4599 | if (!quiet_warnings |
| 4600 | && !i.tm.operand_types[op].bitfield.inoutportreg) |
| 4601 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
| 4602 | register_prefix, |
| 4603 | (i.op[op].regs + (i.types[op].bitfield.reg16 |
| 4604 | ? REGNAM_AL - REGNAM_AX |
| 4605 | : REGNAM_AL - REGNAM_EAX))->reg_name, |
| 4606 | register_prefix, |
| 4607 | i.op[op].regs->reg_name, |
| 4608 | i.suffix); |
| 4609 | #endif |
| 4610 | continue; |
| 4611 | } |
| 4612 | /* Any other register is bad. */ |
| 4613 | if (i.types[op].bitfield.reg16 |
| 4614 | || i.types[op].bitfield.reg32 |
| 4615 | || i.types[op].bitfield.reg64 |
| 4616 | || i.types[op].bitfield.regmmx |
| 4617 | || i.types[op].bitfield.regxmm |
| 4618 | || i.types[op].bitfield.regymm |
| 4619 | || i.types[op].bitfield.sreg2 |
| 4620 | || i.types[op].bitfield.sreg3 |
| 4621 | || i.types[op].bitfield.control |
| 4622 | || i.types[op].bitfield.debug |
| 4623 | || i.types[op].bitfield.test |
| 4624 | || i.types[op].bitfield.floatreg |
| 4625 | || i.types[op].bitfield.floatacc) |
| 4626 | { |
| 4627 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
| 4628 | register_prefix, |
| 4629 | i.op[op].regs->reg_name, |
| 4630 | i.tm.name, |
| 4631 | i.suffix); |
| 4632 | return 0; |
| 4633 | } |
| 4634 | } |
| 4635 | return 1; |
| 4636 | } |
| 4637 | |
| 4638 | static int |
| 4639 | check_long_reg (void) |
| 4640 | { |
| 4641 | int op; |
| 4642 | |
| 4643 | for (op = i.operands; --op >= 0;) |
| 4644 | /* Reject eight bit registers, except where the template requires |
| 4645 | them. (eg. movzb) */ |
| 4646 | if (i.types[op].bitfield.reg8 |
| 4647 | && (i.tm.operand_types[op].bitfield.reg16 |
| 4648 | || i.tm.operand_types[op].bitfield.reg32 |
| 4649 | || i.tm.operand_types[op].bitfield.acc)) |
| 4650 | { |
| 4651 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
| 4652 | register_prefix, |
| 4653 | i.op[op].regs->reg_name, |
| 4654 | i.tm.name, |
| 4655 | i.suffix); |
| 4656 | return 0; |
| 4657 | } |
| 4658 | /* Warn if the e prefix on a general reg is missing. */ |
| 4659 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
| 4660 | && i.types[op].bitfield.reg16 |
| 4661 | && (i.tm.operand_types[op].bitfield.reg32 |
| 4662 | || i.tm.operand_types[op].bitfield.acc)) |
| 4663 | { |
| 4664 | /* Prohibit these changes in the 64bit mode, since the |
| 4665 | lowering is more complicated. */ |
| 4666 | if (flag_code == CODE_64BIT) |
| 4667 | { |
| 4668 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
| 4669 | register_prefix, i.op[op].regs->reg_name, |
| 4670 | i.suffix); |
| 4671 | return 0; |
| 4672 | } |
| 4673 | #if REGISTER_WARNINGS |
| 4674 | else |
| 4675 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
| 4676 | register_prefix, |
| 4677 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, |
| 4678 | register_prefix, |
| 4679 | i.op[op].regs->reg_name, |
| 4680 | i.suffix); |
| 4681 | #endif |
| 4682 | } |
| 4683 | /* Warn if the r prefix on a general reg is missing. */ |
| 4684 | else if (i.types[op].bitfield.reg64 |
| 4685 | && (i.tm.operand_types[op].bitfield.reg32 |
| 4686 | || i.tm.operand_types[op].bitfield.acc)) |
| 4687 | { |
| 4688 | if (intel_syntax |
| 4689 | && i.tm.opcode_modifier.toqword |
| 4690 | && !i.types[0].bitfield.regxmm) |
| 4691 | { |
| 4692 | /* Convert to QWORD. We want REX byte. */ |
| 4693 | i.suffix = QWORD_MNEM_SUFFIX; |
| 4694 | } |
| 4695 | else |
| 4696 | { |
| 4697 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
| 4698 | register_prefix, i.op[op].regs->reg_name, |
| 4699 | i.suffix); |
| 4700 | return 0; |
| 4701 | } |
| 4702 | } |
| 4703 | return 1; |
| 4704 | } |
| 4705 | |
| 4706 | static int |
| 4707 | check_qword_reg (void) |
| 4708 | { |
| 4709 | int op; |
| 4710 | |
| 4711 | for (op = i.operands; --op >= 0; ) |
| 4712 | /* Reject eight bit registers, except where the template requires |
| 4713 | them. (eg. movzb) */ |
| 4714 | if (i.types[op].bitfield.reg8 |
| 4715 | && (i.tm.operand_types[op].bitfield.reg16 |
| 4716 | || i.tm.operand_types[op].bitfield.reg32 |
| 4717 | || i.tm.operand_types[op].bitfield.acc)) |
| 4718 | { |
| 4719 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
| 4720 | register_prefix, |
| 4721 | i.op[op].regs->reg_name, |
| 4722 | i.tm.name, |
| 4723 | i.suffix); |
| 4724 | return 0; |
| 4725 | } |
| 4726 | /* Warn if the e prefix on a general reg is missing. */ |
| 4727 | else if ((i.types[op].bitfield.reg16 |
| 4728 | || i.types[op].bitfield.reg32) |
| 4729 | && (i.tm.operand_types[op].bitfield.reg32 |
| 4730 | || i.tm.operand_types[op].bitfield.acc)) |
| 4731 | { |
| 4732 | /* Prohibit these changes in the 64bit mode, since the |
| 4733 | lowering is more complicated. */ |
| 4734 | if (intel_syntax |
| 4735 | && i.tm.opcode_modifier.todword |
| 4736 | && !i.types[0].bitfield.regxmm) |
| 4737 | { |
| 4738 | /* Convert to DWORD. We don't want REX byte. */ |
| 4739 | i.suffix = LONG_MNEM_SUFFIX; |
| 4740 | } |
| 4741 | else |
| 4742 | { |
| 4743 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
| 4744 | register_prefix, i.op[op].regs->reg_name, |
| 4745 | i.suffix); |
| 4746 | return 0; |
| 4747 | } |
| 4748 | } |
| 4749 | return 1; |
| 4750 | } |
| 4751 | |
| 4752 | static int |
| 4753 | check_word_reg (void) |
| 4754 | { |
| 4755 | int op; |
| 4756 | for (op = i.operands; --op >= 0;) |
| 4757 | /* Reject eight bit registers, except where the template requires |
| 4758 | them. (eg. movzb) */ |
| 4759 | if (i.types[op].bitfield.reg8 |
| 4760 | && (i.tm.operand_types[op].bitfield.reg16 |
| 4761 | || i.tm.operand_types[op].bitfield.reg32 |
| 4762 | || i.tm.operand_types[op].bitfield.acc)) |
| 4763 | { |
| 4764 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
| 4765 | register_prefix, |
| 4766 | i.op[op].regs->reg_name, |
| 4767 | i.tm.name, |
| 4768 | i.suffix); |
| 4769 | return 0; |
| 4770 | } |
| 4771 | /* Warn if the e prefix on a general reg is present. */ |
| 4772 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
| 4773 | && i.types[op].bitfield.reg32 |
| 4774 | && (i.tm.operand_types[op].bitfield.reg16 |
| 4775 | || i.tm.operand_types[op].bitfield.acc)) |
| 4776 | { |
| 4777 | /* Prohibit these changes in the 64bit mode, since the |
| 4778 | lowering is more complicated. */ |
| 4779 | if (flag_code == CODE_64BIT) |
| 4780 | { |
| 4781 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
| 4782 | register_prefix, i.op[op].regs->reg_name, |
| 4783 | i.suffix); |
| 4784 | return 0; |
| 4785 | } |
| 4786 | else |
| 4787 | #if REGISTER_WARNINGS |
| 4788 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
| 4789 | register_prefix, |
| 4790 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, |
| 4791 | register_prefix, |
| 4792 | i.op[op].regs->reg_name, |
| 4793 | i.suffix); |
| 4794 | #endif |
| 4795 | } |
| 4796 | return 1; |
| 4797 | } |
| 4798 | |
| 4799 | static int |
| 4800 | update_imm (unsigned int j) |
| 4801 | { |
| 4802 | i386_operand_type overlap = i.types[j]; |
| 4803 | if ((overlap.bitfield.imm8 |
| 4804 | || overlap.bitfield.imm8s |
| 4805 | || overlap.bitfield.imm16 |
| 4806 | || overlap.bitfield.imm32 |
| 4807 | || overlap.bitfield.imm32s |
| 4808 | || overlap.bitfield.imm64) |
| 4809 | && !operand_type_equal (&overlap, &imm8) |
| 4810 | && !operand_type_equal (&overlap, &imm8s) |
| 4811 | && !operand_type_equal (&overlap, &imm16) |
| 4812 | && !operand_type_equal (&overlap, &imm32) |
| 4813 | && !operand_type_equal (&overlap, &imm32s) |
| 4814 | && !operand_type_equal (&overlap, &imm64)) |
| 4815 | { |
| 4816 | if (i.suffix) |
| 4817 | { |
| 4818 | i386_operand_type temp; |
| 4819 | |
| 4820 | operand_type_set (&temp, 0); |
| 4821 | if (i.suffix == BYTE_MNEM_SUFFIX) |
| 4822 | { |
| 4823 | temp.bitfield.imm8 = overlap.bitfield.imm8; |
| 4824 | temp.bitfield.imm8s = overlap.bitfield.imm8s; |
| 4825 | } |
| 4826 | else if (i.suffix == WORD_MNEM_SUFFIX) |
| 4827 | temp.bitfield.imm16 = overlap.bitfield.imm16; |
| 4828 | else if (i.suffix == QWORD_MNEM_SUFFIX) |
| 4829 | { |
| 4830 | temp.bitfield.imm64 = overlap.bitfield.imm64; |
| 4831 | temp.bitfield.imm32s = overlap.bitfield.imm32s; |
| 4832 | } |
| 4833 | else |
| 4834 | temp.bitfield.imm32 = overlap.bitfield.imm32; |
| 4835 | overlap = temp; |
| 4836 | } |
| 4837 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
| 4838 | || operand_type_equal (&overlap, &imm16_32) |
| 4839 | || operand_type_equal (&overlap, &imm16_32s)) |
| 4840 | { |
| 4841 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
| 4842 | overlap = imm16; |
| 4843 | else |
| 4844 | overlap = imm32s; |
| 4845 | } |
| 4846 | if (!operand_type_equal (&overlap, &imm8) |
| 4847 | && !operand_type_equal (&overlap, &imm8s) |
| 4848 | && !operand_type_equal (&overlap, &imm16) |
| 4849 | && !operand_type_equal (&overlap, &imm32) |
| 4850 | && !operand_type_equal (&overlap, &imm32s) |
| 4851 | && !operand_type_equal (&overlap, &imm64)) |
| 4852 | { |
| 4853 | as_bad (_("no instruction mnemonic suffix given; " |
| 4854 | "can't determine immediate size")); |
| 4855 | return 0; |
| 4856 | } |
| 4857 | } |
| 4858 | i.types[j] = overlap; |
| 4859 | |
| 4860 | return 1; |
| 4861 | } |
| 4862 | |
| 4863 | static int |
| 4864 | finalize_imm (void) |
| 4865 | { |
| 4866 | unsigned int j, n; |
| 4867 | |
| 4868 | /* Update the first 2 immediate operands. */ |
| 4869 | n = i.operands > 2 ? 2 : i.operands; |
| 4870 | if (n) |
| 4871 | { |
| 4872 | for (j = 0; j < n; j++) |
| 4873 | if (update_imm (j) == 0) |
| 4874 | return 0; |
| 4875 | |
| 4876 | /* The 3rd operand can't be immediate operand. */ |
| 4877 | gas_assert (operand_type_check (i.types[2], imm) == 0); |
| 4878 | } |
| 4879 | |
| 4880 | return 1; |
| 4881 | } |
| 4882 | |
| 4883 | static int |
| 4884 | bad_implicit_operand (int xmm) |
| 4885 | { |
| 4886 | const char *ireg = xmm ? "xmm0" : "ymm0"; |
| 4887 | |
| 4888 | if (intel_syntax) |
| 4889 | as_bad (_("the last operand of `%s' must be `%s%s'"), |
| 4890 | i.tm.name, register_prefix, ireg); |
| 4891 | else |
| 4892 | as_bad (_("the first operand of `%s' must be `%s%s'"), |
| 4893 | i.tm.name, register_prefix, ireg); |
| 4894 | return 0; |
| 4895 | } |
| 4896 | |
| 4897 | static int |
| 4898 | process_operands (void) |
| 4899 | { |
| 4900 | /* Default segment register this instruction will use for memory |
| 4901 | accesses. 0 means unknown. This is only for optimizing out |
| 4902 | unnecessary segment overrides. */ |
| 4903 | const seg_entry *default_seg = 0; |
| 4904 | |
| 4905 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
| 4906 | { |
| 4907 | unsigned int dupl = i.operands; |
| 4908 | unsigned int dest = dupl - 1; |
| 4909 | unsigned int j; |
| 4910 | |
| 4911 | /* The destination must be an xmm register. */ |
| 4912 | gas_assert (i.reg_operands |
| 4913 | && MAX_OPERANDS > dupl |
| 4914 | && operand_type_equal (&i.types[dest], ®xmm)); |
| 4915 | |
| 4916 | if (i.tm.opcode_modifier.firstxmm0) |
| 4917 | { |
| 4918 | /* The first operand is implicit and must be xmm0. */ |
| 4919 | gas_assert (operand_type_equal (&i.types[0], ®xmm)); |
| 4920 | if (i.op[0].regs->reg_num != 0) |
| 4921 | return bad_implicit_operand (1); |
| 4922 | |
| 4923 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
| 4924 | { |
| 4925 | /* Keep xmm0 for instructions with VEX prefix and 3 |
| 4926 | sources. */ |
| 4927 | goto duplicate; |
| 4928 | } |
| 4929 | else |
| 4930 | { |
| 4931 | /* We remove the first xmm0 and keep the number of |
| 4932 | operands unchanged, which in fact duplicates the |
| 4933 | destination. */ |
| 4934 | for (j = 1; j < i.operands; j++) |
| 4935 | { |
| 4936 | i.op[j - 1] = i.op[j]; |
| 4937 | i.types[j - 1] = i.types[j]; |
| 4938 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; |
| 4939 | } |
| 4940 | } |
| 4941 | } |
| 4942 | else if (i.tm.opcode_modifier.implicit1stxmm0) |
| 4943 | { |
| 4944 | gas_assert ((MAX_OPERANDS - 1) > dupl |
| 4945 | && (i.tm.opcode_modifier.vexsources |
| 4946 | == VEX3SOURCES)); |
| 4947 | |
| 4948 | /* Add the implicit xmm0 for instructions with VEX prefix |
| 4949 | and 3 sources. */ |
| 4950 | for (j = i.operands; j > 0; j--) |
| 4951 | { |
| 4952 | i.op[j] = i.op[j - 1]; |
| 4953 | i.types[j] = i.types[j - 1]; |
| 4954 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; |
| 4955 | } |
| 4956 | i.op[0].regs |
| 4957 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); |
| 4958 | i.types[0] = regxmm; |
| 4959 | i.tm.operand_types[0] = regxmm; |
| 4960 | |
| 4961 | i.operands += 2; |
| 4962 | i.reg_operands += 2; |
| 4963 | i.tm.operands += 2; |
| 4964 | |
| 4965 | dupl++; |
| 4966 | dest++; |
| 4967 | i.op[dupl] = i.op[dest]; |
| 4968 | i.types[dupl] = i.types[dest]; |
| 4969 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; |
| 4970 | } |
| 4971 | else |
| 4972 | { |
| 4973 | duplicate: |
| 4974 | i.operands++; |
| 4975 | i.reg_operands++; |
| 4976 | i.tm.operands++; |
| 4977 | |
| 4978 | i.op[dupl] = i.op[dest]; |
| 4979 | i.types[dupl] = i.types[dest]; |
| 4980 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; |
| 4981 | } |
| 4982 | |
| 4983 | if (i.tm.opcode_modifier.immext) |
| 4984 | process_immext (); |
| 4985 | } |
| 4986 | else if (i.tm.opcode_modifier.firstxmm0) |
| 4987 | { |
| 4988 | unsigned int j; |
| 4989 | |
| 4990 | /* The first operand is implicit and must be xmm0/ymm0. */ |
| 4991 | gas_assert (i.reg_operands |
| 4992 | && (operand_type_equal (&i.types[0], ®xmm) |
| 4993 | || operand_type_equal (&i.types[0], ®ymm))); |
| 4994 | if (i.op[0].regs->reg_num != 0) |
| 4995 | return bad_implicit_operand (i.types[0].bitfield.regxmm); |
| 4996 | |
| 4997 | for (j = 1; j < i.operands; j++) |
| 4998 | { |
| 4999 | i.op[j - 1] = i.op[j]; |
| 5000 | i.types[j - 1] = i.types[j]; |
| 5001 | |
| 5002 | /* We need to adjust fields in i.tm since they are used by |
| 5003 | build_modrm_byte. */ |
| 5004 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; |
| 5005 | } |
| 5006 | |
| 5007 | i.operands--; |
| 5008 | i.reg_operands--; |
| 5009 | i.tm.operands--; |
| 5010 | } |
| 5011 | else if (i.tm.opcode_modifier.regkludge) |
| 5012 | { |
| 5013 | /* The imul $imm, %reg instruction is converted into |
| 5014 | imul $imm, %reg, %reg, and the clr %reg instruction |
| 5015 | is converted into xor %reg, %reg. */ |
| 5016 | |
| 5017 | unsigned int first_reg_op; |
| 5018 | |
| 5019 | if (operand_type_check (i.types[0], reg)) |
| 5020 | first_reg_op = 0; |
| 5021 | else |
| 5022 | first_reg_op = 1; |
| 5023 | /* Pretend we saw the extra register operand. */ |
| 5024 | gas_assert (i.reg_operands == 1 |
| 5025 | && i.op[first_reg_op + 1].regs == 0); |
| 5026 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
| 5027 | i.types[first_reg_op + 1] = i.types[first_reg_op]; |
| 5028 | i.operands++; |
| 5029 | i.reg_operands++; |
| 5030 | } |
| 5031 | |
| 5032 | if (i.tm.opcode_modifier.shortform) |
| 5033 | { |
| 5034 | if (i.types[0].bitfield.sreg2 |
| 5035 | || i.types[0].bitfield.sreg3) |
| 5036 | { |
| 5037 | if (i.tm.base_opcode == POP_SEG_SHORT |
| 5038 | && i.op[0].regs->reg_num == 1) |
| 5039 | { |
| 5040 | as_bad (_("you can't `pop %scs'"), register_prefix); |
| 5041 | return 0; |
| 5042 | } |
| 5043 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
| 5044 | if ((i.op[0].regs->reg_flags & RegRex) != 0) |
| 5045 | i.rex |= REX_B; |
| 5046 | } |
| 5047 | else |
| 5048 | { |
| 5049 | /* The register or float register operand is in operand |
| 5050 | 0 or 1. */ |
| 5051 | unsigned int op; |
| 5052 | |
| 5053 | if (i.types[0].bitfield.floatreg |
| 5054 | || operand_type_check (i.types[0], reg)) |
| 5055 | op = 0; |
| 5056 | else |
| 5057 | op = 1; |
| 5058 | /* Register goes in low 3 bits of opcode. */ |
| 5059 | i.tm.base_opcode |= i.op[op].regs->reg_num; |
| 5060 | if ((i.op[op].regs->reg_flags & RegRex) != 0) |
| 5061 | i.rex |= REX_B; |
| 5062 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
| 5063 | { |
| 5064 | /* Warn about some common errors, but press on regardless. |
| 5065 | The first case can be generated by gcc (<= 2.8.1). */ |
| 5066 | if (i.operands == 2) |
| 5067 | { |
| 5068 | /* Reversed arguments on faddp, fsubp, etc. */ |
| 5069 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, |
| 5070 | register_prefix, i.op[!intel_syntax].regs->reg_name, |
| 5071 | register_prefix, i.op[intel_syntax].regs->reg_name); |
| 5072 | } |
| 5073 | else |
| 5074 | { |
| 5075 | /* Extraneous `l' suffix on fp insn. */ |
| 5076 | as_warn (_("translating to `%s %s%s'"), i.tm.name, |
| 5077 | register_prefix, i.op[0].regs->reg_name); |
| 5078 | } |
| 5079 | } |
| 5080 | } |
| 5081 | } |
| 5082 | else if (i.tm.opcode_modifier.modrm) |
| 5083 | { |
| 5084 | /* The opcode is completed (modulo i.tm.extension_opcode which |
| 5085 | must be put into the modrm byte). Now, we make the modrm and |
| 5086 | index base bytes based on all the info we've collected. */ |
| 5087 | |
| 5088 | default_seg = build_modrm_byte (); |
| 5089 | } |
| 5090 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
| 5091 | { |
| 5092 | default_seg = &ds; |
| 5093 | } |
| 5094 | else if (i.tm.opcode_modifier.isstring) |
| 5095 | { |
| 5096 | /* For the string instructions that allow a segment override |
| 5097 | on one of their operands, the default segment is ds. */ |
| 5098 | default_seg = &ds; |
| 5099 | } |
| 5100 | |
| 5101 | if (i.tm.base_opcode == 0x8d /* lea */ |
| 5102 | && i.seg[0] |
| 5103 | && !quiet_warnings) |
| 5104 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
| 5105 | |
| 5106 | /* If a segment was explicitly specified, and the specified segment |
| 5107 | is not the default, use an opcode prefix to select it. If we |
| 5108 | never figured out what the default segment is, then default_seg |
| 5109 | will be zero at this point, and the specified segment prefix will |
| 5110 | always be used. */ |
| 5111 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
| 5112 | { |
| 5113 | if (!add_prefix (i.seg[0]->seg_prefix)) |
| 5114 | return 0; |
| 5115 | } |
| 5116 | return 1; |
| 5117 | } |
| 5118 | |
| 5119 | static const seg_entry * |
| 5120 | build_modrm_byte (void) |
| 5121 | { |
| 5122 | const seg_entry *default_seg = 0; |
| 5123 | unsigned int source, dest; |
| 5124 | int vex_3_sources; |
| 5125 | |
| 5126 | /* The first operand of instructions with VEX prefix and 3 sources |
| 5127 | must be VEX_Imm4. */ |
| 5128 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
| 5129 | if (vex_3_sources) |
| 5130 | { |
| 5131 | unsigned int nds, reg_slot; |
| 5132 | expressionS *exp; |
| 5133 | |
| 5134 | if (i.tm.opcode_modifier.veximmext |
| 5135 | && i.tm.opcode_modifier.immext) |
| 5136 | { |
| 5137 | dest = i.operands - 2; |
| 5138 | gas_assert (dest == 3); |
| 5139 | } |
| 5140 | else |
| 5141 | dest = i.operands - 1; |
| 5142 | nds = dest - 1; |
| 5143 | |
| 5144 | /* There are 2 kinds of instructions: |
| 5145 | 1. 5 operands: 4 register operands or 3 register operands |
| 5146 | plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and |
| 5147 | VexW0 or VexW1. The destination must be either XMM or YMM |
| 5148 | register. |
| 5149 | 2. 4 operands: 4 register operands or 3 register operands |
| 5150 | plus 1 memory operand, VexXDS, and VexImmExt */ |
| 5151 | gas_assert ((i.reg_operands == 4 |
| 5152 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
| 5153 | && i.tm.opcode_modifier.vexvvvv == VEXXDS |
| 5154 | && (i.tm.opcode_modifier.veximmext |
| 5155 | || (i.imm_operands == 1 |
| 5156 | && i.types[0].bitfield.vec_imm4 |
| 5157 | && (i.tm.opcode_modifier.vexw == VEXW0 |
| 5158 | || i.tm.opcode_modifier.vexw == VEXW1) |
| 5159 | && (operand_type_equal (&i.tm.operand_types[dest], ®xmm) |
| 5160 | || operand_type_equal (&i.tm.operand_types[dest], ®ymm))))); |
| 5161 | |
| 5162 | if (i.imm_operands == 0) |
| 5163 | { |
| 5164 | /* When there is no immediate operand, generate an 8bit |
| 5165 | immediate operand to encode the first operand. */ |
| 5166 | exp = &im_expressions[i.imm_operands++]; |
| 5167 | i.op[i.operands].imms = exp; |
| 5168 | i.types[i.operands] = imm8; |
| 5169 | i.operands++; |
| 5170 | /* If VexW1 is set, the first operand is the source and |
| 5171 | the second operand is encoded in the immediate operand. */ |
| 5172 | if (i.tm.opcode_modifier.vexw == VEXW1) |
| 5173 | { |
| 5174 | source = 0; |
| 5175 | reg_slot = 1; |
| 5176 | } |
| 5177 | else |
| 5178 | { |
| 5179 | source = 1; |
| 5180 | reg_slot = 0; |
| 5181 | } |
| 5182 | |
| 5183 | /* FMA swaps REG and NDS. */ |
| 5184 | if (i.tm.cpu_flags.bitfield.cpufma) |
| 5185 | { |
| 5186 | unsigned int tmp; |
| 5187 | tmp = reg_slot; |
| 5188 | reg_slot = nds; |
| 5189 | nds = tmp; |
| 5190 | } |
| 5191 | |
| 5192 | gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], |
| 5193 | ®xmm) |
| 5194 | || operand_type_equal (&i.tm.operand_types[reg_slot], |
| 5195 | ®ymm)); |
| 5196 | exp->X_op = O_constant; |
| 5197 | exp->X_add_number |
| 5198 | = ((i.op[reg_slot].regs->reg_num |
| 5199 | + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0)) |
| 5200 | << 4); |
| 5201 | } |
| 5202 | else |
| 5203 | { |
| 5204 | unsigned int imm_slot; |
| 5205 | |
| 5206 | if (i.tm.opcode_modifier.vexw == VEXW0) |
| 5207 | { |
| 5208 | /* If VexW0 is set, the third operand is the source and |
| 5209 | the second operand is encoded in the immediate |
| 5210 | operand. */ |
| 5211 | source = 2; |
| 5212 | reg_slot = 1; |
| 5213 | } |
| 5214 | else |
| 5215 | { |
| 5216 | /* VexW1 is set, the second operand is the source and |
| 5217 | the third operand is encoded in the immediate |
| 5218 | operand. */ |
| 5219 | source = 1; |
| 5220 | reg_slot = 2; |
| 5221 | } |
| 5222 | |
| 5223 | if (i.tm.opcode_modifier.immext) |
| 5224 | { |
| 5225 | /* When ImmExt is set, the immdiate byte is the last |
| 5226 | operand. */ |
| 5227 | imm_slot = i.operands - 1; |
| 5228 | source--; |
| 5229 | reg_slot--; |
| 5230 | } |
| 5231 | else |
| 5232 | { |
| 5233 | imm_slot = 0; |
| 5234 | |
| 5235 | /* Turn on Imm8 so that output_imm will generate it. */ |
| 5236 | i.types[imm_slot].bitfield.imm8 = 1; |
| 5237 | } |
| 5238 | |
| 5239 | gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], |
| 5240 | ®xmm) |
| 5241 | || operand_type_equal (&i.tm.operand_types[reg_slot], |
| 5242 | ®ymm)); |
| 5243 | i.op[imm_slot].imms->X_add_number |
| 5244 | |= ((i.op[reg_slot].regs->reg_num |
| 5245 | + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0)) |
| 5246 | << 4); |
| 5247 | } |
| 5248 | |
| 5249 | gas_assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm) |
| 5250 | || operand_type_equal (&i.tm.operand_types[nds], |
| 5251 | ®ymm)); |
| 5252 | i.vex.register_specifier = i.op[nds].regs; |
| 5253 | } |
| 5254 | else |
| 5255 | source = dest = 0; |
| 5256 | |
| 5257 | /* i.reg_operands MUST be the number of real register operands; |
| 5258 | implicit registers do not count. If there are 3 register |
| 5259 | operands, it must be a instruction with VexNDS. For a |
| 5260 | instruction with VexNDD, the destination register is encoded |
| 5261 | in VEX prefix. If there are 4 register operands, it must be |
| 5262 | a instruction with VEX prefix and 3 sources. */ |
| 5263 | if (i.mem_operands == 0 |
| 5264 | && ((i.reg_operands == 2 |
| 5265 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
| 5266 | || (i.reg_operands == 3 |
| 5267 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
| 5268 | || (i.reg_operands == 4 && vex_3_sources))) |
| 5269 | { |
| 5270 | switch (i.operands) |
| 5271 | { |
| 5272 | case 2: |
| 5273 | source = 0; |
| 5274 | break; |
| 5275 | case 3: |
| 5276 | /* When there are 3 operands, one of them may be immediate, |
| 5277 | which may be the first or the last operand. Otherwise, |
| 5278 | the first operand must be shift count register (cl) or it |
| 5279 | is an instruction with VexNDS. */ |
| 5280 | gas_assert (i.imm_operands == 1 |
| 5281 | || (i.imm_operands == 0 |
| 5282 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
| 5283 | || i.types[0].bitfield.shiftcount))); |
| 5284 | if (operand_type_check (i.types[0], imm) |
| 5285 | || i.types[0].bitfield.shiftcount) |
| 5286 | source = 1; |
| 5287 | else |
| 5288 | source = 0; |
| 5289 | break; |
| 5290 | case 4: |
| 5291 | /* When there are 4 operands, the first two must be 8bit |
| 5292 | immediate operands. The source operand will be the 3rd |
| 5293 | one. |
| 5294 | |
| 5295 | For instructions with VexNDS, if the first operand |
| 5296 | an imm8, the source operand is the 2nd one. If the last |
| 5297 | operand is imm8, the source operand is the first one. */ |
| 5298 | gas_assert ((i.imm_operands == 2 |
| 5299 | && i.types[0].bitfield.imm8 |
| 5300 | && i.types[1].bitfield.imm8) |
| 5301 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
| 5302 | && i.imm_operands == 1 |
| 5303 | && (i.types[0].bitfield.imm8 |
| 5304 | || i.types[i.operands - 1].bitfield.imm8))); |
| 5305 | if (i.imm_operands == 2) |
| 5306 | source = 2; |
| 5307 | else |
| 5308 | { |
| 5309 | if (i.types[0].bitfield.imm8) |
| 5310 | source = 1; |
| 5311 | else |
| 5312 | source = 0; |
| 5313 | } |
| 5314 | break; |
| 5315 | case 5: |
| 5316 | break; |
| 5317 | default: |
| 5318 | abort (); |
| 5319 | } |
| 5320 | |
| 5321 | if (!vex_3_sources) |
| 5322 | { |
| 5323 | dest = source + 1; |
| 5324 | |
| 5325 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
| 5326 | { |
| 5327 | /* For instructions with VexNDS, the register-only |
| 5328 | source operand must be 32/64bit integer, XMM or |
| 5329 | YMM register. It is encoded in VEX prefix. We |
| 5330 | need to clear RegMem bit before calling |
| 5331 | operand_type_equal. */ |
| 5332 | |
| 5333 | i386_operand_type op; |
| 5334 | unsigned int vvvv; |
| 5335 | |
| 5336 | /* Check register-only source operand when two source |
| 5337 | operands are swapped. */ |
| 5338 | if (!i.tm.operand_types[source].bitfield.baseindex |
| 5339 | && i.tm.operand_types[dest].bitfield.baseindex) |
| 5340 | { |
| 5341 | vvvv = source; |
| 5342 | source = dest; |
| 5343 | } |
| 5344 | else |
| 5345 | vvvv = dest; |
| 5346 | |
| 5347 | op = i.tm.operand_types[vvvv]; |
| 5348 | op.bitfield.regmem = 0; |
| 5349 | if ((dest + 1) >= i.operands |
| 5350 | || (op.bitfield.reg32 != 1 |
| 5351 | && !op.bitfield.reg64 != 1 |
| 5352 | && !operand_type_equal (&op, ®xmm) |
| 5353 | && !operand_type_equal (&op, ®ymm))) |
| 5354 | abort (); |
| 5355 | i.vex.register_specifier = i.op[vvvv].regs; |
| 5356 | dest++; |
| 5357 | } |
| 5358 | } |
| 5359 | |
| 5360 | i.rm.mode = 3; |
| 5361 | /* One of the register operands will be encoded in the i.tm.reg |
| 5362 | field, the other in the combined i.tm.mode and i.tm.regmem |
| 5363 | fields. If no form of this instruction supports a memory |
| 5364 | destination operand, then we assume the source operand may |
| 5365 | sometimes be a memory operand and so we need to store the |
| 5366 | destination in the i.rm.reg field. */ |
| 5367 | if (!i.tm.operand_types[dest].bitfield.regmem |
| 5368 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) |
| 5369 | { |
| 5370 | i.rm.reg = i.op[dest].regs->reg_num; |
| 5371 | i.rm.regmem = i.op[source].regs->reg_num; |
| 5372 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) |
| 5373 | i.rex |= REX_R; |
| 5374 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
| 5375 | i.rex |= REX_B; |
| 5376 | } |
| 5377 | else |
| 5378 | { |
| 5379 | i.rm.reg = i.op[source].regs->reg_num; |
| 5380 | i.rm.regmem = i.op[dest].regs->reg_num; |
| 5381 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) |
| 5382 | i.rex |= REX_B; |
| 5383 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
| 5384 | i.rex |= REX_R; |
| 5385 | } |
| 5386 | if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B))) |
| 5387 | { |
| 5388 | if (!i.types[0].bitfield.control |
| 5389 | && !i.types[1].bitfield.control) |
| 5390 | abort (); |
| 5391 | i.rex &= ~(REX_R | REX_B); |
| 5392 | add_prefix (LOCK_PREFIX_OPCODE); |
| 5393 | } |
| 5394 | } |
| 5395 | else |
| 5396 | { /* If it's not 2 reg operands... */ |
| 5397 | unsigned int mem; |
| 5398 | |
| 5399 | if (i.mem_operands) |
| 5400 | { |
| 5401 | unsigned int fake_zero_displacement = 0; |
| 5402 | unsigned int op; |
| 5403 | |
| 5404 | for (op = 0; op < i.operands; op++) |
| 5405 | if (operand_type_check (i.types[op], anymem)) |
| 5406 | break; |
| 5407 | gas_assert (op < i.operands); |
| 5408 | |
| 5409 | default_seg = &ds; |
| 5410 | |
| 5411 | if (i.base_reg == 0) |
| 5412 | { |
| 5413 | i.rm.mode = 0; |
| 5414 | if (!i.disp_operands) |
| 5415 | fake_zero_displacement = 1; |
| 5416 | if (i.index_reg == 0) |
| 5417 | { |
| 5418 | /* Operand is just <disp> */ |
| 5419 | if (flag_code == CODE_64BIT) |
| 5420 | { |
| 5421 | /* 64bit mode overwrites the 32bit absolute |
| 5422 | addressing by RIP relative addressing and |
| 5423 | absolute addressing is encoded by one of the |
| 5424 | redundant SIB forms. */ |
| 5425 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
| 5426 | i.sib.base = NO_BASE_REGISTER; |
| 5427 | i.sib.index = NO_INDEX_REGISTER; |
| 5428 | i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) |
| 5429 | ? disp32s : disp32); |
| 5430 | } |
| 5431 | else if ((flag_code == CODE_16BIT) |
| 5432 | ^ (i.prefix[ADDR_PREFIX] != 0)) |
| 5433 | { |
| 5434 | i.rm.regmem = NO_BASE_REGISTER_16; |
| 5435 | i.types[op] = disp16; |
| 5436 | } |
| 5437 | else |
| 5438 | { |
| 5439 | i.rm.regmem = NO_BASE_REGISTER; |
| 5440 | i.types[op] = disp32; |
| 5441 | } |
| 5442 | } |
| 5443 | else /* !i.base_reg && i.index_reg */ |
| 5444 | { |
| 5445 | if (i.index_reg->reg_num == RegEiz |
| 5446 | || i.index_reg->reg_num == RegRiz) |
| 5447 | i.sib.index = NO_INDEX_REGISTER; |
| 5448 | else |
| 5449 | i.sib.index = i.index_reg->reg_num; |
| 5450 | i.sib.base = NO_BASE_REGISTER; |
| 5451 | i.sib.scale = i.log2_scale_factor; |
| 5452 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
| 5453 | i.types[op].bitfield.disp8 = 0; |
| 5454 | i.types[op].bitfield.disp16 = 0; |
| 5455 | i.types[op].bitfield.disp64 = 0; |
| 5456 | if (flag_code != CODE_64BIT) |
| 5457 | { |
| 5458 | /* Must be 32 bit */ |
| 5459 | i.types[op].bitfield.disp32 = 1; |
| 5460 | i.types[op].bitfield.disp32s = 0; |
| 5461 | } |
| 5462 | else |
| 5463 | { |
| 5464 | i.types[op].bitfield.disp32 = 0; |
| 5465 | i.types[op].bitfield.disp32s = 1; |
| 5466 | } |
| 5467 | if ((i.index_reg->reg_flags & RegRex) != 0) |
| 5468 | i.rex |= REX_X; |
| 5469 | } |
| 5470 | } |
| 5471 | /* RIP addressing for 64bit mode. */ |
| 5472 | else if (i.base_reg->reg_num == RegRip || |
| 5473 | i.base_reg->reg_num == RegEip) |
| 5474 | { |
| 5475 | i.rm.regmem = NO_BASE_REGISTER; |
| 5476 | i.types[op].bitfield.disp8 = 0; |
| 5477 | i.types[op].bitfield.disp16 = 0; |
| 5478 | i.types[op].bitfield.disp32 = 0; |
| 5479 | i.types[op].bitfield.disp32s = 1; |
| 5480 | i.types[op].bitfield.disp64 = 0; |
| 5481 | i.flags[op] |= Operand_PCrel; |
| 5482 | if (! i.disp_operands) |
| 5483 | fake_zero_displacement = 1; |
| 5484 | } |
| 5485 | else if (i.base_reg->reg_type.bitfield.reg16) |
| 5486 | { |
| 5487 | switch (i.base_reg->reg_num) |
| 5488 | { |
| 5489 | case 3: /* (%bx) */ |
| 5490 | if (i.index_reg == 0) |
| 5491 | i.rm.regmem = 7; |
| 5492 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ |
| 5493 | i.rm.regmem = i.index_reg->reg_num - 6; |
| 5494 | break; |
| 5495 | case 5: /* (%bp) */ |
| 5496 | default_seg = &ss; |
| 5497 | if (i.index_reg == 0) |
| 5498 | { |
| 5499 | i.rm.regmem = 6; |
| 5500 | if (operand_type_check (i.types[op], disp) == 0) |
| 5501 | { |
| 5502 | /* fake (%bp) into 0(%bp) */ |
| 5503 | i.types[op].bitfield.disp8 = 1; |
| 5504 | fake_zero_displacement = 1; |
| 5505 | } |
| 5506 | } |
| 5507 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ |
| 5508 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; |
| 5509 | break; |
| 5510 | default: /* (%si) -> 4 or (%di) -> 5 */ |
| 5511 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; |
| 5512 | } |
| 5513 | i.rm.mode = mode_from_disp_size (i.types[op]); |
| 5514 | } |
| 5515 | else /* i.base_reg and 32/64 bit mode */ |
| 5516 | { |
| 5517 | if (flag_code == CODE_64BIT |
| 5518 | && operand_type_check (i.types[op], disp)) |
| 5519 | { |
| 5520 | i386_operand_type temp; |
| 5521 | operand_type_set (&temp, 0); |
| 5522 | temp.bitfield.disp8 = i.types[op].bitfield.disp8; |
| 5523 | i.types[op] = temp; |
| 5524 | if (i.prefix[ADDR_PREFIX] == 0) |
| 5525 | i.types[op].bitfield.disp32s = 1; |
| 5526 | else |
| 5527 | i.types[op].bitfield.disp32 = 1; |
| 5528 | } |
| 5529 | |
| 5530 | i.rm.regmem = i.base_reg->reg_num; |
| 5531 | if ((i.base_reg->reg_flags & RegRex) != 0) |
| 5532 | i.rex |= REX_B; |
| 5533 | i.sib.base = i.base_reg->reg_num; |
| 5534 | /* x86-64 ignores REX prefix bit here to avoid decoder |
| 5535 | complications. */ |
| 5536 | if ((i.base_reg->reg_num & 7) == EBP_REG_NUM) |
| 5537 | { |
| 5538 | default_seg = &ss; |
| 5539 | if (i.disp_operands == 0) |
| 5540 | { |
| 5541 | fake_zero_displacement = 1; |
| 5542 | i.types[op].bitfield.disp8 = 1; |
| 5543 | } |
| 5544 | } |
| 5545 | else if (i.base_reg->reg_num == ESP_REG_NUM) |
| 5546 | { |
| 5547 | default_seg = &ss; |
| 5548 | } |
| 5549 | i.sib.scale = i.log2_scale_factor; |
| 5550 | if (i.index_reg == 0) |
| 5551 | { |
| 5552 | /* <disp>(%esp) becomes two byte modrm with no index |
| 5553 | register. We've already stored the code for esp |
| 5554 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. |
| 5555 | Any base register besides %esp will not use the |
| 5556 | extra modrm byte. */ |
| 5557 | i.sib.index = NO_INDEX_REGISTER; |
| 5558 | } |
| 5559 | else |
| 5560 | { |
| 5561 | if (i.index_reg->reg_num == RegEiz |
| 5562 | || i.index_reg->reg_num == RegRiz) |
| 5563 | i.sib.index = NO_INDEX_REGISTER; |
| 5564 | else |
| 5565 | i.sib.index = i.index_reg->reg_num; |
| 5566 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
| 5567 | if ((i.index_reg->reg_flags & RegRex) != 0) |
| 5568 | i.rex |= REX_X; |
| 5569 | } |
| 5570 | |
| 5571 | if (i.disp_operands |
| 5572 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
| 5573 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) |
| 5574 | i.rm.mode = 0; |
| 5575 | else |
| 5576 | i.rm.mode = mode_from_disp_size (i.types[op]); |
| 5577 | } |
| 5578 | |
| 5579 | if (fake_zero_displacement) |
| 5580 | { |
| 5581 | /* Fakes a zero displacement assuming that i.types[op] |
| 5582 | holds the correct displacement size. */ |
| 5583 | expressionS *exp; |
| 5584 | |
| 5585 | gas_assert (i.op[op].disps == 0); |
| 5586 | exp = &disp_expressions[i.disp_operands++]; |
| 5587 | i.op[op].disps = exp; |
| 5588 | exp->X_op = O_constant; |
| 5589 | exp->X_add_number = 0; |
| 5590 | exp->X_add_symbol = (symbolS *) 0; |
| 5591 | exp->X_op_symbol = (symbolS *) 0; |
| 5592 | } |
| 5593 | |
| 5594 | mem = op; |
| 5595 | } |
| 5596 | else |
| 5597 | mem = ~0; |
| 5598 | |
| 5599 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
| 5600 | { |
| 5601 | if (operand_type_check (i.types[0], imm)) |
| 5602 | i.vex.register_specifier = NULL; |
| 5603 | else |
| 5604 | { |
| 5605 | /* VEX.vvvv encodes one of the sources when the first |
| 5606 | operand is not an immediate. */ |
| 5607 | if (i.tm.opcode_modifier.vexw == VEXW0) |
| 5608 | i.vex.register_specifier = i.op[0].regs; |
| 5609 | else |
| 5610 | i.vex.register_specifier = i.op[1].regs; |
| 5611 | } |
| 5612 | |
| 5613 | /* Destination is a XMM register encoded in the ModRM.reg |
| 5614 | and VEX.R bit. */ |
| 5615 | i.rm.reg = i.op[2].regs->reg_num; |
| 5616 | if ((i.op[2].regs->reg_flags & RegRex) != 0) |
| 5617 | i.rex |= REX_R; |
| 5618 | |
| 5619 | /* ModRM.rm and VEX.B encodes the other source. */ |
| 5620 | if (!i.mem_operands) |
| 5621 | { |
| 5622 | i.rm.mode = 3; |
| 5623 | |
| 5624 | if (i.tm.opcode_modifier.vexw == VEXW0) |
| 5625 | i.rm.regmem = i.op[1].regs->reg_num; |
| 5626 | else |
| 5627 | i.rm.regmem = i.op[0].regs->reg_num; |
| 5628 | |
| 5629 | if ((i.op[1].regs->reg_flags & RegRex) != 0) |
| 5630 | i.rex |= REX_B; |
| 5631 | } |
| 5632 | } |
| 5633 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
| 5634 | { |
| 5635 | i.vex.register_specifier = i.op[2].regs; |
| 5636 | if (!i.mem_operands) |
| 5637 | { |
| 5638 | i.rm.mode = 3; |
| 5639 | i.rm.regmem = i.op[1].regs->reg_num; |
| 5640 | if ((i.op[1].regs->reg_flags & RegRex) != 0) |
| 5641 | i.rex |= REX_B; |
| 5642 | } |
| 5643 | } |
| 5644 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
| 5645 | (if any) based on i.tm.extension_opcode. Again, we must be |
| 5646 | careful to make sure that segment/control/debug/test/MMX |
| 5647 | registers are coded into the i.rm.reg field. */ |
| 5648 | else if (i.reg_operands) |
| 5649 | { |
| 5650 | unsigned int op; |
| 5651 | unsigned int vex_reg = ~0; |
| 5652 | |
| 5653 | for (op = 0; op < i.operands; op++) |
| 5654 | if (i.types[op].bitfield.reg8 |
| 5655 | || i.types[op].bitfield.reg16 |
| 5656 | || i.types[op].bitfield.reg32 |
| 5657 | || i.types[op].bitfield.reg64 |
| 5658 | || i.types[op].bitfield.regmmx |
| 5659 | || i.types[op].bitfield.regxmm |
| 5660 | || i.types[op].bitfield.regymm |
| 5661 | || i.types[op].bitfield.sreg2 |
| 5662 | || i.types[op].bitfield.sreg3 |
| 5663 | || i.types[op].bitfield.control |
| 5664 | || i.types[op].bitfield.debug |
| 5665 | || i.types[op].bitfield.test) |
| 5666 | break; |
| 5667 | |
| 5668 | if (vex_3_sources) |
| 5669 | op = dest; |
| 5670 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
| 5671 | { |
| 5672 | /* For instructions with VexNDS, the register-only |
| 5673 | source operand is encoded in VEX prefix. */ |
| 5674 | gas_assert (mem != (unsigned int) ~0); |
| 5675 | |
| 5676 | if (op > mem) |
| 5677 | { |
| 5678 | vex_reg = op++; |
| 5679 | gas_assert (op < i.operands); |
| 5680 | } |
| 5681 | else |
| 5682 | { |
| 5683 | /* Check register-only source operand when two source |
| 5684 | operands are swapped. */ |
| 5685 | if (!i.tm.operand_types[op].bitfield.baseindex |
| 5686 | && i.tm.operand_types[op + 1].bitfield.baseindex) |
| 5687 | { |
| 5688 | vex_reg = op; |
| 5689 | op += 2; |
| 5690 | gas_assert (mem == (vex_reg + 1) |
| 5691 | && op < i.operands); |
| 5692 | } |
| 5693 | else |
| 5694 | { |
| 5695 | vex_reg = op + 1; |
| 5696 | gas_assert (vex_reg < i.operands); |
| 5697 | } |
| 5698 | } |
| 5699 | } |
| 5700 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
| 5701 | { |
| 5702 | /* For instructions with VexNDD, the register destination |
| 5703 | is encoded in VEX prefix. */ |
| 5704 | if (i.mem_operands == 0) |
| 5705 | { |
| 5706 | /* There is no memory operand. */ |
| 5707 | gas_assert ((op + 2) == i.operands); |
| 5708 | vex_reg = op + 1; |
| 5709 | } |
| 5710 | else |
| 5711 | { |
| 5712 | /* There are only 2 operands. */ |
| 5713 | gas_assert (op < 2 && i.operands == 2); |
| 5714 | vex_reg = 1; |
| 5715 | } |
| 5716 | } |
| 5717 | else |
| 5718 | gas_assert (op < i.operands); |
| 5719 | |
| 5720 | if (vex_reg != (unsigned int) ~0) |
| 5721 | { |
| 5722 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
| 5723 | |
| 5724 | if (type->bitfield.reg32 != 1 |
| 5725 | && type->bitfield.reg64 != 1 |
| 5726 | && !operand_type_equal (type, ®xmm) |
| 5727 | && !operand_type_equal (type, ®ymm)) |
| 5728 | abort (); |
| 5729 | |
| 5730 | i.vex.register_specifier = i.op[vex_reg].regs; |
| 5731 | } |
| 5732 | |
| 5733 | /* Don't set OP operand twice. */ |
| 5734 | if (vex_reg != op) |
| 5735 | { |
| 5736 | /* If there is an extension opcode to put here, the |
| 5737 | register number must be put into the regmem field. */ |
| 5738 | if (i.tm.extension_opcode != None) |
| 5739 | { |
| 5740 | i.rm.regmem = i.op[op].regs->reg_num; |
| 5741 | if ((i.op[op].regs->reg_flags & RegRex) != 0) |
| 5742 | i.rex |= REX_B; |
| 5743 | } |
| 5744 | else |
| 5745 | { |
| 5746 | i.rm.reg = i.op[op].regs->reg_num; |
| 5747 | if ((i.op[op].regs->reg_flags & RegRex) != 0) |
| 5748 | i.rex |= REX_R; |
| 5749 | } |
| 5750 | } |
| 5751 | |
| 5752 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
| 5753 | must set it to 3 to indicate this is a register operand |
| 5754 | in the regmem field. */ |
| 5755 | if (!i.mem_operands) |
| 5756 | i.rm.mode = 3; |
| 5757 | } |
| 5758 | |
| 5759 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
| 5760 | if (i.tm.extension_opcode != None) |
| 5761 | i.rm.reg = i.tm.extension_opcode; |
| 5762 | } |
| 5763 | return default_seg; |
| 5764 | } |
| 5765 | |
| 5766 | static void |
| 5767 | output_branch (void) |
| 5768 | { |
| 5769 | char *p; |
| 5770 | int size; |
| 5771 | int code16; |
| 5772 | int prefix; |
| 5773 | relax_substateT subtype; |
| 5774 | symbolS *sym; |
| 5775 | offsetT off; |
| 5776 | |
| 5777 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
| 5778 | size = i.disp32_encoding ? BIG : SMALL; |
| 5779 | |
| 5780 | prefix = 0; |
| 5781 | if (i.prefix[DATA_PREFIX] != 0) |
| 5782 | { |
| 5783 | prefix = 1; |
| 5784 | i.prefixes -= 1; |
| 5785 | code16 ^= CODE16; |
| 5786 | } |
| 5787 | /* Pentium4 branch hints. */ |
| 5788 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ |
| 5789 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) |
| 5790 | { |
| 5791 | prefix++; |
| 5792 | i.prefixes--; |
| 5793 | } |
| 5794 | if (i.prefix[REX_PREFIX] != 0) |
| 5795 | { |
| 5796 | prefix++; |
| 5797 | i.prefixes--; |
| 5798 | } |
| 5799 | |
| 5800 | if (i.prefixes != 0 && !intel_syntax) |
| 5801 | as_warn (_("skipping prefixes on this instruction")); |
| 5802 | |
| 5803 | /* It's always a symbol; End frag & setup for relax. |
| 5804 | Make sure there is enough room in this frag for the largest |
| 5805 | instruction we may generate in md_convert_frag. This is 2 |
| 5806 | bytes for the opcode and room for the prefix and largest |
| 5807 | displacement. */ |
| 5808 | frag_grow (prefix + 2 + 4); |
| 5809 | /* Prefix and 1 opcode byte go in fr_fix. */ |
| 5810 | p = frag_more (prefix + 1); |
| 5811 | if (i.prefix[DATA_PREFIX] != 0) |
| 5812 | *p++ = DATA_PREFIX_OPCODE; |
| 5813 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE |
| 5814 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) |
| 5815 | *p++ = i.prefix[SEG_PREFIX]; |
| 5816 | if (i.prefix[REX_PREFIX] != 0) |
| 5817 | *p++ = i.prefix[REX_PREFIX]; |
| 5818 | *p = i.tm.base_opcode; |
| 5819 | |
| 5820 | if ((unsigned char) *p == JUMP_PC_RELATIVE) |
| 5821 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
| 5822 | else if (cpu_arch_flags.bitfield.cpui386) |
| 5823 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
| 5824 | else |
| 5825 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
| 5826 | subtype |= code16; |
| 5827 | |
| 5828 | sym = i.op[0].disps->X_add_symbol; |
| 5829 | off = i.op[0].disps->X_add_number; |
| 5830 | |
| 5831 | if (i.op[0].disps->X_op != O_constant |
| 5832 | && i.op[0].disps->X_op != O_symbol) |
| 5833 | { |
| 5834 | /* Handle complex expressions. */ |
| 5835 | sym = make_expr_symbol (i.op[0].disps); |
| 5836 | off = 0; |
| 5837 | } |
| 5838 | |
| 5839 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
| 5840 | Pass reloc in fr_var. */ |
| 5841 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
| 5842 | } |
| 5843 | |
| 5844 | static void |
| 5845 | output_jump (void) |
| 5846 | { |
| 5847 | char *p; |
| 5848 | int size; |
| 5849 | fixS *fixP; |
| 5850 | |
| 5851 | if (i.tm.opcode_modifier.jumpbyte) |
| 5852 | { |
| 5853 | /* This is a loop or jecxz type instruction. */ |
| 5854 | size = 1; |
| 5855 | if (i.prefix[ADDR_PREFIX] != 0) |
| 5856 | { |
| 5857 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); |
| 5858 | i.prefixes -= 1; |
| 5859 | } |
| 5860 | /* Pentium4 branch hints. */ |
| 5861 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ |
| 5862 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) |
| 5863 | { |
| 5864 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); |
| 5865 | i.prefixes--; |
| 5866 | } |
| 5867 | } |
| 5868 | else |
| 5869 | { |
| 5870 | int code16; |
| 5871 | |
| 5872 | code16 = 0; |
| 5873 | if (flag_code == CODE_16BIT) |
| 5874 | code16 = CODE16; |
| 5875 | |
| 5876 | if (i.prefix[DATA_PREFIX] != 0) |
| 5877 | { |
| 5878 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); |
| 5879 | i.prefixes -= 1; |
| 5880 | code16 ^= CODE16; |
| 5881 | } |
| 5882 | |
| 5883 | size = 4; |
| 5884 | if (code16) |
| 5885 | size = 2; |
| 5886 | } |
| 5887 | |
| 5888 | if (i.prefix[REX_PREFIX] != 0) |
| 5889 | { |
| 5890 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); |
| 5891 | i.prefixes -= 1; |
| 5892 | } |
| 5893 | |
| 5894 | if (i.prefixes != 0 && !intel_syntax) |
| 5895 | as_warn (_("skipping prefixes on this instruction")); |
| 5896 | |
| 5897 | p = frag_more (1 + size); |
| 5898 | *p++ = i.tm.base_opcode; |
| 5899 | |
| 5900 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
| 5901 | i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); |
| 5902 | |
| 5903 | /* All jumps handled here are signed, but don't use a signed limit |
| 5904 | check for 32 and 16 bit jumps as we want to allow wrap around at |
| 5905 | 4G and 64k respectively. */ |
| 5906 | if (size == 1) |
| 5907 | fixP->fx_signed = 1; |
| 5908 | } |
| 5909 | |
| 5910 | static void |
| 5911 | output_interseg_jump (void) |
| 5912 | { |
| 5913 | char *p; |
| 5914 | int size; |
| 5915 | int prefix; |
| 5916 | int code16; |
| 5917 | |
| 5918 | code16 = 0; |
| 5919 | if (flag_code == CODE_16BIT) |
| 5920 | code16 = CODE16; |
| 5921 | |
| 5922 | prefix = 0; |
| 5923 | if (i.prefix[DATA_PREFIX] != 0) |
| 5924 | { |
| 5925 | prefix = 1; |
| 5926 | i.prefixes -= 1; |
| 5927 | code16 ^= CODE16; |
| 5928 | } |
| 5929 | if (i.prefix[REX_PREFIX] != 0) |
| 5930 | { |
| 5931 | prefix++; |
| 5932 | i.prefixes -= 1; |
| 5933 | } |
| 5934 | |
| 5935 | size = 4; |
| 5936 | if (code16) |
| 5937 | size = 2; |
| 5938 | |
| 5939 | if (i.prefixes != 0 && !intel_syntax) |
| 5940 | as_warn (_("skipping prefixes on this instruction")); |
| 5941 | |
| 5942 | /* 1 opcode; 2 segment; offset */ |
| 5943 | p = frag_more (prefix + 1 + 2 + size); |
| 5944 | |
| 5945 | if (i.prefix[DATA_PREFIX] != 0) |
| 5946 | *p++ = DATA_PREFIX_OPCODE; |
| 5947 | |
| 5948 | if (i.prefix[REX_PREFIX] != 0) |
| 5949 | *p++ = i.prefix[REX_PREFIX]; |
| 5950 | |
| 5951 | *p++ = i.tm.base_opcode; |
| 5952 | if (i.op[1].imms->X_op == O_constant) |
| 5953 | { |
| 5954 | offsetT n = i.op[1].imms->X_add_number; |
| 5955 | |
| 5956 | if (size == 2 |
| 5957 | && !fits_in_unsigned_word (n) |
| 5958 | && !fits_in_signed_word (n)) |
| 5959 | { |
| 5960 | as_bad (_("16-bit jump out of range")); |
| 5961 | return; |
| 5962 | } |
| 5963 | md_number_to_chars (p, n, size); |
| 5964 | } |
| 5965 | else |
| 5966 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
| 5967 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
| 5968 | if (i.op[0].imms->X_op != O_constant) |
| 5969 | as_bad (_("can't handle non absolute segment in `%s'"), |
| 5970 | i.tm.name); |
| 5971 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); |
| 5972 | } |
| 5973 | |
| 5974 | static void |
| 5975 | output_insn (void) |
| 5976 | { |
| 5977 | fragS *insn_start_frag; |
| 5978 | offsetT insn_start_off; |
| 5979 | |
| 5980 | /* Tie dwarf2 debug info to the address at the start of the insn. |
| 5981 | We can't do this after the insn has been output as the current |
| 5982 | frag may have been closed off. eg. by frag_var. */ |
| 5983 | dwarf2_emit_insn (0); |
| 5984 | |
| 5985 | insn_start_frag = frag_now; |
| 5986 | insn_start_off = frag_now_fix (); |
| 5987 | |
| 5988 | /* Output jumps. */ |
| 5989 | if (i.tm.opcode_modifier.jump) |
| 5990 | output_branch (); |
| 5991 | else if (i.tm.opcode_modifier.jumpbyte |
| 5992 | || i.tm.opcode_modifier.jumpdword) |
| 5993 | output_jump (); |
| 5994 | else if (i.tm.opcode_modifier.jumpintersegment) |
| 5995 | output_interseg_jump (); |
| 5996 | else |
| 5997 | { |
| 5998 | /* Output normal instructions here. */ |
| 5999 | char *p; |
| 6000 | unsigned char *q; |
| 6001 | unsigned int j; |
| 6002 | unsigned int prefix; |
| 6003 | |
| 6004 | /* Since the VEX prefix contains the implicit prefix, we don't |
| 6005 | need the explicit prefix. */ |
| 6006 | if (!i.tm.opcode_modifier.vex) |
| 6007 | { |
| 6008 | switch (i.tm.opcode_length) |
| 6009 | { |
| 6010 | case 3: |
| 6011 | if (i.tm.base_opcode & 0xff000000) |
| 6012 | { |
| 6013 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
| 6014 | goto check_prefix; |
| 6015 | } |
| 6016 | break; |
| 6017 | case 2: |
| 6018 | if ((i.tm.base_opcode & 0xff0000) != 0) |
| 6019 | { |
| 6020 | prefix = (i.tm.base_opcode >> 16) & 0xff; |
| 6021 | if (i.tm.cpu_flags.bitfield.cpupadlock) |
| 6022 | { |
| 6023 | check_prefix: |
| 6024 | if (prefix != REPE_PREFIX_OPCODE |
| 6025 | || (i.prefix[REP_PREFIX] |
| 6026 | != REPE_PREFIX_OPCODE)) |
| 6027 | add_prefix (prefix); |
| 6028 | } |
| 6029 | else |
| 6030 | add_prefix (prefix); |
| 6031 | } |
| 6032 | break; |
| 6033 | case 1: |
| 6034 | break; |
| 6035 | default: |
| 6036 | abort (); |
| 6037 | } |
| 6038 | |
| 6039 | /* The prefix bytes. */ |
| 6040 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) |
| 6041 | if (*q) |
| 6042 | FRAG_APPEND_1_CHAR (*q); |
| 6043 | } |
| 6044 | |
| 6045 | if (i.tm.opcode_modifier.vex) |
| 6046 | { |
| 6047 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) |
| 6048 | if (*q) |
| 6049 | switch (j) |
| 6050 | { |
| 6051 | case REX_PREFIX: |
| 6052 | /* REX byte is encoded in VEX prefix. */ |
| 6053 | break; |
| 6054 | case SEG_PREFIX: |
| 6055 | case ADDR_PREFIX: |
| 6056 | FRAG_APPEND_1_CHAR (*q); |
| 6057 | break; |
| 6058 | default: |
| 6059 | /* There should be no other prefixes for instructions |
| 6060 | with VEX prefix. */ |
| 6061 | abort (); |
| 6062 | } |
| 6063 | |
| 6064 | /* Now the VEX prefix. */ |
| 6065 | p = frag_more (i.vex.length); |
| 6066 | for (j = 0; j < i.vex.length; j++) |
| 6067 | p[j] = i.vex.bytes[j]; |
| 6068 | } |
| 6069 | |
| 6070 | /* Now the opcode; be careful about word order here! */ |
| 6071 | if (i.tm.opcode_length == 1) |
| 6072 | { |
| 6073 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); |
| 6074 | } |
| 6075 | else |
| 6076 | { |
| 6077 | switch (i.tm.opcode_length) |
| 6078 | { |
| 6079 | case 3: |
| 6080 | p = frag_more (3); |
| 6081 | *p++ = (i.tm.base_opcode >> 16) & 0xff; |
| 6082 | break; |
| 6083 | case 2: |
| 6084 | p = frag_more (2); |
| 6085 | break; |
| 6086 | default: |
| 6087 | abort (); |
| 6088 | break; |
| 6089 | } |
| 6090 | |
| 6091 | /* Put out high byte first: can't use md_number_to_chars! */ |
| 6092 | *p++ = (i.tm.base_opcode >> 8) & 0xff; |
| 6093 | *p = i.tm.base_opcode & 0xff; |
| 6094 | } |
| 6095 | |
| 6096 | /* Now the modrm byte and sib byte (if present). */ |
| 6097 | if (i.tm.opcode_modifier.modrm) |
| 6098 | { |
| 6099 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
| 6100 | | i.rm.reg << 3 |
| 6101 | | i.rm.mode << 6)); |
| 6102 | /* If i.rm.regmem == ESP (4) |
| 6103 | && i.rm.mode != (Register mode) |
| 6104 | && not 16 bit |
| 6105 | ==> need second modrm byte. */ |
| 6106 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING |
| 6107 | && i.rm.mode != 3 |
| 6108 | && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16)) |
| 6109 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
| 6110 | | i.sib.index << 3 |
| 6111 | | i.sib.scale << 6)); |
| 6112 | } |
| 6113 | |
| 6114 | if (i.disp_operands) |
| 6115 | output_disp (insn_start_frag, insn_start_off); |
| 6116 | |
| 6117 | if (i.imm_operands) |
| 6118 | output_imm (insn_start_frag, insn_start_off); |
| 6119 | } |
| 6120 | |
| 6121 | #ifdef DEBUG386 |
| 6122 | if (flag_debug) |
| 6123 | { |
| 6124 | pi ("" /*line*/, &i); |
| 6125 | } |
| 6126 | #endif /* DEBUG386 */ |
| 6127 | } |
| 6128 | |
| 6129 | /* Return the size of the displacement operand N. */ |
| 6130 | |
| 6131 | static int |
| 6132 | disp_size (unsigned int n) |
| 6133 | { |
| 6134 | int size = 4; |
| 6135 | if (i.types[n].bitfield.disp64) |
| 6136 | size = 8; |
| 6137 | else if (i.types[n].bitfield.disp8) |
| 6138 | size = 1; |
| 6139 | else if (i.types[n].bitfield.disp16) |
| 6140 | size = 2; |
| 6141 | return size; |
| 6142 | } |
| 6143 | |
| 6144 | /* Return the size of the immediate operand N. */ |
| 6145 | |
| 6146 | static int |
| 6147 | imm_size (unsigned int n) |
| 6148 | { |
| 6149 | int size = 4; |
| 6150 | if (i.types[n].bitfield.imm64) |
| 6151 | size = 8; |
| 6152 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) |
| 6153 | size = 1; |
| 6154 | else if (i.types[n].bitfield.imm16) |
| 6155 | size = 2; |
| 6156 | return size; |
| 6157 | } |
| 6158 | |
| 6159 | static void |
| 6160 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
| 6161 | { |
| 6162 | char *p; |
| 6163 | unsigned int n; |
| 6164 | |
| 6165 | for (n = 0; n < i.operands; n++) |
| 6166 | { |
| 6167 | if (operand_type_check (i.types[n], disp)) |
| 6168 | { |
| 6169 | if (i.op[n].disps->X_op == O_constant) |
| 6170 | { |
| 6171 | int size = disp_size (n); |
| 6172 | offsetT val; |
| 6173 | |
| 6174 | val = offset_in_range (i.op[n].disps->X_add_number, |
| 6175 | size); |
| 6176 | p = frag_more (size); |
| 6177 | md_number_to_chars (p, val, size); |
| 6178 | } |
| 6179 | else |
| 6180 | { |
| 6181 | enum bfd_reloc_code_real reloc_type; |
| 6182 | int size = disp_size (n); |
| 6183 | int sign = i.types[n].bitfield.disp32s; |
| 6184 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
| 6185 | |
| 6186 | /* We can't have 8 bit displacement here. */ |
| 6187 | gas_assert (!i.types[n].bitfield.disp8); |
| 6188 | |
| 6189 | /* The PC relative address is computed relative |
| 6190 | to the instruction boundary, so in case immediate |
| 6191 | fields follows, we need to adjust the value. */ |
| 6192 | if (pcrel && i.imm_operands) |
| 6193 | { |
| 6194 | unsigned int n1; |
| 6195 | int sz = 0; |
| 6196 | |
| 6197 | for (n1 = 0; n1 < i.operands; n1++) |
| 6198 | if (operand_type_check (i.types[n1], imm)) |
| 6199 | { |
| 6200 | /* Only one immediate is allowed for PC |
| 6201 | relative address. */ |
| 6202 | gas_assert (sz == 0); |
| 6203 | sz = imm_size (n1); |
| 6204 | i.op[n].disps->X_add_number -= sz; |
| 6205 | } |
| 6206 | /* We should find the immediate. */ |
| 6207 | gas_assert (sz != 0); |
| 6208 | } |
| 6209 | |
| 6210 | p = frag_more (size); |
| 6211 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
| 6212 | if (GOT_symbol |
| 6213 | && GOT_symbol == i.op[n].disps->X_add_symbol |
| 6214 | && (((reloc_type == BFD_RELOC_32 |
| 6215 | || reloc_type == BFD_RELOC_X86_64_32S |
| 6216 | || (reloc_type == BFD_RELOC_64 |
| 6217 | && object_64bit)) |
| 6218 | && (i.op[n].disps->X_op == O_symbol |
| 6219 | || (i.op[n].disps->X_op == O_add |
| 6220 | && ((symbol_get_value_expression |
| 6221 | (i.op[n].disps->X_op_symbol)->X_op) |
| 6222 | == O_subtract)))) |
| 6223 | || reloc_type == BFD_RELOC_32_PCREL)) |
| 6224 | { |
| 6225 | offsetT add; |
| 6226 | |
| 6227 | if (insn_start_frag == frag_now) |
| 6228 | add = (p - frag_now->fr_literal) - insn_start_off; |
| 6229 | else |
| 6230 | { |
| 6231 | fragS *fr; |
| 6232 | |
| 6233 | add = insn_start_frag->fr_fix - insn_start_off; |
| 6234 | for (fr = insn_start_frag->fr_next; |
| 6235 | fr && fr != frag_now; fr = fr->fr_next) |
| 6236 | add += fr->fr_fix; |
| 6237 | add += p - frag_now->fr_literal; |
| 6238 | } |
| 6239 | |
| 6240 | if (!object_64bit) |
| 6241 | { |
| 6242 | reloc_type = BFD_RELOC_386_GOTPC; |
| 6243 | i.op[n].imms->X_add_number += add; |
| 6244 | } |
| 6245 | else if (reloc_type == BFD_RELOC_64) |
| 6246 | reloc_type = BFD_RELOC_X86_64_GOTPC64; |
| 6247 | else |
| 6248 | /* Don't do the adjustment for x86-64, as there |
| 6249 | the pcrel addressing is relative to the _next_ |
| 6250 | insn, and that is taken care of in other code. */ |
| 6251 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
| 6252 | } |
| 6253 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
| 6254 | i.op[n].disps, pcrel, reloc_type); |
| 6255 | } |
| 6256 | } |
| 6257 | } |
| 6258 | } |
| 6259 | |
| 6260 | static void |
| 6261 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
| 6262 | { |
| 6263 | char *p; |
| 6264 | unsigned int n; |
| 6265 | |
| 6266 | for (n = 0; n < i.operands; n++) |
| 6267 | { |
| 6268 | if (operand_type_check (i.types[n], imm)) |
| 6269 | { |
| 6270 | if (i.op[n].imms->X_op == O_constant) |
| 6271 | { |
| 6272 | int size = imm_size (n); |
| 6273 | offsetT val; |
| 6274 | |
| 6275 | val = offset_in_range (i.op[n].imms->X_add_number, |
| 6276 | size); |
| 6277 | p = frag_more (size); |
| 6278 | md_number_to_chars (p, val, size); |
| 6279 | } |
| 6280 | else |
| 6281 | { |
| 6282 | /* Not absolute_section. |
| 6283 | Need a 32-bit fixup (don't support 8bit |
| 6284 | non-absolute imms). Try to support other |
| 6285 | sizes ... */ |
| 6286 | enum bfd_reloc_code_real reloc_type; |
| 6287 | int size = imm_size (n); |
| 6288 | int sign; |
| 6289 | |
| 6290 | if (i.types[n].bitfield.imm32s |
| 6291 | && (i.suffix == QWORD_MNEM_SUFFIX |
| 6292 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
| 6293 | sign = 1; |
| 6294 | else |
| 6295 | sign = 0; |
| 6296 | |
| 6297 | p = frag_more (size); |
| 6298 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
| 6299 | |
| 6300 | /* This is tough to explain. We end up with this one if we |
| 6301 | * have operands that look like |
| 6302 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to |
| 6303 | * obtain the absolute address of the GOT, and it is strongly |
| 6304 | * preferable from a performance point of view to avoid using |
| 6305 | * a runtime relocation for this. The actual sequence of |
| 6306 | * instructions often look something like: |
| 6307 | * |
| 6308 | * call .L66 |
| 6309 | * .L66: |
| 6310 | * popl %ebx |
| 6311 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx |
| 6312 | * |
| 6313 | * The call and pop essentially return the absolute address |
| 6314 | * of the label .L66 and store it in %ebx. The linker itself |
| 6315 | * will ultimately change the first operand of the addl so |
| 6316 | * that %ebx points to the GOT, but to keep things simple, the |
| 6317 | * .o file must have this operand set so that it generates not |
| 6318 | * the absolute address of .L66, but the absolute address of |
| 6319 | * itself. This allows the linker itself simply treat a GOTPC |
| 6320 | * relocation as asking for a pcrel offset to the GOT to be |
| 6321 | * added in, and the addend of the relocation is stored in the |
| 6322 | * operand field for the instruction itself. |
| 6323 | * |
| 6324 | * Our job here is to fix the operand so that it would add |
| 6325 | * the correct offset so that %ebx would point to itself. The |
| 6326 | * thing that is tricky is that .-.L66 will point to the |
| 6327 | * beginning of the instruction, so we need to further modify |
| 6328 | * the operand so that it will point to itself. There are |
| 6329 | * other cases where you have something like: |
| 6330 | * |
| 6331 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] |
| 6332 | * |
| 6333 | * and here no correction would be required. Internally in |
| 6334 | * the assembler we treat operands of this form as not being |
| 6335 | * pcrel since the '.' is explicitly mentioned, and I wonder |
| 6336 | * whether it would simplify matters to do it this way. Who |
| 6337 | * knows. In earlier versions of the PIC patches, the |
| 6338 | * pcrel_adjust field was used to store the correction, but |
| 6339 | * since the expression is not pcrel, I felt it would be |
| 6340 | * confusing to do it this way. */ |
| 6341 | |
| 6342 | if ((reloc_type == BFD_RELOC_32 |
| 6343 | || reloc_type == BFD_RELOC_X86_64_32S |
| 6344 | || reloc_type == BFD_RELOC_64) |
| 6345 | && GOT_symbol |
| 6346 | && GOT_symbol == i.op[n].imms->X_add_symbol |
| 6347 | && (i.op[n].imms->X_op == O_symbol |
| 6348 | || (i.op[n].imms->X_op == O_add |
| 6349 | && ((symbol_get_value_expression |
| 6350 | (i.op[n].imms->X_op_symbol)->X_op) |
| 6351 | == O_subtract)))) |
| 6352 | { |
| 6353 | offsetT add; |
| 6354 | |
| 6355 | if (insn_start_frag == frag_now) |
| 6356 | add = (p - frag_now->fr_literal) - insn_start_off; |
| 6357 | else |
| 6358 | { |
| 6359 | fragS *fr; |
| 6360 | |
| 6361 | add = insn_start_frag->fr_fix - insn_start_off; |
| 6362 | for (fr = insn_start_frag->fr_next; |
| 6363 | fr && fr != frag_now; fr = fr->fr_next) |
| 6364 | add += fr->fr_fix; |
| 6365 | add += p - frag_now->fr_literal; |
| 6366 | } |
| 6367 | |
| 6368 | if (!object_64bit) |
| 6369 | reloc_type = BFD_RELOC_386_GOTPC; |
| 6370 | else if (size == 4) |
| 6371 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
| 6372 | else if (size == 8) |
| 6373 | reloc_type = BFD_RELOC_X86_64_GOTPC64; |
| 6374 | i.op[n].imms->X_add_number += add; |
| 6375 | } |
| 6376 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
| 6377 | i.op[n].imms, 0, reloc_type); |
| 6378 | } |
| 6379 | } |
| 6380 | } |
| 6381 | } |
| 6382 | \f |
| 6383 | /* x86_cons_fix_new is called via the expression parsing code when a |
| 6384 | reloc is needed. We use this hook to get the correct .got reloc. */ |
| 6385 | static enum bfd_reloc_code_real got_reloc = NO_RELOC; |
| 6386 | static int cons_sign = -1; |
| 6387 | |
| 6388 | void |
| 6389 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
| 6390 | expressionS *exp) |
| 6391 | { |
| 6392 | enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc); |
| 6393 | |
| 6394 | got_reloc = NO_RELOC; |
| 6395 | |
| 6396 | #ifdef TE_PE |
| 6397 | if (exp->X_op == O_secrel) |
| 6398 | { |
| 6399 | exp->X_op = O_symbol; |
| 6400 | r = BFD_RELOC_32_SECREL; |
| 6401 | } |
| 6402 | #endif |
| 6403 | |
| 6404 | fix_new_exp (frag, off, len, exp, 0, r); |
| 6405 | } |
| 6406 | |
| 6407 | #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT) |
| 6408 | # define lex_got(reloc, adjust, types) NULL |
| 6409 | #else |
| 6410 | /* Parse operands of the form |
| 6411 | <symbol>@GOTOFF+<nnn> |
| 6412 | and similar .plt or .got references. |
| 6413 | |
| 6414 | If we find one, set up the correct relocation in RELOC and copy the |
| 6415 | input string, minus the `@GOTOFF' into a malloc'd buffer for |
| 6416 | parsing by the calling routine. Return this buffer, and if ADJUST |
| 6417 | is non-null set it to the length of the string we removed from the |
| 6418 | input line. Otherwise return NULL. */ |
| 6419 | static char * |
| 6420 | lex_got (enum bfd_reloc_code_real *rel, |
| 6421 | int *adjust, |
| 6422 | i386_operand_type *types) |
| 6423 | { |
| 6424 | /* Some of the relocations depend on the size of what field is to |
| 6425 | be relocated. But in our callers i386_immediate and i386_displacement |
| 6426 | we don't yet know the operand size (this will be set by insn |
| 6427 | matching). Hence we record the word32 relocation here, |
| 6428 | and adjust the reloc according to the real size in reloc(). */ |
| 6429 | static const struct { |
| 6430 | const char *str; |
| 6431 | int len; |
| 6432 | const enum bfd_reloc_code_real rel[2]; |
| 6433 | const i386_operand_type types64; |
| 6434 | } gotrel[] = { |
| 6435 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
| 6436 | BFD_RELOC_X86_64_PLTOFF64 }, |
| 6437 | OPERAND_TYPE_IMM64 }, |
| 6438 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
| 6439 | BFD_RELOC_X86_64_PLT32 }, |
| 6440 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
| 6441 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
| 6442 | BFD_RELOC_X86_64_GOTPLT64 }, |
| 6443 | OPERAND_TYPE_IMM64_DISP64 }, |
| 6444 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
| 6445 | BFD_RELOC_X86_64_GOTOFF64 }, |
| 6446 | OPERAND_TYPE_IMM64_DISP64 }, |
| 6447 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
| 6448 | BFD_RELOC_X86_64_GOTPCREL }, |
| 6449 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
| 6450 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
| 6451 | BFD_RELOC_X86_64_TLSGD }, |
| 6452 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
| 6453 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
| 6454 | _dummy_first_bfd_reloc_code_real }, |
| 6455 | OPERAND_TYPE_NONE }, |
| 6456 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
| 6457 | BFD_RELOC_X86_64_TLSLD }, |
| 6458 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
| 6459 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
| 6460 | BFD_RELOC_X86_64_GOTTPOFF }, |
| 6461 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
| 6462 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
| 6463 | BFD_RELOC_X86_64_TPOFF32 }, |
| 6464 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
| 6465 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
| 6466 | _dummy_first_bfd_reloc_code_real }, |
| 6467 | OPERAND_TYPE_NONE }, |
| 6468 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
| 6469 | BFD_RELOC_X86_64_DTPOFF32 }, |
| 6470 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
| 6471 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
| 6472 | _dummy_first_bfd_reloc_code_real }, |
| 6473 | OPERAND_TYPE_NONE }, |
| 6474 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
| 6475 | _dummy_first_bfd_reloc_code_real }, |
| 6476 | OPERAND_TYPE_NONE }, |
| 6477 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
| 6478 | BFD_RELOC_X86_64_GOT32 }, |
| 6479 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
| 6480 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
| 6481 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, |
| 6482 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
| 6483 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
| 6484 | BFD_RELOC_X86_64_TLSDESC_CALL }, |
| 6485 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
| 6486 | }; |
| 6487 | char *cp; |
| 6488 | unsigned int j; |
| 6489 | |
| 6490 | if (!IS_ELF) |
| 6491 | return NULL; |
| 6492 | |
| 6493 | for (cp = input_line_pointer; *cp != '@'; cp++) |
| 6494 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
| 6495 | return NULL; |
| 6496 | |
| 6497 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
| 6498 | { |
| 6499 | int len = gotrel[j].len; |
| 6500 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
| 6501 | { |
| 6502 | if (gotrel[j].rel[object_64bit] != 0) |
| 6503 | { |
| 6504 | int first, second; |
| 6505 | char *tmpbuf, *past_reloc; |
| 6506 | |
| 6507 | *rel = gotrel[j].rel[object_64bit]; |
| 6508 | if (adjust) |
| 6509 | *adjust = len; |
| 6510 | |
| 6511 | if (types) |
| 6512 | { |
| 6513 | if (flag_code != CODE_64BIT) |
| 6514 | { |
| 6515 | types->bitfield.imm32 = 1; |
| 6516 | types->bitfield.disp32 = 1; |
| 6517 | } |
| 6518 | else |
| 6519 | *types = gotrel[j].types64; |
| 6520 | } |
| 6521 | |
| 6522 | if (GOT_symbol == NULL) |
| 6523 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
| 6524 | |
| 6525 | /* The length of the first part of our input line. */ |
| 6526 | first = cp - input_line_pointer; |
| 6527 | |
| 6528 | /* The second part goes from after the reloc token until |
| 6529 | (and including) an end_of_line char or comma. */ |
| 6530 | past_reloc = cp + 1 + len; |
| 6531 | cp = past_reloc; |
| 6532 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') |
| 6533 | ++cp; |
| 6534 | second = cp + 1 - past_reloc; |
| 6535 | |
| 6536 | /* Allocate and copy string. The trailing NUL shouldn't |
| 6537 | be necessary, but be safe. */ |
| 6538 | tmpbuf = (char *) xmalloc (first + second + 2); |
| 6539 | memcpy (tmpbuf, input_line_pointer, first); |
| 6540 | if (second != 0 && *past_reloc != ' ') |
| 6541 | /* Replace the relocation token with ' ', so that |
| 6542 | errors like foo@GOTOFF1 will be detected. */ |
| 6543 | tmpbuf[first++] = ' '; |
| 6544 | memcpy (tmpbuf + first, past_reloc, second); |
| 6545 | tmpbuf[first + second] = '\0'; |
| 6546 | return tmpbuf; |
| 6547 | } |
| 6548 | |
| 6549 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
| 6550 | gotrel[j].str, 1 << (5 + object_64bit)); |
| 6551 | return NULL; |
| 6552 | } |
| 6553 | } |
| 6554 | |
| 6555 | /* Might be a symbol version string. Don't as_bad here. */ |
| 6556 | return NULL; |
| 6557 | } |
| 6558 | |
| 6559 | void |
| 6560 | x86_cons (expressionS *exp, int size) |
| 6561 | { |
| 6562 | intel_syntax = -intel_syntax; |
| 6563 | |
| 6564 | exp->X_md = 0; |
| 6565 | if (size == 4 || (object_64bit && size == 8)) |
| 6566 | { |
| 6567 | /* Handle @GOTOFF and the like in an expression. */ |
| 6568 | char *save; |
| 6569 | char *gotfree_input_line; |
| 6570 | int adjust; |
| 6571 | |
| 6572 | save = input_line_pointer; |
| 6573 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
| 6574 | if (gotfree_input_line) |
| 6575 | input_line_pointer = gotfree_input_line; |
| 6576 | |
| 6577 | expression (exp); |
| 6578 | |
| 6579 | if (gotfree_input_line) |
| 6580 | { |
| 6581 | /* expression () has merrily parsed up to the end of line, |
| 6582 | or a comma - in the wrong buffer. Transfer how far |
| 6583 | input_line_pointer has moved to the right buffer. */ |
| 6584 | input_line_pointer = (save |
| 6585 | + (input_line_pointer - gotfree_input_line) |
| 6586 | + adjust); |
| 6587 | free (gotfree_input_line); |
| 6588 | if (exp->X_op == O_constant |
| 6589 | || exp->X_op == O_absent |
| 6590 | || exp->X_op == O_illegal |
| 6591 | || exp->X_op == O_register |
| 6592 | || exp->X_op == O_big) |
| 6593 | { |
| 6594 | char c = *input_line_pointer; |
| 6595 | *input_line_pointer = 0; |
| 6596 | as_bad (_("missing or invalid expression `%s'"), save); |
| 6597 | *input_line_pointer = c; |
| 6598 | } |
| 6599 | } |
| 6600 | } |
| 6601 | else |
| 6602 | expression (exp); |
| 6603 | |
| 6604 | intel_syntax = -intel_syntax; |
| 6605 | |
| 6606 | if (intel_syntax) |
| 6607 | i386_intel_simplify (exp); |
| 6608 | } |
| 6609 | #endif |
| 6610 | |
| 6611 | static void |
| 6612 | signed_cons (int size) |
| 6613 | { |
| 6614 | if (flag_code == CODE_64BIT) |
| 6615 | cons_sign = 1; |
| 6616 | cons (size); |
| 6617 | cons_sign = -1; |
| 6618 | } |
| 6619 | |
| 6620 | #ifdef TE_PE |
| 6621 | static void |
| 6622 | pe_directive_secrel (dummy) |
| 6623 | int dummy ATTRIBUTE_UNUSED; |
| 6624 | { |
| 6625 | expressionS exp; |
| 6626 | |
| 6627 | do |
| 6628 | { |
| 6629 | expression (&exp); |
| 6630 | if (exp.X_op == O_symbol) |
| 6631 | exp.X_op = O_secrel; |
| 6632 | |
| 6633 | emit_expr (&exp, 4); |
| 6634 | } |
| 6635 | while (*input_line_pointer++ == ','); |
| 6636 | |
| 6637 | input_line_pointer--; |
| 6638 | demand_empty_rest_of_line (); |
| 6639 | } |
| 6640 | #endif |
| 6641 | |
| 6642 | static int |
| 6643 | i386_immediate (char *imm_start) |
| 6644 | { |
| 6645 | char *save_input_line_pointer; |
| 6646 | char *gotfree_input_line; |
| 6647 | segT exp_seg = 0; |
| 6648 | expressionS *exp; |
| 6649 | i386_operand_type types; |
| 6650 | |
| 6651 | operand_type_set (&types, ~0); |
| 6652 | |
| 6653 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) |
| 6654 | { |
| 6655 | as_bad (_("at most %d immediate operands are allowed"), |
| 6656 | MAX_IMMEDIATE_OPERANDS); |
| 6657 | return 0; |
| 6658 | } |
| 6659 | |
| 6660 | exp = &im_expressions[i.imm_operands++]; |
| 6661 | i.op[this_operand].imms = exp; |
| 6662 | |
| 6663 | if (is_space_char (*imm_start)) |
| 6664 | ++imm_start; |
| 6665 | |
| 6666 | save_input_line_pointer = input_line_pointer; |
| 6667 | input_line_pointer = imm_start; |
| 6668 | |
| 6669 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
| 6670 | if (gotfree_input_line) |
| 6671 | input_line_pointer = gotfree_input_line; |
| 6672 | |
| 6673 | exp_seg = expression (exp); |
| 6674 | |
| 6675 | SKIP_WHITESPACE (); |
| 6676 | if (*input_line_pointer) |
| 6677 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
| 6678 | |
| 6679 | input_line_pointer = save_input_line_pointer; |
| 6680 | if (gotfree_input_line) |
| 6681 | { |
| 6682 | free (gotfree_input_line); |
| 6683 | |
| 6684 | if (exp->X_op == O_constant || exp->X_op == O_register) |
| 6685 | exp->X_op = O_illegal; |
| 6686 | } |
| 6687 | |
| 6688 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); |
| 6689 | } |
| 6690 | |
| 6691 | static int |
| 6692 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, |
| 6693 | i386_operand_type types, const char *imm_start) |
| 6694 | { |
| 6695 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) |
| 6696 | { |
| 6697 | if (imm_start) |
| 6698 | as_bad (_("missing or invalid immediate expression `%s'"), |
| 6699 | imm_start); |
| 6700 | return 0; |
| 6701 | } |
| 6702 | else if (exp->X_op == O_constant) |
| 6703 | { |
| 6704 | /* Size it properly later. */ |
| 6705 | i.types[this_operand].bitfield.imm64 = 1; |
| 6706 | /* If not 64bit, sign extend val. */ |
| 6707 | if (flag_code != CODE_64BIT |
| 6708 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
| 6709 | exp->X_add_number |
| 6710 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); |
| 6711 | } |
| 6712 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
| 6713 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
| 6714 | && exp_seg != absolute_section |
| 6715 | && exp_seg != text_section |
| 6716 | && exp_seg != data_section |
| 6717 | && exp_seg != bss_section |
| 6718 | && exp_seg != undefined_section |
| 6719 | && !bfd_is_com_section (exp_seg)) |
| 6720 | { |
| 6721 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
| 6722 | return 0; |
| 6723 | } |
| 6724 | #endif |
| 6725 | else if (!intel_syntax && exp->X_op == O_register) |
| 6726 | { |
| 6727 | if (imm_start) |
| 6728 | as_bad (_("illegal immediate register operand %s"), imm_start); |
| 6729 | return 0; |
| 6730 | } |
| 6731 | else |
| 6732 | { |
| 6733 | /* This is an address. The size of the address will be |
| 6734 | determined later, depending on destination register, |
| 6735 | suffix, or the default for the section. */ |
| 6736 | i.types[this_operand].bitfield.imm8 = 1; |
| 6737 | i.types[this_operand].bitfield.imm16 = 1; |
| 6738 | i.types[this_operand].bitfield.imm32 = 1; |
| 6739 | i.types[this_operand].bitfield.imm32s = 1; |
| 6740 | i.types[this_operand].bitfield.imm64 = 1; |
| 6741 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
| 6742 | types); |
| 6743 | } |
| 6744 | |
| 6745 | return 1; |
| 6746 | } |
| 6747 | |
| 6748 | static char * |
| 6749 | i386_scale (char *scale) |
| 6750 | { |
| 6751 | offsetT val; |
| 6752 | char *save = input_line_pointer; |
| 6753 | |
| 6754 | input_line_pointer = scale; |
| 6755 | val = get_absolute_expression (); |
| 6756 | |
| 6757 | switch (val) |
| 6758 | { |
| 6759 | case 1: |
| 6760 | i.log2_scale_factor = 0; |
| 6761 | break; |
| 6762 | case 2: |
| 6763 | i.log2_scale_factor = 1; |
| 6764 | break; |
| 6765 | case 4: |
| 6766 | i.log2_scale_factor = 2; |
| 6767 | break; |
| 6768 | case 8: |
| 6769 | i.log2_scale_factor = 3; |
| 6770 | break; |
| 6771 | default: |
| 6772 | { |
| 6773 | char sep = *input_line_pointer; |
| 6774 | |
| 6775 | *input_line_pointer = '\0'; |
| 6776 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), |
| 6777 | scale); |
| 6778 | *input_line_pointer = sep; |
| 6779 | input_line_pointer = save; |
| 6780 | return NULL; |
| 6781 | } |
| 6782 | } |
| 6783 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
| 6784 | { |
| 6785 | as_warn (_("scale factor of %d without an index register"), |
| 6786 | 1 << i.log2_scale_factor); |
| 6787 | i.log2_scale_factor = 0; |
| 6788 | } |
| 6789 | scale = input_line_pointer; |
| 6790 | input_line_pointer = save; |
| 6791 | return scale; |
| 6792 | } |
| 6793 | |
| 6794 | static int |
| 6795 | i386_displacement (char *disp_start, char *disp_end) |
| 6796 | { |
| 6797 | expressionS *exp; |
| 6798 | segT exp_seg = 0; |
| 6799 | char *save_input_line_pointer; |
| 6800 | char *gotfree_input_line; |
| 6801 | int override; |
| 6802 | i386_operand_type bigdisp, types = anydisp; |
| 6803 | int ret; |
| 6804 | |
| 6805 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
| 6806 | { |
| 6807 | as_bad (_("at most %d displacement operands are allowed"), |
| 6808 | MAX_MEMORY_OPERANDS); |
| 6809 | return 0; |
| 6810 | } |
| 6811 | |
| 6812 | operand_type_set (&bigdisp, 0); |
| 6813 | if ((i.types[this_operand].bitfield.jumpabsolute) |
| 6814 | || (!current_templates->start->opcode_modifier.jump |
| 6815 | && !current_templates->start->opcode_modifier.jumpdword)) |
| 6816 | { |
| 6817 | bigdisp.bitfield.disp32 = 1; |
| 6818 | override = (i.prefix[ADDR_PREFIX] != 0); |
| 6819 | if (flag_code == CODE_64BIT) |
| 6820 | { |
| 6821 | if (!override) |
| 6822 | { |
| 6823 | bigdisp.bitfield.disp32s = 1; |
| 6824 | bigdisp.bitfield.disp64 = 1; |
| 6825 | } |
| 6826 | } |
| 6827 | else if ((flag_code == CODE_16BIT) ^ override) |
| 6828 | { |
| 6829 | bigdisp.bitfield.disp32 = 0; |
| 6830 | bigdisp.bitfield.disp16 = 1; |
| 6831 | } |
| 6832 | } |
| 6833 | else |
| 6834 | { |
| 6835 | /* For PC-relative branches, the width of the displacement |
| 6836 | is dependent upon data size, not address size. */ |
| 6837 | override = (i.prefix[DATA_PREFIX] != 0); |
| 6838 | if (flag_code == CODE_64BIT) |
| 6839 | { |
| 6840 | if (override || i.suffix == WORD_MNEM_SUFFIX) |
| 6841 | bigdisp.bitfield.disp16 = 1; |
| 6842 | else |
| 6843 | { |
| 6844 | bigdisp.bitfield.disp32 = 1; |
| 6845 | bigdisp.bitfield.disp32s = 1; |
| 6846 | } |
| 6847 | } |
| 6848 | else |
| 6849 | { |
| 6850 | if (!override) |
| 6851 | override = (i.suffix == (flag_code != CODE_16BIT |
| 6852 | ? WORD_MNEM_SUFFIX |
| 6853 | : LONG_MNEM_SUFFIX)); |
| 6854 | bigdisp.bitfield.disp32 = 1; |
| 6855 | if ((flag_code == CODE_16BIT) ^ override) |
| 6856 | { |
| 6857 | bigdisp.bitfield.disp32 = 0; |
| 6858 | bigdisp.bitfield.disp16 = 1; |
| 6859 | } |
| 6860 | } |
| 6861 | } |
| 6862 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
| 6863 | bigdisp); |
| 6864 | |
| 6865 | exp = &disp_expressions[i.disp_operands]; |
| 6866 | i.op[this_operand].disps = exp; |
| 6867 | i.disp_operands++; |
| 6868 | save_input_line_pointer = input_line_pointer; |
| 6869 | input_line_pointer = disp_start; |
| 6870 | END_STRING_AND_SAVE (disp_end); |
| 6871 | |
| 6872 | #ifndef GCC_ASM_O_HACK |
| 6873 | #define GCC_ASM_O_HACK 0 |
| 6874 | #endif |
| 6875 | #if GCC_ASM_O_HACK |
| 6876 | END_STRING_AND_SAVE (disp_end + 1); |
| 6877 | if (i.types[this_operand].bitfield.baseIndex |
| 6878 | && displacement_string_end[-1] == '+') |
| 6879 | { |
| 6880 | /* This hack is to avoid a warning when using the "o" |
| 6881 | constraint within gcc asm statements. |
| 6882 | For instance: |
| 6883 | |
| 6884 | #define _set_tssldt_desc(n,addr,limit,type) \ |
| 6885 | __asm__ __volatile__ ( \ |
| 6886 | "movw %w2,%0\n\t" \ |
| 6887 | "movw %w1,2+%0\n\t" \ |
| 6888 | "rorl $16,%1\n\t" \ |
| 6889 | "movb %b1,4+%0\n\t" \ |
| 6890 | "movb %4,5+%0\n\t" \ |
| 6891 | "movb $0,6+%0\n\t" \ |
| 6892 | "movb %h1,7+%0\n\t" \ |
| 6893 | "rorl $16,%1" \ |
| 6894 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) |
| 6895 | |
| 6896 | This works great except that the output assembler ends |
| 6897 | up looking a bit weird if it turns out that there is |
| 6898 | no offset. You end up producing code that looks like: |
| 6899 | |
| 6900 | #APP |
| 6901 | movw $235,(%eax) |
| 6902 | movw %dx,2+(%eax) |
| 6903 | rorl $16,%edx |
| 6904 | movb %dl,4+(%eax) |
| 6905 | movb $137,5+(%eax) |
| 6906 | movb $0,6+(%eax) |
| 6907 | movb %dh,7+(%eax) |
| 6908 | rorl $16,%edx |
| 6909 | #NO_APP |
| 6910 | |
| 6911 | So here we provide the missing zero. */ |
| 6912 | |
| 6913 | *displacement_string_end = '0'; |
| 6914 | } |
| 6915 | #endif |
| 6916 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
| 6917 | if (gotfree_input_line) |
| 6918 | input_line_pointer = gotfree_input_line; |
| 6919 | |
| 6920 | exp_seg = expression (exp); |
| 6921 | |
| 6922 | SKIP_WHITESPACE (); |
| 6923 | if (*input_line_pointer) |
| 6924 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
| 6925 | #if GCC_ASM_O_HACK |
| 6926 | RESTORE_END_STRING (disp_end + 1); |
| 6927 | #endif |
| 6928 | input_line_pointer = save_input_line_pointer; |
| 6929 | if (gotfree_input_line) |
| 6930 | { |
| 6931 | free (gotfree_input_line); |
| 6932 | |
| 6933 | if (exp->X_op == O_constant || exp->X_op == O_register) |
| 6934 | exp->X_op = O_illegal; |
| 6935 | } |
| 6936 | |
| 6937 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); |
| 6938 | |
| 6939 | RESTORE_END_STRING (disp_end); |
| 6940 | |
| 6941 | return ret; |
| 6942 | } |
| 6943 | |
| 6944 | static int |
| 6945 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, |
| 6946 | i386_operand_type types, const char *disp_start) |
| 6947 | { |
| 6948 | i386_operand_type bigdisp; |
| 6949 | int ret = 1; |
| 6950 | |
| 6951 | /* We do this to make sure that the section symbol is in |
| 6952 | the symbol table. We will ultimately change the relocation |
| 6953 | to be relative to the beginning of the section. */ |
| 6954 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
| 6955 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
| 6956 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
| 6957 | { |
| 6958 | if (exp->X_op != O_symbol) |
| 6959 | goto inv_disp; |
| 6960 | |
| 6961 | if (S_IS_LOCAL (exp->X_add_symbol) |
| 6962 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
| 6963 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) |
| 6964 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
| 6965 | exp->X_op = O_subtract; |
| 6966 | exp->X_op_symbol = GOT_symbol; |
| 6967 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
| 6968 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
| 6969 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
| 6970 | i.reloc[this_operand] = BFD_RELOC_64; |
| 6971 | else |
| 6972 | i.reloc[this_operand] = BFD_RELOC_32; |
| 6973 | } |
| 6974 | |
| 6975 | else if (exp->X_op == O_absent |
| 6976 | || exp->X_op == O_illegal |
| 6977 | || exp->X_op == O_big) |
| 6978 | { |
| 6979 | inv_disp: |
| 6980 | as_bad (_("missing or invalid displacement expression `%s'"), |
| 6981 | disp_start); |
| 6982 | ret = 0; |
| 6983 | } |
| 6984 | |
| 6985 | else if (flag_code == CODE_64BIT |
| 6986 | && !i.prefix[ADDR_PREFIX] |
| 6987 | && exp->X_op == O_constant) |
| 6988 | { |
| 6989 | /* Since displacement is signed extended to 64bit, don't allow |
| 6990 | disp32 and turn off disp32s if they are out of range. */ |
| 6991 | i.types[this_operand].bitfield.disp32 = 0; |
| 6992 | if (!fits_in_signed_long (exp->X_add_number)) |
| 6993 | { |
| 6994 | i.types[this_operand].bitfield.disp32s = 0; |
| 6995 | if (i.types[this_operand].bitfield.baseindex) |
| 6996 | { |
| 6997 | as_bad (_("0x%lx out range of signed 32bit displacement"), |
| 6998 | (long) exp->X_add_number); |
| 6999 | ret = 0; |
| 7000 | } |
| 7001 | } |
| 7002 | } |
| 7003 | |
| 7004 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
| 7005 | else if (exp->X_op != O_constant |
| 7006 | && OUTPUT_FLAVOR == bfd_target_aout_flavour |
| 7007 | && exp_seg != absolute_section |
| 7008 | && exp_seg != text_section |
| 7009 | && exp_seg != data_section |
| 7010 | && exp_seg != bss_section |
| 7011 | && exp_seg != undefined_section |
| 7012 | && !bfd_is_com_section (exp_seg)) |
| 7013 | { |
| 7014 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
| 7015 | ret = 0; |
| 7016 | } |
| 7017 | #endif |
| 7018 | |
| 7019 | /* Check if this is a displacement only operand. */ |
| 7020 | bigdisp = i.types[this_operand]; |
| 7021 | bigdisp.bitfield.disp8 = 0; |
| 7022 | bigdisp.bitfield.disp16 = 0; |
| 7023 | bigdisp.bitfield.disp32 = 0; |
| 7024 | bigdisp.bitfield.disp32s = 0; |
| 7025 | bigdisp.bitfield.disp64 = 0; |
| 7026 | if (operand_type_all_zero (&bigdisp)) |
| 7027 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
| 7028 | types); |
| 7029 | |
| 7030 | return ret; |
| 7031 | } |
| 7032 | |
| 7033 | /* Make sure the memory operand we've been dealt is valid. |
| 7034 | Return 1 on success, 0 on a failure. */ |
| 7035 | |
| 7036 | static int |
| 7037 | i386_index_check (const char *operand_string) |
| 7038 | { |
| 7039 | int ok; |
| 7040 | const char *kind = "base/index"; |
| 7041 | #if INFER_ADDR_PREFIX |
| 7042 | int fudged = 0; |
| 7043 | |
| 7044 | tryprefix: |
| 7045 | #endif |
| 7046 | ok = 1; |
| 7047 | if (current_templates->start->opcode_modifier.isstring |
| 7048 | && !current_templates->start->opcode_modifier.immext |
| 7049 | && (current_templates->end[-1].opcode_modifier.isstring |
| 7050 | || i.mem_operands)) |
| 7051 | { |
| 7052 | /* Memory operands of string insns are special in that they only allow |
| 7053 | a single register (rDI, rSI, or rBX) as their memory address. */ |
| 7054 | unsigned int expected; |
| 7055 | |
| 7056 | kind = "string address"; |
| 7057 | |
| 7058 | if (current_templates->start->opcode_modifier.w) |
| 7059 | { |
| 7060 | i386_operand_type type = current_templates->end[-1].operand_types[0]; |
| 7061 | |
| 7062 | if (!type.bitfield.baseindex |
| 7063 | || ((!i.mem_operands != !intel_syntax) |
| 7064 | && current_templates->end[-1].operand_types[1] |
| 7065 | .bitfield.baseindex)) |
| 7066 | type = current_templates->end[-1].operand_types[1]; |
| 7067 | expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */; |
| 7068 | } |
| 7069 | else |
| 7070 | expected = 3 /* rBX */; |
| 7071 | |
| 7072 | if (!i.base_reg || i.index_reg |
| 7073 | || operand_type_check (i.types[this_operand], disp)) |
| 7074 | ok = -1; |
| 7075 | else if (!(flag_code == CODE_64BIT |
| 7076 | ? i.prefix[ADDR_PREFIX] |
| 7077 | ? i.base_reg->reg_type.bitfield.reg32 |
| 7078 | : i.base_reg->reg_type.bitfield.reg64 |
| 7079 | : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX] |
| 7080 | ? i.base_reg->reg_type.bitfield.reg32 |
| 7081 | : i.base_reg->reg_type.bitfield.reg16)) |
| 7082 | ok = 0; |
| 7083 | else if (i.base_reg->reg_num != expected) |
| 7084 | ok = -1; |
| 7085 | |
| 7086 | if (ok < 0) |
| 7087 | { |
| 7088 | unsigned int j; |
| 7089 | |
| 7090 | for (j = 0; j < i386_regtab_size; ++j) |
| 7091 | if ((flag_code == CODE_64BIT |
| 7092 | ? i.prefix[ADDR_PREFIX] |
| 7093 | ? i386_regtab[j].reg_type.bitfield.reg32 |
| 7094 | : i386_regtab[j].reg_type.bitfield.reg64 |
| 7095 | : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX] |
| 7096 | ? i386_regtab[j].reg_type.bitfield.reg32 |
| 7097 | : i386_regtab[j].reg_type.bitfield.reg16) |
| 7098 | && i386_regtab[j].reg_num == expected) |
| 7099 | break; |
| 7100 | gas_assert (j < i386_regtab_size); |
| 7101 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
| 7102 | operand_string, |
| 7103 | intel_syntax ? '[' : '(', |
| 7104 | register_prefix, |
| 7105 | i386_regtab[j].reg_name, |
| 7106 | intel_syntax ? ']' : ')'); |
| 7107 | ok = 1; |
| 7108 | } |
| 7109 | } |
| 7110 | else if (flag_code == CODE_64BIT) |
| 7111 | { |
| 7112 | if ((i.base_reg |
| 7113 | && ((i.prefix[ADDR_PREFIX] == 0 |
| 7114 | && !i.base_reg->reg_type.bitfield.reg64) |
| 7115 | || (i.prefix[ADDR_PREFIX] |
| 7116 | && !i.base_reg->reg_type.bitfield.reg32)) |
| 7117 | && (i.index_reg |
| 7118 | || i.base_reg->reg_num != |
| 7119 | (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip))) |
| 7120 | || (i.index_reg |
| 7121 | && (!i.index_reg->reg_type.bitfield.baseindex |
| 7122 | || (i.prefix[ADDR_PREFIX] == 0 |
| 7123 | && i.index_reg->reg_num != RegRiz |
| 7124 | && !i.index_reg->reg_type.bitfield.reg64 |
| 7125 | ) |
| 7126 | || (i.prefix[ADDR_PREFIX] |
| 7127 | && i.index_reg->reg_num != RegEiz |
| 7128 | && !i.index_reg->reg_type.bitfield.reg32)))) |
| 7129 | ok = 0; |
| 7130 | } |
| 7131 | else |
| 7132 | { |
| 7133 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) |
| 7134 | { |
| 7135 | /* 16bit checks. */ |
| 7136 | if ((i.base_reg |
| 7137 | && (!i.base_reg->reg_type.bitfield.reg16 |
| 7138 | || !i.base_reg->reg_type.bitfield.baseindex)) |
| 7139 | || (i.index_reg |
| 7140 | && (!i.index_reg->reg_type.bitfield.reg16 |
| 7141 | || !i.index_reg->reg_type.bitfield.baseindex |
| 7142 | || !(i.base_reg |
| 7143 | && i.base_reg->reg_num < 6 |
| 7144 | && i.index_reg->reg_num >= 6 |
| 7145 | && i.log2_scale_factor == 0)))) |
| 7146 | ok = 0; |
| 7147 | } |
| 7148 | else |
| 7149 | { |
| 7150 | /* 32bit checks. */ |
| 7151 | if ((i.base_reg |
| 7152 | && !i.base_reg->reg_type.bitfield.reg32) |
| 7153 | || (i.index_reg |
| 7154 | && ((!i.index_reg->reg_type.bitfield.reg32 |
| 7155 | && i.index_reg->reg_num != RegEiz) |
| 7156 | || !i.index_reg->reg_type.bitfield.baseindex))) |
| 7157 | ok = 0; |
| 7158 | } |
| 7159 | } |
| 7160 | if (!ok) |
| 7161 | { |
| 7162 | #if INFER_ADDR_PREFIX |
| 7163 | if (!i.mem_operands && !i.prefix[ADDR_PREFIX]) |
| 7164 | { |
| 7165 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; |
| 7166 | i.prefixes += 1; |
| 7167 | /* Change the size of any displacement too. At most one of |
| 7168 | Disp16 or Disp32 is set. |
| 7169 | FIXME. There doesn't seem to be any real need for separate |
| 7170 | Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. |
| 7171 | Removing them would probably clean up the code quite a lot. */ |
| 7172 | if (flag_code != CODE_64BIT |
| 7173 | && (i.types[this_operand].bitfield.disp16 |
| 7174 | || i.types[this_operand].bitfield.disp32)) |
| 7175 | i.types[this_operand] |
| 7176 | = operand_type_xor (i.types[this_operand], disp16_32); |
| 7177 | fudged = 1; |
| 7178 | goto tryprefix; |
| 7179 | } |
| 7180 | if (fudged) |
| 7181 | as_bad (_("`%s' is not a valid %s expression"), |
| 7182 | operand_string, |
| 7183 | kind); |
| 7184 | else |
| 7185 | #endif |
| 7186 | as_bad (_("`%s' is not a valid %s-bit %s expression"), |
| 7187 | operand_string, |
| 7188 | flag_code_names[i.prefix[ADDR_PREFIX] |
| 7189 | ? flag_code == CODE_32BIT |
| 7190 | ? CODE_16BIT |
| 7191 | : CODE_32BIT |
| 7192 | : flag_code], |
| 7193 | kind); |
| 7194 | } |
| 7195 | return ok; |
| 7196 | } |
| 7197 | |
| 7198 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
| 7199 | on error. */ |
| 7200 | |
| 7201 | static int |
| 7202 | i386_att_operand (char *operand_string) |
| 7203 | { |
| 7204 | const reg_entry *r; |
| 7205 | char *end_op; |
| 7206 | char *op_string = operand_string; |
| 7207 | |
| 7208 | if (is_space_char (*op_string)) |
| 7209 | ++op_string; |
| 7210 | |
| 7211 | /* We check for an absolute prefix (differentiating, |
| 7212 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
| 7213 | if (*op_string == ABSOLUTE_PREFIX) |
| 7214 | { |
| 7215 | ++op_string; |
| 7216 | if (is_space_char (*op_string)) |
| 7217 | ++op_string; |
| 7218 | i.types[this_operand].bitfield.jumpabsolute = 1; |
| 7219 | } |
| 7220 | |
| 7221 | /* Check if operand is a register. */ |
| 7222 | if ((r = parse_register (op_string, &end_op)) != NULL) |
| 7223 | { |
| 7224 | i386_operand_type temp; |
| 7225 | |
| 7226 | /* Check for a segment override by searching for ':' after a |
| 7227 | segment register. */ |
| 7228 | op_string = end_op; |
| 7229 | if (is_space_char (*op_string)) |
| 7230 | ++op_string; |
| 7231 | if (*op_string == ':' |
| 7232 | && (r->reg_type.bitfield.sreg2 |
| 7233 | || r->reg_type.bitfield.sreg3)) |
| 7234 | { |
| 7235 | switch (r->reg_num) |
| 7236 | { |
| 7237 | case 0: |
| 7238 | i.seg[i.mem_operands] = &es; |
| 7239 | break; |
| 7240 | case 1: |
| 7241 | i.seg[i.mem_operands] = &cs; |
| 7242 | break; |
| 7243 | case 2: |
| 7244 | i.seg[i.mem_operands] = &ss; |
| 7245 | break; |
| 7246 | case 3: |
| 7247 | i.seg[i.mem_operands] = &ds; |
| 7248 | break; |
| 7249 | case 4: |
| 7250 | i.seg[i.mem_operands] = &fs; |
| 7251 | break; |
| 7252 | case 5: |
| 7253 | i.seg[i.mem_operands] = &gs; |
| 7254 | break; |
| 7255 | } |
| 7256 | |
| 7257 | /* Skip the ':' and whitespace. */ |
| 7258 | ++op_string; |
| 7259 | if (is_space_char (*op_string)) |
| 7260 | ++op_string; |
| 7261 | |
| 7262 | if (!is_digit_char (*op_string) |
| 7263 | && !is_identifier_char (*op_string) |
| 7264 | && *op_string != '(' |
| 7265 | && *op_string != ABSOLUTE_PREFIX) |
| 7266 | { |
| 7267 | as_bad (_("bad memory operand `%s'"), op_string); |
| 7268 | return 0; |
| 7269 | } |
| 7270 | /* Handle case of %es:*foo. */ |
| 7271 | if (*op_string == ABSOLUTE_PREFIX) |
| 7272 | { |
| 7273 | ++op_string; |
| 7274 | if (is_space_char (*op_string)) |
| 7275 | ++op_string; |
| 7276 | i.types[this_operand].bitfield.jumpabsolute = 1; |
| 7277 | } |
| 7278 | goto do_memory_reference; |
| 7279 | } |
| 7280 | if (*op_string) |
| 7281 | { |
| 7282 | as_bad (_("junk `%s' after register"), op_string); |
| 7283 | return 0; |
| 7284 | } |
| 7285 | temp = r->reg_type; |
| 7286 | temp.bitfield.baseindex = 0; |
| 7287 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
| 7288 | temp); |
| 7289 | i.types[this_operand].bitfield.unspecified = 0; |
| 7290 | i.op[this_operand].regs = r; |
| 7291 | i.reg_operands++; |
| 7292 | } |
| 7293 | else if (*op_string == REGISTER_PREFIX) |
| 7294 | { |
| 7295 | as_bad (_("bad register name `%s'"), op_string); |
| 7296 | return 0; |
| 7297 | } |
| 7298 | else if (*op_string == IMMEDIATE_PREFIX) |
| 7299 | { |
| 7300 | ++op_string; |
| 7301 | if (i.types[this_operand].bitfield.jumpabsolute) |
| 7302 | { |
| 7303 | as_bad (_("immediate operand illegal with absolute jump")); |
| 7304 | return 0; |
| 7305 | } |
| 7306 | if (!i386_immediate (op_string)) |
| 7307 | return 0; |
| 7308 | } |
| 7309 | else if (is_digit_char (*op_string) |
| 7310 | || is_identifier_char (*op_string) |
| 7311 | || *op_string == '(') |
| 7312 | { |
| 7313 | /* This is a memory reference of some sort. */ |
| 7314 | char *base_string; |
| 7315 | |
| 7316 | /* Start and end of displacement string expression (if found). */ |
| 7317 | char *displacement_string_start; |
| 7318 | char *displacement_string_end; |
| 7319 | |
| 7320 | do_memory_reference: |
| 7321 | if ((i.mem_operands == 1 |
| 7322 | && !current_templates->start->opcode_modifier.isstring) |
| 7323 | || i.mem_operands == 2) |
| 7324 | { |
| 7325 | as_bad (_("too many memory references for `%s'"), |
| 7326 | current_templates->start->name); |
| 7327 | return 0; |
| 7328 | } |
| 7329 | |
| 7330 | /* Check for base index form. We detect the base index form by |
| 7331 | looking for an ')' at the end of the operand, searching |
| 7332 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' |
| 7333 | after the '('. */ |
| 7334 | base_string = op_string + strlen (op_string); |
| 7335 | |
| 7336 | --base_string; |
| 7337 | if (is_space_char (*base_string)) |
| 7338 | --base_string; |
| 7339 | |
| 7340 | /* If we only have a displacement, set-up for it to be parsed later. */ |
| 7341 | displacement_string_start = op_string; |
| 7342 | displacement_string_end = base_string + 1; |
| 7343 | |
| 7344 | if (*base_string == ')') |
| 7345 | { |
| 7346 | char *temp_string; |
| 7347 | unsigned int parens_balanced = 1; |
| 7348 | /* We've already checked that the number of left & right ()'s are |
| 7349 | equal, so this loop will not be infinite. */ |
| 7350 | do |
| 7351 | { |
| 7352 | base_string--; |
| 7353 | if (*base_string == ')') |
| 7354 | parens_balanced++; |
| 7355 | if (*base_string == '(') |
| 7356 | parens_balanced--; |
| 7357 | } |
| 7358 | while (parens_balanced); |
| 7359 | |
| 7360 | temp_string = base_string; |
| 7361 | |
| 7362 | /* Skip past '(' and whitespace. */ |
| 7363 | ++base_string; |
| 7364 | if (is_space_char (*base_string)) |
| 7365 | ++base_string; |
| 7366 | |
| 7367 | if (*base_string == ',' |
| 7368 | || ((i.base_reg = parse_register (base_string, &end_op)) |
| 7369 | != NULL)) |
| 7370 | { |
| 7371 | displacement_string_end = temp_string; |
| 7372 | |
| 7373 | i.types[this_operand].bitfield.baseindex = 1; |
| 7374 | |
| 7375 | if (i.base_reg) |
| 7376 | { |
| 7377 | base_string = end_op; |
| 7378 | if (is_space_char (*base_string)) |
| 7379 | ++base_string; |
| 7380 | } |
| 7381 | |
| 7382 | /* There may be an index reg or scale factor here. */ |
| 7383 | if (*base_string == ',') |
| 7384 | { |
| 7385 | ++base_string; |
| 7386 | if (is_space_char (*base_string)) |
| 7387 | ++base_string; |
| 7388 | |
| 7389 | if ((i.index_reg = parse_register (base_string, &end_op)) |
| 7390 | != NULL) |
| 7391 | { |
| 7392 | base_string = end_op; |
| 7393 | if (is_space_char (*base_string)) |
| 7394 | ++base_string; |
| 7395 | if (*base_string == ',') |
| 7396 | { |
| 7397 | ++base_string; |
| 7398 | if (is_space_char (*base_string)) |
| 7399 | ++base_string; |
| 7400 | } |
| 7401 | else if (*base_string != ')') |
| 7402 | { |
| 7403 | as_bad (_("expecting `,' or `)' " |
| 7404 | "after index register in `%s'"), |
| 7405 | operand_string); |
| 7406 | return 0; |
| 7407 | } |
| 7408 | } |
| 7409 | else if (*base_string == REGISTER_PREFIX) |
| 7410 | { |
| 7411 | as_bad (_("bad register name `%s'"), base_string); |
| 7412 | return 0; |
| 7413 | } |
| 7414 | |
| 7415 | /* Check for scale factor. */ |
| 7416 | if (*base_string != ')') |
| 7417 | { |
| 7418 | char *end_scale = i386_scale (base_string); |
| 7419 | |
| 7420 | if (!end_scale) |
| 7421 | return 0; |
| 7422 | |
| 7423 | base_string = end_scale; |
| 7424 | if (is_space_char (*base_string)) |
| 7425 | ++base_string; |
| 7426 | if (*base_string != ')') |
| 7427 | { |
| 7428 | as_bad (_("expecting `)' " |
| 7429 | "after scale factor in `%s'"), |
| 7430 | operand_string); |
| 7431 | return 0; |
| 7432 | } |
| 7433 | } |
| 7434 | else if (!i.index_reg) |
| 7435 | { |
| 7436 | as_bad (_("expecting index register or scale factor " |
| 7437 | "after `,'; got '%c'"), |
| 7438 | *base_string); |
| 7439 | return 0; |
| 7440 | } |
| 7441 | } |
| 7442 | else if (*base_string != ')') |
| 7443 | { |
| 7444 | as_bad (_("expecting `,' or `)' " |
| 7445 | "after base register in `%s'"), |
| 7446 | operand_string); |
| 7447 | return 0; |
| 7448 | } |
| 7449 | } |
| 7450 | else if (*base_string == REGISTER_PREFIX) |
| 7451 | { |
| 7452 | as_bad (_("bad register name `%s'"), base_string); |
| 7453 | return 0; |
| 7454 | } |
| 7455 | } |
| 7456 | |
| 7457 | /* If there's an expression beginning the operand, parse it, |
| 7458 | assuming displacement_string_start and |
| 7459 | displacement_string_end are meaningful. */ |
| 7460 | if (displacement_string_start != displacement_string_end) |
| 7461 | { |
| 7462 | if (!i386_displacement (displacement_string_start, |
| 7463 | displacement_string_end)) |
| 7464 | return 0; |
| 7465 | } |
| 7466 | |
| 7467 | /* Special case for (%dx) while doing input/output op. */ |
| 7468 | if (i.base_reg |
| 7469 | && operand_type_equal (&i.base_reg->reg_type, |
| 7470 | ®16_inoutportreg) |
| 7471 | && i.index_reg == 0 |
| 7472 | && i.log2_scale_factor == 0 |
| 7473 | && i.seg[i.mem_operands] == 0 |
| 7474 | && !operand_type_check (i.types[this_operand], disp)) |
| 7475 | { |
| 7476 | i.types[this_operand] = inoutportreg; |
| 7477 | return 1; |
| 7478 | } |
| 7479 | |
| 7480 | if (i386_index_check (operand_string) == 0) |
| 7481 | return 0; |
| 7482 | i.types[this_operand].bitfield.mem = 1; |
| 7483 | i.mem_operands++; |
| 7484 | } |
| 7485 | else |
| 7486 | { |
| 7487 | /* It's not a memory operand; argh! */ |
| 7488 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
| 7489 | output_invalid (*op_string), |
| 7490 | this_operand + 1, |
| 7491 | op_string); |
| 7492 | return 0; |
| 7493 | } |
| 7494 | return 1; /* Normal return. */ |
| 7495 | } |
| 7496 | \f |
| 7497 | /* md_estimate_size_before_relax() |
| 7498 | |
| 7499 | Called just before relax() for rs_machine_dependent frags. The x86 |
| 7500 | assembler uses these frags to handle variable size jump |
| 7501 | instructions. |
| 7502 | |
| 7503 | Any symbol that is now undefined will not become defined. |
| 7504 | Return the correct fr_subtype in the frag. |
| 7505 | Return the initial "guess for variable size of frag" to caller. |
| 7506 | The guess is actually the growth beyond the fixed part. Whatever |
| 7507 | we do to grow the fixed or variable part contributes to our |
| 7508 | returned value. */ |
| 7509 | |
| 7510 | int |
| 7511 | md_estimate_size_before_relax (fragP, segment) |
| 7512 | fragS *fragP; |
| 7513 | segT segment; |
| 7514 | { |
| 7515 | /* We've already got fragP->fr_subtype right; all we have to do is |
| 7516 | check for un-relaxable symbols. On an ELF system, we can't relax |
| 7517 | an externally visible symbol, because it may be overridden by a |
| 7518 | shared library. */ |
| 7519 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment |
| 7520 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 7521 | || (IS_ELF |
| 7522 | && (S_IS_EXTERNAL (fragP->fr_symbol) |
| 7523 | || S_IS_WEAK (fragP->fr_symbol) |
| 7524 | || ((symbol_get_bfdsym (fragP->fr_symbol)->flags |
| 7525 | & BSF_GNU_INDIRECT_FUNCTION)))) |
| 7526 | #endif |
| 7527 | #if defined (OBJ_COFF) && defined (TE_PE) |
| 7528 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
| 7529 | && S_IS_WEAK (fragP->fr_symbol)) |
| 7530 | #endif |
| 7531 | ) |
| 7532 | { |
| 7533 | /* Symbol is undefined in this segment, or we need to keep a |
| 7534 | reloc so that weak symbols can be overridden. */ |
| 7535 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; |
| 7536 | enum bfd_reloc_code_real reloc_type; |
| 7537 | unsigned char *opcode; |
| 7538 | int old_fr_fix; |
| 7539 | |
| 7540 | if (fragP->fr_var != NO_RELOC) |
| 7541 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
| 7542 | else if (size == 2) |
| 7543 | reloc_type = BFD_RELOC_16_PCREL; |
| 7544 | else |
| 7545 | reloc_type = BFD_RELOC_32_PCREL; |
| 7546 | |
| 7547 | old_fr_fix = fragP->fr_fix; |
| 7548 | opcode = (unsigned char *) fragP->fr_opcode; |
| 7549 | |
| 7550 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
| 7551 | { |
| 7552 | case UNCOND_JUMP: |
| 7553 | /* Make jmp (0xeb) a (d)word displacement jump. */ |
| 7554 | opcode[0] = 0xe9; |
| 7555 | fragP->fr_fix += size; |
| 7556 | fix_new (fragP, old_fr_fix, size, |
| 7557 | fragP->fr_symbol, |
| 7558 | fragP->fr_offset, 1, |
| 7559 | reloc_type); |
| 7560 | break; |
| 7561 | |
| 7562 | case COND_JUMP86: |
| 7563 | if (size == 2 |
| 7564 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) |
| 7565 | { |
| 7566 | /* Negate the condition, and branch past an |
| 7567 | unconditional jump. */ |
| 7568 | opcode[0] ^= 1; |
| 7569 | opcode[1] = 3; |
| 7570 | /* Insert an unconditional jump. */ |
| 7571 | opcode[2] = 0xe9; |
| 7572 | /* We added two extra opcode bytes, and have a two byte |
| 7573 | offset. */ |
| 7574 | fragP->fr_fix += 2 + 2; |
| 7575 | fix_new (fragP, old_fr_fix + 2, 2, |
| 7576 | fragP->fr_symbol, |
| 7577 | fragP->fr_offset, 1, |
| 7578 | reloc_type); |
| 7579 | break; |
| 7580 | } |
| 7581 | /* Fall through. */ |
| 7582 | |
| 7583 | case COND_JUMP: |
| 7584 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
| 7585 | { |
| 7586 | fixS *fixP; |
| 7587 | |
| 7588 | fragP->fr_fix += 1; |
| 7589 | fixP = fix_new (fragP, old_fr_fix, 1, |
| 7590 | fragP->fr_symbol, |
| 7591 | fragP->fr_offset, 1, |
| 7592 | BFD_RELOC_8_PCREL); |
| 7593 | fixP->fx_signed = 1; |
| 7594 | break; |
| 7595 | } |
| 7596 | |
| 7597 | /* This changes the byte-displacement jump 0x7N |
| 7598 | to the (d)word-displacement jump 0x0f,0x8N. */ |
| 7599 | opcode[1] = opcode[0] + 0x10; |
| 7600 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
| 7601 | /* We've added an opcode byte. */ |
| 7602 | fragP->fr_fix += 1 + size; |
| 7603 | fix_new (fragP, old_fr_fix + 1, size, |
| 7604 | fragP->fr_symbol, |
| 7605 | fragP->fr_offset, 1, |
| 7606 | reloc_type); |
| 7607 | break; |
| 7608 | |
| 7609 | default: |
| 7610 | BAD_CASE (fragP->fr_subtype); |
| 7611 | break; |
| 7612 | } |
| 7613 | frag_wane (fragP); |
| 7614 | return fragP->fr_fix - old_fr_fix; |
| 7615 | } |
| 7616 | |
| 7617 | /* Guess size depending on current relax state. Initially the relax |
| 7618 | state will correspond to a short jump and we return 1, because |
| 7619 | the variable part of the frag (the branch offset) is one byte |
| 7620 | long. However, we can relax a section more than once and in that |
| 7621 | case we must either set fr_subtype back to the unrelaxed state, |
| 7622 | or return the value for the appropriate branch. */ |
| 7623 | return md_relax_table[fragP->fr_subtype].rlx_length; |
| 7624 | } |
| 7625 | |
| 7626 | /* Called after relax() is finished. |
| 7627 | |
| 7628 | In: Address of frag. |
| 7629 | fr_type == rs_machine_dependent. |
| 7630 | fr_subtype is what the address relaxed to. |
| 7631 | |
| 7632 | Out: Any fixSs and constants are set up. |
| 7633 | Caller will turn frag into a ".space 0". */ |
| 7634 | |
| 7635 | void |
| 7636 | md_convert_frag (abfd, sec, fragP) |
| 7637 | bfd *abfd ATTRIBUTE_UNUSED; |
| 7638 | segT sec ATTRIBUTE_UNUSED; |
| 7639 | fragS *fragP; |
| 7640 | { |
| 7641 | unsigned char *opcode; |
| 7642 | unsigned char *where_to_put_displacement = NULL; |
| 7643 | offsetT target_address; |
| 7644 | offsetT opcode_address; |
| 7645 | unsigned int extension = 0; |
| 7646 | offsetT displacement_from_opcode_start; |
| 7647 | |
| 7648 | opcode = (unsigned char *) fragP->fr_opcode; |
| 7649 | |
| 7650 | /* Address we want to reach in file space. */ |
| 7651 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
| 7652 | |
| 7653 | /* Address opcode resides at in file space. */ |
| 7654 | opcode_address = fragP->fr_address + fragP->fr_fix; |
| 7655 | |
| 7656 | /* Displacement from opcode start to fill into instruction. */ |
| 7657 | displacement_from_opcode_start = target_address - opcode_address; |
| 7658 | |
| 7659 | if ((fragP->fr_subtype & BIG) == 0) |
| 7660 | { |
| 7661 | /* Don't have to change opcode. */ |
| 7662 | extension = 1; /* 1 opcode + 1 displacement */ |
| 7663 | where_to_put_displacement = &opcode[1]; |
| 7664 | } |
| 7665 | else |
| 7666 | { |
| 7667 | if (no_cond_jump_promotion |
| 7668 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) |
| 7669 | as_warn_where (fragP->fr_file, fragP->fr_line, |
| 7670 | _("long jump required")); |
| 7671 | |
| 7672 | switch (fragP->fr_subtype) |
| 7673 | { |
| 7674 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): |
| 7675 | extension = 4; /* 1 opcode + 4 displacement */ |
| 7676 | opcode[0] = 0xe9; |
| 7677 | where_to_put_displacement = &opcode[1]; |
| 7678 | break; |
| 7679 | |
| 7680 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
| 7681 | extension = 2; /* 1 opcode + 2 displacement */ |
| 7682 | opcode[0] = 0xe9; |
| 7683 | where_to_put_displacement = &opcode[1]; |
| 7684 | break; |
| 7685 | |
| 7686 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
| 7687 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): |
| 7688 | extension = 5; /* 2 opcode + 4 displacement */ |
| 7689 | opcode[1] = opcode[0] + 0x10; |
| 7690 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
| 7691 | where_to_put_displacement = &opcode[2]; |
| 7692 | break; |
| 7693 | |
| 7694 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
| 7695 | extension = 3; /* 2 opcode + 2 displacement */ |
| 7696 | opcode[1] = opcode[0] + 0x10; |
| 7697 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
| 7698 | where_to_put_displacement = &opcode[2]; |
| 7699 | break; |
| 7700 | |
| 7701 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
| 7702 | extension = 4; |
| 7703 | opcode[0] ^= 1; |
| 7704 | opcode[1] = 3; |
| 7705 | opcode[2] = 0xe9; |
| 7706 | where_to_put_displacement = &opcode[3]; |
| 7707 | break; |
| 7708 | |
| 7709 | default: |
| 7710 | BAD_CASE (fragP->fr_subtype); |
| 7711 | break; |
| 7712 | } |
| 7713 | } |
| 7714 | |
| 7715 | /* If size if less then four we are sure that the operand fits, |
| 7716 | but if it's 4, then it could be that the displacement is larger |
| 7717 | then -/+ 2GB. */ |
| 7718 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 |
| 7719 | && object_64bit |
| 7720 | && ((addressT) (displacement_from_opcode_start - extension |
| 7721 | + ((addressT) 1 << 31)) |
| 7722 | > (((addressT) 2 << 31) - 1))) |
| 7723 | { |
| 7724 | as_bad_where (fragP->fr_file, fragP->fr_line, |
| 7725 | _("jump target out of range")); |
| 7726 | /* Make us emit 0. */ |
| 7727 | displacement_from_opcode_start = extension; |
| 7728 | } |
| 7729 | /* Now put displacement after opcode. */ |
| 7730 | md_number_to_chars ((char *) where_to_put_displacement, |
| 7731 | (valueT) (displacement_from_opcode_start - extension), |
| 7732 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
| 7733 | fragP->fr_fix += extension; |
| 7734 | } |
| 7735 | \f |
| 7736 | /* Apply a fixup (fixS) to segment data, once it has been determined |
| 7737 | by our caller that we have all the info we need to fix it up. |
| 7738 | |
| 7739 | On the 386, immediates, displacements, and data pointers are all in |
| 7740 | the same (little-endian) format, so we don't need to care about which |
| 7741 | we are handling. */ |
| 7742 | |
| 7743 | void |
| 7744 | md_apply_fix (fixP, valP, seg) |
| 7745 | /* The fix we're to put in. */ |
| 7746 | fixS *fixP; |
| 7747 | /* Pointer to the value of the bits. */ |
| 7748 | valueT *valP; |
| 7749 | /* Segment fix is from. */ |
| 7750 | segT seg ATTRIBUTE_UNUSED; |
| 7751 | { |
| 7752 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
| 7753 | valueT value = *valP; |
| 7754 | |
| 7755 | #if !defined (TE_Mach) |
| 7756 | if (fixP->fx_pcrel) |
| 7757 | { |
| 7758 | switch (fixP->fx_r_type) |
| 7759 | { |
| 7760 | default: |
| 7761 | break; |
| 7762 | |
| 7763 | case BFD_RELOC_64: |
| 7764 | fixP->fx_r_type = BFD_RELOC_64_PCREL; |
| 7765 | break; |
| 7766 | case BFD_RELOC_32: |
| 7767 | case BFD_RELOC_X86_64_32S: |
| 7768 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
| 7769 | break; |
| 7770 | case BFD_RELOC_16: |
| 7771 | fixP->fx_r_type = BFD_RELOC_16_PCREL; |
| 7772 | break; |
| 7773 | case BFD_RELOC_8: |
| 7774 | fixP->fx_r_type = BFD_RELOC_8_PCREL; |
| 7775 | break; |
| 7776 | } |
| 7777 | } |
| 7778 | |
| 7779 | if (fixP->fx_addsy != NULL |
| 7780 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
| 7781 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
| 7782 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
| 7783 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
| 7784 | && !use_rela_relocations) |
| 7785 | { |
| 7786 | /* This is a hack. There should be a better way to handle this. |
| 7787 | This covers for the fact that bfd_install_relocation will |
| 7788 | subtract the current location (for partial_inplace, PC relative |
| 7789 | relocations); see more below. */ |
| 7790 | #ifndef OBJ_AOUT |
| 7791 | if (IS_ELF |
| 7792 | #ifdef TE_PE |
| 7793 | || OUTPUT_FLAVOR == bfd_target_coff_flavour |
| 7794 | #endif |
| 7795 | ) |
| 7796 | value += fixP->fx_where + fixP->fx_frag->fr_address; |
| 7797 | #endif |
| 7798 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 7799 | if (IS_ELF) |
| 7800 | { |
| 7801 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
| 7802 | |
| 7803 | if ((sym_seg == seg |
| 7804 | || (symbol_section_p (fixP->fx_addsy) |
| 7805 | && sym_seg != absolute_section)) |
| 7806 | && !generic_force_reloc (fixP)) |
| 7807 | { |
| 7808 | /* Yes, we add the values in twice. This is because |
| 7809 | bfd_install_relocation subtracts them out again. I think |
| 7810 | bfd_install_relocation is broken, but I don't dare change |
| 7811 | it. FIXME. */ |
| 7812 | value += fixP->fx_where + fixP->fx_frag->fr_address; |
| 7813 | } |
| 7814 | } |
| 7815 | #endif |
| 7816 | #if defined (OBJ_COFF) && defined (TE_PE) |
| 7817 | /* For some reason, the PE format does not store a |
| 7818 | section address offset for a PC relative symbol. */ |
| 7819 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg |
| 7820 | || S_IS_WEAK (fixP->fx_addsy)) |
| 7821 | value += md_pcrel_from (fixP); |
| 7822 | #endif |
| 7823 | } |
| 7824 | #if defined (OBJ_COFF) && defined (TE_PE) |
| 7825 | if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) |
| 7826 | { |
| 7827 | value -= S_GET_VALUE (fixP->fx_addsy); |
| 7828 | } |
| 7829 | #endif |
| 7830 | |
| 7831 | /* Fix a few things - the dynamic linker expects certain values here, |
| 7832 | and we must not disappoint it. */ |
| 7833 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 7834 | if (IS_ELF && fixP->fx_addsy) |
| 7835 | switch (fixP->fx_r_type) |
| 7836 | { |
| 7837 | case BFD_RELOC_386_PLT32: |
| 7838 | case BFD_RELOC_X86_64_PLT32: |
| 7839 | /* Make the jump instruction point to the address of the operand. At |
| 7840 | runtime we merely add the offset to the actual PLT entry. */ |
| 7841 | value = -4; |
| 7842 | break; |
| 7843 | |
| 7844 | case BFD_RELOC_386_TLS_GD: |
| 7845 | case BFD_RELOC_386_TLS_LDM: |
| 7846 | case BFD_RELOC_386_TLS_IE_32: |
| 7847 | case BFD_RELOC_386_TLS_IE: |
| 7848 | case BFD_RELOC_386_TLS_GOTIE: |
| 7849 | case BFD_RELOC_386_TLS_GOTDESC: |
| 7850 | case BFD_RELOC_X86_64_TLSGD: |
| 7851 | case BFD_RELOC_X86_64_TLSLD: |
| 7852 | case BFD_RELOC_X86_64_GOTTPOFF: |
| 7853 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
| 7854 | value = 0; /* Fully resolved at runtime. No addend. */ |
| 7855 | /* Fallthrough */ |
| 7856 | case BFD_RELOC_386_TLS_LE: |
| 7857 | case BFD_RELOC_386_TLS_LDO_32: |
| 7858 | case BFD_RELOC_386_TLS_LE_32: |
| 7859 | case BFD_RELOC_X86_64_DTPOFF32: |
| 7860 | case BFD_RELOC_X86_64_DTPOFF64: |
| 7861 | case BFD_RELOC_X86_64_TPOFF32: |
| 7862 | case BFD_RELOC_X86_64_TPOFF64: |
| 7863 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
| 7864 | break; |
| 7865 | |
| 7866 | case BFD_RELOC_386_TLS_DESC_CALL: |
| 7867 | case BFD_RELOC_X86_64_TLSDESC_CALL: |
| 7868 | value = 0; /* Fully resolved at runtime. No addend. */ |
| 7869 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
| 7870 | fixP->fx_done = 0; |
| 7871 | return; |
| 7872 | |
| 7873 | case BFD_RELOC_386_GOT32: |
| 7874 | case BFD_RELOC_X86_64_GOT32: |
| 7875 | value = 0; /* Fully resolved at runtime. No addend. */ |
| 7876 | break; |
| 7877 | |
| 7878 | case BFD_RELOC_VTABLE_INHERIT: |
| 7879 | case BFD_RELOC_VTABLE_ENTRY: |
| 7880 | fixP->fx_done = 0; |
| 7881 | return; |
| 7882 | |
| 7883 | default: |
| 7884 | break; |
| 7885 | } |
| 7886 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ |
| 7887 | *valP = value; |
| 7888 | #endif /* !defined (TE_Mach) */ |
| 7889 | |
| 7890 | /* Are we finished with this relocation now? */ |
| 7891 | if (fixP->fx_addsy == NULL) |
| 7892 | fixP->fx_done = 1; |
| 7893 | #if defined (OBJ_COFF) && defined (TE_PE) |
| 7894 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) |
| 7895 | { |
| 7896 | fixP->fx_done = 0; |
| 7897 | /* Remember value for tc_gen_reloc. */ |
| 7898 | fixP->fx_addnumber = value; |
| 7899 | /* Clear out the frag for now. */ |
| 7900 | value = 0; |
| 7901 | } |
| 7902 | #endif |
| 7903 | else if (use_rela_relocations) |
| 7904 | { |
| 7905 | fixP->fx_no_overflow = 1; |
| 7906 | /* Remember value for tc_gen_reloc. */ |
| 7907 | fixP->fx_addnumber = value; |
| 7908 | value = 0; |
| 7909 | } |
| 7910 | |
| 7911 | md_number_to_chars (p, value, fixP->fx_size); |
| 7912 | } |
| 7913 | \f |
| 7914 | char * |
| 7915 | md_atof (int type, char *litP, int *sizeP) |
| 7916 | { |
| 7917 | /* This outputs the LITTLENUMs in REVERSE order; |
| 7918 | in accord with the bigendian 386. */ |
| 7919 | return ieee_md_atof (type, litP, sizeP, FALSE); |
| 7920 | } |
| 7921 | \f |
| 7922 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
| 7923 | |
| 7924 | static char * |
| 7925 | output_invalid (int c) |
| 7926 | { |
| 7927 | if (ISPRINT (c)) |
| 7928 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
| 7929 | "'%c'", c); |
| 7930 | else |
| 7931 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
| 7932 | "(0x%x)", (unsigned char) c); |
| 7933 | return output_invalid_buf; |
| 7934 | } |
| 7935 | |
| 7936 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
| 7937 | |
| 7938 | static const reg_entry * |
| 7939 | parse_real_register (char *reg_string, char **end_op) |
| 7940 | { |
| 7941 | char *s = reg_string; |
| 7942 | char *p; |
| 7943 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
| 7944 | const reg_entry *r; |
| 7945 | |
| 7946 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ |
| 7947 | if (*s == REGISTER_PREFIX) |
| 7948 | ++s; |
| 7949 | |
| 7950 | if (is_space_char (*s)) |
| 7951 | ++s; |
| 7952 | |
| 7953 | p = reg_name_given; |
| 7954 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
| 7955 | { |
| 7956 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) |
| 7957 | return (const reg_entry *) NULL; |
| 7958 | s++; |
| 7959 | } |
| 7960 | |
| 7961 | /* For naked regs, make sure that we are not dealing with an identifier. |
| 7962 | This prevents confusing an identifier like `eax_var' with register |
| 7963 | `eax'. */ |
| 7964 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) |
| 7965 | return (const reg_entry *) NULL; |
| 7966 | |
| 7967 | *end_op = s; |
| 7968 | |
| 7969 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); |
| 7970 | |
| 7971 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
| 7972 | if (r == i386_regtab /* %st is first entry of table */) |
| 7973 | { |
| 7974 | if (is_space_char (*s)) |
| 7975 | ++s; |
| 7976 | if (*s == '(') |
| 7977 | { |
| 7978 | ++s; |
| 7979 | if (is_space_char (*s)) |
| 7980 | ++s; |
| 7981 | if (*s >= '0' && *s <= '7') |
| 7982 | { |
| 7983 | int fpr = *s - '0'; |
| 7984 | ++s; |
| 7985 | if (is_space_char (*s)) |
| 7986 | ++s; |
| 7987 | if (*s == ')') |
| 7988 | { |
| 7989 | *end_op = s + 1; |
| 7990 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
| 7991 | know (r); |
| 7992 | return r + fpr; |
| 7993 | } |
| 7994 | } |
| 7995 | /* We have "%st(" then garbage. */ |
| 7996 | return (const reg_entry *) NULL; |
| 7997 | } |
| 7998 | } |
| 7999 | |
| 8000 | if (r == NULL || allow_pseudo_reg) |
| 8001 | return r; |
| 8002 | |
| 8003 | if (operand_type_all_zero (&r->reg_type)) |
| 8004 | return (const reg_entry *) NULL; |
| 8005 | |
| 8006 | if ((r->reg_type.bitfield.reg32 |
| 8007 | || r->reg_type.bitfield.sreg3 |
| 8008 | || r->reg_type.bitfield.control |
| 8009 | || r->reg_type.bitfield.debug |
| 8010 | || r->reg_type.bitfield.test) |
| 8011 | && !cpu_arch_flags.bitfield.cpui386) |
| 8012 | return (const reg_entry *) NULL; |
| 8013 | |
| 8014 | if (r->reg_type.bitfield.floatreg |
| 8015 | && !cpu_arch_flags.bitfield.cpu8087 |
| 8016 | && !cpu_arch_flags.bitfield.cpu287 |
| 8017 | && !cpu_arch_flags.bitfield.cpu387) |
| 8018 | return (const reg_entry *) NULL; |
| 8019 | |
| 8020 | if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx) |
| 8021 | return (const reg_entry *) NULL; |
| 8022 | |
| 8023 | if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse) |
| 8024 | return (const reg_entry *) NULL; |
| 8025 | |
| 8026 | if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx) |
| 8027 | return (const reg_entry *) NULL; |
| 8028 | |
| 8029 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
| 8030 | if (!allow_index_reg |
| 8031 | && (r->reg_num == RegEiz || r->reg_num == RegRiz)) |
| 8032 | return (const reg_entry *) NULL; |
| 8033 | |
| 8034 | if (((r->reg_flags & (RegRex64 | RegRex)) |
| 8035 | || r->reg_type.bitfield.reg64) |
| 8036 | && (!cpu_arch_flags.bitfield.cpulm |
| 8037 | || !operand_type_equal (&r->reg_type, &control)) |
| 8038 | && flag_code != CODE_64BIT) |
| 8039 | return (const reg_entry *) NULL; |
| 8040 | |
| 8041 | if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) |
| 8042 | return (const reg_entry *) NULL; |
| 8043 | |
| 8044 | return r; |
| 8045 | } |
| 8046 | |
| 8047 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
| 8048 | |
| 8049 | static const reg_entry * |
| 8050 | parse_register (char *reg_string, char **end_op) |
| 8051 | { |
| 8052 | const reg_entry *r; |
| 8053 | |
| 8054 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) |
| 8055 | r = parse_real_register (reg_string, end_op); |
| 8056 | else |
| 8057 | r = NULL; |
| 8058 | if (!r) |
| 8059 | { |
| 8060 | char *save = input_line_pointer; |
| 8061 | char c; |
| 8062 | symbolS *symbolP; |
| 8063 | |
| 8064 | input_line_pointer = reg_string; |
| 8065 | c = get_symbol_end (); |
| 8066 | symbolP = symbol_find (reg_string); |
| 8067 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) |
| 8068 | { |
| 8069 | const expressionS *e = symbol_get_value_expression (symbolP); |
| 8070 | |
| 8071 | know (e->X_op == O_register); |
| 8072 | know (e->X_add_number >= 0 |
| 8073 | && (valueT) e->X_add_number < i386_regtab_size); |
| 8074 | r = i386_regtab + e->X_add_number; |
| 8075 | *end_op = input_line_pointer; |
| 8076 | } |
| 8077 | *input_line_pointer = c; |
| 8078 | input_line_pointer = save; |
| 8079 | } |
| 8080 | return r; |
| 8081 | } |
| 8082 | |
| 8083 | int |
| 8084 | i386_parse_name (char *name, expressionS *e, char *nextcharP) |
| 8085 | { |
| 8086 | const reg_entry *r; |
| 8087 | char *end = input_line_pointer; |
| 8088 | |
| 8089 | *end = *nextcharP; |
| 8090 | r = parse_register (name, &input_line_pointer); |
| 8091 | if (r && end <= input_line_pointer) |
| 8092 | { |
| 8093 | *nextcharP = *input_line_pointer; |
| 8094 | *input_line_pointer = 0; |
| 8095 | e->X_op = O_register; |
| 8096 | e->X_add_number = r - i386_regtab; |
| 8097 | return 1; |
| 8098 | } |
| 8099 | input_line_pointer = end; |
| 8100 | *end = 0; |
| 8101 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
| 8102 | } |
| 8103 | |
| 8104 | void |
| 8105 | md_operand (expressionS *e) |
| 8106 | { |
| 8107 | char *end; |
| 8108 | const reg_entry *r; |
| 8109 | |
| 8110 | switch (*input_line_pointer) |
| 8111 | { |
| 8112 | case REGISTER_PREFIX: |
| 8113 | r = parse_real_register (input_line_pointer, &end); |
| 8114 | if (r) |
| 8115 | { |
| 8116 | e->X_op = O_register; |
| 8117 | e->X_add_number = r - i386_regtab; |
| 8118 | input_line_pointer = end; |
| 8119 | } |
| 8120 | break; |
| 8121 | |
| 8122 | case '[': |
| 8123 | gas_assert (intel_syntax); |
| 8124 | end = input_line_pointer++; |
| 8125 | expression (e); |
| 8126 | if (*input_line_pointer == ']') |
| 8127 | { |
| 8128 | ++input_line_pointer; |
| 8129 | e->X_op_symbol = make_expr_symbol (e); |
| 8130 | e->X_add_symbol = NULL; |
| 8131 | e->X_add_number = 0; |
| 8132 | e->X_op = O_index; |
| 8133 | } |
| 8134 | else |
| 8135 | { |
| 8136 | e->X_op = O_absent; |
| 8137 | input_line_pointer = end; |
| 8138 | } |
| 8139 | break; |
| 8140 | } |
| 8141 | } |
| 8142 | |
| 8143 | \f |
| 8144 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 8145 | const char *md_shortopts = "kVQ:sqn"; |
| 8146 | #else |
| 8147 | const char *md_shortopts = "qn"; |
| 8148 | #endif |
| 8149 | |
| 8150 | #define OPTION_32 (OPTION_MD_BASE + 0) |
| 8151 | #define OPTION_64 (OPTION_MD_BASE + 1) |
| 8152 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) |
| 8153 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
| 8154 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) |
| 8155 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
| 8156 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) |
| 8157 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) |
| 8158 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) |
| 8159 | #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9) |
| 8160 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
| 8161 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
| 8162 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12) |
| 8163 | #define OPTION_X32 (OPTION_MD_BASE + 13) |
| 8164 | |
| 8165 | struct option md_longopts[] = |
| 8166 | { |
| 8167 | {"32", no_argument, NULL, OPTION_32}, |
| 8168 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
| 8169 | || defined (TE_PE) || defined (TE_PEP)) |
| 8170 | {"64", no_argument, NULL, OPTION_64}, |
| 8171 | #endif |
| 8172 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 8173 | {"x32", no_argument, NULL, OPTION_X32}, |
| 8174 | #endif |
| 8175 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
| 8176 | {"march", required_argument, NULL, OPTION_MARCH}, |
| 8177 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
| 8178 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
| 8179 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, |
| 8180 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, |
| 8181 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, |
| 8182 | {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC}, |
| 8183 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
| 8184 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
| 8185 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
| 8186 | {NULL, no_argument, NULL, 0} |
| 8187 | }; |
| 8188 | size_t md_longopts_size = sizeof (md_longopts); |
| 8189 | |
| 8190 | int |
| 8191 | md_parse_option (int c, char *arg) |
| 8192 | { |
| 8193 | unsigned int j; |
| 8194 | char *arch, *next; |
| 8195 | |
| 8196 | switch (c) |
| 8197 | { |
| 8198 | case 'n': |
| 8199 | optimize_align_code = 0; |
| 8200 | break; |
| 8201 | |
| 8202 | case 'q': |
| 8203 | quiet_warnings = 1; |
| 8204 | break; |
| 8205 | |
| 8206 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 8207 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
| 8208 | should be emitted or not. FIXME: Not implemented. */ |
| 8209 | case 'Q': |
| 8210 | break; |
| 8211 | |
| 8212 | /* -V: SVR4 argument to print version ID. */ |
| 8213 | case 'V': |
| 8214 | print_version_id (); |
| 8215 | break; |
| 8216 | |
| 8217 | /* -k: Ignore for FreeBSD compatibility. */ |
| 8218 | case 'k': |
| 8219 | break; |
| 8220 | |
| 8221 | case 's': |
| 8222 | /* -s: On i386 Solaris, this tells the native assembler to use |
| 8223 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
| 8224 | break; |
| 8225 | #endif |
| 8226 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
| 8227 | || defined (TE_PE) || defined (TE_PEP)) |
| 8228 | case OPTION_64: |
| 8229 | { |
| 8230 | const char **list, **l; |
| 8231 | |
| 8232 | list = bfd_target_list (); |
| 8233 | for (l = list; *l != NULL; l++) |
| 8234 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
| 8235 | || strcmp (*l, "coff-x86-64") == 0 |
| 8236 | || strcmp (*l, "pe-x86-64") == 0 |
| 8237 | || strcmp (*l, "pei-x86-64") == 0) |
| 8238 | { |
| 8239 | default_arch = "x86_64"; |
| 8240 | break; |
| 8241 | } |
| 8242 | if (*l == NULL) |
| 8243 | as_fatal (_("No compiled in support for x86_64")); |
| 8244 | free (list); |
| 8245 | } |
| 8246 | break; |
| 8247 | #endif |
| 8248 | |
| 8249 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 8250 | case OPTION_X32: |
| 8251 | if (IS_ELF) |
| 8252 | { |
| 8253 | const char **list, **l; |
| 8254 | |
| 8255 | list = bfd_target_list (); |
| 8256 | for (l = list; *l != NULL; l++) |
| 8257 | if (CONST_STRNEQ (*l, "elf32-x86-64")) |
| 8258 | { |
| 8259 | default_arch = "x86_64:32"; |
| 8260 | break; |
| 8261 | } |
| 8262 | if (*l == NULL) |
| 8263 | as_fatal (_("No compiled in support for 32bit x86_64")); |
| 8264 | free (list); |
| 8265 | } |
| 8266 | else |
| 8267 | as_fatal (_("32bit x86_64 is only supported for ELF")); |
| 8268 | break; |
| 8269 | #endif |
| 8270 | |
| 8271 | case OPTION_32: |
| 8272 | default_arch = "i386"; |
| 8273 | break; |
| 8274 | |
| 8275 | case OPTION_DIVIDE: |
| 8276 | #ifdef SVR4_COMMENT_CHARS |
| 8277 | { |
| 8278 | char *n, *t; |
| 8279 | const char *s; |
| 8280 | |
| 8281 | n = (char *) xmalloc (strlen (i386_comment_chars) + 1); |
| 8282 | t = n; |
| 8283 | for (s = i386_comment_chars; *s != '\0'; s++) |
| 8284 | if (*s != '/') |
| 8285 | *t++ = *s; |
| 8286 | *t = '\0'; |
| 8287 | i386_comment_chars = n; |
| 8288 | } |
| 8289 | #endif |
| 8290 | break; |
| 8291 | |
| 8292 | case OPTION_MARCH: |
| 8293 | arch = xstrdup (arg); |
| 8294 | do |
| 8295 | { |
| 8296 | if (*arch == '.') |
| 8297 | as_fatal (_("Invalid -march= option: `%s'"), arg); |
| 8298 | next = strchr (arch, '+'); |
| 8299 | if (next) |
| 8300 | *next++ = '\0'; |
| 8301 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
| 8302 | { |
| 8303 | if (strcmp (arch, cpu_arch [j].name) == 0) |
| 8304 | { |
| 8305 | /* Processor. */ |
| 8306 | if (! cpu_arch[j].flags.bitfield.cpui386) |
| 8307 | continue; |
| 8308 | |
| 8309 | cpu_arch_name = cpu_arch[j].name; |
| 8310 | cpu_sub_arch_name = NULL; |
| 8311 | cpu_arch_flags = cpu_arch[j].flags; |
| 8312 | cpu_arch_isa = cpu_arch[j].type; |
| 8313 | cpu_arch_isa_flags = cpu_arch[j].flags; |
| 8314 | if (!cpu_arch_tune_set) |
| 8315 | { |
| 8316 | cpu_arch_tune = cpu_arch_isa; |
| 8317 | cpu_arch_tune_flags = cpu_arch_isa_flags; |
| 8318 | } |
| 8319 | break; |
| 8320 | } |
| 8321 | else if (*cpu_arch [j].name == '.' |
| 8322 | && strcmp (arch, cpu_arch [j].name + 1) == 0) |
| 8323 | { |
| 8324 | /* ISA entension. */ |
| 8325 | i386_cpu_flags flags; |
| 8326 | |
| 8327 | if (!cpu_arch[j].negated) |
| 8328 | flags = cpu_flags_or (cpu_arch_flags, |
| 8329 | cpu_arch[j].flags); |
| 8330 | else |
| 8331 | flags = cpu_flags_and_not (cpu_arch_flags, |
| 8332 | cpu_arch[j].flags); |
| 8333 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
| 8334 | { |
| 8335 | if (cpu_sub_arch_name) |
| 8336 | { |
| 8337 | char *name = cpu_sub_arch_name; |
| 8338 | cpu_sub_arch_name = concat (name, |
| 8339 | cpu_arch[j].name, |
| 8340 | (const char *) NULL); |
| 8341 | free (name); |
| 8342 | } |
| 8343 | else |
| 8344 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
| 8345 | cpu_arch_flags = flags; |
| 8346 | } |
| 8347 | break; |
| 8348 | } |
| 8349 | } |
| 8350 | |
| 8351 | if (j >= ARRAY_SIZE (cpu_arch)) |
| 8352 | as_fatal (_("Invalid -march= option: `%s'"), arg); |
| 8353 | |
| 8354 | arch = next; |
| 8355 | } |
| 8356 | while (next != NULL ); |
| 8357 | break; |
| 8358 | |
| 8359 | case OPTION_MTUNE: |
| 8360 | if (*arg == '.') |
| 8361 | as_fatal (_("Invalid -mtune= option: `%s'"), arg); |
| 8362 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
| 8363 | { |
| 8364 | if (strcmp (arg, cpu_arch [j].name) == 0) |
| 8365 | { |
| 8366 | cpu_arch_tune_set = 1; |
| 8367 | cpu_arch_tune = cpu_arch [j].type; |
| 8368 | cpu_arch_tune_flags = cpu_arch[j].flags; |
| 8369 | break; |
| 8370 | } |
| 8371 | } |
| 8372 | if (j >= ARRAY_SIZE (cpu_arch)) |
| 8373 | as_fatal (_("Invalid -mtune= option: `%s'"), arg); |
| 8374 | break; |
| 8375 | |
| 8376 | case OPTION_MMNEMONIC: |
| 8377 | if (strcasecmp (arg, "att") == 0) |
| 8378 | intel_mnemonic = 0; |
| 8379 | else if (strcasecmp (arg, "intel") == 0) |
| 8380 | intel_mnemonic = 1; |
| 8381 | else |
| 8382 | as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg); |
| 8383 | break; |
| 8384 | |
| 8385 | case OPTION_MSYNTAX: |
| 8386 | if (strcasecmp (arg, "att") == 0) |
| 8387 | intel_syntax = 0; |
| 8388 | else if (strcasecmp (arg, "intel") == 0) |
| 8389 | intel_syntax = 1; |
| 8390 | else |
| 8391 | as_fatal (_("Invalid -msyntax= option: `%s'"), arg); |
| 8392 | break; |
| 8393 | |
| 8394 | case OPTION_MINDEX_REG: |
| 8395 | allow_index_reg = 1; |
| 8396 | break; |
| 8397 | |
| 8398 | case OPTION_MNAKED_REG: |
| 8399 | allow_naked_reg = 1; |
| 8400 | break; |
| 8401 | |
| 8402 | case OPTION_MOLD_GCC: |
| 8403 | old_gcc = 1; |
| 8404 | break; |
| 8405 | |
| 8406 | case OPTION_MSSE2AVX: |
| 8407 | sse2avx = 1; |
| 8408 | break; |
| 8409 | |
| 8410 | case OPTION_MSSE_CHECK: |
| 8411 | if (strcasecmp (arg, "error") == 0) |
| 8412 | sse_check = sse_check_error; |
| 8413 | else if (strcasecmp (arg, "warning") == 0) |
| 8414 | sse_check = sse_check_warning; |
| 8415 | else if (strcasecmp (arg, "none") == 0) |
| 8416 | sse_check = sse_check_none; |
| 8417 | else |
| 8418 | as_fatal (_("Invalid -msse-check= option: `%s'"), arg); |
| 8419 | break; |
| 8420 | |
| 8421 | case OPTION_MAVXSCALAR: |
| 8422 | if (strcasecmp (arg, "128") == 0) |
| 8423 | avxscalar = vex128; |
| 8424 | else if (strcasecmp (arg, "256") == 0) |
| 8425 | avxscalar = vex256; |
| 8426 | else |
| 8427 | as_fatal (_("Invalid -mavxscalar= option: `%s'"), arg); |
| 8428 | break; |
| 8429 | |
| 8430 | default: |
| 8431 | return 0; |
| 8432 | } |
| 8433 | return 1; |
| 8434 | } |
| 8435 | |
| 8436 | #define MESSAGE_TEMPLATE \ |
| 8437 | " " |
| 8438 | |
| 8439 | static void |
| 8440 | show_arch (FILE *stream, int ext, int check) |
| 8441 | { |
| 8442 | static char message[] = MESSAGE_TEMPLATE; |
| 8443 | char *start = message + 27; |
| 8444 | char *p; |
| 8445 | int size = sizeof (MESSAGE_TEMPLATE); |
| 8446 | int left; |
| 8447 | const char *name; |
| 8448 | int len; |
| 8449 | unsigned int j; |
| 8450 | |
| 8451 | p = start; |
| 8452 | left = size - (start - message); |
| 8453 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
| 8454 | { |
| 8455 | /* Should it be skipped? */ |
| 8456 | if (cpu_arch [j].skip) |
| 8457 | continue; |
| 8458 | |
| 8459 | name = cpu_arch [j].name; |
| 8460 | len = cpu_arch [j].len; |
| 8461 | if (*name == '.') |
| 8462 | { |
| 8463 | /* It is an extension. Skip if we aren't asked to show it. */ |
| 8464 | if (ext) |
| 8465 | { |
| 8466 | name++; |
| 8467 | len--; |
| 8468 | } |
| 8469 | else |
| 8470 | continue; |
| 8471 | } |
| 8472 | else if (ext) |
| 8473 | { |
| 8474 | /* It is an processor. Skip if we show only extension. */ |
| 8475 | continue; |
| 8476 | } |
| 8477 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
| 8478 | { |
| 8479 | /* It is an impossible processor - skip. */ |
| 8480 | continue; |
| 8481 | } |
| 8482 | |
| 8483 | /* Reserve 2 spaces for ", " or ",\0" */ |
| 8484 | left -= len + 2; |
| 8485 | |
| 8486 | /* Check if there is any room. */ |
| 8487 | if (left >= 0) |
| 8488 | { |
| 8489 | if (p != start) |
| 8490 | { |
| 8491 | *p++ = ','; |
| 8492 | *p++ = ' '; |
| 8493 | } |
| 8494 | p = mempcpy (p, name, len); |
| 8495 | } |
| 8496 | else |
| 8497 | { |
| 8498 | /* Output the current message now and start a new one. */ |
| 8499 | *p++ = ','; |
| 8500 | *p = '\0'; |
| 8501 | fprintf (stream, "%s\n", message); |
| 8502 | p = start; |
| 8503 | left = size - (start - message) - len - 2; |
| 8504 | |
| 8505 | gas_assert (left >= 0); |
| 8506 | |
| 8507 | p = mempcpy (p, name, len); |
| 8508 | } |
| 8509 | } |
| 8510 | |
| 8511 | *p = '\0'; |
| 8512 | fprintf (stream, "%s\n", message); |
| 8513 | } |
| 8514 | |
| 8515 | void |
| 8516 | md_show_usage (FILE *stream) |
| 8517 | { |
| 8518 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 8519 | fprintf (stream, _("\ |
| 8520 | -Q ignored\n\ |
| 8521 | -V print assembler version number\n\ |
| 8522 | -k ignored\n")); |
| 8523 | #endif |
| 8524 | fprintf (stream, _("\ |
| 8525 | -n Do not optimize code alignment\n\ |
| 8526 | -q quieten some warnings\n")); |
| 8527 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 8528 | fprintf (stream, _("\ |
| 8529 | -s ignored\n")); |
| 8530 | #endif |
| 8531 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
| 8532 | || defined (TE_PE) || defined (TE_PEP)) |
| 8533 | fprintf (stream, _("\ |
| 8534 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
| 8535 | #endif |
| 8536 | #ifdef SVR4_COMMENT_CHARS |
| 8537 | fprintf (stream, _("\ |
| 8538 | --divide do not treat `/' as a comment character\n")); |
| 8539 | #else |
| 8540 | fprintf (stream, _("\ |
| 8541 | --divide ignored\n")); |
| 8542 | #endif |
| 8543 | fprintf (stream, _("\ |
| 8544 | -march=CPU[,+EXTENSION...]\n\ |
| 8545 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
| 8546 | show_arch (stream, 0, 1); |
| 8547 | fprintf (stream, _("\ |
| 8548 | EXTENSION is combination of:\n")); |
| 8549 | show_arch (stream, 1, 0); |
| 8550 | fprintf (stream, _("\ |
| 8551 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
| 8552 | show_arch (stream, 0, 0); |
| 8553 | fprintf (stream, _("\ |
| 8554 | -msse2avx encode SSE instructions with VEX prefix\n")); |
| 8555 | fprintf (stream, _("\ |
| 8556 | -msse-check=[none|error|warning]\n\ |
| 8557 | check SSE instructions\n")); |
| 8558 | fprintf (stream, _("\ |
| 8559 | -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\ |
| 8560 | length\n")); |
| 8561 | fprintf (stream, _("\ |
| 8562 | -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n")); |
| 8563 | fprintf (stream, _("\ |
| 8564 | -msyntax=[att|intel] use AT&T/Intel syntax\n")); |
| 8565 | fprintf (stream, _("\ |
| 8566 | -mindex-reg support pseudo index registers\n")); |
| 8567 | fprintf (stream, _("\ |
| 8568 | -mnaked-reg don't require `%%' prefix for registers\n")); |
| 8569 | fprintf (stream, _("\ |
| 8570 | -mold-gcc support old (<= 2.8.1) versions of gcc\n")); |
| 8571 | } |
| 8572 | |
| 8573 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
| 8574 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
| 8575 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
| 8576 | |
| 8577 | /* Pick the target format to use. */ |
| 8578 | |
| 8579 | const char * |
| 8580 | i386_target_format (void) |
| 8581 | { |
| 8582 | if (!strncmp (default_arch, "x86_64", 6)) |
| 8583 | { |
| 8584 | update_code_flag (CODE_64BIT, 1); |
| 8585 | if (default_arch[6] == '\0') |
| 8586 | x86_elf_abi = X86_64_ABI; |
| 8587 | else |
| 8588 | x86_elf_abi = X86_64_X32_ABI; |
| 8589 | } |
| 8590 | else if (!strcmp (default_arch, "i386")) |
| 8591 | update_code_flag (CODE_32BIT, 1); |
| 8592 | else |
| 8593 | as_fatal (_("Unknown architecture")); |
| 8594 | |
| 8595 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) |
| 8596 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; |
| 8597 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) |
| 8598 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; |
| 8599 | |
| 8600 | switch (OUTPUT_FLAVOR) |
| 8601 | { |
| 8602 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
| 8603 | case bfd_target_aout_flavour: |
| 8604 | return AOUT_TARGET_FORMAT; |
| 8605 | #endif |
| 8606 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
| 8607 | # if defined (TE_PE) || defined (TE_PEP) |
| 8608 | case bfd_target_coff_flavour: |
| 8609 | return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386"; |
| 8610 | # elif defined (TE_GO32) |
| 8611 | case bfd_target_coff_flavour: |
| 8612 | return "coff-go32"; |
| 8613 | # else |
| 8614 | case bfd_target_coff_flavour: |
| 8615 | return "coff-i386"; |
| 8616 | # endif |
| 8617 | #endif |
| 8618 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
| 8619 | case bfd_target_elf_flavour: |
| 8620 | { |
| 8621 | const char *format; |
| 8622 | |
| 8623 | switch (x86_elf_abi) |
| 8624 | { |
| 8625 | default: |
| 8626 | format = ELF_TARGET_FORMAT; |
| 8627 | break; |
| 8628 | case X86_64_ABI: |
| 8629 | use_rela_relocations = 1; |
| 8630 | object_64bit = 1; |
| 8631 | format = ELF_TARGET_FORMAT64; |
| 8632 | break; |
| 8633 | case X86_64_X32_ABI: |
| 8634 | use_rela_relocations = 1; |
| 8635 | object_64bit = 1; |
| 8636 | disallow_64bit_reloc = 1; |
| 8637 | format = ELF_TARGET_FORMAT32; |
| 8638 | break; |
| 8639 | } |
| 8640 | if (cpu_arch_isa == PROCESSOR_L1OM) |
| 8641 | { |
| 8642 | if (x86_elf_abi != X86_64_ABI) |
| 8643 | as_fatal (_("Intel L1OM is 64bit only")); |
| 8644 | return ELF_TARGET_L1OM_FORMAT; |
| 8645 | } |
| 8646 | else |
| 8647 | return format; |
| 8648 | } |
| 8649 | #endif |
| 8650 | #if defined (OBJ_MACH_O) |
| 8651 | case bfd_target_mach_o_flavour: |
| 8652 | return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386"; |
| 8653 | #endif |
| 8654 | default: |
| 8655 | abort (); |
| 8656 | return NULL; |
| 8657 | } |
| 8658 | } |
| 8659 | |
| 8660 | #endif /* OBJ_MAYBE_ more than one */ |
| 8661 | |
| 8662 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) |
| 8663 | void |
| 8664 | i386_elf_emit_arch_note (void) |
| 8665 | { |
| 8666 | if (IS_ELF && cpu_arch_name != NULL) |
| 8667 | { |
| 8668 | char *p; |
| 8669 | asection *seg = now_seg; |
| 8670 | subsegT subseg = now_subseg; |
| 8671 | Elf_Internal_Note i_note; |
| 8672 | Elf_External_Note e_note; |
| 8673 | asection *note_secp; |
| 8674 | int len; |
| 8675 | |
| 8676 | /* Create the .note section. */ |
| 8677 | note_secp = subseg_new (".note", 0); |
| 8678 | bfd_set_section_flags (stdoutput, |
| 8679 | note_secp, |
| 8680 | SEC_HAS_CONTENTS | SEC_READONLY); |
| 8681 | |
| 8682 | /* Process the arch string. */ |
| 8683 | len = strlen (cpu_arch_name); |
| 8684 | |
| 8685 | i_note.namesz = len + 1; |
| 8686 | i_note.descsz = 0; |
| 8687 | i_note.type = NT_ARCH; |
| 8688 | p = frag_more (sizeof (e_note.namesz)); |
| 8689 | md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz)); |
| 8690 | p = frag_more (sizeof (e_note.descsz)); |
| 8691 | md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz)); |
| 8692 | p = frag_more (sizeof (e_note.type)); |
| 8693 | md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type)); |
| 8694 | p = frag_more (len + 1); |
| 8695 | strcpy (p, cpu_arch_name); |
| 8696 | |
| 8697 | frag_align (2, 0, 0); |
| 8698 | |
| 8699 | subseg_set (seg, subseg); |
| 8700 | } |
| 8701 | } |
| 8702 | #endif |
| 8703 | \f |
| 8704 | symbolS * |
| 8705 | md_undefined_symbol (name) |
| 8706 | char *name; |
| 8707 | { |
| 8708 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
| 8709 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] |
| 8710 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] |
| 8711 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) |
| 8712 | { |
| 8713 | if (!GOT_symbol) |
| 8714 | { |
| 8715 | if (symbol_find (name)) |
| 8716 | as_bad (_("GOT already in symbol table")); |
| 8717 | GOT_symbol = symbol_new (name, undefined_section, |
| 8718 | (valueT) 0, &zero_address_frag); |
| 8719 | }; |
| 8720 | return GOT_symbol; |
| 8721 | } |
| 8722 | return 0; |
| 8723 | } |
| 8724 | |
| 8725 | /* Round up a section size to the appropriate boundary. */ |
| 8726 | |
| 8727 | valueT |
| 8728 | md_section_align (segment, size) |
| 8729 | segT segment ATTRIBUTE_UNUSED; |
| 8730 | valueT size; |
| 8731 | { |
| 8732 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
| 8733 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) |
| 8734 | { |
| 8735 | /* For a.out, force the section size to be aligned. If we don't do |
| 8736 | this, BFD will align it for us, but it will not write out the |
| 8737 | final bytes of the section. This may be a bug in BFD, but it is |
| 8738 | easier to fix it here since that is how the other a.out targets |
| 8739 | work. */ |
| 8740 | int align; |
| 8741 | |
| 8742 | align = bfd_get_section_alignment (stdoutput, segment); |
| 8743 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); |
| 8744 | } |
| 8745 | #endif |
| 8746 | |
| 8747 | return size; |
| 8748 | } |
| 8749 | |
| 8750 | /* On the i386, PC-relative offsets are relative to the start of the |
| 8751 | next instruction. That is, the address of the offset, plus its |
| 8752 | size, since the offset is always the last part of the insn. */ |
| 8753 | |
| 8754 | long |
| 8755 | md_pcrel_from (fixS *fixP) |
| 8756 | { |
| 8757 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; |
| 8758 | } |
| 8759 | |
| 8760 | #ifndef I386COFF |
| 8761 | |
| 8762 | static void |
| 8763 | s_bss (int ignore ATTRIBUTE_UNUSED) |
| 8764 | { |
| 8765 | int temp; |
| 8766 | |
| 8767 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 8768 | if (IS_ELF) |
| 8769 | obj_elf_section_change_hook (); |
| 8770 | #endif |
| 8771 | temp = get_absolute_expression (); |
| 8772 | subseg_set (bss_section, (subsegT) temp); |
| 8773 | demand_empty_rest_of_line (); |
| 8774 | } |
| 8775 | |
| 8776 | #endif |
| 8777 | |
| 8778 | void |
| 8779 | i386_validate_fix (fixS *fixp) |
| 8780 | { |
| 8781 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) |
| 8782 | { |
| 8783 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
| 8784 | { |
| 8785 | if (!object_64bit) |
| 8786 | abort (); |
| 8787 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; |
| 8788 | } |
| 8789 | else |
| 8790 | { |
| 8791 | if (!object_64bit) |
| 8792 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; |
| 8793 | else |
| 8794 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; |
| 8795 | } |
| 8796 | fixp->fx_subsy = 0; |
| 8797 | } |
| 8798 | } |
| 8799 | |
| 8800 | arelent * |
| 8801 | tc_gen_reloc (section, fixp) |
| 8802 | asection *section ATTRIBUTE_UNUSED; |
| 8803 | fixS *fixp; |
| 8804 | { |
| 8805 | arelent *rel; |
| 8806 | bfd_reloc_code_real_type code; |
| 8807 | |
| 8808 | switch (fixp->fx_r_type) |
| 8809 | { |
| 8810 | case BFD_RELOC_X86_64_PLT32: |
| 8811 | case BFD_RELOC_X86_64_GOT32: |
| 8812 | case BFD_RELOC_X86_64_GOTPCREL: |
| 8813 | case BFD_RELOC_386_PLT32: |
| 8814 | case BFD_RELOC_386_GOT32: |
| 8815 | case BFD_RELOC_386_GOTOFF: |
| 8816 | case BFD_RELOC_386_GOTPC: |
| 8817 | case BFD_RELOC_386_TLS_GD: |
| 8818 | case BFD_RELOC_386_TLS_LDM: |
| 8819 | case BFD_RELOC_386_TLS_LDO_32: |
| 8820 | case BFD_RELOC_386_TLS_IE_32: |
| 8821 | case BFD_RELOC_386_TLS_IE: |
| 8822 | case BFD_RELOC_386_TLS_GOTIE: |
| 8823 | case BFD_RELOC_386_TLS_LE_32: |
| 8824 | case BFD_RELOC_386_TLS_LE: |
| 8825 | case BFD_RELOC_386_TLS_GOTDESC: |
| 8826 | case BFD_RELOC_386_TLS_DESC_CALL: |
| 8827 | case BFD_RELOC_X86_64_TLSGD: |
| 8828 | case BFD_RELOC_X86_64_TLSLD: |
| 8829 | case BFD_RELOC_X86_64_DTPOFF32: |
| 8830 | case BFD_RELOC_X86_64_DTPOFF64: |
| 8831 | case BFD_RELOC_X86_64_GOTTPOFF: |
| 8832 | case BFD_RELOC_X86_64_TPOFF32: |
| 8833 | case BFD_RELOC_X86_64_TPOFF64: |
| 8834 | case BFD_RELOC_X86_64_GOTOFF64: |
| 8835 | case BFD_RELOC_X86_64_GOTPC32: |
| 8836 | case BFD_RELOC_X86_64_GOT64: |
| 8837 | case BFD_RELOC_X86_64_GOTPCREL64: |
| 8838 | case BFD_RELOC_X86_64_GOTPC64: |
| 8839 | case BFD_RELOC_X86_64_GOTPLT64: |
| 8840 | case BFD_RELOC_X86_64_PLTOFF64: |
| 8841 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
| 8842 | case BFD_RELOC_X86_64_TLSDESC_CALL: |
| 8843 | case BFD_RELOC_RVA: |
| 8844 | case BFD_RELOC_VTABLE_ENTRY: |
| 8845 | case BFD_RELOC_VTABLE_INHERIT: |
| 8846 | #ifdef TE_PE |
| 8847 | case BFD_RELOC_32_SECREL: |
| 8848 | #endif |
| 8849 | code = fixp->fx_r_type; |
| 8850 | break; |
| 8851 | case BFD_RELOC_X86_64_32S: |
| 8852 | if (!fixp->fx_pcrel) |
| 8853 | { |
| 8854 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ |
| 8855 | code = fixp->fx_r_type; |
| 8856 | break; |
| 8857 | } |
| 8858 | default: |
| 8859 | if (fixp->fx_pcrel) |
| 8860 | { |
| 8861 | switch (fixp->fx_size) |
| 8862 | { |
| 8863 | default: |
| 8864 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 8865 | _("can not do %d byte pc-relative relocation"), |
| 8866 | fixp->fx_size); |
| 8867 | code = BFD_RELOC_32_PCREL; |
| 8868 | break; |
| 8869 | case 1: code = BFD_RELOC_8_PCREL; break; |
| 8870 | case 2: code = BFD_RELOC_16_PCREL; break; |
| 8871 | case 4: code = BFD_RELOC_32_PCREL; break; |
| 8872 | #ifdef BFD64 |
| 8873 | case 8: code = BFD_RELOC_64_PCREL; break; |
| 8874 | #endif |
| 8875 | } |
| 8876 | } |
| 8877 | else |
| 8878 | { |
| 8879 | switch (fixp->fx_size) |
| 8880 | { |
| 8881 | default: |
| 8882 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 8883 | _("can not do %d byte relocation"), |
| 8884 | fixp->fx_size); |
| 8885 | code = BFD_RELOC_32; |
| 8886 | break; |
| 8887 | case 1: code = BFD_RELOC_8; break; |
| 8888 | case 2: code = BFD_RELOC_16; break; |
| 8889 | case 4: code = BFD_RELOC_32; break; |
| 8890 | #ifdef BFD64 |
| 8891 | case 8: code = BFD_RELOC_64; break; |
| 8892 | #endif |
| 8893 | } |
| 8894 | } |
| 8895 | break; |
| 8896 | } |
| 8897 | |
| 8898 | if ((code == BFD_RELOC_32 |
| 8899 | || code == BFD_RELOC_32_PCREL |
| 8900 | || code == BFD_RELOC_X86_64_32S) |
| 8901 | && GOT_symbol |
| 8902 | && fixp->fx_addsy == GOT_symbol) |
| 8903 | { |
| 8904 | if (!object_64bit) |
| 8905 | code = BFD_RELOC_386_GOTPC; |
| 8906 | else |
| 8907 | code = BFD_RELOC_X86_64_GOTPC32; |
| 8908 | } |
| 8909 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
| 8910 | && GOT_symbol |
| 8911 | && fixp->fx_addsy == GOT_symbol) |
| 8912 | { |
| 8913 | code = BFD_RELOC_X86_64_GOTPC64; |
| 8914 | } |
| 8915 | |
| 8916 | rel = (arelent *) xmalloc (sizeof (arelent)); |
| 8917 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
| 8918 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
| 8919 | |
| 8920 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; |
| 8921 | |
| 8922 | if (!use_rela_relocations) |
| 8923 | { |
| 8924 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the |
| 8925 | vtable entry to be used in the relocation's section offset. */ |
| 8926 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
| 8927 | rel->address = fixp->fx_offset; |
| 8928 | #if defined (OBJ_COFF) && defined (TE_PE) |
| 8929 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) |
| 8930 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); |
| 8931 | else |
| 8932 | #endif |
| 8933 | rel->addend = 0; |
| 8934 | } |
| 8935 | /* Use the rela in 64bit mode. */ |
| 8936 | else |
| 8937 | { |
| 8938 | if (disallow_64bit_reloc) |
| 8939 | switch (code) |
| 8940 | { |
| 8941 | case BFD_RELOC_64: |
| 8942 | case BFD_RELOC_X86_64_DTPOFF64: |
| 8943 | case BFD_RELOC_X86_64_TPOFF64: |
| 8944 | case BFD_RELOC_64_PCREL: |
| 8945 | case BFD_RELOC_X86_64_GOTOFF64: |
| 8946 | case BFD_RELOC_X86_64_GOT64: |
| 8947 | case BFD_RELOC_X86_64_GOTPCREL64: |
| 8948 | case BFD_RELOC_X86_64_GOTPC64: |
| 8949 | case BFD_RELOC_X86_64_GOTPLT64: |
| 8950 | case BFD_RELOC_X86_64_PLTOFF64: |
| 8951 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 8952 | _("cannot represent relocation type %s in x32 mode"), |
| 8953 | bfd_get_reloc_code_name (code)); |
| 8954 | break; |
| 8955 | default: |
| 8956 | break; |
| 8957 | } |
| 8958 | |
| 8959 | if (!fixp->fx_pcrel) |
| 8960 | rel->addend = fixp->fx_offset; |
| 8961 | else |
| 8962 | switch (code) |
| 8963 | { |
| 8964 | case BFD_RELOC_X86_64_PLT32: |
| 8965 | case BFD_RELOC_X86_64_GOT32: |
| 8966 | case BFD_RELOC_X86_64_GOTPCREL: |
| 8967 | case BFD_RELOC_X86_64_TLSGD: |
| 8968 | case BFD_RELOC_X86_64_TLSLD: |
| 8969 | case BFD_RELOC_X86_64_GOTTPOFF: |
| 8970 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
| 8971 | case BFD_RELOC_X86_64_TLSDESC_CALL: |
| 8972 | rel->addend = fixp->fx_offset - fixp->fx_size; |
| 8973 | break; |
| 8974 | default: |
| 8975 | rel->addend = (section->vma |
| 8976 | - fixp->fx_size |
| 8977 | + fixp->fx_addnumber |
| 8978 | + md_pcrel_from (fixp)); |
| 8979 | break; |
| 8980 | } |
| 8981 | } |
| 8982 | |
| 8983 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
| 8984 | if (rel->howto == NULL) |
| 8985 | { |
| 8986 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 8987 | _("cannot represent relocation type %s"), |
| 8988 | bfd_get_reloc_code_name (code)); |
| 8989 | /* Set howto to a garbage value so that we can keep going. */ |
| 8990 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); |
| 8991 | gas_assert (rel->howto != NULL); |
| 8992 | } |
| 8993 | |
| 8994 | return rel; |
| 8995 | } |
| 8996 | |
| 8997 | #include "tc-i386-intel.c" |
| 8998 | |
| 8999 | void |
| 9000 | tc_x86_parse_to_dw2regnum (expressionS *exp) |
| 9001 | { |
| 9002 | int saved_naked_reg; |
| 9003 | char saved_register_dot; |
| 9004 | |
| 9005 | saved_naked_reg = allow_naked_reg; |
| 9006 | allow_naked_reg = 1; |
| 9007 | saved_register_dot = register_chars['.']; |
| 9008 | register_chars['.'] = '.'; |
| 9009 | allow_pseudo_reg = 1; |
| 9010 | expression_and_evaluate (exp); |
| 9011 | allow_pseudo_reg = 0; |
| 9012 | register_chars['.'] = saved_register_dot; |
| 9013 | allow_naked_reg = saved_naked_reg; |
| 9014 | |
| 9015 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
| 9016 | { |
| 9017 | if ((addressT) exp->X_add_number < i386_regtab_size) |
| 9018 | { |
| 9019 | exp->X_op = O_constant; |
| 9020 | exp->X_add_number = i386_regtab[exp->X_add_number] |
| 9021 | .dw2_regnum[flag_code >> 1]; |
| 9022 | } |
| 9023 | else |
| 9024 | exp->X_op = O_illegal; |
| 9025 | } |
| 9026 | } |
| 9027 | |
| 9028 | void |
| 9029 | tc_x86_frame_initial_instructions (void) |
| 9030 | { |
| 9031 | static unsigned int sp_regno[2]; |
| 9032 | |
| 9033 | if (!sp_regno[flag_code >> 1]) |
| 9034 | { |
| 9035 | char *saved_input = input_line_pointer; |
| 9036 | char sp[][4] = {"esp", "rsp"}; |
| 9037 | expressionS exp; |
| 9038 | |
| 9039 | input_line_pointer = sp[flag_code >> 1]; |
| 9040 | tc_x86_parse_to_dw2regnum (&exp); |
| 9041 | gas_assert (exp.X_op == O_constant); |
| 9042 | sp_regno[flag_code >> 1] = exp.X_add_number; |
| 9043 | input_line_pointer = saved_input; |
| 9044 | } |
| 9045 | |
| 9046 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
| 9047 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); |
| 9048 | } |
| 9049 | |
| 9050 | int |
| 9051 | i386_elf_section_type (const char *str, size_t len) |
| 9052 | { |
| 9053 | if (flag_code == CODE_64BIT |
| 9054 | && len == sizeof ("unwind") - 1 |
| 9055 | && strncmp (str, "unwind", 6) == 0) |
| 9056 | return SHT_X86_64_UNWIND; |
| 9057 | |
| 9058 | return -1; |
| 9059 | } |
| 9060 | |
| 9061 | #ifdef TE_SOLARIS |
| 9062 | void |
| 9063 | i386_solaris_fix_up_eh_frame (segT sec) |
| 9064 | { |
| 9065 | if (flag_code == CODE_64BIT) |
| 9066 | elf_section_type (sec) = SHT_X86_64_UNWIND; |
| 9067 | } |
| 9068 | #endif |
| 9069 | |
| 9070 | #ifdef TE_PE |
| 9071 | void |
| 9072 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) |
| 9073 | { |
| 9074 | expressionS exp; |
| 9075 | |
| 9076 | exp.X_op = O_secrel; |
| 9077 | exp.X_add_symbol = symbol; |
| 9078 | exp.X_add_number = 0; |
| 9079 | emit_expr (&exp, size); |
| 9080 | } |
| 9081 | #endif |
| 9082 | |
| 9083 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 9084 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ |
| 9085 | |
| 9086 | bfd_vma |
| 9087 | x86_64_section_letter (int letter, char **ptr_msg) |
| 9088 | { |
| 9089 | if (flag_code == CODE_64BIT) |
| 9090 | { |
| 9091 | if (letter == 'l') |
| 9092 | return SHF_X86_64_LARGE; |
| 9093 | |
| 9094 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
| 9095 | } |
| 9096 | else |
| 9097 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
| 9098 | return -1; |
| 9099 | } |
| 9100 | |
| 9101 | bfd_vma |
| 9102 | x86_64_section_word (char *str, size_t len) |
| 9103 | { |
| 9104 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
| 9105 | return SHF_X86_64_LARGE; |
| 9106 | |
| 9107 | return -1; |
| 9108 | } |
| 9109 | |
| 9110 | static void |
| 9111 | handle_large_common (int small ATTRIBUTE_UNUSED) |
| 9112 | { |
| 9113 | if (flag_code != CODE_64BIT) |
| 9114 | { |
| 9115 | s_comm_internal (0, elf_common_parse); |
| 9116 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); |
| 9117 | } |
| 9118 | else |
| 9119 | { |
| 9120 | static segT lbss_section; |
| 9121 | asection *saved_com_section_ptr = elf_com_section_ptr; |
| 9122 | asection *saved_bss_section = bss_section; |
| 9123 | |
| 9124 | if (lbss_section == NULL) |
| 9125 | { |
| 9126 | flagword applicable; |
| 9127 | segT seg = now_seg; |
| 9128 | subsegT subseg = now_subseg; |
| 9129 | |
| 9130 | /* The .lbss section is for local .largecomm symbols. */ |
| 9131 | lbss_section = subseg_new (".lbss", 0); |
| 9132 | applicable = bfd_applicable_section_flags (stdoutput); |
| 9133 | bfd_set_section_flags (stdoutput, lbss_section, |
| 9134 | applicable & SEC_ALLOC); |
| 9135 | seg_info (lbss_section)->bss = 1; |
| 9136 | |
| 9137 | subseg_set (seg, subseg); |
| 9138 | } |
| 9139 | |
| 9140 | elf_com_section_ptr = &_bfd_elf_large_com_section; |
| 9141 | bss_section = lbss_section; |
| 9142 | |
| 9143 | s_comm_internal (0, elf_common_parse); |
| 9144 | |
| 9145 | elf_com_section_ptr = saved_com_section_ptr; |
| 9146 | bss_section = saved_bss_section; |
| 9147 | } |
| 9148 | } |
| 9149 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |