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* gdb.python/py-breakpoint.exp: Make tests have unique names.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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1/* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
4 2012
5 Free Software Foundation, Inc.
6
7 This file is part of GAS, the GNU Assembler.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
21 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
22 02110-1301, USA. */
23
24/* Intel 80386 machine specific gas.
25 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
26 x86_64 support by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
28 Bugs & suggestions are completely welcome. This is free software.
29 Please help us make it better. */
30
31#include "as.h"
32#include "safe-ctype.h"
33#include "subsegs.h"
34#include "dwarf2dbg.h"
35#include "dw2gencfi.h"
36#include "elf/x86-64.h"
37#include "opcodes/i386-init.h"
38
39#ifndef REGISTER_WARNINGS
40#define REGISTER_WARNINGS 1
41#endif
42
43#ifndef INFER_ADDR_PREFIX
44#define INFER_ADDR_PREFIX 1
45#endif
46
47#ifndef DEFAULT_ARCH
48#define DEFAULT_ARCH "i386"
49#endif
50
51#ifndef INLINE
52#if __GNUC__ >= 2
53#define INLINE __inline__
54#else
55#define INLINE
56#endif
57#endif
58
59/* Prefixes will be emitted in the order defined below.
60 WAIT_PREFIX must be the first prefix since FWAIT is really is an
61 instruction, and so must come before any prefixes.
62 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
63 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
64#define WAIT_PREFIX 0
65#define SEG_PREFIX 1
66#define ADDR_PREFIX 2
67#define DATA_PREFIX 3
68#define REP_PREFIX 4
69#define HLE_PREFIX REP_PREFIX
70#define BND_PREFIX REP_PREFIX
71#define LOCK_PREFIX 5
72#define REX_PREFIX 6 /* must come last. */
73#define MAX_PREFIXES 7 /* max prefixes per opcode */
74
75/* we define the syntax here (modulo base,index,scale syntax) */
76#define REGISTER_PREFIX '%'
77#define IMMEDIATE_PREFIX '$'
78#define ABSOLUTE_PREFIX '*'
79
80/* these are the instruction mnemonic suffixes in AT&T syntax or
81 memory operand size in Intel syntax. */
82#define WORD_MNEM_SUFFIX 'w'
83#define BYTE_MNEM_SUFFIX 'b'
84#define SHORT_MNEM_SUFFIX 's'
85#define LONG_MNEM_SUFFIX 'l'
86#define QWORD_MNEM_SUFFIX 'q'
87#define XMMWORD_MNEM_SUFFIX 'x'
88#define YMMWORD_MNEM_SUFFIX 'y'
89#define ZMMWORD_MNEM_SUFFIX 'z'
90/* Intel Syntax. Use a non-ascii letter since since it never appears
91 in instructions. */
92#define LONG_DOUBLE_MNEM_SUFFIX '\1'
93
94#define END_OF_INSN '\0'
95
96/*
97 'templates' is for grouping together 'template' structures for opcodes
98 of the same name. This is only used for storing the insns in the grand
99 ole hash table of insns.
100 The templates themselves start at START and range up to (but not including)
101 END.
102 */
103typedef struct
104{
105 const insn_template *start;
106 const insn_template *end;
107}
108templates;
109
110/* 386 operand encoding bytes: see 386 book for details of this. */
111typedef struct
112{
113 unsigned int regmem; /* codes register or memory operand */
114 unsigned int reg; /* codes register operand (or extended opcode) */
115 unsigned int mode; /* how to interpret regmem & reg */
116}
117modrm_byte;
118
119/* x86-64 extension prefix. */
120typedef int rex_byte;
121
122/* 386 opcode byte to code indirect addressing. */
123typedef struct
124{
125 unsigned base;
126 unsigned index;
127 unsigned scale;
128}
129sib_byte;
130
131/* x86 arch names, types and features */
132typedef struct
133{
134 const char *name; /* arch name */
135 unsigned int len; /* arch string length */
136 enum processor_type type; /* arch type */
137 i386_cpu_flags flags; /* cpu feature flags */
138 unsigned int skip; /* show_arch should skip this. */
139 unsigned int negated; /* turn off indicated flags. */
140}
141arch_entry;
142
143static void update_code_flag (int, int);
144static void set_code_flag (int);
145static void set_16bit_gcc_code_flag (int);
146static void set_intel_syntax (int);
147static void set_intel_mnemonic (int);
148static void set_allow_index_reg (int);
149static void set_check (int);
150static void set_cpu_arch (int);
151#ifdef TE_PE
152static void pe_directive_secrel (int);
153#endif
154static void signed_cons (int);
155static char *output_invalid (int c);
156static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
157 const char *);
158static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
159 const char *);
160static int i386_att_operand (char *);
161static int i386_intel_operand (char *, int);
162static int i386_intel_simplify (expressionS *);
163static int i386_intel_parse_name (const char *, expressionS *);
164static const reg_entry *parse_register (char *, char **);
165static char *parse_insn (char *, char *);
166static char *parse_operands (char *, const char *);
167static void swap_operands (void);
168static void swap_2_operands (int, int);
169static void optimize_imm (void);
170static void optimize_disp (void);
171static const insn_template *match_template (void);
172static int check_string (void);
173static int process_suffix (void);
174static int check_byte_reg (void);
175static int check_long_reg (void);
176static int check_qword_reg (void);
177static int check_word_reg (void);
178static int finalize_imm (void);
179static int process_operands (void);
180static const seg_entry *build_modrm_byte (void);
181static void output_insn (void);
182static void output_imm (fragS *, offsetT);
183static void output_disp (fragS *, offsetT);
184#ifndef I386COFF
185static void s_bss (int);
186#endif
187#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
188static void handle_large_common (int small ATTRIBUTE_UNUSED);
189#endif
190
191static const char *default_arch = DEFAULT_ARCH;
192
193/* This struct describes rounding control and SAE in the instruction. */
194struct RC_Operation
195{
196 enum rc_type
197 {
198 rne = 0,
199 rd,
200 ru,
201 rz,
202 saeonly
203 } type;
204 int operand;
205};
206
207static struct RC_Operation rc_op;
208
209/* The struct describes masking, applied to OPERAND in the instruction.
210 MASK is a pointer to the corresponding mask register. ZEROING tells
211 whether merging or zeroing mask is used. */
212struct Mask_Operation
213{
214 const reg_entry *mask;
215 unsigned int zeroing;
216 /* The operand where this operation is associated. */
217 int operand;
218};
219
220static struct Mask_Operation mask_op;
221
222/* The struct describes broadcasting, applied to OPERAND. FACTOR is
223 broadcast factor. */
224struct Broadcast_Operation
225{
226 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
227 int type;
228
229 /* Index of broadcasted operand. */
230 int operand;
231};
232
233static struct Broadcast_Operation broadcast_op;
234
235/* VEX prefix. */
236typedef struct
237{
238 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
239 unsigned char bytes[4];
240 unsigned int length;
241 /* Destination or source register specifier. */
242 const reg_entry *register_specifier;
243} vex_prefix;
244
245/* 'md_assemble ()' gathers together information and puts it into a
246 i386_insn. */
247
248union i386_op
249 {
250 expressionS *disps;
251 expressionS *imms;
252 const reg_entry *regs;
253 };
254
255enum i386_error
256 {
257 operand_size_mismatch,
258 operand_type_mismatch,
259 register_type_mismatch,
260 number_of_operands_mismatch,
261 invalid_instruction_suffix,
262 bad_imm4,
263 old_gcc_only,
264 unsupported_with_intel_mnemonic,
265 unsupported_syntax,
266 unsupported,
267 invalid_vsib_address,
268 invalid_vector_register_set,
269 unsupported_vector_index_register,
270 unsupported_broadcast,
271 broadcast_not_on_src_operand,
272 broadcast_needed,
273 unsupported_masking,
274 mask_not_on_destination,
275 no_default_mask,
276 unsupported_rc_sae,
277 rc_sae_operand_not_last_imm,
278 invalid_register_operand,
279 try_vector_disp8
280 };
281
282struct _i386_insn
283 {
284 /* TM holds the template for the insn were currently assembling. */
285 insn_template tm;
286
287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
289 char suffix;
290
291 /* OPERANDS gives the number of given operands. */
292 unsigned int operands;
293
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
296 operands. */
297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
298
299 /* TYPES [i] is the type (see above #defines) which tells us how to
300 use OP[i] for the corresponding operand. */
301 i386_operand_type types[MAX_OPERANDS];
302
303 /* Displacement expression, immediate expression, or register for each
304 operand. */
305 union i386_op op[MAX_OPERANDS];
306
307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309#define Operand_PCrel 1
310
311 /* Relocation type for operand */
312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
313
314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
319
320 /* SEG gives the seg_entries of this insn. They are zero unless
321 explicit segment overrides are given. */
322 const seg_entry *seg[2];
323
324 /* PREFIX holds all the given prefix opcodes (usually null).
325 PREFIXES is the number of prefix opcodes. */
326 unsigned int prefixes;
327 unsigned char prefix[MAX_PREFIXES];
328
329 /* RM and SIB are the modrm byte and the sib byte where the
330 addressing modes of this insn are encoded. */
331 modrm_byte rm;
332 rex_byte rex;
333 rex_byte vrex;
334 sib_byte sib;
335 vex_prefix vex;
336
337 /* Masking attributes. */
338 struct Mask_Operation *mask;
339
340 /* Rounding control and SAE attributes. */
341 struct RC_Operation *rounding;
342
343 /* Broadcasting attributes. */
344 struct Broadcast_Operation *broadcast;
345
346 /* Compressed disp8*N attribute. */
347 unsigned int memshift;
348
349 /* Swap operand in encoding. */
350 unsigned int swap_operand;
351
352 /* Prefer 8bit or 32bit displacement in encoding. */
353 enum
354 {
355 disp_encoding_default = 0,
356 disp_encoding_8bit,
357 disp_encoding_32bit
358 } disp_encoding;
359
360 /* REP prefix. */
361 const char *rep_prefix;
362
363 /* HLE prefix. */
364 const char *hle_prefix;
365
366 /* Have BND prefix. */
367 const char *bnd_prefix;
368
369 /* Need VREX to support upper 16 registers. */
370 int need_vrex;
371
372 /* Error message. */
373 enum i386_error error;
374 };
375
376typedef struct _i386_insn i386_insn;
377
378/* Link RC type with corresponding string, that'll be looked for in
379 asm. */
380struct RC_name
381{
382 enum rc_type type;
383 const char *name;
384 unsigned int len;
385};
386
387static const struct RC_name RC_NamesTable[] =
388{
389 { rne, STRING_COMMA_LEN ("rn-sae") },
390 { rd, STRING_COMMA_LEN ("rd-sae") },
391 { ru, STRING_COMMA_LEN ("ru-sae") },
392 { rz, STRING_COMMA_LEN ("rz-sae") },
393 { saeonly, STRING_COMMA_LEN ("sae") },
394};
395
396/* List of chars besides those in app.c:symbol_chars that can start an
397 operand. Used to prevent the scrubber eating vital white-space. */
398const char extra_symbol_chars[] = "*%-([{"
399#ifdef LEX_AT
400 "@"
401#endif
402#ifdef LEX_QM
403 "?"
404#endif
405 ;
406
407#if (defined (TE_I386AIX) \
408 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
409 && !defined (TE_GNU) \
410 && !defined (TE_LINUX) \
411 && !defined (TE_NACL) \
412 && !defined (TE_NETWARE) \
413 && !defined (TE_FreeBSD) \
414 && !defined (TE_DragonFly) \
415 && !defined (TE_NetBSD)))
416/* This array holds the chars that always start a comment. If the
417 pre-processor is disabled, these aren't very useful. The option
418 --divide will remove '/' from this list. */
419const char *i386_comment_chars = "#/";
420#define SVR4_COMMENT_CHARS 1
421#define PREFIX_SEPARATOR '\\'
422
423#else
424const char *i386_comment_chars = "#";
425#define PREFIX_SEPARATOR '/'
426#endif
427
428/* This array holds the chars that only start a comment at the beginning of
429 a line. If the line seems to have the form '# 123 filename'
430 .line and .file directives will appear in the pre-processed output.
431 Note that input_file.c hand checks for '#' at the beginning of the
432 first line of the input file. This is because the compiler outputs
433 #NO_APP at the beginning of its output.
434 Also note that comments started like this one will always work if
435 '/' isn't otherwise defined. */
436const char line_comment_chars[] = "#/";
437
438const char line_separator_chars[] = ";";
439
440/* Chars that can be used to separate mant from exp in floating point
441 nums. */
442const char EXP_CHARS[] = "eE";
443
444/* Chars that mean this number is a floating point constant
445 As in 0f12.456
446 or 0d1.2345e12. */
447const char FLT_CHARS[] = "fFdDxX";
448
449/* Tables for lexical analysis. */
450static char mnemonic_chars[256];
451static char register_chars[256];
452static char operand_chars[256];
453static char identifier_chars[256];
454static char digit_chars[256];
455
456/* Lexical macros. */
457#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
458#define is_operand_char(x) (operand_chars[(unsigned char) x])
459#define is_register_char(x) (register_chars[(unsigned char) x])
460#define is_space_char(x) ((x) == ' ')
461#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
462#define is_digit_char(x) (digit_chars[(unsigned char) x])
463
464/* All non-digit non-letter characters that may occur in an operand. */
465static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
466
467/* md_assemble() always leaves the strings it's passed unaltered. To
468 effect this we maintain a stack of saved characters that we've smashed
469 with '\0's (indicating end of strings for various sub-fields of the
470 assembler instruction). */
471static char save_stack[32];
472static char *save_stack_p;
473#define END_STRING_AND_SAVE(s) \
474 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
475#define RESTORE_END_STRING(s) \
476 do { *(s) = *--save_stack_p; } while (0)
477
478/* The instruction we're assembling. */
479static i386_insn i;
480
481/* Possible templates for current insn. */
482static const templates *current_templates;
483
484/* Per instruction expressionS buffers: max displacements & immediates. */
485static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
486static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
487
488/* Current operand we are working on. */
489static int this_operand = -1;
490
491/* We support four different modes. FLAG_CODE variable is used to distinguish
492 these. */
493
494enum flag_code {
495 CODE_32BIT,
496 CODE_16BIT,
497 CODE_64BIT };
498
499static enum flag_code flag_code;
500static unsigned int object_64bit;
501static unsigned int disallow_64bit_reloc;
502static int use_rela_relocations = 0;
503
504#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
505 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
506 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
507
508/* The ELF ABI to use. */
509enum x86_elf_abi
510{
511 I386_ABI,
512 X86_64_ABI,
513 X86_64_X32_ABI
514};
515
516static enum x86_elf_abi x86_elf_abi = I386_ABI;
517#endif
518
519/* 1 for intel syntax,
520 0 if att syntax. */
521static int intel_syntax = 0;
522
523/* 1 for intel mnemonic,
524 0 if att mnemonic. */
525static int intel_mnemonic = !SYSV386_COMPAT;
526
527/* 1 if support old (<= 2.8.1) versions of gcc. */
528static int old_gcc = OLDGCC_COMPAT;
529
530/* 1 if pseudo registers are permitted. */
531static int allow_pseudo_reg = 0;
532
533/* 1 if register prefix % not required. */
534static int allow_naked_reg = 0;
535
536/* 1 if the assembler should add BND prefix for all control-tranferring
537 instructions supporting it, even if this prefix wasn't specified
538 explicitly. */
539static int add_bnd_prefix = 0;
540
541/* 1 if pseudo index register, eiz/riz, is allowed . */
542static int allow_index_reg = 0;
543
544static enum check_kind
545 {
546 check_none = 0,
547 check_warning,
548 check_error
549 }
550sse_check, operand_check = check_warning;
551
552/* Register prefix used for error message. */
553static const char *register_prefix = "%";
554
555/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
556 leave, push, and pop instructions so that gcc has the same stack
557 frame as in 32 bit mode. */
558static char stackop_size = '\0';
559
560/* Non-zero to optimize code alignment. */
561int optimize_align_code = 1;
562
563/* Non-zero to quieten some warnings. */
564static int quiet_warnings = 0;
565
566/* CPU name. */
567static const char *cpu_arch_name = NULL;
568static char *cpu_sub_arch_name = NULL;
569
570/* CPU feature flags. */
571static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
572
573/* If we have selected a cpu we are generating instructions for. */
574static int cpu_arch_tune_set = 0;
575
576/* Cpu we are generating instructions for. */
577enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
578
579/* CPU feature flags of cpu we are generating instructions for. */
580static i386_cpu_flags cpu_arch_tune_flags;
581
582/* CPU instruction set architecture used. */
583enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
584
585/* CPU feature flags of instruction set architecture used. */
586i386_cpu_flags cpu_arch_isa_flags;
587
588/* If set, conditional jumps are not automatically promoted to handle
589 larger than a byte offset. */
590static unsigned int no_cond_jump_promotion = 0;
591
592/* Encode SSE instructions with VEX prefix. */
593static unsigned int sse2avx;
594
595/* Encode scalar AVX instructions with specific vector length. */
596static enum
597 {
598 vex128 = 0,
599 vex256
600 } avxscalar;
601
602/* Encode scalar EVEX LIG instructions with specific vector length. */
603static enum
604 {
605 evexl128 = 0,
606 evexl256,
607 evexl512
608 } evexlig;
609
610/* Encode EVEX WIG instructions with specific evex.w. */
611static enum
612 {
613 evexw0 = 0,
614 evexw1
615 } evexwig;
616
617/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
618static symbolS *GOT_symbol;
619
620/* The dwarf2 return column, adjusted for 32 or 64 bit. */
621unsigned int x86_dwarf2_return_column;
622
623/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
624int x86_cie_data_alignment;
625
626/* Interface to relax_segment.
627 There are 3 major relax states for 386 jump insns because the
628 different types of jumps add different sizes to frags when we're
629 figuring out what sort of jump to choose to reach a given label. */
630
631/* Types. */
632#define UNCOND_JUMP 0
633#define COND_JUMP 1
634#define COND_JUMP86 2
635
636/* Sizes. */
637#define CODE16 1
638#define SMALL 0
639#define SMALL16 (SMALL | CODE16)
640#define BIG 2
641#define BIG16 (BIG | CODE16)
642
643#ifndef INLINE
644#ifdef __GNUC__
645#define INLINE __inline__
646#else
647#define INLINE
648#endif
649#endif
650
651#define ENCODE_RELAX_STATE(type, size) \
652 ((relax_substateT) (((type) << 2) | (size)))
653#define TYPE_FROM_RELAX_STATE(s) \
654 ((s) >> 2)
655#define DISP_SIZE_FROM_RELAX_STATE(s) \
656 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
657
658/* This table is used by relax_frag to promote short jumps to long
659 ones where necessary. SMALL (short) jumps may be promoted to BIG
660 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
661 don't allow a short jump in a 32 bit code segment to be promoted to
662 a 16 bit offset jump because it's slower (requires data size
663 prefix), and doesn't work, unless the destination is in the bottom
664 64k of the code segment (The top 16 bits of eip are zeroed). */
665
666const relax_typeS md_relax_table[] =
667{
668 /* The fields are:
669 1) most positive reach of this state,
670 2) most negative reach of this state,
671 3) how many bytes this mode will have in the variable part of the frag
672 4) which index into the table to try if we can't fit into this one. */
673
674 /* UNCOND_JUMP states. */
675 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
676 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
677 /* dword jmp adds 4 bytes to frag:
678 0 extra opcode bytes, 4 displacement bytes. */
679 {0, 0, 4, 0},
680 /* word jmp adds 2 byte2 to frag:
681 0 extra opcode bytes, 2 displacement bytes. */
682 {0, 0, 2, 0},
683
684 /* COND_JUMP states. */
685 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
686 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
687 /* dword conditionals adds 5 bytes to frag:
688 1 extra opcode byte, 4 displacement bytes. */
689 {0, 0, 5, 0},
690 /* word conditionals add 3 bytes to frag:
691 1 extra opcode byte, 2 displacement bytes. */
692 {0, 0, 3, 0},
693
694 /* COND_JUMP86 states. */
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
696 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
697 /* dword conditionals adds 5 bytes to frag:
698 1 extra opcode byte, 4 displacement bytes. */
699 {0, 0, 5, 0},
700 /* word conditionals add 4 bytes to frag:
701 1 displacement byte and a 3 byte long branch insn. */
702 {0, 0, 4, 0}
703};
704
705static const arch_entry cpu_arch[] =
706{
707 /* Do not replace the first two entries - i386_target_format()
708 relies on them being there in this order. */
709 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
710 CPU_GENERIC32_FLAGS, 0, 0 },
711 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
712 CPU_GENERIC64_FLAGS, 0, 0 },
713 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
714 CPU_NONE_FLAGS, 0, 0 },
715 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
716 CPU_I186_FLAGS, 0, 0 },
717 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
718 CPU_I286_FLAGS, 0, 0 },
719 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
720 CPU_I386_FLAGS, 0, 0 },
721 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
722 CPU_I486_FLAGS, 0, 0 },
723 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
724 CPU_I586_FLAGS, 0, 0 },
725 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
726 CPU_I686_FLAGS, 0, 0 },
727 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
728 CPU_I586_FLAGS, 0, 0 },
729 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
730 CPU_PENTIUMPRO_FLAGS, 0, 0 },
731 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
732 CPU_P2_FLAGS, 0, 0 },
733 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
734 CPU_P3_FLAGS, 0, 0 },
735 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
736 CPU_P4_FLAGS, 0, 0 },
737 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
738 CPU_CORE_FLAGS, 0, 0 },
739 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
740 CPU_NOCONA_FLAGS, 0, 0 },
741 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
742 CPU_CORE_FLAGS, 1, 0 },
743 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
744 CPU_CORE_FLAGS, 0, 0 },
745 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
746 CPU_CORE2_FLAGS, 1, 0 },
747 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
748 CPU_CORE2_FLAGS, 0, 0 },
749 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
750 CPU_COREI7_FLAGS, 0, 0 },
751 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
752 CPU_L1OM_FLAGS, 0, 0 },
753 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
754 CPU_K1OM_FLAGS, 0, 0 },
755 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
756 CPU_K6_FLAGS, 0, 0 },
757 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
758 CPU_K6_2_FLAGS, 0, 0 },
759 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
760 CPU_ATHLON_FLAGS, 0, 0 },
761 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
762 CPU_K8_FLAGS, 1, 0 },
763 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
764 CPU_K8_FLAGS, 0, 0 },
765 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
766 CPU_K8_FLAGS, 0, 0 },
767 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
768 CPU_AMDFAM10_FLAGS, 0, 0 },
769 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
770 CPU_BDVER1_FLAGS, 0, 0 },
771 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
772 CPU_BDVER2_FLAGS, 0, 0 },
773 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
774 CPU_BDVER3_FLAGS, 0, 0 },
775 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
776 CPU_BDVER4_FLAGS, 0, 0 },
777 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
778 CPU_BTVER1_FLAGS, 0, 0 },
779 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
780 CPU_BTVER2_FLAGS, 0, 0 },
781 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
782 CPU_8087_FLAGS, 0, 0 },
783 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
784 CPU_287_FLAGS, 0, 0 },
785 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
786 CPU_387_FLAGS, 0, 0 },
787 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
788 CPU_ANY87_FLAGS, 0, 1 },
789 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
790 CPU_MMX_FLAGS, 0, 0 },
791 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
792 CPU_3DNOWA_FLAGS, 0, 1 },
793 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
794 CPU_SSE_FLAGS, 0, 0 },
795 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
796 CPU_SSE2_FLAGS, 0, 0 },
797 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
798 CPU_SSE3_FLAGS, 0, 0 },
799 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
800 CPU_SSSE3_FLAGS, 0, 0 },
801 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
802 CPU_SSE4_1_FLAGS, 0, 0 },
803 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
804 CPU_SSE4_2_FLAGS, 0, 0 },
805 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
806 CPU_SSE4_2_FLAGS, 0, 0 },
807 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
808 CPU_ANY_SSE_FLAGS, 0, 1 },
809 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
810 CPU_AVX_FLAGS, 0, 0 },
811 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
812 CPU_AVX2_FLAGS, 0, 0 },
813 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
814 CPU_AVX512F_FLAGS, 0, 0 },
815 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
816 CPU_AVX512CD_FLAGS, 0, 0 },
817 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
818 CPU_AVX512ER_FLAGS, 0, 0 },
819 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
820 CPU_AVX512PF_FLAGS, 0, 0 },
821 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
822 CPU_ANY_AVX_FLAGS, 0, 1 },
823 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
824 CPU_VMX_FLAGS, 0, 0 },
825 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
826 CPU_VMFUNC_FLAGS, 0, 0 },
827 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
828 CPU_SMX_FLAGS, 0, 0 },
829 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
830 CPU_XSAVE_FLAGS, 0, 0 },
831 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
832 CPU_XSAVEOPT_FLAGS, 0, 0 },
833 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
834 CPU_AES_FLAGS, 0, 0 },
835 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
836 CPU_PCLMUL_FLAGS, 0, 0 },
837 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
838 CPU_PCLMUL_FLAGS, 1, 0 },
839 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
840 CPU_FSGSBASE_FLAGS, 0, 0 },
841 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
842 CPU_RDRND_FLAGS, 0, 0 },
843 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
844 CPU_F16C_FLAGS, 0, 0 },
845 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
846 CPU_BMI2_FLAGS, 0, 0 },
847 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
848 CPU_FMA_FLAGS, 0, 0 },
849 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
850 CPU_FMA4_FLAGS, 0, 0 },
851 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
852 CPU_XOP_FLAGS, 0, 0 },
853 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
854 CPU_LWP_FLAGS, 0, 0 },
855 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
856 CPU_MOVBE_FLAGS, 0, 0 },
857 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
858 CPU_CX16_FLAGS, 0, 0 },
859 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
860 CPU_EPT_FLAGS, 0, 0 },
861 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
862 CPU_LZCNT_FLAGS, 0, 0 },
863 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
864 CPU_HLE_FLAGS, 0, 0 },
865 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
866 CPU_RTM_FLAGS, 0, 0 },
867 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
868 CPU_INVPCID_FLAGS, 0, 0 },
869 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
870 CPU_CLFLUSH_FLAGS, 0, 0 },
871 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
872 CPU_NOP_FLAGS, 0, 0 },
873 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
874 CPU_SYSCALL_FLAGS, 0, 0 },
875 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
876 CPU_RDTSCP_FLAGS, 0, 0 },
877 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
878 CPU_3DNOW_FLAGS, 0, 0 },
879 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
880 CPU_3DNOWA_FLAGS, 0, 0 },
881 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
882 CPU_PADLOCK_FLAGS, 0, 0 },
883 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
884 CPU_SVME_FLAGS, 1, 0 },
885 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
886 CPU_SVME_FLAGS, 0, 0 },
887 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
888 CPU_SSE4A_FLAGS, 0, 0 },
889 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
890 CPU_ABM_FLAGS, 0, 0 },
891 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
892 CPU_BMI_FLAGS, 0, 0 },
893 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
894 CPU_TBM_FLAGS, 0, 0 },
895 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
896 CPU_ADX_FLAGS, 0, 0 },
897 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
898 CPU_RDSEED_FLAGS, 0, 0 },
899 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
900 CPU_PRFCHW_FLAGS, 0, 0 },
901 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
902 CPU_SMAP_FLAGS, 0, 0 },
903 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
904 CPU_MPX_FLAGS, 0, 0 },
905 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
906 CPU_SHA_FLAGS, 0, 0 },
907};
908
909#ifdef I386COFF
910/* Like s_lcomm_internal in gas/read.c but the alignment string
911 is allowed to be optional. */
912
913static symbolS *
914pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
915{
916 addressT align = 0;
917
918 SKIP_WHITESPACE ();
919
920 if (needs_align
921 && *input_line_pointer == ',')
922 {
923 align = parse_align (needs_align - 1);
924
925 if (align == (addressT) -1)
926 return NULL;
927 }
928 else
929 {
930 if (size >= 8)
931 align = 3;
932 else if (size >= 4)
933 align = 2;
934 else if (size >= 2)
935 align = 1;
936 else
937 align = 0;
938 }
939
940 bss_alloc (symbolP, size, align);
941 return symbolP;
942}
943
944static void
945pe_lcomm (int needs_align)
946{
947 s_comm_internal (needs_align * 2, pe_lcomm_internal);
948}
949#endif
950
951const pseudo_typeS md_pseudo_table[] =
952{
953#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
954 {"align", s_align_bytes, 0},
955#else
956 {"align", s_align_ptwo, 0},
957#endif
958 {"arch", set_cpu_arch, 0},
959#ifndef I386COFF
960 {"bss", s_bss, 0},
961#else
962 {"lcomm", pe_lcomm, 1},
963#endif
964 {"ffloat", float_cons, 'f'},
965 {"dfloat", float_cons, 'd'},
966 {"tfloat", float_cons, 'x'},
967 {"value", cons, 2},
968 {"slong", signed_cons, 4},
969 {"noopt", s_ignore, 0},
970 {"optim", s_ignore, 0},
971 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
972 {"code16", set_code_flag, CODE_16BIT},
973 {"code32", set_code_flag, CODE_32BIT},
974 {"code64", set_code_flag, CODE_64BIT},
975 {"intel_syntax", set_intel_syntax, 1},
976 {"att_syntax", set_intel_syntax, 0},
977 {"intel_mnemonic", set_intel_mnemonic, 1},
978 {"att_mnemonic", set_intel_mnemonic, 0},
979 {"allow_index_reg", set_allow_index_reg, 1},
980 {"disallow_index_reg", set_allow_index_reg, 0},
981 {"sse_check", set_check, 0},
982 {"operand_check", set_check, 1},
983#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
984 {"largecomm", handle_large_common, 0},
985#else
986 {"file", (void (*) (int)) dwarf2_directive_file, 0},
987 {"loc", dwarf2_directive_loc, 0},
988 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
989#endif
990#ifdef TE_PE
991 {"secrel32", pe_directive_secrel, 0},
992#endif
993 {0, 0, 0}
994};
995
996/* For interface with expression (). */
997extern char *input_line_pointer;
998
999/* Hash table for instruction mnemonic lookup. */
1000static struct hash_control *op_hash;
1001
1002/* Hash table for register lookup. */
1003static struct hash_control *reg_hash;
1004\f
1005void
1006i386_align_code (fragS *fragP, int count)
1007{
1008 /* Various efficient no-op patterns for aligning code labels.
1009 Note: Don't try to assemble the instructions in the comments.
1010 0L and 0w are not legal. */
1011 static const char f32_1[] =
1012 {0x90}; /* nop */
1013 static const char f32_2[] =
1014 {0x66,0x90}; /* xchg %ax,%ax */
1015 static const char f32_3[] =
1016 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1017 static const char f32_4[] =
1018 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1019 static const char f32_5[] =
1020 {0x90, /* nop */
1021 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1022 static const char f32_6[] =
1023 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1024 static const char f32_7[] =
1025 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1026 static const char f32_8[] =
1027 {0x90, /* nop */
1028 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1029 static const char f32_9[] =
1030 {0x89,0xf6, /* movl %esi,%esi */
1031 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1032 static const char f32_10[] =
1033 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1034 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1035 static const char f32_11[] =
1036 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1037 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1038 static const char f32_12[] =
1039 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1040 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1041 static const char f32_13[] =
1042 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1043 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1044 static const char f32_14[] =
1045 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1046 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1047 static const char f16_3[] =
1048 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1049 static const char f16_4[] =
1050 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1051 static const char f16_5[] =
1052 {0x90, /* nop */
1053 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1054 static const char f16_6[] =
1055 {0x89,0xf6, /* mov %si,%si */
1056 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1057 static const char f16_7[] =
1058 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1059 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1060 static const char f16_8[] =
1061 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1062 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1063 static const char jump_31[] =
1064 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1065 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1066 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1067 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1068 static const char *const f32_patt[] = {
1069 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
1070 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
1071 };
1072 static const char *const f16_patt[] = {
1073 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
1074 };
1075 /* nopl (%[re]ax) */
1076 static const char alt_3[] =
1077 {0x0f,0x1f,0x00};
1078 /* nopl 0(%[re]ax) */
1079 static const char alt_4[] =
1080 {0x0f,0x1f,0x40,0x00};
1081 /* nopl 0(%[re]ax,%[re]ax,1) */
1082 static const char alt_5[] =
1083 {0x0f,0x1f,0x44,0x00,0x00};
1084 /* nopw 0(%[re]ax,%[re]ax,1) */
1085 static const char alt_6[] =
1086 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1087 /* nopl 0L(%[re]ax) */
1088 static const char alt_7[] =
1089 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1090 /* nopl 0L(%[re]ax,%[re]ax,1) */
1091 static const char alt_8[] =
1092 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1093 /* nopw 0L(%[re]ax,%[re]ax,1) */
1094 static const char alt_9[] =
1095 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1096 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1097 static const char alt_10[] =
1098 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1099 /* data16
1100 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1101 static const char alt_long_11[] =
1102 {0x66,
1103 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1104 /* data16
1105 data16
1106 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1107 static const char alt_long_12[] =
1108 {0x66,
1109 0x66,
1110 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1111 /* data16
1112 data16
1113 data16
1114 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1115 static const char alt_long_13[] =
1116 {0x66,
1117 0x66,
1118 0x66,
1119 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1120 /* data16
1121 data16
1122 data16
1123 data16
1124 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1125 static const char alt_long_14[] =
1126 {0x66,
1127 0x66,
1128 0x66,
1129 0x66,
1130 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1131 /* data16
1132 data16
1133 data16
1134 data16
1135 data16
1136 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1137 static const char alt_long_15[] =
1138 {0x66,
1139 0x66,
1140 0x66,
1141 0x66,
1142 0x66,
1143 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1144 /* nopl 0(%[re]ax,%[re]ax,1)
1145 nopw 0(%[re]ax,%[re]ax,1) */
1146 static const char alt_short_11[] =
1147 {0x0f,0x1f,0x44,0x00,0x00,
1148 0x66,0x0f,0x1f,0x44,0x00,0x00};
1149 /* nopw 0(%[re]ax,%[re]ax,1)
1150 nopw 0(%[re]ax,%[re]ax,1) */
1151 static const char alt_short_12[] =
1152 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1153 0x66,0x0f,0x1f,0x44,0x00,0x00};
1154 /* nopw 0(%[re]ax,%[re]ax,1)
1155 nopl 0L(%[re]ax) */
1156 static const char alt_short_13[] =
1157 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1158 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1159 /* nopl 0L(%[re]ax)
1160 nopl 0L(%[re]ax) */
1161 static const char alt_short_14[] =
1162 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1163 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1164 /* nopl 0L(%[re]ax)
1165 nopl 0L(%[re]ax,%[re]ax,1) */
1166 static const char alt_short_15[] =
1167 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1168 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1169 static const char *const alt_short_patt[] = {
1170 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1171 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1172 alt_short_14, alt_short_15
1173 };
1174 static const char *const alt_long_patt[] = {
1175 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1176 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1177 alt_long_14, alt_long_15
1178 };
1179
1180 /* Only align for at least a positive non-zero boundary. */
1181 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
1182 return;
1183
1184 /* We need to decide which NOP sequence to use for 32bit and
1185 64bit. When -mtune= is used:
1186
1187 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1188 PROCESSOR_GENERIC32, f32_patt will be used.
1189 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1190 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1191 PROCESSOR_GENERIC64, alt_long_patt will be used.
1192 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1193 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1194 will be used.
1195
1196 When -mtune= isn't used, alt_long_patt will be used if
1197 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1198 be used.
1199
1200 When -march= or .arch is used, we can't use anything beyond
1201 cpu_arch_isa_flags. */
1202
1203 if (flag_code == CODE_16BIT)
1204 {
1205 if (count > 8)
1206 {
1207 memcpy (fragP->fr_literal + fragP->fr_fix,
1208 jump_31, count);
1209 /* Adjust jump offset. */
1210 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1211 }
1212 else
1213 memcpy (fragP->fr_literal + fragP->fr_fix,
1214 f16_patt[count - 1], count);
1215 }
1216 else
1217 {
1218 const char *const *patt = NULL;
1219
1220 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1221 {
1222 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1223 switch (cpu_arch_tune)
1224 {
1225 case PROCESSOR_UNKNOWN:
1226 /* We use cpu_arch_isa_flags to check if we SHOULD
1227 optimize with nops. */
1228 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1229 patt = alt_long_patt;
1230 else
1231 patt = f32_patt;
1232 break;
1233 case PROCESSOR_PENTIUM4:
1234 case PROCESSOR_NOCONA:
1235 case PROCESSOR_CORE:
1236 case PROCESSOR_CORE2:
1237 case PROCESSOR_COREI7:
1238 case PROCESSOR_L1OM:
1239 case PROCESSOR_K1OM:
1240 case PROCESSOR_GENERIC64:
1241 patt = alt_long_patt;
1242 break;
1243 case PROCESSOR_K6:
1244 case PROCESSOR_ATHLON:
1245 case PROCESSOR_K8:
1246 case PROCESSOR_AMDFAM10:
1247 case PROCESSOR_BD:
1248 case PROCESSOR_BT:
1249 patt = alt_short_patt;
1250 break;
1251 case PROCESSOR_I386:
1252 case PROCESSOR_I486:
1253 case PROCESSOR_PENTIUM:
1254 case PROCESSOR_PENTIUMPRO:
1255 case PROCESSOR_GENERIC32:
1256 patt = f32_patt;
1257 break;
1258 }
1259 }
1260 else
1261 {
1262 switch (fragP->tc_frag_data.tune)
1263 {
1264 case PROCESSOR_UNKNOWN:
1265 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1266 PROCESSOR_UNKNOWN. */
1267 abort ();
1268 break;
1269
1270 case PROCESSOR_I386:
1271 case PROCESSOR_I486:
1272 case PROCESSOR_PENTIUM:
1273 case PROCESSOR_K6:
1274 case PROCESSOR_ATHLON:
1275 case PROCESSOR_K8:
1276 case PROCESSOR_AMDFAM10:
1277 case PROCESSOR_BD:
1278 case PROCESSOR_BT:
1279 case PROCESSOR_GENERIC32:
1280 /* We use cpu_arch_isa_flags to check if we CAN optimize
1281 with nops. */
1282 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1283 patt = alt_short_patt;
1284 else
1285 patt = f32_patt;
1286 break;
1287 case PROCESSOR_PENTIUMPRO:
1288 case PROCESSOR_PENTIUM4:
1289 case PROCESSOR_NOCONA:
1290 case PROCESSOR_CORE:
1291 case PROCESSOR_CORE2:
1292 case PROCESSOR_COREI7:
1293 case PROCESSOR_L1OM:
1294 case PROCESSOR_K1OM:
1295 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1296 patt = alt_long_patt;
1297 else
1298 patt = f32_patt;
1299 break;
1300 case PROCESSOR_GENERIC64:
1301 patt = alt_long_patt;
1302 break;
1303 }
1304 }
1305
1306 if (patt == f32_patt)
1307 {
1308 /* If the padding is less than 15 bytes, we use the normal
1309 ones. Otherwise, we use a jump instruction and adjust
1310 its offset. */
1311 int limit;
1312
1313 /* For 64bit, the limit is 3 bytes. */
1314 if (flag_code == CODE_64BIT
1315 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1316 limit = 3;
1317 else
1318 limit = 15;
1319 if (count < limit)
1320 memcpy (fragP->fr_literal + fragP->fr_fix,
1321 patt[count - 1], count);
1322 else
1323 {
1324 memcpy (fragP->fr_literal + fragP->fr_fix,
1325 jump_31, count);
1326 /* Adjust jump offset. */
1327 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1328 }
1329 }
1330 else
1331 {
1332 /* Maximum length of an instruction is 15 byte. If the
1333 padding is greater than 15 bytes and we don't use jump,
1334 we have to break it into smaller pieces. */
1335 int padding = count;
1336 while (padding > 15)
1337 {
1338 padding -= 15;
1339 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1340 patt [14], 15);
1341 }
1342
1343 if (padding)
1344 memcpy (fragP->fr_literal + fragP->fr_fix,
1345 patt [padding - 1], padding);
1346 }
1347 }
1348 fragP->fr_var = count;
1349}
1350
1351static INLINE int
1352operand_type_all_zero (const union i386_operand_type *x)
1353{
1354 switch (ARRAY_SIZE(x->array))
1355 {
1356 case 3:
1357 if (x->array[2])
1358 return 0;
1359 case 2:
1360 if (x->array[1])
1361 return 0;
1362 case 1:
1363 return !x->array[0];
1364 default:
1365 abort ();
1366 }
1367}
1368
1369static INLINE void
1370operand_type_set (union i386_operand_type *x, unsigned int v)
1371{
1372 switch (ARRAY_SIZE(x->array))
1373 {
1374 case 3:
1375 x->array[2] = v;
1376 case 2:
1377 x->array[1] = v;
1378 case 1:
1379 x->array[0] = v;
1380 break;
1381 default:
1382 abort ();
1383 }
1384}
1385
1386static INLINE int
1387operand_type_equal (const union i386_operand_type *x,
1388 const union i386_operand_type *y)
1389{
1390 switch (ARRAY_SIZE(x->array))
1391 {
1392 case 3:
1393 if (x->array[2] != y->array[2])
1394 return 0;
1395 case 2:
1396 if (x->array[1] != y->array[1])
1397 return 0;
1398 case 1:
1399 return x->array[0] == y->array[0];
1400 break;
1401 default:
1402 abort ();
1403 }
1404}
1405
1406static INLINE int
1407cpu_flags_all_zero (const union i386_cpu_flags *x)
1408{
1409 switch (ARRAY_SIZE(x->array))
1410 {
1411 case 3:
1412 if (x->array[2])
1413 return 0;
1414 case 2:
1415 if (x->array[1])
1416 return 0;
1417 case 1:
1418 return !x->array[0];
1419 default:
1420 abort ();
1421 }
1422}
1423
1424static INLINE void
1425cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1426{
1427 switch (ARRAY_SIZE(x->array))
1428 {
1429 case 3:
1430 x->array[2] = v;
1431 case 2:
1432 x->array[1] = v;
1433 case 1:
1434 x->array[0] = v;
1435 break;
1436 default:
1437 abort ();
1438 }
1439}
1440
1441static INLINE int
1442cpu_flags_equal (const union i386_cpu_flags *x,
1443 const union i386_cpu_flags *y)
1444{
1445 switch (ARRAY_SIZE(x->array))
1446 {
1447 case 3:
1448 if (x->array[2] != y->array[2])
1449 return 0;
1450 case 2:
1451 if (x->array[1] != y->array[1])
1452 return 0;
1453 case 1:
1454 return x->array[0] == y->array[0];
1455 break;
1456 default:
1457 abort ();
1458 }
1459}
1460
1461static INLINE int
1462cpu_flags_check_cpu64 (i386_cpu_flags f)
1463{
1464 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1465 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1466}
1467
1468static INLINE i386_cpu_flags
1469cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1470{
1471 switch (ARRAY_SIZE (x.array))
1472 {
1473 case 3:
1474 x.array [2] &= y.array [2];
1475 case 2:
1476 x.array [1] &= y.array [1];
1477 case 1:
1478 x.array [0] &= y.array [0];
1479 break;
1480 default:
1481 abort ();
1482 }
1483 return x;
1484}
1485
1486static INLINE i386_cpu_flags
1487cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1488{
1489 switch (ARRAY_SIZE (x.array))
1490 {
1491 case 3:
1492 x.array [2] |= y.array [2];
1493 case 2:
1494 x.array [1] |= y.array [1];
1495 case 1:
1496 x.array [0] |= y.array [0];
1497 break;
1498 default:
1499 abort ();
1500 }
1501 return x;
1502}
1503
1504static INLINE i386_cpu_flags
1505cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1506{
1507 switch (ARRAY_SIZE (x.array))
1508 {
1509 case 3:
1510 x.array [2] &= ~y.array [2];
1511 case 2:
1512 x.array [1] &= ~y.array [1];
1513 case 1:
1514 x.array [0] &= ~y.array [0];
1515 break;
1516 default:
1517 abort ();
1518 }
1519 return x;
1520}
1521
1522#define CPU_FLAGS_ARCH_MATCH 0x1
1523#define CPU_FLAGS_64BIT_MATCH 0x2
1524#define CPU_FLAGS_AES_MATCH 0x4
1525#define CPU_FLAGS_PCLMUL_MATCH 0x8
1526#define CPU_FLAGS_AVX_MATCH 0x10
1527
1528#define CPU_FLAGS_32BIT_MATCH \
1529 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1530 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1531#define CPU_FLAGS_PERFECT_MATCH \
1532 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1533
1534/* Return CPU flags match bits. */
1535
1536static int
1537cpu_flags_match (const insn_template *t)
1538{
1539 i386_cpu_flags x = t->cpu_flags;
1540 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1541
1542 x.bitfield.cpu64 = 0;
1543 x.bitfield.cpuno64 = 0;
1544
1545 if (cpu_flags_all_zero (&x))
1546 {
1547 /* This instruction is available on all archs. */
1548 match |= CPU_FLAGS_32BIT_MATCH;
1549 }
1550 else
1551 {
1552 /* This instruction is available only on some archs. */
1553 i386_cpu_flags cpu = cpu_arch_flags;
1554
1555 cpu.bitfield.cpu64 = 0;
1556 cpu.bitfield.cpuno64 = 0;
1557 cpu = cpu_flags_and (x, cpu);
1558 if (!cpu_flags_all_zero (&cpu))
1559 {
1560 if (x.bitfield.cpuavx)
1561 {
1562 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1563 if (cpu.bitfield.cpuavx)
1564 {
1565 /* Check SSE2AVX. */
1566 if (!t->opcode_modifier.sse2avx|| sse2avx)
1567 {
1568 match |= (CPU_FLAGS_ARCH_MATCH
1569 | CPU_FLAGS_AVX_MATCH);
1570 /* Check AES. */
1571 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1572 match |= CPU_FLAGS_AES_MATCH;
1573 /* Check PCLMUL. */
1574 if (!x.bitfield.cpupclmul
1575 || cpu.bitfield.cpupclmul)
1576 match |= CPU_FLAGS_PCLMUL_MATCH;
1577 }
1578 }
1579 else
1580 match |= CPU_FLAGS_ARCH_MATCH;
1581 }
1582 else
1583 match |= CPU_FLAGS_32BIT_MATCH;
1584 }
1585 }
1586 return match;
1587}
1588
1589static INLINE i386_operand_type
1590operand_type_and (i386_operand_type x, i386_operand_type y)
1591{
1592 switch (ARRAY_SIZE (x.array))
1593 {
1594 case 3:
1595 x.array [2] &= y.array [2];
1596 case 2:
1597 x.array [1] &= y.array [1];
1598 case 1:
1599 x.array [0] &= y.array [0];
1600 break;
1601 default:
1602 abort ();
1603 }
1604 return x;
1605}
1606
1607static INLINE i386_operand_type
1608operand_type_or (i386_operand_type x, i386_operand_type y)
1609{
1610 switch (ARRAY_SIZE (x.array))
1611 {
1612 case 3:
1613 x.array [2] |= y.array [2];
1614 case 2:
1615 x.array [1] |= y.array [1];
1616 case 1:
1617 x.array [0] |= y.array [0];
1618 break;
1619 default:
1620 abort ();
1621 }
1622 return x;
1623}
1624
1625static INLINE i386_operand_type
1626operand_type_xor (i386_operand_type x, i386_operand_type y)
1627{
1628 switch (ARRAY_SIZE (x.array))
1629 {
1630 case 3:
1631 x.array [2] ^= y.array [2];
1632 case 2:
1633 x.array [1] ^= y.array [1];
1634 case 1:
1635 x.array [0] ^= y.array [0];
1636 break;
1637 default:
1638 abort ();
1639 }
1640 return x;
1641}
1642
1643static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1644static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1645static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1646static const i386_operand_type inoutportreg
1647 = OPERAND_TYPE_INOUTPORTREG;
1648static const i386_operand_type reg16_inoutportreg
1649 = OPERAND_TYPE_REG16_INOUTPORTREG;
1650static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1651static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1652static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1653static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1654static const i386_operand_type anydisp
1655 = OPERAND_TYPE_ANYDISP;
1656static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1657static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
1658static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1659static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1660static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1661static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1662static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1663static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1664static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1665static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1666static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1667static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1668static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1669static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1670static const i386_operand_type regbnd = OPERAND_TYPE_REGBND;
1671static const i386_operand_type vec_disp8 = OPERAND_TYPE_VEC_DISP8;
1672
1673enum operand_type
1674{
1675 reg,
1676 imm,
1677 disp,
1678 anymem
1679};
1680
1681static INLINE int
1682operand_type_check (i386_operand_type t, enum operand_type c)
1683{
1684 switch (c)
1685 {
1686 case reg:
1687 return (t.bitfield.reg8
1688 || t.bitfield.reg16
1689 || t.bitfield.reg32
1690 || t.bitfield.reg64);
1691
1692 case imm:
1693 return (t.bitfield.imm8
1694 || t.bitfield.imm8s
1695 || t.bitfield.imm16
1696 || t.bitfield.imm32
1697 || t.bitfield.imm32s
1698 || t.bitfield.imm64);
1699
1700 case disp:
1701 return (t.bitfield.disp8
1702 || t.bitfield.disp16
1703 || t.bitfield.disp32
1704 || t.bitfield.disp32s
1705 || t.bitfield.disp64);
1706
1707 case anymem:
1708 return (t.bitfield.disp8
1709 || t.bitfield.disp16
1710 || t.bitfield.disp32
1711 || t.bitfield.disp32s
1712 || t.bitfield.disp64
1713 || t.bitfield.baseindex);
1714
1715 default:
1716 abort ();
1717 }
1718
1719 return 0;
1720}
1721
1722/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1723 operand J for instruction template T. */
1724
1725static INLINE int
1726match_reg_size (const insn_template *t, unsigned int j)
1727{
1728 return !((i.types[j].bitfield.byte
1729 && !t->operand_types[j].bitfield.byte)
1730 || (i.types[j].bitfield.word
1731 && !t->operand_types[j].bitfield.word)
1732 || (i.types[j].bitfield.dword
1733 && !t->operand_types[j].bitfield.dword)
1734 || (i.types[j].bitfield.qword
1735 && !t->operand_types[j].bitfield.qword));
1736}
1737
1738/* Return 1 if there is no conflict in any size on operand J for
1739 instruction template T. */
1740
1741static INLINE int
1742match_mem_size (const insn_template *t, unsigned int j)
1743{
1744 return (match_reg_size (t, j)
1745 && !((i.types[j].bitfield.unspecified
1746 && !t->operand_types[j].bitfield.unspecified)
1747 || (i.types[j].bitfield.fword
1748 && !t->operand_types[j].bitfield.fword)
1749 || (i.types[j].bitfield.tbyte
1750 && !t->operand_types[j].bitfield.tbyte)
1751 || (i.types[j].bitfield.xmmword
1752 && !t->operand_types[j].bitfield.xmmword)
1753 || (i.types[j].bitfield.ymmword
1754 && !t->operand_types[j].bitfield.ymmword)
1755 || (i.types[j].bitfield.zmmword
1756 && !t->operand_types[j].bitfield.zmmword)));
1757}
1758
1759/* Return 1 if there is no size conflict on any operands for
1760 instruction template T. */
1761
1762static INLINE int
1763operand_size_match (const insn_template *t)
1764{
1765 unsigned int j;
1766 int match = 1;
1767
1768 /* Don't check jump instructions. */
1769 if (t->opcode_modifier.jump
1770 || t->opcode_modifier.jumpbyte
1771 || t->opcode_modifier.jumpdword
1772 || t->opcode_modifier.jumpintersegment)
1773 return match;
1774
1775 /* Check memory and accumulator operand size. */
1776 for (j = 0; j < i.operands; j++)
1777 {
1778 if (t->operand_types[j].bitfield.anysize)
1779 continue;
1780
1781 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1782 {
1783 match = 0;
1784 break;
1785 }
1786
1787 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1788 {
1789 match = 0;
1790 break;
1791 }
1792 }
1793
1794 if (match)
1795 return match;
1796 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1797 {
1798mismatch:
1799 i.error = operand_size_mismatch;
1800 return 0;
1801 }
1802
1803 /* Check reverse. */
1804 gas_assert (i.operands == 2);
1805
1806 match = 1;
1807 for (j = 0; j < 2; j++)
1808 {
1809 if (t->operand_types[j].bitfield.acc
1810 && !match_reg_size (t, j ? 0 : 1))
1811 goto mismatch;
1812
1813 if (i.types[j].bitfield.mem
1814 && !match_mem_size (t, j ? 0 : 1))
1815 goto mismatch;
1816 }
1817
1818 return match;
1819}
1820
1821static INLINE int
1822operand_type_match (i386_operand_type overlap,
1823 i386_operand_type given)
1824{
1825 i386_operand_type temp = overlap;
1826
1827 temp.bitfield.jumpabsolute = 0;
1828 temp.bitfield.unspecified = 0;
1829 temp.bitfield.byte = 0;
1830 temp.bitfield.word = 0;
1831 temp.bitfield.dword = 0;
1832 temp.bitfield.fword = 0;
1833 temp.bitfield.qword = 0;
1834 temp.bitfield.tbyte = 0;
1835 temp.bitfield.xmmword = 0;
1836 temp.bitfield.ymmword = 0;
1837 temp.bitfield.zmmword = 0;
1838 if (operand_type_all_zero (&temp))
1839 goto mismatch;
1840
1841 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1842 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1843 return 1;
1844
1845mismatch:
1846 i.error = operand_type_mismatch;
1847 return 0;
1848}
1849
1850/* If given types g0 and g1 are registers they must be of the same type
1851 unless the expected operand type register overlap is null.
1852 Note that Acc in a template matches every size of reg. */
1853
1854static INLINE int
1855operand_type_register_match (i386_operand_type m0,
1856 i386_operand_type g0,
1857 i386_operand_type t0,
1858 i386_operand_type m1,
1859 i386_operand_type g1,
1860 i386_operand_type t1)
1861{
1862 if (!operand_type_check (g0, reg))
1863 return 1;
1864
1865 if (!operand_type_check (g1, reg))
1866 return 1;
1867
1868 if (g0.bitfield.reg8 == g1.bitfield.reg8
1869 && g0.bitfield.reg16 == g1.bitfield.reg16
1870 && g0.bitfield.reg32 == g1.bitfield.reg32
1871 && g0.bitfield.reg64 == g1.bitfield.reg64)
1872 return 1;
1873
1874 if (m0.bitfield.acc)
1875 {
1876 t0.bitfield.reg8 = 1;
1877 t0.bitfield.reg16 = 1;
1878 t0.bitfield.reg32 = 1;
1879 t0.bitfield.reg64 = 1;
1880 }
1881
1882 if (m1.bitfield.acc)
1883 {
1884 t1.bitfield.reg8 = 1;
1885 t1.bitfield.reg16 = 1;
1886 t1.bitfield.reg32 = 1;
1887 t1.bitfield.reg64 = 1;
1888 }
1889
1890 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1891 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1892 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1893 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1894 return 1;
1895
1896 i.error = register_type_mismatch;
1897
1898 return 0;
1899}
1900
1901static INLINE unsigned int
1902register_number (const reg_entry *r)
1903{
1904 unsigned int nr = r->reg_num;
1905
1906 if (r->reg_flags & RegRex)
1907 nr += 8;
1908
1909 return nr;
1910}
1911
1912static INLINE unsigned int
1913mode_from_disp_size (i386_operand_type t)
1914{
1915 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
1916 return 1;
1917 else if (t.bitfield.disp16
1918 || t.bitfield.disp32
1919 || t.bitfield.disp32s)
1920 return 2;
1921 else
1922 return 0;
1923}
1924
1925static INLINE int
1926fits_in_signed_byte (offsetT num)
1927{
1928 return (num >= -128) && (num <= 127);
1929}
1930
1931static INLINE int
1932fits_in_unsigned_byte (offsetT num)
1933{
1934 return (num & 0xff) == num;
1935}
1936
1937static INLINE int
1938fits_in_unsigned_word (offsetT num)
1939{
1940 return (num & 0xffff) == num;
1941}
1942
1943static INLINE int
1944fits_in_signed_word (offsetT num)
1945{
1946 return (-32768 <= num) && (num <= 32767);
1947}
1948
1949static INLINE int
1950fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
1951{
1952#ifndef BFD64
1953 return 1;
1954#else
1955 return (!(((offsetT) -1 << 31) & num)
1956 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1957#endif
1958} /* fits_in_signed_long() */
1959
1960static INLINE int
1961fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
1962{
1963#ifndef BFD64
1964 return 1;
1965#else
1966 return (num & (((offsetT) 2 << 31) - 1)) == num;
1967#endif
1968} /* fits_in_unsigned_long() */
1969
1970static INLINE int
1971fits_in_vec_disp8 (offsetT num)
1972{
1973 int shift = i.memshift;
1974 unsigned int mask;
1975
1976 if (shift == -1)
1977 abort ();
1978
1979 mask = (1 << shift) - 1;
1980
1981 /* Return 0 if NUM isn't properly aligned. */
1982 if ((num & mask))
1983 return 0;
1984
1985 /* Check if NUM will fit in 8bit after shift. */
1986 return fits_in_signed_byte (num >> shift);
1987}
1988
1989static INLINE int
1990fits_in_imm4 (offsetT num)
1991{
1992 return (num & 0xf) == num;
1993}
1994
1995static i386_operand_type
1996smallest_imm_type (offsetT num)
1997{
1998 i386_operand_type t;
1999
2000 operand_type_set (&t, 0);
2001 t.bitfield.imm64 = 1;
2002
2003 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2004 {
2005 /* This code is disabled on the 486 because all the Imm1 forms
2006 in the opcode table are slower on the i486. They're the
2007 versions with the implicitly specified single-position
2008 displacement, which has another syntax if you really want to
2009 use that form. */
2010 t.bitfield.imm1 = 1;
2011 t.bitfield.imm8 = 1;
2012 t.bitfield.imm8s = 1;
2013 t.bitfield.imm16 = 1;
2014 t.bitfield.imm32 = 1;
2015 t.bitfield.imm32s = 1;
2016 }
2017 else if (fits_in_signed_byte (num))
2018 {
2019 t.bitfield.imm8 = 1;
2020 t.bitfield.imm8s = 1;
2021 t.bitfield.imm16 = 1;
2022 t.bitfield.imm32 = 1;
2023 t.bitfield.imm32s = 1;
2024 }
2025 else if (fits_in_unsigned_byte (num))
2026 {
2027 t.bitfield.imm8 = 1;
2028 t.bitfield.imm16 = 1;
2029 t.bitfield.imm32 = 1;
2030 t.bitfield.imm32s = 1;
2031 }
2032 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2033 {
2034 t.bitfield.imm16 = 1;
2035 t.bitfield.imm32 = 1;
2036 t.bitfield.imm32s = 1;
2037 }
2038 else if (fits_in_signed_long (num))
2039 {
2040 t.bitfield.imm32 = 1;
2041 t.bitfield.imm32s = 1;
2042 }
2043 else if (fits_in_unsigned_long (num))
2044 t.bitfield.imm32 = 1;
2045
2046 return t;
2047}
2048
2049static offsetT
2050offset_in_range (offsetT val, int size)
2051{
2052 addressT mask;
2053
2054 switch (size)
2055 {
2056 case 1: mask = ((addressT) 1 << 8) - 1; break;
2057 case 2: mask = ((addressT) 1 << 16) - 1; break;
2058 case 4: mask = ((addressT) 2 << 31) - 1; break;
2059#ifdef BFD64
2060 case 8: mask = ((addressT) 2 << 63) - 1; break;
2061#endif
2062 default: abort ();
2063 }
2064
2065#ifdef BFD64
2066 /* If BFD64, sign extend val for 32bit address mode. */
2067 if (flag_code != CODE_64BIT
2068 || i.prefix[ADDR_PREFIX])
2069 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2070 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2071#endif
2072
2073 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2074 {
2075 char buf1[40], buf2[40];
2076
2077 sprint_value (buf1, val);
2078 sprint_value (buf2, val & mask);
2079 as_warn (_("%s shortened to %s"), buf1, buf2);
2080 }
2081 return val & mask;
2082}
2083
2084enum PREFIX_GROUP
2085{
2086 PREFIX_EXIST = 0,
2087 PREFIX_LOCK,
2088 PREFIX_REP,
2089 PREFIX_OTHER
2090};
2091
2092/* Returns
2093 a. PREFIX_EXIST if attempting to add a prefix where one from the
2094 same class already exists.
2095 b. PREFIX_LOCK if lock prefix is added.
2096 c. PREFIX_REP if rep/repne prefix is added.
2097 d. PREFIX_OTHER if other prefix is added.
2098 */
2099
2100static enum PREFIX_GROUP
2101add_prefix (unsigned int prefix)
2102{
2103 enum PREFIX_GROUP ret = PREFIX_OTHER;
2104 unsigned int q;
2105
2106 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2107 && flag_code == CODE_64BIT)
2108 {
2109 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2110 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2111 && (prefix & (REX_R | REX_X | REX_B))))
2112 ret = PREFIX_EXIST;
2113 q = REX_PREFIX;
2114 }
2115 else
2116 {
2117 switch (prefix)
2118 {
2119 default:
2120 abort ();
2121
2122 case CS_PREFIX_OPCODE:
2123 case DS_PREFIX_OPCODE:
2124 case ES_PREFIX_OPCODE:
2125 case FS_PREFIX_OPCODE:
2126 case GS_PREFIX_OPCODE:
2127 case SS_PREFIX_OPCODE:
2128 q = SEG_PREFIX;
2129 break;
2130
2131 case REPNE_PREFIX_OPCODE:
2132 case REPE_PREFIX_OPCODE:
2133 q = REP_PREFIX;
2134 ret = PREFIX_REP;
2135 break;
2136
2137 case LOCK_PREFIX_OPCODE:
2138 q = LOCK_PREFIX;
2139 ret = PREFIX_LOCK;
2140 break;
2141
2142 case FWAIT_OPCODE:
2143 q = WAIT_PREFIX;
2144 break;
2145
2146 case ADDR_PREFIX_OPCODE:
2147 q = ADDR_PREFIX;
2148 break;
2149
2150 case DATA_PREFIX_OPCODE:
2151 q = DATA_PREFIX;
2152 break;
2153 }
2154 if (i.prefix[q] != 0)
2155 ret = PREFIX_EXIST;
2156 }
2157
2158 if (ret)
2159 {
2160 if (!i.prefix[q])
2161 ++i.prefixes;
2162 i.prefix[q] |= prefix;
2163 }
2164 else
2165 as_bad (_("same type of prefix used twice"));
2166
2167 return ret;
2168}
2169
2170static void
2171update_code_flag (int value, int check)
2172{
2173 PRINTF_LIKE ((*as_error));
2174
2175 flag_code = (enum flag_code) value;
2176 if (flag_code == CODE_64BIT)
2177 {
2178 cpu_arch_flags.bitfield.cpu64 = 1;
2179 cpu_arch_flags.bitfield.cpuno64 = 0;
2180 }
2181 else
2182 {
2183 cpu_arch_flags.bitfield.cpu64 = 0;
2184 cpu_arch_flags.bitfield.cpuno64 = 1;
2185 }
2186 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2187 {
2188 if (check)
2189 as_error = as_fatal;
2190 else
2191 as_error = as_bad;
2192 (*as_error) (_("64bit mode not supported on `%s'."),
2193 cpu_arch_name ? cpu_arch_name : default_arch);
2194 }
2195 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2196 {
2197 if (check)
2198 as_error = as_fatal;
2199 else
2200 as_error = as_bad;
2201 (*as_error) (_("32bit mode not supported on `%s'."),
2202 cpu_arch_name ? cpu_arch_name : default_arch);
2203 }
2204 stackop_size = '\0';
2205}
2206
2207static void
2208set_code_flag (int value)
2209{
2210 update_code_flag (value, 0);
2211}
2212
2213static void
2214set_16bit_gcc_code_flag (int new_code_flag)
2215{
2216 flag_code = (enum flag_code) new_code_flag;
2217 if (flag_code != CODE_16BIT)
2218 abort ();
2219 cpu_arch_flags.bitfield.cpu64 = 0;
2220 cpu_arch_flags.bitfield.cpuno64 = 1;
2221 stackop_size = LONG_MNEM_SUFFIX;
2222}
2223
2224static void
2225set_intel_syntax (int syntax_flag)
2226{
2227 /* Find out if register prefixing is specified. */
2228 int ask_naked_reg = 0;
2229
2230 SKIP_WHITESPACE ();
2231 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2232 {
2233 char *string = input_line_pointer;
2234 int e = get_symbol_end ();
2235
2236 if (strcmp (string, "prefix") == 0)
2237 ask_naked_reg = 1;
2238 else if (strcmp (string, "noprefix") == 0)
2239 ask_naked_reg = -1;
2240 else
2241 as_bad (_("bad argument to syntax directive."));
2242 *input_line_pointer = e;
2243 }
2244 demand_empty_rest_of_line ();
2245
2246 intel_syntax = syntax_flag;
2247
2248 if (ask_naked_reg == 0)
2249 allow_naked_reg = (intel_syntax
2250 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2251 else
2252 allow_naked_reg = (ask_naked_reg < 0);
2253
2254 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2255
2256 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2257 identifier_chars['$'] = intel_syntax ? '$' : 0;
2258 register_prefix = allow_naked_reg ? "" : "%";
2259}
2260
2261static void
2262set_intel_mnemonic (int mnemonic_flag)
2263{
2264 intel_mnemonic = mnemonic_flag;
2265}
2266
2267static void
2268set_allow_index_reg (int flag)
2269{
2270 allow_index_reg = flag;
2271}
2272
2273static void
2274set_check (int what)
2275{
2276 enum check_kind *kind;
2277 const char *str;
2278
2279 if (what)
2280 {
2281 kind = &operand_check;
2282 str = "operand";
2283 }
2284 else
2285 {
2286 kind = &sse_check;
2287 str = "sse";
2288 }
2289
2290 SKIP_WHITESPACE ();
2291
2292 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2293 {
2294 char *string = input_line_pointer;
2295 int e = get_symbol_end ();
2296
2297 if (strcmp (string, "none") == 0)
2298 *kind = check_none;
2299 else if (strcmp (string, "warning") == 0)
2300 *kind = check_warning;
2301 else if (strcmp (string, "error") == 0)
2302 *kind = check_error;
2303 else
2304 as_bad (_("bad argument to %s_check directive."), str);
2305 *input_line_pointer = e;
2306 }
2307 else
2308 as_bad (_("missing argument for %s_check directive"), str);
2309
2310 demand_empty_rest_of_line ();
2311}
2312
2313static void
2314check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2315 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2316{
2317#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2318 static const char *arch;
2319
2320 /* Intel LIOM is only supported on ELF. */
2321 if (!IS_ELF)
2322 return;
2323
2324 if (!arch)
2325 {
2326 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2327 use default_arch. */
2328 arch = cpu_arch_name;
2329 if (!arch)
2330 arch = default_arch;
2331 }
2332
2333 /* If we are targeting Intel L1OM, we must enable it. */
2334 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2335 || new_flag.bitfield.cpul1om)
2336 return;
2337
2338 /* If we are targeting Intel K1OM, we must enable it. */
2339 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2340 || new_flag.bitfield.cpuk1om)
2341 return;
2342
2343 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2344#endif
2345}
2346
2347static void
2348set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2349{
2350 SKIP_WHITESPACE ();
2351
2352 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2353 {
2354 char *string = input_line_pointer;
2355 int e = get_symbol_end ();
2356 unsigned int j;
2357 i386_cpu_flags flags;
2358
2359 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2360 {
2361 if (strcmp (string, cpu_arch[j].name) == 0)
2362 {
2363 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2364
2365 if (*string != '.')
2366 {
2367 cpu_arch_name = cpu_arch[j].name;
2368 cpu_sub_arch_name = NULL;
2369 cpu_arch_flags = cpu_arch[j].flags;
2370 if (flag_code == CODE_64BIT)
2371 {
2372 cpu_arch_flags.bitfield.cpu64 = 1;
2373 cpu_arch_flags.bitfield.cpuno64 = 0;
2374 }
2375 else
2376 {
2377 cpu_arch_flags.bitfield.cpu64 = 0;
2378 cpu_arch_flags.bitfield.cpuno64 = 1;
2379 }
2380 cpu_arch_isa = cpu_arch[j].type;
2381 cpu_arch_isa_flags = cpu_arch[j].flags;
2382 if (!cpu_arch_tune_set)
2383 {
2384 cpu_arch_tune = cpu_arch_isa;
2385 cpu_arch_tune_flags = cpu_arch_isa_flags;
2386 }
2387 break;
2388 }
2389
2390 if (!cpu_arch[j].negated)
2391 flags = cpu_flags_or (cpu_arch_flags,
2392 cpu_arch[j].flags);
2393 else
2394 flags = cpu_flags_and_not (cpu_arch_flags,
2395 cpu_arch[j].flags);
2396 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2397 {
2398 if (cpu_sub_arch_name)
2399 {
2400 char *name = cpu_sub_arch_name;
2401 cpu_sub_arch_name = concat (name,
2402 cpu_arch[j].name,
2403 (const char *) NULL);
2404 free (name);
2405 }
2406 else
2407 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2408 cpu_arch_flags = flags;
2409 cpu_arch_isa_flags = flags;
2410 }
2411 *input_line_pointer = e;
2412 demand_empty_rest_of_line ();
2413 return;
2414 }
2415 }
2416 if (j >= ARRAY_SIZE (cpu_arch))
2417 as_bad (_("no such architecture: `%s'"), string);
2418
2419 *input_line_pointer = e;
2420 }
2421 else
2422 as_bad (_("missing cpu architecture"));
2423
2424 no_cond_jump_promotion = 0;
2425 if (*input_line_pointer == ','
2426 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2427 {
2428 char *string = ++input_line_pointer;
2429 int e = get_symbol_end ();
2430
2431 if (strcmp (string, "nojumps") == 0)
2432 no_cond_jump_promotion = 1;
2433 else if (strcmp (string, "jumps") == 0)
2434 ;
2435 else
2436 as_bad (_("no such architecture modifier: `%s'"), string);
2437
2438 *input_line_pointer = e;
2439 }
2440
2441 demand_empty_rest_of_line ();
2442}
2443
2444enum bfd_architecture
2445i386_arch (void)
2446{
2447 if (cpu_arch_isa == PROCESSOR_L1OM)
2448 {
2449 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2450 || flag_code != CODE_64BIT)
2451 as_fatal (_("Intel L1OM is 64bit ELF only"));
2452 return bfd_arch_l1om;
2453 }
2454 else if (cpu_arch_isa == PROCESSOR_K1OM)
2455 {
2456 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2457 || flag_code != CODE_64BIT)
2458 as_fatal (_("Intel K1OM is 64bit ELF only"));
2459 return bfd_arch_k1om;
2460 }
2461 else
2462 return bfd_arch_i386;
2463}
2464
2465unsigned long
2466i386_mach (void)
2467{
2468 if (!strncmp (default_arch, "x86_64", 6))
2469 {
2470 if (cpu_arch_isa == PROCESSOR_L1OM)
2471 {
2472 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2473 || default_arch[6] != '\0')
2474 as_fatal (_("Intel L1OM is 64bit ELF only"));
2475 return bfd_mach_l1om;
2476 }
2477 else if (cpu_arch_isa == PROCESSOR_K1OM)
2478 {
2479 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2480 || default_arch[6] != '\0')
2481 as_fatal (_("Intel K1OM is 64bit ELF only"));
2482 return bfd_mach_k1om;
2483 }
2484 else if (default_arch[6] == '\0')
2485 return bfd_mach_x86_64;
2486 else
2487 return bfd_mach_x64_32;
2488 }
2489 else if (!strcmp (default_arch, "i386"))
2490 return bfd_mach_i386_i386;
2491 else
2492 as_fatal (_("unknown architecture"));
2493}
2494\f
2495void
2496md_begin (void)
2497{
2498 const char *hash_err;
2499
2500 /* Initialize op_hash hash table. */
2501 op_hash = hash_new ();
2502
2503 {
2504 const insn_template *optab;
2505 templates *core_optab;
2506
2507 /* Setup for loop. */
2508 optab = i386_optab;
2509 core_optab = (templates *) xmalloc (sizeof (templates));
2510 core_optab->start = optab;
2511
2512 while (1)
2513 {
2514 ++optab;
2515 if (optab->name == NULL
2516 || strcmp (optab->name, (optab - 1)->name) != 0)
2517 {
2518 /* different name --> ship out current template list;
2519 add to hash table; & begin anew. */
2520 core_optab->end = optab;
2521 hash_err = hash_insert (op_hash,
2522 (optab - 1)->name,
2523 (void *) core_optab);
2524 if (hash_err)
2525 {
2526 as_fatal (_("can't hash %s: %s"),
2527 (optab - 1)->name,
2528 hash_err);
2529 }
2530 if (optab->name == NULL)
2531 break;
2532 core_optab = (templates *) xmalloc (sizeof (templates));
2533 core_optab->start = optab;
2534 }
2535 }
2536 }
2537
2538 /* Initialize reg_hash hash table. */
2539 reg_hash = hash_new ();
2540 {
2541 const reg_entry *regtab;
2542 unsigned int regtab_size = i386_regtab_size;
2543
2544 for (regtab = i386_regtab; regtab_size--; regtab++)
2545 {
2546 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2547 if (hash_err)
2548 as_fatal (_("can't hash %s: %s"),
2549 regtab->reg_name,
2550 hash_err);
2551 }
2552 }
2553
2554 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2555 {
2556 int c;
2557 char *p;
2558
2559 for (c = 0; c < 256; c++)
2560 {
2561 if (ISDIGIT (c))
2562 {
2563 digit_chars[c] = c;
2564 mnemonic_chars[c] = c;
2565 register_chars[c] = c;
2566 operand_chars[c] = c;
2567 }
2568 else if (ISLOWER (c))
2569 {
2570 mnemonic_chars[c] = c;
2571 register_chars[c] = c;
2572 operand_chars[c] = c;
2573 }
2574 else if (ISUPPER (c))
2575 {
2576 mnemonic_chars[c] = TOLOWER (c);
2577 register_chars[c] = mnemonic_chars[c];
2578 operand_chars[c] = c;
2579 }
2580 else if (c == '{' || c == '}')
2581 operand_chars[c] = c;
2582
2583 if (ISALPHA (c) || ISDIGIT (c))
2584 identifier_chars[c] = c;
2585 else if (c >= 128)
2586 {
2587 identifier_chars[c] = c;
2588 operand_chars[c] = c;
2589 }
2590 }
2591
2592#ifdef LEX_AT
2593 identifier_chars['@'] = '@';
2594#endif
2595#ifdef LEX_QM
2596 identifier_chars['?'] = '?';
2597 operand_chars['?'] = '?';
2598#endif
2599 digit_chars['-'] = '-';
2600 mnemonic_chars['_'] = '_';
2601 mnemonic_chars['-'] = '-';
2602 mnemonic_chars['.'] = '.';
2603 identifier_chars['_'] = '_';
2604 identifier_chars['.'] = '.';
2605
2606 for (p = operand_special_chars; *p != '\0'; p++)
2607 operand_chars[(unsigned char) *p] = *p;
2608 }
2609
2610 if (flag_code == CODE_64BIT)
2611 {
2612#if defined (OBJ_COFF) && defined (TE_PE)
2613 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2614 ? 32 : 16);
2615#else
2616 x86_dwarf2_return_column = 16;
2617#endif
2618 x86_cie_data_alignment = -8;
2619 }
2620 else
2621 {
2622 x86_dwarf2_return_column = 8;
2623 x86_cie_data_alignment = -4;
2624 }
2625}
2626
2627void
2628i386_print_statistics (FILE *file)
2629{
2630 hash_print_statistics (file, "i386 opcode", op_hash);
2631 hash_print_statistics (file, "i386 register", reg_hash);
2632}
2633\f
2634#ifdef DEBUG386
2635
2636/* Debugging routines for md_assemble. */
2637static void pte (insn_template *);
2638static void pt (i386_operand_type);
2639static void pe (expressionS *);
2640static void ps (symbolS *);
2641
2642static void
2643pi (char *line, i386_insn *x)
2644{
2645 unsigned int j;
2646
2647 fprintf (stdout, "%s: template ", line);
2648 pte (&x->tm);
2649 fprintf (stdout, " address: base %s index %s scale %x\n",
2650 x->base_reg ? x->base_reg->reg_name : "none",
2651 x->index_reg ? x->index_reg->reg_name : "none",
2652 x->log2_scale_factor);
2653 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2654 x->rm.mode, x->rm.reg, x->rm.regmem);
2655 fprintf (stdout, " sib: base %x index %x scale %x\n",
2656 x->sib.base, x->sib.index, x->sib.scale);
2657 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2658 (x->rex & REX_W) != 0,
2659 (x->rex & REX_R) != 0,
2660 (x->rex & REX_X) != 0,
2661 (x->rex & REX_B) != 0);
2662 for (j = 0; j < x->operands; j++)
2663 {
2664 fprintf (stdout, " #%d: ", j + 1);
2665 pt (x->types[j]);
2666 fprintf (stdout, "\n");
2667 if (x->types[j].bitfield.reg8
2668 || x->types[j].bitfield.reg16
2669 || x->types[j].bitfield.reg32
2670 || x->types[j].bitfield.reg64
2671 || x->types[j].bitfield.regmmx
2672 || x->types[j].bitfield.regxmm
2673 || x->types[j].bitfield.regymm
2674 || x->types[j].bitfield.regzmm
2675 || x->types[j].bitfield.sreg2
2676 || x->types[j].bitfield.sreg3
2677 || x->types[j].bitfield.control
2678 || x->types[j].bitfield.debug
2679 || x->types[j].bitfield.test)
2680 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2681 if (operand_type_check (x->types[j], imm))
2682 pe (x->op[j].imms);
2683 if (operand_type_check (x->types[j], disp))
2684 pe (x->op[j].disps);
2685 }
2686}
2687
2688static void
2689pte (insn_template *t)
2690{
2691 unsigned int j;
2692 fprintf (stdout, " %d operands ", t->operands);
2693 fprintf (stdout, "opcode %x ", t->base_opcode);
2694 if (t->extension_opcode != None)
2695 fprintf (stdout, "ext %x ", t->extension_opcode);
2696 if (t->opcode_modifier.d)
2697 fprintf (stdout, "D");
2698 if (t->opcode_modifier.w)
2699 fprintf (stdout, "W");
2700 fprintf (stdout, "\n");
2701 for (j = 0; j < t->operands; j++)
2702 {
2703 fprintf (stdout, " #%d type ", j + 1);
2704 pt (t->operand_types[j]);
2705 fprintf (stdout, "\n");
2706 }
2707}
2708
2709static void
2710pe (expressionS *e)
2711{
2712 fprintf (stdout, " operation %d\n", e->X_op);
2713 fprintf (stdout, " add_number %ld (%lx)\n",
2714 (long) e->X_add_number, (long) e->X_add_number);
2715 if (e->X_add_symbol)
2716 {
2717 fprintf (stdout, " add_symbol ");
2718 ps (e->X_add_symbol);
2719 fprintf (stdout, "\n");
2720 }
2721 if (e->X_op_symbol)
2722 {
2723 fprintf (stdout, " op_symbol ");
2724 ps (e->X_op_symbol);
2725 fprintf (stdout, "\n");
2726 }
2727}
2728
2729static void
2730ps (symbolS *s)
2731{
2732 fprintf (stdout, "%s type %s%s",
2733 S_GET_NAME (s),
2734 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2735 segment_name (S_GET_SEGMENT (s)));
2736}
2737
2738static struct type_name
2739 {
2740 i386_operand_type mask;
2741 const char *name;
2742 }
2743const type_names[] =
2744{
2745 { OPERAND_TYPE_REG8, "r8" },
2746 { OPERAND_TYPE_REG16, "r16" },
2747 { OPERAND_TYPE_REG32, "r32" },
2748 { OPERAND_TYPE_REG64, "r64" },
2749 { OPERAND_TYPE_IMM8, "i8" },
2750 { OPERAND_TYPE_IMM8, "i8s" },
2751 { OPERAND_TYPE_IMM16, "i16" },
2752 { OPERAND_TYPE_IMM32, "i32" },
2753 { OPERAND_TYPE_IMM32S, "i32s" },
2754 { OPERAND_TYPE_IMM64, "i64" },
2755 { OPERAND_TYPE_IMM1, "i1" },
2756 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2757 { OPERAND_TYPE_DISP8, "d8" },
2758 { OPERAND_TYPE_DISP16, "d16" },
2759 { OPERAND_TYPE_DISP32, "d32" },
2760 { OPERAND_TYPE_DISP32S, "d32s" },
2761 { OPERAND_TYPE_DISP64, "d64" },
2762 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
2763 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2764 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2765 { OPERAND_TYPE_CONTROL, "control reg" },
2766 { OPERAND_TYPE_TEST, "test reg" },
2767 { OPERAND_TYPE_DEBUG, "debug reg" },
2768 { OPERAND_TYPE_FLOATREG, "FReg" },
2769 { OPERAND_TYPE_FLOATACC, "FAcc" },
2770 { OPERAND_TYPE_SREG2, "SReg2" },
2771 { OPERAND_TYPE_SREG3, "SReg3" },
2772 { OPERAND_TYPE_ACC, "Acc" },
2773 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2774 { OPERAND_TYPE_REGMMX, "rMMX" },
2775 { OPERAND_TYPE_REGXMM, "rXMM" },
2776 { OPERAND_TYPE_REGYMM, "rYMM" },
2777 { OPERAND_TYPE_REGZMM, "rZMM" },
2778 { OPERAND_TYPE_REGMASK, "Mask reg" },
2779 { OPERAND_TYPE_ESSEG, "es" },
2780};
2781
2782static void
2783pt (i386_operand_type t)
2784{
2785 unsigned int j;
2786 i386_operand_type a;
2787
2788 for (j = 0; j < ARRAY_SIZE (type_names); j++)
2789 {
2790 a = operand_type_and (t, type_names[j].mask);
2791 if (!operand_type_all_zero (&a))
2792 fprintf (stdout, "%s, ", type_names[j].name);
2793 }
2794 fflush (stdout);
2795}
2796
2797#endif /* DEBUG386 */
2798\f
2799static bfd_reloc_code_real_type
2800reloc (unsigned int size,
2801 int pcrel,
2802 int sign,
2803 bfd_reloc_code_real_type other)
2804{
2805 if (other != NO_RELOC)
2806 {
2807 reloc_howto_type *rel;
2808
2809 if (size == 8)
2810 switch (other)
2811 {
2812 case BFD_RELOC_X86_64_GOT32:
2813 return BFD_RELOC_X86_64_GOT64;
2814 break;
2815 case BFD_RELOC_X86_64_PLTOFF64:
2816 return BFD_RELOC_X86_64_PLTOFF64;
2817 break;
2818 case BFD_RELOC_X86_64_GOTPC32:
2819 other = BFD_RELOC_X86_64_GOTPC64;
2820 break;
2821 case BFD_RELOC_X86_64_GOTPCREL:
2822 other = BFD_RELOC_X86_64_GOTPCREL64;
2823 break;
2824 case BFD_RELOC_X86_64_TPOFF32:
2825 other = BFD_RELOC_X86_64_TPOFF64;
2826 break;
2827 case BFD_RELOC_X86_64_DTPOFF32:
2828 other = BFD_RELOC_X86_64_DTPOFF64;
2829 break;
2830 default:
2831 break;
2832 }
2833
2834#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2835 if (other == BFD_RELOC_SIZE32)
2836 {
2837 if (size == 8)
2838 return BFD_RELOC_SIZE64;
2839 if (pcrel)
2840 as_bad (_("there are no pc-relative size relocations"));
2841 }
2842#endif
2843
2844 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2845 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
2846 sign = -1;
2847
2848 rel = bfd_reloc_type_lookup (stdoutput, other);
2849 if (!rel)
2850 as_bad (_("unknown relocation (%u)"), other);
2851 else if (size != bfd_get_reloc_size (rel))
2852 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2853 bfd_get_reloc_size (rel),
2854 size);
2855 else if (pcrel && !rel->pc_relative)
2856 as_bad (_("non-pc-relative relocation for pc-relative field"));
2857 else if ((rel->complain_on_overflow == complain_overflow_signed
2858 && !sign)
2859 || (rel->complain_on_overflow == complain_overflow_unsigned
2860 && sign > 0))
2861 as_bad (_("relocated field and relocation type differ in signedness"));
2862 else
2863 return other;
2864 return NO_RELOC;
2865 }
2866
2867 if (pcrel)
2868 {
2869 if (!sign)
2870 as_bad (_("there are no unsigned pc-relative relocations"));
2871 switch (size)
2872 {
2873 case 1: return BFD_RELOC_8_PCREL;
2874 case 2: return BFD_RELOC_16_PCREL;
2875 case 4: return BFD_RELOC_32_PCREL;
2876 case 8: return BFD_RELOC_64_PCREL;
2877 }
2878 as_bad (_("cannot do %u byte pc-relative relocation"), size);
2879 }
2880 else
2881 {
2882 if (sign > 0)
2883 switch (size)
2884 {
2885 case 4: return BFD_RELOC_X86_64_32S;
2886 }
2887 else
2888 switch (size)
2889 {
2890 case 1: return BFD_RELOC_8;
2891 case 2: return BFD_RELOC_16;
2892 case 4: return BFD_RELOC_32;
2893 case 8: return BFD_RELOC_64;
2894 }
2895 as_bad (_("cannot do %s %u byte relocation"),
2896 sign > 0 ? "signed" : "unsigned", size);
2897 }
2898
2899 return NO_RELOC;
2900}
2901
2902/* Here we decide which fixups can be adjusted to make them relative to
2903 the beginning of the section instead of the symbol. Basically we need
2904 to make sure that the dynamic relocations are done correctly, so in
2905 some cases we force the original symbol to be used. */
2906
2907int
2908tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2909{
2910#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2911 if (!IS_ELF)
2912 return 1;
2913
2914 /* Don't adjust pc-relative references to merge sections in 64-bit
2915 mode. */
2916 if (use_rela_relocations
2917 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2918 && fixP->fx_pcrel)
2919 return 0;
2920
2921 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2922 and changed later by validate_fix. */
2923 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2924 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2925 return 0;
2926
2927 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2928 for size relocations. */
2929 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2930 || fixP->fx_r_type == BFD_RELOC_SIZE64
2931 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2932 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2933 || fixP->fx_r_type == BFD_RELOC_386_GOT32
2934 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2935 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2936 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2937 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2938 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2939 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2940 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2941 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2942 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2943 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2944 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2945 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2946 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2947 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2948 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2949 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2950 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2951 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2952 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2953 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2954 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2955 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2956 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2957 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2958 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2959 return 0;
2960#endif
2961 return 1;
2962}
2963
2964static int
2965intel_float_operand (const char *mnemonic)
2966{
2967 /* Note that the value returned is meaningful only for opcodes with (memory)
2968 operands, hence the code here is free to improperly handle opcodes that
2969 have no operands (for better performance and smaller code). */
2970
2971 if (mnemonic[0] != 'f')
2972 return 0; /* non-math */
2973
2974 switch (mnemonic[1])
2975 {
2976 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2977 the fs segment override prefix not currently handled because no
2978 call path can make opcodes without operands get here */
2979 case 'i':
2980 return 2 /* integer op */;
2981 case 'l':
2982 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2983 return 3; /* fldcw/fldenv */
2984 break;
2985 case 'n':
2986 if (mnemonic[2] != 'o' /* fnop */)
2987 return 3; /* non-waiting control op */
2988 break;
2989 case 'r':
2990 if (mnemonic[2] == 's')
2991 return 3; /* frstor/frstpm */
2992 break;
2993 case 's':
2994 if (mnemonic[2] == 'a')
2995 return 3; /* fsave */
2996 if (mnemonic[2] == 't')
2997 {
2998 switch (mnemonic[3])
2999 {
3000 case 'c': /* fstcw */
3001 case 'd': /* fstdw */
3002 case 'e': /* fstenv */
3003 case 's': /* fsts[gw] */
3004 return 3;
3005 }
3006 }
3007 break;
3008 case 'x':
3009 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3010 return 0; /* fxsave/fxrstor are not really math ops */
3011 break;
3012 }
3013
3014 return 1;
3015}
3016
3017/* Build the VEX prefix. */
3018
3019static void
3020build_vex_prefix (const insn_template *t)
3021{
3022 unsigned int register_specifier;
3023 unsigned int implied_prefix;
3024 unsigned int vector_length;
3025
3026 /* Check register specifier. */
3027 if (i.vex.register_specifier)
3028 {
3029 register_specifier =
3030 ~register_number (i.vex.register_specifier) & 0xf;
3031 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3032 }
3033 else
3034 register_specifier = 0xf;
3035
3036 /* Use 2-byte VEX prefix by swappping destination and source
3037 operand. */
3038 if (!i.swap_operand
3039 && i.operands == i.reg_operands
3040 && i.tm.opcode_modifier.vexopcode == VEX0F
3041 && i.tm.opcode_modifier.s
3042 && i.rex == REX_B)
3043 {
3044 unsigned int xchg = i.operands - 1;
3045 union i386_op temp_op;
3046 i386_operand_type temp_type;
3047
3048 temp_type = i.types[xchg];
3049 i.types[xchg] = i.types[0];
3050 i.types[0] = temp_type;
3051 temp_op = i.op[xchg];
3052 i.op[xchg] = i.op[0];
3053 i.op[0] = temp_op;
3054
3055 gas_assert (i.rm.mode == 3);
3056
3057 i.rex = REX_R;
3058 xchg = i.rm.regmem;
3059 i.rm.regmem = i.rm.reg;
3060 i.rm.reg = xchg;
3061
3062 /* Use the next insn. */
3063 i.tm = t[1];
3064 }
3065
3066 if (i.tm.opcode_modifier.vex == VEXScalar)
3067 vector_length = avxscalar;
3068 else
3069 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
3070
3071 switch ((i.tm.base_opcode >> 8) & 0xff)
3072 {
3073 case 0:
3074 implied_prefix = 0;
3075 break;
3076 case DATA_PREFIX_OPCODE:
3077 implied_prefix = 1;
3078 break;
3079 case REPE_PREFIX_OPCODE:
3080 implied_prefix = 2;
3081 break;
3082 case REPNE_PREFIX_OPCODE:
3083 implied_prefix = 3;
3084 break;
3085 default:
3086 abort ();
3087 }
3088
3089 /* Use 2-byte VEX prefix if possible. */
3090 if (i.tm.opcode_modifier.vexopcode == VEX0F
3091 && i.tm.opcode_modifier.vexw != VEXW1
3092 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3093 {
3094 /* 2-byte VEX prefix. */
3095 unsigned int r;
3096
3097 i.vex.length = 2;
3098 i.vex.bytes[0] = 0xc5;
3099
3100 /* Check the REX.R bit. */
3101 r = (i.rex & REX_R) ? 0 : 1;
3102 i.vex.bytes[1] = (r << 7
3103 | register_specifier << 3
3104 | vector_length << 2
3105 | implied_prefix);
3106 }
3107 else
3108 {
3109 /* 3-byte VEX prefix. */
3110 unsigned int m, w;
3111
3112 i.vex.length = 3;
3113
3114 switch (i.tm.opcode_modifier.vexopcode)
3115 {
3116 case VEX0F:
3117 m = 0x1;
3118 i.vex.bytes[0] = 0xc4;
3119 break;
3120 case VEX0F38:
3121 m = 0x2;
3122 i.vex.bytes[0] = 0xc4;
3123 break;
3124 case VEX0F3A:
3125 m = 0x3;
3126 i.vex.bytes[0] = 0xc4;
3127 break;
3128 case XOP08:
3129 m = 0x8;
3130 i.vex.bytes[0] = 0x8f;
3131 break;
3132 case XOP09:
3133 m = 0x9;
3134 i.vex.bytes[0] = 0x8f;
3135 break;
3136 case XOP0A:
3137 m = 0xa;
3138 i.vex.bytes[0] = 0x8f;
3139 break;
3140 default:
3141 abort ();
3142 }
3143
3144 /* The high 3 bits of the second VEX byte are 1's compliment
3145 of RXB bits from REX. */
3146 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3147
3148 /* Check the REX.W bit. */
3149 w = (i.rex & REX_W) ? 1 : 0;
3150 if (i.tm.opcode_modifier.vexw)
3151 {
3152 if (w)
3153 abort ();
3154
3155 if (i.tm.opcode_modifier.vexw == VEXW1)
3156 w = 1;
3157 }
3158
3159 i.vex.bytes[2] = (w << 7
3160 | register_specifier << 3
3161 | vector_length << 2
3162 | implied_prefix);
3163 }
3164}
3165
3166/* Build the EVEX prefix. */
3167
3168static void
3169build_evex_prefix (void)
3170{
3171 unsigned int register_specifier;
3172 unsigned int implied_prefix;
3173 unsigned int m, w;
3174 rex_byte vrex_used = 0;
3175
3176 /* Check register specifier. */
3177 if (i.vex.register_specifier)
3178 {
3179 gas_assert ((i.vrex & REX_X) == 0);
3180
3181 register_specifier = i.vex.register_specifier->reg_num;
3182 if ((i.vex.register_specifier->reg_flags & RegRex))
3183 register_specifier += 8;
3184 /* The upper 16 registers are encoded in the fourth byte of the
3185 EVEX prefix. */
3186 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3187 i.vex.bytes[3] = 0x8;
3188 register_specifier = ~register_specifier & 0xf;
3189 }
3190 else
3191 {
3192 register_specifier = 0xf;
3193
3194 /* Encode upper 16 vector index register in the fourth byte of
3195 the EVEX prefix. */
3196 if (!(i.vrex & REX_X))
3197 i.vex.bytes[3] = 0x8;
3198 else
3199 vrex_used |= REX_X;
3200 }
3201
3202 switch ((i.tm.base_opcode >> 8) & 0xff)
3203 {
3204 case 0:
3205 implied_prefix = 0;
3206 break;
3207 case DATA_PREFIX_OPCODE:
3208 implied_prefix = 1;
3209 break;
3210 case REPE_PREFIX_OPCODE:
3211 implied_prefix = 2;
3212 break;
3213 case REPNE_PREFIX_OPCODE:
3214 implied_prefix = 3;
3215 break;
3216 default:
3217 abort ();
3218 }
3219
3220 /* 4 byte EVEX prefix. */
3221 i.vex.length = 4;
3222 i.vex.bytes[0] = 0x62;
3223
3224 /* mmmm bits. */
3225 switch (i.tm.opcode_modifier.vexopcode)
3226 {
3227 case VEX0F:
3228 m = 1;
3229 break;
3230 case VEX0F38:
3231 m = 2;
3232 break;
3233 case VEX0F3A:
3234 m = 3;
3235 break;
3236 default:
3237 abort ();
3238 break;
3239 }
3240
3241 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3242 bits from REX. */
3243 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3244
3245 /* The fifth bit of the second EVEX byte is 1's compliment of the
3246 REX_R bit in VREX. */
3247 if (!(i.vrex & REX_R))
3248 i.vex.bytes[1] |= 0x10;
3249 else
3250 vrex_used |= REX_R;
3251
3252 if ((i.reg_operands + i.imm_operands) == i.operands)
3253 {
3254 /* When all operands are registers, the REX_X bit in REX is not
3255 used. We reuse it to encode the upper 16 registers, which is
3256 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3257 as 1's compliment. */
3258 if ((i.vrex & REX_B))
3259 {
3260 vrex_used |= REX_B;
3261 i.vex.bytes[1] &= ~0x40;
3262 }
3263 }
3264
3265 /* EVEX instructions shouldn't need the REX prefix. */
3266 i.vrex &= ~vrex_used;
3267 gas_assert (i.vrex == 0);
3268
3269 /* Check the REX.W bit. */
3270 w = (i.rex & REX_W) ? 1 : 0;
3271 if (i.tm.opcode_modifier.vexw)
3272 {
3273 if (i.tm.opcode_modifier.vexw == VEXW1)
3274 w = 1;
3275 }
3276 /* If w is not set it means we are dealing with WIG instruction. */
3277 else if (!w)
3278 {
3279 if (evexwig == evexw1)
3280 w = 1;
3281 }
3282
3283 /* Encode the U bit. */
3284 implied_prefix |= 0x4;
3285
3286 /* The third byte of the EVEX prefix. */
3287 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3288
3289 /* The fourth byte of the EVEX prefix. */
3290 /* The zeroing-masking bit. */
3291 if (i.mask && i.mask->zeroing)
3292 i.vex.bytes[3] |= 0x80;
3293
3294 /* Don't always set the broadcast bit if there is no RC. */
3295 if (!i.rounding)
3296 {
3297 /* Encode the vector length. */
3298 unsigned int vec_length;
3299
3300 switch (i.tm.opcode_modifier.evex)
3301 {
3302 case EVEXLIG: /* LL' is ignored */
3303 vec_length = evexlig << 5;
3304 break;
3305 case EVEX128:
3306 vec_length = 0 << 5;
3307 break;
3308 case EVEX256:
3309 vec_length = 1 << 5;
3310 break;
3311 case EVEX512:
3312 vec_length = 2 << 5;
3313 break;
3314 default:
3315 abort ();
3316 break;
3317 }
3318 i.vex.bytes[3] |= vec_length;
3319 /* Encode the broadcast bit. */
3320 if (i.broadcast)
3321 i.vex.bytes[3] |= 0x10;
3322 }
3323 else
3324 {
3325 if (i.rounding->type != saeonly)
3326 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3327 else
3328 i.vex.bytes[3] |= 0x10;
3329 }
3330
3331 if (i.mask && i.mask->mask)
3332 i.vex.bytes[3] |= i.mask->mask->reg_num;
3333}
3334
3335static void
3336process_immext (void)
3337{
3338 expressionS *exp;
3339
3340 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3341 && i.operands > 0)
3342 {
3343 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3344 with an opcode suffix which is coded in the same place as an
3345 8-bit immediate field would be.
3346 Here we check those operands and remove them afterwards. */
3347 unsigned int x;
3348
3349 for (x = 0; x < i.operands; x++)
3350 if (register_number (i.op[x].regs) != x)
3351 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3352 register_prefix, i.op[x].regs->reg_name, x + 1,
3353 i.tm.name);
3354
3355 i.operands = 0;
3356 }
3357
3358 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3359 which is coded in the same place as an 8-bit immediate field
3360 would be. Here we fake an 8-bit immediate operand from the
3361 opcode suffix stored in tm.extension_opcode.
3362
3363 AVX instructions also use this encoding, for some of
3364 3 argument instructions. */
3365
3366 gas_assert (i.imm_operands <= 1
3367 && (i.operands <= 2
3368 || ((i.tm.opcode_modifier.vex
3369 || i.tm.opcode_modifier.evex)
3370 && i.operands <= 4)));
3371
3372 exp = &im_expressions[i.imm_operands++];
3373 i.op[i.operands].imms = exp;
3374 i.types[i.operands] = imm8;
3375 i.operands++;
3376 exp->X_op = O_constant;
3377 exp->X_add_number = i.tm.extension_opcode;
3378 i.tm.extension_opcode = None;
3379}
3380
3381
3382static int
3383check_hle (void)
3384{
3385 switch (i.tm.opcode_modifier.hleprefixok)
3386 {
3387 default:
3388 abort ();
3389 case HLEPrefixNone:
3390 as_bad (_("invalid instruction `%s' after `%s'"),
3391 i.tm.name, i.hle_prefix);
3392 return 0;
3393 case HLEPrefixLock:
3394 if (i.prefix[LOCK_PREFIX])
3395 return 1;
3396 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3397 return 0;
3398 case HLEPrefixAny:
3399 return 1;
3400 case HLEPrefixRelease:
3401 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3402 {
3403 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3404 i.tm.name);
3405 return 0;
3406 }
3407 if (i.mem_operands == 0
3408 || !operand_type_check (i.types[i.operands - 1], anymem))
3409 {
3410 as_bad (_("memory destination needed for instruction `%s'"
3411 " after `xrelease'"), i.tm.name);
3412 return 0;
3413 }
3414 return 1;
3415 }
3416}
3417
3418/* This is the guts of the machine-dependent assembler. LINE points to a
3419 machine dependent instruction. This function is supposed to emit
3420 the frags/bytes it assembles to. */
3421
3422void
3423md_assemble (char *line)
3424{
3425 unsigned int j;
3426 char mnemonic[MAX_MNEM_SIZE];
3427 const insn_template *t;
3428
3429 /* Initialize globals. */
3430 memset (&i, '\0', sizeof (i));
3431 for (j = 0; j < MAX_OPERANDS; j++)
3432 i.reloc[j] = NO_RELOC;
3433 memset (disp_expressions, '\0', sizeof (disp_expressions));
3434 memset (im_expressions, '\0', sizeof (im_expressions));
3435 save_stack_p = save_stack;
3436
3437 /* First parse an instruction mnemonic & call i386_operand for the operands.
3438 We assume that the scrubber has arranged it so that line[0] is the valid
3439 start of a (possibly prefixed) mnemonic. */
3440
3441 line = parse_insn (line, mnemonic);
3442 if (line == NULL)
3443 return;
3444
3445 line = parse_operands (line, mnemonic);
3446 this_operand = -1;
3447 if (line == NULL)
3448 return;
3449
3450 /* Now we've parsed the mnemonic into a set of templates, and have the
3451 operands at hand. */
3452
3453 /* All intel opcodes have reversed operands except for "bound" and
3454 "enter". We also don't reverse intersegment "jmp" and "call"
3455 instructions with 2 immediate operands so that the immediate segment
3456 precedes the offset, as it does when in AT&T mode. */
3457 if (intel_syntax
3458 && i.operands > 1
3459 && (strcmp (mnemonic, "bound") != 0)
3460 && (strcmp (mnemonic, "invlpga") != 0)
3461 && !(operand_type_check (i.types[0], imm)
3462 && operand_type_check (i.types[1], imm)))
3463 swap_operands ();
3464
3465 /* The order of the immediates should be reversed
3466 for 2 immediates extrq and insertq instructions */
3467 if (i.imm_operands == 2
3468 && (strcmp (mnemonic, "extrq") == 0
3469 || strcmp (mnemonic, "insertq") == 0))
3470 swap_2_operands (0, 1);
3471
3472 if (i.imm_operands)
3473 optimize_imm ();
3474
3475 /* Don't optimize displacement for movabs since it only takes 64bit
3476 displacement. */
3477 if (i.disp_operands
3478 && i.disp_encoding != disp_encoding_32bit
3479 && (flag_code != CODE_64BIT
3480 || strcmp (mnemonic, "movabs") != 0))
3481 optimize_disp ();
3482
3483 /* Next, we find a template that matches the given insn,
3484 making sure the overlap of the given operands types is consistent
3485 with the template operand types. */
3486
3487 if (!(t = match_template ()))
3488 return;
3489
3490 if (sse_check != check_none
3491 && !i.tm.opcode_modifier.noavx
3492 && (i.tm.cpu_flags.bitfield.cpusse
3493 || i.tm.cpu_flags.bitfield.cpusse2
3494 || i.tm.cpu_flags.bitfield.cpusse3
3495 || i.tm.cpu_flags.bitfield.cpussse3
3496 || i.tm.cpu_flags.bitfield.cpusse4_1
3497 || i.tm.cpu_flags.bitfield.cpusse4_2))
3498 {
3499 (sse_check == check_warning
3500 ? as_warn
3501 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3502 }
3503
3504 /* Zap movzx and movsx suffix. The suffix has been set from
3505 "word ptr" or "byte ptr" on the source operand in Intel syntax
3506 or extracted from mnemonic in AT&T syntax. But we'll use
3507 the destination register to choose the suffix for encoding. */
3508 if ((i.tm.base_opcode & ~9) == 0x0fb6)
3509 {
3510 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3511 there is no suffix, the default will be byte extension. */
3512 if (i.reg_operands != 2
3513 && !i.suffix
3514 && intel_syntax)
3515 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3516
3517 i.suffix = 0;
3518 }
3519
3520 if (i.tm.opcode_modifier.fwait)
3521 if (!add_prefix (FWAIT_OPCODE))
3522 return;
3523
3524 /* Check if REP prefix is OK. */
3525 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3526 {
3527 as_bad (_("invalid instruction `%s' after `%s'"),
3528 i.tm.name, i.rep_prefix);
3529 return;
3530 }
3531
3532 /* Check for lock without a lockable instruction. Destination operand
3533 must be memory unless it is xchg (0x86). */
3534 if (i.prefix[LOCK_PREFIX]
3535 && (!i.tm.opcode_modifier.islockable
3536 || i.mem_operands == 0
3537 || (i.tm.base_opcode != 0x86
3538 && !operand_type_check (i.types[i.operands - 1], anymem))))
3539 {
3540 as_bad (_("expecting lockable instruction after `lock'"));
3541 return;
3542 }
3543
3544 /* Check if HLE prefix is OK. */
3545 if (i.hle_prefix && !check_hle ())
3546 return;
3547
3548 /* Check BND prefix. */
3549 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3550 as_bad (_("expecting valid branch instruction after `bnd'"));
3551
3552 if (i.tm.cpu_flags.bitfield.cpumpx
3553 && flag_code == CODE_64BIT
3554 && i.prefix[ADDR_PREFIX])
3555 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3556
3557 /* Insert BND prefix. */
3558 if (add_bnd_prefix
3559 && i.tm.opcode_modifier.bndprefixok
3560 && !i.prefix[BND_PREFIX])
3561 add_prefix (BND_PREFIX_OPCODE);
3562
3563 /* Check string instruction segment overrides. */
3564 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
3565 {
3566 if (!check_string ())
3567 return;
3568 i.disp_operands = 0;
3569 }
3570
3571 if (!process_suffix ())
3572 return;
3573
3574 /* Update operand types. */
3575 for (j = 0; j < i.operands; j++)
3576 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3577
3578 /* Make still unresolved immediate matches conform to size of immediate
3579 given in i.suffix. */
3580 if (!finalize_imm ())
3581 return;
3582
3583 if (i.types[0].bitfield.imm1)
3584 i.imm_operands = 0; /* kludge for shift insns. */
3585
3586 /* We only need to check those implicit registers for instructions
3587 with 3 operands or less. */
3588 if (i.operands <= 3)
3589 for (j = 0; j < i.operands; j++)
3590 if (i.types[j].bitfield.inoutportreg
3591 || i.types[j].bitfield.shiftcount
3592 || i.types[j].bitfield.acc
3593 || i.types[j].bitfield.floatacc)
3594 i.reg_operands--;
3595
3596 /* ImmExt should be processed after SSE2AVX. */
3597 if (!i.tm.opcode_modifier.sse2avx
3598 && i.tm.opcode_modifier.immext)
3599 process_immext ();
3600
3601 /* For insns with operands there are more diddles to do to the opcode. */
3602 if (i.operands)
3603 {
3604 if (!process_operands ())
3605 return;
3606 }
3607 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
3608 {
3609 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3610 as_warn (_("translating to `%sp'"), i.tm.name);
3611 }
3612
3613 if (i.tm.opcode_modifier.vex)
3614 build_vex_prefix (t);
3615
3616 if (i.tm.opcode_modifier.evex)
3617 build_evex_prefix ();
3618
3619 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3620 instructions may define INT_OPCODE as well, so avoid this corner
3621 case for those instructions that use MODRM. */
3622 if (i.tm.base_opcode == INT_OPCODE
3623 && !i.tm.opcode_modifier.modrm
3624 && i.op[0].imms->X_add_number == 3)
3625 {
3626 i.tm.base_opcode = INT3_OPCODE;
3627 i.imm_operands = 0;
3628 }
3629
3630 if ((i.tm.opcode_modifier.jump
3631 || i.tm.opcode_modifier.jumpbyte
3632 || i.tm.opcode_modifier.jumpdword)
3633 && i.op[0].disps->X_op == O_constant)
3634 {
3635 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3636 the absolute address given by the constant. Since ix86 jumps and
3637 calls are pc relative, we need to generate a reloc. */
3638 i.op[0].disps->X_add_symbol = &abs_symbol;
3639 i.op[0].disps->X_op = O_symbol;
3640 }
3641
3642 if (i.tm.opcode_modifier.rex64)
3643 i.rex |= REX_W;
3644
3645 /* For 8 bit registers we need an empty rex prefix. Also if the
3646 instruction already has a prefix, we need to convert old
3647 registers to new ones. */
3648
3649 if ((i.types[0].bitfield.reg8
3650 && (i.op[0].regs->reg_flags & RegRex64) != 0)
3651 || (i.types[1].bitfield.reg8
3652 && (i.op[1].regs->reg_flags & RegRex64) != 0)
3653 || ((i.types[0].bitfield.reg8
3654 || i.types[1].bitfield.reg8)
3655 && i.rex != 0))
3656 {
3657 int x;
3658
3659 i.rex |= REX_OPCODE;
3660 for (x = 0; x < 2; x++)
3661 {
3662 /* Look for 8 bit operand that uses old registers. */
3663 if (i.types[x].bitfield.reg8
3664 && (i.op[x].regs->reg_flags & RegRex64) == 0)
3665 {
3666 /* In case it is "hi" register, give up. */
3667 if (i.op[x].regs->reg_num > 3)
3668 as_bad (_("can't encode register '%s%s' in an "
3669 "instruction requiring REX prefix."),
3670 register_prefix, i.op[x].regs->reg_name);
3671
3672 /* Otherwise it is equivalent to the extended register.
3673 Since the encoding doesn't change this is merely
3674 cosmetic cleanup for debug output. */
3675
3676 i.op[x].regs = i.op[x].regs + 8;
3677 }
3678 }
3679 }
3680
3681 if (i.rex != 0)
3682 add_prefix (REX_OPCODE | i.rex);
3683
3684 /* We are ready to output the insn. */
3685 output_insn ();
3686}
3687
3688static char *
3689parse_insn (char *line, char *mnemonic)
3690{
3691 char *l = line;
3692 char *token_start = l;
3693 char *mnem_p;
3694 int supported;
3695 const insn_template *t;
3696 char *dot_p = NULL;
3697
3698 while (1)
3699 {
3700 mnem_p = mnemonic;
3701 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3702 {
3703 if (*mnem_p == '.')
3704 dot_p = mnem_p;
3705 mnem_p++;
3706 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
3707 {
3708 as_bad (_("no such instruction: `%s'"), token_start);
3709 return NULL;
3710 }
3711 l++;
3712 }
3713 if (!is_space_char (*l)
3714 && *l != END_OF_INSN
3715 && (intel_syntax
3716 || (*l != PREFIX_SEPARATOR
3717 && *l != ',')))
3718 {
3719 as_bad (_("invalid character %s in mnemonic"),
3720 output_invalid (*l));
3721 return NULL;
3722 }
3723 if (token_start == l)
3724 {
3725 if (!intel_syntax && *l == PREFIX_SEPARATOR)
3726 as_bad (_("expecting prefix; got nothing"));
3727 else
3728 as_bad (_("expecting mnemonic; got nothing"));
3729 return NULL;
3730 }
3731
3732 /* Look up instruction (or prefix) via hash table. */
3733 current_templates = (const templates *) hash_find (op_hash, mnemonic);
3734
3735 if (*l != END_OF_INSN
3736 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3737 && current_templates
3738 && current_templates->start->opcode_modifier.isprefix)
3739 {
3740 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
3741 {
3742 as_bad ((flag_code != CODE_64BIT
3743 ? _("`%s' is only supported in 64-bit mode")
3744 : _("`%s' is not supported in 64-bit mode")),
3745 current_templates->start->name);
3746 return NULL;
3747 }
3748 /* If we are in 16-bit mode, do not allow addr16 or data16.
3749 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3750 if ((current_templates->start->opcode_modifier.size16
3751 || current_templates->start->opcode_modifier.size32)
3752 && flag_code != CODE_64BIT
3753 && (current_templates->start->opcode_modifier.size32
3754 ^ (flag_code == CODE_16BIT)))
3755 {
3756 as_bad (_("redundant %s prefix"),
3757 current_templates->start->name);
3758 return NULL;
3759 }
3760 /* Add prefix, checking for repeated prefixes. */
3761 switch (add_prefix (current_templates->start->base_opcode))
3762 {
3763 case PREFIX_EXIST:
3764 return NULL;
3765 case PREFIX_REP:
3766 if (current_templates->start->cpu_flags.bitfield.cpuhle)
3767 i.hle_prefix = current_templates->start->name;
3768 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3769 i.bnd_prefix = current_templates->start->name;
3770 else
3771 i.rep_prefix = current_templates->start->name;
3772 break;
3773 default:
3774 break;
3775 }
3776 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3777 token_start = ++l;
3778 }
3779 else
3780 break;
3781 }
3782
3783 if (!current_templates)
3784 {
3785 /* Check if we should swap operand or force 32bit displacement in
3786 encoding. */
3787 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3788 i.swap_operand = 1;
3789 else if (mnem_p - 3 == dot_p
3790 && dot_p[1] == 'd'
3791 && dot_p[2] == '8')
3792 i.disp_encoding = disp_encoding_8bit;
3793 else if (mnem_p - 4 == dot_p
3794 && dot_p[1] == 'd'
3795 && dot_p[2] == '3'
3796 && dot_p[3] == '2')
3797 i.disp_encoding = disp_encoding_32bit;
3798 else
3799 goto check_suffix;
3800 mnem_p = dot_p;
3801 *dot_p = '\0';
3802 current_templates = (const templates *) hash_find (op_hash, mnemonic);
3803 }
3804
3805 if (!current_templates)
3806 {
3807check_suffix:
3808 /* See if we can get a match by trimming off a suffix. */
3809 switch (mnem_p[-1])
3810 {
3811 case WORD_MNEM_SUFFIX:
3812 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3813 i.suffix = SHORT_MNEM_SUFFIX;
3814 else
3815 case BYTE_MNEM_SUFFIX:
3816 case QWORD_MNEM_SUFFIX:
3817 i.suffix = mnem_p[-1];
3818 mnem_p[-1] = '\0';
3819 current_templates = (const templates *) hash_find (op_hash,
3820 mnemonic);
3821 break;
3822 case SHORT_MNEM_SUFFIX:
3823 case LONG_MNEM_SUFFIX:
3824 if (!intel_syntax)
3825 {
3826 i.suffix = mnem_p[-1];
3827 mnem_p[-1] = '\0';
3828 current_templates = (const templates *) hash_find (op_hash,
3829 mnemonic);
3830 }
3831 break;
3832
3833 /* Intel Syntax. */
3834 case 'd':
3835 if (intel_syntax)
3836 {
3837 if (intel_float_operand (mnemonic) == 1)
3838 i.suffix = SHORT_MNEM_SUFFIX;
3839 else
3840 i.suffix = LONG_MNEM_SUFFIX;
3841 mnem_p[-1] = '\0';
3842 current_templates = (const templates *) hash_find (op_hash,
3843 mnemonic);
3844 }
3845 break;
3846 }
3847 if (!current_templates)
3848 {
3849 as_bad (_("no such instruction: `%s'"), token_start);
3850 return NULL;
3851 }
3852 }
3853
3854 if (current_templates->start->opcode_modifier.jump
3855 || current_templates->start->opcode_modifier.jumpbyte)
3856 {
3857 /* Check for a branch hint. We allow ",pt" and ",pn" for
3858 predict taken and predict not taken respectively.
3859 I'm not sure that branch hints actually do anything on loop
3860 and jcxz insns (JumpByte) for current Pentium4 chips. They
3861 may work in the future and it doesn't hurt to accept them
3862 now. */
3863 if (l[0] == ',' && l[1] == 'p')
3864 {
3865 if (l[2] == 't')
3866 {
3867 if (!add_prefix (DS_PREFIX_OPCODE))
3868 return NULL;
3869 l += 3;
3870 }
3871 else if (l[2] == 'n')
3872 {
3873 if (!add_prefix (CS_PREFIX_OPCODE))
3874 return NULL;
3875 l += 3;
3876 }
3877 }
3878 }
3879 /* Any other comma loses. */
3880 if (*l == ',')
3881 {
3882 as_bad (_("invalid character %s in mnemonic"),
3883 output_invalid (*l));
3884 return NULL;
3885 }
3886
3887 /* Check if instruction is supported on specified architecture. */
3888 supported = 0;
3889 for (t = current_templates->start; t < current_templates->end; ++t)
3890 {
3891 supported |= cpu_flags_match (t);
3892 if (supported == CPU_FLAGS_PERFECT_MATCH)
3893 goto skip;
3894 }
3895
3896 if (!(supported & CPU_FLAGS_64BIT_MATCH))
3897 {
3898 as_bad (flag_code == CODE_64BIT
3899 ? _("`%s' is not supported in 64-bit mode")
3900 : _("`%s' is only supported in 64-bit mode"),
3901 current_templates->start->name);
3902 return NULL;
3903 }
3904 if (supported != CPU_FLAGS_PERFECT_MATCH)
3905 {
3906 as_bad (_("`%s' is not supported on `%s%s'"),
3907 current_templates->start->name,
3908 cpu_arch_name ? cpu_arch_name : default_arch,
3909 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3910 return NULL;
3911 }
3912
3913skip:
3914 if (!cpu_arch_flags.bitfield.cpui386
3915 && (flag_code != CODE_16BIT))
3916 {
3917 as_warn (_("use .code16 to ensure correct addressing mode"));
3918 }
3919
3920 return l;
3921}
3922
3923static char *
3924parse_operands (char *l, const char *mnemonic)
3925{
3926 char *token_start;
3927
3928 /* 1 if operand is pending after ','. */
3929 unsigned int expecting_operand = 0;
3930
3931 /* Non-zero if operand parens not balanced. */
3932 unsigned int paren_not_balanced;
3933
3934 while (*l != END_OF_INSN)
3935 {
3936 /* Skip optional white space before operand. */
3937 if (is_space_char (*l))
3938 ++l;
3939 if (!is_operand_char (*l) && *l != END_OF_INSN)
3940 {
3941 as_bad (_("invalid character %s before operand %d"),
3942 output_invalid (*l),
3943 i.operands + 1);
3944 return NULL;
3945 }
3946 token_start = l; /* after white space */
3947 paren_not_balanced = 0;
3948 while (paren_not_balanced || *l != ',')
3949 {
3950 if (*l == END_OF_INSN)
3951 {
3952 if (paren_not_balanced)
3953 {
3954 if (!intel_syntax)
3955 as_bad (_("unbalanced parenthesis in operand %d."),
3956 i.operands + 1);
3957 else
3958 as_bad (_("unbalanced brackets in operand %d."),
3959 i.operands + 1);
3960 return NULL;
3961 }
3962 else
3963 break; /* we are done */
3964 }
3965 else if (!is_operand_char (*l) && !is_space_char (*l))
3966 {
3967 as_bad (_("invalid character %s in operand %d"),
3968 output_invalid (*l),
3969 i.operands + 1);
3970 return NULL;
3971 }
3972 if (!intel_syntax)
3973 {
3974 if (*l == '(')
3975 ++paren_not_balanced;
3976 if (*l == ')')
3977 --paren_not_balanced;
3978 }
3979 else
3980 {
3981 if (*l == '[')
3982 ++paren_not_balanced;
3983 if (*l == ']')
3984 --paren_not_balanced;
3985 }
3986 l++;
3987 }
3988 if (l != token_start)
3989 { /* Yes, we've read in another operand. */
3990 unsigned int operand_ok;
3991 this_operand = i.operands++;
3992 i.types[this_operand].bitfield.unspecified = 1;
3993 if (i.operands > MAX_OPERANDS)
3994 {
3995 as_bad (_("spurious operands; (%d operands/instruction max)"),
3996 MAX_OPERANDS);
3997 return NULL;
3998 }
3999 /* Now parse operand adding info to 'i' as we go along. */
4000 END_STRING_AND_SAVE (l);
4001
4002 if (intel_syntax)
4003 operand_ok =
4004 i386_intel_operand (token_start,
4005 intel_float_operand (mnemonic));
4006 else
4007 operand_ok = i386_att_operand (token_start);
4008
4009 RESTORE_END_STRING (l);
4010 if (!operand_ok)
4011 return NULL;
4012 }
4013 else
4014 {
4015 if (expecting_operand)
4016 {
4017 expecting_operand_after_comma:
4018 as_bad (_("expecting operand after ','; got nothing"));
4019 return NULL;
4020 }
4021 if (*l == ',')
4022 {
4023 as_bad (_("expecting operand before ','; got nothing"));
4024 return NULL;
4025 }
4026 }
4027
4028 /* Now *l must be either ',' or END_OF_INSN. */
4029 if (*l == ',')
4030 {
4031 if (*++l == END_OF_INSN)
4032 {
4033 /* Just skip it, if it's \n complain. */
4034 goto expecting_operand_after_comma;
4035 }
4036 expecting_operand = 1;
4037 }
4038 }
4039 return l;
4040}
4041
4042static void
4043swap_2_operands (int xchg1, int xchg2)
4044{
4045 union i386_op temp_op;
4046 i386_operand_type temp_type;
4047 enum bfd_reloc_code_real temp_reloc;
4048
4049 temp_type = i.types[xchg2];
4050 i.types[xchg2] = i.types[xchg1];
4051 i.types[xchg1] = temp_type;
4052 temp_op = i.op[xchg2];
4053 i.op[xchg2] = i.op[xchg1];
4054 i.op[xchg1] = temp_op;
4055 temp_reloc = i.reloc[xchg2];
4056 i.reloc[xchg2] = i.reloc[xchg1];
4057 i.reloc[xchg1] = temp_reloc;
4058
4059 if (i.mask)
4060 {
4061 if (i.mask->operand == xchg1)
4062 i.mask->operand = xchg2;
4063 else if (i.mask->operand == xchg2)
4064 i.mask->operand = xchg1;
4065 }
4066 if (i.broadcast)
4067 {
4068 if (i.broadcast->operand == xchg1)
4069 i.broadcast->operand = xchg2;
4070 else if (i.broadcast->operand == xchg2)
4071 i.broadcast->operand = xchg1;
4072 }
4073 if (i.rounding)
4074 {
4075 if (i.rounding->operand == xchg1)
4076 i.rounding->operand = xchg2;
4077 else if (i.rounding->operand == xchg2)
4078 i.rounding->operand = xchg1;
4079 }
4080}
4081
4082static void
4083swap_operands (void)
4084{
4085 switch (i.operands)
4086 {
4087 case 5:
4088 case 4:
4089 swap_2_operands (1, i.operands - 2);
4090 case 3:
4091 case 2:
4092 swap_2_operands (0, i.operands - 1);
4093 break;
4094 default:
4095 abort ();
4096 }
4097
4098 if (i.mem_operands == 2)
4099 {
4100 const seg_entry *temp_seg;
4101 temp_seg = i.seg[0];
4102 i.seg[0] = i.seg[1];
4103 i.seg[1] = temp_seg;
4104 }
4105}
4106
4107/* Try to ensure constant immediates are represented in the smallest
4108 opcode possible. */
4109static void
4110optimize_imm (void)
4111{
4112 char guess_suffix = 0;
4113 int op;
4114
4115 if (i.suffix)
4116 guess_suffix = i.suffix;
4117 else if (i.reg_operands)
4118 {
4119 /* Figure out a suffix from the last register operand specified.
4120 We can't do this properly yet, ie. excluding InOutPortReg,
4121 but the following works for instructions with immediates.
4122 In any case, we can't set i.suffix yet. */
4123 for (op = i.operands; --op >= 0;)
4124 if (i.types[op].bitfield.reg8)
4125 {
4126 guess_suffix = BYTE_MNEM_SUFFIX;
4127 break;
4128 }
4129 else if (i.types[op].bitfield.reg16)
4130 {
4131 guess_suffix = WORD_MNEM_SUFFIX;
4132 break;
4133 }
4134 else if (i.types[op].bitfield.reg32)
4135 {
4136 guess_suffix = LONG_MNEM_SUFFIX;
4137 break;
4138 }
4139 else if (i.types[op].bitfield.reg64)
4140 {
4141 guess_suffix = QWORD_MNEM_SUFFIX;
4142 break;
4143 }
4144 }
4145 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4146 guess_suffix = WORD_MNEM_SUFFIX;
4147
4148 for (op = i.operands; --op >= 0;)
4149 if (operand_type_check (i.types[op], imm))
4150 {
4151 switch (i.op[op].imms->X_op)
4152 {
4153 case O_constant:
4154 /* If a suffix is given, this operand may be shortened. */
4155 switch (guess_suffix)
4156 {
4157 case LONG_MNEM_SUFFIX:
4158 i.types[op].bitfield.imm32 = 1;
4159 i.types[op].bitfield.imm64 = 1;
4160 break;
4161 case WORD_MNEM_SUFFIX:
4162 i.types[op].bitfield.imm16 = 1;
4163 i.types[op].bitfield.imm32 = 1;
4164 i.types[op].bitfield.imm32s = 1;
4165 i.types[op].bitfield.imm64 = 1;
4166 break;
4167 case BYTE_MNEM_SUFFIX:
4168 i.types[op].bitfield.imm8 = 1;
4169 i.types[op].bitfield.imm8s = 1;
4170 i.types[op].bitfield.imm16 = 1;
4171 i.types[op].bitfield.imm32 = 1;
4172 i.types[op].bitfield.imm32s = 1;
4173 i.types[op].bitfield.imm64 = 1;
4174 break;
4175 }
4176
4177 /* If this operand is at most 16 bits, convert it
4178 to a signed 16 bit number before trying to see
4179 whether it will fit in an even smaller size.
4180 This allows a 16-bit operand such as $0xffe0 to
4181 be recognised as within Imm8S range. */
4182 if ((i.types[op].bitfield.imm16)
4183 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4184 {
4185 i.op[op].imms->X_add_number =
4186 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4187 }
4188 if ((i.types[op].bitfield.imm32)
4189 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4190 == 0))
4191 {
4192 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4193 ^ ((offsetT) 1 << 31))
4194 - ((offsetT) 1 << 31));
4195 }
4196 i.types[op]
4197 = operand_type_or (i.types[op],
4198 smallest_imm_type (i.op[op].imms->X_add_number));
4199
4200 /* We must avoid matching of Imm32 templates when 64bit
4201 only immediate is available. */
4202 if (guess_suffix == QWORD_MNEM_SUFFIX)
4203 i.types[op].bitfield.imm32 = 0;
4204 break;
4205
4206 case O_absent:
4207 case O_register:
4208 abort ();
4209
4210 /* Symbols and expressions. */
4211 default:
4212 /* Convert symbolic operand to proper sizes for matching, but don't
4213 prevent matching a set of insns that only supports sizes other
4214 than those matching the insn suffix. */
4215 {
4216 i386_operand_type mask, allowed;
4217 const insn_template *t;
4218
4219 operand_type_set (&mask, 0);
4220 operand_type_set (&allowed, 0);
4221
4222 for (t = current_templates->start;
4223 t < current_templates->end;
4224 ++t)
4225 allowed = operand_type_or (allowed,
4226 t->operand_types[op]);
4227 switch (guess_suffix)
4228 {
4229 case QWORD_MNEM_SUFFIX:
4230 mask.bitfield.imm64 = 1;
4231 mask.bitfield.imm32s = 1;
4232 break;
4233 case LONG_MNEM_SUFFIX:
4234 mask.bitfield.imm32 = 1;
4235 break;
4236 case WORD_MNEM_SUFFIX:
4237 mask.bitfield.imm16 = 1;
4238 break;
4239 case BYTE_MNEM_SUFFIX:
4240 mask.bitfield.imm8 = 1;
4241 break;
4242 default:
4243 break;
4244 }
4245 allowed = operand_type_and (mask, allowed);
4246 if (!operand_type_all_zero (&allowed))
4247 i.types[op] = operand_type_and (i.types[op], mask);
4248 }
4249 break;
4250 }
4251 }
4252}
4253
4254/* Try to use the smallest displacement type too. */
4255static void
4256optimize_disp (void)
4257{
4258 int op;
4259
4260 for (op = i.operands; --op >= 0;)
4261 if (operand_type_check (i.types[op], disp))
4262 {
4263 if (i.op[op].disps->X_op == O_constant)
4264 {
4265 offsetT op_disp = i.op[op].disps->X_add_number;
4266
4267 if (i.types[op].bitfield.disp16
4268 && (op_disp & ~(offsetT) 0xffff) == 0)
4269 {
4270 /* If this operand is at most 16 bits, convert
4271 to a signed 16 bit number and don't use 64bit
4272 displacement. */
4273 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4274 i.types[op].bitfield.disp64 = 0;
4275 }
4276 if (i.types[op].bitfield.disp32
4277 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4278 {
4279 /* If this operand is at most 32 bits, convert
4280 to a signed 32 bit number and don't use 64bit
4281 displacement. */
4282 op_disp &= (((offsetT) 2 << 31) - 1);
4283 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4284 i.types[op].bitfield.disp64 = 0;
4285 }
4286 if (!op_disp && i.types[op].bitfield.baseindex)
4287 {
4288 i.types[op].bitfield.disp8 = 0;
4289 i.types[op].bitfield.disp16 = 0;
4290 i.types[op].bitfield.disp32 = 0;
4291 i.types[op].bitfield.disp32s = 0;
4292 i.types[op].bitfield.disp64 = 0;
4293 i.op[op].disps = 0;
4294 i.disp_operands--;
4295 }
4296 else if (flag_code == CODE_64BIT)
4297 {
4298 if (fits_in_signed_long (op_disp))
4299 {
4300 i.types[op].bitfield.disp64 = 0;
4301 i.types[op].bitfield.disp32s = 1;
4302 }
4303 if (i.prefix[ADDR_PREFIX]
4304 && fits_in_unsigned_long (op_disp))
4305 i.types[op].bitfield.disp32 = 1;
4306 }
4307 if ((i.types[op].bitfield.disp32
4308 || i.types[op].bitfield.disp32s
4309 || i.types[op].bitfield.disp16)
4310 && fits_in_signed_byte (op_disp))
4311 i.types[op].bitfield.disp8 = 1;
4312 }
4313 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4314 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4315 {
4316 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4317 i.op[op].disps, 0, i.reloc[op]);
4318 i.types[op].bitfield.disp8 = 0;
4319 i.types[op].bitfield.disp16 = 0;
4320 i.types[op].bitfield.disp32 = 0;
4321 i.types[op].bitfield.disp32s = 0;
4322 i.types[op].bitfield.disp64 = 0;
4323 }
4324 else
4325 /* We only support 64bit displacement on constants. */
4326 i.types[op].bitfield.disp64 = 0;
4327 }
4328}
4329
4330/* Check if operands are valid for the instruction. */
4331
4332static int
4333check_VecOperands (const insn_template *t)
4334{
4335 unsigned int op;
4336
4337 /* Without VSIB byte, we can't have a vector register for index. */
4338 if (!t->opcode_modifier.vecsib
4339 && i.index_reg
4340 && (i.index_reg->reg_type.bitfield.regxmm
4341 || i.index_reg->reg_type.bitfield.regymm
4342 || i.index_reg->reg_type.bitfield.regzmm))
4343 {
4344 i.error = unsupported_vector_index_register;
4345 return 1;
4346 }
4347
4348 /* For VSIB byte, we need a vector register for index, and all vector
4349 registers must be distinct. */
4350 if (t->opcode_modifier.vecsib)
4351 {
4352 if (!i.index_reg
4353 || !((t->opcode_modifier.vecsib == VecSIB128
4354 && i.index_reg->reg_type.bitfield.regxmm)
4355 || (t->opcode_modifier.vecsib == VecSIB256
4356 && i.index_reg->reg_type.bitfield.regymm)
4357 || (t->opcode_modifier.vecsib == VecSIB512
4358 && i.index_reg->reg_type.bitfield.regzmm)))
4359 {
4360 i.error = invalid_vsib_address;
4361 return 1;
4362 }
4363
4364 gas_assert (i.reg_operands == 2 || i.mask);
4365 if (i.reg_operands == 2 && !i.mask)
4366 {
4367 gas_assert (i.types[0].bitfield.regxmm
4368 || i.types[0].bitfield.regymm
4369 || i.types[0].bitfield.regzmm);
4370 gas_assert (i.types[2].bitfield.regxmm
4371 || i.types[2].bitfield.regymm
4372 || i.types[2].bitfield.regzmm);
4373 if (operand_check == check_none)
4374 return 0;
4375 if (register_number (i.op[0].regs)
4376 != register_number (i.index_reg)
4377 && register_number (i.op[2].regs)
4378 != register_number (i.index_reg)
4379 && register_number (i.op[0].regs)
4380 != register_number (i.op[2].regs))
4381 return 0;
4382 if (operand_check == check_error)
4383 {
4384 i.error = invalid_vector_register_set;
4385 return 1;
4386 }
4387 as_warn (_("mask, index, and destination registers should be distinct"));
4388 }
4389 }
4390
4391 /* Check if broadcast is supported by the instruction and is applied
4392 to the memory operand. */
4393 if (i.broadcast)
4394 {
4395 int broadcasted_opnd_size;
4396
4397 /* Check if specified broadcast is supported in this instruction,
4398 and it's applied to memory operand of DWORD or QWORD type,
4399 depending on VecESize. */
4400 if (i.broadcast->type != t->opcode_modifier.broadcast
4401 || !i.types[i.broadcast->operand].bitfield.mem
4402 || (t->opcode_modifier.vecesize == 0
4403 && !i.types[i.broadcast->operand].bitfield.dword
4404 && !i.types[i.broadcast->operand].bitfield.unspecified)
4405 || (t->opcode_modifier.vecesize == 1
4406 && !i.types[i.broadcast->operand].bitfield.qword
4407 && !i.types[i.broadcast->operand].bitfield.unspecified))
4408 goto bad_broadcast;
4409
4410 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4411 if (i.broadcast->type == BROADCAST_1TO16)
4412 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4413 else if (i.broadcast->type == BROADCAST_1TO8)
4414 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
4415 else
4416 goto bad_broadcast;
4417
4418 if ((broadcasted_opnd_size == 256
4419 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4420 || (broadcasted_opnd_size == 512
4421 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4422 {
4423 bad_broadcast:
4424 i.error = unsupported_broadcast;
4425 return 1;
4426 }
4427 }
4428 /* If broadcast is supported in this instruction, we need to check if
4429 operand of one-element size isn't specified without broadcast. */
4430 else if (t->opcode_modifier.broadcast && i.mem_operands)
4431 {
4432 /* Find memory operand. */
4433 for (op = 0; op < i.operands; op++)
4434 if (operand_type_check (i.types[op], anymem))
4435 break;
4436 gas_assert (op < i.operands);
4437 /* Check size of the memory operand. */
4438 if ((t->opcode_modifier.vecesize == 0
4439 && i.types[op].bitfield.dword)
4440 || (t->opcode_modifier.vecesize == 1
4441 && i.types[op].bitfield.qword))
4442 {
4443 i.error = broadcast_needed;
4444 return 1;
4445 }
4446 }
4447
4448 /* Check if requested masking is supported. */
4449 if (i.mask
4450 && (!t->opcode_modifier.masking
4451 || (i.mask->zeroing
4452 && t->opcode_modifier.masking == MERGING_MASKING)))
4453 {
4454 i.error = unsupported_masking;
4455 return 1;
4456 }
4457
4458 /* Check if masking is applied to dest operand. */
4459 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4460 {
4461 i.error = mask_not_on_destination;
4462 return 1;
4463 }
4464
4465 /* Check if default mask is allowed. */
4466 if (t->opcode_modifier.nodefmask
4467 && (!i.mask || i.mask->mask->reg_num == 0))
4468 {
4469 i.error = no_default_mask;
4470 return 1;
4471 }
4472
4473 /* Check RC/SAE. */
4474 if (i.rounding)
4475 {
4476 if ((i.rounding->type != saeonly
4477 && !t->opcode_modifier.staticrounding)
4478 || (i.rounding->type == saeonly
4479 && (t->opcode_modifier.staticrounding
4480 || !t->opcode_modifier.sae)))
4481 {
4482 i.error = unsupported_rc_sae;
4483 return 1;
4484 }
4485 /* If the instruction has several immediate operands and one of
4486 them is rounding, the rounding operand should be the last
4487 immediate operand. */
4488 if (i.imm_operands > 1
4489 && i.rounding->operand != (int) (i.imm_operands - 1))
4490 {
4491 i.error = rc_sae_operand_not_last_imm;
4492 return 1;
4493 }
4494 }
4495
4496 /* Check vector Disp8 operand. */
4497 if (t->opcode_modifier.disp8memshift)
4498 {
4499 if (i.broadcast)
4500 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4501 else
4502 i.memshift = t->opcode_modifier.disp8memshift;
4503
4504 for (op = 0; op < i.operands; op++)
4505 if (operand_type_check (i.types[op], disp)
4506 && i.op[op].disps->X_op == O_constant)
4507 {
4508 offsetT value = i.op[op].disps->X_add_number;
4509 int vec_disp8_ok = fits_in_vec_disp8 (value);
4510 if (t->operand_types [op].bitfield.vec_disp8)
4511 {
4512 if (vec_disp8_ok)
4513 i.types[op].bitfield.vec_disp8 = 1;
4514 else
4515 {
4516 /* Vector insn can only have Vec_Disp8/Disp32 in
4517 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4518 mode. */
4519 i.types[op].bitfield.disp8 = 0;
4520 if (flag_code != CODE_16BIT)
4521 i.types[op].bitfield.disp16 = 0;
4522 }
4523 }
4524 else if (flag_code != CODE_16BIT)
4525 {
4526 /* One form of this instruction supports vector Disp8.
4527 Try vector Disp8 if we need to use Disp32. */
4528 if (vec_disp8_ok && !fits_in_signed_byte (value))
4529 {
4530 i.error = try_vector_disp8;
4531 return 1;
4532 }
4533 }
4534 }
4535 }
4536 else
4537 i.memshift = -1;
4538
4539 return 0;
4540}
4541
4542/* Check if operands are valid for the instruction. Update VEX
4543 operand types. */
4544
4545static int
4546VEX_check_operands (const insn_template *t)
4547{
4548 /* VREX is only valid with EVEX prefix. */
4549 if (i.need_vrex && !t->opcode_modifier.evex)
4550 {
4551 i.error = invalid_register_operand;
4552 return 1;
4553 }
4554
4555 if (!t->opcode_modifier.vex)
4556 return 0;
4557
4558 /* Only check VEX_Imm4, which must be the first operand. */
4559 if (t->operand_types[0].bitfield.vec_imm4)
4560 {
4561 if (i.op[0].imms->X_op != O_constant
4562 || !fits_in_imm4 (i.op[0].imms->X_add_number))
4563 {
4564 i.error = bad_imm4;
4565 return 1;
4566 }
4567
4568 /* Turn off Imm8 so that update_imm won't complain. */
4569 i.types[0] = vec_imm4;
4570 }
4571
4572 return 0;
4573}
4574
4575static const insn_template *
4576match_template (void)
4577{
4578 /* Points to template once we've found it. */
4579 const insn_template *t;
4580 i386_operand_type overlap0, overlap1, overlap2, overlap3;
4581 i386_operand_type overlap4;
4582 unsigned int found_reverse_match;
4583 i386_opcode_modifier suffix_check;
4584 i386_operand_type operand_types [MAX_OPERANDS];
4585 int addr_prefix_disp;
4586 unsigned int j;
4587 unsigned int found_cpu_match;
4588 unsigned int check_register;
4589 enum i386_error specific_error = 0;
4590
4591#if MAX_OPERANDS != 5
4592# error "MAX_OPERANDS must be 5."
4593#endif
4594
4595 found_reverse_match = 0;
4596 addr_prefix_disp = -1;
4597
4598 memset (&suffix_check, 0, sizeof (suffix_check));
4599 if (i.suffix == BYTE_MNEM_SUFFIX)
4600 suffix_check.no_bsuf = 1;
4601 else if (i.suffix == WORD_MNEM_SUFFIX)
4602 suffix_check.no_wsuf = 1;
4603 else if (i.suffix == SHORT_MNEM_SUFFIX)
4604 suffix_check.no_ssuf = 1;
4605 else if (i.suffix == LONG_MNEM_SUFFIX)
4606 suffix_check.no_lsuf = 1;
4607 else if (i.suffix == QWORD_MNEM_SUFFIX)
4608 suffix_check.no_qsuf = 1;
4609 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
4610 suffix_check.no_ldsuf = 1;
4611
4612 /* Must have right number of operands. */
4613 i.error = number_of_operands_mismatch;
4614
4615 for (t = current_templates->start; t < current_templates->end; t++)
4616 {
4617 addr_prefix_disp = -1;
4618
4619 if (i.operands != t->operands)
4620 continue;
4621
4622 /* Check processor support. */
4623 i.error = unsupported;
4624 found_cpu_match = (cpu_flags_match (t)
4625 == CPU_FLAGS_PERFECT_MATCH);
4626 if (!found_cpu_match)
4627 continue;
4628
4629 /* Check old gcc support. */
4630 i.error = old_gcc_only;
4631 if (!old_gcc && t->opcode_modifier.oldgcc)
4632 continue;
4633
4634 /* Check AT&T mnemonic. */
4635 i.error = unsupported_with_intel_mnemonic;
4636 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
4637 continue;
4638
4639 /* Check AT&T/Intel syntax. */
4640 i.error = unsupported_syntax;
4641 if ((intel_syntax && t->opcode_modifier.attsyntax)
4642 || (!intel_syntax && t->opcode_modifier.intelsyntax))
4643 continue;
4644
4645 /* Check the suffix, except for some instructions in intel mode. */
4646 i.error = invalid_instruction_suffix;
4647 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4648 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4649 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4650 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4651 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4652 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4653 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
4654 continue;
4655
4656 if (!operand_size_match (t))
4657 continue;
4658
4659 for (j = 0; j < MAX_OPERANDS; j++)
4660 operand_types[j] = t->operand_types[j];
4661
4662 /* In general, don't allow 64-bit operands in 32-bit mode. */
4663 if (i.suffix == QWORD_MNEM_SUFFIX
4664 && flag_code != CODE_64BIT
4665 && (intel_syntax
4666 ? (!t->opcode_modifier.ignoresize
4667 && !intel_float_operand (t->name))
4668 : intel_float_operand (t->name) != 2)
4669 && ((!operand_types[0].bitfield.regmmx
4670 && !operand_types[0].bitfield.regxmm
4671 && !operand_types[0].bitfield.regymm
4672 && !operand_types[0].bitfield.regzmm)
4673 || (!operand_types[t->operands > 1].bitfield.regmmx
4674 && !!operand_types[t->operands > 1].bitfield.regxmm
4675 && !!operand_types[t->operands > 1].bitfield.regymm
4676 && !!operand_types[t->operands > 1].bitfield.regzmm))
4677 && (t->base_opcode != 0x0fc7
4678 || t->extension_opcode != 1 /* cmpxchg8b */))
4679 continue;
4680
4681 /* In general, don't allow 32-bit operands on pre-386. */
4682 else if (i.suffix == LONG_MNEM_SUFFIX
4683 && !cpu_arch_flags.bitfield.cpui386
4684 && (intel_syntax
4685 ? (!t->opcode_modifier.ignoresize
4686 && !intel_float_operand (t->name))
4687 : intel_float_operand (t->name) != 2)
4688 && ((!operand_types[0].bitfield.regmmx
4689 && !operand_types[0].bitfield.regxmm)
4690 || (!operand_types[t->operands > 1].bitfield.regmmx
4691 && !!operand_types[t->operands > 1].bitfield.regxmm)))
4692 continue;
4693
4694 /* Do not verify operands when there are none. */
4695 else
4696 {
4697 if (!t->operands)
4698 /* We've found a match; break out of loop. */
4699 break;
4700 }
4701
4702 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4703 into Disp32/Disp16/Disp32 operand. */
4704 if (i.prefix[ADDR_PREFIX] != 0)
4705 {
4706 /* There should be only one Disp operand. */
4707 switch (flag_code)
4708 {
4709 case CODE_16BIT:
4710 for (j = 0; j < MAX_OPERANDS; j++)
4711 {
4712 if (operand_types[j].bitfield.disp16)
4713 {
4714 addr_prefix_disp = j;
4715 operand_types[j].bitfield.disp32 = 1;
4716 operand_types[j].bitfield.disp16 = 0;
4717 break;
4718 }
4719 }
4720 break;
4721 case CODE_32BIT:
4722 for (j = 0; j < MAX_OPERANDS; j++)
4723 {
4724 if (operand_types[j].bitfield.disp32)
4725 {
4726 addr_prefix_disp = j;
4727 operand_types[j].bitfield.disp32 = 0;
4728 operand_types[j].bitfield.disp16 = 1;
4729 break;
4730 }
4731 }
4732 break;
4733 case CODE_64BIT:
4734 for (j = 0; j < MAX_OPERANDS; j++)
4735 {
4736 if (operand_types[j].bitfield.disp64)
4737 {
4738 addr_prefix_disp = j;
4739 operand_types[j].bitfield.disp64 = 0;
4740 operand_types[j].bitfield.disp32 = 1;
4741 break;
4742 }
4743 }
4744 break;
4745 }
4746 }
4747
4748 /* We check register size if needed. */
4749 check_register = t->opcode_modifier.checkregsize;
4750 overlap0 = operand_type_and (i.types[0], operand_types[0]);
4751 switch (t->operands)
4752 {
4753 case 1:
4754 if (!operand_type_match (overlap0, i.types[0]))
4755 continue;
4756 break;
4757 case 2:
4758 /* xchg %eax, %eax is a special case. It is an aliase for nop
4759 only in 32bit mode and we can use opcode 0x90. In 64bit
4760 mode, we can't use 0x90 for xchg %eax, %eax since it should
4761 zero-extend %eax to %rax. */
4762 if (flag_code == CODE_64BIT
4763 && t->base_opcode == 0x90
4764 && operand_type_equal (&i.types [0], &acc32)
4765 && operand_type_equal (&i.types [1], &acc32))
4766 continue;
4767 if (i.swap_operand)
4768 {
4769 /* If we swap operand in encoding, we either match
4770 the next one or reverse direction of operands. */
4771 if (t->opcode_modifier.s)
4772 continue;
4773 else if (t->opcode_modifier.d)
4774 goto check_reverse;
4775 }
4776
4777 case 3:
4778 /* If we swap operand in encoding, we match the next one. */
4779 if (i.swap_operand && t->opcode_modifier.s)
4780 continue;
4781 case 4:
4782 case 5:
4783 overlap1 = operand_type_and (i.types[1], operand_types[1]);
4784 if (!operand_type_match (overlap0, i.types[0])
4785 || !operand_type_match (overlap1, i.types[1])
4786 || (check_register
4787 && !operand_type_register_match (overlap0, i.types[0],
4788 operand_types[0],
4789 overlap1, i.types[1],
4790 operand_types[1])))
4791 {
4792 /* Check if other direction is valid ... */
4793 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
4794 continue;
4795
4796check_reverse:
4797 /* Try reversing direction of operands. */
4798 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4799 overlap1 = operand_type_and (i.types[1], operand_types[0]);
4800 if (!operand_type_match (overlap0, i.types[0])
4801 || !operand_type_match (overlap1, i.types[1])
4802 || (check_register
4803 && !operand_type_register_match (overlap0,
4804 i.types[0],
4805 operand_types[1],
4806 overlap1,
4807 i.types[1],
4808 operand_types[0])))
4809 {
4810 /* Does not match either direction. */
4811 continue;
4812 }
4813 /* found_reverse_match holds which of D or FloatDR
4814 we've found. */
4815 if (t->opcode_modifier.d)
4816 found_reverse_match = Opcode_D;
4817 else if (t->opcode_modifier.floatd)
4818 found_reverse_match = Opcode_FloatD;
4819 else
4820 found_reverse_match = 0;
4821 if (t->opcode_modifier.floatr)
4822 found_reverse_match |= Opcode_FloatR;
4823 }
4824 else
4825 {
4826 /* Found a forward 2 operand match here. */
4827 switch (t->operands)
4828 {
4829 case 5:
4830 overlap4 = operand_type_and (i.types[4],
4831 operand_types[4]);
4832 case 4:
4833 overlap3 = operand_type_and (i.types[3],
4834 operand_types[3]);
4835 case 3:
4836 overlap2 = operand_type_and (i.types[2],
4837 operand_types[2]);
4838 break;
4839 }
4840
4841 switch (t->operands)
4842 {
4843 case 5:
4844 if (!operand_type_match (overlap4, i.types[4])
4845 || !operand_type_register_match (overlap3,
4846 i.types[3],
4847 operand_types[3],
4848 overlap4,
4849 i.types[4],
4850 operand_types[4]))
4851 continue;
4852 case 4:
4853 if (!operand_type_match (overlap3, i.types[3])
4854 || (check_register
4855 && !operand_type_register_match (overlap2,
4856 i.types[2],
4857 operand_types[2],
4858 overlap3,
4859 i.types[3],
4860 operand_types[3])))
4861 continue;
4862 case 3:
4863 /* Here we make use of the fact that there are no
4864 reverse match 3 operand instructions, and all 3
4865 operand instructions only need to be checked for
4866 register consistency between operands 2 and 3. */
4867 if (!operand_type_match (overlap2, i.types[2])
4868 || (check_register
4869 && !operand_type_register_match (overlap1,
4870 i.types[1],
4871 operand_types[1],
4872 overlap2,
4873 i.types[2],
4874 operand_types[2])))
4875 continue;
4876 break;
4877 }
4878 }
4879 /* Found either forward/reverse 2, 3 or 4 operand match here:
4880 slip through to break. */
4881 }
4882 if (!found_cpu_match)
4883 {
4884 found_reverse_match = 0;
4885 continue;
4886 }
4887
4888 /* Check if vector and VEX operands are valid. */
4889 if (check_VecOperands (t) || VEX_check_operands (t))
4890 {
4891 specific_error = i.error;
4892 continue;
4893 }
4894
4895 /* We've found a match; break out of loop. */
4896 break;
4897 }
4898
4899 if (t == current_templates->end)
4900 {
4901 /* We found no match. */
4902 const char *err_msg;
4903 switch (specific_error ? specific_error : i.error)
4904 {
4905 default:
4906 abort ();
4907 case operand_size_mismatch:
4908 err_msg = _("operand size mismatch");
4909 break;
4910 case operand_type_mismatch:
4911 err_msg = _("operand type mismatch");
4912 break;
4913 case register_type_mismatch:
4914 err_msg = _("register type mismatch");
4915 break;
4916 case number_of_operands_mismatch:
4917 err_msg = _("number of operands mismatch");
4918 break;
4919 case invalid_instruction_suffix:
4920 err_msg = _("invalid instruction suffix");
4921 break;
4922 case bad_imm4:
4923 err_msg = _("constant doesn't fit in 4 bits");
4924 break;
4925 case old_gcc_only:
4926 err_msg = _("only supported with old gcc");
4927 break;
4928 case unsupported_with_intel_mnemonic:
4929 err_msg = _("unsupported with Intel mnemonic");
4930 break;
4931 case unsupported_syntax:
4932 err_msg = _("unsupported syntax");
4933 break;
4934 case unsupported:
4935 as_bad (_("unsupported instruction `%s'"),
4936 current_templates->start->name);
4937 return NULL;
4938 case invalid_vsib_address:
4939 err_msg = _("invalid VSIB address");
4940 break;
4941 case invalid_vector_register_set:
4942 err_msg = _("mask, index, and destination registers must be distinct");
4943 break;
4944 case unsupported_vector_index_register:
4945 err_msg = _("unsupported vector index register");
4946 break;
4947 case unsupported_broadcast:
4948 err_msg = _("unsupported broadcast");
4949 break;
4950 case broadcast_not_on_src_operand:
4951 err_msg = _("broadcast not on source memory operand");
4952 break;
4953 case broadcast_needed:
4954 err_msg = _("broadcast is needed for operand of such type");
4955 break;
4956 case unsupported_masking:
4957 err_msg = _("unsupported masking");
4958 break;
4959 case mask_not_on_destination:
4960 err_msg = _("mask not on destination operand");
4961 break;
4962 case no_default_mask:
4963 err_msg = _("default mask isn't allowed");
4964 break;
4965 case unsupported_rc_sae:
4966 err_msg = _("unsupported static rounding/sae");
4967 break;
4968 case rc_sae_operand_not_last_imm:
4969 if (intel_syntax)
4970 err_msg = _("RC/SAE operand must precede immediate operands");
4971 else
4972 err_msg = _("RC/SAE operand must follow immediate operands");
4973 break;
4974 case invalid_register_operand:
4975 err_msg = _("invalid register operand");
4976 break;
4977 }
4978 as_bad (_("%s for `%s'"), err_msg,
4979 current_templates->start->name);
4980 return NULL;
4981 }
4982
4983 if (!quiet_warnings)
4984 {
4985 if (!intel_syntax
4986 && (i.types[0].bitfield.jumpabsolute
4987 != operand_types[0].bitfield.jumpabsolute))
4988 {
4989 as_warn (_("indirect %s without `*'"), t->name);
4990 }
4991
4992 if (t->opcode_modifier.isprefix
4993 && t->opcode_modifier.ignoresize)
4994 {
4995 /* Warn them that a data or address size prefix doesn't
4996 affect assembly of the next line of code. */
4997 as_warn (_("stand-alone `%s' prefix"), t->name);
4998 }
4999 }
5000
5001 /* Copy the template we found. */
5002 i.tm = *t;
5003
5004 if (addr_prefix_disp != -1)
5005 i.tm.operand_types[addr_prefix_disp]
5006 = operand_types[addr_prefix_disp];
5007
5008 if (found_reverse_match)
5009 {
5010 /* If we found a reverse match we must alter the opcode
5011 direction bit. found_reverse_match holds bits to change
5012 (different for int & float insns). */
5013
5014 i.tm.base_opcode ^= found_reverse_match;
5015
5016 i.tm.operand_types[0] = operand_types[1];
5017 i.tm.operand_types[1] = operand_types[0];
5018 }
5019
5020 return t;
5021}
5022
5023static int
5024check_string (void)
5025{
5026 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5027 if (i.tm.operand_types[mem_op].bitfield.esseg)
5028 {
5029 if (i.seg[0] != NULL && i.seg[0] != &es)
5030 {
5031 as_bad (_("`%s' operand %d must use `%ses' segment"),
5032 i.tm.name,
5033 mem_op + 1,
5034 register_prefix);
5035 return 0;
5036 }
5037 /* There's only ever one segment override allowed per instruction.
5038 This instruction possibly has a legal segment override on the
5039 second operand, so copy the segment to where non-string
5040 instructions store it, allowing common code. */
5041 i.seg[0] = i.seg[1];
5042 }
5043 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5044 {
5045 if (i.seg[1] != NULL && i.seg[1] != &es)
5046 {
5047 as_bad (_("`%s' operand %d must use `%ses' segment"),
5048 i.tm.name,
5049 mem_op + 2,
5050 register_prefix);
5051 return 0;
5052 }
5053 }
5054 return 1;
5055}
5056
5057static int
5058process_suffix (void)
5059{
5060 /* If matched instruction specifies an explicit instruction mnemonic
5061 suffix, use it. */
5062 if (i.tm.opcode_modifier.size16)
5063 i.suffix = WORD_MNEM_SUFFIX;
5064 else if (i.tm.opcode_modifier.size32)
5065 i.suffix = LONG_MNEM_SUFFIX;
5066 else if (i.tm.opcode_modifier.size64)
5067 i.suffix = QWORD_MNEM_SUFFIX;
5068 else if (i.reg_operands)
5069 {
5070 /* If there's no instruction mnemonic suffix we try to invent one
5071 based on register operands. */
5072 if (!i.suffix)
5073 {
5074 /* We take i.suffix from the last register operand specified,
5075 Destination register type is more significant than source
5076 register type. crc32 in SSE4.2 prefers source register
5077 type. */
5078 if (i.tm.base_opcode == 0xf20f38f1)
5079 {
5080 if (i.types[0].bitfield.reg16)
5081 i.suffix = WORD_MNEM_SUFFIX;
5082 else if (i.types[0].bitfield.reg32)
5083 i.suffix = LONG_MNEM_SUFFIX;
5084 else if (i.types[0].bitfield.reg64)
5085 i.suffix = QWORD_MNEM_SUFFIX;
5086 }
5087 else if (i.tm.base_opcode == 0xf20f38f0)
5088 {
5089 if (i.types[0].bitfield.reg8)
5090 i.suffix = BYTE_MNEM_SUFFIX;
5091 }
5092
5093 if (!i.suffix)
5094 {
5095 int op;
5096
5097 if (i.tm.base_opcode == 0xf20f38f1
5098 || i.tm.base_opcode == 0xf20f38f0)
5099 {
5100 /* We have to know the operand size for crc32. */
5101 as_bad (_("ambiguous memory operand size for `%s`"),
5102 i.tm.name);
5103 return 0;
5104 }
5105
5106 for (op = i.operands; --op >= 0;)
5107 if (!i.tm.operand_types[op].bitfield.inoutportreg)
5108 {
5109 if (i.types[op].bitfield.reg8)
5110 {
5111 i.suffix = BYTE_MNEM_SUFFIX;
5112 break;
5113 }
5114 else if (i.types[op].bitfield.reg16)
5115 {
5116 i.suffix = WORD_MNEM_SUFFIX;
5117 break;
5118 }
5119 else if (i.types[op].bitfield.reg32)
5120 {
5121 i.suffix = LONG_MNEM_SUFFIX;
5122 break;
5123 }
5124 else if (i.types[op].bitfield.reg64)
5125 {
5126 i.suffix = QWORD_MNEM_SUFFIX;
5127 break;
5128 }
5129 }
5130 }
5131 }
5132 else if (i.suffix == BYTE_MNEM_SUFFIX)
5133 {
5134 if (intel_syntax
5135 && i.tm.opcode_modifier.ignoresize
5136 && i.tm.opcode_modifier.no_bsuf)
5137 i.suffix = 0;
5138 else if (!check_byte_reg ())
5139 return 0;
5140 }
5141 else if (i.suffix == LONG_MNEM_SUFFIX)
5142 {
5143 if (intel_syntax
5144 && i.tm.opcode_modifier.ignoresize
5145 && i.tm.opcode_modifier.no_lsuf)
5146 i.suffix = 0;
5147 else if (!check_long_reg ())
5148 return 0;
5149 }
5150 else if (i.suffix == QWORD_MNEM_SUFFIX)
5151 {
5152 if (intel_syntax
5153 && i.tm.opcode_modifier.ignoresize
5154 && i.tm.opcode_modifier.no_qsuf)
5155 i.suffix = 0;
5156 else if (!check_qword_reg ())
5157 return 0;
5158 }
5159 else if (i.suffix == WORD_MNEM_SUFFIX)
5160 {
5161 if (intel_syntax
5162 && i.tm.opcode_modifier.ignoresize
5163 && i.tm.opcode_modifier.no_wsuf)
5164 i.suffix = 0;
5165 else if (!check_word_reg ())
5166 return 0;
5167 }
5168 else if (i.suffix == XMMWORD_MNEM_SUFFIX
5169 || i.suffix == YMMWORD_MNEM_SUFFIX
5170 || i.suffix == ZMMWORD_MNEM_SUFFIX)
5171 {
5172 /* Skip if the instruction has x/y/z suffix. match_template
5173 should check if it is a valid suffix. */
5174 }
5175 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5176 /* Do nothing if the instruction is going to ignore the prefix. */
5177 ;
5178 else
5179 abort ();
5180 }
5181 else if (i.tm.opcode_modifier.defaultsize
5182 && !i.suffix
5183 /* exclude fldenv/frstor/fsave/fstenv */
5184 && i.tm.opcode_modifier.no_ssuf)
5185 {
5186 i.suffix = stackop_size;
5187 }
5188 else if (intel_syntax
5189 && !i.suffix
5190 && (i.tm.operand_types[0].bitfield.jumpabsolute
5191 || i.tm.opcode_modifier.jumpbyte
5192 || i.tm.opcode_modifier.jumpintersegment
5193 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5194 && i.tm.extension_opcode <= 3)))
5195 {
5196 switch (flag_code)
5197 {
5198 case CODE_64BIT:
5199 if (!i.tm.opcode_modifier.no_qsuf)
5200 {
5201 i.suffix = QWORD_MNEM_SUFFIX;
5202 break;
5203 }
5204 case CODE_32BIT:
5205 if (!i.tm.opcode_modifier.no_lsuf)
5206 i.suffix = LONG_MNEM_SUFFIX;
5207 break;
5208 case CODE_16BIT:
5209 if (!i.tm.opcode_modifier.no_wsuf)
5210 i.suffix = WORD_MNEM_SUFFIX;
5211 break;
5212 }
5213 }
5214
5215 if (!i.suffix)
5216 {
5217 if (!intel_syntax)
5218 {
5219 if (i.tm.opcode_modifier.w)
5220 {
5221 as_bad (_("no instruction mnemonic suffix given and "
5222 "no register operands; can't size instruction"));
5223 return 0;
5224 }
5225 }
5226 else
5227 {
5228 unsigned int suffixes;
5229
5230 suffixes = !i.tm.opcode_modifier.no_bsuf;
5231 if (!i.tm.opcode_modifier.no_wsuf)
5232 suffixes |= 1 << 1;
5233 if (!i.tm.opcode_modifier.no_lsuf)
5234 suffixes |= 1 << 2;
5235 if (!i.tm.opcode_modifier.no_ldsuf)
5236 suffixes |= 1 << 3;
5237 if (!i.tm.opcode_modifier.no_ssuf)
5238 suffixes |= 1 << 4;
5239 if (!i.tm.opcode_modifier.no_qsuf)
5240 suffixes |= 1 << 5;
5241
5242 /* There are more than suffix matches. */
5243 if (i.tm.opcode_modifier.w
5244 || ((suffixes & (suffixes - 1))
5245 && !i.tm.opcode_modifier.defaultsize
5246 && !i.tm.opcode_modifier.ignoresize))
5247 {
5248 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5249 return 0;
5250 }
5251 }
5252 }
5253
5254 /* Change the opcode based on the operand size given by i.suffix;
5255 We don't need to change things for byte insns. */
5256
5257 if (i.suffix
5258 && i.suffix != BYTE_MNEM_SUFFIX
5259 && i.suffix != XMMWORD_MNEM_SUFFIX
5260 && i.suffix != YMMWORD_MNEM_SUFFIX
5261 && i.suffix != ZMMWORD_MNEM_SUFFIX)
5262 {
5263 /* It's not a byte, select word/dword operation. */
5264 if (i.tm.opcode_modifier.w)
5265 {
5266 if (i.tm.opcode_modifier.shortform)
5267 i.tm.base_opcode |= 8;
5268 else
5269 i.tm.base_opcode |= 1;
5270 }
5271
5272 /* Now select between word & dword operations via the operand
5273 size prefix, except for instructions that will ignore this
5274 prefix anyway. */
5275 if (i.tm.opcode_modifier.addrprefixop0)
5276 {
5277 /* The address size override prefix changes the size of the
5278 first operand. */
5279 if ((flag_code == CODE_32BIT
5280 && i.op->regs[0].reg_type.bitfield.reg16)
5281 || (flag_code != CODE_32BIT
5282 && i.op->regs[0].reg_type.bitfield.reg32))
5283 if (!add_prefix (ADDR_PREFIX_OPCODE))
5284 return 0;
5285 }
5286 else if (i.suffix != QWORD_MNEM_SUFFIX
5287 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
5288 && !i.tm.opcode_modifier.ignoresize
5289 && !i.tm.opcode_modifier.floatmf
5290 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5291 || (flag_code == CODE_64BIT
5292 && i.tm.opcode_modifier.jumpbyte)))
5293 {
5294 unsigned int prefix = DATA_PREFIX_OPCODE;
5295
5296 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5297 prefix = ADDR_PREFIX_OPCODE;
5298
5299 if (!add_prefix (prefix))
5300 return 0;
5301 }
5302
5303 /* Set mode64 for an operand. */
5304 if (i.suffix == QWORD_MNEM_SUFFIX
5305 && flag_code == CODE_64BIT
5306 && !i.tm.opcode_modifier.norex64)
5307 {
5308 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5309 need rex64. cmpxchg8b is also a special case. */
5310 if (! (i.operands == 2
5311 && i.tm.base_opcode == 0x90
5312 && i.tm.extension_opcode == None
5313 && operand_type_equal (&i.types [0], &acc64)
5314 && operand_type_equal (&i.types [1], &acc64))
5315 && ! (i.operands == 1
5316 && i.tm.base_opcode == 0xfc7
5317 && i.tm.extension_opcode == 1
5318 && !operand_type_check (i.types [0], reg)
5319 && operand_type_check (i.types [0], anymem)))
5320 i.rex |= REX_W;
5321 }
5322
5323 /* Size floating point instruction. */
5324 if (i.suffix == LONG_MNEM_SUFFIX)
5325 if (i.tm.opcode_modifier.floatmf)
5326 i.tm.base_opcode ^= 4;
5327 }
5328
5329 return 1;
5330}
5331
5332static int
5333check_byte_reg (void)
5334{
5335 int op;
5336
5337 for (op = i.operands; --op >= 0;)
5338 {
5339 /* If this is an eight bit register, it's OK. If it's the 16 or
5340 32 bit version of an eight bit register, we will just use the
5341 low portion, and that's OK too. */
5342 if (i.types[op].bitfield.reg8)
5343 continue;
5344
5345 /* I/O port address operands are OK too. */
5346 if (i.tm.operand_types[op].bitfield.inoutportreg)
5347 continue;
5348
5349 /* crc32 doesn't generate this warning. */
5350 if (i.tm.base_opcode == 0xf20f38f0)
5351 continue;
5352
5353 if ((i.types[op].bitfield.reg16
5354 || i.types[op].bitfield.reg32
5355 || i.types[op].bitfield.reg64)
5356 && i.op[op].regs->reg_num < 4
5357 /* Prohibit these changes in 64bit mode, since the lowering
5358 would be more complicated. */
5359 && flag_code != CODE_64BIT)
5360 {
5361#if REGISTER_WARNINGS
5362 if (!quiet_warnings)
5363 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5364 register_prefix,
5365 (i.op[op].regs + (i.types[op].bitfield.reg16
5366 ? REGNAM_AL - REGNAM_AX
5367 : REGNAM_AL - REGNAM_EAX))->reg_name,
5368 register_prefix,
5369 i.op[op].regs->reg_name,
5370 i.suffix);
5371#endif
5372 continue;
5373 }
5374 /* Any other register is bad. */
5375 if (i.types[op].bitfield.reg16
5376 || i.types[op].bitfield.reg32
5377 || i.types[op].bitfield.reg64
5378 || i.types[op].bitfield.regmmx
5379 || i.types[op].bitfield.regxmm
5380 || i.types[op].bitfield.regymm
5381 || i.types[op].bitfield.regzmm
5382 || i.types[op].bitfield.sreg2
5383 || i.types[op].bitfield.sreg3
5384 || i.types[op].bitfield.control
5385 || i.types[op].bitfield.debug
5386 || i.types[op].bitfield.test
5387 || i.types[op].bitfield.floatreg
5388 || i.types[op].bitfield.floatacc)
5389 {
5390 as_bad (_("`%s%s' not allowed with `%s%c'"),
5391 register_prefix,
5392 i.op[op].regs->reg_name,
5393 i.tm.name,
5394 i.suffix);
5395 return 0;
5396 }
5397 }
5398 return 1;
5399}
5400
5401static int
5402check_long_reg (void)
5403{
5404 int op;
5405
5406 for (op = i.operands; --op >= 0;)
5407 /* Reject eight bit registers, except where the template requires
5408 them. (eg. movzb) */
5409 if (i.types[op].bitfield.reg8
5410 && (i.tm.operand_types[op].bitfield.reg16
5411 || i.tm.operand_types[op].bitfield.reg32
5412 || i.tm.operand_types[op].bitfield.acc))
5413 {
5414 as_bad (_("`%s%s' not allowed with `%s%c'"),
5415 register_prefix,
5416 i.op[op].regs->reg_name,
5417 i.tm.name,
5418 i.suffix);
5419 return 0;
5420 }
5421 /* Warn if the e prefix on a general reg is missing. */
5422 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5423 && i.types[op].bitfield.reg16
5424 && (i.tm.operand_types[op].bitfield.reg32
5425 || i.tm.operand_types[op].bitfield.acc))
5426 {
5427 /* Prohibit these changes in the 64bit mode, since the
5428 lowering is more complicated. */
5429 if (flag_code == CODE_64BIT)
5430 {
5431 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5432 register_prefix, i.op[op].regs->reg_name,
5433 i.suffix);
5434 return 0;
5435 }
5436#if REGISTER_WARNINGS
5437 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5438 register_prefix,
5439 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5440 register_prefix, i.op[op].regs->reg_name, i.suffix);
5441#endif
5442 }
5443 /* Warn if the r prefix on a general reg is present. */
5444 else if (i.types[op].bitfield.reg64
5445 && (i.tm.operand_types[op].bitfield.reg32
5446 || i.tm.operand_types[op].bitfield.acc))
5447 {
5448 if (intel_syntax
5449 && i.tm.opcode_modifier.toqword
5450 && !i.types[0].bitfield.regxmm)
5451 {
5452 /* Convert to QWORD. We want REX byte. */
5453 i.suffix = QWORD_MNEM_SUFFIX;
5454 }
5455 else
5456 {
5457 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5458 register_prefix, i.op[op].regs->reg_name,
5459 i.suffix);
5460 return 0;
5461 }
5462 }
5463 return 1;
5464}
5465
5466static int
5467check_qword_reg (void)
5468{
5469 int op;
5470
5471 for (op = i.operands; --op >= 0; )
5472 /* Reject eight bit registers, except where the template requires
5473 them. (eg. movzb) */
5474 if (i.types[op].bitfield.reg8
5475 && (i.tm.operand_types[op].bitfield.reg16
5476 || i.tm.operand_types[op].bitfield.reg32
5477 || i.tm.operand_types[op].bitfield.acc))
5478 {
5479 as_bad (_("`%s%s' not allowed with `%s%c'"),
5480 register_prefix,
5481 i.op[op].regs->reg_name,
5482 i.tm.name,
5483 i.suffix);
5484 return 0;
5485 }
5486 /* Warn if the r prefix on a general reg is missing. */
5487 else if ((i.types[op].bitfield.reg16
5488 || i.types[op].bitfield.reg32)
5489 && (i.tm.operand_types[op].bitfield.reg32
5490 || i.tm.operand_types[op].bitfield.acc))
5491 {
5492 /* Prohibit these changes in the 64bit mode, since the
5493 lowering is more complicated. */
5494 if (intel_syntax
5495 && i.tm.opcode_modifier.todword
5496 && !i.types[0].bitfield.regxmm)
5497 {
5498 /* Convert to DWORD. We don't want REX byte. */
5499 i.suffix = LONG_MNEM_SUFFIX;
5500 }
5501 else
5502 {
5503 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5504 register_prefix, i.op[op].regs->reg_name,
5505 i.suffix);
5506 return 0;
5507 }
5508 }
5509 return 1;
5510}
5511
5512static int
5513check_word_reg (void)
5514{
5515 int op;
5516 for (op = i.operands; --op >= 0;)
5517 /* Reject eight bit registers, except where the template requires
5518 them. (eg. movzb) */
5519 if (i.types[op].bitfield.reg8
5520 && (i.tm.operand_types[op].bitfield.reg16
5521 || i.tm.operand_types[op].bitfield.reg32
5522 || i.tm.operand_types[op].bitfield.acc))
5523 {
5524 as_bad (_("`%s%s' not allowed with `%s%c'"),
5525 register_prefix,
5526 i.op[op].regs->reg_name,
5527 i.tm.name,
5528 i.suffix);
5529 return 0;
5530 }
5531 /* Warn if the e or r prefix on a general reg is present. */
5532 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5533 && (i.types[op].bitfield.reg32
5534 || i.types[op].bitfield.reg64)
5535 && (i.tm.operand_types[op].bitfield.reg16
5536 || i.tm.operand_types[op].bitfield.acc))
5537 {
5538 /* Prohibit these changes in the 64bit mode, since the
5539 lowering is more complicated. */
5540 if (flag_code == CODE_64BIT)
5541 {
5542 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5543 register_prefix, i.op[op].regs->reg_name,
5544 i.suffix);
5545 return 0;
5546 }
5547#if REGISTER_WARNINGS
5548 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5549 register_prefix,
5550 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5551 register_prefix, i.op[op].regs->reg_name, i.suffix);
5552#endif
5553 }
5554 return 1;
5555}
5556
5557static int
5558update_imm (unsigned int j)
5559{
5560 i386_operand_type overlap = i.types[j];
5561 if ((overlap.bitfield.imm8
5562 || overlap.bitfield.imm8s
5563 || overlap.bitfield.imm16
5564 || overlap.bitfield.imm32
5565 || overlap.bitfield.imm32s
5566 || overlap.bitfield.imm64)
5567 && !operand_type_equal (&overlap, &imm8)
5568 && !operand_type_equal (&overlap, &imm8s)
5569 && !operand_type_equal (&overlap, &imm16)
5570 && !operand_type_equal (&overlap, &imm32)
5571 && !operand_type_equal (&overlap, &imm32s)
5572 && !operand_type_equal (&overlap, &imm64))
5573 {
5574 if (i.suffix)
5575 {
5576 i386_operand_type temp;
5577
5578 operand_type_set (&temp, 0);
5579 if (i.suffix == BYTE_MNEM_SUFFIX)
5580 {
5581 temp.bitfield.imm8 = overlap.bitfield.imm8;
5582 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5583 }
5584 else if (i.suffix == WORD_MNEM_SUFFIX)
5585 temp.bitfield.imm16 = overlap.bitfield.imm16;
5586 else if (i.suffix == QWORD_MNEM_SUFFIX)
5587 {
5588 temp.bitfield.imm64 = overlap.bitfield.imm64;
5589 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5590 }
5591 else
5592 temp.bitfield.imm32 = overlap.bitfield.imm32;
5593 overlap = temp;
5594 }
5595 else if (operand_type_equal (&overlap, &imm16_32_32s)
5596 || operand_type_equal (&overlap, &imm16_32)
5597 || operand_type_equal (&overlap, &imm16_32s))
5598 {
5599 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
5600 overlap = imm16;
5601 else
5602 overlap = imm32s;
5603 }
5604 if (!operand_type_equal (&overlap, &imm8)
5605 && !operand_type_equal (&overlap, &imm8s)
5606 && !operand_type_equal (&overlap, &imm16)
5607 && !operand_type_equal (&overlap, &imm32)
5608 && !operand_type_equal (&overlap, &imm32s)
5609 && !operand_type_equal (&overlap, &imm64))
5610 {
5611 as_bad (_("no instruction mnemonic suffix given; "
5612 "can't determine immediate size"));
5613 return 0;
5614 }
5615 }
5616 i.types[j] = overlap;
5617
5618 return 1;
5619}
5620
5621static int
5622finalize_imm (void)
5623{
5624 unsigned int j, n;
5625
5626 /* Update the first 2 immediate operands. */
5627 n = i.operands > 2 ? 2 : i.operands;
5628 if (n)
5629 {
5630 for (j = 0; j < n; j++)
5631 if (update_imm (j) == 0)
5632 return 0;
5633
5634 /* The 3rd operand can't be immediate operand. */
5635 gas_assert (operand_type_check (i.types[2], imm) == 0);
5636 }
5637
5638 return 1;
5639}
5640
5641static int
5642bad_implicit_operand (int xmm)
5643{
5644 const char *ireg = xmm ? "xmm0" : "ymm0";
5645
5646 if (intel_syntax)
5647 as_bad (_("the last operand of `%s' must be `%s%s'"),
5648 i.tm.name, register_prefix, ireg);
5649 else
5650 as_bad (_("the first operand of `%s' must be `%s%s'"),
5651 i.tm.name, register_prefix, ireg);
5652 return 0;
5653}
5654
5655static int
5656process_operands (void)
5657{
5658 /* Default segment register this instruction will use for memory
5659 accesses. 0 means unknown. This is only for optimizing out
5660 unnecessary segment overrides. */
5661 const seg_entry *default_seg = 0;
5662
5663 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
5664 {
5665 unsigned int dupl = i.operands;
5666 unsigned int dest = dupl - 1;
5667 unsigned int j;
5668
5669 /* The destination must be an xmm register. */
5670 gas_assert (i.reg_operands
5671 && MAX_OPERANDS > dupl
5672 && operand_type_equal (&i.types[dest], &regxmm));
5673
5674 if (i.tm.opcode_modifier.firstxmm0)
5675 {
5676 /* The first operand is implicit and must be xmm0. */
5677 gas_assert (operand_type_equal (&i.types[0], &regxmm));
5678 if (register_number (i.op[0].regs) != 0)
5679 return bad_implicit_operand (1);
5680
5681 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
5682 {
5683 /* Keep xmm0 for instructions with VEX prefix and 3
5684 sources. */
5685 goto duplicate;
5686 }
5687 else
5688 {
5689 /* We remove the first xmm0 and keep the number of
5690 operands unchanged, which in fact duplicates the
5691 destination. */
5692 for (j = 1; j < i.operands; j++)
5693 {
5694 i.op[j - 1] = i.op[j];
5695 i.types[j - 1] = i.types[j];
5696 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5697 }
5698 }
5699 }
5700 else if (i.tm.opcode_modifier.implicit1stxmm0)
5701 {
5702 gas_assert ((MAX_OPERANDS - 1) > dupl
5703 && (i.tm.opcode_modifier.vexsources
5704 == VEX3SOURCES));
5705
5706 /* Add the implicit xmm0 for instructions with VEX prefix
5707 and 3 sources. */
5708 for (j = i.operands; j > 0; j--)
5709 {
5710 i.op[j] = i.op[j - 1];
5711 i.types[j] = i.types[j - 1];
5712 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5713 }
5714 i.op[0].regs
5715 = (const reg_entry *) hash_find (reg_hash, "xmm0");
5716 i.types[0] = regxmm;
5717 i.tm.operand_types[0] = regxmm;
5718
5719 i.operands += 2;
5720 i.reg_operands += 2;
5721 i.tm.operands += 2;
5722
5723 dupl++;
5724 dest++;
5725 i.op[dupl] = i.op[dest];
5726 i.types[dupl] = i.types[dest];
5727 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
5728 }
5729 else
5730 {
5731duplicate:
5732 i.operands++;
5733 i.reg_operands++;
5734 i.tm.operands++;
5735
5736 i.op[dupl] = i.op[dest];
5737 i.types[dupl] = i.types[dest];
5738 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
5739 }
5740
5741 if (i.tm.opcode_modifier.immext)
5742 process_immext ();
5743 }
5744 else if (i.tm.opcode_modifier.firstxmm0)
5745 {
5746 unsigned int j;
5747
5748 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5749 gas_assert (i.reg_operands
5750 && (operand_type_equal (&i.types[0], &regxmm)
5751 || operand_type_equal (&i.types[0], &regymm)
5752 || operand_type_equal (&i.types[0], &regzmm)));
5753 if (register_number (i.op[0].regs) != 0)
5754 return bad_implicit_operand (i.types[0].bitfield.regxmm);
5755
5756 for (j = 1; j < i.operands; j++)
5757 {
5758 i.op[j - 1] = i.op[j];
5759 i.types[j - 1] = i.types[j];
5760
5761 /* We need to adjust fields in i.tm since they are used by
5762 build_modrm_byte. */
5763 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5764 }
5765
5766 i.operands--;
5767 i.reg_operands--;
5768 i.tm.operands--;
5769 }
5770 else if (i.tm.opcode_modifier.regkludge)
5771 {
5772 /* The imul $imm, %reg instruction is converted into
5773 imul $imm, %reg, %reg, and the clr %reg instruction
5774 is converted into xor %reg, %reg. */
5775
5776 unsigned int first_reg_op;
5777
5778 if (operand_type_check (i.types[0], reg))
5779 first_reg_op = 0;
5780 else
5781 first_reg_op = 1;
5782 /* Pretend we saw the extra register operand. */
5783 gas_assert (i.reg_operands == 1
5784 && i.op[first_reg_op + 1].regs == 0);
5785 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5786 i.types[first_reg_op + 1] = i.types[first_reg_op];
5787 i.operands++;
5788 i.reg_operands++;
5789 }
5790
5791 if (i.tm.opcode_modifier.shortform)
5792 {
5793 if (i.types[0].bitfield.sreg2
5794 || i.types[0].bitfield.sreg3)
5795 {
5796 if (i.tm.base_opcode == POP_SEG_SHORT
5797 && i.op[0].regs->reg_num == 1)
5798 {
5799 as_bad (_("you can't `pop %scs'"), register_prefix);
5800 return 0;
5801 }
5802 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5803 if ((i.op[0].regs->reg_flags & RegRex) != 0)
5804 i.rex |= REX_B;
5805 }
5806 else
5807 {
5808 /* The register or float register operand is in operand
5809 0 or 1. */
5810 unsigned int op;
5811
5812 if (i.types[0].bitfield.floatreg
5813 || operand_type_check (i.types[0], reg))
5814 op = 0;
5815 else
5816 op = 1;
5817 /* Register goes in low 3 bits of opcode. */
5818 i.tm.base_opcode |= i.op[op].regs->reg_num;
5819 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5820 i.rex |= REX_B;
5821 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
5822 {
5823 /* Warn about some common errors, but press on regardless.
5824 The first case can be generated by gcc (<= 2.8.1). */
5825 if (i.operands == 2)
5826 {
5827 /* Reversed arguments on faddp, fsubp, etc. */
5828 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
5829 register_prefix, i.op[!intel_syntax].regs->reg_name,
5830 register_prefix, i.op[intel_syntax].regs->reg_name);
5831 }
5832 else
5833 {
5834 /* Extraneous `l' suffix on fp insn. */
5835 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5836 register_prefix, i.op[0].regs->reg_name);
5837 }
5838 }
5839 }
5840 }
5841 else if (i.tm.opcode_modifier.modrm)
5842 {
5843 /* The opcode is completed (modulo i.tm.extension_opcode which
5844 must be put into the modrm byte). Now, we make the modrm and
5845 index base bytes based on all the info we've collected. */
5846
5847 default_seg = build_modrm_byte ();
5848 }
5849 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
5850 {
5851 default_seg = &ds;
5852 }
5853 else if (i.tm.opcode_modifier.isstring)
5854 {
5855 /* For the string instructions that allow a segment override
5856 on one of their operands, the default segment is ds. */
5857 default_seg = &ds;
5858 }
5859
5860 if (i.tm.base_opcode == 0x8d /* lea */
5861 && i.seg[0]
5862 && !quiet_warnings)
5863 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
5864
5865 /* If a segment was explicitly specified, and the specified segment
5866 is not the default, use an opcode prefix to select it. If we
5867 never figured out what the default segment is, then default_seg
5868 will be zero at this point, and the specified segment prefix will
5869 always be used. */
5870 if ((i.seg[0]) && (i.seg[0] != default_seg))
5871 {
5872 if (!add_prefix (i.seg[0]->seg_prefix))
5873 return 0;
5874 }
5875 return 1;
5876}
5877
5878static const seg_entry *
5879build_modrm_byte (void)
5880{
5881 const seg_entry *default_seg = 0;
5882 unsigned int source, dest;
5883 int vex_3_sources;
5884
5885 /* The first operand of instructions with VEX prefix and 3 sources
5886 must be VEX_Imm4. */
5887 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
5888 if (vex_3_sources)
5889 {
5890 unsigned int nds, reg_slot;
5891 expressionS *exp;
5892
5893 if (i.tm.opcode_modifier.veximmext
5894 && i.tm.opcode_modifier.immext)
5895 {
5896 dest = i.operands - 2;
5897 gas_assert (dest == 3);
5898 }
5899 else
5900 dest = i.operands - 1;
5901 nds = dest - 1;
5902
5903 /* There are 2 kinds of instructions:
5904 1. 5 operands: 4 register operands or 3 register operands
5905 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5906 VexW0 or VexW1. The destination must be either XMM, YMM or
5907 ZMM register.
5908 2. 4 operands: 4 register operands or 3 register operands
5909 plus 1 memory operand, VexXDS, and VexImmExt */
5910 gas_assert ((i.reg_operands == 4
5911 || (i.reg_operands == 3 && i.mem_operands == 1))
5912 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5913 && (i.tm.opcode_modifier.veximmext
5914 || (i.imm_operands == 1
5915 && i.types[0].bitfield.vec_imm4
5916 && (i.tm.opcode_modifier.vexw == VEXW0
5917 || i.tm.opcode_modifier.vexw == VEXW1)
5918 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5919 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5920 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
5921
5922 if (i.imm_operands == 0)
5923 {
5924 /* When there is no immediate operand, generate an 8bit
5925 immediate operand to encode the first operand. */
5926 exp = &im_expressions[i.imm_operands++];
5927 i.op[i.operands].imms = exp;
5928 i.types[i.operands] = imm8;
5929 i.operands++;
5930 /* If VexW1 is set, the first operand is the source and
5931 the second operand is encoded in the immediate operand. */
5932 if (i.tm.opcode_modifier.vexw == VEXW1)
5933 {
5934 source = 0;
5935 reg_slot = 1;
5936 }
5937 else
5938 {
5939 source = 1;
5940 reg_slot = 0;
5941 }
5942
5943 /* FMA swaps REG and NDS. */
5944 if (i.tm.cpu_flags.bitfield.cpufma)
5945 {
5946 unsigned int tmp;
5947 tmp = reg_slot;
5948 reg_slot = nds;
5949 nds = tmp;
5950 }
5951
5952 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5953 &regxmm)
5954 || operand_type_equal (&i.tm.operand_types[reg_slot],
5955 &regymm)
5956 || operand_type_equal (&i.tm.operand_types[reg_slot],
5957 &regzmm));
5958 exp->X_op = O_constant;
5959 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
5960 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
5961 }
5962 else
5963 {
5964 unsigned int imm_slot;
5965
5966 if (i.tm.opcode_modifier.vexw == VEXW0)
5967 {
5968 /* If VexW0 is set, the third operand is the source and
5969 the second operand is encoded in the immediate
5970 operand. */
5971 source = 2;
5972 reg_slot = 1;
5973 }
5974 else
5975 {
5976 /* VexW1 is set, the second operand is the source and
5977 the third operand is encoded in the immediate
5978 operand. */
5979 source = 1;
5980 reg_slot = 2;
5981 }
5982
5983 if (i.tm.opcode_modifier.immext)
5984 {
5985 /* When ImmExt is set, the immdiate byte is the last
5986 operand. */
5987 imm_slot = i.operands - 1;
5988 source--;
5989 reg_slot--;
5990 }
5991 else
5992 {
5993 imm_slot = 0;
5994
5995 /* Turn on Imm8 so that output_imm will generate it. */
5996 i.types[imm_slot].bitfield.imm8 = 1;
5997 }
5998
5999 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6000 &regxmm)
6001 || operand_type_equal (&i.tm.operand_types[reg_slot],
6002 &regymm)
6003 || operand_type_equal (&i.tm.operand_types[reg_slot],
6004 &regzmm));
6005 i.op[imm_slot].imms->X_add_number
6006 |= register_number (i.op[reg_slot].regs) << 4;
6007 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6008 }
6009
6010 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6011 || operand_type_equal (&i.tm.operand_types[nds],
6012 &regymm)
6013 || operand_type_equal (&i.tm.operand_types[nds],
6014 &regzmm));
6015 i.vex.register_specifier = i.op[nds].regs;
6016 }
6017 else
6018 source = dest = 0;
6019
6020 /* i.reg_operands MUST be the number of real register operands;
6021 implicit registers do not count. If there are 3 register
6022 operands, it must be a instruction with VexNDS. For a
6023 instruction with VexNDD, the destination register is encoded
6024 in VEX prefix. If there are 4 register operands, it must be
6025 a instruction with VEX prefix and 3 sources. */
6026 if (i.mem_operands == 0
6027 && ((i.reg_operands == 2
6028 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6029 || (i.reg_operands == 3
6030 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6031 || (i.reg_operands == 4 && vex_3_sources)))
6032 {
6033 switch (i.operands)
6034 {
6035 case 2:
6036 source = 0;
6037 break;
6038 case 3:
6039 /* When there are 3 operands, one of them may be immediate,
6040 which may be the first or the last operand. Otherwise,
6041 the first operand must be shift count register (cl) or it
6042 is an instruction with VexNDS. */
6043 gas_assert (i.imm_operands == 1
6044 || (i.imm_operands == 0
6045 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6046 || i.types[0].bitfield.shiftcount)));
6047 if (operand_type_check (i.types[0], imm)
6048 || i.types[0].bitfield.shiftcount)
6049 source = 1;
6050 else
6051 source = 0;
6052 break;
6053 case 4:
6054 /* When there are 4 operands, the first two must be 8bit
6055 immediate operands. The source operand will be the 3rd
6056 one.
6057
6058 For instructions with VexNDS, if the first operand
6059 an imm8, the source operand is the 2nd one. If the last
6060 operand is imm8, the source operand is the first one. */
6061 gas_assert ((i.imm_operands == 2
6062 && i.types[0].bitfield.imm8
6063 && i.types[1].bitfield.imm8)
6064 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6065 && i.imm_operands == 1
6066 && (i.types[0].bitfield.imm8
6067 || i.types[i.operands - 1].bitfield.imm8
6068 || i.rounding)));
6069 if (i.imm_operands == 2)
6070 source = 2;
6071 else
6072 {
6073 if (i.types[0].bitfield.imm8)
6074 source = 1;
6075 else
6076 source = 0;
6077 }
6078 break;
6079 case 5:
6080 if (i.tm.opcode_modifier.evex)
6081 {
6082 /* For EVEX instructions, when there are 5 operands, the
6083 first one must be immediate operand. If the second one
6084 is immediate operand, the source operand is the 3th
6085 one. If the last one is immediate operand, the source
6086 operand is the 2nd one. */
6087 gas_assert (i.imm_operands == 2
6088 && i.tm.opcode_modifier.sae
6089 && operand_type_check (i.types[0], imm));
6090 if (operand_type_check (i.types[1], imm))
6091 source = 2;
6092 else if (operand_type_check (i.types[4], imm))
6093 source = 1;
6094 else
6095 abort ();
6096 }
6097 break;
6098 default:
6099 abort ();
6100 }
6101
6102 if (!vex_3_sources)
6103 {
6104 dest = source + 1;
6105
6106 /* RC/SAE operand could be between DEST and SRC. That happens
6107 when one operand is GPR and the other one is XMM/YMM/ZMM
6108 register. */
6109 if (i.rounding && i.rounding->operand == (int) dest)
6110 dest++;
6111
6112 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6113 {
6114 /* For instructions with VexNDS, the register-only source
6115 operand must be 32/64bit integer, XMM, YMM or ZMM
6116 register. It is encoded in VEX prefix. We need to
6117 clear RegMem bit before calling operand_type_equal. */
6118
6119 i386_operand_type op;
6120 unsigned int vvvv;
6121
6122 /* Check register-only source operand when two source
6123 operands are swapped. */
6124 if (!i.tm.operand_types[source].bitfield.baseindex
6125 && i.tm.operand_types[dest].bitfield.baseindex)
6126 {
6127 vvvv = source;
6128 source = dest;
6129 }
6130 else
6131 vvvv = dest;
6132
6133 op = i.tm.operand_types[vvvv];
6134 op.bitfield.regmem = 0;
6135 if ((dest + 1) >= i.operands
6136 || (op.bitfield.reg32 != 1
6137 && !op.bitfield.reg64 != 1
6138 && !operand_type_equal (&op, &regxmm)
6139 && !operand_type_equal (&op, &regymm)
6140 && !operand_type_equal (&op, &regzmm)
6141 && !operand_type_equal (&op, &regmask)))
6142 abort ();
6143 i.vex.register_specifier = i.op[vvvv].regs;
6144 dest++;
6145 }
6146 }
6147
6148 i.rm.mode = 3;
6149 /* One of the register operands will be encoded in the i.tm.reg
6150 field, the other in the combined i.tm.mode and i.tm.regmem
6151 fields. If no form of this instruction supports a memory
6152 destination operand, then we assume the source operand may
6153 sometimes be a memory operand and so we need to store the
6154 destination in the i.rm.reg field. */
6155 if (!i.tm.operand_types[dest].bitfield.regmem
6156 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6157 {
6158 i.rm.reg = i.op[dest].regs->reg_num;
6159 i.rm.regmem = i.op[source].regs->reg_num;
6160 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6161 i.rex |= REX_R;
6162 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6163 i.vrex |= REX_R;
6164 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6165 i.rex |= REX_B;
6166 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6167 i.vrex |= REX_B;
6168 }
6169 else
6170 {
6171 i.rm.reg = i.op[source].regs->reg_num;
6172 i.rm.regmem = i.op[dest].regs->reg_num;
6173 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6174 i.rex |= REX_B;
6175 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6176 i.vrex |= REX_B;
6177 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6178 i.rex |= REX_R;
6179 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6180 i.vrex |= REX_R;
6181 }
6182 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6183 {
6184 if (!i.types[0].bitfield.control
6185 && !i.types[1].bitfield.control)
6186 abort ();
6187 i.rex &= ~(REX_R | REX_B);
6188 add_prefix (LOCK_PREFIX_OPCODE);
6189 }
6190 }
6191 else
6192 { /* If it's not 2 reg operands... */
6193 unsigned int mem;
6194
6195 if (i.mem_operands)
6196 {
6197 unsigned int fake_zero_displacement = 0;
6198 unsigned int op;
6199
6200 for (op = 0; op < i.operands; op++)
6201 if (operand_type_check (i.types[op], anymem))
6202 break;
6203 gas_assert (op < i.operands);
6204
6205 if (i.tm.opcode_modifier.vecsib)
6206 {
6207 if (i.index_reg->reg_num == RegEiz
6208 || i.index_reg->reg_num == RegRiz)
6209 abort ();
6210
6211 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6212 if (!i.base_reg)
6213 {
6214 i.sib.base = NO_BASE_REGISTER;
6215 i.sib.scale = i.log2_scale_factor;
6216 /* No Vec_Disp8 if there is no base. */
6217 i.types[op].bitfield.vec_disp8 = 0;
6218 i.types[op].bitfield.disp8 = 0;
6219 i.types[op].bitfield.disp16 = 0;
6220 i.types[op].bitfield.disp64 = 0;
6221 if (flag_code != CODE_64BIT)
6222 {
6223 /* Must be 32 bit */
6224 i.types[op].bitfield.disp32 = 1;
6225 i.types[op].bitfield.disp32s = 0;
6226 }
6227 else
6228 {
6229 i.types[op].bitfield.disp32 = 0;
6230 i.types[op].bitfield.disp32s = 1;
6231 }
6232 }
6233 i.sib.index = i.index_reg->reg_num;
6234 if ((i.index_reg->reg_flags & RegRex) != 0)
6235 i.rex |= REX_X;
6236 if ((i.index_reg->reg_flags & RegVRex) != 0)
6237 i.vrex |= REX_X;
6238 }
6239
6240 default_seg = &ds;
6241
6242 if (i.base_reg == 0)
6243 {
6244 i.rm.mode = 0;
6245 if (!i.disp_operands)
6246 {
6247 fake_zero_displacement = 1;
6248 /* Instructions with VSIB byte need 32bit displacement
6249 if there is no base register. */
6250 if (i.tm.opcode_modifier.vecsib)
6251 i.types[op].bitfield.disp32 = 1;
6252 }
6253 if (i.index_reg == 0)
6254 {
6255 gas_assert (!i.tm.opcode_modifier.vecsib);
6256 /* Operand is just <disp> */
6257 if (flag_code == CODE_64BIT)
6258 {
6259 /* 64bit mode overwrites the 32bit absolute
6260 addressing by RIP relative addressing and
6261 absolute addressing is encoded by one of the
6262 redundant SIB forms. */
6263 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6264 i.sib.base = NO_BASE_REGISTER;
6265 i.sib.index = NO_INDEX_REGISTER;
6266 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
6267 ? disp32s : disp32);
6268 }
6269 else if ((flag_code == CODE_16BIT)
6270 ^ (i.prefix[ADDR_PREFIX] != 0))
6271 {
6272 i.rm.regmem = NO_BASE_REGISTER_16;
6273 i.types[op] = disp16;
6274 }
6275 else
6276 {
6277 i.rm.regmem = NO_BASE_REGISTER;
6278 i.types[op] = disp32;
6279 }
6280 }
6281 else if (!i.tm.opcode_modifier.vecsib)
6282 {
6283 /* !i.base_reg && i.index_reg */
6284 if (i.index_reg->reg_num == RegEiz
6285 || i.index_reg->reg_num == RegRiz)
6286 i.sib.index = NO_INDEX_REGISTER;
6287 else
6288 i.sib.index = i.index_reg->reg_num;
6289 i.sib.base = NO_BASE_REGISTER;
6290 i.sib.scale = i.log2_scale_factor;
6291 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6292 /* No Vec_Disp8 if there is no base. */
6293 i.types[op].bitfield.vec_disp8 = 0;
6294 i.types[op].bitfield.disp8 = 0;
6295 i.types[op].bitfield.disp16 = 0;
6296 i.types[op].bitfield.disp64 = 0;
6297 if (flag_code != CODE_64BIT)
6298 {
6299 /* Must be 32 bit */
6300 i.types[op].bitfield.disp32 = 1;
6301 i.types[op].bitfield.disp32s = 0;
6302 }
6303 else
6304 {
6305 i.types[op].bitfield.disp32 = 0;
6306 i.types[op].bitfield.disp32s = 1;
6307 }
6308 if ((i.index_reg->reg_flags & RegRex) != 0)
6309 i.rex |= REX_X;
6310 }
6311 }
6312 /* RIP addressing for 64bit mode. */
6313 else if (i.base_reg->reg_num == RegRip ||
6314 i.base_reg->reg_num == RegEip)
6315 {
6316 gas_assert (!i.tm.opcode_modifier.vecsib);
6317 i.rm.regmem = NO_BASE_REGISTER;
6318 i.types[op].bitfield.disp8 = 0;
6319 i.types[op].bitfield.disp16 = 0;
6320 i.types[op].bitfield.disp32 = 0;
6321 i.types[op].bitfield.disp32s = 1;
6322 i.types[op].bitfield.disp64 = 0;
6323 i.types[op].bitfield.vec_disp8 = 0;
6324 i.flags[op] |= Operand_PCrel;
6325 if (! i.disp_operands)
6326 fake_zero_displacement = 1;
6327 }
6328 else if (i.base_reg->reg_type.bitfield.reg16)
6329 {
6330 gas_assert (!i.tm.opcode_modifier.vecsib);
6331 switch (i.base_reg->reg_num)
6332 {
6333 case 3: /* (%bx) */
6334 if (i.index_reg == 0)
6335 i.rm.regmem = 7;
6336 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6337 i.rm.regmem = i.index_reg->reg_num - 6;
6338 break;
6339 case 5: /* (%bp) */
6340 default_seg = &ss;
6341 if (i.index_reg == 0)
6342 {
6343 i.rm.regmem = 6;
6344 if (operand_type_check (i.types[op], disp) == 0)
6345 {
6346 /* fake (%bp) into 0(%bp) */
6347 if (i.tm.operand_types[op].bitfield.vec_disp8)
6348 i.types[op].bitfield.vec_disp8 = 1;
6349 else
6350 i.types[op].bitfield.disp8 = 1;
6351 fake_zero_displacement = 1;
6352 }
6353 }
6354 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6355 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6356 break;
6357 default: /* (%si) -> 4 or (%di) -> 5 */
6358 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6359 }
6360 i.rm.mode = mode_from_disp_size (i.types[op]);
6361 }
6362 else /* i.base_reg and 32/64 bit mode */
6363 {
6364 if (flag_code == CODE_64BIT
6365 && operand_type_check (i.types[op], disp))
6366 {
6367 i386_operand_type temp;
6368 operand_type_set (&temp, 0);
6369 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
6370 temp.bitfield.vec_disp8
6371 = i.types[op].bitfield.vec_disp8;
6372 i.types[op] = temp;
6373 if (i.prefix[ADDR_PREFIX] == 0)
6374 i.types[op].bitfield.disp32s = 1;
6375 else
6376 i.types[op].bitfield.disp32 = 1;
6377 }
6378
6379 if (!i.tm.opcode_modifier.vecsib)
6380 i.rm.regmem = i.base_reg->reg_num;
6381 if ((i.base_reg->reg_flags & RegRex) != 0)
6382 i.rex |= REX_B;
6383 i.sib.base = i.base_reg->reg_num;
6384 /* x86-64 ignores REX prefix bit here to avoid decoder
6385 complications. */
6386 if (!(i.base_reg->reg_flags & RegRex)
6387 && (i.base_reg->reg_num == EBP_REG_NUM
6388 || i.base_reg->reg_num == ESP_REG_NUM))
6389 default_seg = &ss;
6390 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
6391 {
6392 fake_zero_displacement = 1;
6393 if (i.tm.operand_types [op].bitfield.vec_disp8)
6394 i.types[op].bitfield.vec_disp8 = 1;
6395 else
6396 i.types[op].bitfield.disp8 = 1;
6397 }
6398 i.sib.scale = i.log2_scale_factor;
6399 if (i.index_reg == 0)
6400 {
6401 gas_assert (!i.tm.opcode_modifier.vecsib);
6402 /* <disp>(%esp) becomes two byte modrm with no index
6403 register. We've already stored the code for esp
6404 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6405 Any base register besides %esp will not use the
6406 extra modrm byte. */
6407 i.sib.index = NO_INDEX_REGISTER;
6408 }
6409 else if (!i.tm.opcode_modifier.vecsib)
6410 {
6411 if (i.index_reg->reg_num == RegEiz
6412 || i.index_reg->reg_num == RegRiz)
6413 i.sib.index = NO_INDEX_REGISTER;
6414 else
6415 i.sib.index = i.index_reg->reg_num;
6416 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6417 if ((i.index_reg->reg_flags & RegRex) != 0)
6418 i.rex |= REX_X;
6419 }
6420
6421 if (i.disp_operands
6422 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6423 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6424 i.rm.mode = 0;
6425 else
6426 {
6427 if (!fake_zero_displacement
6428 && !i.disp_operands
6429 && i.disp_encoding)
6430 {
6431 fake_zero_displacement = 1;
6432 if (i.disp_encoding == disp_encoding_8bit)
6433 i.types[op].bitfield.disp8 = 1;
6434 else
6435 i.types[op].bitfield.disp32 = 1;
6436 }
6437 i.rm.mode = mode_from_disp_size (i.types[op]);
6438 }
6439 }
6440
6441 if (fake_zero_displacement)
6442 {
6443 /* Fakes a zero displacement assuming that i.types[op]
6444 holds the correct displacement size. */
6445 expressionS *exp;
6446
6447 gas_assert (i.op[op].disps == 0);
6448 exp = &disp_expressions[i.disp_operands++];
6449 i.op[op].disps = exp;
6450 exp->X_op = O_constant;
6451 exp->X_add_number = 0;
6452 exp->X_add_symbol = (symbolS *) 0;
6453 exp->X_op_symbol = (symbolS *) 0;
6454 }
6455
6456 mem = op;
6457 }
6458 else
6459 mem = ~0;
6460
6461 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
6462 {
6463 if (operand_type_check (i.types[0], imm))
6464 i.vex.register_specifier = NULL;
6465 else
6466 {
6467 /* VEX.vvvv encodes one of the sources when the first
6468 operand is not an immediate. */
6469 if (i.tm.opcode_modifier.vexw == VEXW0)
6470 i.vex.register_specifier = i.op[0].regs;
6471 else
6472 i.vex.register_specifier = i.op[1].regs;
6473 }
6474
6475 /* Destination is a XMM register encoded in the ModRM.reg
6476 and VEX.R bit. */
6477 i.rm.reg = i.op[2].regs->reg_num;
6478 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6479 i.rex |= REX_R;
6480
6481 /* ModRM.rm and VEX.B encodes the other source. */
6482 if (!i.mem_operands)
6483 {
6484 i.rm.mode = 3;
6485
6486 if (i.tm.opcode_modifier.vexw == VEXW0)
6487 i.rm.regmem = i.op[1].regs->reg_num;
6488 else
6489 i.rm.regmem = i.op[0].regs->reg_num;
6490
6491 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6492 i.rex |= REX_B;
6493 }
6494 }
6495 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
6496 {
6497 i.vex.register_specifier = i.op[2].regs;
6498 if (!i.mem_operands)
6499 {
6500 i.rm.mode = 3;
6501 i.rm.regmem = i.op[1].regs->reg_num;
6502 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6503 i.rex |= REX_B;
6504 }
6505 }
6506 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6507 (if any) based on i.tm.extension_opcode. Again, we must be
6508 careful to make sure that segment/control/debug/test/MMX
6509 registers are coded into the i.rm.reg field. */
6510 else if (i.reg_operands)
6511 {
6512 unsigned int op;
6513 unsigned int vex_reg = ~0;
6514
6515 for (op = 0; op < i.operands; op++)
6516 if (i.types[op].bitfield.reg8
6517 || i.types[op].bitfield.reg16
6518 || i.types[op].bitfield.reg32
6519 || i.types[op].bitfield.reg64
6520 || i.types[op].bitfield.regmmx
6521 || i.types[op].bitfield.regxmm
6522 || i.types[op].bitfield.regymm
6523 || i.types[op].bitfield.regbnd
6524 || i.types[op].bitfield.regzmm
6525 || i.types[op].bitfield.regmask
6526 || i.types[op].bitfield.sreg2
6527 || i.types[op].bitfield.sreg3
6528 || i.types[op].bitfield.control
6529 || i.types[op].bitfield.debug
6530 || i.types[op].bitfield.test)
6531 break;
6532
6533 if (vex_3_sources)
6534 op = dest;
6535 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6536 {
6537 /* For instructions with VexNDS, the register-only
6538 source operand is encoded in VEX prefix. */
6539 gas_assert (mem != (unsigned int) ~0);
6540
6541 if (op > mem)
6542 {
6543 vex_reg = op++;
6544 gas_assert (op < i.operands);
6545 }
6546 else
6547 {
6548 /* Check register-only source operand when two source
6549 operands are swapped. */
6550 if (!i.tm.operand_types[op].bitfield.baseindex
6551 && i.tm.operand_types[op + 1].bitfield.baseindex)
6552 {
6553 vex_reg = op;
6554 op += 2;
6555 gas_assert (mem == (vex_reg + 1)
6556 && op < i.operands);
6557 }
6558 else
6559 {
6560 vex_reg = op + 1;
6561 gas_assert (vex_reg < i.operands);
6562 }
6563 }
6564 }
6565 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
6566 {
6567 /* For instructions with VexNDD, the register destination
6568 is encoded in VEX prefix. */
6569 if (i.mem_operands == 0)
6570 {
6571 /* There is no memory operand. */
6572 gas_assert ((op + 2) == i.operands);
6573 vex_reg = op + 1;
6574 }
6575 else
6576 {
6577 /* There are only 2 operands. */
6578 gas_assert (op < 2 && i.operands == 2);
6579 vex_reg = 1;
6580 }
6581 }
6582 else
6583 gas_assert (op < i.operands);
6584
6585 if (vex_reg != (unsigned int) ~0)
6586 {
6587 i386_operand_type *type = &i.tm.operand_types[vex_reg];
6588
6589 if (type->bitfield.reg32 != 1
6590 && type->bitfield.reg64 != 1
6591 && !operand_type_equal (type, &regxmm)
6592 && !operand_type_equal (type, &regymm)
6593 && !operand_type_equal (type, &regzmm)
6594 && !operand_type_equal (type, &regmask))
6595 abort ();
6596
6597 i.vex.register_specifier = i.op[vex_reg].regs;
6598 }
6599
6600 /* Don't set OP operand twice. */
6601 if (vex_reg != op)
6602 {
6603 /* If there is an extension opcode to put here, the
6604 register number must be put into the regmem field. */
6605 if (i.tm.extension_opcode != None)
6606 {
6607 i.rm.regmem = i.op[op].regs->reg_num;
6608 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6609 i.rex |= REX_B;
6610 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6611 i.vrex |= REX_B;
6612 }
6613 else
6614 {
6615 i.rm.reg = i.op[op].regs->reg_num;
6616 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6617 i.rex |= REX_R;
6618 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6619 i.vrex |= REX_R;
6620 }
6621 }
6622
6623 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6624 must set it to 3 to indicate this is a register operand
6625 in the regmem field. */
6626 if (!i.mem_operands)
6627 i.rm.mode = 3;
6628 }
6629
6630 /* Fill in i.rm.reg field with extension opcode (if any). */
6631 if (i.tm.extension_opcode != None)
6632 i.rm.reg = i.tm.extension_opcode;
6633 }
6634 return default_seg;
6635}
6636
6637static void
6638output_branch (void)
6639{
6640 char *p;
6641 int size;
6642 int code16;
6643 int prefix;
6644 relax_substateT subtype;
6645 symbolS *sym;
6646 offsetT off;
6647
6648 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
6649 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
6650
6651 prefix = 0;
6652 if (i.prefix[DATA_PREFIX] != 0)
6653 {
6654 prefix = 1;
6655 i.prefixes -= 1;
6656 code16 ^= CODE16;
6657 }
6658 /* Pentium4 branch hints. */
6659 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6660 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6661 {
6662 prefix++;
6663 i.prefixes--;
6664 }
6665 if (i.prefix[REX_PREFIX] != 0)
6666 {
6667 prefix++;
6668 i.prefixes--;
6669 }
6670
6671 /* BND prefixed jump. */
6672 if (i.prefix[BND_PREFIX] != 0)
6673 {
6674 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6675 i.prefixes -= 1;
6676 }
6677
6678 if (i.prefixes != 0 && !intel_syntax)
6679 as_warn (_("skipping prefixes on this instruction"));
6680
6681 /* It's always a symbol; End frag & setup for relax.
6682 Make sure there is enough room in this frag for the largest
6683 instruction we may generate in md_convert_frag. This is 2
6684 bytes for the opcode and room for the prefix and largest
6685 displacement. */
6686 frag_grow (prefix + 2 + 4);
6687 /* Prefix and 1 opcode byte go in fr_fix. */
6688 p = frag_more (prefix + 1);
6689 if (i.prefix[DATA_PREFIX] != 0)
6690 *p++ = DATA_PREFIX_OPCODE;
6691 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6692 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6693 *p++ = i.prefix[SEG_PREFIX];
6694 if (i.prefix[REX_PREFIX] != 0)
6695 *p++ = i.prefix[REX_PREFIX];
6696 *p = i.tm.base_opcode;
6697
6698 if ((unsigned char) *p == JUMP_PC_RELATIVE)
6699 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
6700 else if (cpu_arch_flags.bitfield.cpui386)
6701 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
6702 else
6703 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
6704 subtype |= code16;
6705
6706 sym = i.op[0].disps->X_add_symbol;
6707 off = i.op[0].disps->X_add_number;
6708
6709 if (i.op[0].disps->X_op != O_constant
6710 && i.op[0].disps->X_op != O_symbol)
6711 {
6712 /* Handle complex expressions. */
6713 sym = make_expr_symbol (i.op[0].disps);
6714 off = 0;
6715 }
6716
6717 /* 1 possible extra opcode + 4 byte displacement go in var part.
6718 Pass reloc in fr_var. */
6719 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
6720}
6721
6722static void
6723output_jump (void)
6724{
6725 char *p;
6726 int size;
6727 fixS *fixP;
6728
6729 if (i.tm.opcode_modifier.jumpbyte)
6730 {
6731 /* This is a loop or jecxz type instruction. */
6732 size = 1;
6733 if (i.prefix[ADDR_PREFIX] != 0)
6734 {
6735 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6736 i.prefixes -= 1;
6737 }
6738 /* Pentium4 branch hints. */
6739 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6740 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6741 {
6742 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6743 i.prefixes--;
6744 }
6745 }
6746 else
6747 {
6748 int code16;
6749
6750 code16 = 0;
6751 if (flag_code == CODE_16BIT)
6752 code16 = CODE16;
6753
6754 if (i.prefix[DATA_PREFIX] != 0)
6755 {
6756 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6757 i.prefixes -= 1;
6758 code16 ^= CODE16;
6759 }
6760
6761 size = 4;
6762 if (code16)
6763 size = 2;
6764 }
6765
6766 if (i.prefix[REX_PREFIX] != 0)
6767 {
6768 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6769 i.prefixes -= 1;
6770 }
6771
6772 /* BND prefixed jump. */
6773 if (i.prefix[BND_PREFIX] != 0)
6774 {
6775 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6776 i.prefixes -= 1;
6777 }
6778
6779 if (i.prefixes != 0 && !intel_syntax)
6780 as_warn (_("skipping prefixes on this instruction"));
6781
6782 p = frag_more (i.tm.opcode_length + size);
6783 switch (i.tm.opcode_length)
6784 {
6785 case 2:
6786 *p++ = i.tm.base_opcode >> 8;
6787 case 1:
6788 *p++ = i.tm.base_opcode;
6789 break;
6790 default:
6791 abort ();
6792 }
6793
6794 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6795 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
6796
6797 /* All jumps handled here are signed, but don't use a signed limit
6798 check for 32 and 16 bit jumps as we want to allow wrap around at
6799 4G and 64k respectively. */
6800 if (size == 1)
6801 fixP->fx_signed = 1;
6802}
6803
6804static void
6805output_interseg_jump (void)
6806{
6807 char *p;
6808 int size;
6809 int prefix;
6810 int code16;
6811
6812 code16 = 0;
6813 if (flag_code == CODE_16BIT)
6814 code16 = CODE16;
6815
6816 prefix = 0;
6817 if (i.prefix[DATA_PREFIX] != 0)
6818 {
6819 prefix = 1;
6820 i.prefixes -= 1;
6821 code16 ^= CODE16;
6822 }
6823 if (i.prefix[REX_PREFIX] != 0)
6824 {
6825 prefix++;
6826 i.prefixes -= 1;
6827 }
6828
6829 size = 4;
6830 if (code16)
6831 size = 2;
6832
6833 if (i.prefixes != 0 && !intel_syntax)
6834 as_warn (_("skipping prefixes on this instruction"));
6835
6836 /* 1 opcode; 2 segment; offset */
6837 p = frag_more (prefix + 1 + 2 + size);
6838
6839 if (i.prefix[DATA_PREFIX] != 0)
6840 *p++ = DATA_PREFIX_OPCODE;
6841
6842 if (i.prefix[REX_PREFIX] != 0)
6843 *p++ = i.prefix[REX_PREFIX];
6844
6845 *p++ = i.tm.base_opcode;
6846 if (i.op[1].imms->X_op == O_constant)
6847 {
6848 offsetT n = i.op[1].imms->X_add_number;
6849
6850 if (size == 2
6851 && !fits_in_unsigned_word (n)
6852 && !fits_in_signed_word (n))
6853 {
6854 as_bad (_("16-bit jump out of range"));
6855 return;
6856 }
6857 md_number_to_chars (p, n, size);
6858 }
6859 else
6860 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6861 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
6862 if (i.op[0].imms->X_op != O_constant)
6863 as_bad (_("can't handle non absolute segment in `%s'"),
6864 i.tm.name);
6865 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6866}
6867
6868static void
6869output_insn (void)
6870{
6871 fragS *insn_start_frag;
6872 offsetT insn_start_off;
6873
6874 /* Tie dwarf2 debug info to the address at the start of the insn.
6875 We can't do this after the insn has been output as the current
6876 frag may have been closed off. eg. by frag_var. */
6877 dwarf2_emit_insn (0);
6878
6879 insn_start_frag = frag_now;
6880 insn_start_off = frag_now_fix ();
6881
6882 /* Output jumps. */
6883 if (i.tm.opcode_modifier.jump)
6884 output_branch ();
6885 else if (i.tm.opcode_modifier.jumpbyte
6886 || i.tm.opcode_modifier.jumpdword)
6887 output_jump ();
6888 else if (i.tm.opcode_modifier.jumpintersegment)
6889 output_interseg_jump ();
6890 else
6891 {
6892 /* Output normal instructions here. */
6893 char *p;
6894 unsigned char *q;
6895 unsigned int j;
6896 unsigned int prefix;
6897
6898 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6899 don't need the explicit prefix. */
6900 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
6901 {
6902 switch (i.tm.opcode_length)
6903 {
6904 case 3:
6905 if (i.tm.base_opcode & 0xff000000)
6906 {
6907 prefix = (i.tm.base_opcode >> 24) & 0xff;
6908 goto check_prefix;
6909 }
6910 break;
6911 case 2:
6912 if ((i.tm.base_opcode & 0xff0000) != 0)
6913 {
6914 prefix = (i.tm.base_opcode >> 16) & 0xff;
6915 if (i.tm.cpu_flags.bitfield.cpupadlock)
6916 {
6917check_prefix:
6918 if (prefix != REPE_PREFIX_OPCODE
6919 || (i.prefix[REP_PREFIX]
6920 != REPE_PREFIX_OPCODE))
6921 add_prefix (prefix);
6922 }
6923 else
6924 add_prefix (prefix);
6925 }
6926 break;
6927 case 1:
6928 break;
6929 default:
6930 abort ();
6931 }
6932
6933 /* The prefix bytes. */
6934 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6935 if (*q)
6936 FRAG_APPEND_1_CHAR (*q);
6937 }
6938 else
6939 {
6940 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6941 if (*q)
6942 switch (j)
6943 {
6944 case REX_PREFIX:
6945 /* REX byte is encoded in VEX prefix. */
6946 break;
6947 case SEG_PREFIX:
6948 case ADDR_PREFIX:
6949 FRAG_APPEND_1_CHAR (*q);
6950 break;
6951 default:
6952 /* There should be no other prefixes for instructions
6953 with VEX prefix. */
6954 abort ();
6955 }
6956
6957 /* For EVEX instructions i.vrex should become 0 after
6958 build_evex_prefix. For VEX instructions upper 16 registers
6959 aren't available, so VREX should be 0. */
6960 if (i.vrex)
6961 abort ();
6962 /* Now the VEX prefix. */
6963 p = frag_more (i.vex.length);
6964 for (j = 0; j < i.vex.length; j++)
6965 p[j] = i.vex.bytes[j];
6966 }
6967
6968 /* Now the opcode; be careful about word order here! */
6969 if (i.tm.opcode_length == 1)
6970 {
6971 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
6972 }
6973 else
6974 {
6975 switch (i.tm.opcode_length)
6976 {
6977 case 4:
6978 p = frag_more (4);
6979 *p++ = (i.tm.base_opcode >> 24) & 0xff;
6980 *p++ = (i.tm.base_opcode >> 16) & 0xff;
6981 break;
6982 case 3:
6983 p = frag_more (3);
6984 *p++ = (i.tm.base_opcode >> 16) & 0xff;
6985 break;
6986 case 2:
6987 p = frag_more (2);
6988 break;
6989 default:
6990 abort ();
6991 break;
6992 }
6993
6994 /* Put out high byte first: can't use md_number_to_chars! */
6995 *p++ = (i.tm.base_opcode >> 8) & 0xff;
6996 *p = i.tm.base_opcode & 0xff;
6997 }
6998
6999 /* Now the modrm byte and sib byte (if present). */
7000 if (i.tm.opcode_modifier.modrm)
7001 {
7002 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7003 | i.rm.reg << 3
7004 | i.rm.mode << 6));
7005 /* If i.rm.regmem == ESP (4)
7006 && i.rm.mode != (Register mode)
7007 && not 16 bit
7008 ==> need second modrm byte. */
7009 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7010 && i.rm.mode != 3
7011 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
7012 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7013 | i.sib.index << 3
7014 | i.sib.scale << 6));
7015 }
7016
7017 if (i.disp_operands)
7018 output_disp (insn_start_frag, insn_start_off);
7019
7020 if (i.imm_operands)
7021 output_imm (insn_start_frag, insn_start_off);
7022 }
7023
7024#ifdef DEBUG386
7025 if (flag_debug)
7026 {
7027 pi ("" /*line*/, &i);
7028 }
7029#endif /* DEBUG386 */
7030}
7031
7032/* Return the size of the displacement operand N. */
7033
7034static int
7035disp_size (unsigned int n)
7036{
7037 int size = 4;
7038
7039 /* Vec_Disp8 has to be 8bit. */
7040 if (i.types[n].bitfield.vec_disp8)
7041 size = 1;
7042 else if (i.types[n].bitfield.disp64)
7043 size = 8;
7044 else if (i.types[n].bitfield.disp8)
7045 size = 1;
7046 else if (i.types[n].bitfield.disp16)
7047 size = 2;
7048 return size;
7049}
7050
7051/* Return the size of the immediate operand N. */
7052
7053static int
7054imm_size (unsigned int n)
7055{
7056 int size = 4;
7057 if (i.types[n].bitfield.imm64)
7058 size = 8;
7059 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7060 size = 1;
7061 else if (i.types[n].bitfield.imm16)
7062 size = 2;
7063 return size;
7064}
7065
7066static void
7067output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7068{
7069 char *p;
7070 unsigned int n;
7071
7072 for (n = 0; n < i.operands; n++)
7073 {
7074 if (i.types[n].bitfield.vec_disp8
7075 || operand_type_check (i.types[n], disp))
7076 {
7077 if (i.op[n].disps->X_op == O_constant)
7078 {
7079 int size = disp_size (n);
7080 offsetT val = i.op[n].disps->X_add_number;
7081
7082 if (i.types[n].bitfield.vec_disp8)
7083 val >>= i.memshift;
7084 val = offset_in_range (val, size);
7085 p = frag_more (size);
7086 md_number_to_chars (p, val, size);
7087 }
7088 else
7089 {
7090 enum bfd_reloc_code_real reloc_type;
7091 int size = disp_size (n);
7092 int sign = i.types[n].bitfield.disp32s;
7093 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7094
7095 /* We can't have 8 bit displacement here. */
7096 gas_assert (!i.types[n].bitfield.disp8);
7097
7098 /* The PC relative address is computed relative
7099 to the instruction boundary, so in case immediate
7100 fields follows, we need to adjust the value. */
7101 if (pcrel && i.imm_operands)
7102 {
7103 unsigned int n1;
7104 int sz = 0;
7105
7106 for (n1 = 0; n1 < i.operands; n1++)
7107 if (operand_type_check (i.types[n1], imm))
7108 {
7109 /* Only one immediate is allowed for PC
7110 relative address. */
7111 gas_assert (sz == 0);
7112 sz = imm_size (n1);
7113 i.op[n].disps->X_add_number -= sz;
7114 }
7115 /* We should find the immediate. */
7116 gas_assert (sz != 0);
7117 }
7118
7119 p = frag_more (size);
7120 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7121 if (GOT_symbol
7122 && GOT_symbol == i.op[n].disps->X_add_symbol
7123 && (((reloc_type == BFD_RELOC_32
7124 || reloc_type == BFD_RELOC_X86_64_32S
7125 || (reloc_type == BFD_RELOC_64
7126 && object_64bit))
7127 && (i.op[n].disps->X_op == O_symbol
7128 || (i.op[n].disps->X_op == O_add
7129 && ((symbol_get_value_expression
7130 (i.op[n].disps->X_op_symbol)->X_op)
7131 == O_subtract))))
7132 || reloc_type == BFD_RELOC_32_PCREL))
7133 {
7134 offsetT add;
7135
7136 if (insn_start_frag == frag_now)
7137 add = (p - frag_now->fr_literal) - insn_start_off;
7138 else
7139 {
7140 fragS *fr;
7141
7142 add = insn_start_frag->fr_fix - insn_start_off;
7143 for (fr = insn_start_frag->fr_next;
7144 fr && fr != frag_now; fr = fr->fr_next)
7145 add += fr->fr_fix;
7146 add += p - frag_now->fr_literal;
7147 }
7148
7149 if (!object_64bit)
7150 {
7151 reloc_type = BFD_RELOC_386_GOTPC;
7152 i.op[n].imms->X_add_number += add;
7153 }
7154 else if (reloc_type == BFD_RELOC_64)
7155 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7156 else
7157 /* Don't do the adjustment for x86-64, as there
7158 the pcrel addressing is relative to the _next_
7159 insn, and that is taken care of in other code. */
7160 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7161 }
7162 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7163 i.op[n].disps, pcrel, reloc_type);
7164 }
7165 }
7166 }
7167}
7168
7169static void
7170output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7171{
7172 char *p;
7173 unsigned int n;
7174
7175 for (n = 0; n < i.operands; n++)
7176 {
7177 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7178 if (i.rounding && (int) n == i.rounding->operand)
7179 continue;
7180
7181 if (operand_type_check (i.types[n], imm))
7182 {
7183 if (i.op[n].imms->X_op == O_constant)
7184 {
7185 int size = imm_size (n);
7186 offsetT val;
7187
7188 val = offset_in_range (i.op[n].imms->X_add_number,
7189 size);
7190 p = frag_more (size);
7191 md_number_to_chars (p, val, size);
7192 }
7193 else
7194 {
7195 /* Not absolute_section.
7196 Need a 32-bit fixup (don't support 8bit
7197 non-absolute imms). Try to support other
7198 sizes ... */
7199 enum bfd_reloc_code_real reloc_type;
7200 int size = imm_size (n);
7201 int sign;
7202
7203 if (i.types[n].bitfield.imm32s
7204 && (i.suffix == QWORD_MNEM_SUFFIX
7205 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7206 sign = 1;
7207 else
7208 sign = 0;
7209
7210 p = frag_more (size);
7211 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7212
7213 /* This is tough to explain. We end up with this one if we
7214 * have operands that look like
7215 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7216 * obtain the absolute address of the GOT, and it is strongly
7217 * preferable from a performance point of view to avoid using
7218 * a runtime relocation for this. The actual sequence of
7219 * instructions often look something like:
7220 *
7221 * call .L66
7222 * .L66:
7223 * popl %ebx
7224 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7225 *
7226 * The call and pop essentially return the absolute address
7227 * of the label .L66 and store it in %ebx. The linker itself
7228 * will ultimately change the first operand of the addl so
7229 * that %ebx points to the GOT, but to keep things simple, the
7230 * .o file must have this operand set so that it generates not
7231 * the absolute address of .L66, but the absolute address of
7232 * itself. This allows the linker itself simply treat a GOTPC
7233 * relocation as asking for a pcrel offset to the GOT to be
7234 * added in, and the addend of the relocation is stored in the
7235 * operand field for the instruction itself.
7236 *
7237 * Our job here is to fix the operand so that it would add
7238 * the correct offset so that %ebx would point to itself. The
7239 * thing that is tricky is that .-.L66 will point to the
7240 * beginning of the instruction, so we need to further modify
7241 * the operand so that it will point to itself. There are
7242 * other cases where you have something like:
7243 *
7244 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7245 *
7246 * and here no correction would be required. Internally in
7247 * the assembler we treat operands of this form as not being
7248 * pcrel since the '.' is explicitly mentioned, and I wonder
7249 * whether it would simplify matters to do it this way. Who
7250 * knows. In earlier versions of the PIC patches, the
7251 * pcrel_adjust field was used to store the correction, but
7252 * since the expression is not pcrel, I felt it would be
7253 * confusing to do it this way. */
7254
7255 if ((reloc_type == BFD_RELOC_32
7256 || reloc_type == BFD_RELOC_X86_64_32S
7257 || reloc_type == BFD_RELOC_64)
7258 && GOT_symbol
7259 && GOT_symbol == i.op[n].imms->X_add_symbol
7260 && (i.op[n].imms->X_op == O_symbol
7261 || (i.op[n].imms->X_op == O_add
7262 && ((symbol_get_value_expression
7263 (i.op[n].imms->X_op_symbol)->X_op)
7264 == O_subtract))))
7265 {
7266 offsetT add;
7267
7268 if (insn_start_frag == frag_now)
7269 add = (p - frag_now->fr_literal) - insn_start_off;
7270 else
7271 {
7272 fragS *fr;
7273
7274 add = insn_start_frag->fr_fix - insn_start_off;
7275 for (fr = insn_start_frag->fr_next;
7276 fr && fr != frag_now; fr = fr->fr_next)
7277 add += fr->fr_fix;
7278 add += p - frag_now->fr_literal;
7279 }
7280
7281 if (!object_64bit)
7282 reloc_type = BFD_RELOC_386_GOTPC;
7283 else if (size == 4)
7284 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7285 else if (size == 8)
7286 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7287 i.op[n].imms->X_add_number += add;
7288 }
7289 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7290 i.op[n].imms, 0, reloc_type);
7291 }
7292 }
7293 }
7294}
7295\f
7296/* x86_cons_fix_new is called via the expression parsing code when a
7297 reloc is needed. We use this hook to get the correct .got reloc. */
7298static enum bfd_reloc_code_real got_reloc = NO_RELOC;
7299static int cons_sign = -1;
7300
7301void
7302x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
7303 expressionS *exp)
7304{
7305 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
7306
7307 got_reloc = NO_RELOC;
7308
7309#ifdef TE_PE
7310 if (exp->X_op == O_secrel)
7311 {
7312 exp->X_op = O_symbol;
7313 r = BFD_RELOC_32_SECREL;
7314 }
7315#endif
7316
7317 fix_new_exp (frag, off, len, exp, 0, r);
7318}
7319
7320/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7321 purpose of the `.dc.a' internal pseudo-op. */
7322
7323int
7324x86_address_bytes (void)
7325{
7326 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7327 return 4;
7328 return stdoutput->arch_info->bits_per_address / 8;
7329}
7330
7331#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7332 || defined (LEX_AT)
7333# define lex_got(reloc, adjust, types) NULL
7334#else
7335/* Parse operands of the form
7336 <symbol>@GOTOFF+<nnn>
7337 and similar .plt or .got references.
7338
7339 If we find one, set up the correct relocation in RELOC and copy the
7340 input string, minus the `@GOTOFF' into a malloc'd buffer for
7341 parsing by the calling routine. Return this buffer, and if ADJUST
7342 is non-null set it to the length of the string we removed from the
7343 input line. Otherwise return NULL. */
7344static char *
7345lex_got (enum bfd_reloc_code_real *rel,
7346 int *adjust,
7347 i386_operand_type *types)
7348{
7349 /* Some of the relocations depend on the size of what field is to
7350 be relocated. But in our callers i386_immediate and i386_displacement
7351 we don't yet know the operand size (this will be set by insn
7352 matching). Hence we record the word32 relocation here,
7353 and adjust the reloc according to the real size in reloc(). */
7354 static const struct {
7355 const char *str;
7356 int len;
7357 const enum bfd_reloc_code_real rel[2];
7358 const i386_operand_type types64;
7359 } gotrel[] = {
7360#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7361 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7362 BFD_RELOC_SIZE32 },
7363 OPERAND_TYPE_IMM32_64 },
7364#endif
7365 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7366 BFD_RELOC_X86_64_PLTOFF64 },
7367 OPERAND_TYPE_IMM64 },
7368 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7369 BFD_RELOC_X86_64_PLT32 },
7370 OPERAND_TYPE_IMM32_32S_DISP32 },
7371 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7372 BFD_RELOC_X86_64_GOTPLT64 },
7373 OPERAND_TYPE_IMM64_DISP64 },
7374 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7375 BFD_RELOC_X86_64_GOTOFF64 },
7376 OPERAND_TYPE_IMM64_DISP64 },
7377 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7378 BFD_RELOC_X86_64_GOTPCREL },
7379 OPERAND_TYPE_IMM32_32S_DISP32 },
7380 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7381 BFD_RELOC_X86_64_TLSGD },
7382 OPERAND_TYPE_IMM32_32S_DISP32 },
7383 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7384 _dummy_first_bfd_reloc_code_real },
7385 OPERAND_TYPE_NONE },
7386 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7387 BFD_RELOC_X86_64_TLSLD },
7388 OPERAND_TYPE_IMM32_32S_DISP32 },
7389 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7390 BFD_RELOC_X86_64_GOTTPOFF },
7391 OPERAND_TYPE_IMM32_32S_DISP32 },
7392 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7393 BFD_RELOC_X86_64_TPOFF32 },
7394 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7395 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7396 _dummy_first_bfd_reloc_code_real },
7397 OPERAND_TYPE_NONE },
7398 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7399 BFD_RELOC_X86_64_DTPOFF32 },
7400 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7401 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7402 _dummy_first_bfd_reloc_code_real },
7403 OPERAND_TYPE_NONE },
7404 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7405 _dummy_first_bfd_reloc_code_real },
7406 OPERAND_TYPE_NONE },
7407 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7408 BFD_RELOC_X86_64_GOT32 },
7409 OPERAND_TYPE_IMM32_32S_64_DISP32 },
7410 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7411 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
7412 OPERAND_TYPE_IMM32_32S_DISP32 },
7413 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7414 BFD_RELOC_X86_64_TLSDESC_CALL },
7415 OPERAND_TYPE_IMM32_32S_DISP32 },
7416 };
7417 char *cp;
7418 unsigned int j;
7419
7420#if defined (OBJ_MAYBE_ELF)
7421 if (!IS_ELF)
7422 return NULL;
7423#endif
7424
7425 for (cp = input_line_pointer; *cp != '@'; cp++)
7426 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7427 return NULL;
7428
7429 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7430 {
7431 int len = gotrel[j].len;
7432 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7433 {
7434 if (gotrel[j].rel[object_64bit] != 0)
7435 {
7436 int first, second;
7437 char *tmpbuf, *past_reloc;
7438
7439 *rel = gotrel[j].rel[object_64bit];
7440
7441 if (types)
7442 {
7443 if (flag_code != CODE_64BIT)
7444 {
7445 types->bitfield.imm32 = 1;
7446 types->bitfield.disp32 = 1;
7447 }
7448 else
7449 *types = gotrel[j].types64;
7450 }
7451
7452 if (j != 0 && GOT_symbol == NULL)
7453 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7454
7455 /* The length of the first part of our input line. */
7456 first = cp - input_line_pointer;
7457
7458 /* The second part goes from after the reloc token until
7459 (and including) an end_of_line char or comma. */
7460 past_reloc = cp + 1 + len;
7461 cp = past_reloc;
7462 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7463 ++cp;
7464 second = cp + 1 - past_reloc;
7465
7466 /* Allocate and copy string. The trailing NUL shouldn't
7467 be necessary, but be safe. */
7468 tmpbuf = (char *) xmalloc (first + second + 2);
7469 memcpy (tmpbuf, input_line_pointer, first);
7470 if (second != 0 && *past_reloc != ' ')
7471 /* Replace the relocation token with ' ', so that
7472 errors like foo@GOTOFF1 will be detected. */
7473 tmpbuf[first++] = ' ';
7474 else
7475 /* Increment length by 1 if the relocation token is
7476 removed. */
7477 len++;
7478 if (adjust)
7479 *adjust = len;
7480 memcpy (tmpbuf + first, past_reloc, second);
7481 tmpbuf[first + second] = '\0';
7482 return tmpbuf;
7483 }
7484
7485 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7486 gotrel[j].str, 1 << (5 + object_64bit));
7487 return NULL;
7488 }
7489 }
7490
7491 /* Might be a symbol version string. Don't as_bad here. */
7492 return NULL;
7493}
7494#endif
7495
7496#ifdef TE_PE
7497#ifdef lex_got
7498#undef lex_got
7499#endif
7500/* Parse operands of the form
7501 <symbol>@SECREL32+<nnn>
7502
7503 If we find one, set up the correct relocation in RELOC and copy the
7504 input string, minus the `@SECREL32' into a malloc'd buffer for
7505 parsing by the calling routine. Return this buffer, and if ADJUST
7506 is non-null set it to the length of the string we removed from the
7507 input line. Otherwise return NULL.
7508
7509 This function is copied from the ELF version above adjusted for PE targets. */
7510
7511static char *
7512lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7513 int *adjust ATTRIBUTE_UNUSED,
7514 i386_operand_type *types ATTRIBUTE_UNUSED)
7515{
7516 static const struct
7517 {
7518 const char *str;
7519 int len;
7520 const enum bfd_reloc_code_real rel[2];
7521 const i386_operand_type types64;
7522 }
7523 gotrel[] =
7524 {
7525 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7526 BFD_RELOC_32_SECREL },
7527 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7528 };
7529
7530 char *cp;
7531 unsigned j;
7532
7533 for (cp = input_line_pointer; *cp != '@'; cp++)
7534 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7535 return NULL;
7536
7537 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7538 {
7539 int len = gotrel[j].len;
7540
7541 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7542 {
7543 if (gotrel[j].rel[object_64bit] != 0)
7544 {
7545 int first, second;
7546 char *tmpbuf, *past_reloc;
7547
7548 *rel = gotrel[j].rel[object_64bit];
7549 if (adjust)
7550 *adjust = len;
7551
7552 if (types)
7553 {
7554 if (flag_code != CODE_64BIT)
7555 {
7556 types->bitfield.imm32 = 1;
7557 types->bitfield.disp32 = 1;
7558 }
7559 else
7560 *types = gotrel[j].types64;
7561 }
7562
7563 /* The length of the first part of our input line. */
7564 first = cp - input_line_pointer;
7565
7566 /* The second part goes from after the reloc token until
7567 (and including) an end_of_line char or comma. */
7568 past_reloc = cp + 1 + len;
7569 cp = past_reloc;
7570 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7571 ++cp;
7572 second = cp + 1 - past_reloc;
7573
7574 /* Allocate and copy string. The trailing NUL shouldn't
7575 be necessary, but be safe. */
7576 tmpbuf = (char *) xmalloc (first + second + 2);
7577 memcpy (tmpbuf, input_line_pointer, first);
7578 if (second != 0 && *past_reloc != ' ')
7579 /* Replace the relocation token with ' ', so that
7580 errors like foo@SECLREL321 will be detected. */
7581 tmpbuf[first++] = ' ';
7582 memcpy (tmpbuf + first, past_reloc, second);
7583 tmpbuf[first + second] = '\0';
7584 return tmpbuf;
7585 }
7586
7587 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7588 gotrel[j].str, 1 << (5 + object_64bit));
7589 return NULL;
7590 }
7591 }
7592
7593 /* Might be a symbol version string. Don't as_bad here. */
7594 return NULL;
7595}
7596
7597#endif /* TE_PE */
7598
7599void
7600x86_cons (expressionS *exp, int size)
7601{
7602 intel_syntax = -intel_syntax;
7603
7604 exp->X_md = 0;
7605 if (size == 4 || (object_64bit && size == 8))
7606 {
7607 /* Handle @GOTOFF and the like in an expression. */
7608 char *save;
7609 char *gotfree_input_line;
7610 int adjust = 0;
7611
7612 save = input_line_pointer;
7613 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
7614 if (gotfree_input_line)
7615 input_line_pointer = gotfree_input_line;
7616
7617 expression (exp);
7618
7619 if (gotfree_input_line)
7620 {
7621 /* expression () has merrily parsed up to the end of line,
7622 or a comma - in the wrong buffer. Transfer how far
7623 input_line_pointer has moved to the right buffer. */
7624 input_line_pointer = (save
7625 + (input_line_pointer - gotfree_input_line)
7626 + adjust);
7627 free (gotfree_input_line);
7628 if (exp->X_op == O_constant
7629 || exp->X_op == O_absent
7630 || exp->X_op == O_illegal
7631 || exp->X_op == O_register
7632 || exp->X_op == O_big)
7633 {
7634 char c = *input_line_pointer;
7635 *input_line_pointer = 0;
7636 as_bad (_("missing or invalid expression `%s'"), save);
7637 *input_line_pointer = c;
7638 }
7639 }
7640 }
7641 else
7642 expression (exp);
7643
7644 intel_syntax = -intel_syntax;
7645
7646 if (intel_syntax)
7647 i386_intel_simplify (exp);
7648}
7649
7650static void
7651signed_cons (int size)
7652{
7653 if (flag_code == CODE_64BIT)
7654 cons_sign = 1;
7655 cons (size);
7656 cons_sign = -1;
7657}
7658
7659#ifdef TE_PE
7660static void
7661pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
7662{
7663 expressionS exp;
7664
7665 do
7666 {
7667 expression (&exp);
7668 if (exp.X_op == O_symbol)
7669 exp.X_op = O_secrel;
7670
7671 emit_expr (&exp, 4);
7672 }
7673 while (*input_line_pointer++ == ',');
7674
7675 input_line_pointer--;
7676 demand_empty_rest_of_line ();
7677}
7678#endif
7679
7680/* Handle Vector operations. */
7681
7682static char *
7683check_VecOperations (char *op_string, char *op_end)
7684{
7685 const reg_entry *mask;
7686 const char *saved;
7687 char *end_op;
7688
7689 while (*op_string
7690 && (op_end == NULL || op_string < op_end))
7691 {
7692 saved = op_string;
7693 if (*op_string == '{')
7694 {
7695 op_string++;
7696
7697 /* Check broadcasts. */
7698 if (strncmp (op_string, "1to", 3) == 0)
7699 {
7700 int bcst_type;
7701
7702 if (i.broadcast)
7703 goto duplicated_vec_op;
7704
7705 op_string += 3;
7706 if (*op_string == '8')
7707 bcst_type = BROADCAST_1TO8;
7708 else if (*op_string == '1'
7709 && *(op_string+1) == '6')
7710 {
7711 bcst_type = BROADCAST_1TO16;
7712 op_string++;
7713 }
7714 else
7715 {
7716 as_bad (_("Unsupported broadcast: `%s'"), saved);
7717 return NULL;
7718 }
7719 op_string++;
7720
7721 broadcast_op.type = bcst_type;
7722 broadcast_op.operand = this_operand;
7723 i.broadcast = &broadcast_op;
7724 }
7725 /* Check masking operation. */
7726 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7727 {
7728 /* k0 can't be used for write mask. */
7729 if (mask->reg_num == 0)
7730 {
7731 as_bad (_("`%s' can't be used for write mask"),
7732 op_string);
7733 return NULL;
7734 }
7735
7736 if (!i.mask)
7737 {
7738 mask_op.mask = mask;
7739 mask_op.zeroing = 0;
7740 mask_op.operand = this_operand;
7741 i.mask = &mask_op;
7742 }
7743 else
7744 {
7745 if (i.mask->mask)
7746 goto duplicated_vec_op;
7747
7748 i.mask->mask = mask;
7749
7750 /* Only "{z}" is allowed here. No need to check
7751 zeroing mask explicitly. */
7752 if (i.mask->operand != this_operand)
7753 {
7754 as_bad (_("invalid write mask `%s'"), saved);
7755 return NULL;
7756 }
7757 }
7758
7759 op_string = end_op;
7760 }
7761 /* Check zeroing-flag for masking operation. */
7762 else if (*op_string == 'z')
7763 {
7764 if (!i.mask)
7765 {
7766 mask_op.mask = NULL;
7767 mask_op.zeroing = 1;
7768 mask_op.operand = this_operand;
7769 i.mask = &mask_op;
7770 }
7771 else
7772 {
7773 if (i.mask->zeroing)
7774 {
7775 duplicated_vec_op:
7776 as_bad (_("duplicated `%s'"), saved);
7777 return NULL;
7778 }
7779
7780 i.mask->zeroing = 1;
7781
7782 /* Only "{%k}" is allowed here. No need to check mask
7783 register explicitly. */
7784 if (i.mask->operand != this_operand)
7785 {
7786 as_bad (_("invalid zeroing-masking `%s'"),
7787 saved);
7788 return NULL;
7789 }
7790 }
7791
7792 op_string++;
7793 }
7794 else
7795 goto unknown_vec_op;
7796
7797 if (*op_string != '}')
7798 {
7799 as_bad (_("missing `}' in `%s'"), saved);
7800 return NULL;
7801 }
7802 op_string++;
7803 continue;
7804 }
7805 unknown_vec_op:
7806 /* We don't know this one. */
7807 as_bad (_("unknown vector operation: `%s'"), saved);
7808 return NULL;
7809 }
7810
7811 return op_string;
7812}
7813
7814static int
7815i386_immediate (char *imm_start)
7816{
7817 char *save_input_line_pointer;
7818 char *gotfree_input_line;
7819 segT exp_seg = 0;
7820 expressionS *exp;
7821 i386_operand_type types;
7822
7823 operand_type_set (&types, ~0);
7824
7825 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7826 {
7827 as_bad (_("at most %d immediate operands are allowed"),
7828 MAX_IMMEDIATE_OPERANDS);
7829 return 0;
7830 }
7831
7832 exp = &im_expressions[i.imm_operands++];
7833 i.op[this_operand].imms = exp;
7834
7835 if (is_space_char (*imm_start))
7836 ++imm_start;
7837
7838 save_input_line_pointer = input_line_pointer;
7839 input_line_pointer = imm_start;
7840
7841 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
7842 if (gotfree_input_line)
7843 input_line_pointer = gotfree_input_line;
7844
7845 exp_seg = expression (exp);
7846
7847 SKIP_WHITESPACE ();
7848
7849 /* Handle vector operations. */
7850 if (*input_line_pointer == '{')
7851 {
7852 input_line_pointer = check_VecOperations (input_line_pointer,
7853 NULL);
7854 if (input_line_pointer == NULL)
7855 return 0;
7856 }
7857
7858 if (*input_line_pointer)
7859 as_bad (_("junk `%s' after expression"), input_line_pointer);
7860
7861 input_line_pointer = save_input_line_pointer;
7862 if (gotfree_input_line)
7863 {
7864 free (gotfree_input_line);
7865
7866 if (exp->X_op == O_constant || exp->X_op == O_register)
7867 exp->X_op = O_illegal;
7868 }
7869
7870 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7871}
7872
7873static int
7874i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7875 i386_operand_type types, const char *imm_start)
7876{
7877 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
7878 {
7879 if (imm_start)
7880 as_bad (_("missing or invalid immediate expression `%s'"),
7881 imm_start);
7882 return 0;
7883 }
7884 else if (exp->X_op == O_constant)
7885 {
7886 /* Size it properly later. */
7887 i.types[this_operand].bitfield.imm64 = 1;
7888 /* If not 64bit, sign extend val. */
7889 if (flag_code != CODE_64BIT
7890 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7891 exp->X_add_number
7892 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
7893 }
7894#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7895 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
7896 && exp_seg != absolute_section
7897 && exp_seg != text_section
7898 && exp_seg != data_section
7899 && exp_seg != bss_section
7900 && exp_seg != undefined_section
7901 && !bfd_is_com_section (exp_seg))
7902 {
7903 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
7904 return 0;
7905 }
7906#endif
7907 else if (!intel_syntax && exp->X_op == O_register)
7908 {
7909 if (imm_start)
7910 as_bad (_("illegal immediate register operand %s"), imm_start);
7911 return 0;
7912 }
7913 else
7914 {
7915 /* This is an address. The size of the address will be
7916 determined later, depending on destination register,
7917 suffix, or the default for the section. */
7918 i.types[this_operand].bitfield.imm8 = 1;
7919 i.types[this_operand].bitfield.imm16 = 1;
7920 i.types[this_operand].bitfield.imm32 = 1;
7921 i.types[this_operand].bitfield.imm32s = 1;
7922 i.types[this_operand].bitfield.imm64 = 1;
7923 i.types[this_operand] = operand_type_and (i.types[this_operand],
7924 types);
7925 }
7926
7927 return 1;
7928}
7929
7930static char *
7931i386_scale (char *scale)
7932{
7933 offsetT val;
7934 char *save = input_line_pointer;
7935
7936 input_line_pointer = scale;
7937 val = get_absolute_expression ();
7938
7939 switch (val)
7940 {
7941 case 1:
7942 i.log2_scale_factor = 0;
7943 break;
7944 case 2:
7945 i.log2_scale_factor = 1;
7946 break;
7947 case 4:
7948 i.log2_scale_factor = 2;
7949 break;
7950 case 8:
7951 i.log2_scale_factor = 3;
7952 break;
7953 default:
7954 {
7955 char sep = *input_line_pointer;
7956
7957 *input_line_pointer = '\0';
7958 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7959 scale);
7960 *input_line_pointer = sep;
7961 input_line_pointer = save;
7962 return NULL;
7963 }
7964 }
7965 if (i.log2_scale_factor != 0 && i.index_reg == 0)
7966 {
7967 as_warn (_("scale factor of %d without an index register"),
7968 1 << i.log2_scale_factor);
7969 i.log2_scale_factor = 0;
7970 }
7971 scale = input_line_pointer;
7972 input_line_pointer = save;
7973 return scale;
7974}
7975
7976static int
7977i386_displacement (char *disp_start, char *disp_end)
7978{
7979 expressionS *exp;
7980 segT exp_seg = 0;
7981 char *save_input_line_pointer;
7982 char *gotfree_input_line;
7983 int override;
7984 i386_operand_type bigdisp, types = anydisp;
7985 int ret;
7986
7987 if (i.disp_operands == MAX_MEMORY_OPERANDS)
7988 {
7989 as_bad (_("at most %d displacement operands are allowed"),
7990 MAX_MEMORY_OPERANDS);
7991 return 0;
7992 }
7993
7994 operand_type_set (&bigdisp, 0);
7995 if ((i.types[this_operand].bitfield.jumpabsolute)
7996 || (!current_templates->start->opcode_modifier.jump
7997 && !current_templates->start->opcode_modifier.jumpdword))
7998 {
7999 bigdisp.bitfield.disp32 = 1;
8000 override = (i.prefix[ADDR_PREFIX] != 0);
8001 if (flag_code == CODE_64BIT)
8002 {
8003 if (!override)
8004 {
8005 bigdisp.bitfield.disp32s = 1;
8006 bigdisp.bitfield.disp64 = 1;
8007 }
8008 }
8009 else if ((flag_code == CODE_16BIT) ^ override)
8010 {
8011 bigdisp.bitfield.disp32 = 0;
8012 bigdisp.bitfield.disp16 = 1;
8013 }
8014 }
8015 else
8016 {
8017 /* For PC-relative branches, the width of the displacement
8018 is dependent upon data size, not address size. */
8019 override = (i.prefix[DATA_PREFIX] != 0);
8020 if (flag_code == CODE_64BIT)
8021 {
8022 if (override || i.suffix == WORD_MNEM_SUFFIX)
8023 bigdisp.bitfield.disp16 = 1;
8024 else
8025 {
8026 bigdisp.bitfield.disp32 = 1;
8027 bigdisp.bitfield.disp32s = 1;
8028 }
8029 }
8030 else
8031 {
8032 if (!override)
8033 override = (i.suffix == (flag_code != CODE_16BIT
8034 ? WORD_MNEM_SUFFIX
8035 : LONG_MNEM_SUFFIX));
8036 bigdisp.bitfield.disp32 = 1;
8037 if ((flag_code == CODE_16BIT) ^ override)
8038 {
8039 bigdisp.bitfield.disp32 = 0;
8040 bigdisp.bitfield.disp16 = 1;
8041 }
8042 }
8043 }
8044 i.types[this_operand] = operand_type_or (i.types[this_operand],
8045 bigdisp);
8046
8047 exp = &disp_expressions[i.disp_operands];
8048 i.op[this_operand].disps = exp;
8049 i.disp_operands++;
8050 save_input_line_pointer = input_line_pointer;
8051 input_line_pointer = disp_start;
8052 END_STRING_AND_SAVE (disp_end);
8053
8054#ifndef GCC_ASM_O_HACK
8055#define GCC_ASM_O_HACK 0
8056#endif
8057#if GCC_ASM_O_HACK
8058 END_STRING_AND_SAVE (disp_end + 1);
8059 if (i.types[this_operand].bitfield.baseIndex
8060 && displacement_string_end[-1] == '+')
8061 {
8062 /* This hack is to avoid a warning when using the "o"
8063 constraint within gcc asm statements.
8064 For instance:
8065
8066 #define _set_tssldt_desc(n,addr,limit,type) \
8067 __asm__ __volatile__ ( \
8068 "movw %w2,%0\n\t" \
8069 "movw %w1,2+%0\n\t" \
8070 "rorl $16,%1\n\t" \
8071 "movb %b1,4+%0\n\t" \
8072 "movb %4,5+%0\n\t" \
8073 "movb $0,6+%0\n\t" \
8074 "movb %h1,7+%0\n\t" \
8075 "rorl $16,%1" \
8076 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8077
8078 This works great except that the output assembler ends
8079 up looking a bit weird if it turns out that there is
8080 no offset. You end up producing code that looks like:
8081
8082 #APP
8083 movw $235,(%eax)
8084 movw %dx,2+(%eax)
8085 rorl $16,%edx
8086 movb %dl,4+(%eax)
8087 movb $137,5+(%eax)
8088 movb $0,6+(%eax)
8089 movb %dh,7+(%eax)
8090 rorl $16,%edx
8091 #NO_APP
8092
8093 So here we provide the missing zero. */
8094
8095 *displacement_string_end = '0';
8096 }
8097#endif
8098 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8099 if (gotfree_input_line)
8100 input_line_pointer = gotfree_input_line;
8101
8102 exp_seg = expression (exp);
8103
8104 SKIP_WHITESPACE ();
8105 if (*input_line_pointer)
8106 as_bad (_("junk `%s' after expression"), input_line_pointer);
8107#if GCC_ASM_O_HACK
8108 RESTORE_END_STRING (disp_end + 1);
8109#endif
8110 input_line_pointer = save_input_line_pointer;
8111 if (gotfree_input_line)
8112 {
8113 free (gotfree_input_line);
8114
8115 if (exp->X_op == O_constant || exp->X_op == O_register)
8116 exp->X_op = O_illegal;
8117 }
8118
8119 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8120
8121 RESTORE_END_STRING (disp_end);
8122
8123 return ret;
8124}
8125
8126static int
8127i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8128 i386_operand_type types, const char *disp_start)
8129{
8130 i386_operand_type bigdisp;
8131 int ret = 1;
8132
8133 /* We do this to make sure that the section symbol is in
8134 the symbol table. We will ultimately change the relocation
8135 to be relative to the beginning of the section. */
8136 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8137 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8138 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8139 {
8140 if (exp->X_op != O_symbol)
8141 goto inv_disp;
8142
8143 if (S_IS_LOCAL (exp->X_add_symbol)
8144 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8145 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8146 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8147 exp->X_op = O_subtract;
8148 exp->X_op_symbol = GOT_symbol;
8149 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8150 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8151 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8152 i.reloc[this_operand] = BFD_RELOC_64;
8153 else
8154 i.reloc[this_operand] = BFD_RELOC_32;
8155 }
8156
8157 else if (exp->X_op == O_absent
8158 || exp->X_op == O_illegal
8159 || exp->X_op == O_big)
8160 {
8161 inv_disp:
8162 as_bad (_("missing or invalid displacement expression `%s'"),
8163 disp_start);
8164 ret = 0;
8165 }
8166
8167 else if (flag_code == CODE_64BIT
8168 && !i.prefix[ADDR_PREFIX]
8169 && exp->X_op == O_constant)
8170 {
8171 /* Since displacement is signed extended to 64bit, don't allow
8172 disp32 and turn off disp32s if they are out of range. */
8173 i.types[this_operand].bitfield.disp32 = 0;
8174 if (!fits_in_signed_long (exp->X_add_number))
8175 {
8176 i.types[this_operand].bitfield.disp32s = 0;
8177 if (i.types[this_operand].bitfield.baseindex)
8178 {
8179 as_bad (_("0x%lx out range of signed 32bit displacement"),
8180 (long) exp->X_add_number);
8181 ret = 0;
8182 }
8183 }
8184 }
8185
8186#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8187 else if (exp->X_op != O_constant
8188 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8189 && exp_seg != absolute_section
8190 && exp_seg != text_section
8191 && exp_seg != data_section
8192 && exp_seg != bss_section
8193 && exp_seg != undefined_section
8194 && !bfd_is_com_section (exp_seg))
8195 {
8196 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8197 ret = 0;
8198 }
8199#endif
8200
8201 /* Check if this is a displacement only operand. */
8202 bigdisp = i.types[this_operand];
8203 bigdisp.bitfield.disp8 = 0;
8204 bigdisp.bitfield.disp16 = 0;
8205 bigdisp.bitfield.disp32 = 0;
8206 bigdisp.bitfield.disp32s = 0;
8207 bigdisp.bitfield.disp64 = 0;
8208 if (operand_type_all_zero (&bigdisp))
8209 i.types[this_operand] = operand_type_and (i.types[this_operand],
8210 types);
8211
8212 return ret;
8213}
8214
8215/* Make sure the memory operand we've been dealt is valid.
8216 Return 1 on success, 0 on a failure. */
8217
8218static int
8219i386_index_check (const char *operand_string)
8220{
8221 const char *kind = "base/index";
8222 enum flag_code addr_mode;
8223
8224 if (i.prefix[ADDR_PREFIX])
8225 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8226 else
8227 {
8228 addr_mode = flag_code;
8229
8230#if INFER_ADDR_PREFIX
8231 if (i.mem_operands == 0)
8232 {
8233 /* Infer address prefix from the first memory operand. */
8234 const reg_entry *addr_reg = i.base_reg;
8235
8236 if (addr_reg == NULL)
8237 addr_reg = i.index_reg;
8238
8239 if (addr_reg)
8240 {
8241 if (addr_reg->reg_num == RegEip
8242 || addr_reg->reg_num == RegEiz
8243 || addr_reg->reg_type.bitfield.reg32)
8244 addr_mode = CODE_32BIT;
8245 else if (flag_code != CODE_64BIT
8246 && addr_reg->reg_type.bitfield.reg16)
8247 addr_mode = CODE_16BIT;
8248
8249 if (addr_mode != flag_code)
8250 {
8251 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8252 i.prefixes += 1;
8253 /* Change the size of any displacement too. At most one
8254 of Disp16 or Disp32 is set.
8255 FIXME. There doesn't seem to be any real need for
8256 separate Disp16 and Disp32 flags. The same goes for
8257 Imm16 and Imm32. Removing them would probably clean
8258 up the code quite a lot. */
8259 if (flag_code != CODE_64BIT
8260 && (i.types[this_operand].bitfield.disp16
8261 || i.types[this_operand].bitfield.disp32))
8262 i.types[this_operand]
8263 = operand_type_xor (i.types[this_operand], disp16_32);
8264 }
8265 }
8266 }
8267#endif
8268 }
8269
8270 if (current_templates->start->opcode_modifier.isstring
8271 && !current_templates->start->opcode_modifier.immext
8272 && (current_templates->end[-1].opcode_modifier.isstring
8273 || i.mem_operands))
8274 {
8275 /* Memory operands of string insns are special in that they only allow
8276 a single register (rDI, rSI, or rBX) as their memory address. */
8277 const reg_entry *expected_reg;
8278 static const char *di_si[][2] =
8279 {
8280 { "esi", "edi" },
8281 { "si", "di" },
8282 { "rsi", "rdi" }
8283 };
8284 static const char *bx[] = { "ebx", "bx", "rbx" };
8285
8286 kind = "string address";
8287
8288 if (current_templates->start->opcode_modifier.w)
8289 {
8290 i386_operand_type type = current_templates->end[-1].operand_types[0];
8291
8292 if (!type.bitfield.baseindex
8293 || ((!i.mem_operands != !intel_syntax)
8294 && current_templates->end[-1].operand_types[1]
8295 .bitfield.baseindex))
8296 type = current_templates->end[-1].operand_types[1];
8297 expected_reg = hash_find (reg_hash,
8298 di_si[addr_mode][type.bitfield.esseg]);
8299
8300 }
8301 else
8302 expected_reg = hash_find (reg_hash, bx[addr_mode]);
8303
8304 if (i.base_reg != expected_reg
8305 || i.index_reg
8306 || operand_type_check (i.types[this_operand], disp))
8307 {
8308 /* The second memory operand must have the same size as
8309 the first one. */
8310 if (i.mem_operands
8311 && i.base_reg
8312 && !((addr_mode == CODE_64BIT
8313 && i.base_reg->reg_type.bitfield.reg64)
8314 || (addr_mode == CODE_32BIT
8315 ? i.base_reg->reg_type.bitfield.reg32
8316 : i.base_reg->reg_type.bitfield.reg16)))
8317 goto bad_address;
8318
8319 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8320 operand_string,
8321 intel_syntax ? '[' : '(',
8322 register_prefix,
8323 expected_reg->reg_name,
8324 intel_syntax ? ']' : ')');
8325 return 1;
8326 }
8327 else
8328 return 1;
8329
8330bad_address:
8331 as_bad (_("`%s' is not a valid %s expression"),
8332 operand_string, kind);
8333 return 0;
8334 }
8335 else
8336 {
8337 if (addr_mode != CODE_16BIT)
8338 {
8339 /* 32-bit/64-bit checks. */
8340 if ((i.base_reg
8341 && (addr_mode == CODE_64BIT
8342 ? !i.base_reg->reg_type.bitfield.reg64
8343 : !i.base_reg->reg_type.bitfield.reg32)
8344 && (i.index_reg
8345 || (i.base_reg->reg_num
8346 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8347 || (i.index_reg
8348 && !i.index_reg->reg_type.bitfield.regxmm
8349 && !i.index_reg->reg_type.bitfield.regymm
8350 && !i.index_reg->reg_type.bitfield.regzmm
8351 && ((addr_mode == CODE_64BIT
8352 ? !(i.index_reg->reg_type.bitfield.reg64
8353 || i.index_reg->reg_num == RegRiz)
8354 : !(i.index_reg->reg_type.bitfield.reg32
8355 || i.index_reg->reg_num == RegEiz))
8356 || !i.index_reg->reg_type.bitfield.baseindex)))
8357 goto bad_address;
8358 }
8359 else
8360 {
8361 /* 16-bit checks. */
8362 if ((i.base_reg
8363 && (!i.base_reg->reg_type.bitfield.reg16
8364 || !i.base_reg->reg_type.bitfield.baseindex))
8365 || (i.index_reg
8366 && (!i.index_reg->reg_type.bitfield.reg16
8367 || !i.index_reg->reg_type.bitfield.baseindex
8368 || !(i.base_reg
8369 && i.base_reg->reg_num < 6
8370 && i.index_reg->reg_num >= 6
8371 && i.log2_scale_factor == 0))))
8372 goto bad_address;
8373 }
8374 }
8375 return 1;
8376}
8377
8378/* Handle vector immediates. */
8379
8380static int
8381RC_SAE_immediate (const char *imm_start)
8382{
8383 unsigned int match_found, j;
8384 const char *pstr = imm_start;
8385 expressionS *exp;
8386
8387 if (*pstr != '{')
8388 return 0;
8389
8390 pstr++;
8391 match_found = 0;
8392 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8393 {
8394 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8395 {
8396 if (!i.rounding)
8397 {
8398 rc_op.type = RC_NamesTable[j].type;
8399 rc_op.operand = this_operand;
8400 i.rounding = &rc_op;
8401 }
8402 else
8403 {
8404 as_bad (_("duplicated `%s'"), imm_start);
8405 return 0;
8406 }
8407 pstr += RC_NamesTable[j].len;
8408 match_found = 1;
8409 break;
8410 }
8411 }
8412 if (!match_found)
8413 return 0;
8414
8415 if (*pstr++ != '}')
8416 {
8417 as_bad (_("Missing '}': '%s'"), imm_start);
8418 return 0;
8419 }
8420 /* RC/SAE immediate string should contain nothing more. */;
8421 if (*pstr != 0)
8422 {
8423 as_bad (_("Junk after '}': '%s'"), imm_start);
8424 return 0;
8425 }
8426
8427 exp = &im_expressions[i.imm_operands++];
8428 i.op[this_operand].imms = exp;
8429
8430 exp->X_op = O_constant;
8431 exp->X_add_number = 0;
8432 exp->X_add_symbol = (symbolS *) 0;
8433 exp->X_op_symbol = (symbolS *) 0;
8434
8435 i.types[this_operand].bitfield.imm8 = 1;
8436 return 1;
8437}
8438
8439/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8440 on error. */
8441
8442static int
8443i386_att_operand (char *operand_string)
8444{
8445 const reg_entry *r;
8446 char *end_op;
8447 char *op_string = operand_string;
8448
8449 if (is_space_char (*op_string))
8450 ++op_string;
8451
8452 /* We check for an absolute prefix (differentiating,
8453 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8454 if (*op_string == ABSOLUTE_PREFIX)
8455 {
8456 ++op_string;
8457 if (is_space_char (*op_string))
8458 ++op_string;
8459 i.types[this_operand].bitfield.jumpabsolute = 1;
8460 }
8461
8462 /* Check if operand is a register. */
8463 if ((r = parse_register (op_string, &end_op)) != NULL)
8464 {
8465 i386_operand_type temp;
8466
8467 /* Check for a segment override by searching for ':' after a
8468 segment register. */
8469 op_string = end_op;
8470 if (is_space_char (*op_string))
8471 ++op_string;
8472 if (*op_string == ':'
8473 && (r->reg_type.bitfield.sreg2
8474 || r->reg_type.bitfield.sreg3))
8475 {
8476 switch (r->reg_num)
8477 {
8478 case 0:
8479 i.seg[i.mem_operands] = &es;
8480 break;
8481 case 1:
8482 i.seg[i.mem_operands] = &cs;
8483 break;
8484 case 2:
8485 i.seg[i.mem_operands] = &ss;
8486 break;
8487 case 3:
8488 i.seg[i.mem_operands] = &ds;
8489 break;
8490 case 4:
8491 i.seg[i.mem_operands] = &fs;
8492 break;
8493 case 5:
8494 i.seg[i.mem_operands] = &gs;
8495 break;
8496 }
8497
8498 /* Skip the ':' and whitespace. */
8499 ++op_string;
8500 if (is_space_char (*op_string))
8501 ++op_string;
8502
8503 if (!is_digit_char (*op_string)
8504 && !is_identifier_char (*op_string)
8505 && *op_string != '('
8506 && *op_string != ABSOLUTE_PREFIX)
8507 {
8508 as_bad (_("bad memory operand `%s'"), op_string);
8509 return 0;
8510 }
8511 /* Handle case of %es:*foo. */
8512 if (*op_string == ABSOLUTE_PREFIX)
8513 {
8514 ++op_string;
8515 if (is_space_char (*op_string))
8516 ++op_string;
8517 i.types[this_operand].bitfield.jumpabsolute = 1;
8518 }
8519 goto do_memory_reference;
8520 }
8521
8522 /* Handle vector operations. */
8523 if (*op_string == '{')
8524 {
8525 op_string = check_VecOperations (op_string, NULL);
8526 if (op_string == NULL)
8527 return 0;
8528 }
8529
8530 if (*op_string)
8531 {
8532 as_bad (_("junk `%s' after register"), op_string);
8533 return 0;
8534 }
8535 temp = r->reg_type;
8536 temp.bitfield.baseindex = 0;
8537 i.types[this_operand] = operand_type_or (i.types[this_operand],
8538 temp);
8539 i.types[this_operand].bitfield.unspecified = 0;
8540 i.op[this_operand].regs = r;
8541 i.reg_operands++;
8542 }
8543 else if (*op_string == REGISTER_PREFIX)
8544 {
8545 as_bad (_("bad register name `%s'"), op_string);
8546 return 0;
8547 }
8548 else if (*op_string == IMMEDIATE_PREFIX)
8549 {
8550 ++op_string;
8551 if (i.types[this_operand].bitfield.jumpabsolute)
8552 {
8553 as_bad (_("immediate operand illegal with absolute jump"));
8554 return 0;
8555 }
8556 if (!i386_immediate (op_string))
8557 return 0;
8558 }
8559 else if (RC_SAE_immediate (operand_string))
8560 {
8561 /* If it is a RC or SAE immediate, do nothing. */
8562 ;
8563 }
8564 else if (is_digit_char (*op_string)
8565 || is_identifier_char (*op_string)
8566 || *op_string == '(')
8567 {
8568 /* This is a memory reference of some sort. */
8569 char *base_string;
8570
8571 /* Start and end of displacement string expression (if found). */
8572 char *displacement_string_start;
8573 char *displacement_string_end;
8574 char *vop_start;
8575
8576 do_memory_reference:
8577 if ((i.mem_operands == 1
8578 && !current_templates->start->opcode_modifier.isstring)
8579 || i.mem_operands == 2)
8580 {
8581 as_bad (_("too many memory references for `%s'"),
8582 current_templates->start->name);
8583 return 0;
8584 }
8585
8586 /* Check for base index form. We detect the base index form by
8587 looking for an ')' at the end of the operand, searching
8588 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8589 after the '('. */
8590 base_string = op_string + strlen (op_string);
8591
8592 /* Handle vector operations. */
8593 vop_start = strchr (op_string, '{');
8594 if (vop_start && vop_start < base_string)
8595 {
8596 if (check_VecOperations (vop_start, base_string) == NULL)
8597 return 0;
8598 base_string = vop_start;
8599 }
8600
8601 --base_string;
8602 if (is_space_char (*base_string))
8603 --base_string;
8604
8605 /* If we only have a displacement, set-up for it to be parsed later. */
8606 displacement_string_start = op_string;
8607 displacement_string_end = base_string + 1;
8608
8609 if (*base_string == ')')
8610 {
8611 char *temp_string;
8612 unsigned int parens_balanced = 1;
8613 /* We've already checked that the number of left & right ()'s are
8614 equal, so this loop will not be infinite. */
8615 do
8616 {
8617 base_string--;
8618 if (*base_string == ')')
8619 parens_balanced++;
8620 if (*base_string == '(')
8621 parens_balanced--;
8622 }
8623 while (parens_balanced);
8624
8625 temp_string = base_string;
8626
8627 /* Skip past '(' and whitespace. */
8628 ++base_string;
8629 if (is_space_char (*base_string))
8630 ++base_string;
8631
8632 if (*base_string == ','
8633 || ((i.base_reg = parse_register (base_string, &end_op))
8634 != NULL))
8635 {
8636 displacement_string_end = temp_string;
8637
8638 i.types[this_operand].bitfield.baseindex = 1;
8639
8640 if (i.base_reg)
8641 {
8642 base_string = end_op;
8643 if (is_space_char (*base_string))
8644 ++base_string;
8645 }
8646
8647 /* There may be an index reg or scale factor here. */
8648 if (*base_string == ',')
8649 {
8650 ++base_string;
8651 if (is_space_char (*base_string))
8652 ++base_string;
8653
8654 if ((i.index_reg = parse_register (base_string, &end_op))
8655 != NULL)
8656 {
8657 base_string = end_op;
8658 if (is_space_char (*base_string))
8659 ++base_string;
8660 if (*base_string == ',')
8661 {
8662 ++base_string;
8663 if (is_space_char (*base_string))
8664 ++base_string;
8665 }
8666 else if (*base_string != ')')
8667 {
8668 as_bad (_("expecting `,' or `)' "
8669 "after index register in `%s'"),
8670 operand_string);
8671 return 0;
8672 }
8673 }
8674 else if (*base_string == REGISTER_PREFIX)
8675 {
8676 end_op = strchr (base_string, ',');
8677 if (end_op)
8678 *end_op = '\0';
8679 as_bad (_("bad register name `%s'"), base_string);
8680 return 0;
8681 }
8682
8683 /* Check for scale factor. */
8684 if (*base_string != ')')
8685 {
8686 char *end_scale = i386_scale (base_string);
8687
8688 if (!end_scale)
8689 return 0;
8690
8691 base_string = end_scale;
8692 if (is_space_char (*base_string))
8693 ++base_string;
8694 if (*base_string != ')')
8695 {
8696 as_bad (_("expecting `)' "
8697 "after scale factor in `%s'"),
8698 operand_string);
8699 return 0;
8700 }
8701 }
8702 else if (!i.index_reg)
8703 {
8704 as_bad (_("expecting index register or scale factor "
8705 "after `,'; got '%c'"),
8706 *base_string);
8707 return 0;
8708 }
8709 }
8710 else if (*base_string != ')')
8711 {
8712 as_bad (_("expecting `,' or `)' "
8713 "after base register in `%s'"),
8714 operand_string);
8715 return 0;
8716 }
8717 }
8718 else if (*base_string == REGISTER_PREFIX)
8719 {
8720 end_op = strchr (base_string, ',');
8721 if (end_op)
8722 *end_op = '\0';
8723 as_bad (_("bad register name `%s'"), base_string);
8724 return 0;
8725 }
8726 }
8727
8728 /* If there's an expression beginning the operand, parse it,
8729 assuming displacement_string_start and
8730 displacement_string_end are meaningful. */
8731 if (displacement_string_start != displacement_string_end)
8732 {
8733 if (!i386_displacement (displacement_string_start,
8734 displacement_string_end))
8735 return 0;
8736 }
8737
8738 /* Special case for (%dx) while doing input/output op. */
8739 if (i.base_reg
8740 && operand_type_equal (&i.base_reg->reg_type,
8741 &reg16_inoutportreg)
8742 && i.index_reg == 0
8743 && i.log2_scale_factor == 0
8744 && i.seg[i.mem_operands] == 0
8745 && !operand_type_check (i.types[this_operand], disp))
8746 {
8747 i.types[this_operand] = inoutportreg;
8748 return 1;
8749 }
8750
8751 if (i386_index_check (operand_string) == 0)
8752 return 0;
8753 i.types[this_operand].bitfield.mem = 1;
8754 i.mem_operands++;
8755 }
8756 else
8757 {
8758 /* It's not a memory operand; argh! */
8759 as_bad (_("invalid char %s beginning operand %d `%s'"),
8760 output_invalid (*op_string),
8761 this_operand + 1,
8762 op_string);
8763 return 0;
8764 }
8765 return 1; /* Normal return. */
8766}
8767\f
8768/* Calculate the maximum variable size (i.e., excluding fr_fix)
8769 that an rs_machine_dependent frag may reach. */
8770
8771unsigned int
8772i386_frag_max_var (fragS *frag)
8773{
8774 /* The only relaxable frags are for jumps.
8775 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8776 gas_assert (frag->fr_type == rs_machine_dependent);
8777 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8778}
8779
8780/* md_estimate_size_before_relax()
8781
8782 Called just before relax() for rs_machine_dependent frags. The x86
8783 assembler uses these frags to handle variable size jump
8784 instructions.
8785
8786 Any symbol that is now undefined will not become defined.
8787 Return the correct fr_subtype in the frag.
8788 Return the initial "guess for variable size of frag" to caller.
8789 The guess is actually the growth beyond the fixed part. Whatever
8790 we do to grow the fixed or variable part contributes to our
8791 returned value. */
8792
8793int
8794md_estimate_size_before_relax (fragS *fragP, segT segment)
8795{
8796 /* We've already got fragP->fr_subtype right; all we have to do is
8797 check for un-relaxable symbols. On an ELF system, we can't relax
8798 an externally visible symbol, because it may be overridden by a
8799 shared library. */
8800 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
8801#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8802 || (IS_ELF
8803 && (S_IS_EXTERNAL (fragP->fr_symbol)
8804 || S_IS_WEAK (fragP->fr_symbol)
8805 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
8806 & BSF_GNU_INDIRECT_FUNCTION))))
8807#endif
8808#if defined (OBJ_COFF) && defined (TE_PE)
8809 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
8810 && S_IS_WEAK (fragP->fr_symbol))
8811#endif
8812 )
8813 {
8814 /* Symbol is undefined in this segment, or we need to keep a
8815 reloc so that weak symbols can be overridden. */
8816 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
8817 enum bfd_reloc_code_real reloc_type;
8818 unsigned char *opcode;
8819 int old_fr_fix;
8820
8821 if (fragP->fr_var != NO_RELOC)
8822 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
8823 else if (size == 2)
8824 reloc_type = BFD_RELOC_16_PCREL;
8825 else
8826 reloc_type = BFD_RELOC_32_PCREL;
8827
8828 old_fr_fix = fragP->fr_fix;
8829 opcode = (unsigned char *) fragP->fr_opcode;
8830
8831 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
8832 {
8833 case UNCOND_JUMP:
8834 /* Make jmp (0xeb) a (d)word displacement jump. */
8835 opcode[0] = 0xe9;
8836 fragP->fr_fix += size;
8837 fix_new (fragP, old_fr_fix, size,
8838 fragP->fr_symbol,
8839 fragP->fr_offset, 1,
8840 reloc_type);
8841 break;
8842
8843 case COND_JUMP86:
8844 if (size == 2
8845 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
8846 {
8847 /* Negate the condition, and branch past an
8848 unconditional jump. */
8849 opcode[0] ^= 1;
8850 opcode[1] = 3;
8851 /* Insert an unconditional jump. */
8852 opcode[2] = 0xe9;
8853 /* We added two extra opcode bytes, and have a two byte
8854 offset. */
8855 fragP->fr_fix += 2 + 2;
8856 fix_new (fragP, old_fr_fix + 2, 2,
8857 fragP->fr_symbol,
8858 fragP->fr_offset, 1,
8859 reloc_type);
8860 break;
8861 }
8862 /* Fall through. */
8863
8864 case COND_JUMP:
8865 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8866 {
8867 fixS *fixP;
8868
8869 fragP->fr_fix += 1;
8870 fixP = fix_new (fragP, old_fr_fix, 1,
8871 fragP->fr_symbol,
8872 fragP->fr_offset, 1,
8873 BFD_RELOC_8_PCREL);
8874 fixP->fx_signed = 1;
8875 break;
8876 }
8877
8878 /* This changes the byte-displacement jump 0x7N
8879 to the (d)word-displacement jump 0x0f,0x8N. */
8880 opcode[1] = opcode[0] + 0x10;
8881 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8882 /* We've added an opcode byte. */
8883 fragP->fr_fix += 1 + size;
8884 fix_new (fragP, old_fr_fix + 1, size,
8885 fragP->fr_symbol,
8886 fragP->fr_offset, 1,
8887 reloc_type);
8888 break;
8889
8890 default:
8891 BAD_CASE (fragP->fr_subtype);
8892 break;
8893 }
8894 frag_wane (fragP);
8895 return fragP->fr_fix - old_fr_fix;
8896 }
8897
8898 /* Guess size depending on current relax state. Initially the relax
8899 state will correspond to a short jump and we return 1, because
8900 the variable part of the frag (the branch offset) is one byte
8901 long. However, we can relax a section more than once and in that
8902 case we must either set fr_subtype back to the unrelaxed state,
8903 or return the value for the appropriate branch. */
8904 return md_relax_table[fragP->fr_subtype].rlx_length;
8905}
8906
8907/* Called after relax() is finished.
8908
8909 In: Address of frag.
8910 fr_type == rs_machine_dependent.
8911 fr_subtype is what the address relaxed to.
8912
8913 Out: Any fixSs and constants are set up.
8914 Caller will turn frag into a ".space 0". */
8915
8916void
8917md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
8918 fragS *fragP)
8919{
8920 unsigned char *opcode;
8921 unsigned char *where_to_put_displacement = NULL;
8922 offsetT target_address;
8923 offsetT opcode_address;
8924 unsigned int extension = 0;
8925 offsetT displacement_from_opcode_start;
8926
8927 opcode = (unsigned char *) fragP->fr_opcode;
8928
8929 /* Address we want to reach in file space. */
8930 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
8931
8932 /* Address opcode resides at in file space. */
8933 opcode_address = fragP->fr_address + fragP->fr_fix;
8934
8935 /* Displacement from opcode start to fill into instruction. */
8936 displacement_from_opcode_start = target_address - opcode_address;
8937
8938 if ((fragP->fr_subtype & BIG) == 0)
8939 {
8940 /* Don't have to change opcode. */
8941 extension = 1; /* 1 opcode + 1 displacement */
8942 where_to_put_displacement = &opcode[1];
8943 }
8944 else
8945 {
8946 if (no_cond_jump_promotion
8947 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
8948 as_warn_where (fragP->fr_file, fragP->fr_line,
8949 _("long jump required"));
8950
8951 switch (fragP->fr_subtype)
8952 {
8953 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
8954 extension = 4; /* 1 opcode + 4 displacement */
8955 opcode[0] = 0xe9;
8956 where_to_put_displacement = &opcode[1];
8957 break;
8958
8959 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
8960 extension = 2; /* 1 opcode + 2 displacement */
8961 opcode[0] = 0xe9;
8962 where_to_put_displacement = &opcode[1];
8963 break;
8964
8965 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
8966 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
8967 extension = 5; /* 2 opcode + 4 displacement */
8968 opcode[1] = opcode[0] + 0x10;
8969 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8970 where_to_put_displacement = &opcode[2];
8971 break;
8972
8973 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
8974 extension = 3; /* 2 opcode + 2 displacement */
8975 opcode[1] = opcode[0] + 0x10;
8976 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8977 where_to_put_displacement = &opcode[2];
8978 break;
8979
8980 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
8981 extension = 4;
8982 opcode[0] ^= 1;
8983 opcode[1] = 3;
8984 opcode[2] = 0xe9;
8985 where_to_put_displacement = &opcode[3];
8986 break;
8987
8988 default:
8989 BAD_CASE (fragP->fr_subtype);
8990 break;
8991 }
8992 }
8993
8994 /* If size if less then four we are sure that the operand fits,
8995 but if it's 4, then it could be that the displacement is larger
8996 then -/+ 2GB. */
8997 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
8998 && object_64bit
8999 && ((addressT) (displacement_from_opcode_start - extension
9000 + ((addressT) 1 << 31))
9001 > (((addressT) 2 << 31) - 1)))
9002 {
9003 as_bad_where (fragP->fr_file, fragP->fr_line,
9004 _("jump target out of range"));
9005 /* Make us emit 0. */
9006 displacement_from_opcode_start = extension;
9007 }
9008 /* Now put displacement after opcode. */
9009 md_number_to_chars ((char *) where_to_put_displacement,
9010 (valueT) (displacement_from_opcode_start - extension),
9011 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9012 fragP->fr_fix += extension;
9013}
9014\f
9015/* Apply a fixup (fixP) to segment data, once it has been determined
9016 by our caller that we have all the info we need to fix it up.
9017
9018 Parameter valP is the pointer to the value of the bits.
9019
9020 On the 386, immediates, displacements, and data pointers are all in
9021 the same (little-endian) format, so we don't need to care about which
9022 we are handling. */
9023
9024void
9025md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9026{
9027 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9028 valueT value = *valP;
9029
9030#if !defined (TE_Mach)
9031 if (fixP->fx_pcrel)
9032 {
9033 switch (fixP->fx_r_type)
9034 {
9035 default:
9036 break;
9037
9038 case BFD_RELOC_64:
9039 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9040 break;
9041 case BFD_RELOC_32:
9042 case BFD_RELOC_X86_64_32S:
9043 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9044 break;
9045 case BFD_RELOC_16:
9046 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9047 break;
9048 case BFD_RELOC_8:
9049 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9050 break;
9051 }
9052 }
9053
9054 if (fixP->fx_addsy != NULL
9055 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9056 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9057 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9058 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9059 && !use_rela_relocations)
9060 {
9061 /* This is a hack. There should be a better way to handle this.
9062 This covers for the fact that bfd_install_relocation will
9063 subtract the current location (for partial_inplace, PC relative
9064 relocations); see more below. */
9065#ifndef OBJ_AOUT
9066 if (IS_ELF
9067#ifdef TE_PE
9068 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9069#endif
9070 )
9071 value += fixP->fx_where + fixP->fx_frag->fr_address;
9072#endif
9073#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9074 if (IS_ELF)
9075 {
9076 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9077
9078 if ((sym_seg == seg
9079 || (symbol_section_p (fixP->fx_addsy)
9080 && sym_seg != absolute_section))
9081 && !generic_force_reloc (fixP))
9082 {
9083 /* Yes, we add the values in twice. This is because
9084 bfd_install_relocation subtracts them out again. I think
9085 bfd_install_relocation is broken, but I don't dare change
9086 it. FIXME. */
9087 value += fixP->fx_where + fixP->fx_frag->fr_address;
9088 }
9089 }
9090#endif
9091#if defined (OBJ_COFF) && defined (TE_PE)
9092 /* For some reason, the PE format does not store a
9093 section address offset for a PC relative symbol. */
9094 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9095 || S_IS_WEAK (fixP->fx_addsy))
9096 value += md_pcrel_from (fixP);
9097#endif
9098 }
9099#if defined (OBJ_COFF) && defined (TE_PE)
9100 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9101 {
9102 value -= S_GET_VALUE (fixP->fx_addsy);
9103 }
9104#endif
9105
9106 /* Fix a few things - the dynamic linker expects certain values here,
9107 and we must not disappoint it. */
9108#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9109 if (IS_ELF && fixP->fx_addsy)
9110 switch (fixP->fx_r_type)
9111 {
9112 case BFD_RELOC_386_PLT32:
9113 case BFD_RELOC_X86_64_PLT32:
9114 /* Make the jump instruction point to the address of the operand. At
9115 runtime we merely add the offset to the actual PLT entry. */
9116 value = -4;
9117 break;
9118
9119 case BFD_RELOC_386_TLS_GD:
9120 case BFD_RELOC_386_TLS_LDM:
9121 case BFD_RELOC_386_TLS_IE_32:
9122 case BFD_RELOC_386_TLS_IE:
9123 case BFD_RELOC_386_TLS_GOTIE:
9124 case BFD_RELOC_386_TLS_GOTDESC:
9125 case BFD_RELOC_X86_64_TLSGD:
9126 case BFD_RELOC_X86_64_TLSLD:
9127 case BFD_RELOC_X86_64_GOTTPOFF:
9128 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9129 value = 0; /* Fully resolved at runtime. No addend. */
9130 /* Fallthrough */
9131 case BFD_RELOC_386_TLS_LE:
9132 case BFD_RELOC_386_TLS_LDO_32:
9133 case BFD_RELOC_386_TLS_LE_32:
9134 case BFD_RELOC_X86_64_DTPOFF32:
9135 case BFD_RELOC_X86_64_DTPOFF64:
9136 case BFD_RELOC_X86_64_TPOFF32:
9137 case BFD_RELOC_X86_64_TPOFF64:
9138 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9139 break;
9140
9141 case BFD_RELOC_386_TLS_DESC_CALL:
9142 case BFD_RELOC_X86_64_TLSDESC_CALL:
9143 value = 0; /* Fully resolved at runtime. No addend. */
9144 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9145 fixP->fx_done = 0;
9146 return;
9147
9148 case BFD_RELOC_386_GOT32:
9149 case BFD_RELOC_X86_64_GOT32:
9150 value = 0; /* Fully resolved at runtime. No addend. */
9151 break;
9152
9153 case BFD_RELOC_VTABLE_INHERIT:
9154 case BFD_RELOC_VTABLE_ENTRY:
9155 fixP->fx_done = 0;
9156 return;
9157
9158 default:
9159 break;
9160 }
9161#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9162 *valP = value;
9163#endif /* !defined (TE_Mach) */
9164
9165 /* Are we finished with this relocation now? */
9166 if (fixP->fx_addsy == NULL)
9167 fixP->fx_done = 1;
9168#if defined (OBJ_COFF) && defined (TE_PE)
9169 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9170 {
9171 fixP->fx_done = 0;
9172 /* Remember value for tc_gen_reloc. */
9173 fixP->fx_addnumber = value;
9174 /* Clear out the frag for now. */
9175 value = 0;
9176 }
9177#endif
9178 else if (use_rela_relocations)
9179 {
9180 fixP->fx_no_overflow = 1;
9181 /* Remember value for tc_gen_reloc. */
9182 fixP->fx_addnumber = value;
9183 value = 0;
9184 }
9185
9186 md_number_to_chars (p, value, fixP->fx_size);
9187}
9188\f
9189char *
9190md_atof (int type, char *litP, int *sizeP)
9191{
9192 /* This outputs the LITTLENUMs in REVERSE order;
9193 in accord with the bigendian 386. */
9194 return ieee_md_atof (type, litP, sizeP, FALSE);
9195}
9196\f
9197static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
9198
9199static char *
9200output_invalid (int c)
9201{
9202 if (ISPRINT (c))
9203 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9204 "'%c'", c);
9205 else
9206 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9207 "(0x%x)", (unsigned char) c);
9208 return output_invalid_buf;
9209}
9210
9211/* REG_STRING starts *before* REGISTER_PREFIX. */
9212
9213static const reg_entry *
9214parse_real_register (char *reg_string, char **end_op)
9215{
9216 char *s = reg_string;
9217 char *p;
9218 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9219 const reg_entry *r;
9220
9221 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9222 if (*s == REGISTER_PREFIX)
9223 ++s;
9224
9225 if (is_space_char (*s))
9226 ++s;
9227
9228 p = reg_name_given;
9229 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
9230 {
9231 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
9232 return (const reg_entry *) NULL;
9233 s++;
9234 }
9235
9236 /* For naked regs, make sure that we are not dealing with an identifier.
9237 This prevents confusing an identifier like `eax_var' with register
9238 `eax'. */
9239 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9240 return (const reg_entry *) NULL;
9241
9242 *end_op = s;
9243
9244 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9245
9246 /* Handle floating point regs, allowing spaces in the (i) part. */
9247 if (r == i386_regtab /* %st is first entry of table */)
9248 {
9249 if (is_space_char (*s))
9250 ++s;
9251 if (*s == '(')
9252 {
9253 ++s;
9254 if (is_space_char (*s))
9255 ++s;
9256 if (*s >= '0' && *s <= '7')
9257 {
9258 int fpr = *s - '0';
9259 ++s;
9260 if (is_space_char (*s))
9261 ++s;
9262 if (*s == ')')
9263 {
9264 *end_op = s + 1;
9265 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
9266 know (r);
9267 return r + fpr;
9268 }
9269 }
9270 /* We have "%st(" then garbage. */
9271 return (const reg_entry *) NULL;
9272 }
9273 }
9274
9275 if (r == NULL || allow_pseudo_reg)
9276 return r;
9277
9278 if (operand_type_all_zero (&r->reg_type))
9279 return (const reg_entry *) NULL;
9280
9281 if ((r->reg_type.bitfield.reg32
9282 || r->reg_type.bitfield.sreg3
9283 || r->reg_type.bitfield.control
9284 || r->reg_type.bitfield.debug
9285 || r->reg_type.bitfield.test)
9286 && !cpu_arch_flags.bitfield.cpui386)
9287 return (const reg_entry *) NULL;
9288
9289 if (r->reg_type.bitfield.floatreg
9290 && !cpu_arch_flags.bitfield.cpu8087
9291 && !cpu_arch_flags.bitfield.cpu287
9292 && !cpu_arch_flags.bitfield.cpu387)
9293 return (const reg_entry *) NULL;
9294
9295 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9296 return (const reg_entry *) NULL;
9297
9298 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9299 return (const reg_entry *) NULL;
9300
9301 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9302 return (const reg_entry *) NULL;
9303
9304 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9305 && !cpu_arch_flags.bitfield.cpuavx512f)
9306 return (const reg_entry *) NULL;
9307
9308 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9309 if (!allow_index_reg
9310 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9311 return (const reg_entry *) NULL;
9312
9313 /* Upper 16 vector register is only available with VREX in 64bit
9314 mode. */
9315 if ((r->reg_flags & RegVRex))
9316 {
9317 if (!cpu_arch_flags.bitfield.cpuvrex
9318 || flag_code != CODE_64BIT)
9319 return (const reg_entry *) NULL;
9320
9321 i.need_vrex = 1;
9322 }
9323
9324 if (((r->reg_flags & (RegRex64 | RegRex))
9325 || r->reg_type.bitfield.reg64)
9326 && (!cpu_arch_flags.bitfield.cpulm
9327 || !operand_type_equal (&r->reg_type, &control))
9328 && flag_code != CODE_64BIT)
9329 return (const reg_entry *) NULL;
9330
9331 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9332 return (const reg_entry *) NULL;
9333
9334 return r;
9335}
9336
9337/* REG_STRING starts *before* REGISTER_PREFIX. */
9338
9339static const reg_entry *
9340parse_register (char *reg_string, char **end_op)
9341{
9342 const reg_entry *r;
9343
9344 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9345 r = parse_real_register (reg_string, end_op);
9346 else
9347 r = NULL;
9348 if (!r)
9349 {
9350 char *save = input_line_pointer;
9351 char c;
9352 symbolS *symbolP;
9353
9354 input_line_pointer = reg_string;
9355 c = get_symbol_end ();
9356 symbolP = symbol_find (reg_string);
9357 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9358 {
9359 const expressionS *e = symbol_get_value_expression (symbolP);
9360
9361 know (e->X_op == O_register);
9362 know (e->X_add_number >= 0
9363 && (valueT) e->X_add_number < i386_regtab_size);
9364 r = i386_regtab + e->X_add_number;
9365 *end_op = input_line_pointer;
9366 }
9367 *input_line_pointer = c;
9368 input_line_pointer = save;
9369 }
9370 return r;
9371}
9372
9373int
9374i386_parse_name (char *name, expressionS *e, char *nextcharP)
9375{
9376 const reg_entry *r;
9377 char *end = input_line_pointer;
9378
9379 *end = *nextcharP;
9380 r = parse_register (name, &input_line_pointer);
9381 if (r && end <= input_line_pointer)
9382 {
9383 *nextcharP = *input_line_pointer;
9384 *input_line_pointer = 0;
9385 e->X_op = O_register;
9386 e->X_add_number = r - i386_regtab;
9387 return 1;
9388 }
9389 input_line_pointer = end;
9390 *end = 0;
9391 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
9392}
9393
9394void
9395md_operand (expressionS *e)
9396{
9397 char *end;
9398 const reg_entry *r;
9399
9400 switch (*input_line_pointer)
9401 {
9402 case REGISTER_PREFIX:
9403 r = parse_real_register (input_line_pointer, &end);
9404 if (r)
9405 {
9406 e->X_op = O_register;
9407 e->X_add_number = r - i386_regtab;
9408 input_line_pointer = end;
9409 }
9410 break;
9411
9412 case '[':
9413 gas_assert (intel_syntax);
9414 end = input_line_pointer++;
9415 expression (e);
9416 if (*input_line_pointer == ']')
9417 {
9418 ++input_line_pointer;
9419 e->X_op_symbol = make_expr_symbol (e);
9420 e->X_add_symbol = NULL;
9421 e->X_add_number = 0;
9422 e->X_op = O_index;
9423 }
9424 else
9425 {
9426 e->X_op = O_absent;
9427 input_line_pointer = end;
9428 }
9429 break;
9430 }
9431}
9432
9433\f
9434#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9435const char *md_shortopts = "kVQ:sqn";
9436#else
9437const char *md_shortopts = "qn";
9438#endif
9439
9440#define OPTION_32 (OPTION_MD_BASE + 0)
9441#define OPTION_64 (OPTION_MD_BASE + 1)
9442#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9443#define OPTION_MARCH (OPTION_MD_BASE + 3)
9444#define OPTION_MTUNE (OPTION_MD_BASE + 4)
9445#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9446#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9447#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9448#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9449#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9450#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9451#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9452#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9453#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9454#define OPTION_X32 (OPTION_MD_BASE + 14)
9455#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9456#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9457#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9458
9459struct option md_longopts[] =
9460{
9461 {"32", no_argument, NULL, OPTION_32},
9462#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9463 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9464 {"64", no_argument, NULL, OPTION_64},
9465#endif
9466#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9467 {"x32", no_argument, NULL, OPTION_X32},
9468#endif
9469 {"divide", no_argument, NULL, OPTION_DIVIDE},
9470 {"march", required_argument, NULL, OPTION_MARCH},
9471 {"mtune", required_argument, NULL, OPTION_MTUNE},
9472 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9473 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9474 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9475 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9476 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
9477 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
9478 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
9479 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
9480 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
9481 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
9482 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9483 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
9484 {NULL, no_argument, NULL, 0}
9485};
9486size_t md_longopts_size = sizeof (md_longopts);
9487
9488int
9489md_parse_option (int c, char *arg)
9490{
9491 unsigned int j;
9492 char *arch, *next;
9493
9494 switch (c)
9495 {
9496 case 'n':
9497 optimize_align_code = 0;
9498 break;
9499
9500 case 'q':
9501 quiet_warnings = 1;
9502 break;
9503
9504#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9505 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9506 should be emitted or not. FIXME: Not implemented. */
9507 case 'Q':
9508 break;
9509
9510 /* -V: SVR4 argument to print version ID. */
9511 case 'V':
9512 print_version_id ();
9513 break;
9514
9515 /* -k: Ignore for FreeBSD compatibility. */
9516 case 'k':
9517 break;
9518
9519 case 's':
9520 /* -s: On i386 Solaris, this tells the native assembler to use
9521 .stab instead of .stab.excl. We always use .stab anyhow. */
9522 break;
9523#endif
9524#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9525 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9526 case OPTION_64:
9527 {
9528 const char **list, **l;
9529
9530 list = bfd_target_list ();
9531 for (l = list; *l != NULL; l++)
9532 if (CONST_STRNEQ (*l, "elf64-x86-64")
9533 || strcmp (*l, "coff-x86-64") == 0
9534 || strcmp (*l, "pe-x86-64") == 0
9535 || strcmp (*l, "pei-x86-64") == 0
9536 || strcmp (*l, "mach-o-x86-64") == 0)
9537 {
9538 default_arch = "x86_64";
9539 break;
9540 }
9541 if (*l == NULL)
9542 as_fatal (_("no compiled in support for x86_64"));
9543 free (list);
9544 }
9545 break;
9546#endif
9547
9548#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9549 case OPTION_X32:
9550 if (IS_ELF)
9551 {
9552 const char **list, **l;
9553
9554 list = bfd_target_list ();
9555 for (l = list; *l != NULL; l++)
9556 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9557 {
9558 default_arch = "x86_64:32";
9559 break;
9560 }
9561 if (*l == NULL)
9562 as_fatal (_("no compiled in support for 32bit x86_64"));
9563 free (list);
9564 }
9565 else
9566 as_fatal (_("32bit x86_64 is only supported for ELF"));
9567 break;
9568#endif
9569
9570 case OPTION_32:
9571 default_arch = "i386";
9572 break;
9573
9574 case OPTION_DIVIDE:
9575#ifdef SVR4_COMMENT_CHARS
9576 {
9577 char *n, *t;
9578 const char *s;
9579
9580 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9581 t = n;
9582 for (s = i386_comment_chars; *s != '\0'; s++)
9583 if (*s != '/')
9584 *t++ = *s;
9585 *t = '\0';
9586 i386_comment_chars = n;
9587 }
9588#endif
9589 break;
9590
9591 case OPTION_MARCH:
9592 arch = xstrdup (arg);
9593 do
9594 {
9595 if (*arch == '.')
9596 as_fatal (_("invalid -march= option: `%s'"), arg);
9597 next = strchr (arch, '+');
9598 if (next)
9599 *next++ = '\0';
9600 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9601 {
9602 if (strcmp (arch, cpu_arch [j].name) == 0)
9603 {
9604 /* Processor. */
9605 if (! cpu_arch[j].flags.bitfield.cpui386)
9606 continue;
9607
9608 cpu_arch_name = cpu_arch[j].name;
9609 cpu_sub_arch_name = NULL;
9610 cpu_arch_flags = cpu_arch[j].flags;
9611 cpu_arch_isa = cpu_arch[j].type;
9612 cpu_arch_isa_flags = cpu_arch[j].flags;
9613 if (!cpu_arch_tune_set)
9614 {
9615 cpu_arch_tune = cpu_arch_isa;
9616 cpu_arch_tune_flags = cpu_arch_isa_flags;
9617 }
9618 break;
9619 }
9620 else if (*cpu_arch [j].name == '.'
9621 && strcmp (arch, cpu_arch [j].name + 1) == 0)
9622 {
9623 /* ISA entension. */
9624 i386_cpu_flags flags;
9625
9626 if (!cpu_arch[j].negated)
9627 flags = cpu_flags_or (cpu_arch_flags,
9628 cpu_arch[j].flags);
9629 else
9630 flags = cpu_flags_and_not (cpu_arch_flags,
9631 cpu_arch[j].flags);
9632 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
9633 {
9634 if (cpu_sub_arch_name)
9635 {
9636 char *name = cpu_sub_arch_name;
9637 cpu_sub_arch_name = concat (name,
9638 cpu_arch[j].name,
9639 (const char *) NULL);
9640 free (name);
9641 }
9642 else
9643 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
9644 cpu_arch_flags = flags;
9645 cpu_arch_isa_flags = flags;
9646 }
9647 break;
9648 }
9649 }
9650
9651 if (j >= ARRAY_SIZE (cpu_arch))
9652 as_fatal (_("invalid -march= option: `%s'"), arg);
9653
9654 arch = next;
9655 }
9656 while (next != NULL );
9657 break;
9658
9659 case OPTION_MTUNE:
9660 if (*arg == '.')
9661 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9662 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9663 {
9664 if (strcmp (arg, cpu_arch [j].name) == 0)
9665 {
9666 cpu_arch_tune_set = 1;
9667 cpu_arch_tune = cpu_arch [j].type;
9668 cpu_arch_tune_flags = cpu_arch[j].flags;
9669 break;
9670 }
9671 }
9672 if (j >= ARRAY_SIZE (cpu_arch))
9673 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9674 break;
9675
9676 case OPTION_MMNEMONIC:
9677 if (strcasecmp (arg, "att") == 0)
9678 intel_mnemonic = 0;
9679 else if (strcasecmp (arg, "intel") == 0)
9680 intel_mnemonic = 1;
9681 else
9682 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
9683 break;
9684
9685 case OPTION_MSYNTAX:
9686 if (strcasecmp (arg, "att") == 0)
9687 intel_syntax = 0;
9688 else if (strcasecmp (arg, "intel") == 0)
9689 intel_syntax = 1;
9690 else
9691 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
9692 break;
9693
9694 case OPTION_MINDEX_REG:
9695 allow_index_reg = 1;
9696 break;
9697
9698 case OPTION_MNAKED_REG:
9699 allow_naked_reg = 1;
9700 break;
9701
9702 case OPTION_MOLD_GCC:
9703 old_gcc = 1;
9704 break;
9705
9706 case OPTION_MSSE2AVX:
9707 sse2avx = 1;
9708 break;
9709
9710 case OPTION_MSSE_CHECK:
9711 if (strcasecmp (arg, "error") == 0)
9712 sse_check = check_error;
9713 else if (strcasecmp (arg, "warning") == 0)
9714 sse_check = check_warning;
9715 else if (strcasecmp (arg, "none") == 0)
9716 sse_check = check_none;
9717 else
9718 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
9719 break;
9720
9721 case OPTION_MOPERAND_CHECK:
9722 if (strcasecmp (arg, "error") == 0)
9723 operand_check = check_error;
9724 else if (strcasecmp (arg, "warning") == 0)
9725 operand_check = check_warning;
9726 else if (strcasecmp (arg, "none") == 0)
9727 operand_check = check_none;
9728 else
9729 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9730 break;
9731
9732 case OPTION_MAVXSCALAR:
9733 if (strcasecmp (arg, "128") == 0)
9734 avxscalar = vex128;
9735 else if (strcasecmp (arg, "256") == 0)
9736 avxscalar = vex256;
9737 else
9738 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
9739 break;
9740
9741 case OPTION_MADD_BND_PREFIX:
9742 add_bnd_prefix = 1;
9743 break;
9744
9745 case OPTION_MEVEXLIG:
9746 if (strcmp (arg, "128") == 0)
9747 evexlig = evexl128;
9748 else if (strcmp (arg, "256") == 0)
9749 evexlig = evexl256;
9750 else if (strcmp (arg, "512") == 0)
9751 evexlig = evexl512;
9752 else
9753 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9754 break;
9755
9756 case OPTION_MEVEXWIG:
9757 if (strcmp (arg, "0") == 0)
9758 evexwig = evexw0;
9759 else if (strcmp (arg, "1") == 0)
9760 evexwig = evexw1;
9761 else
9762 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9763 break;
9764
9765 default:
9766 return 0;
9767 }
9768 return 1;
9769}
9770
9771#define MESSAGE_TEMPLATE \
9772" "
9773
9774static void
9775show_arch (FILE *stream, int ext, int check)
9776{
9777 static char message[] = MESSAGE_TEMPLATE;
9778 char *start = message + 27;
9779 char *p;
9780 int size = sizeof (MESSAGE_TEMPLATE);
9781 int left;
9782 const char *name;
9783 int len;
9784 unsigned int j;
9785
9786 p = start;
9787 left = size - (start - message);
9788 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9789 {
9790 /* Should it be skipped? */
9791 if (cpu_arch [j].skip)
9792 continue;
9793
9794 name = cpu_arch [j].name;
9795 len = cpu_arch [j].len;
9796 if (*name == '.')
9797 {
9798 /* It is an extension. Skip if we aren't asked to show it. */
9799 if (ext)
9800 {
9801 name++;
9802 len--;
9803 }
9804 else
9805 continue;
9806 }
9807 else if (ext)
9808 {
9809 /* It is an processor. Skip if we show only extension. */
9810 continue;
9811 }
9812 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9813 {
9814 /* It is an impossible processor - skip. */
9815 continue;
9816 }
9817
9818 /* Reserve 2 spaces for ", " or ",\0" */
9819 left -= len + 2;
9820
9821 /* Check if there is any room. */
9822 if (left >= 0)
9823 {
9824 if (p != start)
9825 {
9826 *p++ = ',';
9827 *p++ = ' ';
9828 }
9829 p = mempcpy (p, name, len);
9830 }
9831 else
9832 {
9833 /* Output the current message now and start a new one. */
9834 *p++ = ',';
9835 *p = '\0';
9836 fprintf (stream, "%s\n", message);
9837 p = start;
9838 left = size - (start - message) - len - 2;
9839
9840 gas_assert (left >= 0);
9841
9842 p = mempcpy (p, name, len);
9843 }
9844 }
9845
9846 *p = '\0';
9847 fprintf (stream, "%s\n", message);
9848}
9849
9850void
9851md_show_usage (FILE *stream)
9852{
9853#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9854 fprintf (stream, _("\
9855 -Q ignored\n\
9856 -V print assembler version number\n\
9857 -k ignored\n"));
9858#endif
9859 fprintf (stream, _("\
9860 -n Do not optimize code alignment\n\
9861 -q quieten some warnings\n"));
9862#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9863 fprintf (stream, _("\
9864 -s ignored\n"));
9865#endif
9866#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9867 || defined (TE_PE) || defined (TE_PEP))
9868 fprintf (stream, _("\
9869 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
9870#endif
9871#ifdef SVR4_COMMENT_CHARS
9872 fprintf (stream, _("\
9873 --divide do not treat `/' as a comment character\n"));
9874#else
9875 fprintf (stream, _("\
9876 --divide ignored\n"));
9877#endif
9878 fprintf (stream, _("\
9879 -march=CPU[,+EXTENSION...]\n\
9880 generate code for CPU and EXTENSION, CPU is one of:\n"));
9881 show_arch (stream, 0, 1);
9882 fprintf (stream, _("\
9883 EXTENSION is combination of:\n"));
9884 show_arch (stream, 1, 0);
9885 fprintf (stream, _("\
9886 -mtune=CPU optimize for CPU, CPU is one of:\n"));
9887 show_arch (stream, 0, 0);
9888 fprintf (stream, _("\
9889 -msse2avx encode SSE instructions with VEX prefix\n"));
9890 fprintf (stream, _("\
9891 -msse-check=[none|error|warning]\n\
9892 check SSE instructions\n"));
9893 fprintf (stream, _("\
9894 -moperand-check=[none|error|warning]\n\
9895 check operand combinations for validity\n"));
9896 fprintf (stream, _("\
9897 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
9898 length\n"));
9899 fprintf (stream, _("\
9900 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
9901 length\n"));
9902 fprintf (stream, _("\
9903 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
9904 for EVEX.W bit ignored instructions\n"));
9905 fprintf (stream, _("\
9906 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
9907 fprintf (stream, _("\
9908 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9909 fprintf (stream, _("\
9910 -mindex-reg support pseudo index registers\n"));
9911 fprintf (stream, _("\
9912 -mnaked-reg don't require `%%' prefix for registers\n"));
9913 fprintf (stream, _("\
9914 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
9915 fprintf (stream, _("\
9916 -madd-bnd-prefix add BND prefix for all valid branches\n"));
9917}
9918
9919#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
9920 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9921 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9922
9923/* Pick the target format to use. */
9924
9925const char *
9926i386_target_format (void)
9927{
9928 if (!strncmp (default_arch, "x86_64", 6))
9929 {
9930 update_code_flag (CODE_64BIT, 1);
9931 if (default_arch[6] == '\0')
9932 x86_elf_abi = X86_64_ABI;
9933 else
9934 x86_elf_abi = X86_64_X32_ABI;
9935 }
9936 else if (!strcmp (default_arch, "i386"))
9937 update_code_flag (CODE_32BIT, 1);
9938 else
9939 as_fatal (_("unknown architecture"));
9940
9941 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
9942 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
9943 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
9944 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
9945
9946 switch (OUTPUT_FLAVOR)
9947 {
9948#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
9949 case bfd_target_aout_flavour:
9950 return AOUT_TARGET_FORMAT;
9951#endif
9952#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
9953# if defined (TE_PE) || defined (TE_PEP)
9954 case bfd_target_coff_flavour:
9955 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
9956# elif defined (TE_GO32)
9957 case bfd_target_coff_flavour:
9958 return "coff-go32";
9959# else
9960 case bfd_target_coff_flavour:
9961 return "coff-i386";
9962# endif
9963#endif
9964#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9965 case bfd_target_elf_flavour:
9966 {
9967 const char *format;
9968
9969 switch (x86_elf_abi)
9970 {
9971 default:
9972 format = ELF_TARGET_FORMAT;
9973 break;
9974 case X86_64_ABI:
9975 use_rela_relocations = 1;
9976 object_64bit = 1;
9977 format = ELF_TARGET_FORMAT64;
9978 break;
9979 case X86_64_X32_ABI:
9980 use_rela_relocations = 1;
9981 object_64bit = 1;
9982 disallow_64bit_reloc = 1;
9983 format = ELF_TARGET_FORMAT32;
9984 break;
9985 }
9986 if (cpu_arch_isa == PROCESSOR_L1OM)
9987 {
9988 if (x86_elf_abi != X86_64_ABI)
9989 as_fatal (_("Intel L1OM is 64bit only"));
9990 return ELF_TARGET_L1OM_FORMAT;
9991 }
9992 if (cpu_arch_isa == PROCESSOR_K1OM)
9993 {
9994 if (x86_elf_abi != X86_64_ABI)
9995 as_fatal (_("Intel K1OM is 64bit only"));
9996 return ELF_TARGET_K1OM_FORMAT;
9997 }
9998 else
9999 return format;
10000 }
10001#endif
10002#if defined (OBJ_MACH_O)
10003 case bfd_target_mach_o_flavour:
10004 if (flag_code == CODE_64BIT)
10005 {
10006 use_rela_relocations = 1;
10007 object_64bit = 1;
10008 return "mach-o-x86-64";
10009 }
10010 else
10011 return "mach-o-i386";
10012#endif
10013 default:
10014 abort ();
10015 return NULL;
10016 }
10017}
10018
10019#endif /* OBJ_MAYBE_ more than one */
10020
10021#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
10022void
10023i386_elf_emit_arch_note (void)
10024{
10025 if (IS_ELF && cpu_arch_name != NULL)
10026 {
10027 char *p;
10028 asection *seg = now_seg;
10029 subsegT subseg = now_subseg;
10030 Elf_Internal_Note i_note;
10031 Elf_External_Note e_note;
10032 asection *note_secp;
10033 int len;
10034
10035 /* Create the .note section. */
10036 note_secp = subseg_new (".note", 0);
10037 bfd_set_section_flags (stdoutput,
10038 note_secp,
10039 SEC_HAS_CONTENTS | SEC_READONLY);
10040
10041 /* Process the arch string. */
10042 len = strlen (cpu_arch_name);
10043
10044 i_note.namesz = len + 1;
10045 i_note.descsz = 0;
10046 i_note.type = NT_ARCH;
10047 p = frag_more (sizeof (e_note.namesz));
10048 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
10049 p = frag_more (sizeof (e_note.descsz));
10050 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
10051 p = frag_more (sizeof (e_note.type));
10052 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
10053 p = frag_more (len + 1);
10054 strcpy (p, cpu_arch_name);
10055
10056 frag_align (2, 0, 0);
10057
10058 subseg_set (seg, subseg);
10059 }
10060}
10061#endif
10062\f
10063symbolS *
10064md_undefined_symbol (char *name)
10065{
10066 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10067 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10068 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10069 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
10070 {
10071 if (!GOT_symbol)
10072 {
10073 if (symbol_find (name))
10074 as_bad (_("GOT already in symbol table"));
10075 GOT_symbol = symbol_new (name, undefined_section,
10076 (valueT) 0, &zero_address_frag);
10077 };
10078 return GOT_symbol;
10079 }
10080 return 0;
10081}
10082
10083/* Round up a section size to the appropriate boundary. */
10084
10085valueT
10086md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
10087{
10088#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10089 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10090 {
10091 /* For a.out, force the section size to be aligned. If we don't do
10092 this, BFD will align it for us, but it will not write out the
10093 final bytes of the section. This may be a bug in BFD, but it is
10094 easier to fix it here since that is how the other a.out targets
10095 work. */
10096 int align;
10097
10098 align = bfd_get_section_alignment (stdoutput, segment);
10099 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10100 }
10101#endif
10102
10103 return size;
10104}
10105
10106/* On the i386, PC-relative offsets are relative to the start of the
10107 next instruction. That is, the address of the offset, plus its
10108 size, since the offset is always the last part of the insn. */
10109
10110long
10111md_pcrel_from (fixS *fixP)
10112{
10113 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10114}
10115
10116#ifndef I386COFF
10117
10118static void
10119s_bss (int ignore ATTRIBUTE_UNUSED)
10120{
10121 int temp;
10122
10123#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10124 if (IS_ELF)
10125 obj_elf_section_change_hook ();
10126#endif
10127 temp = get_absolute_expression ();
10128 subseg_set (bss_section, (subsegT) temp);
10129 demand_empty_rest_of_line ();
10130}
10131
10132#endif
10133
10134void
10135i386_validate_fix (fixS *fixp)
10136{
10137 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10138 {
10139 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10140 {
10141 if (!object_64bit)
10142 abort ();
10143 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10144 }
10145 else
10146 {
10147 if (!object_64bit)
10148 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10149 else
10150 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10151 }
10152 fixp->fx_subsy = 0;
10153 }
10154}
10155
10156arelent *
10157tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
10158{
10159 arelent *rel;
10160 bfd_reloc_code_real_type code;
10161
10162 switch (fixp->fx_r_type)
10163 {
10164#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10165 case BFD_RELOC_SIZE32:
10166 case BFD_RELOC_SIZE64:
10167 if (S_IS_DEFINED (fixp->fx_addsy)
10168 && !S_IS_EXTERNAL (fixp->fx_addsy))
10169 {
10170 /* Resolve size relocation against local symbol to size of
10171 the symbol plus addend. */
10172 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10173 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10174 && !fits_in_unsigned_long (value))
10175 as_bad_where (fixp->fx_file, fixp->fx_line,
10176 _("symbol size computation overflow"));
10177 fixp->fx_addsy = NULL;
10178 fixp->fx_subsy = NULL;
10179 md_apply_fix (fixp, (valueT *) &value, NULL);
10180 return NULL;
10181 }
10182#endif
10183
10184 case BFD_RELOC_X86_64_PLT32:
10185 case BFD_RELOC_X86_64_GOT32:
10186 case BFD_RELOC_X86_64_GOTPCREL:
10187 case BFD_RELOC_386_PLT32:
10188 case BFD_RELOC_386_GOT32:
10189 case BFD_RELOC_386_GOTOFF:
10190 case BFD_RELOC_386_GOTPC:
10191 case BFD_RELOC_386_TLS_GD:
10192 case BFD_RELOC_386_TLS_LDM:
10193 case BFD_RELOC_386_TLS_LDO_32:
10194 case BFD_RELOC_386_TLS_IE_32:
10195 case BFD_RELOC_386_TLS_IE:
10196 case BFD_RELOC_386_TLS_GOTIE:
10197 case BFD_RELOC_386_TLS_LE_32:
10198 case BFD_RELOC_386_TLS_LE:
10199 case BFD_RELOC_386_TLS_GOTDESC:
10200 case BFD_RELOC_386_TLS_DESC_CALL:
10201 case BFD_RELOC_X86_64_TLSGD:
10202 case BFD_RELOC_X86_64_TLSLD:
10203 case BFD_RELOC_X86_64_DTPOFF32:
10204 case BFD_RELOC_X86_64_DTPOFF64:
10205 case BFD_RELOC_X86_64_GOTTPOFF:
10206 case BFD_RELOC_X86_64_TPOFF32:
10207 case BFD_RELOC_X86_64_TPOFF64:
10208 case BFD_RELOC_X86_64_GOTOFF64:
10209 case BFD_RELOC_X86_64_GOTPC32:
10210 case BFD_RELOC_X86_64_GOT64:
10211 case BFD_RELOC_X86_64_GOTPCREL64:
10212 case BFD_RELOC_X86_64_GOTPC64:
10213 case BFD_RELOC_X86_64_GOTPLT64:
10214 case BFD_RELOC_X86_64_PLTOFF64:
10215 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10216 case BFD_RELOC_X86_64_TLSDESC_CALL:
10217 case BFD_RELOC_RVA:
10218 case BFD_RELOC_VTABLE_ENTRY:
10219 case BFD_RELOC_VTABLE_INHERIT:
10220#ifdef TE_PE
10221 case BFD_RELOC_32_SECREL:
10222#endif
10223 code = fixp->fx_r_type;
10224 break;
10225 case BFD_RELOC_X86_64_32S:
10226 if (!fixp->fx_pcrel)
10227 {
10228 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10229 code = fixp->fx_r_type;
10230 break;
10231 }
10232 default:
10233 if (fixp->fx_pcrel)
10234 {
10235 switch (fixp->fx_size)
10236 {
10237 default:
10238 as_bad_where (fixp->fx_file, fixp->fx_line,
10239 _("can not do %d byte pc-relative relocation"),
10240 fixp->fx_size);
10241 code = BFD_RELOC_32_PCREL;
10242 break;
10243 case 1: code = BFD_RELOC_8_PCREL; break;
10244 case 2: code = BFD_RELOC_16_PCREL; break;
10245 case 4: code = BFD_RELOC_32_PCREL; break;
10246#ifdef BFD64
10247 case 8: code = BFD_RELOC_64_PCREL; break;
10248#endif
10249 }
10250 }
10251 else
10252 {
10253 switch (fixp->fx_size)
10254 {
10255 default:
10256 as_bad_where (fixp->fx_file, fixp->fx_line,
10257 _("can not do %d byte relocation"),
10258 fixp->fx_size);
10259 code = BFD_RELOC_32;
10260 break;
10261 case 1: code = BFD_RELOC_8; break;
10262 case 2: code = BFD_RELOC_16; break;
10263 case 4: code = BFD_RELOC_32; break;
10264#ifdef BFD64
10265 case 8: code = BFD_RELOC_64; break;
10266#endif
10267 }
10268 }
10269 break;
10270 }
10271
10272 if ((code == BFD_RELOC_32
10273 || code == BFD_RELOC_32_PCREL
10274 || code == BFD_RELOC_X86_64_32S)
10275 && GOT_symbol
10276 && fixp->fx_addsy == GOT_symbol)
10277 {
10278 if (!object_64bit)
10279 code = BFD_RELOC_386_GOTPC;
10280 else
10281 code = BFD_RELOC_X86_64_GOTPC32;
10282 }
10283 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10284 && GOT_symbol
10285 && fixp->fx_addsy == GOT_symbol)
10286 {
10287 code = BFD_RELOC_X86_64_GOTPC64;
10288 }
10289
10290 rel = (arelent *) xmalloc (sizeof (arelent));
10291 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10292 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
10293
10294 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
10295
10296 if (!use_rela_relocations)
10297 {
10298 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10299 vtable entry to be used in the relocation's section offset. */
10300 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10301 rel->address = fixp->fx_offset;
10302#if defined (OBJ_COFF) && defined (TE_PE)
10303 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10304 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10305 else
10306#endif
10307 rel->addend = 0;
10308 }
10309 /* Use the rela in 64bit mode. */
10310 else
10311 {
10312 if (disallow_64bit_reloc)
10313 switch (code)
10314 {
10315 case BFD_RELOC_X86_64_DTPOFF64:
10316 case BFD_RELOC_X86_64_TPOFF64:
10317 case BFD_RELOC_64_PCREL:
10318 case BFD_RELOC_X86_64_GOTOFF64:
10319 case BFD_RELOC_X86_64_GOT64:
10320 case BFD_RELOC_X86_64_GOTPCREL64:
10321 case BFD_RELOC_X86_64_GOTPC64:
10322 case BFD_RELOC_X86_64_GOTPLT64:
10323 case BFD_RELOC_X86_64_PLTOFF64:
10324 as_bad_where (fixp->fx_file, fixp->fx_line,
10325 _("cannot represent relocation type %s in x32 mode"),
10326 bfd_get_reloc_code_name (code));
10327 break;
10328 default:
10329 break;
10330 }
10331
10332 if (!fixp->fx_pcrel)
10333 rel->addend = fixp->fx_offset;
10334 else
10335 switch (code)
10336 {
10337 case BFD_RELOC_X86_64_PLT32:
10338 case BFD_RELOC_X86_64_GOT32:
10339 case BFD_RELOC_X86_64_GOTPCREL:
10340 case BFD_RELOC_X86_64_TLSGD:
10341 case BFD_RELOC_X86_64_TLSLD:
10342 case BFD_RELOC_X86_64_GOTTPOFF:
10343 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10344 case BFD_RELOC_X86_64_TLSDESC_CALL:
10345 rel->addend = fixp->fx_offset - fixp->fx_size;
10346 break;
10347 default:
10348 rel->addend = (section->vma
10349 - fixp->fx_size
10350 + fixp->fx_addnumber
10351 + md_pcrel_from (fixp));
10352 break;
10353 }
10354 }
10355
10356 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10357 if (rel->howto == NULL)
10358 {
10359 as_bad_where (fixp->fx_file, fixp->fx_line,
10360 _("cannot represent relocation type %s"),
10361 bfd_get_reloc_code_name (code));
10362 /* Set howto to a garbage value so that we can keep going. */
10363 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
10364 gas_assert (rel->howto != NULL);
10365 }
10366
10367 return rel;
10368}
10369
10370#include "tc-i386-intel.c"
10371
10372void
10373tc_x86_parse_to_dw2regnum (expressionS *exp)
10374{
10375 int saved_naked_reg;
10376 char saved_register_dot;
10377
10378 saved_naked_reg = allow_naked_reg;
10379 allow_naked_reg = 1;
10380 saved_register_dot = register_chars['.'];
10381 register_chars['.'] = '.';
10382 allow_pseudo_reg = 1;
10383 expression_and_evaluate (exp);
10384 allow_pseudo_reg = 0;
10385 register_chars['.'] = saved_register_dot;
10386 allow_naked_reg = saved_naked_reg;
10387
10388 if (exp->X_op == O_register && exp->X_add_number >= 0)
10389 {
10390 if ((addressT) exp->X_add_number < i386_regtab_size)
10391 {
10392 exp->X_op = O_constant;
10393 exp->X_add_number = i386_regtab[exp->X_add_number]
10394 .dw2_regnum[flag_code >> 1];
10395 }
10396 else
10397 exp->X_op = O_illegal;
10398 }
10399}
10400
10401void
10402tc_x86_frame_initial_instructions (void)
10403{
10404 static unsigned int sp_regno[2];
10405
10406 if (!sp_regno[flag_code >> 1])
10407 {
10408 char *saved_input = input_line_pointer;
10409 char sp[][4] = {"esp", "rsp"};
10410 expressionS exp;
10411
10412 input_line_pointer = sp[flag_code >> 1];
10413 tc_x86_parse_to_dw2regnum (&exp);
10414 gas_assert (exp.X_op == O_constant);
10415 sp_regno[flag_code >> 1] = exp.X_add_number;
10416 input_line_pointer = saved_input;
10417 }
10418
10419 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10420 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
10421}
10422
10423int
10424x86_dwarf2_addr_size (void)
10425{
10426#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10427 if (x86_elf_abi == X86_64_X32_ABI)
10428 return 4;
10429#endif
10430 return bfd_arch_bits_per_address (stdoutput) / 8;
10431}
10432
10433int
10434i386_elf_section_type (const char *str, size_t len)
10435{
10436 if (flag_code == CODE_64BIT
10437 && len == sizeof ("unwind") - 1
10438 && strncmp (str, "unwind", 6) == 0)
10439 return SHT_X86_64_UNWIND;
10440
10441 return -1;
10442}
10443
10444#ifdef TE_SOLARIS
10445void
10446i386_solaris_fix_up_eh_frame (segT sec)
10447{
10448 if (flag_code == CODE_64BIT)
10449 elf_section_type (sec) = SHT_X86_64_UNWIND;
10450}
10451#endif
10452
10453#ifdef TE_PE
10454void
10455tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10456{
10457 expressionS exp;
10458
10459 exp.X_op = O_secrel;
10460 exp.X_add_symbol = symbol;
10461 exp.X_add_number = 0;
10462 emit_expr (&exp, size);
10463}
10464#endif
10465
10466#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10467/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10468
10469bfd_vma
10470x86_64_section_letter (int letter, char **ptr_msg)
10471{
10472 if (flag_code == CODE_64BIT)
10473 {
10474 if (letter == 'l')
10475 return SHF_X86_64_LARGE;
10476
10477 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10478 }
10479 else
10480 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
10481 return -1;
10482}
10483
10484bfd_vma
10485x86_64_section_word (char *str, size_t len)
10486{
10487 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
10488 return SHF_X86_64_LARGE;
10489
10490 return -1;
10491}
10492
10493static void
10494handle_large_common (int small ATTRIBUTE_UNUSED)
10495{
10496 if (flag_code != CODE_64BIT)
10497 {
10498 s_comm_internal (0, elf_common_parse);
10499 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10500 }
10501 else
10502 {
10503 static segT lbss_section;
10504 asection *saved_com_section_ptr = elf_com_section_ptr;
10505 asection *saved_bss_section = bss_section;
10506
10507 if (lbss_section == NULL)
10508 {
10509 flagword applicable;
10510 segT seg = now_seg;
10511 subsegT subseg = now_subseg;
10512
10513 /* The .lbss section is for local .largecomm symbols. */
10514 lbss_section = subseg_new (".lbss", 0);
10515 applicable = bfd_applicable_section_flags (stdoutput);
10516 bfd_set_section_flags (stdoutput, lbss_section,
10517 applicable & SEC_ALLOC);
10518 seg_info (lbss_section)->bss = 1;
10519
10520 subseg_set (seg, subseg);
10521 }
10522
10523 elf_com_section_ptr = &_bfd_elf_large_com_section;
10524 bss_section = lbss_section;
10525
10526 s_comm_internal (0, elf_common_parse);
10527
10528 elf_com_section_ptr = saved_com_section_ptr;
10529 bss_section = saved_bss_section;
10530 }
10531}
10532#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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