| 1 | /* tc-i386.h -- Header file for tc-i386.c |
| 2 | Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
| 3 | 2001, 2002, 2003 |
| 4 | Free Software Foundation, Inc. |
| 5 | |
| 6 | This file is part of GAS, the GNU Assembler. |
| 7 | |
| 8 | GAS is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU General Public License as published by |
| 10 | the Free Software Foundation; either version 2, or (at your option) |
| 11 | any later version. |
| 12 | |
| 13 | GAS is distributed in the hope that it will be useful, |
| 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | GNU General Public License for more details. |
| 17 | |
| 18 | You should have received a copy of the GNU General Public License |
| 19 | along with GAS; see the file COPYING. If not, write to the Free |
| 20 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA |
| 21 | 02111-1307, USA. */ |
| 22 | |
| 23 | #ifndef TC_I386 |
| 24 | #define TC_I386 1 |
| 25 | |
| 26 | #ifdef ANSI_PROTOTYPES |
| 27 | struct fix; |
| 28 | #endif |
| 29 | |
| 30 | #define TARGET_BYTES_BIG_ENDIAN 0 |
| 31 | |
| 32 | #ifdef TE_LYNX |
| 33 | #define TARGET_FORMAT "coff-i386-lynx" |
| 34 | #endif |
| 35 | |
| 36 | #ifdef BFD_ASSEMBLER |
| 37 | #define TARGET_ARCH bfd_arch_i386 |
| 38 | #define TARGET_MACH (i386_mach ()) |
| 39 | extern unsigned long i386_mach PARAMS ((void)); |
| 40 | |
| 41 | #ifdef TE_FreeBSD |
| 42 | #define AOUT_TARGET_FORMAT "a.out-i386-freebsd" |
| 43 | #endif |
| 44 | #ifdef TE_NetBSD |
| 45 | #define AOUT_TARGET_FORMAT "a.out-i386-netbsd" |
| 46 | #endif |
| 47 | #ifdef TE_386BSD |
| 48 | #define AOUT_TARGET_FORMAT "a.out-i386-bsd" |
| 49 | #endif |
| 50 | #ifdef TE_LINUX |
| 51 | #define AOUT_TARGET_FORMAT "a.out-i386-linux" |
| 52 | #endif |
| 53 | #ifdef TE_Mach |
| 54 | #define AOUT_TARGET_FORMAT "a.out-mach3" |
| 55 | #endif |
| 56 | #ifdef TE_DYNIX |
| 57 | #define AOUT_TARGET_FORMAT "a.out-i386-dynix" |
| 58 | #endif |
| 59 | #ifndef AOUT_TARGET_FORMAT |
| 60 | #define AOUT_TARGET_FORMAT "a.out-i386" |
| 61 | #endif |
| 62 | |
| 63 | #ifdef TE_FreeBSD |
| 64 | #define ELF_TARGET_FORMAT "elf32-i386-freebsd" |
| 65 | #endif |
| 66 | #ifndef ELF_TARGET_FORMAT |
| 67 | #define ELF_TARGET_FORMAT "elf32-i386" |
| 68 | #endif |
| 69 | |
| 70 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
| 71 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) |
| 72 | extern const char *i386_target_format PARAMS ((void)); |
| 73 | #define TARGET_FORMAT i386_target_format () |
| 74 | #else |
| 75 | #ifdef OBJ_ELF |
| 76 | #define TARGET_FORMAT ELF_TARGET_FORMAT |
| 77 | #endif |
| 78 | #ifdef OBJ_AOUT |
| 79 | #define TARGET_FORMAT AOUT_TARGET_FORMAT |
| 80 | #endif |
| 81 | #endif |
| 82 | |
| 83 | #if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)) |
| 84 | #define md_end i386_elf_emit_arch_note |
| 85 | extern void i386_elf_emit_arch_note PARAMS ((void)); |
| 86 | #endif |
| 87 | |
| 88 | #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0 |
| 89 | |
| 90 | #else /* ! BFD_ASSEMBLER */ |
| 91 | |
| 92 | /* COFF STUFF */ |
| 93 | |
| 94 | #define COFF_MAGIC I386MAGIC |
| 95 | #define BFD_ARCH bfd_arch_i386 |
| 96 | #define COFF_FLAGS F_AR32WR |
| 97 | #define TC_COUNT_RELOC(x) ((x)->fx_addsy || (x)->fx_r_type==7) |
| 98 | #define TC_COFF_FIX2RTYPE(FIX) tc_coff_fix2rtype(FIX) |
| 99 | extern short tc_coff_fix2rtype PARAMS ((struct fix *)); |
| 100 | #define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep (frag) |
| 101 | extern int tc_coff_sizemachdep PARAMS ((fragS *frag)); |
| 102 | |
| 103 | #ifdef TE_GO32 |
| 104 | /* DJGPP now expects some sections to be 2**4 aligned. */ |
| 105 | #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) \ |
| 106 | ((strcmp (obj_segment_name (SEG), ".text") == 0 \ |
| 107 | || strcmp (obj_segment_name (SEG), ".data") == 0 \ |
| 108 | || strcmp (obj_segment_name (SEG), ".bss") == 0 \ |
| 109 | || strncmp (obj_segment_name (SEG), ".gnu.linkonce.t", 15) == 0 \ |
| 110 | || strncmp (obj_segment_name (SEG), ".gnu.linkonce.d", 15) == 0 \ |
| 111 | || strncmp (obj_segment_name (SEG), ".gnu.linkonce.r", 15) == 0) \ |
| 112 | ? 4 \ |
| 113 | : 2) |
| 114 | #else |
| 115 | #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 2 |
| 116 | #endif |
| 117 | |
| 118 | #ifdef TE_386BSD |
| 119 | /* The BSDI linker apparently rejects objects with a machine type of |
| 120 | M_386 (100). */ |
| 121 | #define AOUT_MACHTYPE 0 |
| 122 | #else |
| 123 | #define AOUT_MACHTYPE 100 |
| 124 | #endif |
| 125 | |
| 126 | #ifndef OBJ_AOUT |
| 127 | #ifndef TE_PE |
| 128 | #ifndef TE_GO32 |
| 129 | /* Local labels starts with .L */ |
| 130 | #define LOCAL_LABEL(name) (name[0] == '.' \ |
| 131 | && (name[1] == 'L' || name[1] == 'X' || name[1] == '.')) |
| 132 | #endif |
| 133 | #endif |
| 134 | #endif |
| 135 | |
| 136 | #define tc_aout_pre_write_hook(x) {;} /* not used */ |
| 137 | #define tc_crawl_symbol_chain(a) {;} /* not used */ |
| 138 | #define tc_headers_hook(a) {;} /* not used */ |
| 139 | #define tc_coff_symbol_emit_hook(a) {;} /* not used */ |
| 140 | |
| 141 | #endif /* ! BFD_ASSEMBLER */ |
| 142 | |
| 143 | #define LOCAL_LABELS_FB 1 |
| 144 | |
| 145 | extern const char extra_symbol_chars[]; |
| 146 | #define tc_symbol_chars extra_symbol_chars |
| 147 | |
| 148 | #define MAX_OPERANDS 3 /* max operands per insn */ |
| 149 | #define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */ |
| 150 | #define MAX_MEMORY_OPERANDS 2 /* max memory refs per insn (string ops) */ |
| 151 | |
| 152 | /* Prefixes will be emitted in the order defined below. |
| 153 | WAIT_PREFIX must be the first prefix since FWAIT is really is an |
| 154 | instruction, and so must come before any prefixes. */ |
| 155 | #define WAIT_PREFIX 0 |
| 156 | #define LOCKREP_PREFIX 1 |
| 157 | #define ADDR_PREFIX 2 |
| 158 | #define DATA_PREFIX 3 |
| 159 | #define SEG_PREFIX 4 |
| 160 | #define REX_PREFIX 5 /* must come last. */ |
| 161 | #define MAX_PREFIXES 6 /* max prefixes per opcode */ |
| 162 | |
| 163 | /* we define the syntax here (modulo base,index,scale syntax) */ |
| 164 | #define REGISTER_PREFIX '%' |
| 165 | #define IMMEDIATE_PREFIX '$' |
| 166 | #define ABSOLUTE_PREFIX '*' |
| 167 | |
| 168 | #define TWO_BYTE_OPCODE_ESCAPE 0x0f |
| 169 | #define NOP_OPCODE (char) 0x90 |
| 170 | |
| 171 | /* register numbers */ |
| 172 | #define EBP_REG_NUM 5 |
| 173 | #define ESP_REG_NUM 4 |
| 174 | |
| 175 | /* modrm_byte.regmem for twobyte escape */ |
| 176 | #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM |
| 177 | /* index_base_byte.index for no index register addressing */ |
| 178 | #define NO_INDEX_REGISTER ESP_REG_NUM |
| 179 | /* index_base_byte.base for no base register addressing */ |
| 180 | #define NO_BASE_REGISTER EBP_REG_NUM |
| 181 | #define NO_BASE_REGISTER_16 6 |
| 182 | |
| 183 | /* these are the instruction mnemonic suffixes. */ |
| 184 | #define WORD_MNEM_SUFFIX 'w' |
| 185 | #define BYTE_MNEM_SUFFIX 'b' |
| 186 | #define SHORT_MNEM_SUFFIX 's' |
| 187 | #define LONG_MNEM_SUFFIX 'l' |
| 188 | #define QWORD_MNEM_SUFFIX 'q' |
| 189 | /* Intel Syntax */ |
| 190 | #define LONG_DOUBLE_MNEM_SUFFIX 'x' |
| 191 | |
| 192 | /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */ |
| 193 | #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */ |
| 194 | #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG) |
| 195 | |
| 196 | #define END_OF_INSN '\0' |
| 197 | |
| 198 | /* Intel Syntax */ |
| 199 | /* Values 0-4 map onto scale factor */ |
| 200 | #define BYTE_PTR 0 |
| 201 | #define WORD_PTR 1 |
| 202 | #define DWORD_PTR 2 |
| 203 | #define QWORD_PTR 3 |
| 204 | #define XWORD_PTR 4 |
| 205 | #define SHORT 5 |
| 206 | #define OFFSET_FLAT 6 |
| 207 | #define FLAT 7 |
| 208 | #define NONE_FOUND 8 |
| 209 | |
| 210 | typedef struct |
| 211 | { |
| 212 | /* instruction name sans width suffix ("mov" for movl insns) */ |
| 213 | char *name; |
| 214 | |
| 215 | /* how many operands */ |
| 216 | unsigned int operands; |
| 217 | |
| 218 | /* base_opcode is the fundamental opcode byte without optional |
| 219 | prefix(es). */ |
| 220 | unsigned int base_opcode; |
| 221 | |
| 222 | /* extension_opcode is the 3 bit extension for group <n> insns. |
| 223 | This field is also used to store the 8-bit opcode suffix for the |
| 224 | AMD 3DNow! instructions. |
| 225 | If this template has no extension opcode (the usual case) use None */ |
| 226 | unsigned int extension_opcode; |
| 227 | #define None 0xffff /* If no extension_opcode is possible. */ |
| 228 | |
| 229 | /* cpu feature flags */ |
| 230 | unsigned int cpu_flags; |
| 231 | #define Cpu086 0x1 /* Any old cpu will do, 0 does the same */ |
| 232 | #define Cpu186 0x2 /* i186 or better required */ |
| 233 | #define Cpu286 0x4 /* i286 or better required */ |
| 234 | #define Cpu386 0x8 /* i386 or better required */ |
| 235 | #define Cpu486 0x10 /* i486 or better required */ |
| 236 | #define Cpu586 0x20 /* i585 or better required */ |
| 237 | #define Cpu686 0x40 /* i686 or better required */ |
| 238 | #define CpuP4 0x80 /* Pentium4 or better required */ |
| 239 | #define CpuK6 0x100 /* AMD K6 or better required*/ |
| 240 | #define CpuAthlon 0x200 /* AMD Athlon or better required*/ |
| 241 | #define CpuSledgehammer 0x400 /* Sledgehammer or better required */ |
| 242 | #define CpuMMX 0x800 /* MMX support required */ |
| 243 | #define CpuSSE 0x1000 /* Streaming SIMD extensions required */ |
| 244 | #define CpuSSE2 0x2000 /* Streaming SIMD extensions 2 required */ |
| 245 | #define Cpu3dnow 0x4000 /* 3dnow! support required */ |
| 246 | |
| 247 | /* These flags are set by gas depending on the flag_code. */ |
| 248 | #define Cpu64 0x4000000 /* 64bit support required */ |
| 249 | #define CpuNo64 0x8000000 /* Not supported in the 64bit mode */ |
| 250 | |
| 251 | /* The default value for unknown CPUs - enable all features to avoid problems. */ |
| 252 | #define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuSSE|CpuSSE2|Cpu3dnow|CpuK6|CpuAthlon) |
| 253 | |
| 254 | /* the bits in opcode_modifier are used to generate the final opcode from |
| 255 | the base_opcode. These bits also are used to detect alternate forms of |
| 256 | the same instruction */ |
| 257 | unsigned int opcode_modifier; |
| 258 | |
| 259 | /* opcode_modifier bits: */ |
| 260 | #define W 0x1 /* set if operands can be words or dwords |
| 261 | encoded the canonical way */ |
| 262 | #define D 0x2 /* D = 0 if Reg --> Regmem; |
| 263 | D = 1 if Regmem --> Reg: MUST BE 0x2 */ |
| 264 | #define Modrm 0x4 |
| 265 | #define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */ |
| 266 | #define ShortForm 0x10 /* register is in low 3 bits of opcode */ |
| 267 | #define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */ |
| 268 | #define Jump 0x40 /* special case for jump insns. */ |
| 269 | #define JumpDword 0x80 /* call and jump */ |
| 270 | #define JumpByte 0x100 /* loop and jecxz */ |
| 271 | #define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */ |
| 272 | #define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */ |
| 273 | #define Seg2ShortForm 0x800 /* encoding of load segment reg insns */ |
| 274 | #define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */ |
| 275 | #define Size16 0x2000 /* needs size prefix if in 32-bit mode */ |
| 276 | #define Size32 0x4000 /* needs size prefix if in 16-bit mode */ |
| 277 | #define Size64 0x8000 /* needs size prefix if in 16-bit mode */ |
| 278 | #define IgnoreSize 0x10000 /* instruction ignores operand size prefix */ |
| 279 | #define DefaultSize 0x20000 /* default insn size depends on mode */ |
| 280 | #define No_bSuf 0x40000 /* b suffix on instruction illegal */ |
| 281 | #define No_wSuf 0x80000 /* w suffix on instruction illegal */ |
| 282 | #define No_lSuf 0x100000 /* l suffix on instruction illegal */ |
| 283 | #define No_sSuf 0x200000 /* s suffix on instruction illegal */ |
| 284 | #define No_qSuf 0x400000 /* q suffix on instruction illegal */ |
| 285 | #define No_xSuf 0x800000 /* x suffix on instruction illegal */ |
| 286 | #define FWait 0x1000000 /* instruction needs FWAIT */ |
| 287 | #define IsString 0x2000000 /* quick test for string instructions */ |
| 288 | #define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */ |
| 289 | #define IsPrefix 0x8000000 /* opcode is a prefix */ |
| 290 | #define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */ |
| 291 | #define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */ |
| 292 | #define Rex64 0x40000000 /* instruction require Rex64 prefix. */ |
| 293 | #define Ugh 0x80000000 /* deprecated fp insn, gets a warning */ |
| 294 | |
| 295 | /* operand_types[i] describes the type of operand i. This is made |
| 296 | by OR'ing together all of the possible type masks. (e.g. |
| 297 | 'operand_types[i] = Reg|Imm' specifies that operand i can be |
| 298 | either a register or an immediate operand. */ |
| 299 | unsigned int operand_types[3]; |
| 300 | |
| 301 | /* operand_types[i] bits */ |
| 302 | /* register */ |
| 303 | #define Reg8 0x1 /* 8 bit reg */ |
| 304 | #define Reg16 0x2 /* 16 bit reg */ |
| 305 | #define Reg32 0x4 /* 32 bit reg */ |
| 306 | #define Reg64 0x8 /* 64 bit reg */ |
| 307 | /* immediate */ |
| 308 | #define Imm8 0x10 /* 8 bit immediate */ |
| 309 | #define Imm8S 0x20 /* 8 bit immediate sign extended */ |
| 310 | #define Imm16 0x40 /* 16 bit immediate */ |
| 311 | #define Imm32 0x80 /* 32 bit immediate */ |
| 312 | #define Imm32S 0x100 /* 32 bit immediate sign extended */ |
| 313 | #define Imm64 0x200 /* 64 bit immediate */ |
| 314 | #define Imm1 0x400 /* 1 bit immediate */ |
| 315 | /* memory */ |
| 316 | #define BaseIndex 0x800 |
| 317 | /* Disp8,16,32 are used in different ways, depending on the |
| 318 | instruction. For jumps, they specify the size of the PC relative |
| 319 | displacement, for baseindex type instructions, they specify the |
| 320 | size of the offset relative to the base register, and for memory |
| 321 | offset instructions such as `mov 1234,%al' they specify the size of |
| 322 | the offset relative to the segment base. */ |
| 323 | #define Disp8 0x1000 /* 8 bit displacement */ |
| 324 | #define Disp16 0x2000 /* 16 bit displacement */ |
| 325 | #define Disp32 0x4000 /* 32 bit displacement */ |
| 326 | #define Disp32S 0x8000 /* 32 bit signed displacement */ |
| 327 | #define Disp64 0x10000 /* 64 bit displacement */ |
| 328 | /* specials */ |
| 329 | #define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */ |
| 330 | #define ShiftCount 0x40000 /* register to hold shift cound = cl */ |
| 331 | #define Control 0x80000 /* Control register */ |
| 332 | #define Debug 0x100000 /* Debug register */ |
| 333 | #define Test 0x200000 /* Test register */ |
| 334 | #define FloatReg 0x400000 /* Float register */ |
| 335 | #define FloatAcc 0x800000 /* Float stack top %st(0) */ |
| 336 | #define SReg2 0x1000000 /* 2 bit segment register */ |
| 337 | #define SReg3 0x2000000 /* 3 bit segment register */ |
| 338 | #define Acc 0x4000000 /* Accumulator %al or %ax or %eax */ |
| 339 | #define JumpAbsolute 0x8000000 |
| 340 | #define RegMMX 0x10000000 /* MMX register */ |
| 341 | #define RegXMM 0x20000000 /* XMM registers in PIII */ |
| 342 | #define EsSeg 0x40000000 /* String insn operand with fixed es segment */ |
| 343 | |
| 344 | /* InvMem is for instructions with a modrm byte that only allow a |
| 345 | general register encoding in the i.tm.mode and i.tm.regmem fields, |
| 346 | eg. control reg moves. They really ought to support a memory form, |
| 347 | but don't, so we add an InvMem flag to the register operand to |
| 348 | indicate that it should be encoded in the i.tm.regmem field. */ |
| 349 | #define InvMem 0x80000000 |
| 350 | |
| 351 | #define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */ |
| 352 | #define WordReg (Reg16|Reg32|Reg64) |
| 353 | #define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc) |
| 354 | #define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */ |
| 355 | #define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */ |
| 356 | #define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */ |
| 357 | #define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem) /* General memory */ |
| 358 | /* The following aliases are defined because the opcode table |
| 359 | carefully specifies the allowed memory types for each instruction. |
| 360 | At the moment we can only tell a memory reference size by the |
| 361 | instruction suffix, so there's not much point in defining Mem8, |
| 362 | Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use |
| 363 | the suffix directly to check memory operands. */ |
| 364 | #define LLongMem AnyMem /* 64 bits (or more) */ |
| 365 | #define LongMem AnyMem /* 32 bit memory ref */ |
| 366 | #define ShortMem AnyMem /* 16 bit memory ref */ |
| 367 | #define WordMem AnyMem /* 16 or 32 bit memory ref */ |
| 368 | #define ByteMem AnyMem /* 8 bit memory ref */ |
| 369 | } |
| 370 | template; |
| 371 | |
| 372 | /* |
| 373 | 'templates' is for grouping together 'template' structures for opcodes |
| 374 | of the same name. This is only used for storing the insns in the grand |
| 375 | ole hash table of insns. |
| 376 | The templates themselves start at START and range up to (but not including) |
| 377 | END. |
| 378 | */ |
| 379 | typedef struct |
| 380 | { |
| 381 | const template *start; |
| 382 | const template *end; |
| 383 | } |
| 384 | templates; |
| 385 | |
| 386 | /* these are for register name --> number & type hash lookup */ |
| 387 | typedef struct |
| 388 | { |
| 389 | char *reg_name; |
| 390 | unsigned int reg_type; |
| 391 | unsigned int reg_flags; |
| 392 | #define RegRex 0x1 /* Extended register. */ |
| 393 | #define RegRex64 0x2 /* Extended 8 bit register. */ |
| 394 | unsigned int reg_num; |
| 395 | } |
| 396 | reg_entry; |
| 397 | |
| 398 | typedef struct |
| 399 | { |
| 400 | char *seg_name; |
| 401 | unsigned int seg_prefix; |
| 402 | } |
| 403 | seg_entry; |
| 404 | |
| 405 | /* 386 operand encoding bytes: see 386 book for details of this. */ |
| 406 | typedef struct |
| 407 | { |
| 408 | unsigned int regmem; /* codes register or memory operand */ |
| 409 | unsigned int reg; /* codes register operand (or extended opcode) */ |
| 410 | unsigned int mode; /* how to interpret regmem & reg */ |
| 411 | } |
| 412 | modrm_byte; |
| 413 | |
| 414 | /* x86-64 extension prefix. */ |
| 415 | typedef int rex_byte; |
| 416 | #define REX_OPCODE 0x40 |
| 417 | |
| 418 | /* Indicates 64 bit operand size. */ |
| 419 | #define REX_MODE64 8 |
| 420 | /* High extension to reg field of modrm byte. */ |
| 421 | #define REX_EXTX 4 |
| 422 | /* High extension to SIB index field. */ |
| 423 | #define REX_EXTY 2 |
| 424 | /* High extension to base field of modrm or SIB, or reg field of opcode. */ |
| 425 | #define REX_EXTZ 1 |
| 426 | |
| 427 | /* 386 opcode byte to code indirect addressing. */ |
| 428 | typedef struct |
| 429 | { |
| 430 | unsigned base; |
| 431 | unsigned index; |
| 432 | unsigned scale; |
| 433 | } |
| 434 | sib_byte; |
| 435 | |
| 436 | /* x86 arch names and features */ |
| 437 | typedef struct |
| 438 | { |
| 439 | const char *name; /* arch name */ |
| 440 | unsigned int flags; /* cpu feature flags */ |
| 441 | } |
| 442 | arch_entry; |
| 443 | |
| 444 | /* The name of the global offset table generated by the compiler. Allow |
| 445 | this to be overridden if need be. */ |
| 446 | #ifndef GLOBAL_OFFSET_TABLE_NAME |
| 447 | #define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_" |
| 448 | #endif |
| 449 | |
| 450 | #ifndef LEX_AT |
| 451 | #define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES) |
| 452 | extern void x86_cons PARAMS ((expressionS *, int)); |
| 453 | |
| 454 | #define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP) |
| 455 | extern void x86_cons_fix_new |
| 456 | PARAMS ((fragS *, unsigned int, unsigned int, expressionS *)); |
| 457 | #endif |
| 458 | |
| 459 | #define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */ |
| 460 | |
| 461 | #ifdef BFD_ASSEMBLER |
| 462 | #define NO_RELOC BFD_RELOC_NONE |
| 463 | |
| 464 | void i386_validate_fix PARAMS ((struct fix *)); |
| 465 | #define TC_VALIDATE_FIX(FIX,SEGTYPE,SKIP) i386_validate_fix(FIX) |
| 466 | |
| 467 | #define tc_fix_adjustable(X) tc_i386_fix_adjustable(X) |
| 468 | extern int tc_i386_fix_adjustable PARAMS ((struct fix *)); |
| 469 | |
| 470 | /* Values passed to md_apply_fix3 don't include the symbol value. */ |
| 471 | #define MD_APPLY_SYM_VALUE(FIX) 0 |
| 472 | |
| 473 | /* ELF wants external syms kept, as does PE COFF. */ |
| 474 | #if defined (TE_PE) && defined (STRICT_PE_FORMAT) |
| 475 | #define EXTERN_FORCE_RELOC \ |
| 476 | (OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
| 477 | || OUTPUT_FLAVOR == bfd_target_coff_flavour) |
| 478 | #else |
| 479 | #define EXTERN_FORCE_RELOC \ |
| 480 | (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
| 481 | #endif |
| 482 | |
| 483 | /* This expression evaluates to true if the relocation is for a local |
| 484 | object for which we still want to do the relocation at runtime. |
| 485 | False if we are willing to perform this relocation while building |
| 486 | the .o file. GOTOFF does not need to be checked here because it is |
| 487 | not pcrel. I am not sure if some of the others are ever used with |
| 488 | pcrel, but it is easier to be safe than sorry. */ |
| 489 | |
| 490 | #define TC_FORCE_RELOCATION_LOCAL(FIX) \ |
| 491 | (!(FIX)->fx_pcrel \ |
| 492 | || (FIX)->fx_plt \ |
| 493 | || (FIX)->fx_r_type == BFD_RELOC_386_PLT32 \ |
| 494 | || (FIX)->fx_r_type == BFD_RELOC_386_GOT32 \ |
| 495 | || (FIX)->fx_r_type == BFD_RELOC_386_GOTPC \ |
| 496 | || TC_FORCE_RELOCATION (FIX)) |
| 497 | |
| 498 | #else /* ! BFD_ASSEMBLER */ |
| 499 | |
| 500 | #define NO_RELOC 0 |
| 501 | |
| 502 | #define TC_RVA_RELOC 7 |
| 503 | |
| 504 | /* Need this for PIC relocations */ |
| 505 | #define NEED_FX_R_TYPE |
| 506 | |
| 507 | #undef REVERSE_SORT_RELOCS |
| 508 | |
| 509 | /* For COFF. */ |
| 510 | #define TC_FORCE_RELOCATION(FIX) \ |
| 511 | ((FIX)->fx_r_type == 7 || generic_force_reloc (FIX)) |
| 512 | #endif /* ! BFD_ASSEMBLER */ |
| 513 | |
| 514 | #define md_operand(x) |
| 515 | |
| 516 | extern const struct relax_type md_relax_table[]; |
| 517 | #define TC_GENERIC_RELAX_TABLE md_relax_table |
| 518 | |
| 519 | #define md_do_align(n, fill, len, max, around) \ |
| 520 | if ((n) && !need_pass_2 \ |
| 521 | && (!(fill) || ((char)*(fill) == (char)0x90 && (len) == 1)) \ |
| 522 | && subseg_text_p (now_seg)) \ |
| 523 | { \ |
| 524 | frag_align_code ((n), (max)); \ |
| 525 | goto around; \ |
| 526 | } |
| 527 | |
| 528 | #define MAX_MEM_FOR_RS_ALIGN_CODE 15 |
| 529 | |
| 530 | extern void i386_align_code PARAMS ((fragS *, int)); |
| 531 | |
| 532 | #define HANDLE_ALIGN(fragP) \ |
| 533 | if (fragP->fr_type == rs_align_code) \ |
| 534 | i386_align_code (fragP, (fragP->fr_next->fr_address \ |
| 535 | - fragP->fr_address \ |
| 536 | - fragP->fr_fix)); |
| 537 | |
| 538 | void i386_print_statistics PARAMS ((FILE *)); |
| 539 | #define tc_print_statistics i386_print_statistics |
| 540 | |
| 541 | #define md_number_to_chars number_to_chars_littleendian |
| 542 | |
| 543 | #ifdef SCO_ELF |
| 544 | #define tc_init_after_args() sco_id () |
| 545 | extern void sco_id PARAMS ((void)); |
| 546 | #endif |
| 547 | |
| 548 | /* We want .cfi_* pseudo-ops for generating unwind info. */ |
| 549 | #define TARGET_USE_CFIPOP |
| 550 | #ifdef TARGET_USE_CFIPOP |
| 551 | |
| 552 | #define tc_cfi_init() tc_x86_cfi_init () |
| 553 | extern void tc_x86_cfi_init PARAMS ((void)); |
| 554 | |
| 555 | #define tc_regname_to_dw2regnum tc_x86_regname_to_dw2regnum |
| 556 | extern unsigned long tc_x86_regname_to_dw2regnum PARAMS ((const char *regname)); |
| 557 | |
| 558 | #define tc_cfi_frame_initial_instructions tc_x86_frame_initial_instructions |
| 559 | extern void tc_x86_frame_initial_instructions PARAMS ((void)); |
| 560 | |
| 561 | #endif /* TARGET_USE_CFIPOP */ |
| 562 | |
| 563 | #endif /* TC_I386 */ |