| 1 | /* tc-m32r.c -- Assembler for the Renesas M32R. |
| 2 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 |
| 3 | Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GAS, the GNU Assembler. |
| 6 | |
| 7 | GAS is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 2, or (at your option) |
| 10 | any later version. |
| 11 | |
| 12 | GAS is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with GAS; see the file COPYING. If not, write to |
| 19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
| 20 | Boston, MA 02111-1307, USA. */ |
| 21 | |
| 22 | #include <stdio.h> |
| 23 | #include "as.h" |
| 24 | #include "safe-ctype.h" |
| 25 | #include "subsegs.h" |
| 26 | #include "symcat.h" |
| 27 | #include "opcodes/m32r-desc.h" |
| 28 | #include "opcodes/m32r-opc.h" |
| 29 | #include "cgen.h" |
| 30 | #include "elf/m32r.h" |
| 31 | |
| 32 | /* Linked list of symbols that are debugging symbols to be defined as the |
| 33 | beginning of the current instruction. */ |
| 34 | typedef struct sym_link |
| 35 | { |
| 36 | struct sym_link *next; |
| 37 | symbolS *symbol; |
| 38 | } sym_linkS; |
| 39 | |
| 40 | static sym_linkS *debug_sym_link = (sym_linkS *) 0; |
| 41 | |
| 42 | /* Structure to hold all of the different components describing |
| 43 | an individual instruction. */ |
| 44 | typedef struct |
| 45 | { |
| 46 | const CGEN_INSN *insn; |
| 47 | const CGEN_INSN *orig_insn; |
| 48 | CGEN_FIELDS fields; |
| 49 | #if CGEN_INT_INSN_P |
| 50 | CGEN_INSN_INT buffer[1]; |
| 51 | #define INSN_VALUE(buf) (*(buf)) |
| 52 | #else |
| 53 | unsigned char buffer[CGEN_MAX_INSN_SIZE]; |
| 54 | #define INSN_VALUE(buf) (buf) |
| 55 | #endif |
| 56 | char *addr; |
| 57 | fragS *frag; |
| 58 | int num_fixups; |
| 59 | fixS *fixups[GAS_CGEN_MAX_FIXUPS]; |
| 60 | int indices[MAX_OPERAND_INSTANCES]; |
| 61 | sym_linkS *debug_sym_link; |
| 62 | } |
| 63 | m32r_insn; |
| 64 | |
| 65 | /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit |
| 66 | boundary (i.e. was the first of two 16 bit insns). */ |
| 67 | static m32r_insn prev_insn; |
| 68 | |
| 69 | /* Non-zero if we've seen a relaxable insn since the last 32 bit |
| 70 | alignment request. */ |
| 71 | static int seen_relaxable_p = 0; |
| 72 | |
| 73 | /* Non-zero if -relax specified, in which case sufficient relocs are output |
| 74 | for the linker to do relaxing. |
| 75 | We do simple forms of relaxing internally, but they are always done. |
| 76 | This flag does not apply to them. */ |
| 77 | static int m32r_relax; |
| 78 | |
| 79 | #if 0 |
| 80 | /* Not supported yet. */ |
| 81 | /* If non-NULL, pointer to cpu description file to read. |
| 82 | This allows runtime additions to the assembler. */ |
| 83 | static const char *m32r_cpu_desc; |
| 84 | #endif |
| 85 | |
| 86 | /* Non-zero if warn when a high/shigh reloc has no matching low reloc. |
| 87 | Each high/shigh reloc must be paired with it's low cousin in order to |
| 88 | properly calculate the addend in a relocatable link (since there is a |
| 89 | potential carry from the low to the high/shigh). |
| 90 | This option is off by default though for user-written assembler code it |
| 91 | might make sense to make the default be on (i.e. have gcc pass a flag |
| 92 | to turn it off). This warning must not be on for GCC created code as |
| 93 | optimization may delete the low but not the high/shigh (at least we |
| 94 | shouldn't assume or require it to). */ |
| 95 | static int warn_unmatched_high = 0; |
| 96 | |
| 97 | /* 1 if -m32rx has been specified, in which case support for |
| 98 | the extended M32RX instruction set should be enabled. |
| 99 | 2 if -m32r2 has been specified, in which case support for |
| 100 | the extended M32R2 instruction set should be enabled. */ |
| 101 | static int enable_m32rx = 0; /* Default to M32R. */ |
| 102 | |
| 103 | /* Non-zero if -m32rx -hidden has been specified, in which case support for |
| 104 | the special M32RX instruction set should be enabled. */ |
| 105 | static int enable_special = 0; |
| 106 | |
| 107 | /* Non-zero if -bitinst has been specified, in which case support |
| 108 | for extended M32R bit-field instruction set should be enabled. */ |
| 109 | static int enable_special_m32r = 0; |
| 110 | |
| 111 | /* Non-zero if -float has been specified, in which case support for |
| 112 | extended M32R floating point instruction set should be enabled. */ |
| 113 | static int enable_special_float = 0; |
| 114 | |
| 115 | /* Non-zero if the programmer should be warned when an explicit parallel |
| 116 | instruction might have constraint violations. */ |
| 117 | static int warn_explicit_parallel_conflicts = 1; |
| 118 | |
| 119 | /* Non-zero if the programmer should receive an error message when an |
| 120 | explicit parallel instruction might have constraint violations. */ |
| 121 | static int error_explicit_parallel_conflicts = 1; |
| 122 | |
| 123 | /* Non-zero if insns can be made parallel. */ |
| 124 | static int use_parallel = 1; |
| 125 | |
| 126 | /* Non-zero if optimizations should be performed. */ |
| 127 | static int optimize; |
| 128 | |
| 129 | /* m32r er_flags. */ |
| 130 | static int m32r_flags = 0; |
| 131 | |
| 132 | /* Stuff for .scomm symbols. */ |
| 133 | static segT sbss_section; |
| 134 | static asection scom_section; |
| 135 | static asymbol scom_symbol; |
| 136 | |
| 137 | const char comment_chars[] = ";"; |
| 138 | const char line_comment_chars[] = "#"; |
| 139 | const char line_separator_chars[] = "!"; |
| 140 | const char EXP_CHARS[] = "eE"; |
| 141 | const char FLT_CHARS[] = "dD"; |
| 142 | |
| 143 | /* Relocations against symbols are done in two |
| 144 | parts, with a HI relocation and a LO relocation. Each relocation |
| 145 | has only 16 bits of space to store an addend. This means that in |
| 146 | order for the linker to handle carries correctly, it must be able |
| 147 | to locate both the HI and the LO relocation. This means that the |
| 148 | relocations must appear in order in the relocation table. |
| 149 | |
| 150 | In order to implement this, we keep track of each unmatched HI |
| 151 | relocation. We then sort them so that they immediately precede the |
| 152 | corresponding LO relocation. */ |
| 153 | |
| 154 | struct m32r_hi_fixup |
| 155 | { |
| 156 | /* Next HI fixup. */ |
| 157 | struct m32r_hi_fixup *next; |
| 158 | |
| 159 | /* This fixup. */ |
| 160 | fixS *fixp; |
| 161 | |
| 162 | /* The section this fixup is in. */ |
| 163 | segT seg; |
| 164 | }; |
| 165 | |
| 166 | /* The list of unmatched HI relocs. */ |
| 167 | |
| 168 | static struct m32r_hi_fixup *m32r_hi_fixup_list; |
| 169 | \f |
| 170 | struct { |
| 171 | enum bfd_architecture bfd_mach; |
| 172 | int mach_flags; |
| 173 | } mach_table[] = |
| 174 | { |
| 175 | { bfd_mach_m32r, (1<<MACH_M32R) }, |
| 176 | { bfd_mach_m32rx, (1<<MACH_M32RX) }, |
| 177 | { bfd_mach_m32r2, (1<<MACH_M32R2) } |
| 178 | }; |
| 179 | |
| 180 | static void allow_m32rx (int); |
| 181 | |
| 182 | static void |
| 183 | allow_m32rx (int on) |
| 184 | { |
| 185 | enable_m32rx = on; |
| 186 | |
| 187 | if (stdoutput != NULL) |
| 188 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach_table[on].bfd_mach); |
| 189 | |
| 190 | if (gas_cgen_cpu_desc != NULL) |
| 191 | gas_cgen_cpu_desc->machs = mach_table[on].mach_flags; |
| 192 | } |
| 193 | \f |
| 194 | #define M32R_SHORTOPTS "O" |
| 195 | |
| 196 | const char *md_shortopts = M32R_SHORTOPTS; |
| 197 | |
| 198 | struct option md_longopts[] = |
| 199 | { |
| 200 | #define OPTION_M32R (OPTION_MD_BASE) |
| 201 | #define OPTION_M32RX (OPTION_M32R + 1) |
| 202 | #define OPTION_M32R2 (OPTION_M32RX + 1) |
| 203 | #define OPTION_BIG (OPTION_M32R2 + 1) |
| 204 | #define OPTION_LITTLE (OPTION_BIG + 1) |
| 205 | #define OPTION_PARALLEL (OPTION_LITTLE + 1) |
| 206 | #define OPTION_NO_PARALLEL (OPTION_PARALLEL + 1) |
| 207 | #define OPTION_WARN_PARALLEL (OPTION_NO_PARALLEL + 1) |
| 208 | #define OPTION_NO_WARN_PARALLEL (OPTION_WARN_PARALLEL + 1) |
| 209 | #define OPTION_ERROR_PARALLEL (OPTION_NO_WARN_PARALLEL + 1) |
| 210 | #define OPTION_NO_ERROR_PARALLEL (OPTION_ERROR_PARALLEL + 1) |
| 211 | #define OPTION_SPECIAL (OPTION_NO_ERROR_PARALLEL + 1) |
| 212 | #define OPTION_SPECIAL_M32R (OPTION_SPECIAL + 1) |
| 213 | #define OPTION_SPECIAL_FLOAT (OPTION_SPECIAL_M32R + 1) |
| 214 | #define OPTION_WARN_UNMATCHED (OPTION_SPECIAL_FLOAT + 1) |
| 215 | #define OPTION_NO_WARN_UNMATCHED (OPTION_WARN_UNMATCHED + 1) |
| 216 | {"m32r", no_argument, NULL, OPTION_M32R}, |
| 217 | {"m32rx", no_argument, NULL, OPTION_M32RX}, |
| 218 | {"m32r2", no_argument, NULL, OPTION_M32R2}, |
| 219 | {"big", no_argument, NULL, OPTION_BIG}, |
| 220 | {"little", no_argument, NULL, OPTION_LITTLE}, |
| 221 | {"EB", no_argument, NULL, OPTION_BIG}, |
| 222 | {"EL", no_argument, NULL, OPTION_LITTLE}, |
| 223 | {"parallel", no_argument, NULL, OPTION_PARALLEL}, |
| 224 | {"no-parallel", no_argument, NULL, OPTION_NO_PARALLEL}, |
| 225 | {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL}, |
| 226 | {"Wp", no_argument, NULL, OPTION_WARN_PARALLEL}, |
| 227 | {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, |
| 228 | {"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, |
| 229 | {"error-explicit-parallel-conflicts", no_argument, NULL, OPTION_ERROR_PARALLEL}, |
| 230 | {"Ep", no_argument, NULL, OPTION_ERROR_PARALLEL}, |
| 231 | {"no-error-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_ERROR_PARALLEL}, |
| 232 | {"Enp", no_argument, NULL, OPTION_NO_ERROR_PARALLEL}, |
| 233 | {"hidden", no_argument, NULL, OPTION_SPECIAL}, |
| 234 | {"bitinst", no_argument, NULL, OPTION_SPECIAL_M32R}, |
| 235 | {"float", no_argument, NULL, OPTION_SPECIAL_FLOAT}, |
| 236 | /* Sigh. I guess all warnings must now have both variants. */ |
| 237 | {"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED}, |
| 238 | {"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED}, |
| 239 | {"no-warn-unmatched-high", no_argument, NULL, OPTION_NO_WARN_UNMATCHED}, |
| 240 | {"Wnuh", no_argument, NULL, OPTION_NO_WARN_UNMATCHED}, |
| 241 | |
| 242 | #if 0 |
| 243 | /* Not supported yet. */ |
| 244 | #define OPTION_RELAX (OPTION_NO_WARN_UNMATCHED + 1) |
| 245 | #define OPTION_CPU_DESC (OPTION_RELAX + 1) |
| 246 | {"relax", no_argument, NULL, OPTION_RELAX}, |
| 247 | {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC}, |
| 248 | #endif |
| 249 | {NULL, no_argument, NULL, 0} |
| 250 | }; |
| 251 | |
| 252 | size_t md_longopts_size = sizeof (md_longopts); |
| 253 | |
| 254 | static void little (int); |
| 255 | static int parallel (void); |
| 256 | |
| 257 | static void |
| 258 | little (int on) |
| 259 | { |
| 260 | target_big_endian = ! on; |
| 261 | } |
| 262 | |
| 263 | /* Use parallel execution. */ |
| 264 | |
| 265 | static int |
| 266 | parallel (void) |
| 267 | { |
| 268 | if (! enable_m32rx) |
| 269 | return 0; |
| 270 | |
| 271 | if (use_parallel == 1) |
| 272 | return 1; |
| 273 | |
| 274 | return 0; |
| 275 | } |
| 276 | |
| 277 | int |
| 278 | md_parse_option (c, arg) |
| 279 | int c; |
| 280 | char *arg ATTRIBUTE_UNUSED; |
| 281 | { |
| 282 | switch (c) |
| 283 | { |
| 284 | case 'O': |
| 285 | optimize = 1; |
| 286 | use_parallel = 1; |
| 287 | break; |
| 288 | |
| 289 | case OPTION_M32R: |
| 290 | allow_m32rx (0); |
| 291 | break; |
| 292 | |
| 293 | case OPTION_M32RX: |
| 294 | allow_m32rx (1); |
| 295 | break; |
| 296 | |
| 297 | case OPTION_M32R2: |
| 298 | allow_m32rx (2); |
| 299 | enable_special = 1; |
| 300 | enable_special_m32r = 1; |
| 301 | break; |
| 302 | |
| 303 | case OPTION_BIG: |
| 304 | target_big_endian = 1; |
| 305 | break; |
| 306 | |
| 307 | case OPTION_LITTLE: |
| 308 | target_big_endian = 0; |
| 309 | break; |
| 310 | |
| 311 | case OPTION_PARALLEL: |
| 312 | use_parallel = 1; |
| 313 | break; |
| 314 | |
| 315 | case OPTION_NO_PARALLEL: |
| 316 | use_parallel = 0; |
| 317 | break; |
| 318 | |
| 319 | case OPTION_WARN_PARALLEL: |
| 320 | warn_explicit_parallel_conflicts = 1; |
| 321 | error_explicit_parallel_conflicts = 0; |
| 322 | break; |
| 323 | |
| 324 | case OPTION_NO_WARN_PARALLEL: |
| 325 | warn_explicit_parallel_conflicts = 0; |
| 326 | error_explicit_parallel_conflicts = 0; |
| 327 | break; |
| 328 | |
| 329 | case OPTION_ERROR_PARALLEL: |
| 330 | warn_explicit_parallel_conflicts = 1; |
| 331 | error_explicit_parallel_conflicts = 1; |
| 332 | break; |
| 333 | |
| 334 | case OPTION_NO_ERROR_PARALLEL: |
| 335 | error_explicit_parallel_conflicts = 0; |
| 336 | warn_explicit_parallel_conflicts = 0; |
| 337 | break; |
| 338 | |
| 339 | case OPTION_SPECIAL: |
| 340 | if (enable_m32rx) |
| 341 | enable_special = 1; |
| 342 | else |
| 343 | { |
| 344 | /* Pretend that we do not recognise this option. */ |
| 345 | as_bad (_("Unrecognised option: -hidden")); |
| 346 | return 0; |
| 347 | } |
| 348 | break; |
| 349 | |
| 350 | case OPTION_SPECIAL_M32R: |
| 351 | enable_special_m32r = 1; |
| 352 | break; |
| 353 | |
| 354 | case OPTION_SPECIAL_FLOAT: |
| 355 | enable_special_float = 1; |
| 356 | break; |
| 357 | |
| 358 | case OPTION_WARN_UNMATCHED: |
| 359 | warn_unmatched_high = 1; |
| 360 | break; |
| 361 | |
| 362 | case OPTION_NO_WARN_UNMATCHED: |
| 363 | warn_unmatched_high = 0; |
| 364 | break; |
| 365 | |
| 366 | #if 0 |
| 367 | /* Not supported yet. */ |
| 368 | case OPTION_RELAX: |
| 369 | m32r_relax = 1; |
| 370 | break; |
| 371 | case OPTION_CPU_DESC: |
| 372 | m32r_cpu_desc = arg; |
| 373 | break; |
| 374 | #endif |
| 375 | |
| 376 | default: |
| 377 | return 0; |
| 378 | } |
| 379 | |
| 380 | return 1; |
| 381 | } |
| 382 | |
| 383 | void |
| 384 | md_show_usage (stream) |
| 385 | FILE *stream; |
| 386 | { |
| 387 | fprintf (stream, _(" M32R specific command line options:\n")); |
| 388 | |
| 389 | fprintf (stream, _("\ |
| 390 | -m32r disable support for the m32rx instruction set\n")); |
| 391 | fprintf (stream, _("\ |
| 392 | -m32rx support the extended m32rx instruction set\n")); |
| 393 | fprintf (stream, _("\ |
| 394 | -m32r2 support the extended m32r2 instruction set\n")); |
| 395 | fprintf (stream, _("\ |
| 396 | -EL,-little produce little endian code and data\n")); |
| 397 | fprintf (stream, _("\ |
| 398 | -EB,-big produce big endian code and data\n")); |
| 399 | fprintf (stream, _("\ |
| 400 | -parallel try to combine instructions in parallel\n")); |
| 401 | fprintf (stream, _("\ |
| 402 | -no-parallel disable -parallel\n")); |
| 403 | fprintf (stream, _("\ |
| 404 | -O try to optimize code. Implies -parallel\n")); |
| 405 | |
| 406 | fprintf (stream, _("\ |
| 407 | -warn-explicit-parallel-conflicts warn when parallel instructions\n")); |
| 408 | fprintf (stream, _("\ |
| 409 | violate contraints\n")); |
| 410 | fprintf (stream, _("\ |
| 411 | -no-warn-explicit-parallel-conflicts do not warn when parallel\n")); |
| 412 | fprintf (stream, _("\ |
| 413 | instructions violate contraints\n")); |
| 414 | fprintf (stream, _("\ |
| 415 | -Wp synonym for -warn-explicit-parallel-conflicts\n")); |
| 416 | fprintf (stream, _("\ |
| 417 | -Wnp synonym for -no-warn-explicit-parallel-conflicts\n")); |
| 418 | fprintf (stream, _("\ |
| 419 | -error-explicit-parallel-conflicts error when parallel instructions\n")); |
| 420 | fprintf (stream, _("\ |
| 421 | violate contraints\n")); |
| 422 | fprintf (stream, _("\ |
| 423 | -no-error-explicit-parallel-conflicts do not error when parallel\n")); |
| 424 | fprintf (stream, _("\ |
| 425 | instructions violate contraints\n")); |
| 426 | fprintf (stream, _("\ |
| 427 | -Ep synonym for -error-explicit-parallel-conflicts\n")); |
| 428 | fprintf (stream, _("\ |
| 429 | -Enp synonym for -no-error-explicit-parallel-conflicts\n")); |
| 430 | |
| 431 | fprintf (stream, _("\ |
| 432 | -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n")); |
| 433 | fprintf (stream, _("\ |
| 434 | -no-warn-unmatched-high do not warn about missing low relocs\n")); |
| 435 | fprintf (stream, _("\ |
| 436 | -Wuh synonym for -warn-unmatched-high\n")); |
| 437 | fprintf (stream, _("\ |
| 438 | -Wnuh synonym for -no-warn-unmatched-high\n")); |
| 439 | |
| 440 | #if 0 |
| 441 | fprintf (stream, _("\ |
| 442 | -relax create linker relaxable code\n")); |
| 443 | fprintf (stream, _("\ |
| 444 | -cpu-desc provide runtime cpu description file\n")); |
| 445 | #endif |
| 446 | } |
| 447 | |
| 448 | static void fill_insn PARAMS ((int)); |
| 449 | static void m32r_scomm PARAMS ((int)); |
| 450 | static void debug_sym PARAMS ((int)); |
| 451 | static void expand_debug_syms PARAMS ((sym_linkS *, int)); |
| 452 | |
| 453 | /* Set by md_assemble for use by m32r_fill_insn. */ |
| 454 | static subsegT prev_subseg; |
| 455 | static segT prev_seg; |
| 456 | |
| 457 | /* The target specific pseudo-ops which we support. */ |
| 458 | const pseudo_typeS md_pseudo_table[] = |
| 459 | { |
| 460 | { "word", cons, 4 }, |
| 461 | { "fillinsn", fill_insn, 0 }, |
| 462 | { "scomm", m32r_scomm, 0 }, |
| 463 | { "debugsym", debug_sym, 0 }, |
| 464 | { "m32r", allow_m32rx, 0 }, |
| 465 | { "m32rx", allow_m32rx, 1 }, |
| 466 | { "m32r2", allow_m32rx, 2 }, |
| 467 | { "little", little, 1 }, |
| 468 | { "big", little, 0 }, |
| 469 | { NULL, NULL, 0 } |
| 470 | }; |
| 471 | |
| 472 | /* FIXME: Should be machine generated. */ |
| 473 | #define NOP_INSN 0x7000 |
| 474 | #define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot. */ |
| 475 | |
| 476 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
| 477 | of an rs_align_code fragment. */ |
| 478 | |
| 479 | void |
| 480 | m32r_handle_align (fragp) |
| 481 | fragS *fragp; |
| 482 | { |
| 483 | static const unsigned char nop_pattern[] = { 0xf0, 0x00 }; |
| 484 | static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 }; |
| 485 | |
| 486 | int bytes, fix; |
| 487 | char *p; |
| 488 | |
| 489 | if (fragp->fr_type != rs_align_code) |
| 490 | return; |
| 491 | |
| 492 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
| 493 | p = fragp->fr_literal + fragp->fr_fix; |
| 494 | fix = 0; |
| 495 | |
| 496 | if (bytes & 1) |
| 497 | { |
| 498 | fix = 1; |
| 499 | *p++ = 0; |
| 500 | bytes--; |
| 501 | } |
| 502 | |
| 503 | if (bytes & 2) |
| 504 | { |
| 505 | memcpy (p, nop_pattern, 2); |
| 506 | p += 2; |
| 507 | bytes -= 2; |
| 508 | fix += 2; |
| 509 | } |
| 510 | |
| 511 | memcpy (p, multi_nop_pattern, 4); |
| 512 | |
| 513 | fragp->fr_fix += fix; |
| 514 | fragp->fr_var = 4; |
| 515 | } |
| 516 | |
| 517 | /* If the last instruction was the first of 2 16 bit insns, |
| 518 | output a nop to move the PC to a 32 bit boundary. |
| 519 | |
| 520 | This is done via an alignment specification since branch relaxing |
| 521 | may make it unnecessary. |
| 522 | |
| 523 | Internally, we need to output one of these each time a 32 bit insn is |
| 524 | seen after an insn that is relaxable. */ |
| 525 | |
| 526 | static void |
| 527 | fill_insn (ignore) |
| 528 | int ignore ATTRIBUTE_UNUSED; |
| 529 | { |
| 530 | frag_align_code (2, 0); |
| 531 | prev_insn.insn = NULL; |
| 532 | seen_relaxable_p = 0; |
| 533 | } |
| 534 | |
| 535 | /* Record the symbol so that when we output the insn, we can create |
| 536 | a symbol that is at the start of the instruction. This is used |
| 537 | to emit the label for the start of a breakpoint without causing |
| 538 | the assembler to emit a NOP if the previous instruction was a |
| 539 | 16 bit instruction. */ |
| 540 | |
| 541 | static void |
| 542 | debug_sym (ignore) |
| 543 | int ignore ATTRIBUTE_UNUSED; |
| 544 | { |
| 545 | register char *name; |
| 546 | register char delim; |
| 547 | register char *end_name; |
| 548 | register symbolS *symbolP; |
| 549 | register sym_linkS *link; |
| 550 | |
| 551 | name = input_line_pointer; |
| 552 | delim = get_symbol_end (); |
| 553 | end_name = input_line_pointer; |
| 554 | |
| 555 | if ((symbolP = symbol_find (name)) == NULL |
| 556 | && (symbolP = md_undefined_symbol (name)) == NULL) |
| 557 | { |
| 558 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); |
| 559 | } |
| 560 | |
| 561 | symbol_table_insert (symbolP); |
| 562 | if (S_IS_DEFINED (symbolP) && S_GET_SEGMENT (symbolP) != reg_section) |
| 563 | /* xgettext:c-format */ |
| 564 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); |
| 565 | |
| 566 | else |
| 567 | { |
| 568 | link = (sym_linkS *) xmalloc (sizeof (sym_linkS)); |
| 569 | link->symbol = symbolP; |
| 570 | link->next = debug_sym_link; |
| 571 | debug_sym_link = link; |
| 572 | symbol_get_obj (symbolP)->local = 1; |
| 573 | } |
| 574 | |
| 575 | *end_name = delim; |
| 576 | demand_empty_rest_of_line (); |
| 577 | } |
| 578 | |
| 579 | /* Second pass to expanding the debug symbols, go through linked |
| 580 | list of symbols and reassign the address. */ |
| 581 | |
| 582 | static void |
| 583 | expand_debug_syms (syms, align) |
| 584 | sym_linkS *syms; |
| 585 | int align; |
| 586 | { |
| 587 | char *save_input_line = input_line_pointer; |
| 588 | sym_linkS *next_syms; |
| 589 | |
| 590 | if (!syms) |
| 591 | return; |
| 592 | |
| 593 | (void) frag_align_code (align, 0); |
| 594 | for (; syms != (sym_linkS *) 0; syms = next_syms) |
| 595 | { |
| 596 | symbolS *symbolP = syms->symbol; |
| 597 | next_syms = syms->next; |
| 598 | input_line_pointer = ".\n"; |
| 599 | pseudo_set (symbolP); |
| 600 | free ((char *) syms); |
| 601 | } |
| 602 | |
| 603 | input_line_pointer = save_input_line; |
| 604 | } |
| 605 | |
| 606 | void |
| 607 | m32r_flush_pending_output() |
| 608 | { |
| 609 | if (debug_sym_link) |
| 610 | { |
| 611 | expand_debug_syms (debug_sym_link, 1); |
| 612 | debug_sym_link = (sym_linkS *) 0; |
| 613 | } |
| 614 | } |
| 615 | |
| 616 | /* Cover function to fill_insn called after a label and at end of assembly. |
| 617 | The result is always 1: we're called in a conditional to see if the |
| 618 | current line is a label. */ |
| 619 | |
| 620 | int |
| 621 | m32r_fill_insn (done) |
| 622 | int done; |
| 623 | { |
| 624 | if (prev_seg != NULL) |
| 625 | { |
| 626 | segT seg = now_seg; |
| 627 | subsegT subseg = now_subseg; |
| 628 | |
| 629 | subseg_set (prev_seg, prev_subseg); |
| 630 | |
| 631 | fill_insn (0); |
| 632 | |
| 633 | subseg_set (seg, subseg); |
| 634 | } |
| 635 | |
| 636 | if (done && debug_sym_link) |
| 637 | { |
| 638 | expand_debug_syms (debug_sym_link, 1); |
| 639 | debug_sym_link = (sym_linkS *) 0; |
| 640 | } |
| 641 | |
| 642 | return 1; |
| 643 | } |
| 644 | \f |
| 645 | /* The default target format to use. */ |
| 646 | |
| 647 | const char * |
| 648 | m32r_target_format () |
| 649 | { |
| 650 | #ifdef TE_LINUX |
| 651 | if (target_big_endian) |
| 652 | return "elf32-m32r-linux"; |
| 653 | else |
| 654 | return "elf32-m32rle-linux"; |
| 655 | #else |
| 656 | if (target_big_endian) |
| 657 | return "elf32-m32r"; |
| 658 | else |
| 659 | return "elf32-m32rle"; |
| 660 | #endif |
| 661 | } |
| 662 | |
| 663 | void |
| 664 | md_begin () |
| 665 | { |
| 666 | flagword applicable; |
| 667 | segT seg; |
| 668 | subsegT subseg; |
| 669 | |
| 670 | /* Initialize the `cgen' interface. */ |
| 671 | |
| 672 | /* Set the machine number and endian. */ |
| 673 | gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0, |
| 674 | CGEN_CPU_OPEN_ENDIAN, |
| 675 | (target_big_endian ? |
| 676 | CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE), |
| 677 | CGEN_CPU_OPEN_END); |
| 678 | m32r_cgen_init_asm (gas_cgen_cpu_desc); |
| 679 | |
| 680 | /* The operand instance table is used during optimization to determine |
| 681 | which insns can be executed in parallel. It is also used to give |
| 682 | warnings regarding operand interference in parallel insns. */ |
| 683 | m32r_cgen_init_opinst_table (gas_cgen_cpu_desc); |
| 684 | |
| 685 | /* This is a callback from cgen to gas to parse operands. */ |
| 686 | cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand); |
| 687 | |
| 688 | #if 0 |
| 689 | /* Not supported yet. */ |
| 690 | /* If a runtime cpu description file was provided, parse it. */ |
| 691 | if (m32r_cpu_desc != NULL) |
| 692 | { |
| 693 | const char *errmsg; |
| 694 | |
| 695 | errmsg = cgen_read_cpu_file (gas_cgen_cpu_desc, m32r_cpu_desc); |
| 696 | if (errmsg != NULL) |
| 697 | as_bad ("%s: %s", m32r_cpu_desc, errmsg); |
| 698 | } |
| 699 | #endif |
| 700 | |
| 701 | /* Save the current subseg so we can restore it [it's the default one and |
| 702 | we don't want the initial section to be .sbss]. */ |
| 703 | seg = now_seg; |
| 704 | subseg = now_subseg; |
| 705 | |
| 706 | /* The sbss section is for local .scomm symbols. */ |
| 707 | sbss_section = subseg_new (".sbss", 0); |
| 708 | |
| 709 | /* This is copied from perform_an_assembly_pass. */ |
| 710 | applicable = bfd_applicable_section_flags (stdoutput); |
| 711 | bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC); |
| 712 | |
| 713 | #if 0 |
| 714 | /* What does this do? [see perform_an_assembly_pass] */ |
| 715 | seg_info (bss_section)->bss = 1; |
| 716 | #endif |
| 717 | |
| 718 | subseg_set (seg, subseg); |
| 719 | |
| 720 | /* We must construct a fake section similar to bfd_com_section |
| 721 | but with the name .scommon. */ |
| 722 | scom_section = bfd_com_section; |
| 723 | scom_section.name = ".scommon"; |
| 724 | scom_section.output_section = &scom_section; |
| 725 | scom_section.symbol = &scom_symbol; |
| 726 | scom_section.symbol_ptr_ptr = &scom_section.symbol; |
| 727 | scom_symbol = *bfd_com_section.symbol; |
| 728 | scom_symbol.name = ".scommon"; |
| 729 | scom_symbol.section = &scom_section; |
| 730 | |
| 731 | allow_m32rx (enable_m32rx); |
| 732 | |
| 733 | gas_cgen_initialize_saved_fixups_array (); |
| 734 | } |
| 735 | |
| 736 | #define OPERAND_IS_COND_BIT(operand, indices, index) \ |
| 737 | ((operand)->hw_type == HW_H_COND \ |
| 738 | || ((operand)->hw_type == HW_H_PSW) \ |
| 739 | || ((operand)->hw_type == HW_H_CR \ |
| 740 | && (indices [index] == 0 || indices [index] == 1))) |
| 741 | |
| 742 | /* Returns true if an output of instruction 'a' is referenced by an operand |
| 743 | of instruction 'b'. If 'check_outputs' is true then b's outputs are |
| 744 | checked, otherwise its inputs are examined. */ |
| 745 | |
| 746 | static int first_writes_to_seconds_operands |
| 747 | PARAMS ((m32r_insn *, m32r_insn *, const int)); |
| 748 | |
| 749 | static int |
| 750 | first_writes_to_seconds_operands (a, b, check_outputs) |
| 751 | m32r_insn *a; |
| 752 | m32r_insn *b; |
| 753 | const int check_outputs; |
| 754 | { |
| 755 | const CGEN_OPINST *a_operands = CGEN_INSN_OPERANDS (a->insn); |
| 756 | const CGEN_OPINST *b_ops = CGEN_INSN_OPERANDS (b->insn); |
| 757 | int a_index; |
| 758 | |
| 759 | /* If at least one of the instructions takes no operands, then there is |
| 760 | nothing to check. There really are instructions without operands, |
| 761 | eg 'nop'. */ |
| 762 | if (a_operands == NULL || b_ops == NULL) |
| 763 | return 0; |
| 764 | |
| 765 | /* Scan the operand list of 'a' looking for an output operand. */ |
| 766 | for (a_index = 0; |
| 767 | a_operands->type != CGEN_OPINST_END; |
| 768 | a_index ++, a_operands ++) |
| 769 | { |
| 770 | if (a_operands->type == CGEN_OPINST_OUTPUT) |
| 771 | { |
| 772 | int b_index; |
| 773 | const CGEN_OPINST *b_operands = b_ops; |
| 774 | |
| 775 | /* Special Case: |
| 776 | The Condition bit 'C' is a shadow of the CBR register (control |
| 777 | register 1) and also a shadow of bit 31 of the program status |
| 778 | word (control register 0). For now this is handled here, rather |
| 779 | than by cgen.... */ |
| 780 | |
| 781 | if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index)) |
| 782 | { |
| 783 | /* Scan operand list of 'b' looking for another reference to the |
| 784 | condition bit, which goes in the right direction. */ |
| 785 | for (b_index = 0; |
| 786 | b_operands->type != CGEN_OPINST_END; |
| 787 | b_index++, b_operands++) |
| 788 | { |
| 789 | if ((b_operands->type |
| 790 | == (check_outputs |
| 791 | ? CGEN_OPINST_OUTPUT |
| 792 | : CGEN_OPINST_INPUT)) |
| 793 | && OPERAND_IS_COND_BIT (b_operands, b->indices, b_index)) |
| 794 | return 1; |
| 795 | } |
| 796 | } |
| 797 | else |
| 798 | { |
| 799 | /* Scan operand list of 'b' looking for an operand that |
| 800 | references the same hardware element, and which goes in the |
| 801 | right direction. */ |
| 802 | for (b_index = 0; |
| 803 | b_operands->type != CGEN_OPINST_END; |
| 804 | b_index++, b_operands++) |
| 805 | { |
| 806 | if ((b_operands->type |
| 807 | == (check_outputs |
| 808 | ? CGEN_OPINST_OUTPUT |
| 809 | : CGEN_OPINST_INPUT)) |
| 810 | && (b_operands->hw_type == a_operands->hw_type) |
| 811 | && (a->indices[a_index] == b->indices[b_index])) |
| 812 | return 1; |
| 813 | } |
| 814 | } |
| 815 | } |
| 816 | } |
| 817 | |
| 818 | return 0; |
| 819 | } |
| 820 | |
| 821 | /* Returns true if the insn can (potentially) alter the program counter. */ |
| 822 | |
| 823 | static int writes_to_pc PARAMS ((m32r_insn *)); |
| 824 | |
| 825 | static int |
| 826 | writes_to_pc (a) |
| 827 | m32r_insn *a; |
| 828 | { |
| 829 | #if 0 |
| 830 | /* Once PC operands are working.... */ |
| 831 | const CGEN_OPINST *a_operands == CGEN_INSN_OPERANDS (gas_cgen_cpu_desc, |
| 832 | a->insn); |
| 833 | |
| 834 | if (a_operands == NULL) |
| 835 | return 0; |
| 836 | |
| 837 | while (a_operands->type != CGEN_OPINST_END) |
| 838 | { |
| 839 | if (a_operands->operand != NULL |
| 840 | && CGEN_OPERAND_INDEX (gas_cgen_cpu_desc, |
| 841 | a_operands->operand) == M32R_OPERAND_PC) |
| 842 | return 1; |
| 843 | |
| 844 | a_operands++; |
| 845 | } |
| 846 | #else |
| 847 | if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI) |
| 848 | || CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI)) |
| 849 | return 1; |
| 850 | #endif |
| 851 | return 0; |
| 852 | } |
| 853 | |
| 854 | /* Return NULL if the two 16 bit insns can be executed in parallel. |
| 855 | Otherwise return a pointer to an error message explaining why not. */ |
| 856 | |
| 857 | static const char *can_make_parallel PARAMS ((m32r_insn *, m32r_insn *)); |
| 858 | |
| 859 | static const char * |
| 860 | can_make_parallel (a, b) |
| 861 | m32r_insn *a; |
| 862 | m32r_insn *b; |
| 863 | { |
| 864 | PIPE_ATTR a_pipe; |
| 865 | PIPE_ATTR b_pipe; |
| 866 | |
| 867 | /* Make sure the instructions are the right length. */ |
| 868 | if (CGEN_FIELDS_BITSIZE (&a->fields) != 16 |
| 869 | || CGEN_FIELDS_BITSIZE (&b->fields) != 16) |
| 870 | abort (); |
| 871 | |
| 872 | if (first_writes_to_seconds_operands (a, b, TRUE)) |
| 873 | return _("Instructions write to the same destination register."); |
| 874 | |
| 875 | a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE); |
| 876 | b_pipe = CGEN_INSN_ATTR_VALUE (b->insn, CGEN_INSN_PIPE); |
| 877 | |
| 878 | /* Make sure that the instructions use the correct execution pipelines. */ |
| 879 | if (a_pipe == PIPE_NONE |
| 880 | || b_pipe == PIPE_NONE) |
| 881 | return _("Instructions do not use parallel execution pipelines."); |
| 882 | |
| 883 | /* Leave this test for last, since it is the only test that can |
| 884 | go away if the instructions are swapped, and we want to make |
| 885 | sure that any other errors are detected before this happens. */ |
| 886 | if (a_pipe == PIPE_S |
| 887 | || b_pipe == PIPE_O |
| 888 | || (b_pipe == PIPE_O_OS && (enable_m32rx != 2))) |
| 889 | return _("Instructions share the same execution pipeline"); |
| 890 | |
| 891 | return NULL; |
| 892 | } |
| 893 | |
| 894 | /* Force the top bit of the second 16-bit insn to be set. */ |
| 895 | |
| 896 | static void make_parallel PARAMS ((CGEN_INSN_BYTES_PTR)); |
| 897 | |
| 898 | static void |
| 899 | make_parallel (buffer) |
| 900 | CGEN_INSN_BYTES_PTR buffer; |
| 901 | { |
| 902 | #if CGEN_INT_INSN_P |
| 903 | *buffer |= 0x8000; |
| 904 | #else |
| 905 | buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1] |
| 906 | |= 0x80; |
| 907 | #endif |
| 908 | } |
| 909 | |
| 910 | /* Same as make_parallel except buffer contains the bytes in target order. */ |
| 911 | |
| 912 | static void target_make_parallel PARAMS ((char *)); |
| 913 | |
| 914 | static void |
| 915 | target_make_parallel (buffer) |
| 916 | char *buffer; |
| 917 | { |
| 918 | buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1] |
| 919 | |= 0x80; |
| 920 | } |
| 921 | |
| 922 | /* Assemble two instructions with an explicit parallel operation (||) or |
| 923 | sequential operation (->). */ |
| 924 | |
| 925 | static void assemble_two_insns PARAMS ((char *, char *, int)); |
| 926 | |
| 927 | static void |
| 928 | assemble_two_insns (str, str2, parallel_p) |
| 929 | char *str; |
| 930 | char *str2; |
| 931 | int parallel_p; |
| 932 | { |
| 933 | char *str3; |
| 934 | m32r_insn first; |
| 935 | m32r_insn second; |
| 936 | char *errmsg; |
| 937 | char save_str2 = *str2; |
| 938 | |
| 939 | /* Separate the two instructions. */ |
| 940 | *str2 = 0; |
| 941 | |
| 942 | /* Make sure the two insns begin on a 32 bit boundary. |
| 943 | This is also done for the serial case (foo -> bar), relaxing doesn't |
| 944 | affect insns written like this. |
| 945 | Note that we must always do this as we can't assume anything about |
| 946 | whether we're currently on a 32 bit boundary or not. Relaxing may |
| 947 | change this. */ |
| 948 | fill_insn (0); |
| 949 | |
| 950 | first.debug_sym_link = debug_sym_link; |
| 951 | debug_sym_link = (sym_linkS *) 0; |
| 952 | |
| 953 | /* Parse the first instruction. */ |
| 954 | if (! (first.insn = m32r_cgen_assemble_insn |
| 955 | (gas_cgen_cpu_desc, str, & first.fields, first.buffer, & errmsg))) |
| 956 | { |
| 957 | as_bad (errmsg); |
| 958 | return; |
| 959 | } |
| 960 | |
| 961 | /* Check it. */ |
| 962 | if (CGEN_FIELDS_BITSIZE (&first.fields) != 16) |
| 963 | { |
| 964 | /* xgettext:c-format */ |
| 965 | as_bad (_("not a 16 bit instruction '%s'"), str); |
| 966 | return; |
| 967 | } |
| 968 | #ifdef E_M32R2_ARCH |
| 969 | else if ((enable_m32rx == 1) |
| 970 | /* FIXME: Need standard macro to perform this test. */ |
| 971 | && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) |
| 972 | & (1 << MACH_M32R2)) |
| 973 | && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) |
| 974 | & (1 << MACH_M32RX))))) |
| 975 | { |
| 976 | /* xgettext:c-format */ |
| 977 | as_bad (_("instruction '%s' is for the M32R2 only"), str); |
| 978 | return; |
| 979 | } |
| 980 | else if ((! enable_special |
| 981 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)) |
| 982 | || (! enable_special_m32r |
| 983 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R))) |
| 984 | #else |
| 985 | else if (! enable_special |
| 986 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)) |
| 987 | #endif |
| 988 | { |
| 989 | /* xgettext:c-format */ |
| 990 | as_bad (_("unknown instruction '%s'"), str); |
| 991 | return; |
| 992 | } |
| 993 | else if (! enable_m32rx |
| 994 | /* FIXME: Need standard macro to perform this test. */ |
| 995 | && (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) |
| 996 | == (1 << MACH_M32RX))) |
| 997 | { |
| 998 | /* xgettext:c-format */ |
| 999 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
| 1000 | return; |
| 1001 | } |
| 1002 | |
| 1003 | /* Check to see if this is an allowable parallel insn. */ |
| 1004 | if (parallel_p |
| 1005 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE) |
| 1006 | { |
| 1007 | /* xgettext:c-format */ |
| 1008 | as_bad (_("instruction '%s' cannot be executed in parallel."), str); |
| 1009 | return; |
| 1010 | } |
| 1011 | |
| 1012 | /* Restore the original assembly text, just in case it is needed. */ |
| 1013 | *str2 = save_str2; |
| 1014 | |
| 1015 | /* Save the original string pointer. */ |
| 1016 | str3 = str; |
| 1017 | |
| 1018 | /* Advanced past the parsed string. */ |
| 1019 | str = str2 + 2; |
| 1020 | |
| 1021 | /* Remember the entire string in case it is needed for error |
| 1022 | messages. */ |
| 1023 | str2 = str3; |
| 1024 | |
| 1025 | /* Convert the opcode to lower case. */ |
| 1026 | { |
| 1027 | char *s2 = str; |
| 1028 | |
| 1029 | while (ISSPACE (*s2++)) |
| 1030 | continue; |
| 1031 | |
| 1032 | --s2; |
| 1033 | |
| 1034 | while (ISALNUM (*s2)) |
| 1035 | { |
| 1036 | *s2 = TOLOWER (*s2); |
| 1037 | s2++; |
| 1038 | } |
| 1039 | } |
| 1040 | |
| 1041 | /* Preserve any fixups that have been generated and reset the list |
| 1042 | to empty. */ |
| 1043 | gas_cgen_save_fixups (0); |
| 1044 | |
| 1045 | /* Get the indices of the operands of the instruction. */ |
| 1046 | /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact |
| 1047 | doesn't seem right. Perhaps allow passing fields like we do insn. */ |
| 1048 | /* FIXME: ALIAS insns do not have operands, so we use this function |
| 1049 | to find the equivalent insn and overwrite the value stored in our |
| 1050 | structure. We still need the original insn, however, since this |
| 1051 | may have certain attributes that are not present in the unaliased |
| 1052 | version (eg relaxability). When aliases behave differently this |
| 1053 | may have to change. */ |
| 1054 | first.orig_insn = first.insn; |
| 1055 | { |
| 1056 | CGEN_FIELDS tmp_fields; |
| 1057 | first.insn = cgen_lookup_get_insn_operands |
| 1058 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (first.buffer), NULL, 16, |
| 1059 | first.indices, &tmp_fields); |
| 1060 | } |
| 1061 | |
| 1062 | if (first.insn == NULL) |
| 1063 | as_fatal (_("internal error: lookup/get operands failed")); |
| 1064 | |
| 1065 | second.debug_sym_link = NULL; |
| 1066 | |
| 1067 | /* Parse the second instruction. */ |
| 1068 | if (! (second.insn = m32r_cgen_assemble_insn |
| 1069 | (gas_cgen_cpu_desc, str, & second.fields, second.buffer, & errmsg))) |
| 1070 | { |
| 1071 | as_bad (errmsg); |
| 1072 | return; |
| 1073 | } |
| 1074 | |
| 1075 | /* Check it. */ |
| 1076 | if (CGEN_FIELDS_BITSIZE (&second.fields) != 16) |
| 1077 | { |
| 1078 | /* xgettext:c-format */ |
| 1079 | as_bad (_("not a 16 bit instruction '%s'"), str); |
| 1080 | return; |
| 1081 | } |
| 1082 | #ifdef E_M32R2_ARCH |
| 1083 | else if ((enable_m32rx == 1) |
| 1084 | /* FIXME: Need standard macro to perform this test. */ |
| 1085 | && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) |
| 1086 | & (1 << MACH_M32R2)) |
| 1087 | && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) |
| 1088 | & (1 << MACH_M32RX))))) |
| 1089 | { |
| 1090 | /* xgettext:c-format */ |
| 1091 | as_bad (_("instruction '%s' is for the M32R2 only"), str); |
| 1092 | return; |
| 1093 | } |
| 1094 | else if ((! enable_special |
| 1095 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) |
| 1096 | || (! enable_special_m32r |
| 1097 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R))) |
| 1098 | #else |
| 1099 | else if (! enable_special |
| 1100 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) |
| 1101 | #endif |
| 1102 | { |
| 1103 | /* xgettext:c-format */ |
| 1104 | as_bad (_("unknown instruction '%s'"), str); |
| 1105 | return; |
| 1106 | } |
| 1107 | else if (! enable_m32rx |
| 1108 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) |
| 1109 | { |
| 1110 | /* xgettext:c-format */ |
| 1111 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
| 1112 | return; |
| 1113 | } |
| 1114 | |
| 1115 | /* Check to see if this is an allowable parallel insn. */ |
| 1116 | if (parallel_p |
| 1117 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE) |
| 1118 | { |
| 1119 | /* xgettext:c-format */ |
| 1120 | as_bad (_("instruction '%s' cannot be executed in parallel."), str); |
| 1121 | return; |
| 1122 | } |
| 1123 | |
| 1124 | if (parallel_p && ! enable_m32rx) |
| 1125 | { |
| 1126 | if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP |
| 1127 | && CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP) |
| 1128 | { |
| 1129 | /* xgettext:c-format */ |
| 1130 | as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2); |
| 1131 | return; |
| 1132 | } |
| 1133 | } |
| 1134 | |
| 1135 | /* Get the indices of the operands of the instruction. */ |
| 1136 | second.orig_insn = second.insn; |
| 1137 | { |
| 1138 | CGEN_FIELDS tmp_fields; |
| 1139 | second.insn = cgen_lookup_get_insn_operands |
| 1140 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (second.buffer), NULL, 16, |
| 1141 | second.indices, &tmp_fields); |
| 1142 | } |
| 1143 | |
| 1144 | if (second.insn == NULL) |
| 1145 | as_fatal (_("internal error: lookup/get operands failed")); |
| 1146 | |
| 1147 | /* We assume that if the first instruction writes to a register that is |
| 1148 | read by the second instruction it is because the programmer intended |
| 1149 | this to happen, (after all they have explicitly requested that these |
| 1150 | two instructions be executed in parallel). Although if the global |
| 1151 | variable warn_explicit_parallel_conflicts is true then we do generate |
| 1152 | a warning message. Similarly we assume that parallel branch and jump |
| 1153 | instructions are deliberate and should not produce errors. */ |
| 1154 | |
| 1155 | if (parallel_p && warn_explicit_parallel_conflicts) |
| 1156 | { |
| 1157 | void (* func)(const char *, ...); |
| 1158 | |
| 1159 | func = error_explicit_parallel_conflicts ? as_bad : as_warn; |
| 1160 | |
| 1161 | if (first_writes_to_seconds_operands (&first, &second, FALSE)) |
| 1162 | /* xgettext:c-format */ |
| 1163 | func (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2); |
| 1164 | |
| 1165 | if (first_writes_to_seconds_operands (&second, &first, FALSE)) |
| 1166 | /* xgettext:c-format */ |
| 1167 | func (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2); |
| 1168 | } |
| 1169 | |
| 1170 | if (!parallel_p |
| 1171 | || (errmsg = (char *) can_make_parallel (&first, &second)) == NULL) |
| 1172 | { |
| 1173 | /* Get the fixups for the first instruction. */ |
| 1174 | gas_cgen_swap_fixups (0); |
| 1175 | |
| 1176 | /* Write it out. */ |
| 1177 | expand_debug_syms (first.debug_sym_link, 1); |
| 1178 | gas_cgen_finish_insn (first.orig_insn, first.buffer, |
| 1179 | CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL); |
| 1180 | |
| 1181 | /* Force the top bit of the second insn to be set. */ |
| 1182 | if (parallel_p) |
| 1183 | make_parallel (second.buffer); |
| 1184 | |
| 1185 | /* Get its fixups. */ |
| 1186 | gas_cgen_restore_fixups (0); |
| 1187 | |
| 1188 | /* Write it out. */ |
| 1189 | expand_debug_syms (second.debug_sym_link, 1); |
| 1190 | gas_cgen_finish_insn (second.orig_insn, second.buffer, |
| 1191 | CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL); |
| 1192 | } |
| 1193 | /* Try swapping the instructions to see if they work that way. */ |
| 1194 | else if (can_make_parallel (&second, &first) == NULL) |
| 1195 | { |
| 1196 | /* Write out the second instruction first. */ |
| 1197 | expand_debug_syms (second.debug_sym_link, 1); |
| 1198 | gas_cgen_finish_insn (second.orig_insn, second.buffer, |
| 1199 | CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL); |
| 1200 | |
| 1201 | /* Force the top bit of the first instruction to be set. */ |
| 1202 | make_parallel (first.buffer); |
| 1203 | |
| 1204 | /* Get the fixups for the first instruction. */ |
| 1205 | gas_cgen_restore_fixups (0); |
| 1206 | |
| 1207 | /* Write out the first instruction. */ |
| 1208 | expand_debug_syms (first.debug_sym_link, 1); |
| 1209 | gas_cgen_finish_insn (first.orig_insn, first.buffer, |
| 1210 | CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL); |
| 1211 | } |
| 1212 | else |
| 1213 | { |
| 1214 | as_bad ("'%s': %s", str2, errmsg); |
| 1215 | return; |
| 1216 | } |
| 1217 | |
| 1218 | if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL) |
| 1219 | || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) |
| 1220 | m32r_flags |= E_M32R_HAS_HIDDEN_INST; |
| 1221 | if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R) |
| 1222 | || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R)) |
| 1223 | m32r_flags |= E_M32R_HAS_BIT_INST; |
| 1224 | if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_FLOAT) |
| 1225 | || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_FLOAT)) |
| 1226 | m32r_flags |= E_M32R_HAS_FLOAT_INST; |
| 1227 | |
| 1228 | /* Set these so m32r_fill_insn can use them. */ |
| 1229 | prev_seg = now_seg; |
| 1230 | prev_subseg = now_subseg; |
| 1231 | } |
| 1232 | |
| 1233 | void |
| 1234 | md_assemble (str) |
| 1235 | char *str; |
| 1236 | { |
| 1237 | m32r_insn insn; |
| 1238 | char *errmsg; |
| 1239 | char *str2 = NULL; |
| 1240 | |
| 1241 | /* Initialize GAS's cgen interface for a new instruction. */ |
| 1242 | gas_cgen_init_parse (); |
| 1243 | |
| 1244 | /* Look for a parallel instruction separator. */ |
| 1245 | if ((str2 = strstr (str, "||")) != NULL) |
| 1246 | { |
| 1247 | assemble_two_insns (str, str2, 1); |
| 1248 | m32r_flags |= E_M32R_HAS_PARALLEL; |
| 1249 | return; |
| 1250 | } |
| 1251 | |
| 1252 | /* Also look for a sequential instruction separator. */ |
| 1253 | if ((str2 = strstr (str, "->")) != NULL) |
| 1254 | { |
| 1255 | assemble_two_insns (str, str2, 0); |
| 1256 | return; |
| 1257 | } |
| 1258 | |
| 1259 | insn.debug_sym_link = debug_sym_link; |
| 1260 | debug_sym_link = (sym_linkS *) 0; |
| 1261 | |
| 1262 | insn.insn = m32r_cgen_assemble_insn |
| 1263 | (gas_cgen_cpu_desc, str, &insn.fields, insn.buffer, & errmsg); |
| 1264 | |
| 1265 | if (!insn.insn) |
| 1266 | { |
| 1267 | as_bad (errmsg); |
| 1268 | return; |
| 1269 | } |
| 1270 | |
| 1271 | #ifdef E_M32R2_ARCH |
| 1272 | if ((enable_m32rx == 1) |
| 1273 | /* FIXME: Need standard macro to perform this test. */ |
| 1274 | && ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) |
| 1275 | & (1 << MACH_M32R2)) |
| 1276 | && !((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) |
| 1277 | & (1 << MACH_M32RX))))) |
| 1278 | { |
| 1279 | /* xgettext:c-format */ |
| 1280 | as_bad (_("instruction '%s' is for the M32R2 only"), str); |
| 1281 | return; |
| 1282 | } |
| 1283 | else if ((! enable_special |
| 1284 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) |
| 1285 | || (! enable_special_m32r |
| 1286 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R))) |
| 1287 | #else |
| 1288 | if (! enable_special |
| 1289 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) |
| 1290 | #endif |
| 1291 | { |
| 1292 | /* xgettext:c-format */ |
| 1293 | as_bad (_("unknown instruction '%s'"), str); |
| 1294 | return; |
| 1295 | } |
| 1296 | else if (! enable_m32rx |
| 1297 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) |
| 1298 | { |
| 1299 | /* xgettext:c-format */ |
| 1300 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
| 1301 | return; |
| 1302 | } |
| 1303 | |
| 1304 | if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) |
| 1305 | m32r_flags |= E_M32R_HAS_HIDDEN_INST; |
| 1306 | if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R)) |
| 1307 | m32r_flags |= E_M32R_HAS_BIT_INST; |
| 1308 | if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_FLOAT)) |
| 1309 | m32r_flags |= E_M32R_HAS_FLOAT_INST; |
| 1310 | |
| 1311 | if (CGEN_INSN_BITSIZE (insn.insn) == 32) |
| 1312 | { |
| 1313 | /* 32 bit insns must live on 32 bit boundaries. */ |
| 1314 | if (prev_insn.insn || seen_relaxable_p) |
| 1315 | { |
| 1316 | /* ??? If calling fill_insn too many times turns us into a memory |
| 1317 | pig, can we call a fn to assemble a nop instead of |
| 1318 | !seen_relaxable_p? */ |
| 1319 | fill_insn (0); |
| 1320 | } |
| 1321 | |
| 1322 | expand_debug_syms (insn.debug_sym_link, 2); |
| 1323 | |
| 1324 | /* Doesn't really matter what we pass for RELAX_P here. */ |
| 1325 | gas_cgen_finish_insn (insn.insn, insn.buffer, |
| 1326 | CGEN_FIELDS_BITSIZE (&insn.fields), 1, NULL); |
| 1327 | } |
| 1328 | else |
| 1329 | { |
| 1330 | int on_32bit_boundary_p; |
| 1331 | int swap = FALSE; |
| 1332 | |
| 1333 | if (CGEN_INSN_BITSIZE (insn.insn) != 16) |
| 1334 | abort (); |
| 1335 | |
| 1336 | insn.orig_insn = insn.insn; |
| 1337 | |
| 1338 | /* If the previous insn was relaxable, then it may be expanded |
| 1339 | to fill the current 16 bit slot. Emit a NOP here to occupy |
| 1340 | this slot, so that we can start at optimizing at a 32 bit |
| 1341 | boundary. */ |
| 1342 | if (prev_insn.insn && seen_relaxable_p && optimize) |
| 1343 | fill_insn (0); |
| 1344 | |
| 1345 | if (enable_m32rx) |
| 1346 | { |
| 1347 | /* Get the indices of the operands of the instruction. |
| 1348 | FIXME: See assemble_parallel for notes on orig_insn. */ |
| 1349 | { |
| 1350 | CGEN_FIELDS tmp_fields; |
| 1351 | insn.insn = cgen_lookup_get_insn_operands |
| 1352 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (insn.buffer), NULL, |
| 1353 | 16, insn.indices, &tmp_fields); |
| 1354 | } |
| 1355 | |
| 1356 | if (insn.insn == NULL) |
| 1357 | as_fatal (_("internal error: lookup/get operands failed")); |
| 1358 | } |
| 1359 | |
| 1360 | /* Compute whether we're on a 32 bit boundary or not. |
| 1361 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ |
| 1362 | on_32bit_boundary_p = prev_insn.insn == NULL; |
| 1363 | |
| 1364 | /* Look to see if this instruction can be combined with the |
| 1365 | previous instruction to make one, parallel, 32 bit instruction. |
| 1366 | If the previous instruction (potentially) changed the flow of |
| 1367 | program control, then it cannot be combined with the current |
| 1368 | instruction. If the current instruction is relaxable, then it |
| 1369 | might be replaced with a longer version, so we cannot combine it. |
| 1370 | Also if the output of the previous instruction is used as an |
| 1371 | input to the current instruction then it cannot be combined. |
| 1372 | Otherwise call can_make_parallel() with both orderings of the |
| 1373 | instructions to see if they can be combined. */ |
| 1374 | if (! on_32bit_boundary_p |
| 1375 | && parallel () |
| 1376 | && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0 |
| 1377 | && ! writes_to_pc (&prev_insn) |
| 1378 | && ! first_writes_to_seconds_operands (&prev_insn, &insn, FALSE)) |
| 1379 | { |
| 1380 | if (can_make_parallel (&prev_insn, &insn) == NULL) |
| 1381 | make_parallel (insn.buffer); |
| 1382 | else if (can_make_parallel (&insn, &prev_insn) == NULL) |
| 1383 | swap = TRUE; |
| 1384 | } |
| 1385 | |
| 1386 | expand_debug_syms (insn.debug_sym_link, 1); |
| 1387 | |
| 1388 | { |
| 1389 | int i; |
| 1390 | finished_insnS fi; |
| 1391 | |
| 1392 | /* Ensure each pair of 16 bit insns is in the same frag. */ |
| 1393 | frag_grow (4); |
| 1394 | |
| 1395 | gas_cgen_finish_insn (insn.orig_insn, insn.buffer, |
| 1396 | CGEN_FIELDS_BITSIZE (&insn.fields), |
| 1397 | 1 /* relax_p */, &fi); |
| 1398 | insn.addr = fi.addr; |
| 1399 | insn.frag = fi.frag; |
| 1400 | insn.num_fixups = fi.num_fixups; |
| 1401 | for (i = 0; i < fi.num_fixups; ++i) |
| 1402 | insn.fixups[i] = fi.fixups[i]; |
| 1403 | } |
| 1404 | |
| 1405 | if (swap) |
| 1406 | { |
| 1407 | int i, tmp; |
| 1408 | |
| 1409 | #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp |
| 1410 | |
| 1411 | /* Swap the two insns */ |
| 1412 | SWAP_BYTES (prev_insn.addr[0], insn.addr[0]); |
| 1413 | SWAP_BYTES (prev_insn.addr[1], insn.addr[1]); |
| 1414 | |
| 1415 | target_make_parallel (insn.addr); |
| 1416 | |
| 1417 | /* Swap any relaxable frags recorded for the two insns. */ |
| 1418 | /* FIXME: Clarify. relaxation precludes parallel insns */ |
| 1419 | if (prev_insn.frag->fr_opcode == prev_insn.addr) |
| 1420 | prev_insn.frag->fr_opcode = insn.addr; |
| 1421 | else if (insn.frag->fr_opcode == insn.addr) |
| 1422 | insn.frag->fr_opcode = prev_insn.addr; |
| 1423 | |
| 1424 | /* Update the addresses in any fixups. |
| 1425 | Note that we don't have to handle the case where each insn is in |
| 1426 | a different frag as we ensure they're in the same frag above. */ |
| 1427 | for (i = 0; i < prev_insn.num_fixups; ++i) |
| 1428 | prev_insn.fixups[i]->fx_where += 2; |
| 1429 | for (i = 0; i < insn.num_fixups; ++i) |
| 1430 | insn.fixups[i]->fx_where -= 2; |
| 1431 | } |
| 1432 | |
| 1433 | /* Keep track of whether we've seen a pair of 16 bit insns. |
| 1434 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ |
| 1435 | if (on_32bit_boundary_p) |
| 1436 | prev_insn = insn; |
| 1437 | else |
| 1438 | prev_insn.insn = NULL; |
| 1439 | |
| 1440 | /* If the insn needs the following one to be on a 32 bit boundary |
| 1441 | (e.g. subroutine calls), fill this insn's slot. */ |
| 1442 | if (on_32bit_boundary_p |
| 1443 | && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0) |
| 1444 | fill_insn (0); |
| 1445 | |
| 1446 | /* If this is a relaxable insn (can be replaced with a larger version) |
| 1447 | mark the fact so that we can emit an alignment directive for a |
| 1448 | following 32 bit insn if we see one. */ |
| 1449 | if (CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0) |
| 1450 | seen_relaxable_p = 1; |
| 1451 | } |
| 1452 | |
| 1453 | /* Set these so m32r_fill_insn can use them. */ |
| 1454 | prev_seg = now_seg; |
| 1455 | prev_subseg = now_subseg; |
| 1456 | } |
| 1457 | |
| 1458 | /* The syntax in the manual says constants begin with '#'. |
| 1459 | We just ignore it. */ |
| 1460 | |
| 1461 | void |
| 1462 | md_operand (expressionP) |
| 1463 | expressionS *expressionP; |
| 1464 | { |
| 1465 | if (*input_line_pointer == '#') |
| 1466 | { |
| 1467 | input_line_pointer++; |
| 1468 | expression (expressionP); |
| 1469 | } |
| 1470 | } |
| 1471 | |
| 1472 | valueT |
| 1473 | md_section_align (segment, size) |
| 1474 | segT segment; |
| 1475 | valueT size; |
| 1476 | { |
| 1477 | int align = bfd_get_section_alignment (stdoutput, segment); |
| 1478 | return ((size + (1 << align) - 1) & (-1 << align)); |
| 1479 | } |
| 1480 | |
| 1481 | symbolS * |
| 1482 | md_undefined_symbol (name) |
| 1483 | char *name ATTRIBUTE_UNUSED; |
| 1484 | { |
| 1485 | return 0; |
| 1486 | } |
| 1487 | \f |
| 1488 | /* .scomm pseudo-op handler. |
| 1489 | |
| 1490 | This is a new pseudo-op to handle putting objects in .scommon. |
| 1491 | By doing this the linker won't need to do any work, |
| 1492 | and more importantly it removes the implicit -G arg necessary to |
| 1493 | correctly link the object file. */ |
| 1494 | |
| 1495 | static void |
| 1496 | m32r_scomm (ignore) |
| 1497 | int ignore ATTRIBUTE_UNUSED; |
| 1498 | { |
| 1499 | register char *name; |
| 1500 | register char c; |
| 1501 | register char *p; |
| 1502 | offsetT size; |
| 1503 | register symbolS *symbolP; |
| 1504 | offsetT align; |
| 1505 | int align2; |
| 1506 | |
| 1507 | name = input_line_pointer; |
| 1508 | c = get_symbol_end (); |
| 1509 | |
| 1510 | /* Just after name is now '\0'. */ |
| 1511 | p = input_line_pointer; |
| 1512 | *p = c; |
| 1513 | SKIP_WHITESPACE (); |
| 1514 | if (*input_line_pointer != ',') |
| 1515 | { |
| 1516 | as_bad (_("Expected comma after symbol-name: rest of line ignored.")); |
| 1517 | ignore_rest_of_line (); |
| 1518 | return; |
| 1519 | } |
| 1520 | |
| 1521 | /* Skip ','. */ |
| 1522 | input_line_pointer++; |
| 1523 | if ((size = get_absolute_expression ()) < 0) |
| 1524 | { |
| 1525 | /* xgettext:c-format */ |
| 1526 | as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size); |
| 1527 | ignore_rest_of_line (); |
| 1528 | return; |
| 1529 | } |
| 1530 | |
| 1531 | /* The third argument to .scomm is the alignment. */ |
| 1532 | if (*input_line_pointer != ',') |
| 1533 | align = 8; |
| 1534 | else |
| 1535 | { |
| 1536 | ++input_line_pointer; |
| 1537 | align = get_absolute_expression (); |
| 1538 | if (align <= 0) |
| 1539 | { |
| 1540 | as_warn (_("ignoring bad alignment")); |
| 1541 | align = 8; |
| 1542 | } |
| 1543 | } |
| 1544 | |
| 1545 | /* Convert to a power of 2 alignment. */ |
| 1546 | if (align) |
| 1547 | { |
| 1548 | for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2) |
| 1549 | continue; |
| 1550 | if (align != 1) |
| 1551 | { |
| 1552 | as_bad (_("Common alignment not a power of 2")); |
| 1553 | ignore_rest_of_line (); |
| 1554 | return; |
| 1555 | } |
| 1556 | } |
| 1557 | else |
| 1558 | align2 = 0; |
| 1559 | |
| 1560 | *p = 0; |
| 1561 | symbolP = symbol_find_or_make (name); |
| 1562 | *p = c; |
| 1563 | |
| 1564 | if (S_IS_DEFINED (symbolP)) |
| 1565 | { |
| 1566 | /* xgettext:c-format */ |
| 1567 | as_bad (_("Ignoring attempt to re-define symbol `%s'."), |
| 1568 | S_GET_NAME (symbolP)); |
| 1569 | ignore_rest_of_line (); |
| 1570 | return; |
| 1571 | } |
| 1572 | |
| 1573 | if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) |
| 1574 | { |
| 1575 | /* xgettext:c-format */ |
| 1576 | as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."), |
| 1577 | S_GET_NAME (symbolP), |
| 1578 | (long) S_GET_VALUE (symbolP), |
| 1579 | (long) size); |
| 1580 | |
| 1581 | ignore_rest_of_line (); |
| 1582 | return; |
| 1583 | } |
| 1584 | |
| 1585 | if (symbol_get_obj (symbolP)->local) |
| 1586 | { |
| 1587 | segT old_sec = now_seg; |
| 1588 | int old_subsec = now_subseg; |
| 1589 | char *pfrag; |
| 1590 | |
| 1591 | record_alignment (sbss_section, align2); |
| 1592 | subseg_set (sbss_section, 0); |
| 1593 | |
| 1594 | if (align2) |
| 1595 | frag_align (align2, 0, 0); |
| 1596 | |
| 1597 | if (S_GET_SEGMENT (symbolP) == sbss_section) |
| 1598 | symbol_get_frag (symbolP)->fr_symbol = 0; |
| 1599 | |
| 1600 | symbol_set_frag (symbolP, frag_now); |
| 1601 | |
| 1602 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, |
| 1603 | (char *) 0); |
| 1604 | *pfrag = 0; |
| 1605 | S_SET_SIZE (symbolP, size); |
| 1606 | S_SET_SEGMENT (symbolP, sbss_section); |
| 1607 | S_CLEAR_EXTERNAL (symbolP); |
| 1608 | subseg_set (old_sec, old_subsec); |
| 1609 | } |
| 1610 | else |
| 1611 | { |
| 1612 | S_SET_VALUE (symbolP, (valueT) size); |
| 1613 | S_SET_ALIGN (symbolP, align2); |
| 1614 | S_SET_EXTERNAL (symbolP); |
| 1615 | S_SET_SEGMENT (symbolP, &scom_section); |
| 1616 | } |
| 1617 | |
| 1618 | demand_empty_rest_of_line (); |
| 1619 | } |
| 1620 | \f |
| 1621 | /* Interface to relax_segment. */ |
| 1622 | |
| 1623 | /* FIXME: Build table by hand, get it working, then machine generate. */ |
| 1624 | |
| 1625 | const relax_typeS md_relax_table[] = |
| 1626 | { |
| 1627 | /* The fields are: |
| 1628 | 1) most positive reach of this state, |
| 1629 | 2) most negative reach of this state, |
| 1630 | 3) how many bytes this mode will add to the size of the current frag |
| 1631 | 4) which index into the table to try if we can't fit into this one. */ |
| 1632 | |
| 1633 | /* The first entry must be unused because an `rlx_more' value of zero ends |
| 1634 | each list. */ |
| 1635 | {1, 1, 0, 0}, |
| 1636 | |
| 1637 | /* The displacement used by GAS is from the end of the 2 byte insn, |
| 1638 | so we subtract 2 from the following. */ |
| 1639 | /* 16 bit insn, 8 bit disp -> 10 bit range. |
| 1640 | This doesn't handle a branch in the right slot at the border: |
| 1641 | the "& -4" isn't taken into account. It's not important enough to |
| 1642 | complicate things over it, so we subtract an extra 2 (or + 2 in -ve |
| 1643 | case). */ |
| 1644 | {511 - 2 - 2, -512 - 2 + 2, 0, 2 }, |
| 1645 | /* 32 bit insn, 24 bit disp -> 26 bit range. */ |
| 1646 | {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 }, |
| 1647 | /* Same thing, but with leading nop for alignment. */ |
| 1648 | {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 } |
| 1649 | }; |
| 1650 | |
| 1651 | long |
| 1652 | m32r_relax_frag (segment, fragP, stretch) |
| 1653 | segT segment; |
| 1654 | fragS *fragP; |
| 1655 | long stretch; |
| 1656 | { |
| 1657 | /* Address of branch insn. */ |
| 1658 | long address = fragP->fr_address + fragP->fr_fix - 2; |
| 1659 | long growth = 0; |
| 1660 | |
| 1661 | /* Keep 32 bit insns aligned on 32 bit boundaries. */ |
| 1662 | if (fragP->fr_subtype == 2) |
| 1663 | { |
| 1664 | if ((address & 3) != 0) |
| 1665 | { |
| 1666 | fragP->fr_subtype = 3; |
| 1667 | growth = 2; |
| 1668 | } |
| 1669 | } |
| 1670 | else if (fragP->fr_subtype == 3) |
| 1671 | { |
| 1672 | if ((address & 3) == 0) |
| 1673 | { |
| 1674 | fragP->fr_subtype = 2; |
| 1675 | growth = -2; |
| 1676 | } |
| 1677 | } |
| 1678 | else |
| 1679 | { |
| 1680 | growth = relax_frag (segment, fragP, stretch); |
| 1681 | |
| 1682 | /* Long jump on odd halfword boundary? */ |
| 1683 | if (fragP->fr_subtype == 2 && (address & 3) != 0) |
| 1684 | { |
| 1685 | fragP->fr_subtype = 3; |
| 1686 | growth += 2; |
| 1687 | } |
| 1688 | } |
| 1689 | |
| 1690 | return growth; |
| 1691 | } |
| 1692 | |
| 1693 | /* Return an initial guess of the length by which a fragment must grow to |
| 1694 | hold a branch to reach its destination. |
| 1695 | Also updates fr_type/fr_subtype as necessary. |
| 1696 | |
| 1697 | Called just before doing relaxation. |
| 1698 | Any symbol that is now undefined will not become defined. |
| 1699 | The guess for fr_var is ACTUALLY the growth beyond fr_fix. |
| 1700 | Whatever we do to grow fr_fix or fr_var contributes to our returned value. |
| 1701 | Although it may not be explicit in the frag, pretend fr_var starts |
| 1702 | with a 0 value. */ |
| 1703 | |
| 1704 | int |
| 1705 | md_estimate_size_before_relax (fragP, segment) |
| 1706 | fragS *fragP; |
| 1707 | segT segment; |
| 1708 | { |
| 1709 | /* The only thing we have to handle here are symbols outside of the |
| 1710 | current segment. They may be undefined or in a different segment in |
| 1711 | which case linker scripts may place them anywhere. |
| 1712 | However, we can't finish the fragment here and emit the reloc as insn |
| 1713 | alignment requirements may move the insn about. */ |
| 1714 | |
| 1715 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment) |
| 1716 | { |
| 1717 | #if 0 |
| 1718 | int old_fr_fix = fragP->fr_fix; |
| 1719 | #endif |
| 1720 | |
| 1721 | /* The symbol is undefined in this segment. |
| 1722 | Change the relaxation subtype to the max allowable and leave |
| 1723 | all further handling to md_convert_frag. */ |
| 1724 | fragP->fr_subtype = 2; |
| 1725 | |
| 1726 | #if 0 |
| 1727 | /* Can't use this, but leave in for illustration. */ |
| 1728 | /* Change 16 bit insn to 32 bit insn. */ |
| 1729 | fragP->fr_opcode[0] |= 0x80; |
| 1730 | |
| 1731 | /* Increase known (fixed) size of fragment. */ |
| 1732 | fragP->fr_fix += 2; |
| 1733 | |
| 1734 | /* Create a relocation for it. */ |
| 1735 | fix_new (fragP, old_fr_fix, 4, |
| 1736 | fragP->fr_symbol, |
| 1737 | fragP->fr_offset, 1 /* pcrel */, |
| 1738 | /* FIXME: Can't use a real BFD reloc here. |
| 1739 | gas_cgen_md_apply_fix3 can't handle it. */ |
| 1740 | BFD_RELOC_M32R_26_PCREL); |
| 1741 | |
| 1742 | /* Mark this fragment as finished. */ |
| 1743 | frag_wane (fragP); |
| 1744 | return fragP->fr_fix - old_fr_fix; |
| 1745 | #else |
| 1746 | { |
| 1747 | const CGEN_INSN *insn; |
| 1748 | int i; |
| 1749 | |
| 1750 | /* Update the recorded insn. |
| 1751 | Fortunately we don't have to look very far. |
| 1752 | FIXME: Change this to record in the instruction the next higher |
| 1753 | relaxable insn to use. */ |
| 1754 | for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++) |
| 1755 | { |
| 1756 | if ((strcmp (CGEN_INSN_MNEMONIC (insn), |
| 1757 | CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn)) |
| 1758 | == 0) |
| 1759 | && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED)) |
| 1760 | break; |
| 1761 | } |
| 1762 | if (i == 4) |
| 1763 | abort (); |
| 1764 | |
| 1765 | fragP->fr_cgen.insn = insn; |
| 1766 | return 2; |
| 1767 | } |
| 1768 | #endif |
| 1769 | } |
| 1770 | |
| 1771 | return md_relax_table[fragP->fr_subtype].rlx_length; |
| 1772 | } |
| 1773 | |
| 1774 | /* *FRAGP has been relaxed to its final size, and now needs to have |
| 1775 | the bytes inside it modified to conform to the new size. |
| 1776 | |
| 1777 | Called after relaxation is finished. |
| 1778 | fragP->fr_type == rs_machine_dependent. |
| 1779 | fragP->fr_subtype is the subtype of what the address relaxed to. */ |
| 1780 | |
| 1781 | void |
| 1782 | md_convert_frag (abfd, sec, fragP) |
| 1783 | bfd *abfd ATTRIBUTE_UNUSED; |
| 1784 | segT sec; |
| 1785 | fragS *fragP; |
| 1786 | { |
| 1787 | char *opcode; |
| 1788 | char *displacement; |
| 1789 | int target_address; |
| 1790 | int opcode_address; |
| 1791 | int extension; |
| 1792 | int addend; |
| 1793 | |
| 1794 | opcode = fragP->fr_opcode; |
| 1795 | |
| 1796 | /* Address opcode resides at in file space. */ |
| 1797 | opcode_address = fragP->fr_address + fragP->fr_fix - 2; |
| 1798 | |
| 1799 | switch (fragP->fr_subtype) |
| 1800 | { |
| 1801 | case 1: |
| 1802 | extension = 0; |
| 1803 | displacement = &opcode[1]; |
| 1804 | break; |
| 1805 | case 2: |
| 1806 | opcode[0] |= 0x80; |
| 1807 | extension = 2; |
| 1808 | displacement = &opcode[1]; |
| 1809 | break; |
| 1810 | case 3: |
| 1811 | opcode[2] = opcode[0] | 0x80; |
| 1812 | md_number_to_chars (opcode, PAR_NOP_INSN, 2); |
| 1813 | opcode_address += 2; |
| 1814 | extension = 4; |
| 1815 | displacement = &opcode[3]; |
| 1816 | break; |
| 1817 | default: |
| 1818 | abort (); |
| 1819 | } |
| 1820 | |
| 1821 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec) |
| 1822 | { |
| 1823 | /* Symbol must be resolved by linker. */ |
| 1824 | if (fragP->fr_offset & 3) |
| 1825 | as_warn (_("Addend to unresolved symbol not on word boundary.")); |
| 1826 | addend = fragP->fr_offset >> 2; |
| 1827 | } |
| 1828 | else |
| 1829 | { |
| 1830 | /* Address we want to reach in file space. */ |
| 1831 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
| 1832 | addend = (target_address - (opcode_address & -4)) >> 2; |
| 1833 | } |
| 1834 | |
| 1835 | /* Create a relocation for symbols that must be resolved by the linker. |
| 1836 | Otherwise output the completed insn. */ |
| 1837 | |
| 1838 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec) |
| 1839 | { |
| 1840 | assert (fragP->fr_subtype != 1); |
| 1841 | assert (fragP->fr_cgen.insn != 0); |
| 1842 | gas_cgen_record_fixup (fragP, |
| 1843 | /* Offset of branch insn in frag. */ |
| 1844 | fragP->fr_fix + extension - 4, |
| 1845 | fragP->fr_cgen.insn, |
| 1846 | 4 /* Length. */, |
| 1847 | /* FIXME: quick hack. */ |
| 1848 | #if 0 |
| 1849 | cgen_operand_lookup_by_num (gas_cgen_cpu_desc, |
| 1850 | fragP->fr_cgen.opindex), |
| 1851 | #else |
| 1852 | cgen_operand_lookup_by_num (gas_cgen_cpu_desc, |
| 1853 | M32R_OPERAND_DISP24), |
| 1854 | #endif |
| 1855 | fragP->fr_cgen.opinfo, |
| 1856 | fragP->fr_symbol, fragP->fr_offset); |
| 1857 | } |
| 1858 | |
| 1859 | #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3) |
| 1860 | |
| 1861 | md_number_to_chars (displacement, (valueT) addend, |
| 1862 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
| 1863 | |
| 1864 | fragP->fr_fix += extension; |
| 1865 | } |
| 1866 | \f |
| 1867 | /* Functions concerning relocs. */ |
| 1868 | |
| 1869 | /* The location from which a PC relative jump should be calculated, |
| 1870 | given a PC relative reloc. */ |
| 1871 | |
| 1872 | long |
| 1873 | md_pcrel_from_section (fixP, sec) |
| 1874 | fixS *fixP; |
| 1875 | segT sec; |
| 1876 | { |
| 1877 | if (fixP->fx_addsy != (symbolS *) NULL |
| 1878 | && (! S_IS_DEFINED (fixP->fx_addsy) |
| 1879 | || S_GET_SEGMENT (fixP->fx_addsy) != sec)) |
| 1880 | { |
| 1881 | /* The symbol is undefined (or is defined but not in this section). |
| 1882 | Let the linker figure it out. */ |
| 1883 | return 0; |
| 1884 | } |
| 1885 | |
| 1886 | return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L; |
| 1887 | } |
| 1888 | |
| 1889 | /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. |
| 1890 | Returns BFD_RELOC_NONE if no reloc type can be found. |
| 1891 | *FIXP may be modified if desired. */ |
| 1892 | |
| 1893 | bfd_reloc_code_real_type |
| 1894 | md_cgen_lookup_reloc (insn, operand, fixP) |
| 1895 | const CGEN_INSN *insn ATTRIBUTE_UNUSED; |
| 1896 | const CGEN_OPERAND *operand; |
| 1897 | fixS *fixP; |
| 1898 | { |
| 1899 | switch (operand->type) |
| 1900 | { |
| 1901 | case M32R_OPERAND_DISP8: return BFD_RELOC_M32R_10_PCREL; |
| 1902 | case M32R_OPERAND_DISP16: return BFD_RELOC_M32R_18_PCREL; |
| 1903 | case M32R_OPERAND_DISP24: return BFD_RELOC_M32R_26_PCREL; |
| 1904 | case M32R_OPERAND_UIMM24: return BFD_RELOC_M32R_24; |
| 1905 | case M32R_OPERAND_HI16: |
| 1906 | case M32R_OPERAND_SLO16: |
| 1907 | case M32R_OPERAND_ULO16: |
| 1908 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ |
| 1909 | if (fixP->fx_cgen.opinfo != 0) |
| 1910 | return fixP->fx_cgen.opinfo; |
| 1911 | break; |
| 1912 | default: |
| 1913 | /* Avoid -Wall warning. */ |
| 1914 | break; |
| 1915 | } |
| 1916 | return BFD_RELOC_NONE; |
| 1917 | } |
| 1918 | |
| 1919 | /* Record a HI16 reloc for later matching with its LO16 cousin. */ |
| 1920 | |
| 1921 | static void m32r_record_hi16 PARAMS ((int, fixS *, segT)); |
| 1922 | |
| 1923 | static void |
| 1924 | m32r_record_hi16 (reloc_type, fixP, seg) |
| 1925 | int reloc_type; |
| 1926 | fixS *fixP; |
| 1927 | segT seg ATTRIBUTE_UNUSED; |
| 1928 | { |
| 1929 | struct m32r_hi_fixup *hi_fixup; |
| 1930 | |
| 1931 | assert (reloc_type == BFD_RELOC_M32R_HI16_SLO |
| 1932 | || reloc_type == BFD_RELOC_M32R_HI16_ULO); |
| 1933 | |
| 1934 | hi_fixup = ((struct m32r_hi_fixup *) |
| 1935 | xmalloc (sizeof (struct m32r_hi_fixup))); |
| 1936 | hi_fixup->fixp = fixP; |
| 1937 | hi_fixup->seg = now_seg; |
| 1938 | hi_fixup->next = m32r_hi_fixup_list; |
| 1939 | |
| 1940 | m32r_hi_fixup_list = hi_fixup; |
| 1941 | } |
| 1942 | |
| 1943 | /* Called while parsing an instruction to create a fixup. |
| 1944 | We need to check for HI16 relocs and queue them up for later sorting. */ |
| 1945 | |
| 1946 | fixS * |
| 1947 | m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp) |
| 1948 | fragS *frag; |
| 1949 | int where; |
| 1950 | const CGEN_INSN *insn; |
| 1951 | int length; |
| 1952 | const CGEN_OPERAND *operand; |
| 1953 | int opinfo; |
| 1954 | expressionS *exp; |
| 1955 | { |
| 1956 | fixS *fixP = gas_cgen_record_fixup_exp (frag, where, insn, length, |
| 1957 | operand, opinfo, exp); |
| 1958 | |
| 1959 | switch (operand->type) |
| 1960 | { |
| 1961 | case M32R_OPERAND_HI16: |
| 1962 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ |
| 1963 | if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO |
| 1964 | || fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) |
| 1965 | m32r_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg); |
| 1966 | break; |
| 1967 | default: |
| 1968 | /* Avoid -Wall warning */ |
| 1969 | break; |
| 1970 | } |
| 1971 | |
| 1972 | return fixP; |
| 1973 | } |
| 1974 | |
| 1975 | /* Return BFD reloc type from opinfo field in a fixS. |
| 1976 | It's tricky using fx_r_type in m32r_frob_file because the values |
| 1977 | are BFD_RELOC_UNUSED + operand number. */ |
| 1978 | #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo) |
| 1979 | |
| 1980 | /* Sort any unmatched HI16 relocs so that they immediately precede |
| 1981 | the corresponding LO16 reloc. This is called before md_apply_fix3 and |
| 1982 | tc_gen_reloc. */ |
| 1983 | |
| 1984 | void |
| 1985 | m32r_frob_file () |
| 1986 | { |
| 1987 | struct m32r_hi_fixup *l; |
| 1988 | |
| 1989 | for (l = m32r_hi_fixup_list; l != NULL; l = l->next) |
| 1990 | { |
| 1991 | segment_info_type *seginfo; |
| 1992 | int pass; |
| 1993 | |
| 1994 | assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO |
| 1995 | || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO); |
| 1996 | |
| 1997 | /* Check quickly whether the next fixup happens to be a matching low. */ |
| 1998 | if (l->fixp->fx_next != NULL |
| 1999 | && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16 |
| 2000 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy |
| 2001 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) |
| 2002 | continue; |
| 2003 | |
| 2004 | /* Look through the fixups for this segment for a matching `low'. |
| 2005 | When we find one, move the high/shigh just in front of it. We do |
| 2006 | this in two passes. In the first pass, we try to find a |
| 2007 | unique `low'. In the second pass, we permit multiple high's |
| 2008 | relocs for a single `low'. */ |
| 2009 | seginfo = seg_info (l->seg); |
| 2010 | for (pass = 0; pass < 2; pass++) |
| 2011 | { |
| 2012 | fixS *f; |
| 2013 | fixS *prev; |
| 2014 | |
| 2015 | prev = NULL; |
| 2016 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) |
| 2017 | { |
| 2018 | /* Check whether this is a `low' fixup which matches l->fixp. */ |
| 2019 | if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16 |
| 2020 | && f->fx_addsy == l->fixp->fx_addsy |
| 2021 | && f->fx_offset == l->fixp->fx_offset |
| 2022 | && (pass == 1 |
| 2023 | || prev == NULL |
| 2024 | || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO |
| 2025 | && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO) |
| 2026 | || prev->fx_addsy != f->fx_addsy |
| 2027 | || prev->fx_offset != f->fx_offset)) |
| 2028 | { |
| 2029 | fixS **pf; |
| 2030 | |
| 2031 | /* Move l->fixp before f. */ |
| 2032 | for (pf = &seginfo->fix_root; |
| 2033 | *pf != l->fixp; |
| 2034 | pf = & (*pf)->fx_next) |
| 2035 | assert (*pf != NULL); |
| 2036 | |
| 2037 | *pf = l->fixp->fx_next; |
| 2038 | |
| 2039 | l->fixp->fx_next = f; |
| 2040 | if (prev == NULL) |
| 2041 | seginfo->fix_root = l->fixp; |
| 2042 | else |
| 2043 | prev->fx_next = l->fixp; |
| 2044 | |
| 2045 | break; |
| 2046 | } |
| 2047 | |
| 2048 | prev = f; |
| 2049 | } |
| 2050 | |
| 2051 | if (f != NULL) |
| 2052 | break; |
| 2053 | |
| 2054 | if (pass == 1 |
| 2055 | && warn_unmatched_high) |
| 2056 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, |
| 2057 | _("Unmatched high/shigh reloc")); |
| 2058 | } |
| 2059 | } |
| 2060 | } |
| 2061 | |
| 2062 | /* See whether we need to force a relocation into the output file. |
| 2063 | This is used to force out switch and PC relative relocations when |
| 2064 | relaxing. */ |
| 2065 | |
| 2066 | int |
| 2067 | m32r_force_relocation (fix) |
| 2068 | fixS *fix; |
| 2069 | { |
| 2070 | if (generic_force_reloc (fix)) |
| 2071 | return 1; |
| 2072 | |
| 2073 | if (! m32r_relax) |
| 2074 | return 0; |
| 2075 | |
| 2076 | return fix->fx_pcrel; |
| 2077 | } |
| 2078 | \f |
| 2079 | /* Write a value out to the object file, using the appropriate endianness. */ |
| 2080 | |
| 2081 | void |
| 2082 | md_number_to_chars (buf, val, n) |
| 2083 | char *buf; |
| 2084 | valueT val; |
| 2085 | int n; |
| 2086 | { |
| 2087 | if (target_big_endian) |
| 2088 | number_to_chars_bigendian (buf, val, n); |
| 2089 | else |
| 2090 | number_to_chars_littleendian (buf, val, n); |
| 2091 | } |
| 2092 | |
| 2093 | /* Turn a string in input_line_pointer into a floating point constant |
| 2094 | of type TYPE, and store the appropriate bytes in *LITP. The number |
| 2095 | of LITTLENUMS emitted is stored in *SIZEP. An error message is |
| 2096 | returned, or NULL on OK. */ |
| 2097 | |
| 2098 | /* Equal to MAX_PRECISION in atof-ieee.c. */ |
| 2099 | #define MAX_LITTLENUMS 6 |
| 2100 | |
| 2101 | char * |
| 2102 | md_atof (type, litP, sizeP) |
| 2103 | char type; |
| 2104 | char *litP; |
| 2105 | int *sizeP; |
| 2106 | { |
| 2107 | int i; |
| 2108 | int prec; |
| 2109 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
| 2110 | char *t; |
| 2111 | |
| 2112 | switch (type) |
| 2113 | { |
| 2114 | case 'f': |
| 2115 | case 'F': |
| 2116 | case 's': |
| 2117 | case 'S': |
| 2118 | prec = 2; |
| 2119 | break; |
| 2120 | |
| 2121 | case 'd': |
| 2122 | case 'D': |
| 2123 | case 'r': |
| 2124 | case 'R': |
| 2125 | prec = 4; |
| 2126 | break; |
| 2127 | |
| 2128 | /* FIXME: Some targets allow other format chars for bigger sizes |
| 2129 | here. */ |
| 2130 | |
| 2131 | default: |
| 2132 | *sizeP = 0; |
| 2133 | return _("Bad call to md_atof()"); |
| 2134 | } |
| 2135 | |
| 2136 | t = atof_ieee (input_line_pointer, type, words); |
| 2137 | if (t) |
| 2138 | input_line_pointer = t; |
| 2139 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
| 2140 | |
| 2141 | if (target_big_endian) |
| 2142 | { |
| 2143 | for (i = 0; i < prec; i++) |
| 2144 | { |
| 2145 | md_number_to_chars (litP, (valueT) words[i], |
| 2146 | sizeof (LITTLENUM_TYPE)); |
| 2147 | litP += sizeof (LITTLENUM_TYPE); |
| 2148 | } |
| 2149 | } |
| 2150 | else |
| 2151 | { |
| 2152 | for (i = prec - 1; i >= 0; i--) |
| 2153 | { |
| 2154 | md_number_to_chars (litP, (valueT) words[i], |
| 2155 | sizeof (LITTLENUM_TYPE)); |
| 2156 | litP += sizeof (LITTLENUM_TYPE); |
| 2157 | } |
| 2158 | } |
| 2159 | |
| 2160 | return 0; |
| 2161 | } |
| 2162 | |
| 2163 | void |
| 2164 | m32r_elf_section_change_hook () |
| 2165 | { |
| 2166 | /* If we have reached the end of a section and we have just emitted a |
| 2167 | 16 bit insn, then emit a nop to make sure that the section ends on |
| 2168 | a 32 bit boundary. */ |
| 2169 | |
| 2170 | if (prev_insn.insn || seen_relaxable_p) |
| 2171 | (void) m32r_fill_insn (0); |
| 2172 | } |
| 2173 | |
| 2174 | /* Return true if can adjust the reloc to be relative to its section |
| 2175 | (such as .data) instead of relative to some symbol. */ |
| 2176 | |
| 2177 | bfd_boolean |
| 2178 | m32r_fix_adjustable (fixP) |
| 2179 | fixS *fixP; |
| 2180 | { |
| 2181 | bfd_reloc_code_real_type reloc_type; |
| 2182 | |
| 2183 | if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED) |
| 2184 | { |
| 2185 | const CGEN_INSN *insn = NULL; |
| 2186 | int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED; |
| 2187 | const CGEN_OPERAND *operand = |
| 2188 | cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex); |
| 2189 | reloc_type = md_cgen_lookup_reloc (insn, operand, fixP); |
| 2190 | } |
| 2191 | else |
| 2192 | reloc_type = fixP->fx_r_type; |
| 2193 | |
| 2194 | /* We need the symbol name for the VTABLE entries. */ |
| 2195 | if (reloc_type == BFD_RELOC_VTABLE_INHERIT |
| 2196 | || reloc_type == BFD_RELOC_VTABLE_ENTRY) |
| 2197 | return 0; |
| 2198 | |
| 2199 | return 1; |
| 2200 | } |
| 2201 | |
| 2202 | void |
| 2203 | m32r_elf_final_processing () |
| 2204 | { |
| 2205 | if (use_parallel) |
| 2206 | m32r_flags |= E_M32R_HAS_PARALLEL; |
| 2207 | elf_elfheader (stdoutput)->e_flags |= m32r_flags; |
| 2208 | } |