| 1 | /* tc-m68k.c -- Assemble for the m68k family |
| 2 | Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
| 3 | 2000, 2001 |
| 4 | Free Software Foundation, Inc. |
| 5 | |
| 6 | This file is part of GAS, the GNU Assembler. |
| 7 | |
| 8 | GAS is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU General Public License as published by |
| 10 | the Free Software Foundation; either version 2, or (at your option) |
| 11 | any later version. |
| 12 | |
| 13 | GAS is distributed in the hope that it will be useful, |
| 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | GNU General Public License for more details. |
| 17 | |
| 18 | You should have received a copy of the GNU General Public License |
| 19 | along with GAS; see the file COPYING. If not, write to the Free |
| 20 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA |
| 21 | 02111-1307, USA. */ |
| 22 | |
| 23 | #include "as.h" |
| 24 | #include "safe-ctype.h" |
| 25 | #include "obstack.h" |
| 26 | #include "subsegs.h" |
| 27 | #include "dwarf2dbg.h" |
| 28 | |
| 29 | #include "opcode/m68k.h" |
| 30 | #include "m68k-parse.h" |
| 31 | |
| 32 | #if defined (OBJ_ELF) |
| 33 | #include "elf/m68k.h" |
| 34 | #endif |
| 35 | |
| 36 | /* This string holds the chars that always start a comment. If the |
| 37 | pre-processor is disabled, these aren't very useful. The macro |
| 38 | tc_comment_chars points to this. We use this, rather than the |
| 39 | usual comment_chars, so that the --bitwise-or option will work. */ |
| 40 | #if defined (TE_SVR4) || defined (TE_DELTA) |
| 41 | const char *m68k_comment_chars = "|#"; |
| 42 | #else |
| 43 | const char *m68k_comment_chars = "|"; |
| 44 | #endif |
| 45 | |
| 46 | /* This array holds the chars that only start a comment at the beginning of |
| 47 | a line. If the line seems to have the form '# 123 filename' |
| 48 | .line and .file directives will appear in the pre-processed output */ |
| 49 | /* Note that input_file.c hand checks for '#' at the beginning of the |
| 50 | first line of the input file. This is because the compiler outputs |
| 51 | #NO_APP at the beginning of its output. */ |
| 52 | /* Also note that comments like this one will always work. */ |
| 53 | const char line_comment_chars[] = "#*"; |
| 54 | |
| 55 | const char line_separator_chars[] = ";"; |
| 56 | |
| 57 | /* Chars that can be used to separate mant from exp in floating point nums */ |
| 58 | CONST char EXP_CHARS[] = "eE"; |
| 59 | |
| 60 | /* Chars that mean this number is a floating point constant, as |
| 61 | in "0f12.456" or "0d1.2345e12". */ |
| 62 | |
| 63 | CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
| 64 | |
| 65 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be |
| 66 | changed in read.c . Ideally it shouldn't have to know about it at all, |
| 67 | but nothing is ideal around here. */ |
| 68 | |
| 69 | const int md_reloc_size = 8; /* Size of relocation record */ |
| 70 | |
| 71 | /* Are we trying to generate PIC code? If so, absolute references |
| 72 | ought to be made into linkage table references or pc-relative |
| 73 | references. Not implemented. For ELF there are other means |
| 74 | to denote pic relocations. */ |
| 75 | int flag_want_pic; |
| 76 | |
| 77 | static int flag_short_refs; /* -l option */ |
| 78 | static int flag_long_jumps; /* -S option */ |
| 79 | static int flag_keep_pcrel; /* --pcrel option. */ |
| 80 | |
| 81 | #ifdef REGISTER_PREFIX_OPTIONAL |
| 82 | int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL; |
| 83 | #else |
| 84 | int flag_reg_prefix_optional; |
| 85 | #endif |
| 86 | |
| 87 | /* Whether --register-prefix-optional was used on the command line. */ |
| 88 | static int reg_prefix_optional_seen; |
| 89 | |
| 90 | /* The floating point coprocessor to use by default. */ |
| 91 | static enum m68k_register m68k_float_copnum = COP1; |
| 92 | |
| 93 | /* If this is non-zero, then references to number(%pc) will be taken |
| 94 | to refer to number, rather than to %pc + number. */ |
| 95 | static int m68k_abspcadd; |
| 96 | |
| 97 | /* If this is non-zero, then the quick forms of the move, add, and sub |
| 98 | instructions are used when possible. */ |
| 99 | static int m68k_quick = 1; |
| 100 | |
| 101 | /* If this is non-zero, then if the size is not specified for a base |
| 102 | or outer displacement, the assembler assumes that the size should |
| 103 | be 32 bits. */ |
| 104 | static int m68k_rel32 = 1; |
| 105 | |
| 106 | /* This is non-zero if m68k_rel32 was set from the command line. */ |
| 107 | static int m68k_rel32_from_cmdline; |
| 108 | |
| 109 | /* The default width to use for an index register when using a base |
| 110 | displacement. */ |
| 111 | static enum m68k_size m68k_index_width_default = SIZE_LONG; |
| 112 | |
| 113 | /* We want to warn if any text labels are misaligned. In order to get |
| 114 | the right line number, we need to record the line number for each |
| 115 | label. */ |
| 116 | |
| 117 | struct label_line |
| 118 | { |
| 119 | struct label_line *next; |
| 120 | symbolS *label; |
| 121 | char *file; |
| 122 | unsigned int line; |
| 123 | int text; |
| 124 | }; |
| 125 | |
| 126 | /* The list of labels. */ |
| 127 | |
| 128 | static struct label_line *labels; |
| 129 | |
| 130 | /* The current label. */ |
| 131 | |
| 132 | static struct label_line *current_label; |
| 133 | |
| 134 | /* Its an arbitrary name: This means I don't approve of it */ |
| 135 | /* See flames below */ |
| 136 | static struct obstack robyn; |
| 137 | |
| 138 | struct m68k_incant |
| 139 | { |
| 140 | const char *m_operands; |
| 141 | unsigned long m_opcode; |
| 142 | short m_opnum; |
| 143 | short m_codenum; |
| 144 | int m_arch; |
| 145 | struct m68k_incant *m_next; |
| 146 | }; |
| 147 | |
| 148 | #define getone(x) ((((x)->m_opcode)>>16)&0xffff) |
| 149 | #define gettwo(x) (((x)->m_opcode)&0xffff) |
| 150 | |
| 151 | static const enum m68k_register m68000_control_regs[] = { 0 }; |
| 152 | static const enum m68k_register m68010_control_regs[] = { |
| 153 | SFC, DFC, USP, VBR, |
| 154 | 0 |
| 155 | }; |
| 156 | static const enum m68k_register m68020_control_regs[] = { |
| 157 | SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP, |
| 158 | 0 |
| 159 | }; |
| 160 | static const enum m68k_register m68040_control_regs[] = { |
| 161 | SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, |
| 162 | USP, VBR, MSP, ISP, MMUSR, URP, SRP, |
| 163 | 0 |
| 164 | }; |
| 165 | static const enum m68k_register m68060_control_regs[] = { |
| 166 | SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, |
| 167 | USP, VBR, URP, SRP, PCR, |
| 168 | 0 |
| 169 | }; |
| 170 | static const enum m68k_register mcf_control_regs[] = { |
| 171 | CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR, |
| 172 | RAMBAR0, RAMBAR1, MBAR, |
| 173 | 0 |
| 174 | }; |
| 175 | #define cpu32_control_regs m68010_control_regs |
| 176 | |
| 177 | static const enum m68k_register *control_regs; |
| 178 | |
| 179 | /* internal form of a 68020 instruction */ |
| 180 | struct m68k_it |
| 181 | { |
| 182 | const char *error; |
| 183 | const char *args; /* list of opcode info */ |
| 184 | int numargs; |
| 185 | |
| 186 | int numo; /* Number of shorts in opcode */ |
| 187 | short opcode[11]; |
| 188 | |
| 189 | struct m68k_op operands[6]; |
| 190 | |
| 191 | int nexp; /* number of exprs in use */ |
| 192 | struct m68k_exp exprs[4]; |
| 193 | |
| 194 | int nfrag; /* Number of frags we have to produce */ |
| 195 | struct |
| 196 | { |
| 197 | int fragoff; /* Where in the current opcode the frag ends */ |
| 198 | symbolS *fadd; |
| 199 | offsetT foff; |
| 200 | int fragty; |
| 201 | } |
| 202 | fragb[4]; |
| 203 | |
| 204 | int nrel; /* Num of reloc strucs in use */ |
| 205 | struct |
| 206 | { |
| 207 | int n; |
| 208 | expressionS exp; |
| 209 | char wid; |
| 210 | char pcrel; |
| 211 | /* In a pc relative address the difference between the address |
| 212 | of the offset and the address that the offset is relative |
| 213 | to. This depends on the addressing mode. Basically this |
| 214 | is the value to put in the offset field to address the |
| 215 | first byte of the offset, without regarding the special |
| 216 | significance of some values (in the branch instruction, for |
| 217 | example). */ |
| 218 | int pcrel_fix; |
| 219 | #ifdef OBJ_ELF |
| 220 | /* Whether this expression needs special pic relocation, and if |
| 221 | so, which. */ |
| 222 | enum pic_relocation pic_reloc; |
| 223 | #endif |
| 224 | } |
| 225 | reloc[5]; /* Five is enough??? */ |
| 226 | }; |
| 227 | |
| 228 | #define cpu_of_arch(x) ((x) & (m68000up|mcf)) |
| 229 | #define float_of_arch(x) ((x) & mfloat) |
| 230 | #define mmu_of_arch(x) ((x) & mmmu) |
| 231 | #define arch_coldfire_p(x) (((x) & mcf) != 0) |
| 232 | |
| 233 | /* Macros for determining if cpu supports a specific addressing mode */ |
| 234 | #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407)) |
| 235 | |
| 236 | static struct m68k_it the_ins; /* the instruction being assembled */ |
| 237 | |
| 238 | #define op(ex) ((ex)->exp.X_op) |
| 239 | #define adds(ex) ((ex)->exp.X_add_symbol) |
| 240 | #define subs(ex) ((ex)->exp.X_op_symbol) |
| 241 | #define offs(ex) ((ex)->exp.X_add_number) |
| 242 | |
| 243 | /* Macros for adding things to the m68k_it struct */ |
| 244 | |
| 245 | #define addword(w) the_ins.opcode[the_ins.numo++]=(w) |
| 246 | |
| 247 | /* Static functions. */ |
| 248 | |
| 249 | static void insop PARAMS ((int, const struct m68k_incant *)); |
| 250 | static void add_fix PARAMS ((int, struct m68k_exp *, int, int)); |
| 251 | static void add_frag PARAMS ((symbolS *, offsetT, int)); |
| 252 | |
| 253 | /* Like addword, but goes BEFORE general operands */ |
| 254 | static void |
| 255 | insop (w, opcode) |
| 256 | int w; |
| 257 | const struct m68k_incant *opcode; |
| 258 | { |
| 259 | int z; |
| 260 | for (z = the_ins.numo; z > opcode->m_codenum; --z) |
| 261 | the_ins.opcode[z]=the_ins.opcode[z-1]; |
| 262 | for (z = 0;z < the_ins.nrel; z++) |
| 263 | the_ins.reloc[z].n+=2; |
| 264 | for (z = 0; z < the_ins.nfrag; z++) |
| 265 | the_ins.fragb[z].fragoff++; |
| 266 | the_ins.opcode[opcode->m_codenum]=w; |
| 267 | the_ins.numo++; |
| 268 | } |
| 269 | |
| 270 | /* The numo+1 kludge is so we can hit the low order byte of the prev word. |
| 271 | Blecch. */ |
| 272 | static void |
| 273 | add_fix (width, exp, pc_rel, pc_fix) |
| 274 | int width; |
| 275 | struct m68k_exp *exp; |
| 276 | int pc_rel; |
| 277 | int pc_fix; |
| 278 | { |
| 279 | the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3') |
| 280 | ? (the_ins.numo*2-1) |
| 281 | : (((width)=='b') |
| 282 | ? (the_ins.numo*2+1) |
| 283 | : (the_ins.numo*2))); |
| 284 | the_ins.reloc[the_ins.nrel].exp = exp->exp; |
| 285 | the_ins.reloc[the_ins.nrel].wid = width; |
| 286 | the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix; |
| 287 | #ifdef OBJ_ELF |
| 288 | the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc; |
| 289 | #endif |
| 290 | the_ins.reloc[the_ins.nrel++].pcrel = pc_rel; |
| 291 | } |
| 292 | |
| 293 | /* Cause an extra frag to be generated here, inserting up to 10 bytes |
| 294 | (that value is chosen in the frag_var call in md_assemble). TYPE |
| 295 | is the subtype of the frag to be generated; its primary type is |
| 296 | rs_machine_dependent. |
| 297 | |
| 298 | The TYPE parameter is also used by md_convert_frag_1 and |
| 299 | md_estimate_size_before_relax. The appropriate type of fixup will |
| 300 | be emitted by md_convert_frag_1. |
| 301 | |
| 302 | ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */ |
| 303 | static void |
| 304 | add_frag (add, off, type) |
| 305 | symbolS *add; |
| 306 | offsetT off; |
| 307 | int type; |
| 308 | { |
| 309 | the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo; |
| 310 | the_ins.fragb[the_ins.nfrag].fadd=add; |
| 311 | the_ins.fragb[the_ins.nfrag].foff=off; |
| 312 | the_ins.fragb[the_ins.nfrag++].fragty=type; |
| 313 | } |
| 314 | |
| 315 | #define isvar(ex) \ |
| 316 | (op (ex) != O_constant && op (ex) != O_big) |
| 317 | |
| 318 | static char *crack_operand PARAMS ((char *str, struct m68k_op *opP)); |
| 319 | static int get_num PARAMS ((struct m68k_exp *exp, int ok)); |
| 320 | static void m68k_ip PARAMS ((char *)); |
| 321 | static void insert_reg PARAMS ((const char *, int)); |
| 322 | static void select_control_regs PARAMS ((void)); |
| 323 | static void init_regtable PARAMS ((void)); |
| 324 | static int reverse_16_bits PARAMS ((int in)); |
| 325 | static int reverse_8_bits PARAMS ((int in)); |
| 326 | static void install_gen_operand PARAMS ((int mode, int val)); |
| 327 | static void install_operand PARAMS ((int mode, int val)); |
| 328 | static void s_bss PARAMS ((int)); |
| 329 | static void s_data1 PARAMS ((int)); |
| 330 | static void s_data2 PARAMS ((int)); |
| 331 | static void s_even PARAMS ((int)); |
| 332 | static void s_proc PARAMS ((int)); |
| 333 | static void mri_chip PARAMS ((void)); |
| 334 | static void s_chip PARAMS ((int)); |
| 335 | static void s_fopt PARAMS ((int)); |
| 336 | static void s_opt PARAMS ((int)); |
| 337 | static void s_reg PARAMS ((int)); |
| 338 | static void s_restore PARAMS ((int)); |
| 339 | static void s_save PARAMS ((int)); |
| 340 | static void s_mri_if PARAMS ((int)); |
| 341 | static void s_mri_else PARAMS ((int)); |
| 342 | static void s_mri_endi PARAMS ((int)); |
| 343 | static void s_mri_break PARAMS ((int)); |
| 344 | static void s_mri_next PARAMS ((int)); |
| 345 | static void s_mri_for PARAMS ((int)); |
| 346 | static void s_mri_endf PARAMS ((int)); |
| 347 | static void s_mri_repeat PARAMS ((int)); |
| 348 | static void s_mri_until PARAMS ((int)); |
| 349 | static void s_mri_while PARAMS ((int)); |
| 350 | static void s_mri_endw PARAMS ((int)); |
| 351 | static void md_convert_frag_1 PARAMS ((fragS *)); |
| 352 | |
| 353 | static int current_architecture; |
| 354 | |
| 355 | struct m68k_cpu |
| 356 | { |
| 357 | unsigned long arch; |
| 358 | const char *name; |
| 359 | int alias; |
| 360 | }; |
| 361 | |
| 362 | static const struct m68k_cpu archs[] = |
| 363 | { |
| 364 | { m68000, "68000", 0 }, |
| 365 | { m68010, "68010", 0 }, |
| 366 | { m68020, "68020", 0 }, |
| 367 | { m68030, "68030", 0 }, |
| 368 | { m68040, "68040", 0 }, |
| 369 | { m68060, "68060", 0 }, |
| 370 | { cpu32, "cpu32", 0 }, |
| 371 | { m68881, "68881", 0 }, |
| 372 | { m68851, "68851", 0 }, |
| 373 | { mcf5200, "5200", 0 }, |
| 374 | { mcf5206e, "5206e", 0 }, |
| 375 | { mcf5307, "5307", 0}, |
| 376 | { mcf5407, "5407", 0}, |
| 377 | /* Aliases (effectively, so far as gas is concerned) for the above |
| 378 | cpus. */ |
| 379 | { m68020, "68k", 1 }, |
| 380 | { m68000, "68008", 1 }, |
| 381 | { m68000, "68302", 1 }, |
| 382 | { m68000, "68306", 1 }, |
| 383 | { m68000, "68307", 1 }, |
| 384 | { m68000, "68322", 1 }, |
| 385 | { m68000, "68356", 1 }, |
| 386 | { m68000, "68ec000", 1 }, |
| 387 | { m68000, "68hc000", 1 }, |
| 388 | { m68000, "68hc001", 1 }, |
| 389 | { m68020, "68ec020", 1 }, |
| 390 | { m68030, "68ec030", 1 }, |
| 391 | { m68040, "68ec040", 1 }, |
| 392 | { m68060, "68ec060", 1 }, |
| 393 | { cpu32, "68330", 1 }, |
| 394 | { cpu32, "68331", 1 }, |
| 395 | { cpu32, "68332", 1 }, |
| 396 | { cpu32, "68333", 1 }, |
| 397 | { cpu32, "68334", 1 }, |
| 398 | { cpu32, "68336", 1 }, |
| 399 | { cpu32, "68340", 1 }, |
| 400 | { cpu32, "68341", 1 }, |
| 401 | { cpu32, "68349", 1 }, |
| 402 | { cpu32, "68360", 1 }, |
| 403 | { m68881, "68882", 1 }, |
| 404 | { mcf5200, "5202", 1 }, |
| 405 | { mcf5200, "5204", 1 }, |
| 406 | { mcf5200, "5206", 1 }, |
| 407 | }; |
| 408 | |
| 409 | static const int n_archs = sizeof (archs) / sizeof (archs[0]); |
| 410 | |
| 411 | /* This is the assembler relaxation table for m68k. m68k is a rich CISC |
| 412 | architecture and we have a lot of relaxation modes. */ |
| 413 | |
| 414 | /* Macros used in the relaxation code. */ |
| 415 | #define TAB(x,y) (((x) << 2) + (y)) |
| 416 | #define TABTYPE(x) ((x) >> 2) |
| 417 | |
| 418 | /* Relaxation states. */ |
| 419 | #define BYTE 0 |
| 420 | #define SHORT 1 |
| 421 | #define LONG 2 |
| 422 | #define SZ_UNDEF 3 |
| 423 | |
| 424 | /* Here are all the relaxation modes we support. First we can relax ordinary |
| 425 | branches. On 68020 and higher and on CPU32 all branch instructions take |
| 426 | three forms, so on these CPUs all branches always remain as such. When we |
| 427 | have to expand to the LONG form on a 68000, though, we substitute an |
| 428 | absolute jump instead. This is a direct replacement for unconditional |
| 429 | branches and a branch over a jump for conditional branches. However, if the |
| 430 | user requires PIC and disables this with --pcrel, we can only relax between |
| 431 | BYTE and SHORT forms, punting if that isn't enough. This gives us four |
| 432 | different relaxation modes for branches: */ |
| 433 | |
| 434 | #define BRANCHBWL 0 /* branch byte, word, or long */ |
| 435 | #define BRABSJUNC 1 /* absolute jump for LONG, unconditional */ |
| 436 | #define BRABSJCOND 2 /* absolute jump for LONG, conditional */ |
| 437 | #define BRANCHBW 3 /* branch byte or word */ |
| 438 | |
| 439 | /* We also relax coprocessor branches and DBcc's. All CPUs that support |
| 440 | coprocessor branches support them in word and long forms, so we have only |
| 441 | one relaxation mode for them. DBcc's are word only on all CPUs. We can |
| 442 | relax them to the LONG form with a branch-around sequence. This sequence |
| 443 | can use a long branch (if available) or an absolute jump (if acceptable). |
| 444 | This gives us two relaxation modes. If long branches are not available and |
| 445 | absolute jumps are not acceptable, we don't relax DBcc's. */ |
| 446 | |
| 447 | #define FBRANCH 4 /* coprocessor branch */ |
| 448 | #define DBCCLBR 5 /* DBcc relaxable with a long branch */ |
| 449 | #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump */ |
| 450 | |
| 451 | /* That's all for instruction relaxation. However, we also relax PC-relative |
| 452 | operands. Specifically, we have three operand relaxation modes. On the |
| 453 | 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and |
| 454 | on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the |
| 455 | two. Also PC+displacement+index operands in their simple form (with a non- |
| 456 | suppressed index without memory indirection) are supported on all CPUs, but |
| 457 | on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher |
| 458 | and on CPU32 we relax it to SHORT and LONG forms as well using the extended |
| 459 | form of the PC+displacement+index operand. Finally, some absolute operands |
| 460 | can be relaxed down to 16-bit PC-relative. */ |
| 461 | |
| 462 | #define PCREL1632 7 /* 16-bit or 32-bit PC-relative */ |
| 463 | #define PCINDEX 8 /* PC+displacement+index */ |
| 464 | #define ABSTOPCREL 9 /* absolute relax down to 16-bit PC-relative */ |
| 465 | |
| 466 | /* Note that calls to frag_var need to specify the maximum expansion |
| 467 | needed; this is currently 10 bytes for DBCC. */ |
| 468 | |
| 469 | /* The fields are: |
| 470 | How far Forward this mode will reach: |
| 471 | How far Backward this mode will reach: |
| 472 | How many bytes this mode will add to the size of the frag |
| 473 | Which mode to go to if the offset won't fit in this one |
| 474 | |
| 475 | Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */ |
| 476 | relax_typeS md_relax_table[] = |
| 477 | { |
| 478 | { 127, -128, 0, TAB (BRANCHBWL, SHORT) }, |
| 479 | { 32767, -32768, 2, TAB (BRANCHBWL, LONG) }, |
| 480 | { 0, 0, 4, 0 }, |
| 481 | { 1, 1, 0, 0 }, |
| 482 | |
| 483 | { 127, -128, 0, TAB (BRABSJUNC, SHORT) }, |
| 484 | { 32767, -32768, 2, TAB (BRABSJUNC, LONG) }, |
| 485 | { 0, 0, 4, 0 }, |
| 486 | { 1, 1, 0, 0 }, |
| 487 | |
| 488 | { 127, -128, 0, TAB (BRABSJCOND, SHORT) }, |
| 489 | { 32767, -32768, 2, TAB (BRABSJCOND, LONG) }, |
| 490 | { 0, 0, 6, 0 }, |
| 491 | { 1, 1, 0, 0 }, |
| 492 | |
| 493 | { 127, -128, 0, TAB (BRANCHBW, SHORT) }, |
| 494 | { 0, 0, 2, 0 }, |
| 495 | { 1, 1, 0, 0 }, |
| 496 | { 1, 1, 0, 0 }, |
| 497 | |
| 498 | { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */ |
| 499 | { 32767, -32768, 2, TAB (FBRANCH, LONG) }, |
| 500 | { 0, 0, 4, 0 }, |
| 501 | { 1, 1, 0, 0 }, |
| 502 | |
| 503 | { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */ |
| 504 | { 32767, -32768, 2, TAB (DBCCLBR, LONG) }, |
| 505 | { 0, 0, 10, 0 }, |
| 506 | { 1, 1, 0, 0 }, |
| 507 | |
| 508 | { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */ |
| 509 | { 32767, -32768, 2, TAB (DBCCABSJ, LONG) }, |
| 510 | { 0, 0, 10, 0 }, |
| 511 | { 1, 1, 0, 0 }, |
| 512 | |
| 513 | { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE */ |
| 514 | { 32767, -32768, 2, TAB (PCREL1632, LONG) }, |
| 515 | { 0, 0, 6, 0 }, |
| 516 | { 1, 1, 0, 0 }, |
| 517 | |
| 518 | { 125, -130, 0, TAB (PCINDEX, SHORT) }, |
| 519 | { 32765, -32770, 2, TAB (PCINDEX, LONG) }, |
| 520 | { 0, 0, 4, 0 }, |
| 521 | { 1, 1, 0, 0 }, |
| 522 | |
| 523 | { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE */ |
| 524 | { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) }, |
| 525 | { 0, 0, 4, 0 }, |
| 526 | { 1, 1, 0, 0 }, |
| 527 | }; |
| 528 | |
| 529 | /* These are the machine dependent pseudo-ops. These are included so |
| 530 | the assembler can work on the output from the SUN C compiler, which |
| 531 | generates these. |
| 532 | */ |
| 533 | |
| 534 | /* This table describes all the machine specific pseudo-ops the assembler |
| 535 | has to support. The fields are: |
| 536 | pseudo-op name without dot |
| 537 | function to call to execute this pseudo-op |
| 538 | Integer arg to pass to the function |
| 539 | */ |
| 540 | const pseudo_typeS md_pseudo_table[] = |
| 541 | { |
| 542 | {"data1", s_data1, 0}, |
| 543 | {"data2", s_data2, 0}, |
| 544 | {"bss", s_bss, 0}, |
| 545 | {"even", s_even, 0}, |
| 546 | {"skip", s_space, 0}, |
| 547 | {"proc", s_proc, 0}, |
| 548 | #if defined (TE_SUN3) || defined (OBJ_ELF) |
| 549 | {"align", s_align_bytes, 0}, |
| 550 | #endif |
| 551 | #ifdef OBJ_ELF |
| 552 | {"swbeg", s_ignore, 0}, |
| 553 | #endif |
| 554 | {"extend", float_cons, 'x'}, |
| 555 | {"ldouble", float_cons, 'x'}, |
| 556 | |
| 557 | #ifdef OBJ_ELF |
| 558 | /* Dwarf2 support for Gcc. */ |
| 559 | {"file", dwarf2_directive_file, 0}, |
| 560 | {"loc", dwarf2_directive_loc, 0}, |
| 561 | #endif |
| 562 | |
| 563 | /* The following pseudo-ops are supported for MRI compatibility. */ |
| 564 | {"chip", s_chip, 0}, |
| 565 | {"comline", s_space, 1}, |
| 566 | {"fopt", s_fopt, 0}, |
| 567 | {"mask2", s_ignore, 0}, |
| 568 | {"opt", s_opt, 0}, |
| 569 | {"reg", s_reg, 0}, |
| 570 | {"restore", s_restore, 0}, |
| 571 | {"save", s_save, 0}, |
| 572 | |
| 573 | {"if", s_mri_if, 0}, |
| 574 | {"if.b", s_mri_if, 'b'}, |
| 575 | {"if.w", s_mri_if, 'w'}, |
| 576 | {"if.l", s_mri_if, 'l'}, |
| 577 | {"else", s_mri_else, 0}, |
| 578 | {"else.s", s_mri_else, 's'}, |
| 579 | {"else.l", s_mri_else, 'l'}, |
| 580 | {"endi", s_mri_endi, 0}, |
| 581 | {"break", s_mri_break, 0}, |
| 582 | {"break.s", s_mri_break, 's'}, |
| 583 | {"break.l", s_mri_break, 'l'}, |
| 584 | {"next", s_mri_next, 0}, |
| 585 | {"next.s", s_mri_next, 's'}, |
| 586 | {"next.l", s_mri_next, 'l'}, |
| 587 | {"for", s_mri_for, 0}, |
| 588 | {"for.b", s_mri_for, 'b'}, |
| 589 | {"for.w", s_mri_for, 'w'}, |
| 590 | {"for.l", s_mri_for, 'l'}, |
| 591 | {"endf", s_mri_endf, 0}, |
| 592 | {"repeat", s_mri_repeat, 0}, |
| 593 | {"until", s_mri_until, 0}, |
| 594 | {"until.b", s_mri_until, 'b'}, |
| 595 | {"until.w", s_mri_until, 'w'}, |
| 596 | {"until.l", s_mri_until, 'l'}, |
| 597 | {"while", s_mri_while, 0}, |
| 598 | {"while.b", s_mri_while, 'b'}, |
| 599 | {"while.w", s_mri_while, 'w'}, |
| 600 | {"while.l", s_mri_while, 'l'}, |
| 601 | {"endw", s_mri_endw, 0}, |
| 602 | |
| 603 | {0, 0, 0} |
| 604 | }; |
| 605 | |
| 606 | /* The mote pseudo ops are put into the opcode table, since they |
| 607 | don't start with a . they look like opcodes to gas. |
| 608 | */ |
| 609 | |
| 610 | #ifdef M68KCOFF |
| 611 | extern void obj_coff_section PARAMS ((int)); |
| 612 | #endif |
| 613 | |
| 614 | CONST pseudo_typeS mote_pseudo_table[] = |
| 615 | { |
| 616 | |
| 617 | {"dcl", cons, 4}, |
| 618 | {"dc", cons, 2}, |
| 619 | {"dcw", cons, 2}, |
| 620 | {"dcb", cons, 1}, |
| 621 | |
| 622 | {"dsl", s_space, 4}, |
| 623 | {"ds", s_space, 2}, |
| 624 | {"dsw", s_space, 2}, |
| 625 | {"dsb", s_space, 1}, |
| 626 | |
| 627 | {"xdef", s_globl, 0}, |
| 628 | #ifdef OBJ_ELF |
| 629 | {"align", s_align_bytes, 0}, |
| 630 | #else |
| 631 | {"align", s_align_ptwo, 0}, |
| 632 | #endif |
| 633 | #ifdef M68KCOFF |
| 634 | {"sect", obj_coff_section, 0}, |
| 635 | {"section", obj_coff_section, 0}, |
| 636 | #endif |
| 637 | {0, 0, 0} |
| 638 | }; |
| 639 | |
| 640 | #define issbyte(x) ((x)>=-128 && (x)<=127) |
| 641 | #define isubyte(x) ((x)>=0 && (x)<=255) |
| 642 | #define issword(x) ((x)>=-32768 && (x)<=32767) |
| 643 | #define isuword(x) ((x)>=0 && (x)<=65535) |
| 644 | |
| 645 | #define isbyte(x) ((x)>= -255 && (x)<=255) |
| 646 | #define isword(x) ((x)>=-65536 && (x)<=65535) |
| 647 | #define islong(x) (1) |
| 648 | |
| 649 | extern char *input_line_pointer; |
| 650 | |
| 651 | static char notend_table[256]; |
| 652 | static char alt_notend_table[256]; |
| 653 | #define notend(s) \ |
| 654 | (! (notend_table[(unsigned char) *s] \ |
| 655 | || (*s == ':' \ |
| 656 | && alt_notend_table[(unsigned char) s[1]]))) |
| 657 | |
| 658 | #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER) |
| 659 | |
| 660 | #ifdef NO_PCREL_RELOCS |
| 661 | |
| 662 | int |
| 663 | make_pcrel_absolute(fixP, add_number) |
| 664 | fixS *fixP; |
| 665 | long *add_number; |
| 666 | { |
| 667 | register unsigned char *opcode = fixP->fx_frag->fr_opcode; |
| 668 | |
| 669 | /* rewrite the PC relative instructions to absolute address ones. |
| 670 | * these are rumoured to be faster, and the apollo linker refuses |
| 671 | * to deal with the PC relative relocations. |
| 672 | */ |
| 673 | if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */ |
| 674 | { |
| 675 | opcode[0] = 0x4e; |
| 676 | opcode[1] = 0xf9; |
| 677 | } |
| 678 | else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */ |
| 679 | { |
| 680 | opcode[0] = 0x4e; |
| 681 | opcode[1] = 0xb9; |
| 682 | } |
| 683 | else |
| 684 | as_fatal (_("Unknown PC relative instruction")); |
| 685 | *add_number -= 4; |
| 686 | return 0; |
| 687 | } |
| 688 | |
| 689 | #endif /* NO_PCREL_RELOCS */ |
| 690 | |
| 691 | short |
| 692 | tc_coff_fix2rtype (fixP) |
| 693 | fixS *fixP; |
| 694 | { |
| 695 | if (fixP->fx_tcbit && fixP->fx_size == 4) |
| 696 | return R_RELLONG_NEG; |
| 697 | #ifdef NO_PCREL_RELOCS |
| 698 | know (fixP->fx_pcrel == 0); |
| 699 | return (fixP->fx_size == 1 ? R_RELBYTE |
| 700 | : fixP->fx_size == 2 ? R_DIR16 |
| 701 | : R_DIR32); |
| 702 | #else |
| 703 | return (fixP->fx_pcrel ? |
| 704 | (fixP->fx_size == 1 ? R_PCRBYTE : |
| 705 | fixP->fx_size == 2 ? R_PCRWORD : |
| 706 | R_PCRLONG) : |
| 707 | (fixP->fx_size == 1 ? R_RELBYTE : |
| 708 | fixP->fx_size == 2 ? R_RELWORD : |
| 709 | R_RELLONG)); |
| 710 | #endif |
| 711 | } |
| 712 | |
| 713 | #endif |
| 714 | |
| 715 | #ifdef OBJ_ELF |
| 716 | |
| 717 | /* Return zero if the reference to SYMBOL from within the same segment may |
| 718 | be relaxed. */ |
| 719 | |
| 720 | /* On an ELF system, we can't relax an externally visible symbol, |
| 721 | because it may be overridden by a shared library. However, if |
| 722 | TARGET_OS is "elf", then we presume that we are assembling for an |
| 723 | embedded system, in which case we don't have to worry about shared |
| 724 | libraries, and we can relax any external sym. */ |
| 725 | |
| 726 | #define relaxable_symbol(symbol) \ |
| 727 | (!((S_IS_EXTERNAL (symbol) && strcmp (TARGET_OS, "elf") != 0) \ |
| 728 | || S_IS_WEAK (symbol))) |
| 729 | |
| 730 | /* Compute the relocation code for a fixup of SIZE bytes, using pc |
| 731 | relative relocation if PCREL is non-zero. PIC says whether a special |
| 732 | pic relocation was requested. */ |
| 733 | |
| 734 | static bfd_reloc_code_real_type get_reloc_code |
| 735 | PARAMS ((int, int, enum pic_relocation)); |
| 736 | |
| 737 | static bfd_reloc_code_real_type |
| 738 | get_reloc_code (size, pcrel, pic) |
| 739 | int size; |
| 740 | int pcrel; |
| 741 | enum pic_relocation pic; |
| 742 | { |
| 743 | switch (pic) |
| 744 | { |
| 745 | case pic_got_pcrel: |
| 746 | switch (size) |
| 747 | { |
| 748 | case 1: |
| 749 | return BFD_RELOC_8_GOT_PCREL; |
| 750 | case 2: |
| 751 | return BFD_RELOC_16_GOT_PCREL; |
| 752 | case 4: |
| 753 | return BFD_RELOC_32_GOT_PCREL; |
| 754 | } |
| 755 | break; |
| 756 | |
| 757 | case pic_got_off: |
| 758 | switch (size) |
| 759 | { |
| 760 | case 1: |
| 761 | return BFD_RELOC_8_GOTOFF; |
| 762 | case 2: |
| 763 | return BFD_RELOC_16_GOTOFF; |
| 764 | case 4: |
| 765 | return BFD_RELOC_32_GOTOFF; |
| 766 | } |
| 767 | break; |
| 768 | |
| 769 | case pic_plt_pcrel: |
| 770 | switch (size) |
| 771 | { |
| 772 | case 1: |
| 773 | return BFD_RELOC_8_PLT_PCREL; |
| 774 | case 2: |
| 775 | return BFD_RELOC_16_PLT_PCREL; |
| 776 | case 4: |
| 777 | return BFD_RELOC_32_PLT_PCREL; |
| 778 | } |
| 779 | break; |
| 780 | |
| 781 | case pic_plt_off: |
| 782 | switch (size) |
| 783 | { |
| 784 | case 1: |
| 785 | return BFD_RELOC_8_PLTOFF; |
| 786 | case 2: |
| 787 | return BFD_RELOC_16_PLTOFF; |
| 788 | case 4: |
| 789 | return BFD_RELOC_32_PLTOFF; |
| 790 | } |
| 791 | break; |
| 792 | |
| 793 | case pic_none: |
| 794 | if (pcrel) |
| 795 | { |
| 796 | switch (size) |
| 797 | { |
| 798 | case 1: |
| 799 | return BFD_RELOC_8_PCREL; |
| 800 | case 2: |
| 801 | return BFD_RELOC_16_PCREL; |
| 802 | case 4: |
| 803 | return BFD_RELOC_32_PCREL; |
| 804 | } |
| 805 | } |
| 806 | else |
| 807 | { |
| 808 | switch (size) |
| 809 | { |
| 810 | case 1: |
| 811 | return BFD_RELOC_8; |
| 812 | case 2: |
| 813 | return BFD_RELOC_16; |
| 814 | case 4: |
| 815 | return BFD_RELOC_32; |
| 816 | } |
| 817 | } |
| 818 | } |
| 819 | |
| 820 | if (pcrel) |
| 821 | { |
| 822 | if (pic == pic_none) |
| 823 | as_bad (_("Can not do %d byte pc-relative relocation"), size); |
| 824 | else |
| 825 | as_bad (_("Can not do %d byte pc-relative pic relocation"), size); |
| 826 | } |
| 827 | else |
| 828 | { |
| 829 | if (pic == pic_none) |
| 830 | as_bad (_("Can not do %d byte relocation"), size); |
| 831 | else |
| 832 | as_bad (_("Can not do %d byte pic relocation"), size); |
| 833 | } |
| 834 | |
| 835 | return BFD_RELOC_NONE; |
| 836 | } |
| 837 | |
| 838 | /* Here we decide which fixups can be adjusted to make them relative |
| 839 | to the beginning of the section instead of the symbol. Basically |
| 840 | we need to make sure that the dynamic relocations are done |
| 841 | correctly, so in some cases we force the original symbol to be |
| 842 | used. */ |
| 843 | int |
| 844 | tc_m68k_fix_adjustable (fixP) |
| 845 | fixS *fixP; |
| 846 | { |
| 847 | /* Prevent all adjustments to global symbols. */ |
| 848 | if (! relaxable_symbol (fixP->fx_addsy)) |
| 849 | return 0; |
| 850 | |
| 851 | /* adjust_reloc_syms doesn't know about the GOT */ |
| 852 | switch (fixP->fx_r_type) |
| 853 | { |
| 854 | case BFD_RELOC_8_GOT_PCREL: |
| 855 | case BFD_RELOC_16_GOT_PCREL: |
| 856 | case BFD_RELOC_32_GOT_PCREL: |
| 857 | case BFD_RELOC_8_GOTOFF: |
| 858 | case BFD_RELOC_16_GOTOFF: |
| 859 | case BFD_RELOC_32_GOTOFF: |
| 860 | case BFD_RELOC_8_PLT_PCREL: |
| 861 | case BFD_RELOC_16_PLT_PCREL: |
| 862 | case BFD_RELOC_32_PLT_PCREL: |
| 863 | case BFD_RELOC_8_PLTOFF: |
| 864 | case BFD_RELOC_16_PLTOFF: |
| 865 | case BFD_RELOC_32_PLTOFF: |
| 866 | return 0; |
| 867 | |
| 868 | case BFD_RELOC_VTABLE_INHERIT: |
| 869 | case BFD_RELOC_VTABLE_ENTRY: |
| 870 | return 0; |
| 871 | |
| 872 | default: |
| 873 | return 1; |
| 874 | } |
| 875 | } |
| 876 | |
| 877 | #else /* !OBJ_ELF */ |
| 878 | |
| 879 | #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC |
| 880 | |
| 881 | #define relaxable_symbol(symbol) 1 |
| 882 | |
| 883 | #endif /* OBJ_ELF */ |
| 884 | |
| 885 | #ifdef BFD_ASSEMBLER |
| 886 | |
| 887 | arelent * |
| 888 | tc_gen_reloc (section, fixp) |
| 889 | asection *section; |
| 890 | fixS *fixp; |
| 891 | { |
| 892 | arelent *reloc; |
| 893 | bfd_reloc_code_real_type code; |
| 894 | |
| 895 | /* If the tcbit is set, then this was a fixup of a negative value |
| 896 | that was never resolved. We do not have a reloc to handle this, |
| 897 | so just return. We assume that other code will have detected this |
| 898 | situation and produced a helpful error message, so we just tell the |
| 899 | user that the reloc cannot be produced. */ |
| 900 | if (fixp->fx_tcbit) |
| 901 | { |
| 902 | if (fixp->fx_addsy) |
| 903 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 904 | _("Unable to produce reloc against symbol '%s'"), |
| 905 | S_GET_NAME (fixp->fx_addsy)); |
| 906 | return NULL; |
| 907 | } |
| 908 | |
| 909 | if (fixp->fx_r_type != BFD_RELOC_NONE) |
| 910 | { |
| 911 | code = fixp->fx_r_type; |
| 912 | |
| 913 | /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible |
| 914 | that fixup_segment converted a non-PC relative reloc into a |
| 915 | PC relative reloc. In such a case, we need to convert the |
| 916 | reloc code. */ |
| 917 | if (fixp->fx_pcrel) |
| 918 | { |
| 919 | switch (code) |
| 920 | { |
| 921 | case BFD_RELOC_8: |
| 922 | code = BFD_RELOC_8_PCREL; |
| 923 | break; |
| 924 | case BFD_RELOC_16: |
| 925 | code = BFD_RELOC_16_PCREL; |
| 926 | break; |
| 927 | case BFD_RELOC_32: |
| 928 | code = BFD_RELOC_32_PCREL; |
| 929 | break; |
| 930 | case BFD_RELOC_8_PCREL: |
| 931 | case BFD_RELOC_16_PCREL: |
| 932 | case BFD_RELOC_32_PCREL: |
| 933 | case BFD_RELOC_8_GOT_PCREL: |
| 934 | case BFD_RELOC_16_GOT_PCREL: |
| 935 | case BFD_RELOC_32_GOT_PCREL: |
| 936 | case BFD_RELOC_8_GOTOFF: |
| 937 | case BFD_RELOC_16_GOTOFF: |
| 938 | case BFD_RELOC_32_GOTOFF: |
| 939 | case BFD_RELOC_8_PLT_PCREL: |
| 940 | case BFD_RELOC_16_PLT_PCREL: |
| 941 | case BFD_RELOC_32_PLT_PCREL: |
| 942 | case BFD_RELOC_8_PLTOFF: |
| 943 | case BFD_RELOC_16_PLTOFF: |
| 944 | case BFD_RELOC_32_PLTOFF: |
| 945 | break; |
| 946 | default: |
| 947 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 948 | _("Cannot make %s relocation PC relative"), |
| 949 | bfd_get_reloc_code_name (code)); |
| 950 | } |
| 951 | } |
| 952 | } |
| 953 | else |
| 954 | { |
| 955 | #define F(SZ,PCREL) (((SZ) << 1) + (PCREL)) |
| 956 | switch (F (fixp->fx_size, fixp->fx_pcrel)) |
| 957 | { |
| 958 | #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break |
| 959 | MAP (1, 0, BFD_RELOC_8); |
| 960 | MAP (2, 0, BFD_RELOC_16); |
| 961 | MAP (4, 0, BFD_RELOC_32); |
| 962 | MAP (1, 1, BFD_RELOC_8_PCREL); |
| 963 | MAP (2, 1, BFD_RELOC_16_PCREL); |
| 964 | MAP (4, 1, BFD_RELOC_32_PCREL); |
| 965 | default: |
| 966 | abort (); |
| 967 | } |
| 968 | } |
| 969 | #undef F |
| 970 | #undef MAP |
| 971 | |
| 972 | reloc = (arelent *) xmalloc (sizeof (arelent)); |
| 973 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
| 974 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
| 975 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
| 976 | #ifndef OBJ_ELF |
| 977 | if (fixp->fx_pcrel) |
| 978 | reloc->addend = fixp->fx_addnumber; |
| 979 | else |
| 980 | reloc->addend = 0; |
| 981 | #else |
| 982 | if (!fixp->fx_pcrel) |
| 983 | reloc->addend = fixp->fx_addnumber; |
| 984 | else |
| 985 | reloc->addend = (section->vma |
| 986 | /* Explicit sign extension in case char is |
| 987 | unsigned. */ |
| 988 | + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80 |
| 989 | + fixp->fx_addnumber |
| 990 | + md_pcrel_from (fixp)); |
| 991 | #endif |
| 992 | |
| 993 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
| 994 | assert (reloc->howto != 0); |
| 995 | |
| 996 | return reloc; |
| 997 | } |
| 998 | |
| 999 | #endif /* BFD_ASSEMBLER */ |
| 1000 | |
| 1001 | /* Handle of the OPCODE hash table. NULL means any use before |
| 1002 | m68k_ip_begin() will crash. */ |
| 1003 | static struct hash_control *op_hash; |
| 1004 | \f |
| 1005 | /* Assemble an m68k instruction. */ |
| 1006 | |
| 1007 | static void |
| 1008 | m68k_ip (instring) |
| 1009 | char *instring; |
| 1010 | { |
| 1011 | register char *p; |
| 1012 | register struct m68k_op *opP; |
| 1013 | register const struct m68k_incant *opcode; |
| 1014 | register const char *s; |
| 1015 | register int tmpreg = 0, baseo = 0, outro = 0, nextword; |
| 1016 | char *pdot, *pdotmove; |
| 1017 | enum m68k_size siz1, siz2; |
| 1018 | char c; |
| 1019 | int losing; |
| 1020 | int opsfound; |
| 1021 | LITTLENUM_TYPE words[6]; |
| 1022 | LITTLENUM_TYPE *wordp; |
| 1023 | unsigned long ok_arch = 0; |
| 1024 | |
| 1025 | if (*instring == ' ') |
| 1026 | instring++; /* skip leading whitespace */ |
| 1027 | |
| 1028 | /* Scan up to end of operation-code, which MUST end in end-of-string |
| 1029 | or exactly 1 space. */ |
| 1030 | pdot = 0; |
| 1031 | for (p = instring; *p != '\0'; p++) |
| 1032 | { |
| 1033 | if (*p == ' ') |
| 1034 | break; |
| 1035 | if (*p == '.') |
| 1036 | pdot = p; |
| 1037 | } |
| 1038 | |
| 1039 | if (p == instring) |
| 1040 | { |
| 1041 | the_ins.error = _("No operator"); |
| 1042 | return; |
| 1043 | } |
| 1044 | |
| 1045 | /* p now points to the end of the opcode name, probably whitespace. |
| 1046 | Make sure the name is null terminated by clobbering the |
| 1047 | whitespace, look it up in the hash table, then fix it back. |
| 1048 | Remove a dot, first, since the opcode tables have none. */ |
| 1049 | if (pdot != NULL) |
| 1050 | { |
| 1051 | for (pdotmove = pdot; pdotmove < p; pdotmove++) |
| 1052 | *pdotmove = pdotmove[1]; |
| 1053 | p--; |
| 1054 | } |
| 1055 | |
| 1056 | c = *p; |
| 1057 | *p = '\0'; |
| 1058 | opcode = (const struct m68k_incant *) hash_find (op_hash, instring); |
| 1059 | *p = c; |
| 1060 | |
| 1061 | if (pdot != NULL) |
| 1062 | { |
| 1063 | for (pdotmove = p; pdotmove > pdot; pdotmove--) |
| 1064 | *pdotmove = pdotmove[-1]; |
| 1065 | *pdot = '.'; |
| 1066 | ++p; |
| 1067 | } |
| 1068 | |
| 1069 | if (opcode == NULL) |
| 1070 | { |
| 1071 | the_ins.error = _("Unknown operator"); |
| 1072 | return; |
| 1073 | } |
| 1074 | |
| 1075 | /* found a legitimate opcode, start matching operands */ |
| 1076 | while (*p == ' ') |
| 1077 | ++p; |
| 1078 | |
| 1079 | if (opcode->m_operands == 0) |
| 1080 | { |
| 1081 | char *old = input_line_pointer; |
| 1082 | *old = '\n'; |
| 1083 | input_line_pointer = p; |
| 1084 | /* Ahh - it's a motorola style psuedo op */ |
| 1085 | mote_pseudo_table[opcode->m_opnum].poc_handler |
| 1086 | (mote_pseudo_table[opcode->m_opnum].poc_val); |
| 1087 | input_line_pointer = old; |
| 1088 | *old = 0; |
| 1089 | |
| 1090 | return; |
| 1091 | } |
| 1092 | |
| 1093 | if (flag_mri && opcode->m_opnum == 0) |
| 1094 | { |
| 1095 | /* In MRI mode, random garbage is allowed after an instruction |
| 1096 | which accepts no operands. */ |
| 1097 | the_ins.args = opcode->m_operands; |
| 1098 | the_ins.numargs = opcode->m_opnum; |
| 1099 | the_ins.numo = opcode->m_codenum; |
| 1100 | the_ins.opcode[0] = getone (opcode); |
| 1101 | the_ins.opcode[1] = gettwo (opcode); |
| 1102 | return; |
| 1103 | } |
| 1104 | |
| 1105 | for (opP = &the_ins.operands[0]; *p; opP++) |
| 1106 | { |
| 1107 | p = crack_operand (p, opP); |
| 1108 | |
| 1109 | if (opP->error) |
| 1110 | { |
| 1111 | the_ins.error = opP->error; |
| 1112 | return; |
| 1113 | } |
| 1114 | } |
| 1115 | |
| 1116 | opsfound = opP - &the_ins.operands[0]; |
| 1117 | |
| 1118 | /* This ugly hack is to support the floating pt opcodes in their |
| 1119 | standard form. Essentially, we fake a first enty of type COP#1 */ |
| 1120 | if (opcode->m_operands[0] == 'I') |
| 1121 | { |
| 1122 | int n; |
| 1123 | |
| 1124 | for (n = opsfound; n > 0; --n) |
| 1125 | the_ins.operands[n] = the_ins.operands[n - 1]; |
| 1126 | |
| 1127 | memset ((char *) (&the_ins.operands[0]), '\0', |
| 1128 | sizeof (the_ins.operands[0])); |
| 1129 | the_ins.operands[0].mode = CONTROL; |
| 1130 | the_ins.operands[0].reg = m68k_float_copnum; |
| 1131 | opsfound++; |
| 1132 | } |
| 1133 | |
| 1134 | /* We've got the operands. Find an opcode that'll accept them */ |
| 1135 | for (losing = 0;;) |
| 1136 | { |
| 1137 | /* If we didn't get the right number of ops, or we have no |
| 1138 | common model with this pattern then reject this pattern. */ |
| 1139 | |
| 1140 | ok_arch |= opcode->m_arch; |
| 1141 | if (opsfound != opcode->m_opnum |
| 1142 | || ((opcode->m_arch & current_architecture) == 0)) |
| 1143 | ++losing; |
| 1144 | else |
| 1145 | { |
| 1146 | for (s = opcode->m_operands, opP = &the_ins.operands[0]; |
| 1147 | *s && !losing; |
| 1148 | s += 2, opP++) |
| 1149 | { |
| 1150 | /* Warning: this switch is huge! */ |
| 1151 | /* I've tried to organize the cases into this order: |
| 1152 | non-alpha first, then alpha by letter. Lower-case |
| 1153 | goes directly before uppercase counterpart. */ |
| 1154 | /* Code with multiple case ...: gets sorted by the lowest |
| 1155 | case ... it belongs to. I hope this makes sense. */ |
| 1156 | switch (*s) |
| 1157 | { |
| 1158 | case '!': |
| 1159 | switch (opP->mode) |
| 1160 | { |
| 1161 | case IMMED: |
| 1162 | case DREG: |
| 1163 | case AREG: |
| 1164 | case FPREG: |
| 1165 | case CONTROL: |
| 1166 | case AINC: |
| 1167 | case ADEC: |
| 1168 | case REGLST: |
| 1169 | losing++; |
| 1170 | break; |
| 1171 | default: |
| 1172 | break; |
| 1173 | } |
| 1174 | break; |
| 1175 | |
| 1176 | case '<': |
| 1177 | switch (opP->mode) |
| 1178 | { |
| 1179 | case DREG: |
| 1180 | case AREG: |
| 1181 | case FPREG: |
| 1182 | case CONTROL: |
| 1183 | case IMMED: |
| 1184 | case ADEC: |
| 1185 | case REGLST: |
| 1186 | losing++; |
| 1187 | break; |
| 1188 | default: |
| 1189 | break; |
| 1190 | } |
| 1191 | break; |
| 1192 | |
| 1193 | case '>': |
| 1194 | switch (opP->mode) |
| 1195 | { |
| 1196 | case DREG: |
| 1197 | case AREG: |
| 1198 | case FPREG: |
| 1199 | case CONTROL: |
| 1200 | case IMMED: |
| 1201 | case AINC: |
| 1202 | case REGLST: |
| 1203 | losing++; |
| 1204 | break; |
| 1205 | case ABSL: |
| 1206 | break; |
| 1207 | default: |
| 1208 | if (opP->reg == PC |
| 1209 | || opP->reg == ZPC) |
| 1210 | losing++; |
| 1211 | break; |
| 1212 | } |
| 1213 | break; |
| 1214 | |
| 1215 | case 'm': |
| 1216 | switch (opP->mode) |
| 1217 | { |
| 1218 | case DREG: |
| 1219 | case AREG: |
| 1220 | case AINDR: |
| 1221 | case AINC: |
| 1222 | case ADEC: |
| 1223 | break; |
| 1224 | default: |
| 1225 | losing++; |
| 1226 | } |
| 1227 | break; |
| 1228 | |
| 1229 | case 'n': |
| 1230 | switch (opP->mode) |
| 1231 | { |
| 1232 | case DISP: |
| 1233 | break; |
| 1234 | default: |
| 1235 | losing++; |
| 1236 | } |
| 1237 | break; |
| 1238 | |
| 1239 | case 'o': |
| 1240 | switch (opP->mode) |
| 1241 | { |
| 1242 | case BASE: |
| 1243 | case ABSL: |
| 1244 | case IMMED: |
| 1245 | break; |
| 1246 | default: |
| 1247 | losing++; |
| 1248 | } |
| 1249 | break; |
| 1250 | |
| 1251 | case 'p': |
| 1252 | switch (opP->mode) |
| 1253 | { |
| 1254 | case DREG: |
| 1255 | case AREG: |
| 1256 | case AINDR: |
| 1257 | case AINC: |
| 1258 | case ADEC: |
| 1259 | break; |
| 1260 | case DISP: |
| 1261 | if (opP->reg == PC || opP->reg == ZPC) |
| 1262 | losing++; |
| 1263 | break; |
| 1264 | default: |
| 1265 | losing++; |
| 1266 | } |
| 1267 | break; |
| 1268 | |
| 1269 | case 'q': |
| 1270 | switch (opP->mode) |
| 1271 | { |
| 1272 | case DREG: |
| 1273 | case AINDR: |
| 1274 | case AINC: |
| 1275 | case ADEC: |
| 1276 | break; |
| 1277 | case DISP: |
| 1278 | if (opP->reg == PC || opP->reg == ZPC) |
| 1279 | losing++; |
| 1280 | break; |
| 1281 | default: |
| 1282 | losing++; |
| 1283 | break; |
| 1284 | } |
| 1285 | break; |
| 1286 | |
| 1287 | case 'v': |
| 1288 | switch (opP->mode) |
| 1289 | { |
| 1290 | case DREG: |
| 1291 | case AINDR: |
| 1292 | case AINC: |
| 1293 | case ADEC: |
| 1294 | case ABSL: |
| 1295 | break; |
| 1296 | case DISP: |
| 1297 | if (opP->reg == PC || opP->reg == ZPC) |
| 1298 | losing++; |
| 1299 | break; |
| 1300 | default: |
| 1301 | losing++; |
| 1302 | break; |
| 1303 | } |
| 1304 | break; |
| 1305 | |
| 1306 | case '#': |
| 1307 | if (opP->mode != IMMED) |
| 1308 | losing++; |
| 1309 | else if (s[1] == 'b' |
| 1310 | && ! isvar (&opP->disp) |
| 1311 | && (opP->disp.exp.X_op != O_constant |
| 1312 | || ! isbyte (opP->disp.exp.X_add_number))) |
| 1313 | losing++; |
| 1314 | else if (s[1] == 'B' |
| 1315 | && ! isvar (&opP->disp) |
| 1316 | && (opP->disp.exp.X_op != O_constant |
| 1317 | || ! issbyte (opP->disp.exp.X_add_number))) |
| 1318 | losing++; |
| 1319 | else if (s[1] == 'w' |
| 1320 | && ! isvar (&opP->disp) |
| 1321 | && (opP->disp.exp.X_op != O_constant |
| 1322 | || ! isword (opP->disp.exp.X_add_number))) |
| 1323 | losing++; |
| 1324 | else if (s[1] == 'W' |
| 1325 | && ! isvar (&opP->disp) |
| 1326 | && (opP->disp.exp.X_op != O_constant |
| 1327 | || ! issword (opP->disp.exp.X_add_number))) |
| 1328 | losing++; |
| 1329 | break; |
| 1330 | |
| 1331 | case '^': |
| 1332 | case 'T': |
| 1333 | if (opP->mode != IMMED) |
| 1334 | losing++; |
| 1335 | break; |
| 1336 | |
| 1337 | case '$': |
| 1338 | if (opP->mode == AREG |
| 1339 | || opP->mode == CONTROL |
| 1340 | || opP->mode == FPREG |
| 1341 | || opP->mode == IMMED |
| 1342 | || opP->mode == REGLST |
| 1343 | || (opP->mode != ABSL |
| 1344 | && (opP->reg == PC |
| 1345 | || opP->reg == ZPC))) |
| 1346 | losing++; |
| 1347 | break; |
| 1348 | |
| 1349 | case '%': |
| 1350 | if (opP->mode == CONTROL |
| 1351 | || opP->mode == FPREG |
| 1352 | || opP->mode == REGLST |
| 1353 | || opP->mode == IMMED |
| 1354 | || (opP->mode != ABSL |
| 1355 | && (opP->reg == PC |
| 1356 | || opP->reg == ZPC))) |
| 1357 | losing++; |
| 1358 | break; |
| 1359 | |
| 1360 | case '&': |
| 1361 | switch (opP->mode) |
| 1362 | { |
| 1363 | case DREG: |
| 1364 | case AREG: |
| 1365 | case FPREG: |
| 1366 | case CONTROL: |
| 1367 | case IMMED: |
| 1368 | case AINC: |
| 1369 | case ADEC: |
| 1370 | case REGLST: |
| 1371 | losing++; |
| 1372 | break; |
| 1373 | case ABSL: |
| 1374 | break; |
| 1375 | default: |
| 1376 | if (opP->reg == PC |
| 1377 | || opP->reg == ZPC) |
| 1378 | losing++; |
| 1379 | break; |
| 1380 | } |
| 1381 | break; |
| 1382 | |
| 1383 | case '*': |
| 1384 | if (opP->mode == CONTROL |
| 1385 | || opP->mode == FPREG |
| 1386 | || opP->mode == REGLST) |
| 1387 | losing++; |
| 1388 | break; |
| 1389 | |
| 1390 | case '+': |
| 1391 | if (opP->mode != AINC) |
| 1392 | losing++; |
| 1393 | break; |
| 1394 | |
| 1395 | case '-': |
| 1396 | if (opP->mode != ADEC) |
| 1397 | losing++; |
| 1398 | break; |
| 1399 | |
| 1400 | case '/': |
| 1401 | switch (opP->mode) |
| 1402 | { |
| 1403 | case AREG: |
| 1404 | case CONTROL: |
| 1405 | case FPREG: |
| 1406 | case AINC: |
| 1407 | case ADEC: |
| 1408 | case IMMED: |
| 1409 | case REGLST: |
| 1410 | losing++; |
| 1411 | break; |
| 1412 | default: |
| 1413 | break; |
| 1414 | } |
| 1415 | break; |
| 1416 | |
| 1417 | case ';': |
| 1418 | switch (opP->mode) |
| 1419 | { |
| 1420 | case AREG: |
| 1421 | case CONTROL: |
| 1422 | case FPREG: |
| 1423 | case REGLST: |
| 1424 | losing++; |
| 1425 | break; |
| 1426 | default: |
| 1427 | break; |
| 1428 | } |
| 1429 | break; |
| 1430 | |
| 1431 | case '?': |
| 1432 | switch (opP->mode) |
| 1433 | { |
| 1434 | case AREG: |
| 1435 | case CONTROL: |
| 1436 | case FPREG: |
| 1437 | case AINC: |
| 1438 | case ADEC: |
| 1439 | case IMMED: |
| 1440 | case REGLST: |
| 1441 | losing++; |
| 1442 | break; |
| 1443 | case ABSL: |
| 1444 | break; |
| 1445 | default: |
| 1446 | if (opP->reg == PC || opP->reg == ZPC) |
| 1447 | losing++; |
| 1448 | break; |
| 1449 | } |
| 1450 | break; |
| 1451 | |
| 1452 | case '@': |
| 1453 | switch (opP->mode) |
| 1454 | { |
| 1455 | case AREG: |
| 1456 | case CONTROL: |
| 1457 | case FPREG: |
| 1458 | case IMMED: |
| 1459 | case REGLST: |
| 1460 | losing++; |
| 1461 | break; |
| 1462 | default: |
| 1463 | break; |
| 1464 | } |
| 1465 | break; |
| 1466 | |
| 1467 | case '~': /* For now! (JF FOO is this right?) */ |
| 1468 | switch (opP->mode) |
| 1469 | { |
| 1470 | case DREG: |
| 1471 | case AREG: |
| 1472 | case CONTROL: |
| 1473 | case FPREG: |
| 1474 | case IMMED: |
| 1475 | case REGLST: |
| 1476 | losing++; |
| 1477 | break; |
| 1478 | case ABSL: |
| 1479 | break; |
| 1480 | default: |
| 1481 | if (opP->reg == PC |
| 1482 | || opP->reg == ZPC) |
| 1483 | losing++; |
| 1484 | break; |
| 1485 | } |
| 1486 | break; |
| 1487 | |
| 1488 | case '3': |
| 1489 | if (opP->mode != CONTROL |
| 1490 | || (opP->reg != TT0 && opP->reg != TT1)) |
| 1491 | losing++; |
| 1492 | break; |
| 1493 | |
| 1494 | case 'A': |
| 1495 | if (opP->mode != AREG) |
| 1496 | losing++; |
| 1497 | break; |
| 1498 | |
| 1499 | case 'a': |
| 1500 | if (opP->mode != AINDR) |
| 1501 | ++losing; |
| 1502 | break; |
| 1503 | |
| 1504 | case 'B': /* FOO */ |
| 1505 | if (opP->mode != ABSL |
| 1506 | || (flag_long_jumps |
| 1507 | && strncmp (instring, "jbsr", 4) == 0)) |
| 1508 | losing++; |
| 1509 | break; |
| 1510 | |
| 1511 | case 'C': |
| 1512 | if (opP->mode != CONTROL || opP->reg != CCR) |
| 1513 | losing++; |
| 1514 | break; |
| 1515 | |
| 1516 | case 'd': |
| 1517 | if (opP->mode != DISP |
| 1518 | || opP->reg < ADDR0 |
| 1519 | || opP->reg > ADDR7) |
| 1520 | losing++; |
| 1521 | break; |
| 1522 | |
| 1523 | case 'D': |
| 1524 | if (opP->mode != DREG) |
| 1525 | losing++; |
| 1526 | break; |
| 1527 | |
| 1528 | case 'E': |
| 1529 | if (opP->reg != ACC) |
| 1530 | losing++; |
| 1531 | break; |
| 1532 | |
| 1533 | case 'F': |
| 1534 | if (opP->mode != FPREG) |
| 1535 | losing++; |
| 1536 | break; |
| 1537 | |
| 1538 | case 'G': |
| 1539 | if (opP->reg != MACSR) |
| 1540 | losing++; |
| 1541 | break; |
| 1542 | |
| 1543 | case 'H': |
| 1544 | if (opP->reg != MASK) |
| 1545 | losing++; |
| 1546 | break; |
| 1547 | |
| 1548 | case 'I': |
| 1549 | if (opP->mode != CONTROL |
| 1550 | || opP->reg < COP0 |
| 1551 | || opP->reg > COP7) |
| 1552 | losing++; |
| 1553 | break; |
| 1554 | |
| 1555 | case 'J': |
| 1556 | if (opP->mode != CONTROL |
| 1557 | || opP->reg < USP |
| 1558 | || opP->reg > last_movec_reg) |
| 1559 | losing++; |
| 1560 | else |
| 1561 | { |
| 1562 | const enum m68k_register *rp; |
| 1563 | for (rp = control_regs; *rp; rp++) |
| 1564 | if (*rp == opP->reg) |
| 1565 | break; |
| 1566 | if (*rp == 0) |
| 1567 | losing++; |
| 1568 | } |
| 1569 | break; |
| 1570 | |
| 1571 | case 'k': |
| 1572 | if (opP->mode != IMMED) |
| 1573 | losing++; |
| 1574 | break; |
| 1575 | |
| 1576 | case 'l': |
| 1577 | case 'L': |
| 1578 | if (opP->mode == DREG |
| 1579 | || opP->mode == AREG |
| 1580 | || opP->mode == FPREG) |
| 1581 | { |
| 1582 | if (s[1] == '8') |
| 1583 | losing++; |
| 1584 | else |
| 1585 | { |
| 1586 | switch (opP->mode) |
| 1587 | { |
| 1588 | case DREG: |
| 1589 | opP->mask = 1 << (opP->reg - DATA0); |
| 1590 | break; |
| 1591 | case AREG: |
| 1592 | opP->mask = 1 << (opP->reg - ADDR0 + 8); |
| 1593 | break; |
| 1594 | case FPREG: |
| 1595 | opP->mask = 1 << (opP->reg - FP0 + 16); |
| 1596 | break; |
| 1597 | default: |
| 1598 | abort (); |
| 1599 | } |
| 1600 | opP->mode = REGLST; |
| 1601 | } |
| 1602 | } |
| 1603 | else if (opP->mode == CONTROL) |
| 1604 | { |
| 1605 | if (s[1] != '8') |
| 1606 | losing++; |
| 1607 | else |
| 1608 | { |
| 1609 | switch (opP->reg) |
| 1610 | { |
| 1611 | case FPI: |
| 1612 | opP->mask = 1 << 24; |
| 1613 | break; |
| 1614 | case FPS: |
| 1615 | opP->mask = 1 << 25; |
| 1616 | break; |
| 1617 | case FPC: |
| 1618 | opP->mask = 1 << 26; |
| 1619 | break; |
| 1620 | default: |
| 1621 | losing++; |
| 1622 | break; |
| 1623 | } |
| 1624 | opP->mode = REGLST; |
| 1625 | } |
| 1626 | } |
| 1627 | else if (opP->mode != REGLST) |
| 1628 | losing++; |
| 1629 | else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0) |
| 1630 | losing++; |
| 1631 | else if (s[1] == '3' && (opP->mask & 0x7000000) != 0) |
| 1632 | losing++; |
| 1633 | break; |
| 1634 | |
| 1635 | case 'M': |
| 1636 | if (opP->mode != IMMED) |
| 1637 | losing++; |
| 1638 | else if (opP->disp.exp.X_op != O_constant |
| 1639 | || ! issbyte (opP->disp.exp.X_add_number)) |
| 1640 | losing++; |
| 1641 | else if (! m68k_quick |
| 1642 | && instring[3] != 'q' |
| 1643 | && instring[4] != 'q') |
| 1644 | losing++; |
| 1645 | break; |
| 1646 | |
| 1647 | case 'O': |
| 1648 | if (opP->mode != DREG |
| 1649 | && opP->mode != IMMED |
| 1650 | && opP->mode != ABSL) |
| 1651 | losing++; |
| 1652 | break; |
| 1653 | |
| 1654 | case 'Q': |
| 1655 | if (opP->mode != IMMED) |
| 1656 | losing++; |
| 1657 | else if (opP->disp.exp.X_op != O_constant |
| 1658 | || opP->disp.exp.X_add_number < 1 |
| 1659 | || opP->disp.exp.X_add_number > 8) |
| 1660 | losing++; |
| 1661 | else if (! m68k_quick |
| 1662 | && (strncmp (instring, "add", 3) == 0 |
| 1663 | || strncmp (instring, "sub", 3) == 0) |
| 1664 | && instring[3] != 'q') |
| 1665 | losing++; |
| 1666 | break; |
| 1667 | |
| 1668 | case 'R': |
| 1669 | if (opP->mode != DREG && opP->mode != AREG) |
| 1670 | losing++; |
| 1671 | break; |
| 1672 | |
| 1673 | case 'r': |
| 1674 | if (opP->mode != AINDR |
| 1675 | && (opP->mode != BASE |
| 1676 | || (opP->reg != 0 |
| 1677 | && opP->reg != ZADDR0) |
| 1678 | || opP->disp.exp.X_op != O_absent |
| 1679 | || ((opP->index.reg < DATA0 |
| 1680 | || opP->index.reg > DATA7) |
| 1681 | && (opP->index.reg < ADDR0 |
| 1682 | || opP->index.reg > ADDR7)) |
| 1683 | || opP->index.size != SIZE_UNSPEC |
| 1684 | || opP->index.scale != 1)) |
| 1685 | losing++; |
| 1686 | break; |
| 1687 | |
| 1688 | case 's': |
| 1689 | if (opP->mode != CONTROL |
| 1690 | || ! (opP->reg == FPI |
| 1691 | || opP->reg == FPS |
| 1692 | || opP->reg == FPC)) |
| 1693 | losing++; |
| 1694 | break; |
| 1695 | |
| 1696 | case 'S': |
| 1697 | if (opP->mode != CONTROL || opP->reg != SR) |
| 1698 | losing++; |
| 1699 | break; |
| 1700 | |
| 1701 | case 't': |
| 1702 | if (opP->mode != IMMED) |
| 1703 | losing++; |
| 1704 | else if (opP->disp.exp.X_op != O_constant |
| 1705 | || opP->disp.exp.X_add_number < 0 |
| 1706 | || opP->disp.exp.X_add_number > 7) |
| 1707 | losing++; |
| 1708 | break; |
| 1709 | |
| 1710 | case 'U': |
| 1711 | if (opP->mode != CONTROL || opP->reg != USP) |
| 1712 | losing++; |
| 1713 | break; |
| 1714 | |
| 1715 | /* JF these are out of order. We could put them |
| 1716 | in order if we were willing to put up with |
| 1717 | bunches of #ifdef m68851s in the code. |
| 1718 | |
| 1719 | Don't forget that you need these operands |
| 1720 | to use 68030 MMU instructions. */ |
| 1721 | #ifndef NO_68851 |
| 1722 | /* Memory addressing mode used by pflushr */ |
| 1723 | case '|': |
| 1724 | if (opP->mode == CONTROL |
| 1725 | || opP->mode == FPREG |
| 1726 | || opP->mode == DREG |
| 1727 | || opP->mode == AREG |
| 1728 | || opP->mode == REGLST) |
| 1729 | losing++; |
| 1730 | /* We should accept immediate operands, but they |
| 1731 | supposedly have to be quad word, and we don't |
| 1732 | handle that. I would like to see what a Motorola |
| 1733 | assembler does before doing something here. */ |
| 1734 | if (opP->mode == IMMED) |
| 1735 | losing++; |
| 1736 | break; |
| 1737 | |
| 1738 | case 'f': |
| 1739 | if (opP->mode != CONTROL |
| 1740 | || (opP->reg != SFC && opP->reg != DFC)) |
| 1741 | losing++; |
| 1742 | break; |
| 1743 | |
| 1744 | case '0': |
| 1745 | if (opP->mode != CONTROL || opP->reg != TC) |
| 1746 | losing++; |
| 1747 | break; |
| 1748 | |
| 1749 | case '1': |
| 1750 | if (opP->mode != CONTROL || opP->reg != AC) |
| 1751 | losing++; |
| 1752 | break; |
| 1753 | |
| 1754 | case '2': |
| 1755 | if (opP->mode != CONTROL |
| 1756 | || (opP->reg != CAL |
| 1757 | && opP->reg != VAL |
| 1758 | && opP->reg != SCC)) |
| 1759 | losing++; |
| 1760 | break; |
| 1761 | |
| 1762 | case 'V': |
| 1763 | if (opP->mode != CONTROL |
| 1764 | || opP->reg != VAL) |
| 1765 | losing++; |
| 1766 | break; |
| 1767 | |
| 1768 | case 'W': |
| 1769 | if (opP->mode != CONTROL |
| 1770 | || (opP->reg != DRP |
| 1771 | && opP->reg != SRP |
| 1772 | && opP->reg != CRP)) |
| 1773 | losing++; |
| 1774 | break; |
| 1775 | |
| 1776 | case 'X': |
| 1777 | if (opP->mode != CONTROL |
| 1778 | || (!(opP->reg >= BAD && opP->reg <= BAD + 7) |
| 1779 | && !(opP->reg >= BAC && opP->reg <= BAC + 7))) |
| 1780 | losing++; |
| 1781 | break; |
| 1782 | |
| 1783 | case 'Y': |
| 1784 | if (opP->mode != CONTROL || opP->reg != PSR) |
| 1785 | losing++; |
| 1786 | break; |
| 1787 | |
| 1788 | case 'Z': |
| 1789 | if (opP->mode != CONTROL || opP->reg != PCSR) |
| 1790 | losing++; |
| 1791 | break; |
| 1792 | #endif |
| 1793 | case 'c': |
| 1794 | if (opP->mode != CONTROL |
| 1795 | || (opP->reg != NC |
| 1796 | && opP->reg != IC |
| 1797 | && opP->reg != DC |
| 1798 | && opP->reg != BC)) |
| 1799 | { |
| 1800 | losing++; |
| 1801 | } /* not a cache specifier. */ |
| 1802 | break; |
| 1803 | |
| 1804 | case '_': |
| 1805 | if (opP->mode != ABSL) |
| 1806 | ++losing; |
| 1807 | break; |
| 1808 | |
| 1809 | case 'u': |
| 1810 | if (opP->reg < DATA0L || opP->reg > ADDR7U) |
| 1811 | losing++; |
| 1812 | /* FIXME: kludge instead of fixing parser: |
| 1813 | upper/lower registers are *not* CONTROL |
| 1814 | registers, but ordinary ones. */ |
| 1815 | if ((opP->reg >= DATA0L && opP->reg <= DATA7L) |
| 1816 | || (opP->reg >= DATA0U && opP->reg <= DATA7U)) |
| 1817 | opP->mode = DREG; |
| 1818 | else |
| 1819 | opP->mode = AREG; |
| 1820 | break; |
| 1821 | |
| 1822 | default: |
| 1823 | abort (); |
| 1824 | } /* switch on type of operand */ |
| 1825 | |
| 1826 | if (losing) |
| 1827 | break; |
| 1828 | } /* for each operand */ |
| 1829 | } /* if immediately wrong */ |
| 1830 | |
| 1831 | if (!losing) |
| 1832 | { |
| 1833 | break; |
| 1834 | } /* got it. */ |
| 1835 | |
| 1836 | opcode = opcode->m_next; |
| 1837 | |
| 1838 | if (!opcode) |
| 1839 | { |
| 1840 | if (ok_arch |
| 1841 | && !(ok_arch & current_architecture)) |
| 1842 | { |
| 1843 | char buf[200], *cp; |
| 1844 | |
| 1845 | strcpy (buf, |
| 1846 | _("invalid instruction for this architecture; needs ")); |
| 1847 | cp = buf + strlen (buf); |
| 1848 | switch (ok_arch) |
| 1849 | { |
| 1850 | case mfloat: |
| 1851 | strcpy (cp, _("fpu (68040, 68060 or 68881/68882)")); |
| 1852 | break; |
| 1853 | case mmmu: |
| 1854 | strcpy (cp, _("mmu (68030 or 68851)")); |
| 1855 | break; |
| 1856 | case m68020up: |
| 1857 | strcpy (cp, _("68020 or higher")); |
| 1858 | break; |
| 1859 | case m68000up: |
| 1860 | strcpy (cp, _("68000 or higher")); |
| 1861 | break; |
| 1862 | case m68010up: |
| 1863 | strcpy (cp, _("68010 or higher")); |
| 1864 | break; |
| 1865 | default: |
| 1866 | { |
| 1867 | int got_one = 0, idx; |
| 1868 | for (idx = 0; |
| 1869 | idx < (int) (sizeof (archs) / sizeof (archs[0])); |
| 1870 | idx++) |
| 1871 | { |
| 1872 | if ((archs[idx].arch & ok_arch) |
| 1873 | && ! archs[idx].alias) |
| 1874 | { |
| 1875 | if (got_one) |
| 1876 | { |
| 1877 | strcpy (cp, " or "); |
| 1878 | cp += strlen (cp); |
| 1879 | } |
| 1880 | got_one = 1; |
| 1881 | strcpy (cp, archs[idx].name); |
| 1882 | cp += strlen (cp); |
| 1883 | } |
| 1884 | } |
| 1885 | } |
| 1886 | } |
| 1887 | cp = xmalloc (strlen (buf) + 1); |
| 1888 | strcpy (cp, buf); |
| 1889 | the_ins.error = cp; |
| 1890 | } |
| 1891 | else |
| 1892 | the_ins.error = _("operands mismatch"); |
| 1893 | return; |
| 1894 | } /* Fell off the end */ |
| 1895 | |
| 1896 | losing = 0; |
| 1897 | } |
| 1898 | |
| 1899 | /* now assemble it */ |
| 1900 | |
| 1901 | the_ins.args = opcode->m_operands; |
| 1902 | the_ins.numargs = opcode->m_opnum; |
| 1903 | the_ins.numo = opcode->m_codenum; |
| 1904 | the_ins.opcode[0] = getone (opcode); |
| 1905 | the_ins.opcode[1] = gettwo (opcode); |
| 1906 | |
| 1907 | for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++) |
| 1908 | { |
| 1909 | /* This switch is a doozy. |
| 1910 | Watch the first step; its a big one! */ |
| 1911 | switch (s[0]) |
| 1912 | { |
| 1913 | |
| 1914 | case '*': |
| 1915 | case '~': |
| 1916 | case '%': |
| 1917 | case ';': |
| 1918 | case '@': |
| 1919 | case '!': |
| 1920 | case '&': |
| 1921 | case '$': |
| 1922 | case '?': |
| 1923 | case '/': |
| 1924 | case '<': |
| 1925 | case '>': |
| 1926 | case 'm': |
| 1927 | case 'n': |
| 1928 | case 'o': |
| 1929 | case 'p': |
| 1930 | case 'q': |
| 1931 | case 'v': |
| 1932 | #ifndef NO_68851 |
| 1933 | case '|': |
| 1934 | #endif |
| 1935 | switch (opP->mode) |
| 1936 | { |
| 1937 | case IMMED: |
| 1938 | tmpreg = 0x3c; /* 7.4 */ |
| 1939 | if (strchr ("bwl", s[1])) |
| 1940 | nextword = get_num (&opP->disp, 80); |
| 1941 | else |
| 1942 | nextword = get_num (&opP->disp, 0); |
| 1943 | if (isvar (&opP->disp)) |
| 1944 | add_fix (s[1], &opP->disp, 0, 0); |
| 1945 | switch (s[1]) |
| 1946 | { |
| 1947 | case 'b': |
| 1948 | if (!isbyte (nextword)) |
| 1949 | opP->error = _("operand out of range"); |
| 1950 | addword (nextword); |
| 1951 | baseo = 0; |
| 1952 | break; |
| 1953 | case 'w': |
| 1954 | if (!isword (nextword)) |
| 1955 | opP->error = _("operand out of range"); |
| 1956 | addword (nextword); |
| 1957 | baseo = 0; |
| 1958 | break; |
| 1959 | case 'W': |
| 1960 | if (!issword (nextword)) |
| 1961 | opP->error = _("operand out of range"); |
| 1962 | addword (nextword); |
| 1963 | baseo = 0; |
| 1964 | break; |
| 1965 | case 'l': |
| 1966 | addword (nextword >> 16); |
| 1967 | addword (nextword); |
| 1968 | baseo = 0; |
| 1969 | break; |
| 1970 | |
| 1971 | case 'f': |
| 1972 | baseo = 2; |
| 1973 | outro = 8; |
| 1974 | break; |
| 1975 | case 'F': |
| 1976 | baseo = 4; |
| 1977 | outro = 11; |
| 1978 | break; |
| 1979 | case 'x': |
| 1980 | baseo = 6; |
| 1981 | outro = 15; |
| 1982 | break; |
| 1983 | case 'p': |
| 1984 | baseo = 6; |
| 1985 | outro = -1; |
| 1986 | break; |
| 1987 | default: |
| 1988 | abort (); |
| 1989 | } |
| 1990 | if (!baseo) |
| 1991 | break; |
| 1992 | |
| 1993 | /* We gotta put out some float */ |
| 1994 | if (op (&opP->disp) != O_big) |
| 1995 | { |
| 1996 | valueT val; |
| 1997 | int gencnt; |
| 1998 | |
| 1999 | /* Can other cases happen here? */ |
| 2000 | if (op (&opP->disp) != O_constant) |
| 2001 | abort (); |
| 2002 | |
| 2003 | val = (valueT) offs (&opP->disp); |
| 2004 | gencnt = 0; |
| 2005 | do |
| 2006 | { |
| 2007 | generic_bignum[gencnt] = (LITTLENUM_TYPE) val; |
| 2008 | val >>= LITTLENUM_NUMBER_OF_BITS; |
| 2009 | ++gencnt; |
| 2010 | } |
| 2011 | while (val != 0); |
| 2012 | offs (&opP->disp) = gencnt; |
| 2013 | } |
| 2014 | if (offs (&opP->disp) > 0) |
| 2015 | { |
| 2016 | if (offs (&opP->disp) > baseo) |
| 2017 | { |
| 2018 | as_warn (_("Bignum too big for %c format; truncated"), |
| 2019 | s[1]); |
| 2020 | offs (&opP->disp) = baseo; |
| 2021 | } |
| 2022 | baseo -= offs (&opP->disp); |
| 2023 | while (baseo--) |
| 2024 | addword (0); |
| 2025 | for (wordp = generic_bignum + offs (&opP->disp) - 1; |
| 2026 | offs (&opP->disp)--; |
| 2027 | --wordp) |
| 2028 | addword (*wordp); |
| 2029 | break; |
| 2030 | } |
| 2031 | gen_to_words (words, baseo, (long) outro); |
| 2032 | for (wordp = words; baseo--; wordp++) |
| 2033 | addword (*wordp); |
| 2034 | break; |
| 2035 | case DREG: |
| 2036 | tmpreg = opP->reg - DATA; /* 0.dreg */ |
| 2037 | break; |
| 2038 | case AREG: |
| 2039 | tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */ |
| 2040 | break; |
| 2041 | case AINDR: |
| 2042 | tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */ |
| 2043 | break; |
| 2044 | case ADEC: |
| 2045 | tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */ |
| 2046 | break; |
| 2047 | case AINC: |
| 2048 | tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */ |
| 2049 | break; |
| 2050 | case DISP: |
| 2051 | |
| 2052 | nextword = get_num (&opP->disp, 80); |
| 2053 | |
| 2054 | if (opP->reg == PC |
| 2055 | && ! isvar (&opP->disp) |
| 2056 | && m68k_abspcadd) |
| 2057 | { |
| 2058 | opP->disp.exp.X_op = O_symbol; |
| 2059 | #ifndef BFD_ASSEMBLER |
| 2060 | opP->disp.exp.X_add_symbol = &abs_symbol; |
| 2061 | #else |
| 2062 | opP->disp.exp.X_add_symbol = |
| 2063 | section_symbol (absolute_section); |
| 2064 | #endif |
| 2065 | } |
| 2066 | |
| 2067 | /* Force into index mode. Hope this works */ |
| 2068 | |
| 2069 | /* We do the first bit for 32-bit displacements, and the |
| 2070 | second bit for 16 bit ones. It is possible that we |
| 2071 | should make the default be WORD instead of LONG, but |
| 2072 | I think that'd break GCC, so we put up with a little |
| 2073 | inefficiency for the sake of working output. */ |
| 2074 | |
| 2075 | if (!issword (nextword) |
| 2076 | || (isvar (&opP->disp) |
| 2077 | && ((opP->disp.size == SIZE_UNSPEC |
| 2078 | && flag_short_refs == 0 |
| 2079 | && cpu_of_arch (current_architecture) >= m68020 |
| 2080 | && ! arch_coldfire_p (current_architecture)) |
| 2081 | || opP->disp.size == SIZE_LONG))) |
| 2082 | { |
| 2083 | if (cpu_of_arch (current_architecture) < m68020 |
| 2084 | || arch_coldfire_p (current_architecture)) |
| 2085 | opP->error = |
| 2086 | _("displacement too large for this architecture; needs 68020 or higher"); |
| 2087 | if (opP->reg == PC) |
| 2088 | tmpreg = 0x3B; /* 7.3 */ |
| 2089 | else |
| 2090 | tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */ |
| 2091 | if (isvar (&opP->disp)) |
| 2092 | { |
| 2093 | if (opP->reg == PC) |
| 2094 | { |
| 2095 | if (opP->disp.size == SIZE_LONG |
| 2096 | #ifdef OBJ_ELF |
| 2097 | /* If the displacement needs pic |
| 2098 | relocation it cannot be relaxed. */ |
| 2099 | || opP->disp.pic_reloc != pic_none |
| 2100 | #endif |
| 2101 | ) |
| 2102 | { |
| 2103 | addword (0x0170); |
| 2104 | add_fix ('l', &opP->disp, 1, 2); |
| 2105 | } |
| 2106 | else |
| 2107 | { |
| 2108 | add_frag (adds (&opP->disp), |
| 2109 | offs (&opP->disp), |
| 2110 | TAB (PCREL1632, SZ_UNDEF)); |
| 2111 | break; |
| 2112 | } |
| 2113 | } |
| 2114 | else |
| 2115 | { |
| 2116 | addword (0x0170); |
| 2117 | add_fix ('l', &opP->disp, 0, 0); |
| 2118 | } |
| 2119 | } |
| 2120 | else |
| 2121 | addword (0x0170); |
| 2122 | addword (nextword >> 16); |
| 2123 | } |
| 2124 | else |
| 2125 | { |
| 2126 | if (opP->reg == PC) |
| 2127 | tmpreg = 0x3A; /* 7.2 */ |
| 2128 | else |
| 2129 | tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */ |
| 2130 | |
| 2131 | if (isvar (&opP->disp)) |
| 2132 | { |
| 2133 | if (opP->reg == PC) |
| 2134 | { |
| 2135 | add_fix ('w', &opP->disp, 1, 0); |
| 2136 | } |
| 2137 | else |
| 2138 | add_fix ('w', &opP->disp, 0, 0); |
| 2139 | } |
| 2140 | } |
| 2141 | addword (nextword); |
| 2142 | break; |
| 2143 | |
| 2144 | case POST: |
| 2145 | case PRE: |
| 2146 | case BASE: |
| 2147 | nextword = 0; |
| 2148 | baseo = get_num (&opP->disp, 80); |
| 2149 | if (opP->mode == POST || opP->mode == PRE) |
| 2150 | outro = get_num (&opP->odisp, 80); |
| 2151 | /* Figure out the `addressing mode'. |
| 2152 | Also turn on the BASE_DISABLE bit, if needed. */ |
| 2153 | if (opP->reg == PC || opP->reg == ZPC) |
| 2154 | { |
| 2155 | tmpreg = 0x3b; /* 7.3 */ |
| 2156 | if (opP->reg == ZPC) |
| 2157 | nextword |= 0x80; |
| 2158 | } |
| 2159 | else if (opP->reg == 0) |
| 2160 | { |
| 2161 | nextword |= 0x80; |
| 2162 | tmpreg = 0x30; /* 6.garbage */ |
| 2163 | } |
| 2164 | else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7) |
| 2165 | { |
| 2166 | nextword |= 0x80; |
| 2167 | tmpreg = 0x30 + opP->reg - ZADDR0; |
| 2168 | } |
| 2169 | else |
| 2170 | tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */ |
| 2171 | |
| 2172 | siz1 = opP->disp.size; |
| 2173 | if (opP->mode == POST || opP->mode == PRE) |
| 2174 | siz2 = opP->odisp.size; |
| 2175 | else |
| 2176 | siz2 = SIZE_UNSPEC; |
| 2177 | |
| 2178 | /* Index register stuff */ |
| 2179 | if (opP->index.reg != 0 |
| 2180 | && opP->index.reg >= DATA |
| 2181 | && opP->index.reg <= ADDR7) |
| 2182 | { |
| 2183 | nextword |= (opP->index.reg - DATA) << 12; |
| 2184 | |
| 2185 | if (opP->index.size == SIZE_LONG |
| 2186 | || (opP->index.size == SIZE_UNSPEC |
| 2187 | && m68k_index_width_default == SIZE_LONG)) |
| 2188 | nextword |= 0x800; |
| 2189 | |
| 2190 | if ((opP->index.scale != 1 |
| 2191 | && cpu_of_arch (current_architecture) < m68020) |
| 2192 | || (opP->index.scale == 8 |
| 2193 | && arch_coldfire_p (current_architecture))) |
| 2194 | { |
| 2195 | opP->error = |
| 2196 | _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher"); |
| 2197 | } |
| 2198 | |
| 2199 | if (arch_coldfire_p (current_architecture) |
| 2200 | && opP->index.size == SIZE_WORD) |
| 2201 | opP->error = _("invalid index size for coldfire"); |
| 2202 | |
| 2203 | switch (opP->index.scale) |
| 2204 | { |
| 2205 | case 1: |
| 2206 | break; |
| 2207 | case 2: |
| 2208 | nextword |= 0x200; |
| 2209 | break; |
| 2210 | case 4: |
| 2211 | nextword |= 0x400; |
| 2212 | break; |
| 2213 | case 8: |
| 2214 | nextword |= 0x600; |
| 2215 | break; |
| 2216 | default: |
| 2217 | abort (); |
| 2218 | } |
| 2219 | /* IF its simple, |
| 2220 | GET US OUT OF HERE! */ |
| 2221 | |
| 2222 | /* Must be INDEX, with an index register. Address |
| 2223 | register cannot be ZERO-PC, and either :b was |
| 2224 | forced, or we know it will fit. For a 68000 or |
| 2225 | 68010, force this mode anyways, because the |
| 2226 | larger modes aren't supported. */ |
| 2227 | if (opP->mode == BASE |
| 2228 | && ((opP->reg >= ADDR0 |
| 2229 | && opP->reg <= ADDR7) |
| 2230 | || opP->reg == PC)) |
| 2231 | { |
| 2232 | if (siz1 == SIZE_BYTE |
| 2233 | || cpu_of_arch (current_architecture) < m68020 |
| 2234 | || arch_coldfire_p (current_architecture) |
| 2235 | || (siz1 == SIZE_UNSPEC |
| 2236 | && ! isvar (&opP->disp) |
| 2237 | && issbyte (baseo))) |
| 2238 | { |
| 2239 | nextword += baseo & 0xff; |
| 2240 | addword (nextword); |
| 2241 | if (isvar (&opP->disp)) |
| 2242 | { |
| 2243 | /* Do a byte relocation. If it doesn't |
| 2244 | fit (possible on m68000) let the |
| 2245 | fixup processing complain later. */ |
| 2246 | if (opP->reg == PC) |
| 2247 | add_fix ('B', &opP->disp, 1, 1); |
| 2248 | else |
| 2249 | add_fix ('B', &opP->disp, 0, 0); |
| 2250 | } |
| 2251 | else if (siz1 != SIZE_BYTE) |
| 2252 | { |
| 2253 | if (siz1 != SIZE_UNSPEC) |
| 2254 | as_warn (_("Forcing byte displacement")); |
| 2255 | if (! issbyte (baseo)) |
| 2256 | opP->error = _("byte displacement out of range"); |
| 2257 | } |
| 2258 | |
| 2259 | break; |
| 2260 | } |
| 2261 | else if (siz1 == SIZE_UNSPEC |
| 2262 | && opP->reg == PC |
| 2263 | && isvar (&opP->disp) |
| 2264 | && subs (&opP->disp) == NULL |
| 2265 | #ifdef OBJ_ELF |
| 2266 | /* If the displacement needs pic |
| 2267 | relocation it cannot be relaxed. */ |
| 2268 | && opP->disp.pic_reloc == pic_none |
| 2269 | #endif |
| 2270 | ) |
| 2271 | { |
| 2272 | /* The code in md_convert_frag_1 needs to be |
| 2273 | able to adjust nextword. Call frag_grow |
| 2274 | to ensure that we have enough space in |
| 2275 | the frag obstack to make all the bytes |
| 2276 | contiguous. */ |
| 2277 | frag_grow (14); |
| 2278 | nextword += baseo & 0xff; |
| 2279 | addword (nextword); |
| 2280 | add_frag (adds (&opP->disp), offs (&opP->disp), |
| 2281 | TAB (PCINDEX, SZ_UNDEF)); |
| 2282 | |
| 2283 | break; |
| 2284 | } |
| 2285 | } |
| 2286 | } |
| 2287 | else |
| 2288 | { |
| 2289 | nextword |= 0x40; /* No index reg */ |
| 2290 | if (opP->index.reg >= ZDATA0 |
| 2291 | && opP->index.reg <= ZDATA7) |
| 2292 | nextword |= (opP->index.reg - ZDATA0) << 12; |
| 2293 | else if (opP->index.reg >= ZADDR0 |
| 2294 | || opP->index.reg <= ZADDR7) |
| 2295 | nextword |= (opP->index.reg - ZADDR0 + 8) << 12; |
| 2296 | } |
| 2297 | |
| 2298 | /* It isn't simple. */ |
| 2299 | |
| 2300 | if (cpu_of_arch (current_architecture) < m68020 |
| 2301 | || arch_coldfire_p (current_architecture)) |
| 2302 | opP->error = |
| 2303 | _("invalid operand mode for this architecture; needs 68020 or higher"); |
| 2304 | |
| 2305 | nextword |= 0x100; |
| 2306 | /* If the guy specified a width, we assume that it is |
| 2307 | wide enough. Maybe it isn't. If so, we lose. */ |
| 2308 | switch (siz1) |
| 2309 | { |
| 2310 | case SIZE_UNSPEC: |
| 2311 | if (isvar (&opP->disp) |
| 2312 | ? m68k_rel32 |
| 2313 | : ! issword (baseo)) |
| 2314 | { |
| 2315 | siz1 = SIZE_LONG; |
| 2316 | nextword |= 0x30; |
| 2317 | } |
| 2318 | else if (! isvar (&opP->disp) && baseo == 0) |
| 2319 | nextword |= 0x10; |
| 2320 | else |
| 2321 | { |
| 2322 | nextword |= 0x20; |
| 2323 | siz1 = SIZE_WORD; |
| 2324 | } |
| 2325 | break; |
| 2326 | case SIZE_BYTE: |
| 2327 | as_warn (_(":b not permitted; defaulting to :w")); |
| 2328 | /* Fall through. */ |
| 2329 | case SIZE_WORD: |
| 2330 | nextword |= 0x20; |
| 2331 | break; |
| 2332 | case SIZE_LONG: |
| 2333 | nextword |= 0x30; |
| 2334 | break; |
| 2335 | } |
| 2336 | |
| 2337 | /* Figure out innner displacement stuff */ |
| 2338 | if (opP->mode == POST || opP->mode == PRE) |
| 2339 | { |
| 2340 | if (cpu_of_arch (current_architecture) & cpu32) |
| 2341 | opP->error = _("invalid operand mode for this architecture; needs 68020 or higher"); |
| 2342 | switch (siz2) |
| 2343 | { |
| 2344 | case SIZE_UNSPEC: |
| 2345 | if (isvar (&opP->odisp) |
| 2346 | ? m68k_rel32 |
| 2347 | : ! issword (outro)) |
| 2348 | { |
| 2349 | siz2 = SIZE_LONG; |
| 2350 | nextword |= 0x3; |
| 2351 | } |
| 2352 | else if (! isvar (&opP->odisp) && outro == 0) |
| 2353 | nextword |= 0x1; |
| 2354 | else |
| 2355 | { |
| 2356 | nextword |= 0x2; |
| 2357 | siz2 = SIZE_WORD; |
| 2358 | } |
| 2359 | break; |
| 2360 | case 1: |
| 2361 | as_warn (_(":b not permitted; defaulting to :w")); |
| 2362 | /* Fall through. */ |
| 2363 | case 2: |
| 2364 | nextword |= 0x2; |
| 2365 | break; |
| 2366 | case 3: |
| 2367 | nextword |= 0x3; |
| 2368 | break; |
| 2369 | } |
| 2370 | if (opP->mode == POST |
| 2371 | && (nextword & 0x40) == 0) |
| 2372 | nextword |= 0x04; |
| 2373 | } |
| 2374 | addword (nextword); |
| 2375 | |
| 2376 | if (siz1 != SIZE_UNSPEC && isvar (&opP->disp)) |
| 2377 | { |
| 2378 | if (opP->reg == PC || opP->reg == ZPC) |
| 2379 | add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2); |
| 2380 | else |
| 2381 | add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0); |
| 2382 | } |
| 2383 | if (siz1 == SIZE_LONG) |
| 2384 | addword (baseo >> 16); |
| 2385 | if (siz1 != SIZE_UNSPEC) |
| 2386 | addword (baseo); |
| 2387 | |
| 2388 | if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp)) |
| 2389 | add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0); |
| 2390 | if (siz2 == SIZE_LONG) |
| 2391 | addword (outro >> 16); |
| 2392 | if (siz2 != SIZE_UNSPEC) |
| 2393 | addword (outro); |
| 2394 | |
| 2395 | break; |
| 2396 | |
| 2397 | case ABSL: |
| 2398 | nextword = get_num (&opP->disp, 80); |
| 2399 | switch (opP->disp.size) |
| 2400 | { |
| 2401 | default: |
| 2402 | abort (); |
| 2403 | case SIZE_UNSPEC: |
| 2404 | if (!isvar (&opP->disp) && issword (offs (&opP->disp))) |
| 2405 | { |
| 2406 | tmpreg = 0x38; /* 7.0 */ |
| 2407 | addword (nextword); |
| 2408 | break; |
| 2409 | } |
| 2410 | if (isvar (&opP->disp) |
| 2411 | && !subs (&opP->disp) |
| 2412 | && adds (&opP->disp) |
| 2413 | #ifdef OBJ_ELF |
| 2414 | /* If the displacement needs pic relocation it |
| 2415 | cannot be relaxed. */ |
| 2416 | && opP->disp.pic_reloc == pic_none |
| 2417 | #endif |
| 2418 | && !flag_long_jumps |
| 2419 | && !strchr ("~%&$?", s[0])) |
| 2420 | { |
| 2421 | tmpreg = 0x3A; /* 7.2 */ |
| 2422 | add_frag (adds (&opP->disp), |
| 2423 | offs (&opP->disp), |
| 2424 | TAB (ABSTOPCREL, SZ_UNDEF)); |
| 2425 | break; |
| 2426 | } |
| 2427 | /* Fall through into long */ |
| 2428 | case SIZE_LONG: |
| 2429 | if (isvar (&opP->disp)) |
| 2430 | add_fix ('l', &opP->disp, 0, 0); |
| 2431 | |
| 2432 | tmpreg = 0x39;/* 7.1 mode */ |
| 2433 | addword (nextword >> 16); |
| 2434 | addword (nextword); |
| 2435 | break; |
| 2436 | |
| 2437 | case SIZE_BYTE: |
| 2438 | as_bad (_("unsupported byte value; use a different suffix")); |
| 2439 | /* Fall through. */ |
| 2440 | case SIZE_WORD: /* Word */ |
| 2441 | if (isvar (&opP->disp)) |
| 2442 | add_fix ('w', &opP->disp, 0, 0); |
| 2443 | |
| 2444 | tmpreg = 0x38;/* 7.0 mode */ |
| 2445 | addword (nextword); |
| 2446 | break; |
| 2447 | } |
| 2448 | break; |
| 2449 | case CONTROL: |
| 2450 | case FPREG: |
| 2451 | default: |
| 2452 | as_bad (_("unknown/incorrect operand")); |
| 2453 | /* abort (); */ |
| 2454 | } |
| 2455 | install_gen_operand (s[1], tmpreg); |
| 2456 | break; |
| 2457 | |
| 2458 | case '#': |
| 2459 | case '^': |
| 2460 | switch (s[1]) |
| 2461 | { /* JF: I hate floating point! */ |
| 2462 | case 'j': |
| 2463 | tmpreg = 70; |
| 2464 | break; |
| 2465 | case '8': |
| 2466 | tmpreg = 20; |
| 2467 | break; |
| 2468 | case 'C': |
| 2469 | tmpreg = 50; |
| 2470 | break; |
| 2471 | case '3': |
| 2472 | default: |
| 2473 | tmpreg = 80; |
| 2474 | break; |
| 2475 | } |
| 2476 | tmpreg = get_num (&opP->disp, tmpreg); |
| 2477 | if (isvar (&opP->disp)) |
| 2478 | add_fix (s[1], &opP->disp, 0, 0); |
| 2479 | switch (s[1]) |
| 2480 | { |
| 2481 | case 'b': /* Danger: These do no check for |
| 2482 | certain types of overflow. |
| 2483 | user beware! */ |
| 2484 | if (!isbyte (tmpreg)) |
| 2485 | opP->error = _("out of range"); |
| 2486 | insop (tmpreg, opcode); |
| 2487 | if (isvar (&opP->disp)) |
| 2488 | the_ins.reloc[the_ins.nrel - 1].n = |
| 2489 | (opcode->m_codenum) * 2 + 1; |
| 2490 | break; |
| 2491 | case 'B': |
| 2492 | if (!issbyte (tmpreg)) |
| 2493 | opP->error = _("out of range"); |
| 2494 | the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff; |
| 2495 | if (isvar (&opP->disp)) |
| 2496 | the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1; |
| 2497 | break; |
| 2498 | case 'w': |
| 2499 | if (!isword (tmpreg)) |
| 2500 | opP->error = _("out of range"); |
| 2501 | insop (tmpreg, opcode); |
| 2502 | if (isvar (&opP->disp)) |
| 2503 | the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; |
| 2504 | break; |
| 2505 | case 'W': |
| 2506 | if (!issword (tmpreg)) |
| 2507 | opP->error = _("out of range"); |
| 2508 | insop (tmpreg, opcode); |
| 2509 | if (isvar (&opP->disp)) |
| 2510 | the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; |
| 2511 | break; |
| 2512 | case 'l': |
| 2513 | /* Because of the way insop works, we put these two out |
| 2514 | backwards. */ |
| 2515 | insop (tmpreg, opcode); |
| 2516 | insop (tmpreg >> 16, opcode); |
| 2517 | if (isvar (&opP->disp)) |
| 2518 | the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; |
| 2519 | break; |
| 2520 | case '3': |
| 2521 | tmpreg &= 0xFF; |
| 2522 | case '8': |
| 2523 | case 'C': |
| 2524 | case 'j': |
| 2525 | install_operand (s[1], tmpreg); |
| 2526 | break; |
| 2527 | default: |
| 2528 | abort (); |
| 2529 | } |
| 2530 | break; |
| 2531 | |
| 2532 | case '+': |
| 2533 | case '-': |
| 2534 | case 'A': |
| 2535 | case 'a': |
| 2536 | install_operand (s[1], opP->reg - ADDR); |
| 2537 | break; |
| 2538 | |
| 2539 | case 'B': |
| 2540 | tmpreg = get_num (&opP->disp, 80); |
| 2541 | switch (s[1]) |
| 2542 | { |
| 2543 | case 'B': |
| 2544 | add_fix ('B', &opP->disp, 1, -1); |
| 2545 | break; |
| 2546 | case 'W': |
| 2547 | add_fix ('w', &opP->disp, 1, 0); |
| 2548 | addword (0); |
| 2549 | break; |
| 2550 | case 'L': |
| 2551 | long_branch: |
| 2552 | if (! HAVE_LONG_BRANCH (current_architecture)) |
| 2553 | as_warn (_("Can't use long branches on 68000/68010/5200")); |
| 2554 | the_ins.opcode[0] |= 0xff; |
| 2555 | add_fix ('l', &opP->disp, 1, 0); |
| 2556 | addword (0); |
| 2557 | addword (0); |
| 2558 | break; |
| 2559 | case 'g': |
| 2560 | if (subs (&opP->disp)) /* We can't relax it */ |
| 2561 | goto long_branch; |
| 2562 | |
| 2563 | #ifdef OBJ_ELF |
| 2564 | /* If the displacement needs pic relocation it cannot be |
| 2565 | relaxed. */ |
| 2566 | if (opP->disp.pic_reloc != pic_none) |
| 2567 | goto long_branch; |
| 2568 | #endif |
| 2569 | /* This could either be a symbol, or an absolute |
| 2570 | address. If it's an absolute address, turn it into |
| 2571 | an absolute jump right here and keep it out of the |
| 2572 | relaxer. */ |
| 2573 | if (adds (&opP->disp) == 0) |
| 2574 | { |
| 2575 | if (the_ins.opcode[0] == 0x6000) /* jbra */ |
| 2576 | the_ins.opcode[0] = 0x4EF9; |
| 2577 | else if (the_ins.opcode[0] == 0x6100) /* jbsr */ |
| 2578 | the_ins.opcode[0] = 0x4EB9; |
| 2579 | else /* jCC */ |
| 2580 | { |
| 2581 | the_ins.opcode[0] ^= 0x0100; |
| 2582 | the_ins.opcode[0] |= 0x0006; |
| 2583 | addword (0x4EF9); |
| 2584 | } |
| 2585 | add_fix ('l', &opP->disp, 0, 0); |
| 2586 | addword (0); |
| 2587 | addword (0); |
| 2588 | break; |
| 2589 | } |
| 2590 | |
| 2591 | /* Now we know it's going into the relaxer. Now figure |
| 2592 | out which mode. We try in this order of preference: |
| 2593 | long branch, absolute jump, byte/word branches only. */ |
| 2594 | if (HAVE_LONG_BRANCH (current_architecture)) |
| 2595 | add_frag (adds (&opP->disp), offs (&opP->disp), |
| 2596 | TAB (BRANCHBWL, SZ_UNDEF)); |
| 2597 | else if (! flag_keep_pcrel) |
| 2598 | { |
| 2599 | if ((the_ins.opcode[0] == 0x6000) |
| 2600 | || (the_ins.opcode[0] == 0x6100)) |
| 2601 | add_frag (adds (&opP->disp), offs (&opP->disp), |
| 2602 | TAB (BRABSJUNC, SZ_UNDEF)); |
| 2603 | else |
| 2604 | add_frag (adds (&opP->disp), offs (&opP->disp), |
| 2605 | TAB (BRABSJCOND, SZ_UNDEF)); |
| 2606 | } |
| 2607 | else |
| 2608 | add_frag (adds (&opP->disp), offs (&opP->disp), |
| 2609 | TAB (BRANCHBW, SZ_UNDEF)); |
| 2610 | break; |
| 2611 | case 'w': |
| 2612 | if (isvar (&opP->disp)) |
| 2613 | { |
| 2614 | /* Check for DBcc instructions. We can relax them, |
| 2615 | but only if we have long branches and/or absolute |
| 2616 | jumps. */ |
| 2617 | if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8) |
| 2618 | && (HAVE_LONG_BRANCH (current_architecture) |
| 2619 | || (! flag_keep_pcrel))) |
| 2620 | { |
| 2621 | if (HAVE_LONG_BRANCH (current_architecture)) |
| 2622 | add_frag (adds (&opP->disp), offs (&opP->disp), |
| 2623 | TAB (DBCCLBR, SZ_UNDEF)); |
| 2624 | else |
| 2625 | add_frag (adds (&opP->disp), offs (&opP->disp), |
| 2626 | TAB (DBCCABSJ, SZ_UNDEF)); |
| 2627 | break; |
| 2628 | } |
| 2629 | add_fix ('w', &opP->disp, 1, 0); |
| 2630 | } |
| 2631 | addword (0); |
| 2632 | break; |
| 2633 | case 'C': /* Fixed size LONG coproc branches */ |
| 2634 | add_fix ('l', &opP->disp, 1, 0); |
| 2635 | addword (0); |
| 2636 | addword (0); |
| 2637 | break; |
| 2638 | case 'c': /* Var size Coprocesssor branches */ |
| 2639 | if (subs (&opP->disp) || (adds (&opP->disp) == 0)) |
| 2640 | { |
| 2641 | the_ins.opcode[the_ins.numo - 1] |= 0x40; |
| 2642 | add_fix ('l', &opP->disp, 1, 0); |
| 2643 | addword (0); |
| 2644 | addword (0); |
| 2645 | } |
| 2646 | else |
| 2647 | add_frag (adds (&opP->disp), offs (&opP->disp), |
| 2648 | TAB (FBRANCH, SZ_UNDEF)); |
| 2649 | break; |
| 2650 | default: |
| 2651 | abort (); |
| 2652 | } |
| 2653 | break; |
| 2654 | |
| 2655 | case 'C': /* Ignore it */ |
| 2656 | break; |
| 2657 | |
| 2658 | case 'd': /* JF this is a kludge */ |
| 2659 | install_operand ('s', opP->reg - ADDR); |
| 2660 | tmpreg = get_num (&opP->disp, 80); |
| 2661 | if (!issword (tmpreg)) |
| 2662 | { |
| 2663 | as_warn (_("Expression out of range, using 0")); |
| 2664 | tmpreg = 0; |
| 2665 | } |
| 2666 | addword (tmpreg); |
| 2667 | break; |
| 2668 | |
| 2669 | case 'D': |
| 2670 | install_operand (s[1], opP->reg - DATA); |
| 2671 | break; |
| 2672 | |
| 2673 | case 'E': /* Ignore it */ |
| 2674 | break; |
| 2675 | |
| 2676 | case 'F': |
| 2677 | install_operand (s[1], opP->reg - FP0); |
| 2678 | break; |
| 2679 | |
| 2680 | case 'G': /* Ignore it */ |
| 2681 | case 'H': |
| 2682 | break; |
| 2683 | |
| 2684 | case 'I': |
| 2685 | tmpreg = opP->reg - COP0; |
| 2686 | install_operand (s[1], tmpreg); |
| 2687 | break; |
| 2688 | |
| 2689 | case 'J': /* JF foo */ |
| 2690 | switch (opP->reg) |
| 2691 | { |
| 2692 | case SFC: |
| 2693 | tmpreg = 0x000; |
| 2694 | break; |
| 2695 | case DFC: |
| 2696 | tmpreg = 0x001; |
| 2697 | break; |
| 2698 | case CACR: |
| 2699 | tmpreg = 0x002; |
| 2700 | break; |
| 2701 | case TC: |
| 2702 | tmpreg = 0x003; |
| 2703 | break; |
| 2704 | case ITT0: |
| 2705 | tmpreg = 0x004; |
| 2706 | break; |
| 2707 | case ITT1: |
| 2708 | tmpreg = 0x005; |
| 2709 | break; |
| 2710 | case DTT0: |
| 2711 | tmpreg = 0x006; |
| 2712 | break; |
| 2713 | case DTT1: |
| 2714 | tmpreg = 0x007; |
| 2715 | break; |
| 2716 | case BUSCR: |
| 2717 | tmpreg = 0x008; |
| 2718 | break; |
| 2719 | |
| 2720 | case USP: |
| 2721 | tmpreg = 0x800; |
| 2722 | break; |
| 2723 | case VBR: |
| 2724 | tmpreg = 0x801; |
| 2725 | break; |
| 2726 | case CAAR: |
| 2727 | tmpreg = 0x802; |
| 2728 | break; |
| 2729 | case MSP: |
| 2730 | tmpreg = 0x803; |
| 2731 | break; |
| 2732 | case ISP: |
| 2733 | tmpreg = 0x804; |
| 2734 | break; |
| 2735 | case MMUSR: |
| 2736 | tmpreg = 0x805; |
| 2737 | break; |
| 2738 | case URP: |
| 2739 | tmpreg = 0x806; |
| 2740 | break; |
| 2741 | case SRP: |
| 2742 | tmpreg = 0x807; |
| 2743 | break; |
| 2744 | case PCR: |
| 2745 | tmpreg = 0x808; |
| 2746 | break; |
| 2747 | case ROMBAR: |
| 2748 | tmpreg = 0xC00; |
| 2749 | break; |
| 2750 | case RAMBAR0: |
| 2751 | tmpreg = 0xC04; |
| 2752 | break; |
| 2753 | case RAMBAR1: |
| 2754 | tmpreg = 0xC05; |
| 2755 | break; |
| 2756 | case MBAR: |
| 2757 | tmpreg = 0xC0F; |
| 2758 | break; |
| 2759 | default: |
| 2760 | abort (); |
| 2761 | } |
| 2762 | install_operand (s[1], tmpreg); |
| 2763 | break; |
| 2764 | |
| 2765 | case 'k': |
| 2766 | tmpreg = get_num (&opP->disp, 55); |
| 2767 | install_operand (s[1], tmpreg & 0x7f); |
| 2768 | break; |
| 2769 | |
| 2770 | case 'l': |
| 2771 | tmpreg = opP->mask; |
| 2772 | if (s[1] == 'w') |
| 2773 | { |
| 2774 | if (tmpreg & 0x7FF0000) |
| 2775 | as_bad (_("Floating point register in register list")); |
| 2776 | insop (reverse_16_bits (tmpreg), opcode); |
| 2777 | } |
| 2778 | else |
| 2779 | { |
| 2780 | if (tmpreg & 0x700FFFF) |
| 2781 | as_bad (_("Wrong register in floating-point reglist")); |
| 2782 | install_operand (s[1], reverse_8_bits (tmpreg >> 16)); |
| 2783 | } |
| 2784 | break; |
| 2785 | |
| 2786 | case 'L': |
| 2787 | tmpreg = opP->mask; |
| 2788 | if (s[1] == 'w') |
| 2789 | { |
| 2790 | if (tmpreg & 0x7FF0000) |
| 2791 | as_bad (_("Floating point register in register list")); |
| 2792 | insop (tmpreg, opcode); |
| 2793 | } |
| 2794 | else if (s[1] == '8') |
| 2795 | { |
| 2796 | if (tmpreg & 0x0FFFFFF) |
| 2797 | as_bad (_("incorrect register in reglist")); |
| 2798 | install_operand (s[1], tmpreg >> 24); |
| 2799 | } |
| 2800 | else |
| 2801 | { |
| 2802 | if (tmpreg & 0x700FFFF) |
| 2803 | as_bad (_("wrong register in floating-point reglist")); |
| 2804 | else |
| 2805 | install_operand (s[1], tmpreg >> 16); |
| 2806 | } |
| 2807 | break; |
| 2808 | |
| 2809 | case 'M': |
| 2810 | install_operand (s[1], get_num (&opP->disp, 60)); |
| 2811 | break; |
| 2812 | |
| 2813 | case 'O': |
| 2814 | tmpreg = ((opP->mode == DREG) |
| 2815 | ? 0x20 + (int) (opP->reg - DATA) |
| 2816 | : (get_num (&opP->disp, 40) & 0x1F)); |
| 2817 | install_operand (s[1], tmpreg); |
| 2818 | break; |
| 2819 | |
| 2820 | case 'Q': |
| 2821 | tmpreg = get_num (&opP->disp, 10); |
| 2822 | if (tmpreg == 8) |
| 2823 | tmpreg = 0; |
| 2824 | install_operand (s[1], tmpreg); |
| 2825 | break; |
| 2826 | |
| 2827 | case 'R': |
| 2828 | /* This depends on the fact that ADDR registers are eight |
| 2829 | more than their corresponding DATA regs, so the result |
| 2830 | will have the ADDR_REG bit set */ |
| 2831 | install_operand (s[1], opP->reg - DATA); |
| 2832 | break; |
| 2833 | |
| 2834 | case 'r': |
| 2835 | if (opP->mode == AINDR) |
| 2836 | install_operand (s[1], opP->reg - DATA); |
| 2837 | else |
| 2838 | install_operand (s[1], opP->index.reg - DATA); |
| 2839 | break; |
| 2840 | |
| 2841 | case 's': |
| 2842 | if (opP->reg == FPI) |
| 2843 | tmpreg = 0x1; |
| 2844 | else if (opP->reg == FPS) |
| 2845 | tmpreg = 0x2; |
| 2846 | else if (opP->reg == FPC) |
| 2847 | tmpreg = 0x4; |
| 2848 | else |
| 2849 | abort (); |
| 2850 | install_operand (s[1], tmpreg); |
| 2851 | break; |
| 2852 | |
| 2853 | case 'S': /* Ignore it */ |
| 2854 | break; |
| 2855 | |
| 2856 | case 'T': |
| 2857 | install_operand (s[1], get_num (&opP->disp, 30)); |
| 2858 | break; |
| 2859 | |
| 2860 | case 'U': /* Ignore it */ |
| 2861 | break; |
| 2862 | |
| 2863 | case 'c': |
| 2864 | switch (opP->reg) |
| 2865 | { |
| 2866 | case NC: |
| 2867 | tmpreg = 0; |
| 2868 | break; |
| 2869 | case DC: |
| 2870 | tmpreg = 1; |
| 2871 | break; |
| 2872 | case IC: |
| 2873 | tmpreg = 2; |
| 2874 | break; |
| 2875 | case BC: |
| 2876 | tmpreg = 3; |
| 2877 | break; |
| 2878 | default: |
| 2879 | as_fatal (_("failed sanity check")); |
| 2880 | } /* switch on cache token */ |
| 2881 | install_operand (s[1], tmpreg); |
| 2882 | break; |
| 2883 | #ifndef NO_68851 |
| 2884 | /* JF: These are out of order, I fear. */ |
| 2885 | case 'f': |
| 2886 | switch (opP->reg) |
| 2887 | { |
| 2888 | case SFC: |
| 2889 | tmpreg = 0; |
| 2890 | break; |
| 2891 | case DFC: |
| 2892 | tmpreg = 1; |
| 2893 | break; |
| 2894 | default: |
| 2895 | abort (); |
| 2896 | } |
| 2897 | install_operand (s[1], tmpreg); |
| 2898 | break; |
| 2899 | |
| 2900 | case '0': |
| 2901 | case '1': |
| 2902 | case '2': |
| 2903 | switch (opP->reg) |
| 2904 | { |
| 2905 | case TC: |
| 2906 | tmpreg = 0; |
| 2907 | break; |
| 2908 | case CAL: |
| 2909 | tmpreg = 4; |
| 2910 | break; |
| 2911 | case VAL: |
| 2912 | tmpreg = 5; |
| 2913 | break; |
| 2914 | case SCC: |
| 2915 | tmpreg = 6; |
| 2916 | break; |
| 2917 | case AC: |
| 2918 | tmpreg = 7; |
| 2919 | break; |
| 2920 | default: |
| 2921 | abort (); |
| 2922 | } |
| 2923 | install_operand (s[1], tmpreg); |
| 2924 | break; |
| 2925 | |
| 2926 | case 'V': |
| 2927 | if (opP->reg == VAL) |
| 2928 | break; |
| 2929 | abort (); |
| 2930 | |
| 2931 | case 'W': |
| 2932 | switch (opP->reg) |
| 2933 | { |
| 2934 | case DRP: |
| 2935 | tmpreg = 1; |
| 2936 | break; |
| 2937 | case SRP: |
| 2938 | tmpreg = 2; |
| 2939 | break; |
| 2940 | case CRP: |
| 2941 | tmpreg = 3; |
| 2942 | break; |
| 2943 | default: |
| 2944 | abort (); |
| 2945 | } |
| 2946 | install_operand (s[1], tmpreg); |
| 2947 | break; |
| 2948 | |
| 2949 | case 'X': |
| 2950 | switch (opP->reg) |
| 2951 | { |
| 2952 | case BAD: |
| 2953 | case BAD + 1: |
| 2954 | case BAD + 2: |
| 2955 | case BAD + 3: |
| 2956 | case BAD + 4: |
| 2957 | case BAD + 5: |
| 2958 | case BAD + 6: |
| 2959 | case BAD + 7: |
| 2960 | tmpreg = (4 << 10) | ((opP->reg - BAD) << 2); |
| 2961 | break; |
| 2962 | |
| 2963 | case BAC: |
| 2964 | case BAC + 1: |
| 2965 | case BAC + 2: |
| 2966 | case BAC + 3: |
| 2967 | case BAC + 4: |
| 2968 | case BAC + 5: |
| 2969 | case BAC + 6: |
| 2970 | case BAC + 7: |
| 2971 | tmpreg = (5 << 10) | ((opP->reg - BAC) << 2); |
| 2972 | break; |
| 2973 | |
| 2974 | default: |
| 2975 | abort (); |
| 2976 | } |
| 2977 | install_operand (s[1], tmpreg); |
| 2978 | break; |
| 2979 | case 'Y': |
| 2980 | know (opP->reg == PSR); |
| 2981 | break; |
| 2982 | case 'Z': |
| 2983 | know (opP->reg == PCSR); |
| 2984 | break; |
| 2985 | #endif /* m68851 */ |
| 2986 | case '3': |
| 2987 | switch (opP->reg) |
| 2988 | { |
| 2989 | case TT0: |
| 2990 | tmpreg = 2; |
| 2991 | break; |
| 2992 | case TT1: |
| 2993 | tmpreg = 3; |
| 2994 | break; |
| 2995 | default: |
| 2996 | abort (); |
| 2997 | } |
| 2998 | install_operand (s[1], tmpreg); |
| 2999 | break; |
| 3000 | case 't': |
| 3001 | tmpreg = get_num (&opP->disp, 20); |
| 3002 | install_operand (s[1], tmpreg); |
| 3003 | break; |
| 3004 | case '_': /* used only for move16 absolute 32-bit address */ |
| 3005 | if (isvar (&opP->disp)) |
| 3006 | add_fix ('l', &opP->disp, 0, 0); |
| 3007 | tmpreg = get_num (&opP->disp, 80); |
| 3008 | addword (tmpreg >> 16); |
| 3009 | addword (tmpreg & 0xFFFF); |
| 3010 | break; |
| 3011 | case 'u': |
| 3012 | install_operand (s[1], opP->reg - DATA0L); |
| 3013 | opP->reg -= (DATA0L); |
| 3014 | opP->reg &= 0x0F; /* remove upper/lower bit */ |
| 3015 | break; |
| 3016 | default: |
| 3017 | abort (); |
| 3018 | } |
| 3019 | } |
| 3020 | |
| 3021 | /* By the time whe get here (FINALLY) the_ins contains the complete |
| 3022 | instruction, ready to be emitted. . . */ |
| 3023 | } |
| 3024 | |
| 3025 | static int |
| 3026 | reverse_16_bits (in) |
| 3027 | int in; |
| 3028 | { |
| 3029 | int out = 0; |
| 3030 | int n; |
| 3031 | |
| 3032 | static int mask[16] = |
| 3033 | { |
| 3034 | 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, |
| 3035 | 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000 |
| 3036 | }; |
| 3037 | for (n = 0; n < 16; n++) |
| 3038 | { |
| 3039 | if (in & mask[n]) |
| 3040 | out |= mask[15 - n]; |
| 3041 | } |
| 3042 | return out; |
| 3043 | } /* reverse_16_bits() */ |
| 3044 | |
| 3045 | static int |
| 3046 | reverse_8_bits (in) |
| 3047 | int in; |
| 3048 | { |
| 3049 | int out = 0; |
| 3050 | int n; |
| 3051 | |
| 3052 | static int mask[8] = |
| 3053 | { |
| 3054 | 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, |
| 3055 | }; |
| 3056 | |
| 3057 | for (n = 0; n < 8; n++) |
| 3058 | { |
| 3059 | if (in & mask[n]) |
| 3060 | out |= mask[7 - n]; |
| 3061 | } |
| 3062 | return out; |
| 3063 | } /* reverse_8_bits() */ |
| 3064 | |
| 3065 | /* Cause an extra frag to be generated here, inserting up to 10 bytes |
| 3066 | (that value is chosen in the frag_var call in md_assemble). TYPE |
| 3067 | is the subtype of the frag to be generated; its primary type is |
| 3068 | rs_machine_dependent. |
| 3069 | |
| 3070 | The TYPE parameter is also used by md_convert_frag_1 and |
| 3071 | md_estimate_size_before_relax. The appropriate type of fixup will |
| 3072 | be emitted by md_convert_frag_1. |
| 3073 | |
| 3074 | ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */ |
| 3075 | static void |
| 3076 | install_operand (mode, val) |
| 3077 | int mode; |
| 3078 | int val; |
| 3079 | { |
| 3080 | switch (mode) |
| 3081 | { |
| 3082 | case 's': |
| 3083 | the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */ |
| 3084 | break; |
| 3085 | case 'd': |
| 3086 | the_ins.opcode[0] |= val << 9; |
| 3087 | break; |
| 3088 | case '1': |
| 3089 | the_ins.opcode[1] |= val << 12; |
| 3090 | break; |
| 3091 | case '2': |
| 3092 | the_ins.opcode[1] |= val << 6; |
| 3093 | break; |
| 3094 | case '3': |
| 3095 | the_ins.opcode[1] |= val; |
| 3096 | break; |
| 3097 | case '4': |
| 3098 | the_ins.opcode[2] |= val << 12; |
| 3099 | break; |
| 3100 | case '5': |
| 3101 | the_ins.opcode[2] |= val << 6; |
| 3102 | break; |
| 3103 | case '6': |
| 3104 | /* DANGER! This is a hack to force cas2l and cas2w cmds to be |
| 3105 | three words long! */ |
| 3106 | the_ins.numo++; |
| 3107 | the_ins.opcode[2] |= val; |
| 3108 | break; |
| 3109 | case '7': |
| 3110 | the_ins.opcode[1] |= val << 7; |
| 3111 | break; |
| 3112 | case '8': |
| 3113 | the_ins.opcode[1] |= val << 10; |
| 3114 | break; |
| 3115 | #ifndef NO_68851 |
| 3116 | case '9': |
| 3117 | the_ins.opcode[1] |= val << 5; |
| 3118 | break; |
| 3119 | #endif |
| 3120 | |
| 3121 | case 't': |
| 3122 | the_ins.opcode[1] |= (val << 10) | (val << 7); |
| 3123 | break; |
| 3124 | case 'D': |
| 3125 | the_ins.opcode[1] |= (val << 12) | val; |
| 3126 | break; |
| 3127 | case 'g': |
| 3128 | the_ins.opcode[0] |= val = 0xff; |
| 3129 | break; |
| 3130 | case 'i': |
| 3131 | the_ins.opcode[0] |= val << 9; |
| 3132 | break; |
| 3133 | case 'C': |
| 3134 | the_ins.opcode[1] |= val; |
| 3135 | break; |
| 3136 | case 'j': |
| 3137 | the_ins.opcode[1] |= val; |
| 3138 | the_ins.numo++; /* What a hack */ |
| 3139 | break; |
| 3140 | case 'k': |
| 3141 | the_ins.opcode[1] |= val << 4; |
| 3142 | break; |
| 3143 | case 'b': |
| 3144 | case 'w': |
| 3145 | case 'W': |
| 3146 | case 'l': |
| 3147 | break; |
| 3148 | case 'e': |
| 3149 | the_ins.opcode[0] |= (val << 6); |
| 3150 | break; |
| 3151 | case 'L': |
| 3152 | the_ins.opcode[1] = (val >> 16); |
| 3153 | the_ins.opcode[2] = val & 0xffff; |
| 3154 | break; |
| 3155 | case 'm': |
| 3156 | the_ins.opcode[0] |= ((val & 0x8) << (6 - 3)); |
| 3157 | the_ins.opcode[0] |= ((val & 0x7) << 9); |
| 3158 | the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); |
| 3159 | break; |
| 3160 | case 'n': |
| 3161 | the_ins.opcode[0] |= ((val & 0x8) << (6 - 3)); |
| 3162 | the_ins.opcode[0] |= ((val & 0x7) << 9); |
| 3163 | break; |
| 3164 | case 'o': |
| 3165 | the_ins.opcode[1] |= val << 12; |
| 3166 | the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); |
| 3167 | break; |
| 3168 | case 'M': |
| 3169 | the_ins.opcode[0] |= (val & 0xF); |
| 3170 | the_ins.opcode[1] |= ((val & 0x10) << (6 - 4)); |
| 3171 | break; |
| 3172 | case 'N': |
| 3173 | the_ins.opcode[1] |= (val & 0xF); |
| 3174 | the_ins.opcode[1] |= ((val & 0x10) << (6 - 4)); |
| 3175 | break; |
| 3176 | case 'h': |
| 3177 | the_ins.opcode[1] |= ((val != 1) << 10); |
| 3178 | break; |
| 3179 | case 'c': |
| 3180 | default: |
| 3181 | as_fatal (_("failed sanity check.")); |
| 3182 | } |
| 3183 | } /* install_operand() */ |
| 3184 | |
| 3185 | static void |
| 3186 | install_gen_operand (mode, val) |
| 3187 | int mode; |
| 3188 | int val; |
| 3189 | { |
| 3190 | switch (mode) |
| 3191 | { |
| 3192 | case 's': |
| 3193 | the_ins.opcode[0] |= val; |
| 3194 | break; |
| 3195 | case 'd': |
| 3196 | /* This is a kludge!!! */ |
| 3197 | the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3; |
| 3198 | break; |
| 3199 | case 'b': |
| 3200 | case 'w': |
| 3201 | case 'l': |
| 3202 | case 'f': |
| 3203 | case 'F': |
| 3204 | case 'x': |
| 3205 | case 'p': |
| 3206 | the_ins.opcode[0] |= val; |
| 3207 | break; |
| 3208 | /* more stuff goes here */ |
| 3209 | default: |
| 3210 | as_fatal (_("failed sanity check.")); |
| 3211 | } |
| 3212 | } /* install_gen_operand() */ |
| 3213 | |
| 3214 | /* |
| 3215 | * verify that we have some number of paren pairs, do m68k_ip_op(), and |
| 3216 | * then deal with the bitfield hack. |
| 3217 | */ |
| 3218 | |
| 3219 | static char * |
| 3220 | crack_operand (str, opP) |
| 3221 | register char *str; |
| 3222 | register struct m68k_op *opP; |
| 3223 | { |
| 3224 | register int parens; |
| 3225 | register int c; |
| 3226 | register char *beg_str; |
| 3227 | int inquote = 0; |
| 3228 | |
| 3229 | if (!str) |
| 3230 | { |
| 3231 | return str; |
| 3232 | } |
| 3233 | beg_str = str; |
| 3234 | for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++) |
| 3235 | { |
| 3236 | if (! inquote) |
| 3237 | { |
| 3238 | if (*str == '(') |
| 3239 | parens++; |
| 3240 | else if (*str == ')') |
| 3241 | { |
| 3242 | if (!parens) |
| 3243 | { /* ERROR */ |
| 3244 | opP->error = _("Extra )"); |
| 3245 | return str; |
| 3246 | } |
| 3247 | --parens; |
| 3248 | } |
| 3249 | } |
| 3250 | if (flag_mri && *str == '\'') |
| 3251 | inquote = ! inquote; |
| 3252 | } |
| 3253 | if (!*str && parens) |
| 3254 | { /* ERROR */ |
| 3255 | opP->error = _("Missing )"); |
| 3256 | return str; |
| 3257 | } |
| 3258 | c = *str; |
| 3259 | *str = '\0'; |
| 3260 | if (m68k_ip_op (beg_str, opP) != 0) |
| 3261 | { |
| 3262 | *str = c; |
| 3263 | return str; |
| 3264 | } |
| 3265 | *str = c; |
| 3266 | if (c == '}') |
| 3267 | c = *++str; /* JF bitfield hack */ |
| 3268 | if (c) |
| 3269 | { |
| 3270 | c = *++str; |
| 3271 | if (!c) |
| 3272 | as_bad (_("Missing operand")); |
| 3273 | } |
| 3274 | |
| 3275 | /* Detect MRI REG symbols and convert them to REGLSTs. */ |
| 3276 | if (opP->mode == CONTROL && (int)opP->reg < 0) |
| 3277 | { |
| 3278 | opP->mode = REGLST; |
| 3279 | opP->mask = ~(int)opP->reg; |
| 3280 | opP->reg = 0; |
| 3281 | } |
| 3282 | |
| 3283 | return str; |
| 3284 | } |
| 3285 | |
| 3286 | /* This is the guts of the machine-dependent assembler. STR points to a |
| 3287 | machine dependent instruction. This function is supposed to emit |
| 3288 | the frags/bytes it assembles to. |
| 3289 | */ |
| 3290 | |
| 3291 | static void |
| 3292 | insert_reg (regname, regnum) |
| 3293 | const char *regname; |
| 3294 | int regnum; |
| 3295 | { |
| 3296 | char buf[100]; |
| 3297 | int i; |
| 3298 | |
| 3299 | #ifdef REGISTER_PREFIX |
| 3300 | if (!flag_reg_prefix_optional) |
| 3301 | { |
| 3302 | buf[0] = REGISTER_PREFIX; |
| 3303 | strcpy (buf + 1, regname); |
| 3304 | regname = buf; |
| 3305 | } |
| 3306 | #endif |
| 3307 | |
| 3308 | symbol_table_insert (symbol_new (regname, reg_section, regnum, |
| 3309 | &zero_address_frag)); |
| 3310 | |
| 3311 | for (i = 0; regname[i]; i++) |
| 3312 | buf[i] = TOUPPER (regname[i]); |
| 3313 | buf[i] = '\0'; |
| 3314 | |
| 3315 | symbol_table_insert (symbol_new (buf, reg_section, regnum, |
| 3316 | &zero_address_frag)); |
| 3317 | } |
| 3318 | |
| 3319 | struct init_entry |
| 3320 | { |
| 3321 | const char *name; |
| 3322 | int number; |
| 3323 | }; |
| 3324 | |
| 3325 | static const struct init_entry init_table[] = |
| 3326 | { |
| 3327 | { "d0", DATA0 }, |
| 3328 | { "d1", DATA1 }, |
| 3329 | { "d2", DATA2 }, |
| 3330 | { "d3", DATA3 }, |
| 3331 | { "d4", DATA4 }, |
| 3332 | { "d5", DATA5 }, |
| 3333 | { "d6", DATA6 }, |
| 3334 | { "d7", DATA7 }, |
| 3335 | { "a0", ADDR0 }, |
| 3336 | { "a1", ADDR1 }, |
| 3337 | { "a2", ADDR2 }, |
| 3338 | { "a3", ADDR3 }, |
| 3339 | { "a4", ADDR4 }, |
| 3340 | { "a5", ADDR5 }, |
| 3341 | { "a6", ADDR6 }, |
| 3342 | { "fp", ADDR6 }, |
| 3343 | { "a7", ADDR7 }, |
| 3344 | { "sp", ADDR7 }, |
| 3345 | { "ssp", ADDR7 }, |
| 3346 | { "fp0", FP0 }, |
| 3347 | { "fp1", FP1 }, |
| 3348 | { "fp2", FP2 }, |
| 3349 | { "fp3", FP3 }, |
| 3350 | { "fp4", FP4 }, |
| 3351 | { "fp5", FP5 }, |
| 3352 | { "fp6", FP6 }, |
| 3353 | { "fp7", FP7 }, |
| 3354 | { "fpi", FPI }, |
| 3355 | { "fpiar", FPI }, |
| 3356 | { "fpc", FPI }, |
| 3357 | { "fps", FPS }, |
| 3358 | { "fpsr", FPS }, |
| 3359 | { "fpc", FPC }, |
| 3360 | { "fpcr", FPC }, |
| 3361 | { "control", FPC }, |
| 3362 | { "status", FPS }, |
| 3363 | { "iaddr", FPI }, |
| 3364 | |
| 3365 | { "cop0", COP0 }, |
| 3366 | { "cop1", COP1 }, |
| 3367 | { "cop2", COP2 }, |
| 3368 | { "cop3", COP3 }, |
| 3369 | { "cop4", COP4 }, |
| 3370 | { "cop5", COP5 }, |
| 3371 | { "cop6", COP6 }, |
| 3372 | { "cop7", COP7 }, |
| 3373 | { "pc", PC }, |
| 3374 | { "zpc", ZPC }, |
| 3375 | { "sr", SR }, |
| 3376 | |
| 3377 | { "ccr", CCR }, |
| 3378 | { "cc", CCR }, |
| 3379 | |
| 3380 | { "acc", ACC }, |
| 3381 | { "macsr", MACSR }, |
| 3382 | { "mask", MASK }, |
| 3383 | |
| 3384 | /* control registers */ |
| 3385 | { "sfc", SFC }, /* Source Function Code */ |
| 3386 | { "sfcr", SFC }, |
| 3387 | { "dfc", DFC }, /* Destination Function Code */ |
| 3388 | { "dfcr", DFC }, |
| 3389 | { "cacr", CACR }, /* Cache Control Register */ |
| 3390 | { "caar", CAAR }, /* Cache Address Register */ |
| 3391 | |
| 3392 | { "usp", USP }, /* User Stack Pointer */ |
| 3393 | { "vbr", VBR }, /* Vector Base Register */ |
| 3394 | { "msp", MSP }, /* Master Stack Pointer */ |
| 3395 | { "isp", ISP }, /* Interrupt Stack Pointer */ |
| 3396 | |
| 3397 | { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */ |
| 3398 | { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */ |
| 3399 | { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */ |
| 3400 | { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */ |
| 3401 | |
| 3402 | /* 68ec040 versions of same */ |
| 3403 | { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */ |
| 3404 | { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */ |
| 3405 | { "dacr0", DTT0 }, /* Data Access Control Register 0 */ |
| 3406 | { "dacr1", DTT1 }, /* Data Access Control Register 0 */ |
| 3407 | |
| 3408 | /* mcf5200 versions of same. The ColdFire programmer's reference |
| 3409 | manual indicated that the order is 2,3,0,1, but Ken Rose |
| 3410 | <rose@netcom.com> says that 0,1,2,3 is the correct order. */ |
| 3411 | { "acr0", ITT0 }, /* Access Control Unit 0 */ |
| 3412 | { "acr1", ITT1 }, /* Access Control Unit 1 */ |
| 3413 | { "acr2", DTT0 }, /* Access Control Unit 2 */ |
| 3414 | { "acr3", DTT1 }, /* Access Control Unit 3 */ |
| 3415 | |
| 3416 | { "tc", TC }, /* MMU Translation Control Register */ |
| 3417 | { "tcr", TC }, |
| 3418 | |
| 3419 | { "mmusr", MMUSR }, /* MMU Status Register */ |
| 3420 | { "srp", SRP }, /* User Root Pointer */ |
| 3421 | { "urp", URP }, /* Supervisor Root Pointer */ |
| 3422 | |
| 3423 | { "buscr", BUSCR }, |
| 3424 | { "pcr", PCR }, |
| 3425 | |
| 3426 | { "rombar", ROMBAR }, /* ROM Base Address Register */ |
| 3427 | { "rambar0", RAMBAR0 }, /* ROM Base Address Register */ |
| 3428 | { "rambar1", RAMBAR1 }, /* ROM Base Address Register */ |
| 3429 | { "mbar", MBAR }, /* Module Base Address Register */ |
| 3430 | /* end of control registers */ |
| 3431 | |
| 3432 | { "ac", AC }, |
| 3433 | { "bc", BC }, |
| 3434 | { "cal", CAL }, |
| 3435 | { "crp", CRP }, |
| 3436 | { "drp", DRP }, |
| 3437 | { "pcsr", PCSR }, |
| 3438 | { "psr", PSR }, |
| 3439 | { "scc", SCC }, |
| 3440 | { "val", VAL }, |
| 3441 | { "bad0", BAD0 }, |
| 3442 | { "bad1", BAD1 }, |
| 3443 | { "bad2", BAD2 }, |
| 3444 | { "bad3", BAD3 }, |
| 3445 | { "bad4", BAD4 }, |
| 3446 | { "bad5", BAD5 }, |
| 3447 | { "bad6", BAD6 }, |
| 3448 | { "bad7", BAD7 }, |
| 3449 | { "bac0", BAC0 }, |
| 3450 | { "bac1", BAC1 }, |
| 3451 | { "bac2", BAC2 }, |
| 3452 | { "bac3", BAC3 }, |
| 3453 | { "bac4", BAC4 }, |
| 3454 | { "bac5", BAC5 }, |
| 3455 | { "bac6", BAC6 }, |
| 3456 | { "bac7", BAC7 }, |
| 3457 | |
| 3458 | { "ic", IC }, |
| 3459 | { "dc", DC }, |
| 3460 | { "nc", NC }, |
| 3461 | |
| 3462 | { "tt0", TT0 }, |
| 3463 | { "tt1", TT1 }, |
| 3464 | /* 68ec030 versions of same */ |
| 3465 | { "ac0", TT0 }, |
| 3466 | { "ac1", TT1 }, |
| 3467 | /* 68ec030 access control unit, identical to 030 MMU status reg */ |
| 3468 | { "acusr", PSR }, |
| 3469 | |
| 3470 | /* Suppressed data and address registers. */ |
| 3471 | { "zd0", ZDATA0 }, |
| 3472 | { "zd1", ZDATA1 }, |
| 3473 | { "zd2", ZDATA2 }, |
| 3474 | { "zd3", ZDATA3 }, |
| 3475 | { "zd4", ZDATA4 }, |
| 3476 | { "zd5", ZDATA5 }, |
| 3477 | { "zd6", ZDATA6 }, |
| 3478 | { "zd7", ZDATA7 }, |
| 3479 | { "za0", ZADDR0 }, |
| 3480 | { "za1", ZADDR1 }, |
| 3481 | { "za2", ZADDR2 }, |
| 3482 | { "za3", ZADDR3 }, |
| 3483 | { "za4", ZADDR4 }, |
| 3484 | { "za5", ZADDR5 }, |
| 3485 | { "za6", ZADDR6 }, |
| 3486 | { "za7", ZADDR7 }, |
| 3487 | |
| 3488 | /* Upper and lower data and address registers, used by macw and msacw. */ |
| 3489 | { "d0l", DATA0L }, |
| 3490 | { "d1l", DATA1L }, |
| 3491 | { "d2l", DATA2L }, |
| 3492 | { "d3l", DATA3L }, |
| 3493 | { "d4l", DATA4L }, |
| 3494 | { "d5l", DATA5L }, |
| 3495 | { "d6l", DATA6L }, |
| 3496 | { "d7l", DATA7L }, |
| 3497 | |
| 3498 | { "a0l", ADDR0L }, |
| 3499 | { "a1l", ADDR1L }, |
| 3500 | { "a2l", ADDR2L }, |
| 3501 | { "a3l", ADDR3L }, |
| 3502 | { "a4l", ADDR4L }, |
| 3503 | { "a5l", ADDR5L }, |
| 3504 | { "a6l", ADDR6L }, |
| 3505 | { "a7l", ADDR7L }, |
| 3506 | |
| 3507 | { "d0u", DATA0U }, |
| 3508 | { "d1u", DATA1U }, |
| 3509 | { "d2u", DATA2U }, |
| 3510 | { "d3u", DATA3U }, |
| 3511 | { "d4u", DATA4U }, |
| 3512 | { "d5u", DATA5U }, |
| 3513 | { "d6u", DATA6U }, |
| 3514 | { "d7u", DATA7U }, |
| 3515 | |
| 3516 | { "a0u", ADDR0U }, |
| 3517 | { "a1u", ADDR1U }, |
| 3518 | { "a2u", ADDR2U }, |
| 3519 | { "a3u", ADDR3U }, |
| 3520 | { "a4u", ADDR4U }, |
| 3521 | { "a5u", ADDR5U }, |
| 3522 | { "a6u", ADDR6U }, |
| 3523 | { "a7u", ADDR7U }, |
| 3524 | |
| 3525 | { 0, 0 } |
| 3526 | }; |
| 3527 | |
| 3528 | static void |
| 3529 | init_regtable () |
| 3530 | { |
| 3531 | int i; |
| 3532 | for (i = 0; init_table[i].name; i++) |
| 3533 | insert_reg (init_table[i].name, init_table[i].number); |
| 3534 | } |
| 3535 | |
| 3536 | static int no_68851, no_68881; |
| 3537 | |
| 3538 | #ifdef OBJ_AOUT |
| 3539 | /* a.out machine type. Default to 68020. */ |
| 3540 | int m68k_aout_machtype = 2; |
| 3541 | #endif |
| 3542 | |
| 3543 | void |
| 3544 | md_assemble (str) |
| 3545 | char *str; |
| 3546 | { |
| 3547 | const char *er; |
| 3548 | short *fromP; |
| 3549 | char *toP = NULL; |
| 3550 | int m, n = 0; |
| 3551 | char *to_beg_P; |
| 3552 | int shorts_this_frag; |
| 3553 | fixS *fixP; |
| 3554 | |
| 3555 | /* In MRI mode, the instruction and operands are separated by a |
| 3556 | space. Anything following the operands is a comment. The label |
| 3557 | has already been removed. */ |
| 3558 | if (flag_mri) |
| 3559 | { |
| 3560 | char *s; |
| 3561 | int fields = 0; |
| 3562 | int infield = 0; |
| 3563 | int inquote = 0; |
| 3564 | |
| 3565 | for (s = str; *s != '\0'; s++) |
| 3566 | { |
| 3567 | if ((*s == ' ' || *s == '\t') && ! inquote) |
| 3568 | { |
| 3569 | if (infield) |
| 3570 | { |
| 3571 | ++fields; |
| 3572 | if (fields >= 2) |
| 3573 | { |
| 3574 | *s = '\0'; |
| 3575 | break; |
| 3576 | } |
| 3577 | infield = 0; |
| 3578 | } |
| 3579 | } |
| 3580 | else |
| 3581 | { |
| 3582 | if (! infield) |
| 3583 | infield = 1; |
| 3584 | if (*s == '\'') |
| 3585 | inquote = ! inquote; |
| 3586 | } |
| 3587 | } |
| 3588 | } |
| 3589 | |
| 3590 | memset ((char *) (&the_ins), '\0', sizeof (the_ins)); |
| 3591 | m68k_ip (str); |
| 3592 | er = the_ins.error; |
| 3593 | if (!er) |
| 3594 | { |
| 3595 | for (n = 0; n < the_ins.numargs; n++) |
| 3596 | if (the_ins.operands[n].error) |
| 3597 | { |
| 3598 | er = the_ins.operands[n].error; |
| 3599 | break; |
| 3600 | } |
| 3601 | } |
| 3602 | if (er) |
| 3603 | { |
| 3604 | as_bad (_("%s -- statement `%s' ignored"), er, str); |
| 3605 | return; |
| 3606 | } |
| 3607 | |
| 3608 | /* If there is a current label, record that it marks an instruction. */ |
| 3609 | if (current_label != NULL) |
| 3610 | { |
| 3611 | current_label->text = 1; |
| 3612 | current_label = NULL; |
| 3613 | } |
| 3614 | |
| 3615 | #ifdef OBJ_ELF |
| 3616 | /* Tie dwarf2 debug info to the address at the start of the insn. */ |
| 3617 | dwarf2_emit_insn (0); |
| 3618 | #endif |
| 3619 | |
| 3620 | if (the_ins.nfrag == 0) |
| 3621 | { |
| 3622 | /* No frag hacking involved; just put it out */ |
| 3623 | toP = frag_more (2 * the_ins.numo); |
| 3624 | fromP = &the_ins.opcode[0]; |
| 3625 | for (m = the_ins.numo; m; --m) |
| 3626 | { |
| 3627 | md_number_to_chars (toP, (long) (*fromP), 2); |
| 3628 | toP += 2; |
| 3629 | fromP++; |
| 3630 | } |
| 3631 | /* put out symbol-dependent info */ |
| 3632 | for (m = 0; m < the_ins.nrel; m++) |
| 3633 | { |
| 3634 | switch (the_ins.reloc[m].wid) |
| 3635 | { |
| 3636 | case 'B': |
| 3637 | n = 1; |
| 3638 | break; |
| 3639 | case 'b': |
| 3640 | n = 1; |
| 3641 | break; |
| 3642 | case '3': |
| 3643 | n = 1; |
| 3644 | break; |
| 3645 | case 'w': |
| 3646 | case 'W': |
| 3647 | n = 2; |
| 3648 | break; |
| 3649 | case 'l': |
| 3650 | n = 4; |
| 3651 | break; |
| 3652 | default: |
| 3653 | as_fatal (_("Don't know how to figure width of %c in md_assemble()"), |
| 3654 | the_ins.reloc[m].wid); |
| 3655 | } |
| 3656 | |
| 3657 | fixP = fix_new_exp (frag_now, |
| 3658 | ((toP - frag_now->fr_literal) |
| 3659 | - the_ins.numo * 2 + the_ins.reloc[m].n), |
| 3660 | n, |
| 3661 | &the_ins.reloc[m].exp, |
| 3662 | the_ins.reloc[m].pcrel, |
| 3663 | get_reloc_code (n, the_ins.reloc[m].pcrel, |
| 3664 | the_ins.reloc[m].pic_reloc)); |
| 3665 | fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; |
| 3666 | if (the_ins.reloc[m].wid == 'B') |
| 3667 | fixP->fx_signed = 1; |
| 3668 | } |
| 3669 | return; |
| 3670 | } |
| 3671 | |
| 3672 | /* There's some frag hacking */ |
| 3673 | { |
| 3674 | /* Calculate the max frag size. */ |
| 3675 | int wid; |
| 3676 | |
| 3677 | wid = 2 * the_ins.fragb[0].fragoff; |
| 3678 | for (n = 1; n < the_ins.nfrag; n++) |
| 3679 | wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff); |
| 3680 | /* frag_var part. */ |
| 3681 | wid += 10; |
| 3682 | /* Make sure the whole insn fits in one chunk, in particular that |
| 3683 | the var part is attached, as we access one byte before the |
| 3684 | variable frag for byte branches. */ |
| 3685 | frag_grow (wid); |
| 3686 | } |
| 3687 | |
| 3688 | for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++) |
| 3689 | { |
| 3690 | int wid; |
| 3691 | |
| 3692 | if (n == 0) |
| 3693 | wid = 2 * the_ins.fragb[n].fragoff; |
| 3694 | else |
| 3695 | wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff); |
| 3696 | toP = frag_more (wid); |
| 3697 | to_beg_P = toP; |
| 3698 | shorts_this_frag = 0; |
| 3699 | for (m = wid / 2; m; --m) |
| 3700 | { |
| 3701 | md_number_to_chars (toP, (long) (*fromP), 2); |
| 3702 | toP += 2; |
| 3703 | fromP++; |
| 3704 | shorts_this_frag++; |
| 3705 | } |
| 3706 | for (m = 0; m < the_ins.nrel; m++) |
| 3707 | { |
| 3708 | if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag) |
| 3709 | { |
| 3710 | the_ins.reloc[m].n -= 2 * shorts_this_frag; |
| 3711 | break; |
| 3712 | } |
| 3713 | wid = the_ins.reloc[m].wid; |
| 3714 | if (wid == 0) |
| 3715 | continue; |
| 3716 | the_ins.reloc[m].wid = 0; |
| 3717 | wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000; |
| 3718 | |
| 3719 | fixP = fix_new_exp (frag_now, |
| 3720 | ((toP - frag_now->fr_literal) |
| 3721 | - the_ins.numo * 2 + the_ins.reloc[m].n), |
| 3722 | wid, |
| 3723 | &the_ins.reloc[m].exp, |
| 3724 | the_ins.reloc[m].pcrel, |
| 3725 | get_reloc_code (wid, the_ins.reloc[m].pcrel, |
| 3726 | the_ins.reloc[m].pic_reloc)); |
| 3727 | fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; |
| 3728 | } |
| 3729 | (void) frag_var (rs_machine_dependent, 10, 0, |
| 3730 | (relax_substateT) (the_ins.fragb[n].fragty), |
| 3731 | the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P); |
| 3732 | } |
| 3733 | n = (the_ins.numo - the_ins.fragb[n - 1].fragoff); |
| 3734 | shorts_this_frag = 0; |
| 3735 | if (n) |
| 3736 | { |
| 3737 | toP = frag_more (n * sizeof (short)); |
| 3738 | while (n--) |
| 3739 | { |
| 3740 | md_number_to_chars (toP, (long) (*fromP), 2); |
| 3741 | toP += 2; |
| 3742 | fromP++; |
| 3743 | shorts_this_frag++; |
| 3744 | } |
| 3745 | } |
| 3746 | for (m = 0; m < the_ins.nrel; m++) |
| 3747 | { |
| 3748 | int wid; |
| 3749 | |
| 3750 | wid = the_ins.reloc[m].wid; |
| 3751 | if (wid == 0) |
| 3752 | continue; |
| 3753 | the_ins.reloc[m].wid = 0; |
| 3754 | wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000; |
| 3755 | |
| 3756 | fixP = fix_new_exp (frag_now, |
| 3757 | ((the_ins.reloc[m].n + toP - frag_now->fr_literal) |
| 3758 | - shorts_this_frag * 2), |
| 3759 | wid, |
| 3760 | &the_ins.reloc[m].exp, |
| 3761 | the_ins.reloc[m].pcrel, |
| 3762 | get_reloc_code (wid, the_ins.reloc[m].pcrel, |
| 3763 | the_ins.reloc[m].pic_reloc)); |
| 3764 | fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; |
| 3765 | } |
| 3766 | } |
| 3767 | |
| 3768 | void |
| 3769 | md_begin () |
| 3770 | { |
| 3771 | /* |
| 3772 | * md_begin -- set up hash tables with 68000 instructions. |
| 3773 | * similar to what the vax assembler does. ---phr |
| 3774 | */ |
| 3775 | /* RMS claims the thing to do is take the m68k-opcode.h table, and make |
| 3776 | a copy of it at runtime, adding in the information we want but isn't |
| 3777 | there. I think it'd be better to have an awk script hack the table |
| 3778 | at compile time. Or even just xstr the table and use it as-is. But |
| 3779 | my lord ghod hath spoken, so we do it this way. Excuse the ugly var |
| 3780 | names. */ |
| 3781 | |
| 3782 | const struct m68k_opcode *ins; |
| 3783 | struct m68k_incant *hack, *slak; |
| 3784 | const char *retval = 0; /* empty string, or error msg text */ |
| 3785 | int i; |
| 3786 | |
| 3787 | if (flag_mri) |
| 3788 | { |
| 3789 | flag_reg_prefix_optional = 1; |
| 3790 | m68k_abspcadd = 1; |
| 3791 | if (! m68k_rel32_from_cmdline) |
| 3792 | m68k_rel32 = 0; |
| 3793 | } |
| 3794 | |
| 3795 | op_hash = hash_new (); |
| 3796 | |
| 3797 | obstack_begin (&robyn, 4000); |
| 3798 | for (i = 0; i < m68k_numopcodes; i++) |
| 3799 | { |
| 3800 | hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant)); |
| 3801 | do |
| 3802 | { |
| 3803 | ins = &m68k_opcodes[i]; |
| 3804 | /* We *could* ignore insns that don't match our arch here |
| 3805 | but just leaving them out of the hash. */ |
| 3806 | slak->m_operands = ins->args; |
| 3807 | slak->m_opnum = strlen (slak->m_operands) / 2; |
| 3808 | slak->m_arch = ins->arch; |
| 3809 | slak->m_opcode = ins->opcode; |
| 3810 | /* This is kludgey */ |
| 3811 | slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1; |
| 3812 | if (i + 1 != m68k_numopcodes |
| 3813 | && !strcmp (ins->name, m68k_opcodes[i + 1].name)) |
| 3814 | { |
| 3815 | slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant)); |
| 3816 | i++; |
| 3817 | } |
| 3818 | else |
| 3819 | slak->m_next = 0; |
| 3820 | slak = slak->m_next; |
| 3821 | } |
| 3822 | while (slak); |
| 3823 | |
| 3824 | retval = hash_insert (op_hash, ins->name, (char *) hack); |
| 3825 | if (retval) |
| 3826 | as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval); |
| 3827 | } |
| 3828 | |
| 3829 | for (i = 0; i < m68k_numaliases; i++) |
| 3830 | { |
| 3831 | const char *name = m68k_opcode_aliases[i].primary; |
| 3832 | const char *alias = m68k_opcode_aliases[i].alias; |
| 3833 | PTR val = hash_find (op_hash, name); |
| 3834 | if (!val) |
| 3835 | as_fatal (_("Internal Error: Can't find %s in hash table"), name); |
| 3836 | retval = hash_insert (op_hash, alias, val); |
| 3837 | if (retval) |
| 3838 | as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval); |
| 3839 | } |
| 3840 | |
| 3841 | /* In MRI mode, all unsized branches are variable sized. Normally, |
| 3842 | they are word sized. */ |
| 3843 | if (flag_mri) |
| 3844 | { |
| 3845 | static struct m68k_opcode_alias mri_aliases[] = |
| 3846 | { |
| 3847 | { "bhi", "jhi", }, |
| 3848 | { "bls", "jls", }, |
| 3849 | { "bcc", "jcc", }, |
| 3850 | { "bcs", "jcs", }, |
| 3851 | { "bne", "jne", }, |
| 3852 | { "beq", "jeq", }, |
| 3853 | { "bvc", "jvc", }, |
| 3854 | { "bvs", "jvs", }, |
| 3855 | { "bpl", "jpl", }, |
| 3856 | { "bmi", "jmi", }, |
| 3857 | { "bge", "jge", }, |
| 3858 | { "blt", "jlt", }, |
| 3859 | { "bgt", "jgt", }, |
| 3860 | { "ble", "jle", }, |
| 3861 | { "bra", "jra", }, |
| 3862 | { "bsr", "jbsr", }, |
| 3863 | }; |
| 3864 | |
| 3865 | for (i = 0; |
| 3866 | i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]); |
| 3867 | i++) |
| 3868 | { |
| 3869 | const char *name = mri_aliases[i].primary; |
| 3870 | const char *alias = mri_aliases[i].alias; |
| 3871 | PTR val = hash_find (op_hash, name); |
| 3872 | if (!val) |
| 3873 | as_fatal (_("Internal Error: Can't find %s in hash table"), name); |
| 3874 | retval = hash_jam (op_hash, alias, val); |
| 3875 | if (retval) |
| 3876 | as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval); |
| 3877 | } |
| 3878 | } |
| 3879 | |
| 3880 | for (i = 0; i < (int) sizeof (notend_table); i++) |
| 3881 | { |
| 3882 | notend_table[i] = 0; |
| 3883 | alt_notend_table[i] = 0; |
| 3884 | } |
| 3885 | notend_table[','] = 1; |
| 3886 | notend_table['{'] = 1; |
| 3887 | notend_table['}'] = 1; |
| 3888 | alt_notend_table['a'] = 1; |
| 3889 | alt_notend_table['A'] = 1; |
| 3890 | alt_notend_table['d'] = 1; |
| 3891 | alt_notend_table['D'] = 1; |
| 3892 | alt_notend_table['#'] = 1; |
| 3893 | alt_notend_table['&'] = 1; |
| 3894 | alt_notend_table['f'] = 1; |
| 3895 | alt_notend_table['F'] = 1; |
| 3896 | #ifdef REGISTER_PREFIX |
| 3897 | alt_notend_table[REGISTER_PREFIX] = 1; |
| 3898 | #endif |
| 3899 | |
| 3900 | /* We need to put '(' in alt_notend_table to handle |
| 3901 | cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) |
| 3902 | */ |
| 3903 | alt_notend_table['('] = 1; |
| 3904 | |
| 3905 | /* We need to put '@' in alt_notend_table to handle |
| 3906 | cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) |
| 3907 | */ |
| 3908 | alt_notend_table['@'] = 1; |
| 3909 | |
| 3910 | /* We need to put digits in alt_notend_table to handle |
| 3911 | bfextu %d0{24:1},%d0 |
| 3912 | */ |
| 3913 | alt_notend_table['0'] = 1; |
| 3914 | alt_notend_table['1'] = 1; |
| 3915 | alt_notend_table['2'] = 1; |
| 3916 | alt_notend_table['3'] = 1; |
| 3917 | alt_notend_table['4'] = 1; |
| 3918 | alt_notend_table['5'] = 1; |
| 3919 | alt_notend_table['6'] = 1; |
| 3920 | alt_notend_table['7'] = 1; |
| 3921 | alt_notend_table['8'] = 1; |
| 3922 | alt_notend_table['9'] = 1; |
| 3923 | |
| 3924 | #ifndef MIT_SYNTAX_ONLY |
| 3925 | /* Insert pseudo ops, these have to go into the opcode table since |
| 3926 | gas expects pseudo ops to start with a dot */ |
| 3927 | { |
| 3928 | int n = 0; |
| 3929 | while (mote_pseudo_table[n].poc_name) |
| 3930 | { |
| 3931 | hack = (struct m68k_incant *) |
| 3932 | obstack_alloc (&robyn, sizeof (struct m68k_incant)); |
| 3933 | hash_insert (op_hash, |
| 3934 | mote_pseudo_table[n].poc_name, (char *) hack); |
| 3935 | hack->m_operands = 0; |
| 3936 | hack->m_opnum = n; |
| 3937 | n++; |
| 3938 | } |
| 3939 | } |
| 3940 | #endif |
| 3941 | |
| 3942 | init_regtable (); |
| 3943 | |
| 3944 | #ifdef OBJ_ELF |
| 3945 | record_alignment (text_section, 2); |
| 3946 | record_alignment (data_section, 2); |
| 3947 | record_alignment (bss_section, 2); |
| 3948 | #endif |
| 3949 | } |
| 3950 | |
| 3951 | static void |
| 3952 | select_control_regs () |
| 3953 | { |
| 3954 | /* Note which set of "movec" control registers is available. */ |
| 3955 | switch (cpu_of_arch (current_architecture)) |
| 3956 | { |
| 3957 | case m68000: |
| 3958 | control_regs = m68000_control_regs; |
| 3959 | break; |
| 3960 | case m68010: |
| 3961 | control_regs = m68010_control_regs; |
| 3962 | break; |
| 3963 | case m68020: |
| 3964 | case m68030: |
| 3965 | control_regs = m68020_control_regs; |
| 3966 | break; |
| 3967 | case m68040: |
| 3968 | control_regs = m68040_control_regs; |
| 3969 | break; |
| 3970 | case m68060: |
| 3971 | control_regs = m68060_control_regs; |
| 3972 | break; |
| 3973 | case cpu32: |
| 3974 | control_regs = cpu32_control_regs; |
| 3975 | break; |
| 3976 | case mcf5200: |
| 3977 | case mcf5206e: |
| 3978 | case mcf5307: |
| 3979 | case mcf5407: |
| 3980 | control_regs = mcf_control_regs; |
| 3981 | break; |
| 3982 | default: |
| 3983 | abort (); |
| 3984 | } |
| 3985 | } |
| 3986 | |
| 3987 | void |
| 3988 | m68k_init_after_args () |
| 3989 | { |
| 3990 | if (cpu_of_arch (current_architecture) == 0) |
| 3991 | { |
| 3992 | int i; |
| 3993 | const char *default_cpu = TARGET_CPU; |
| 3994 | |
| 3995 | if (*default_cpu == 'm') |
| 3996 | default_cpu++; |
| 3997 | for (i = 0; i < n_archs; i++) |
| 3998 | if (strcasecmp (default_cpu, archs[i].name) == 0) |
| 3999 | break; |
| 4000 | if (i == n_archs) |
| 4001 | { |
| 4002 | as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU); |
| 4003 | current_architecture |= m68020; |
| 4004 | } |
| 4005 | else |
| 4006 | current_architecture |= archs[i].arch; |
| 4007 | } |
| 4008 | /* Permit m68881 specification with all cpus; those that can't work |
| 4009 | with a coprocessor could be doing emulation. */ |
| 4010 | if (current_architecture & m68851) |
| 4011 | { |
| 4012 | if (current_architecture & m68040) |
| 4013 | { |
| 4014 | as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly")); |
| 4015 | } |
| 4016 | } |
| 4017 | /* What other incompatibilities could we check for? */ |
| 4018 | |
| 4019 | /* Toss in some default assumptions about coprocessors. */ |
| 4020 | if (!no_68881 |
| 4021 | && (cpu_of_arch (current_architecture) |
| 4022 | /* Can CPU32 have a 68881 coprocessor?? */ |
| 4023 | & (m68020 | m68030 | cpu32))) |
| 4024 | { |
| 4025 | current_architecture |= m68881; |
| 4026 | } |
| 4027 | if (!no_68851 |
| 4028 | && (cpu_of_arch (current_architecture) & m68020up) != 0 |
| 4029 | && (cpu_of_arch (current_architecture) & m68040up) == 0) |
| 4030 | { |
| 4031 | current_architecture |= m68851; |
| 4032 | } |
| 4033 | if (no_68881 && (current_architecture & m68881)) |
| 4034 | as_bad (_("options for 68881 and no-68881 both given")); |
| 4035 | if (no_68851 && (current_architecture & m68851)) |
| 4036 | as_bad (_("options for 68851 and no-68851 both given")); |
| 4037 | |
| 4038 | #ifdef OBJ_AOUT |
| 4039 | /* Work out the magic number. This isn't very general. */ |
| 4040 | if (current_architecture & m68000) |
| 4041 | m68k_aout_machtype = 0; |
| 4042 | else if (current_architecture & m68010) |
| 4043 | m68k_aout_machtype = 1; |
| 4044 | else if (current_architecture & m68020) |
| 4045 | m68k_aout_machtype = 2; |
| 4046 | else |
| 4047 | m68k_aout_machtype = 2; |
| 4048 | #endif |
| 4049 | |
| 4050 | /* Note which set of "movec" control registers is available. */ |
| 4051 | select_control_regs (); |
| 4052 | |
| 4053 | if (cpu_of_arch (current_architecture) < m68020 |
| 4054 | || arch_coldfire_p (current_architecture)) |
| 4055 | md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0; |
| 4056 | } |
| 4057 | \f |
| 4058 | /* This is called when a label is defined. */ |
| 4059 | |
| 4060 | void |
| 4061 | m68k_frob_label (sym) |
| 4062 | symbolS *sym; |
| 4063 | { |
| 4064 | struct label_line *n; |
| 4065 | |
| 4066 | n = (struct label_line *) xmalloc (sizeof *n); |
| 4067 | n->next = labels; |
| 4068 | n->label = sym; |
| 4069 | as_where (&n->file, &n->line); |
| 4070 | n->text = 0; |
| 4071 | labels = n; |
| 4072 | current_label = n; |
| 4073 | } |
| 4074 | |
| 4075 | /* This is called when a value that is not an instruction is emitted. */ |
| 4076 | |
| 4077 | void |
| 4078 | m68k_flush_pending_output () |
| 4079 | { |
| 4080 | current_label = NULL; |
| 4081 | } |
| 4082 | |
| 4083 | /* This is called at the end of the assembly, when the final value of |
| 4084 | the label is known. We warn if this is a text symbol aligned at an |
| 4085 | odd location. */ |
| 4086 | |
| 4087 | void |
| 4088 | m68k_frob_symbol (sym) |
| 4089 | symbolS *sym; |
| 4090 | { |
| 4091 | if (S_GET_SEGMENT (sym) == reg_section |
| 4092 | && (int) S_GET_VALUE (sym) < 0) |
| 4093 | { |
| 4094 | S_SET_SEGMENT (sym, absolute_section); |
| 4095 | S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym)); |
| 4096 | } |
| 4097 | else if ((S_GET_VALUE (sym) & 1) != 0) |
| 4098 | { |
| 4099 | struct label_line *l; |
| 4100 | |
| 4101 | for (l = labels; l != NULL; l = l->next) |
| 4102 | { |
| 4103 | if (l->label == sym) |
| 4104 | { |
| 4105 | if (l->text) |
| 4106 | as_warn_where (l->file, l->line, |
| 4107 | _("text label `%s' aligned to odd boundary"), |
| 4108 | S_GET_NAME (sym)); |
| 4109 | break; |
| 4110 | } |
| 4111 | } |
| 4112 | } |
| 4113 | } |
| 4114 | \f |
| 4115 | /* This is called if we go in or out of MRI mode because of the .mri |
| 4116 | pseudo-op. */ |
| 4117 | |
| 4118 | void |
| 4119 | m68k_mri_mode_change (on) |
| 4120 | int on; |
| 4121 | { |
| 4122 | if (on) |
| 4123 | { |
| 4124 | if (! flag_reg_prefix_optional) |
| 4125 | { |
| 4126 | flag_reg_prefix_optional = 1; |
| 4127 | #ifdef REGISTER_PREFIX |
| 4128 | init_regtable (); |
| 4129 | #endif |
| 4130 | } |
| 4131 | m68k_abspcadd = 1; |
| 4132 | if (! m68k_rel32_from_cmdline) |
| 4133 | m68k_rel32 = 0; |
| 4134 | } |
| 4135 | else |
| 4136 | { |
| 4137 | if (! reg_prefix_optional_seen) |
| 4138 | { |
| 4139 | #ifdef REGISTER_PREFIX_OPTIONAL |
| 4140 | flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL; |
| 4141 | #else |
| 4142 | flag_reg_prefix_optional = 0; |
| 4143 | #endif |
| 4144 | #ifdef REGISTER_PREFIX |
| 4145 | init_regtable (); |
| 4146 | #endif |
| 4147 | } |
| 4148 | m68k_abspcadd = 0; |
| 4149 | if (! m68k_rel32_from_cmdline) |
| 4150 | m68k_rel32 = 1; |
| 4151 | } |
| 4152 | } |
| 4153 | |
| 4154 | /* Equal to MAX_PRECISION in atof-ieee.c */ |
| 4155 | #define MAX_LITTLENUMS 6 |
| 4156 | |
| 4157 | /* Turn a string in input_line_pointer into a floating point constant |
| 4158 | of type TYPE, and store the appropriate bytes in *LITP. The number |
| 4159 | of LITTLENUMS emitted is stored in *SIZEP. An error message is |
| 4160 | returned, or NULL on OK. */ |
| 4161 | |
| 4162 | char * |
| 4163 | md_atof (type, litP, sizeP) |
| 4164 | char type; |
| 4165 | char *litP; |
| 4166 | int *sizeP; |
| 4167 | { |
| 4168 | int prec; |
| 4169 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
| 4170 | LITTLENUM_TYPE *wordP; |
| 4171 | char *t; |
| 4172 | |
| 4173 | switch (type) |
| 4174 | { |
| 4175 | case 'f': |
| 4176 | case 'F': |
| 4177 | case 's': |
| 4178 | case 'S': |
| 4179 | prec = 2; |
| 4180 | break; |
| 4181 | |
| 4182 | case 'd': |
| 4183 | case 'D': |
| 4184 | case 'r': |
| 4185 | case 'R': |
| 4186 | prec = 4; |
| 4187 | break; |
| 4188 | |
| 4189 | case 'x': |
| 4190 | case 'X': |
| 4191 | prec = 6; |
| 4192 | break; |
| 4193 | |
| 4194 | case 'p': |
| 4195 | case 'P': |
| 4196 | prec = 6; |
| 4197 | break; |
| 4198 | |
| 4199 | default: |
| 4200 | *sizeP = 0; |
| 4201 | return _("Bad call to MD_ATOF()"); |
| 4202 | } |
| 4203 | t = atof_ieee (input_line_pointer, type, words); |
| 4204 | if (t) |
| 4205 | input_line_pointer = t; |
| 4206 | |
| 4207 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
| 4208 | for (wordP = words; prec--;) |
| 4209 | { |
| 4210 | md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE)); |
| 4211 | litP += sizeof (LITTLENUM_TYPE); |
| 4212 | } |
| 4213 | return 0; |
| 4214 | } |
| 4215 | |
| 4216 | void |
| 4217 | md_number_to_chars (buf, val, n) |
| 4218 | char *buf; |
| 4219 | valueT val; |
| 4220 | int n; |
| 4221 | { |
| 4222 | number_to_chars_bigendian (buf, val, n); |
| 4223 | } |
| 4224 | |
| 4225 | void |
| 4226 | md_apply_fix3 (fixP, valP, seg) |
| 4227 | fixS *fixP; |
| 4228 | valueT *valP; |
| 4229 | segT seg ATTRIBUTE_UNUSED; |
| 4230 | { |
| 4231 | offsetT val = *valP; |
| 4232 | addressT upper_limit; |
| 4233 | offsetT lower_limit; |
| 4234 | |
| 4235 | /* This is unnecessary but it convinces the native rs6000 compiler |
| 4236 | to generate the code we want. */ |
| 4237 | char *buf = fixP->fx_frag->fr_literal; |
| 4238 | buf += fixP->fx_where; |
| 4239 | /* end ibm compiler workaround */ |
| 4240 | |
| 4241 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; |
| 4242 | |
| 4243 | if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) |
| 4244 | fixP->fx_done = 1; |
| 4245 | |
| 4246 | #ifdef OBJ_ELF |
| 4247 | if (fixP->fx_addsy) |
| 4248 | { |
| 4249 | memset (buf, 0, fixP->fx_size); |
| 4250 | fixP->fx_addnumber = val; /* Remember value for emit_reloc */ |
| 4251 | |
| 4252 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
| 4253 | && !S_IS_DEFINED (fixP->fx_addsy) |
| 4254 | && !S_IS_WEAK (fixP->fx_addsy)) |
| 4255 | S_SET_WEAK (fixP->fx_addsy); |
| 4256 | return; |
| 4257 | } |
| 4258 | #endif |
| 4259 | |
| 4260 | #ifdef BFD_ASSEMBLER |
| 4261 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
| 4262 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
| 4263 | return; |
| 4264 | #endif |
| 4265 | |
| 4266 | switch (fixP->fx_size) |
| 4267 | { |
| 4268 | /* The cast to offsetT below are necessary to make code |
| 4269 | correct for machines where ints are smaller than offsetT. */ |
| 4270 | case 1: |
| 4271 | *buf++ = val; |
| 4272 | upper_limit = 0x7f; |
| 4273 | lower_limit = - (offsetT) 0x80; |
| 4274 | break; |
| 4275 | case 2: |
| 4276 | *buf++ = (val >> 8); |
| 4277 | *buf++ = val; |
| 4278 | upper_limit = 0x7fff; |
| 4279 | lower_limit = - (offsetT) 0x8000; |
| 4280 | break; |
| 4281 | case 4: |
| 4282 | *buf++ = (val >> 24); |
| 4283 | *buf++ = (val >> 16); |
| 4284 | *buf++ = (val >> 8); |
| 4285 | *buf++ = val; |
| 4286 | upper_limit = 0x7fffffff; |
| 4287 | lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */ |
| 4288 | break; |
| 4289 | default: |
| 4290 | BAD_CASE (fixP->fx_size); |
| 4291 | } |
| 4292 | |
| 4293 | /* Fix up a negative reloc. */ |
| 4294 | if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL) |
| 4295 | { |
| 4296 | fixP->fx_addsy = fixP->fx_subsy; |
| 4297 | fixP->fx_subsy = NULL; |
| 4298 | fixP->fx_tcbit = 1; |
| 4299 | } |
| 4300 | |
| 4301 | /* For non-pc-relative values, it's conceivable we might get something |
| 4302 | like "0xff" for a byte field. So extend the upper part of the range |
| 4303 | to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff", |
| 4304 | so that we can do any range checking at all. */ |
| 4305 | if (! fixP->fx_pcrel && ! fixP->fx_signed) |
| 4306 | upper_limit = upper_limit * 2 + 1; |
| 4307 | |
| 4308 | if ((addressT) val > upper_limit |
| 4309 | && (val > 0 || val < lower_limit)) |
| 4310 | as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range")); |
| 4311 | |
| 4312 | /* A one byte PC-relative reloc means a short branch. We can't use |
| 4313 | a short branch with a value of 0 or -1, because those indicate |
| 4314 | different opcodes (branches with longer offsets). fixup_segment |
| 4315 | in write.c may have clobbered fx_pcrel, so we need to examine the |
| 4316 | reloc type. */ |
| 4317 | if ((fixP->fx_pcrel |
| 4318 | #ifdef BFD_ASSEMBLER |
| 4319 | || fixP->fx_r_type == BFD_RELOC_8_PCREL |
| 4320 | #endif |
| 4321 | ) |
| 4322 | && fixP->fx_size == 1 |
| 4323 | && (fixP->fx_addsy == NULL |
| 4324 | || S_IS_DEFINED (fixP->fx_addsy)) |
| 4325 | && (val == 0 || val == -1)) |
| 4326 | as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset")); |
| 4327 | } |
| 4328 | |
| 4329 | /* *fragP has been relaxed to its final size, and now needs to have |
| 4330 | the bytes inside it modified to conform to the new size There is UGLY |
| 4331 | MAGIC here. .. |
| 4332 | */ |
| 4333 | static void |
| 4334 | md_convert_frag_1 (fragP) |
| 4335 | register fragS *fragP; |
| 4336 | { |
| 4337 | long disp; |
| 4338 | fixS *fixP; |
| 4339 | |
| 4340 | /* Address in object code of the displacement. */ |
| 4341 | register int object_address = fragP->fr_fix + fragP->fr_address; |
| 4342 | |
| 4343 | /* Address in gas core of the place to store the displacement. */ |
| 4344 | /* This convinces the native rs6000 compiler to generate the code we |
| 4345 | want. */ |
| 4346 | register char *buffer_address = fragP->fr_literal; |
| 4347 | buffer_address += fragP->fr_fix; |
| 4348 | /* end ibm compiler workaround */ |
| 4349 | |
| 4350 | /* The displacement of the address, from current location. */ |
| 4351 | disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0; |
| 4352 | disp = (disp + fragP->fr_offset) - object_address; |
| 4353 | |
| 4354 | switch (fragP->fr_subtype) |
| 4355 | { |
| 4356 | case TAB (BRANCHBWL, BYTE): |
| 4357 | case TAB (BRABSJUNC, BYTE): |
| 4358 | case TAB (BRABSJCOND, BYTE): |
| 4359 | case TAB (BRANCHBW, BYTE): |
| 4360 | know (issbyte (disp)); |
| 4361 | if (disp == 0) |
| 4362 | as_bad_where (fragP->fr_file, fragP->fr_line, |
| 4363 | _("short branch with zero offset: use :w")); |
| 4364 | fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol, |
| 4365 | fragP->fr_offset, 1, RELAX_RELOC_PC8); |
| 4366 | fixP->fx_pcrel_adjust = -1; |
| 4367 | break; |
| 4368 | case TAB (BRANCHBWL, SHORT): |
| 4369 | case TAB (BRABSJUNC, SHORT): |
| 4370 | case TAB (BRABSJCOND, SHORT): |
| 4371 | case TAB (BRANCHBW, SHORT): |
| 4372 | fragP->fr_opcode[1] = 0x00; |
| 4373 | fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset, |
| 4374 | 1, RELAX_RELOC_PC16); |
| 4375 | fragP->fr_fix += 2; |
| 4376 | break; |
| 4377 | case TAB (BRANCHBWL, LONG): |
| 4378 | fragP->fr_opcode[1] = (char) 0xFF; |
| 4379 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, |
| 4380 | 1, RELAX_RELOC_PC32); |
| 4381 | fragP->fr_fix += 4; |
| 4382 | break; |
| 4383 | case TAB (BRABSJUNC, LONG): |
| 4384 | if (fragP->fr_opcode[0] == 0x61) /* jbsr */ |
| 4385 | { |
| 4386 | fragP->fr_opcode[0] = 0x4E; |
| 4387 | fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand */ |
| 4388 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, |
| 4389 | 0, RELAX_RELOC_ABS32); |
| 4390 | fragP->fr_fix += 4; |
| 4391 | } |
| 4392 | else if (fragP->fr_opcode[0] == 0x60) /* jbra */ |
| 4393 | { |
| 4394 | fragP->fr_opcode[0] = 0x4E; |
| 4395 | fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand */ |
| 4396 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, |
| 4397 | 0, RELAX_RELOC_ABS32); |
| 4398 | fragP->fr_fix += 4; |
| 4399 | } |
| 4400 | else |
| 4401 | { |
| 4402 | /* This cannot happen, because jbsr and jbra are the only two |
| 4403 | unconditional branches. */ |
| 4404 | abort (); |
| 4405 | } |
| 4406 | break; |
| 4407 | case TAB (BRABSJCOND, LONG): |
| 4408 | /* Only Bcc 68000 instructions can come here. */ |
| 4409 | /* Change bcc into b!cc/jmp absl long. */ |
| 4410 | |
| 4411 | fragP->fr_opcode[0] ^= 0x01; /* invert bcc */ |
| 4412 | fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */ |
| 4413 | |
| 4414 | /* JF: these used to be fr_opcode[2,3], but they may be in a |
| 4415 | different frag, in which case refering to them is a no-no. |
| 4416 | Only fr_opcode[0,1] are guaranteed to work. */ |
| 4417 | *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */ |
| 4418 | *buffer_address++ = (char) 0xf9; |
| 4419 | fragP->fr_fix += 2; /* account for jmp instruction */ |
| 4420 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
| 4421 | fragP->fr_offset, 0, RELAX_RELOC_ABS32); |
| 4422 | fragP->fr_fix += 4; |
| 4423 | break; |
| 4424 | case TAB (FBRANCH, SHORT): |
| 4425 | know ((fragP->fr_opcode[1] & 0x40) == 0); |
| 4426 | fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset, |
| 4427 | 1, RELAX_RELOC_PC16); |
| 4428 | fragP->fr_fix += 2; |
| 4429 | break; |
| 4430 | case TAB (FBRANCH, LONG): |
| 4431 | fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */ |
| 4432 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, |
| 4433 | 1, RELAX_RELOC_PC32); |
| 4434 | fragP->fr_fix += 4; |
| 4435 | break; |
| 4436 | case TAB (DBCCLBR, SHORT): |
| 4437 | case TAB (DBCCABSJ, SHORT): |
| 4438 | fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset, |
| 4439 | 1, RELAX_RELOC_PC16); |
| 4440 | fragP->fr_fix += 2; |
| 4441 | break; |
| 4442 | case TAB (DBCCLBR, LONG): |
| 4443 | /* only DBcc instructions can come here */ |
| 4444 | /* Change dbcc into dbcc/bral. */ |
| 4445 | |
| 4446 | /* JF: these used to be fr_opcode[2-7], but that's wrong */ |
| 4447 | *buffer_address++ = 0x00; /* branch offset = 4 */ |
| 4448 | *buffer_address++ = 0x04; |
| 4449 | *buffer_address++ = 0x60; /* put in bra pc+6 */ |
| 4450 | *buffer_address++ = 0x06; |
| 4451 | *buffer_address++ = 0x60; /* Put in bral (0x60ff). */ |
| 4452 | *buffer_address++ = (char) 0xff; |
| 4453 | |
| 4454 | fragP->fr_fix += 6; /* account for bra/jmp instructions */ |
| 4455 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1, |
| 4456 | RELAX_RELOC_PC32); |
| 4457 | fragP->fr_fix += 4; |
| 4458 | break; |
| 4459 | case TAB (DBCCABSJ, LONG): |
| 4460 | /* only DBcc instructions can come here */ |
| 4461 | /* Change dbcc into dbcc/jmp. */ |
| 4462 | |
| 4463 | /* JF: these used to be fr_opcode[2-7], but that's wrong */ |
| 4464 | *buffer_address++ = 0x00; /* branch offset = 4 */ |
| 4465 | *buffer_address++ = 0x04; |
| 4466 | *buffer_address++ = 0x60; /* put in bra pc+6 */ |
| 4467 | *buffer_address++ = 0x06; |
| 4468 | *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */ |
| 4469 | *buffer_address++ = (char) 0xf9; |
| 4470 | |
| 4471 | fragP->fr_fix += 6; /* account for bra/jmp instructions */ |
| 4472 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0, |
| 4473 | RELAX_RELOC_ABS32); |
| 4474 | fragP->fr_fix += 4; |
| 4475 | break; |
| 4476 | case TAB (PCREL1632, SHORT): |
| 4477 | fragP->fr_opcode[1] &= ~0x3F; |
| 4478 | fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */ |
| 4479 | fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol, |
| 4480 | fragP->fr_offset, 1, RELAX_RELOC_PC16); |
| 4481 | fragP->fr_fix += 2; |
| 4482 | break; |
| 4483 | case TAB (PCREL1632, LONG): |
| 4484 | /* Already set to mode 7.3; this indicates: PC indirect with |
| 4485 | suppressed index, 32-bit displacement. */ |
| 4486 | *buffer_address++ = 0x01; |
| 4487 | *buffer_address++ = 0x70; |
| 4488 | fragP->fr_fix += 2; |
| 4489 | fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol, |
| 4490 | fragP->fr_offset, 1, RELAX_RELOC_PC32); |
| 4491 | fixP->fx_pcrel_adjust = 2; |
| 4492 | fragP->fr_fix += 4; |
| 4493 | break; |
| 4494 | case TAB (PCINDEX, BYTE): |
| 4495 | assert (fragP->fr_fix >= 2); |
| 4496 | buffer_address[-2] &= ~1; |
| 4497 | fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol, |
| 4498 | fragP->fr_offset, 1, RELAX_RELOC_PC8); |
| 4499 | fixP->fx_pcrel_adjust = 1; |
| 4500 | break; |
| 4501 | case TAB (PCINDEX, SHORT): |
| 4502 | assert (fragP->fr_fix >= 2); |
| 4503 | buffer_address[-2] |= 0x1; |
| 4504 | buffer_address[-1] = 0x20; |
| 4505 | fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol, |
| 4506 | fragP->fr_offset, 1, RELAX_RELOC_PC16); |
| 4507 | fixP->fx_pcrel_adjust = 2; |
| 4508 | fragP->fr_fix += 2; |
| 4509 | break; |
| 4510 | case TAB (PCINDEX, LONG): |
| 4511 | assert (fragP->fr_fix >= 2); |
| 4512 | buffer_address[-2] |= 0x1; |
| 4513 | buffer_address[-1] = 0x30; |
| 4514 | fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol, |
| 4515 | fragP->fr_offset, 1, RELAX_RELOC_PC32); |
| 4516 | fixP->fx_pcrel_adjust = 2; |
| 4517 | fragP->fr_fix += 4; |
| 4518 | break; |
| 4519 | case TAB (ABSTOPCREL, SHORT): |
| 4520 | fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset, |
| 4521 | 1, RELAX_RELOC_PC16); |
| 4522 | fragP->fr_fix += 2; |
| 4523 | break; |
| 4524 | case TAB (ABSTOPCREL, LONG): |
| 4525 | /* The thing to do here is force it to ABSOLUTE LONG, since |
| 4526 | ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway */ |
| 4527 | if ((fragP->fr_opcode[1] & 0x3F) != 0x3A) |
| 4528 | abort (); |
| 4529 | fragP->fr_opcode[1] &= ~0x3F; |
| 4530 | fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */ |
| 4531 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, |
| 4532 | 0, RELAX_RELOC_ABS32); |
| 4533 | fragP->fr_fix += 4; |
| 4534 | break; |
| 4535 | } |
| 4536 | } |
| 4537 | |
| 4538 | #ifndef BFD_ASSEMBLER |
| 4539 | |
| 4540 | void |
| 4541 | md_convert_frag (headers, sec, fragP) |
| 4542 | object_headers *headers ATTRIBUTE_UNUSED; |
| 4543 | segT sec ATTRIBUTE_UNUSED; |
| 4544 | fragS *fragP; |
| 4545 | { |
| 4546 | md_convert_frag_1 (fragP); |
| 4547 | } |
| 4548 | |
| 4549 | #else |
| 4550 | |
| 4551 | void |
| 4552 | md_convert_frag (abfd, sec, fragP) |
| 4553 | bfd *abfd ATTRIBUTE_UNUSED; |
| 4554 | segT sec ATTRIBUTE_UNUSED; |
| 4555 | fragS *fragP; |
| 4556 | { |
| 4557 | md_convert_frag_1 (fragP); |
| 4558 | } |
| 4559 | #endif |
| 4560 | |
| 4561 | /* Force truly undefined symbols to their maximum size, and generally set up |
| 4562 | the frag list to be relaxed |
| 4563 | */ |
| 4564 | int |
| 4565 | md_estimate_size_before_relax (fragP, segment) |
| 4566 | register fragS *fragP; |
| 4567 | segT segment; |
| 4568 | { |
| 4569 | /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */ |
| 4570 | switch (fragP->fr_subtype) |
| 4571 | { |
| 4572 | case TAB (BRANCHBWL, SZ_UNDEF): |
| 4573 | case TAB (BRABSJUNC, SZ_UNDEF): |
| 4574 | case TAB (BRABSJCOND, SZ_UNDEF): |
| 4575 | { |
| 4576 | if (S_GET_SEGMENT (fragP->fr_symbol) == segment |
| 4577 | && relaxable_symbol (fragP->fr_symbol)) |
| 4578 | { |
| 4579 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE); |
| 4580 | } |
| 4581 | else if (flag_short_refs) |
| 4582 | { |
| 4583 | /* Symbol is undefined and we want short ref. */ |
| 4584 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); |
| 4585 | } |
| 4586 | else |
| 4587 | { |
| 4588 | /* Symbol is still undefined. Make it LONG. */ |
| 4589 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG); |
| 4590 | } |
| 4591 | break; |
| 4592 | } |
| 4593 | |
| 4594 | case TAB (BRANCHBW, SZ_UNDEF): |
| 4595 | { |
| 4596 | if (S_GET_SEGMENT (fragP->fr_symbol) == segment |
| 4597 | && relaxable_symbol (fragP->fr_symbol)) |
| 4598 | { |
| 4599 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE); |
| 4600 | } |
| 4601 | else |
| 4602 | { |
| 4603 | /* Symbol is undefined and we don't have long branches. */ |
| 4604 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); |
| 4605 | } |
| 4606 | break; |
| 4607 | } |
| 4608 | |
| 4609 | case TAB (FBRANCH, SZ_UNDEF): |
| 4610 | case TAB (DBCCLBR, SZ_UNDEF): |
| 4611 | case TAB (DBCCABSJ, SZ_UNDEF): |
| 4612 | case TAB (PCREL1632, SZ_UNDEF): |
| 4613 | { |
| 4614 | if ((S_GET_SEGMENT (fragP->fr_symbol) == segment |
| 4615 | && relaxable_symbol (fragP->fr_symbol)) |
| 4616 | || flag_short_refs) |
| 4617 | { |
| 4618 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); |
| 4619 | } |
| 4620 | else |
| 4621 | { |
| 4622 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG); |
| 4623 | } |
| 4624 | break; |
| 4625 | } |
| 4626 | |
| 4627 | case TAB (PCINDEX, SZ_UNDEF): |
| 4628 | if ((S_GET_SEGMENT (fragP->fr_symbol) == segment |
| 4629 | && relaxable_symbol (fragP->fr_symbol))) |
| 4630 | { |
| 4631 | fragP->fr_subtype = TAB (PCINDEX, BYTE); |
| 4632 | } |
| 4633 | else |
| 4634 | { |
| 4635 | fragP->fr_subtype = TAB (PCINDEX, LONG); |
| 4636 | } |
| 4637 | break; |
| 4638 | |
| 4639 | case TAB (ABSTOPCREL, SZ_UNDEF): |
| 4640 | { |
| 4641 | if ((S_GET_SEGMENT (fragP->fr_symbol) == segment |
| 4642 | && relaxable_symbol (fragP->fr_symbol))) |
| 4643 | { |
| 4644 | fragP->fr_subtype = TAB (ABSTOPCREL, SHORT); |
| 4645 | } |
| 4646 | else |
| 4647 | { |
| 4648 | fragP->fr_subtype = TAB (ABSTOPCREL, LONG); |
| 4649 | } |
| 4650 | break; |
| 4651 | } |
| 4652 | |
| 4653 | default: |
| 4654 | break; |
| 4655 | } |
| 4656 | |
| 4657 | /* Now that SZ_UNDEF are taken care of, check others. */ |
| 4658 | switch (fragP->fr_subtype) |
| 4659 | { |
| 4660 | case TAB (BRANCHBWL, BYTE): |
| 4661 | case TAB (BRABSJUNC, BYTE): |
| 4662 | case TAB (BRABSJCOND, BYTE): |
| 4663 | case TAB (BRANCHBW, BYTE): |
| 4664 | /* We can't do a short jump to the next instruction, so in that |
| 4665 | case we force word mode. If the symbol is at the start of a |
| 4666 | frag, and it is the next frag with any data in it (usually |
| 4667 | this is just the next frag, but assembler listings may |
| 4668 | introduce empty frags), we must use word mode. */ |
| 4669 | if (fragP->fr_symbol) |
| 4670 | { |
| 4671 | fragS *sym_frag; |
| 4672 | |
| 4673 | sym_frag = symbol_get_frag (fragP->fr_symbol); |
| 4674 | if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address) |
| 4675 | { |
| 4676 | fragS *l; |
| 4677 | |
| 4678 | for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next) |
| 4679 | if (l->fr_fix != 0) |
| 4680 | break; |
| 4681 | if (l == sym_frag) |
| 4682 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); |
| 4683 | } |
| 4684 | } |
| 4685 | break; |
| 4686 | default: |
| 4687 | break; |
| 4688 | } |
| 4689 | return md_relax_table[fragP->fr_subtype].rlx_length; |
| 4690 | } |
| 4691 | |
| 4692 | #if defined(OBJ_AOUT) | defined(OBJ_BOUT) |
| 4693 | /* the bit-field entries in the relocation_info struct plays hell |
| 4694 | with the byte-order problems of cross-assembly. So as a hack, |
| 4695 | I added this mach. dependent ri twiddler. Ugly, but it gets |
| 4696 | you there. -KWK */ |
| 4697 | /* on m68k: first 4 bytes are normal unsigned long, next three bytes |
| 4698 | are symbolnum, most sig. byte first. Last byte is broken up with |
| 4699 | bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower |
| 4700 | nibble as nuthin. (on Sun 3 at least) */ |
| 4701 | /* Translate the internal relocation information into target-specific |
| 4702 | format. */ |
| 4703 | #ifdef comment |
| 4704 | void |
| 4705 | md_ri_to_chars (the_bytes, ri) |
| 4706 | char *the_bytes; |
| 4707 | struct reloc_info_generic *ri; |
| 4708 | { |
| 4709 | /* this is easy */ |
| 4710 | md_number_to_chars (the_bytes, ri->r_address, 4); |
| 4711 | /* now the fun stuff */ |
| 4712 | the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff; |
| 4713 | the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff; |
| 4714 | the_bytes[6] = ri->r_symbolnum & 0x0ff; |
| 4715 | the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) | |
| 4716 | ((ri->r_extern << 4) & 0x10)); |
| 4717 | } |
| 4718 | |
| 4719 | #endif /* comment */ |
| 4720 | |
| 4721 | #ifndef BFD_ASSEMBLER |
| 4722 | void |
| 4723 | tc_aout_fix_to_chars (where, fixP, segment_address_in_file) |
| 4724 | char *where; |
| 4725 | fixS *fixP; |
| 4726 | relax_addressT segment_address_in_file; |
| 4727 | { |
| 4728 | /* |
| 4729 | * In: length of relocation (or of address) in chars: 1, 2 or 4. |
| 4730 | * Out: GNU LD relocation length code: 0, 1, or 2. |
| 4731 | */ |
| 4732 | |
| 4733 | static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2}; |
| 4734 | long r_symbolnum; |
| 4735 | |
| 4736 | know (fixP->fx_addsy != NULL); |
| 4737 | |
| 4738 | md_number_to_chars (where, |
| 4739 | fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file, |
| 4740 | 4); |
| 4741 | |
| 4742 | r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy) |
| 4743 | ? S_GET_TYPE (fixP->fx_addsy) |
| 4744 | : fixP->fx_addsy->sy_number); |
| 4745 | |
| 4746 | where[4] = (r_symbolnum >> 16) & 0x0ff; |
| 4747 | where[5] = (r_symbolnum >> 8) & 0x0ff; |
| 4748 | where[6] = r_symbolnum & 0x0ff; |
| 4749 | where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) | |
| 4750 | (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10)); |
| 4751 | } |
| 4752 | #endif |
| 4753 | |
| 4754 | #endif /* OBJ_AOUT or OBJ_BOUT */ |
| 4755 | |
| 4756 | #ifndef WORKING_DOT_WORD |
| 4757 | CONST int md_short_jump_size = 4; |
| 4758 | CONST int md_long_jump_size = 6; |
| 4759 | |
| 4760 | void |
| 4761 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) |
| 4762 | char *ptr; |
| 4763 | addressT from_addr, to_addr; |
| 4764 | fragS *frag ATTRIBUTE_UNUSED; |
| 4765 | symbolS *to_symbol ATTRIBUTE_UNUSED; |
| 4766 | { |
| 4767 | valueT offset; |
| 4768 | |
| 4769 | offset = to_addr - (from_addr + 2); |
| 4770 | |
| 4771 | md_number_to_chars (ptr, (valueT) 0x6000, 2); |
| 4772 | md_number_to_chars (ptr + 2, (valueT) offset, 2); |
| 4773 | } |
| 4774 | |
| 4775 | void |
| 4776 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) |
| 4777 | char *ptr; |
| 4778 | addressT from_addr, to_addr; |
| 4779 | fragS *frag; |
| 4780 | symbolS *to_symbol; |
| 4781 | { |
| 4782 | valueT offset; |
| 4783 | |
| 4784 | if (!HAVE_LONG_BRANCH(current_architecture)) |
| 4785 | { |
| 4786 | offset = to_addr - S_GET_VALUE (to_symbol); |
| 4787 | md_number_to_chars (ptr, (valueT) 0x4EF9, 2); |
| 4788 | md_number_to_chars (ptr + 2, (valueT) offset, 4); |
| 4789 | fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0, |
| 4790 | 0, NO_RELOC); |
| 4791 | } |
| 4792 | else |
| 4793 | { |
| 4794 | offset = to_addr - (from_addr + 2); |
| 4795 | md_number_to_chars (ptr, (valueT) 0x60ff, 2); |
| 4796 | md_number_to_chars (ptr + 2, (valueT) offset, 4); |
| 4797 | } |
| 4798 | } |
| 4799 | |
| 4800 | #endif |
| 4801 | |
| 4802 | /* Different values of OK tell what its OK to return. Things that |
| 4803 | aren't OK are an error (what a shock, no?) |
| 4804 | |
| 4805 | 0: Everything is OK |
| 4806 | 10: Absolute 1:8 only |
| 4807 | 20: Absolute 0:7 only |
| 4808 | 30: absolute 0:15 only |
| 4809 | 40: Absolute 0:31 only |
| 4810 | 50: absolute 0:127 only |
| 4811 | 55: absolute -64:63 only |
| 4812 | 60: absolute -128:127 only |
| 4813 | 70: absolute 0:4095 only |
| 4814 | 80: No bignums |
| 4815 | |
| 4816 | */ |
| 4817 | |
| 4818 | static int |
| 4819 | get_num (exp, ok) |
| 4820 | struct m68k_exp *exp; |
| 4821 | int ok; |
| 4822 | { |
| 4823 | if (exp->exp.X_op == O_absent) |
| 4824 | { |
| 4825 | /* Do the same thing the VAX asm does */ |
| 4826 | op (exp) = O_constant; |
| 4827 | adds (exp) = 0; |
| 4828 | subs (exp) = 0; |
| 4829 | offs (exp) = 0; |
| 4830 | if (ok == 10) |
| 4831 | { |
| 4832 | as_warn (_("expression out of range: defaulting to 1")); |
| 4833 | offs (exp) = 1; |
| 4834 | } |
| 4835 | } |
| 4836 | else if (exp->exp.X_op == O_constant) |
| 4837 | { |
| 4838 | switch (ok) |
| 4839 | { |
| 4840 | case 10: |
| 4841 | if (offs (exp) < 1 || offs (exp) > 8) |
| 4842 | { |
| 4843 | as_warn (_("expression out of range: defaulting to 1")); |
| 4844 | offs (exp) = 1; |
| 4845 | } |
| 4846 | break; |
| 4847 | case 20: |
| 4848 | if (offs (exp) < 0 || offs (exp) > 7) |
| 4849 | goto outrange; |
| 4850 | break; |
| 4851 | case 30: |
| 4852 | if (offs (exp) < 0 || offs (exp) > 15) |
| 4853 | goto outrange; |
| 4854 | break; |
| 4855 | case 40: |
| 4856 | if (offs (exp) < 0 || offs (exp) > 32) |
| 4857 | goto outrange; |
| 4858 | break; |
| 4859 | case 50: |
| 4860 | if (offs (exp) < 0 || offs (exp) > 127) |
| 4861 | goto outrange; |
| 4862 | break; |
| 4863 | case 55: |
| 4864 | if (offs (exp) < -64 || offs (exp) > 63) |
| 4865 | goto outrange; |
| 4866 | break; |
| 4867 | case 60: |
| 4868 | if (offs (exp) < -128 || offs (exp) > 127) |
| 4869 | goto outrange; |
| 4870 | break; |
| 4871 | case 70: |
| 4872 | if (offs (exp) < 0 || offs (exp) > 4095) |
| 4873 | { |
| 4874 | outrange: |
| 4875 | as_warn (_("expression out of range: defaulting to 0")); |
| 4876 | offs (exp) = 0; |
| 4877 | } |
| 4878 | break; |
| 4879 | default: |
| 4880 | break; |
| 4881 | } |
| 4882 | } |
| 4883 | else if (exp->exp.X_op == O_big) |
| 4884 | { |
| 4885 | if (offs (exp) <= 0 /* flonum */ |
| 4886 | && (ok == 80 /* no bignums */ |
| 4887 | || (ok > 10 /* small-int ranges including 0 ok */ |
| 4888 | /* If we have a flonum zero, a zero integer should |
| 4889 | do as well (e.g., in moveq). */ |
| 4890 | && generic_floating_point_number.exponent == 0 |
| 4891 | && generic_floating_point_number.low[0] == 0))) |
| 4892 | { |
| 4893 | /* HACK! Turn it into a long */ |
| 4894 | LITTLENUM_TYPE words[6]; |
| 4895 | |
| 4896 | gen_to_words (words, 2, 8L); /* These numbers are magic! */ |
| 4897 | op (exp) = O_constant; |
| 4898 | adds (exp) = 0; |
| 4899 | subs (exp) = 0; |
| 4900 | offs (exp) = words[1] | (words[0] << 16); |
| 4901 | } |
| 4902 | else if (ok != 0) |
| 4903 | { |
| 4904 | op (exp) = O_constant; |
| 4905 | adds (exp) = 0; |
| 4906 | subs (exp) = 0; |
| 4907 | offs (exp) = (ok == 10) ? 1 : 0; |
| 4908 | as_warn (_("Can't deal with expression; defaulting to %ld"), |
| 4909 | offs (exp)); |
| 4910 | } |
| 4911 | } |
| 4912 | else |
| 4913 | { |
| 4914 | if (ok >= 10 && ok <= 70) |
| 4915 | { |
| 4916 | op (exp) = O_constant; |
| 4917 | adds (exp) = 0; |
| 4918 | subs (exp) = 0; |
| 4919 | offs (exp) = (ok == 10) ? 1 : 0; |
| 4920 | as_warn (_("Can't deal with expression; defaulting to %ld"), |
| 4921 | offs (exp)); |
| 4922 | } |
| 4923 | } |
| 4924 | |
| 4925 | if (exp->size != SIZE_UNSPEC) |
| 4926 | { |
| 4927 | switch (exp->size) |
| 4928 | { |
| 4929 | case SIZE_UNSPEC: |
| 4930 | case SIZE_LONG: |
| 4931 | break; |
| 4932 | case SIZE_BYTE: |
| 4933 | if (!isbyte (offs (exp))) |
| 4934 | as_warn (_("expression doesn't fit in BYTE")); |
| 4935 | break; |
| 4936 | case SIZE_WORD: |
| 4937 | if (!isword (offs (exp))) |
| 4938 | as_warn (_("expression doesn't fit in WORD")); |
| 4939 | break; |
| 4940 | } |
| 4941 | } |
| 4942 | |
| 4943 | return offs (exp); |
| 4944 | } |
| 4945 | |
| 4946 | /* These are the back-ends for the various machine dependent pseudo-ops. */ |
| 4947 | |
| 4948 | static void |
| 4949 | s_data1 (ignore) |
| 4950 | int ignore ATTRIBUTE_UNUSED; |
| 4951 | { |
| 4952 | subseg_set (data_section, 1); |
| 4953 | demand_empty_rest_of_line (); |
| 4954 | } |
| 4955 | |
| 4956 | static void |
| 4957 | s_data2 (ignore) |
| 4958 | int ignore ATTRIBUTE_UNUSED; |
| 4959 | { |
| 4960 | subseg_set (data_section, 2); |
| 4961 | demand_empty_rest_of_line (); |
| 4962 | } |
| 4963 | |
| 4964 | static void |
| 4965 | s_bss (ignore) |
| 4966 | int ignore ATTRIBUTE_UNUSED; |
| 4967 | { |
| 4968 | /* We don't support putting frags in the BSS segment, we fake it |
| 4969 | by marking in_bss, then looking at s_skip for clues. */ |
| 4970 | |
| 4971 | subseg_set (bss_section, 0); |
| 4972 | demand_empty_rest_of_line (); |
| 4973 | } |
| 4974 | |
| 4975 | static void |
| 4976 | s_even (ignore) |
| 4977 | int ignore ATTRIBUTE_UNUSED; |
| 4978 | { |
| 4979 | register int temp; |
| 4980 | register long temp_fill; |
| 4981 | |
| 4982 | temp = 1; /* JF should be 2? */ |
| 4983 | temp_fill = get_absolute_expression (); |
| 4984 | if (!need_pass_2) /* Never make frag if expect extra pass. */ |
| 4985 | frag_align (temp, (int) temp_fill, 0); |
| 4986 | demand_empty_rest_of_line (); |
| 4987 | record_alignment (now_seg, temp); |
| 4988 | } |
| 4989 | |
| 4990 | static void |
| 4991 | s_proc (ignore) |
| 4992 | int ignore ATTRIBUTE_UNUSED; |
| 4993 | { |
| 4994 | demand_empty_rest_of_line (); |
| 4995 | } |
| 4996 | \f |
| 4997 | /* Pseudo-ops handled for MRI compatibility. */ |
| 4998 | |
| 4999 | /* This function returns non-zero if the argument is a conditional |
| 5000 | pseudo-op. This is called when checking whether a pending |
| 5001 | alignment is needed. */ |
| 5002 | |
| 5003 | int |
| 5004 | m68k_conditional_pseudoop (pop) |
| 5005 | pseudo_typeS *pop; |
| 5006 | { |
| 5007 | return (pop->poc_handler == s_mri_if |
| 5008 | || pop->poc_handler == s_mri_else); |
| 5009 | } |
| 5010 | |
| 5011 | /* Handle an MRI style chip specification. */ |
| 5012 | |
| 5013 | static void |
| 5014 | mri_chip () |
| 5015 | { |
| 5016 | char *s; |
| 5017 | char c; |
| 5018 | int i; |
| 5019 | |
| 5020 | s = input_line_pointer; |
| 5021 | /* We can't use get_symbol_end since the processor names are not proper |
| 5022 | symbols. */ |
| 5023 | while (is_part_of_name (c = *input_line_pointer++)) |
| 5024 | ; |
| 5025 | *--input_line_pointer = 0; |
| 5026 | for (i = 0; i < n_archs; i++) |
| 5027 | if (strcasecmp (s, archs[i].name) == 0) |
| 5028 | break; |
| 5029 | if (i >= n_archs) |
| 5030 | { |
| 5031 | as_bad (_("%s: unrecognized processor name"), s); |
| 5032 | *input_line_pointer = c; |
| 5033 | ignore_rest_of_line (); |
| 5034 | return; |
| 5035 | } |
| 5036 | *input_line_pointer = c; |
| 5037 | |
| 5038 | if (*input_line_pointer == '/') |
| 5039 | current_architecture = 0; |
| 5040 | else |
| 5041 | current_architecture &= m68881 | m68851; |
| 5042 | current_architecture |= archs[i].arch; |
| 5043 | |
| 5044 | while (*input_line_pointer == '/') |
| 5045 | { |
| 5046 | ++input_line_pointer; |
| 5047 | s = input_line_pointer; |
| 5048 | /* We can't use get_symbol_end since the processor names are not |
| 5049 | proper symbols. */ |
| 5050 | while (is_part_of_name (c = *input_line_pointer++)) |
| 5051 | ; |
| 5052 | *--input_line_pointer = 0; |
| 5053 | if (strcmp (s, "68881") == 0) |
| 5054 | current_architecture |= m68881; |
| 5055 | else if (strcmp (s, "68851") == 0) |
| 5056 | current_architecture |= m68851; |
| 5057 | *input_line_pointer = c; |
| 5058 | } |
| 5059 | |
| 5060 | /* Update info about available control registers. */ |
| 5061 | select_control_regs (); |
| 5062 | } |
| 5063 | |
| 5064 | /* The MRI CHIP pseudo-op. */ |
| 5065 | |
| 5066 | static void |
| 5067 | s_chip (ignore) |
| 5068 | int ignore ATTRIBUTE_UNUSED; |
| 5069 | { |
| 5070 | char *stop = NULL; |
| 5071 | char stopc; |
| 5072 | |
| 5073 | if (flag_mri) |
| 5074 | stop = mri_comment_field (&stopc); |
| 5075 | mri_chip (); |
| 5076 | if (flag_mri) |
| 5077 | mri_comment_end (stop, stopc); |
| 5078 | demand_empty_rest_of_line (); |
| 5079 | } |
| 5080 | |
| 5081 | /* The MRI FOPT pseudo-op. */ |
| 5082 | |
| 5083 | static void |
| 5084 | s_fopt (ignore) |
| 5085 | int ignore ATTRIBUTE_UNUSED; |
| 5086 | { |
| 5087 | SKIP_WHITESPACE (); |
| 5088 | |
| 5089 | if (strncasecmp (input_line_pointer, "ID=", 3) == 0) |
| 5090 | { |
| 5091 | int temp; |
| 5092 | |
| 5093 | input_line_pointer += 3; |
| 5094 | temp = get_absolute_expression (); |
| 5095 | if (temp < 0 || temp > 7) |
| 5096 | as_bad (_("bad coprocessor id")); |
| 5097 | else |
| 5098 | m68k_float_copnum = COP0 + temp; |
| 5099 | } |
| 5100 | else |
| 5101 | { |
| 5102 | as_bad (_("unrecognized fopt option")); |
| 5103 | ignore_rest_of_line (); |
| 5104 | return; |
| 5105 | } |
| 5106 | |
| 5107 | demand_empty_rest_of_line (); |
| 5108 | } |
| 5109 | |
| 5110 | /* The structure used to handle the MRI OPT pseudo-op. */ |
| 5111 | |
| 5112 | struct opt_action |
| 5113 | { |
| 5114 | /* The name of the option. */ |
| 5115 | const char *name; |
| 5116 | |
| 5117 | /* If this is not NULL, just call this function. The first argument |
| 5118 | is the ARG field of this structure, the second argument is |
| 5119 | whether the option was negated. */ |
| 5120 | void (*pfn) PARAMS ((int arg, int on)); |
| 5121 | |
| 5122 | /* If this is not NULL, and the PFN field is NULL, set the variable |
| 5123 | this points to. Set it to the ARG field if the option was not |
| 5124 | negated, and the NOTARG field otherwise. */ |
| 5125 | int *pvar; |
| 5126 | |
| 5127 | /* The value to pass to PFN or to assign to *PVAR. */ |
| 5128 | int arg; |
| 5129 | |
| 5130 | /* The value to assign to *PVAR if the option is negated. If PFN is |
| 5131 | NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then |
| 5132 | the option may not be negated. */ |
| 5133 | int notarg; |
| 5134 | }; |
| 5135 | |
| 5136 | /* The table used to handle the MRI OPT pseudo-op. */ |
| 5137 | |
| 5138 | static void skip_to_comma PARAMS ((int, int)); |
| 5139 | static void opt_nest PARAMS ((int, int)); |
| 5140 | static void opt_chip PARAMS ((int, int)); |
| 5141 | static void opt_list PARAMS ((int, int)); |
| 5142 | static void opt_list_symbols PARAMS ((int, int)); |
| 5143 | |
| 5144 | static const struct opt_action opt_table[] = |
| 5145 | { |
| 5146 | { "abspcadd", 0, &m68k_abspcadd, 1, 0 }, |
| 5147 | |
| 5148 | /* We do relaxing, so there is little use for these options. */ |
| 5149 | { "b", 0, 0, 0, 0 }, |
| 5150 | { "brs", 0, 0, 0, 0 }, |
| 5151 | { "brb", 0, 0, 0, 0 }, |
| 5152 | { "brl", 0, 0, 0, 0 }, |
| 5153 | { "brw", 0, 0, 0, 0 }, |
| 5154 | |
| 5155 | { "c", 0, 0, 0, 0 }, |
| 5156 | { "cex", 0, 0, 0, 0 }, |
| 5157 | { "case", 0, &symbols_case_sensitive, 1, 0 }, |
| 5158 | { "cl", 0, 0, 0, 0 }, |
| 5159 | { "cre", 0, 0, 0, 0 }, |
| 5160 | { "d", 0, &flag_keep_locals, 1, 0 }, |
| 5161 | { "e", 0, 0, 0, 0 }, |
| 5162 | { "f", 0, &flag_short_refs, 1, 0 }, |
| 5163 | { "frs", 0, &flag_short_refs, 1, 0 }, |
| 5164 | { "frl", 0, &flag_short_refs, 0, 1 }, |
| 5165 | { "g", 0, 0, 0, 0 }, |
| 5166 | { "i", 0, 0, 0, 0 }, |
| 5167 | { "m", 0, 0, 0, 0 }, |
| 5168 | { "mex", 0, 0, 0, 0 }, |
| 5169 | { "mc", 0, 0, 0, 0 }, |
| 5170 | { "md", 0, 0, 0, 0 }, |
| 5171 | { "nest", opt_nest, 0, 0, 0 }, |
| 5172 | { "next", skip_to_comma, 0, 0, 0 }, |
| 5173 | { "o", 0, 0, 0, 0 }, |
| 5174 | { "old", 0, 0, 0, 0 }, |
| 5175 | { "op", skip_to_comma, 0, 0, 0 }, |
| 5176 | { "pco", 0, 0, 0, 0 }, |
| 5177 | { "p", opt_chip, 0, 0, 0 }, |
| 5178 | { "pcr", 0, 0, 0, 0 }, |
| 5179 | { "pcs", 0, 0, 0, 0 }, |
| 5180 | { "r", 0, 0, 0, 0 }, |
| 5181 | { "quick", 0, &m68k_quick, 1, 0 }, |
| 5182 | { "rel32", 0, &m68k_rel32, 1, 0 }, |
| 5183 | { "s", opt_list, 0, 0, 0 }, |
| 5184 | { "t", opt_list_symbols, 0, 0, 0 }, |
| 5185 | { "w", 0, &flag_no_warnings, 0, 1 }, |
| 5186 | { "x", 0, 0, 0, 0 } |
| 5187 | }; |
| 5188 | |
| 5189 | #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0])) |
| 5190 | |
| 5191 | /* The MRI OPT pseudo-op. */ |
| 5192 | |
| 5193 | static void |
| 5194 | s_opt (ignore) |
| 5195 | int ignore ATTRIBUTE_UNUSED; |
| 5196 | { |
| 5197 | do |
| 5198 | { |
| 5199 | int t; |
| 5200 | char *s; |
| 5201 | char c; |
| 5202 | int i; |
| 5203 | const struct opt_action *o; |
| 5204 | |
| 5205 | SKIP_WHITESPACE (); |
| 5206 | |
| 5207 | t = 1; |
| 5208 | if (*input_line_pointer == '-') |
| 5209 | { |
| 5210 | ++input_line_pointer; |
| 5211 | t = 0; |
| 5212 | } |
| 5213 | else if (strncasecmp (input_line_pointer, "NO", 2) == 0) |
| 5214 | { |
| 5215 | input_line_pointer += 2; |
| 5216 | t = 0; |
| 5217 | } |
| 5218 | |
| 5219 | s = input_line_pointer; |
| 5220 | c = get_symbol_end (); |
| 5221 | |
| 5222 | for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++) |
| 5223 | { |
| 5224 | if (strcasecmp (s, o->name) == 0) |
| 5225 | { |
| 5226 | if (o->pfn) |
| 5227 | { |
| 5228 | /* Restore input_line_pointer now in case the option |
| 5229 | takes arguments. */ |
| 5230 | *input_line_pointer = c; |
| 5231 | (*o->pfn) (o->arg, t); |
| 5232 | } |
| 5233 | else if (o->pvar != NULL) |
| 5234 | { |
| 5235 | if (! t && o->arg == o->notarg) |
| 5236 | as_bad (_("option `%s' may not be negated"), s); |
| 5237 | *input_line_pointer = c; |
| 5238 | *o->pvar = t ? o->arg : o->notarg; |
| 5239 | } |
| 5240 | else |
| 5241 | *input_line_pointer = c; |
| 5242 | break; |
| 5243 | } |
| 5244 | } |
| 5245 | if (i >= OPTCOUNT) |
| 5246 | { |
| 5247 | as_bad (_("option `%s' not recognized"), s); |
| 5248 | *input_line_pointer = c; |
| 5249 | } |
| 5250 | } |
| 5251 | while (*input_line_pointer++ == ','); |
| 5252 | |
| 5253 | /* Move back to terminating character. */ |
| 5254 | --input_line_pointer; |
| 5255 | demand_empty_rest_of_line (); |
| 5256 | } |
| 5257 | |
| 5258 | /* Skip ahead to a comma. This is used for OPT options which we do |
| 5259 | not suppor tand which take arguments. */ |
| 5260 | |
| 5261 | static void |
| 5262 | skip_to_comma (arg, on) |
| 5263 | int arg ATTRIBUTE_UNUSED; |
| 5264 | int on ATTRIBUTE_UNUSED; |
| 5265 | { |
| 5266 | while (*input_line_pointer != ',' |
| 5267 | && ! is_end_of_line[(unsigned char) *input_line_pointer]) |
| 5268 | ++input_line_pointer; |
| 5269 | } |
| 5270 | |
| 5271 | /* Handle the OPT NEST=depth option. */ |
| 5272 | |
| 5273 | static void |
| 5274 | opt_nest (arg, on) |
| 5275 | int arg ATTRIBUTE_UNUSED; |
| 5276 | int on ATTRIBUTE_UNUSED; |
| 5277 | { |
| 5278 | if (*input_line_pointer != '=') |
| 5279 | { |
| 5280 | as_bad (_("bad format of OPT NEST=depth")); |
| 5281 | return; |
| 5282 | } |
| 5283 | |
| 5284 | ++input_line_pointer; |
| 5285 | max_macro_nest = get_absolute_expression (); |
| 5286 | } |
| 5287 | |
| 5288 | /* Handle the OPT P=chip option. */ |
| 5289 | |
| 5290 | static void |
| 5291 | opt_chip (arg, on) |
| 5292 | int arg ATTRIBUTE_UNUSED; |
| 5293 | int on ATTRIBUTE_UNUSED; |
| 5294 | { |
| 5295 | if (*input_line_pointer != '=') |
| 5296 | { |
| 5297 | /* This is just OPT P, which we do not support. */ |
| 5298 | return; |
| 5299 | } |
| 5300 | |
| 5301 | ++input_line_pointer; |
| 5302 | mri_chip (); |
| 5303 | } |
| 5304 | |
| 5305 | /* Handle the OPT S option. */ |
| 5306 | |
| 5307 | static void |
| 5308 | opt_list (arg, on) |
| 5309 | int arg ATTRIBUTE_UNUSED; |
| 5310 | int on; |
| 5311 | { |
| 5312 | listing_list (on); |
| 5313 | } |
| 5314 | |
| 5315 | /* Handle the OPT T option. */ |
| 5316 | |
| 5317 | static void |
| 5318 | opt_list_symbols (arg, on) |
| 5319 | int arg ATTRIBUTE_UNUSED; |
| 5320 | int on; |
| 5321 | { |
| 5322 | if (on) |
| 5323 | listing |= LISTING_SYMBOLS; |
| 5324 | else |
| 5325 | listing &=~ LISTING_SYMBOLS; |
| 5326 | } |
| 5327 | |
| 5328 | /* Handle the MRI REG pseudo-op. */ |
| 5329 | |
| 5330 | static void |
| 5331 | s_reg (ignore) |
| 5332 | int ignore ATTRIBUTE_UNUSED; |
| 5333 | { |
| 5334 | char *s; |
| 5335 | int c; |
| 5336 | struct m68k_op rop; |
| 5337 | int mask; |
| 5338 | char *stop = NULL; |
| 5339 | char stopc; |
| 5340 | |
| 5341 | if (line_label == NULL) |
| 5342 | { |
| 5343 | as_bad (_("missing label")); |
| 5344 | ignore_rest_of_line (); |
| 5345 | return; |
| 5346 | } |
| 5347 | |
| 5348 | if (flag_mri) |
| 5349 | stop = mri_comment_field (&stopc); |
| 5350 | |
| 5351 | SKIP_WHITESPACE (); |
| 5352 | |
| 5353 | s = input_line_pointer; |
| 5354 | while (ISALNUM (*input_line_pointer) |
| 5355 | #ifdef REGISTER_PREFIX |
| 5356 | || *input_line_pointer == REGISTER_PREFIX |
| 5357 | #endif |
| 5358 | || *input_line_pointer == '/' |
| 5359 | || *input_line_pointer == '-') |
| 5360 | ++input_line_pointer; |
| 5361 | c = *input_line_pointer; |
| 5362 | *input_line_pointer = '\0'; |
| 5363 | |
| 5364 | if (m68k_ip_op (s, &rop) != 0) |
| 5365 | { |
| 5366 | if (rop.error == NULL) |
| 5367 | as_bad (_("bad register list")); |
| 5368 | else |
| 5369 | as_bad (_("bad register list: %s"), rop.error); |
| 5370 | *input_line_pointer = c; |
| 5371 | ignore_rest_of_line (); |
| 5372 | return; |
| 5373 | } |
| 5374 | |
| 5375 | *input_line_pointer = c; |
| 5376 | |
| 5377 | if (rop.mode == REGLST) |
| 5378 | mask = rop.mask; |
| 5379 | else if (rop.mode == DREG) |
| 5380 | mask = 1 << (rop.reg - DATA0); |
| 5381 | else if (rop.mode == AREG) |
| 5382 | mask = 1 << (rop.reg - ADDR0 + 8); |
| 5383 | else if (rop.mode == FPREG) |
| 5384 | mask = 1 << (rop.reg - FP0 + 16); |
| 5385 | else if (rop.mode == CONTROL |
| 5386 | && rop.reg == FPI) |
| 5387 | mask = 1 << 24; |
| 5388 | else if (rop.mode == CONTROL |
| 5389 | && rop.reg == FPS) |
| 5390 | mask = 1 << 25; |
| 5391 | else if (rop.mode == CONTROL |
| 5392 | && rop.reg == FPC) |
| 5393 | mask = 1 << 26; |
| 5394 | else |
| 5395 | { |
| 5396 | as_bad (_("bad register list")); |
| 5397 | ignore_rest_of_line (); |
| 5398 | return; |
| 5399 | } |
| 5400 | |
| 5401 | S_SET_SEGMENT (line_label, reg_section); |
| 5402 | S_SET_VALUE (line_label, ~mask); |
| 5403 | symbol_set_frag (line_label, &zero_address_frag); |
| 5404 | |
| 5405 | if (flag_mri) |
| 5406 | mri_comment_end (stop, stopc); |
| 5407 | |
| 5408 | demand_empty_rest_of_line (); |
| 5409 | } |
| 5410 | |
| 5411 | /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */ |
| 5412 | |
| 5413 | struct save_opts |
| 5414 | { |
| 5415 | struct save_opts *next; |
| 5416 | int abspcadd; |
| 5417 | int symbols_case_sensitive; |
| 5418 | int keep_locals; |
| 5419 | int short_refs; |
| 5420 | int architecture; |
| 5421 | int quick; |
| 5422 | int rel32; |
| 5423 | int listing; |
| 5424 | int no_warnings; |
| 5425 | /* FIXME: We don't save OPT S. */ |
| 5426 | }; |
| 5427 | |
| 5428 | /* This variable holds the stack of saved options. */ |
| 5429 | |
| 5430 | static struct save_opts *save_stack; |
| 5431 | |
| 5432 | /* The MRI SAVE pseudo-op. */ |
| 5433 | |
| 5434 | static void |
| 5435 | s_save (ignore) |
| 5436 | int ignore ATTRIBUTE_UNUSED; |
| 5437 | { |
| 5438 | struct save_opts *s; |
| 5439 | |
| 5440 | s = (struct save_opts *) xmalloc (sizeof (struct save_opts)); |
| 5441 | s->abspcadd = m68k_abspcadd; |
| 5442 | s->symbols_case_sensitive = symbols_case_sensitive; |
| 5443 | s->keep_locals = flag_keep_locals; |
| 5444 | s->short_refs = flag_short_refs; |
| 5445 | s->architecture = current_architecture; |
| 5446 | s->quick = m68k_quick; |
| 5447 | s->rel32 = m68k_rel32; |
| 5448 | s->listing = listing; |
| 5449 | s->no_warnings = flag_no_warnings; |
| 5450 | |
| 5451 | s->next = save_stack; |
| 5452 | save_stack = s; |
| 5453 | |
| 5454 | demand_empty_rest_of_line (); |
| 5455 | } |
| 5456 | |
| 5457 | /* The MRI RESTORE pseudo-op. */ |
| 5458 | |
| 5459 | static void |
| 5460 | s_restore (ignore) |
| 5461 | int ignore ATTRIBUTE_UNUSED; |
| 5462 | { |
| 5463 | struct save_opts *s; |
| 5464 | |
| 5465 | if (save_stack == NULL) |
| 5466 | { |
| 5467 | as_bad (_("restore without save")); |
| 5468 | ignore_rest_of_line (); |
| 5469 | return; |
| 5470 | } |
| 5471 | |
| 5472 | s = save_stack; |
| 5473 | save_stack = s->next; |
| 5474 | |
| 5475 | m68k_abspcadd = s->abspcadd; |
| 5476 | symbols_case_sensitive = s->symbols_case_sensitive; |
| 5477 | flag_keep_locals = s->keep_locals; |
| 5478 | flag_short_refs = s->short_refs; |
| 5479 | current_architecture = s->architecture; |
| 5480 | m68k_quick = s->quick; |
| 5481 | m68k_rel32 = s->rel32; |
| 5482 | listing = s->listing; |
| 5483 | flag_no_warnings = s->no_warnings; |
| 5484 | |
| 5485 | free (s); |
| 5486 | |
| 5487 | demand_empty_rest_of_line (); |
| 5488 | } |
| 5489 | |
| 5490 | /* Types of MRI structured control directives. */ |
| 5491 | |
| 5492 | enum mri_control_type |
| 5493 | { |
| 5494 | mri_for, |
| 5495 | mri_if, |
| 5496 | mri_repeat, |
| 5497 | mri_while |
| 5498 | }; |
| 5499 | |
| 5500 | /* This structure is used to stack the MRI structured control |
| 5501 | directives. */ |
| 5502 | |
| 5503 | struct mri_control_info |
| 5504 | { |
| 5505 | /* The directive within which this one is enclosed. */ |
| 5506 | struct mri_control_info *outer; |
| 5507 | |
| 5508 | /* The type of directive. */ |
| 5509 | enum mri_control_type type; |
| 5510 | |
| 5511 | /* Whether an ELSE has been in an IF. */ |
| 5512 | int else_seen; |
| 5513 | |
| 5514 | /* The add or sub statement at the end of a FOR. */ |
| 5515 | char *incr; |
| 5516 | |
| 5517 | /* The label of the top of a FOR or REPEAT loop. */ |
| 5518 | char *top; |
| 5519 | |
| 5520 | /* The label to jump to for the next iteration, or the else |
| 5521 | expression of a conditional. */ |
| 5522 | char *next; |
| 5523 | |
| 5524 | /* The label to jump to to break out of the loop, or the label past |
| 5525 | the end of a conditional. */ |
| 5526 | char *bottom; |
| 5527 | }; |
| 5528 | |
| 5529 | /* The stack of MRI structured control directives. */ |
| 5530 | |
| 5531 | static struct mri_control_info *mri_control_stack; |
| 5532 | |
| 5533 | /* The current MRI structured control directive index number, used to |
| 5534 | generate label names. */ |
| 5535 | |
| 5536 | static int mri_control_index; |
| 5537 | |
| 5538 | /* Some function prototypes. */ |
| 5539 | |
| 5540 | static void mri_assemble PARAMS ((char *)); |
| 5541 | static char *mri_control_label PARAMS ((void)); |
| 5542 | static struct mri_control_info *push_mri_control |
| 5543 | PARAMS ((enum mri_control_type)); |
| 5544 | static void pop_mri_control PARAMS ((void)); |
| 5545 | static int parse_mri_condition PARAMS ((int *)); |
| 5546 | static int parse_mri_control_operand |
| 5547 | PARAMS ((int *, char **, char **, char **, char **)); |
| 5548 | static int swap_mri_condition PARAMS ((int)); |
| 5549 | static int reverse_mri_condition PARAMS ((int)); |
| 5550 | static void build_mri_control_operand |
| 5551 | PARAMS ((int, int, char *, char *, char *, char *, const char *, |
| 5552 | const char *, int)); |
| 5553 | static void parse_mri_control_expression |
| 5554 | PARAMS ((char *, int, const char *, const char *, int)); |
| 5555 | |
| 5556 | /* Assemble an instruction for an MRI structured control directive. */ |
| 5557 | |
| 5558 | static void |
| 5559 | mri_assemble (str) |
| 5560 | char *str; |
| 5561 | { |
| 5562 | char *s; |
| 5563 | |
| 5564 | /* md_assemble expects the opcode to be in lower case. */ |
| 5565 | for (s = str; *s != ' ' && *s != '\0'; s++) |
| 5566 | *s = TOLOWER (*s); |
| 5567 | |
| 5568 | md_assemble (str); |
| 5569 | } |
| 5570 | |
| 5571 | /* Generate a new MRI label structured control directive label name. */ |
| 5572 | |
| 5573 | static char * |
| 5574 | mri_control_label () |
| 5575 | { |
| 5576 | char *n; |
| 5577 | |
| 5578 | n = (char *) xmalloc (20); |
| 5579 | sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index); |
| 5580 | ++mri_control_index; |
| 5581 | return n; |
| 5582 | } |
| 5583 | |
| 5584 | /* Create a new MRI structured control directive. */ |
| 5585 | |
| 5586 | static struct mri_control_info * |
| 5587 | push_mri_control (type) |
| 5588 | enum mri_control_type type; |
| 5589 | { |
| 5590 | struct mri_control_info *n; |
| 5591 | |
| 5592 | n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info)); |
| 5593 | |
| 5594 | n->type = type; |
| 5595 | n->else_seen = 0; |
| 5596 | if (type == mri_if || type == mri_while) |
| 5597 | n->top = NULL; |
| 5598 | else |
| 5599 | n->top = mri_control_label (); |
| 5600 | n->next = mri_control_label (); |
| 5601 | n->bottom = mri_control_label (); |
| 5602 | |
| 5603 | n->outer = mri_control_stack; |
| 5604 | mri_control_stack = n; |
| 5605 | |
| 5606 | return n; |
| 5607 | } |
| 5608 | |
| 5609 | /* Pop off the stack of MRI structured control directives. */ |
| 5610 | |
| 5611 | static void |
| 5612 | pop_mri_control () |
| 5613 | { |
| 5614 | struct mri_control_info *n; |
| 5615 | |
| 5616 | n = mri_control_stack; |
| 5617 | mri_control_stack = n->outer; |
| 5618 | if (n->top != NULL) |
| 5619 | free (n->top); |
| 5620 | free (n->next); |
| 5621 | free (n->bottom); |
| 5622 | free (n); |
| 5623 | } |
| 5624 | |
| 5625 | /* Recognize a condition code in an MRI structured control expression. */ |
| 5626 | |
| 5627 | static int |
| 5628 | parse_mri_condition (pcc) |
| 5629 | int *pcc; |
| 5630 | { |
| 5631 | char c1, c2; |
| 5632 | |
| 5633 | know (*input_line_pointer == '<'); |
| 5634 | |
| 5635 | ++input_line_pointer; |
| 5636 | c1 = *input_line_pointer++; |
| 5637 | c2 = *input_line_pointer++; |
| 5638 | |
| 5639 | if (*input_line_pointer != '>') |
| 5640 | { |
| 5641 | as_bad (_("syntax error in structured control directive")); |
| 5642 | return 0; |
| 5643 | } |
| 5644 | |
| 5645 | ++input_line_pointer; |
| 5646 | SKIP_WHITESPACE (); |
| 5647 | |
| 5648 | c1 = TOLOWER (c1); |
| 5649 | c2 = TOLOWER (c2); |
| 5650 | |
| 5651 | *pcc = (c1 << 8) | c2; |
| 5652 | |
| 5653 | return 1; |
| 5654 | } |
| 5655 | |
| 5656 | /* Parse a single operand in an MRI structured control expression. */ |
| 5657 | |
| 5658 | static int |
| 5659 | parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop) |
| 5660 | int *pcc; |
| 5661 | char **leftstart; |
| 5662 | char **leftstop; |
| 5663 | char **rightstart; |
| 5664 | char **rightstop; |
| 5665 | { |
| 5666 | char *s; |
| 5667 | |
| 5668 | SKIP_WHITESPACE (); |
| 5669 | |
| 5670 | *pcc = -1; |
| 5671 | *leftstart = NULL; |
| 5672 | *leftstop = NULL; |
| 5673 | *rightstart = NULL; |
| 5674 | *rightstop = NULL; |
| 5675 | |
| 5676 | if (*input_line_pointer == '<') |
| 5677 | { |
| 5678 | /* It's just a condition code. */ |
| 5679 | return parse_mri_condition (pcc); |
| 5680 | } |
| 5681 | |
| 5682 | /* Look ahead for the condition code. */ |
| 5683 | for (s = input_line_pointer; *s != '\0'; ++s) |
| 5684 | { |
| 5685 | if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>') |
| 5686 | break; |
| 5687 | } |
| 5688 | if (*s == '\0') |
| 5689 | { |
| 5690 | as_bad (_("missing condition code in structured control directive")); |
| 5691 | return 0; |
| 5692 | } |
| 5693 | |
| 5694 | *leftstart = input_line_pointer; |
| 5695 | *leftstop = s; |
| 5696 | if (*leftstop > *leftstart |
| 5697 | && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t')) |
| 5698 | --*leftstop; |
| 5699 | |
| 5700 | input_line_pointer = s; |
| 5701 | if (! parse_mri_condition (pcc)) |
| 5702 | return 0; |
| 5703 | |
| 5704 | /* Look ahead for AND or OR or end of line. */ |
| 5705 | for (s = input_line_pointer; *s != '\0'; ++s) |
| 5706 | { |
| 5707 | /* We must make sure we don't misinterpret AND/OR at the end of labels! |
| 5708 | if d0 <eq> #FOOAND and d1 <ne> #BAROR then |
| 5709 | ^^^ ^^ */ |
| 5710 | if ( ( s == input_line_pointer |
| 5711 | || *(s-1) == ' ' |
| 5712 | || *(s-1) == '\t') |
| 5713 | && ( ( strncasecmp (s, "AND", 3) == 0 |
| 5714 | && (s[3] == '.' || ! is_part_of_name (s[3]))) |
| 5715 | || ( strncasecmp (s, "OR", 2) == 0 |
| 5716 | && (s[2] == '.' || ! is_part_of_name (s[2]))))) |
| 5717 | break; |
| 5718 | } |
| 5719 | |
| 5720 | *rightstart = input_line_pointer; |
| 5721 | *rightstop = s; |
| 5722 | if (*rightstop > *rightstart |
| 5723 | && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t')) |
| 5724 | --*rightstop; |
| 5725 | |
| 5726 | input_line_pointer = s; |
| 5727 | |
| 5728 | return 1; |
| 5729 | } |
| 5730 | |
| 5731 | #define MCC(b1, b2) (((b1) << 8) | (b2)) |
| 5732 | |
| 5733 | /* Swap the sense of a condition. This changes the condition so that |
| 5734 | it generates the same result when the operands are swapped. */ |
| 5735 | |
| 5736 | static int |
| 5737 | swap_mri_condition (cc) |
| 5738 | int cc; |
| 5739 | { |
| 5740 | switch (cc) |
| 5741 | { |
| 5742 | case MCC ('h', 'i'): return MCC ('c', 's'); |
| 5743 | case MCC ('l', 's'): return MCC ('c', 'c'); |
| 5744 | /* <HS> is an alias for <CC> */ |
| 5745 | case MCC ('h', 's'): |
| 5746 | case MCC ('c', 'c'): return MCC ('l', 's'); |
| 5747 | /* <LO> is an alias for <CS> */ |
| 5748 | case MCC ('l', 'o'): |
| 5749 | case MCC ('c', 's'): return MCC ('h', 'i'); |
| 5750 | case MCC ('p', 'l'): return MCC ('m', 'i'); |
| 5751 | case MCC ('m', 'i'): return MCC ('p', 'l'); |
| 5752 | case MCC ('g', 'e'): return MCC ('l', 'e'); |
| 5753 | case MCC ('l', 't'): return MCC ('g', 't'); |
| 5754 | case MCC ('g', 't'): return MCC ('l', 't'); |
| 5755 | case MCC ('l', 'e'): return MCC ('g', 'e'); |
| 5756 | /* issue a warning for conditions we can not swap */ |
| 5757 | case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here |
| 5758 | case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem |
| 5759 | case MCC ('v', 'c'): |
| 5760 | case MCC ('v', 's'): |
| 5761 | default : |
| 5762 | as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"), |
| 5763 | (char) (cc >> 8), (char) (cc)); |
| 5764 | break; |
| 5765 | } |
| 5766 | return cc; |
| 5767 | } |
| 5768 | |
| 5769 | /* Reverse the sense of a condition. */ |
| 5770 | |
| 5771 | static int |
| 5772 | reverse_mri_condition (cc) |
| 5773 | int cc; |
| 5774 | { |
| 5775 | switch (cc) |
| 5776 | { |
| 5777 | case MCC ('h', 'i'): return MCC ('l', 's'); |
| 5778 | case MCC ('l', 's'): return MCC ('h', 'i'); |
| 5779 | /* <HS> is an alias for <CC> */ |
| 5780 | case MCC ('h', 's'): return MCC ('l', 'o'); |
| 5781 | case MCC ('c', 'c'): return MCC ('c', 's'); |
| 5782 | /* <LO> is an alias for <CS> */ |
| 5783 | case MCC ('l', 'o'): return MCC ('h', 's'); |
| 5784 | case MCC ('c', 's'): return MCC ('c', 'c'); |
| 5785 | case MCC ('n', 'e'): return MCC ('e', 'q'); |
| 5786 | case MCC ('e', 'q'): return MCC ('n', 'e'); |
| 5787 | case MCC ('v', 'c'): return MCC ('v', 's'); |
| 5788 | case MCC ('v', 's'): return MCC ('v', 'c'); |
| 5789 | case MCC ('p', 'l'): return MCC ('m', 'i'); |
| 5790 | case MCC ('m', 'i'): return MCC ('p', 'l'); |
| 5791 | case MCC ('g', 'e'): return MCC ('l', 't'); |
| 5792 | case MCC ('l', 't'): return MCC ('g', 'e'); |
| 5793 | case MCC ('g', 't'): return MCC ('l', 'e'); |
| 5794 | case MCC ('l', 'e'): return MCC ('g', 't'); |
| 5795 | } |
| 5796 | return cc; |
| 5797 | } |
| 5798 | |
| 5799 | /* Build an MRI structured control expression. This generates test |
| 5800 | and branch instructions. It goes to TRUELAB if the condition is |
| 5801 | true, and to FALSELAB if the condition is false. Exactly one of |
| 5802 | TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL |
| 5803 | is the size qualifier for the expression. EXTENT is the size to |
| 5804 | use for the branch. */ |
| 5805 | |
| 5806 | static void |
| 5807 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, |
| 5808 | rightstop, truelab, falselab, extent) |
| 5809 | int qual; |
| 5810 | int cc; |
| 5811 | char *leftstart; |
| 5812 | char *leftstop; |
| 5813 | char *rightstart; |
| 5814 | char *rightstop; |
| 5815 | const char *truelab; |
| 5816 | const char *falselab; |
| 5817 | int extent; |
| 5818 | { |
| 5819 | char *buf; |
| 5820 | char *s; |
| 5821 | |
| 5822 | if (leftstart != NULL) |
| 5823 | { |
| 5824 | struct m68k_op leftop, rightop; |
| 5825 | char c; |
| 5826 | |
| 5827 | /* Swap the compare operands, if necessary, to produce a legal |
| 5828 | m68k compare instruction. Comparing a register operand with |
| 5829 | a non-register operand requires the register to be on the |
| 5830 | right (cmp, cmpa). Comparing an immediate value with |
| 5831 | anything requires the immediate value to be on the left |
| 5832 | (cmpi). */ |
| 5833 | |
| 5834 | c = *leftstop; |
| 5835 | *leftstop = '\0'; |
| 5836 | (void) m68k_ip_op (leftstart, &leftop); |
| 5837 | *leftstop = c; |
| 5838 | |
| 5839 | c = *rightstop; |
| 5840 | *rightstop = '\0'; |
| 5841 | (void) m68k_ip_op (rightstart, &rightop); |
| 5842 | *rightstop = c; |
| 5843 | |
| 5844 | if (rightop.mode == IMMED |
| 5845 | || ((leftop.mode == DREG || leftop.mode == AREG) |
| 5846 | && (rightop.mode != DREG && rightop.mode != AREG))) |
| 5847 | { |
| 5848 | char *temp; |
| 5849 | |
| 5850 | /* Correct conditional handling: |
| 5851 | if #1 <lt> d0 then ;means if (1 < d0) |
| 5852 | ... |
| 5853 | endi |
| 5854 | |
| 5855 | should assemble to: |
| 5856 | |
| 5857 | cmp #1,d0 if we do *not* swap the operands |
| 5858 | bgt true we need the swapped condition! |
| 5859 | ble false |
| 5860 | true: |
| 5861 | ... |
| 5862 | false: |
| 5863 | */ |
| 5864 | temp = leftstart; |
| 5865 | leftstart = rightstart; |
| 5866 | rightstart = temp; |
| 5867 | temp = leftstop; |
| 5868 | leftstop = rightstop; |
| 5869 | rightstop = temp; |
| 5870 | } else { |
| 5871 | cc = swap_mri_condition (cc); |
| 5872 | } |
| 5873 | } |
| 5874 | |
| 5875 | if (truelab == NULL) |
| 5876 | { |
| 5877 | cc = reverse_mri_condition (cc); |
| 5878 | truelab = falselab; |
| 5879 | } |
| 5880 | |
| 5881 | if (leftstart != NULL) |
| 5882 | { |
| 5883 | buf = (char *) xmalloc (20 |
| 5884 | + (leftstop - leftstart) |
| 5885 | + (rightstop - rightstart)); |
| 5886 | s = buf; |
| 5887 | *s++ = 'c'; |
| 5888 | *s++ = 'm'; |
| 5889 | *s++ = 'p'; |
| 5890 | if (qual != '\0') |
| 5891 | *s++ = TOLOWER (qual); |
| 5892 | *s++ = ' '; |
| 5893 | memcpy (s, leftstart, leftstop - leftstart); |
| 5894 | s += leftstop - leftstart; |
| 5895 | *s++ = ','; |
| 5896 | memcpy (s, rightstart, rightstop - rightstart); |
| 5897 | s += rightstop - rightstart; |
| 5898 | *s = '\0'; |
| 5899 | mri_assemble (buf); |
| 5900 | free (buf); |
| 5901 | } |
| 5902 | |
| 5903 | buf = (char *) xmalloc (20 + strlen (truelab)); |
| 5904 | s = buf; |
| 5905 | *s++ = 'b'; |
| 5906 | *s++ = cc >> 8; |
| 5907 | *s++ = cc & 0xff; |
| 5908 | if (extent != '\0') |
| 5909 | *s++ = TOLOWER (extent); |
| 5910 | *s++ = ' '; |
| 5911 | strcpy (s, truelab); |
| 5912 | mri_assemble (buf); |
| 5913 | free (buf); |
| 5914 | } |
| 5915 | |
| 5916 | /* Parse an MRI structured control expression. This generates test |
| 5917 | and branch instructions. STOP is where the expression ends. It |
| 5918 | goes to TRUELAB if the condition is true, and to FALSELAB if the |
| 5919 | condition is false. Exactly one of TRUELAB and FALSELAB will be |
| 5920 | NULL, meaning to fall through. QUAL is the size qualifier for the |
| 5921 | expression. EXTENT is the size to use for the branch. */ |
| 5922 | |
| 5923 | static void |
| 5924 | parse_mri_control_expression (stop, qual, truelab, falselab, extent) |
| 5925 | char *stop; |
| 5926 | int qual; |
| 5927 | const char *truelab; |
| 5928 | const char *falselab; |
| 5929 | int extent; |
| 5930 | { |
| 5931 | int c; |
| 5932 | int cc; |
| 5933 | char *leftstart; |
| 5934 | char *leftstop; |
| 5935 | char *rightstart; |
| 5936 | char *rightstop; |
| 5937 | |
| 5938 | c = *stop; |
| 5939 | *stop = '\0'; |
| 5940 | |
| 5941 | if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, |
| 5942 | &rightstart, &rightstop)) |
| 5943 | { |
| 5944 | *stop = c; |
| 5945 | return; |
| 5946 | } |
| 5947 | |
| 5948 | if (strncasecmp (input_line_pointer, "AND", 3) == 0) |
| 5949 | { |
| 5950 | const char *flab; |
| 5951 | |
| 5952 | if (falselab != NULL) |
| 5953 | flab = falselab; |
| 5954 | else |
| 5955 | flab = mri_control_label (); |
| 5956 | |
| 5957 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, |
| 5958 | rightstop, (const char *) NULL, flab, extent); |
| 5959 | |
| 5960 | input_line_pointer += 3; |
| 5961 | if (*input_line_pointer != '.' |
| 5962 | || input_line_pointer[1] == '\0') |
| 5963 | qual = '\0'; |
| 5964 | else |
| 5965 | { |
| 5966 | qual = input_line_pointer[1]; |
| 5967 | input_line_pointer += 2; |
| 5968 | } |
| 5969 | |
| 5970 | if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, |
| 5971 | &rightstart, &rightstop)) |
| 5972 | { |
| 5973 | *stop = c; |
| 5974 | return; |
| 5975 | } |
| 5976 | |
| 5977 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, |
| 5978 | rightstop, truelab, falselab, extent); |
| 5979 | |
| 5980 | if (falselab == NULL) |
| 5981 | colon (flab); |
| 5982 | } |
| 5983 | else if (strncasecmp (input_line_pointer, "OR", 2) == 0) |
| 5984 | { |
| 5985 | const char *tlab; |
| 5986 | |
| 5987 | if (truelab != NULL) |
| 5988 | tlab = truelab; |
| 5989 | else |
| 5990 | tlab = mri_control_label (); |
| 5991 | |
| 5992 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, |
| 5993 | rightstop, tlab, (const char *) NULL, extent); |
| 5994 | |
| 5995 | input_line_pointer += 2; |
| 5996 | if (*input_line_pointer != '.' |
| 5997 | || input_line_pointer[1] == '\0') |
| 5998 | qual = '\0'; |
| 5999 | else |
| 6000 | { |
| 6001 | qual = input_line_pointer[1]; |
| 6002 | input_line_pointer += 2; |
| 6003 | } |
| 6004 | |
| 6005 | if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, |
| 6006 | &rightstart, &rightstop)) |
| 6007 | { |
| 6008 | *stop = c; |
| 6009 | return; |
| 6010 | } |
| 6011 | |
| 6012 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, |
| 6013 | rightstop, truelab, falselab, extent); |
| 6014 | |
| 6015 | if (truelab == NULL) |
| 6016 | colon (tlab); |
| 6017 | } |
| 6018 | else |
| 6019 | { |
| 6020 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, |
| 6021 | rightstop, truelab, falselab, extent); |
| 6022 | } |
| 6023 | |
| 6024 | *stop = c; |
| 6025 | if (input_line_pointer != stop) |
| 6026 | as_bad (_("syntax error in structured control directive")); |
| 6027 | } |
| 6028 | |
| 6029 | /* Handle the MRI IF pseudo-op. This may be a structured control |
| 6030 | directive, or it may be a regular assembler conditional, depending |
| 6031 | on its operands. */ |
| 6032 | |
| 6033 | static void |
| 6034 | s_mri_if (qual) |
| 6035 | int qual; |
| 6036 | { |
| 6037 | char *s; |
| 6038 | int c; |
| 6039 | struct mri_control_info *n; |
| 6040 | |
| 6041 | /* A structured control directive must end with THEN with an |
| 6042 | optional qualifier. */ |
| 6043 | s = input_line_pointer; |
| 6044 | /* We only accept '*' as introduction of comments if preceded by white space |
| 6045 | or at first column of a line (I think this can't actually happen here?) |
| 6046 | This is important when assembling: |
| 6047 | if d0 <ne> 12(a0,d0*2) then |
| 6048 | if d0 <ne> #CONST*20 then */ |
| 6049 | while ( ! ( is_end_of_line[(unsigned char) *s] |
| 6050 | || ( flag_mri |
| 6051 | && *s == '*' |
| 6052 | && ( s == input_line_pointer |
| 6053 | || *(s-1) == ' ' |
| 6054 | || *(s-1) == '\t')))) |
| 6055 | ++s; |
| 6056 | --s; |
| 6057 | while (s > input_line_pointer && (*s == ' ' || *s == '\t')) |
| 6058 | --s; |
| 6059 | |
| 6060 | if (s - input_line_pointer > 1 |
| 6061 | && s[-1] == '.') |
| 6062 | s -= 2; |
| 6063 | |
| 6064 | if (s - input_line_pointer < 3 |
| 6065 | || strncasecmp (s - 3, "THEN", 4) != 0) |
| 6066 | { |
| 6067 | if (qual != '\0') |
| 6068 | { |
| 6069 | as_bad (_("missing then")); |
| 6070 | ignore_rest_of_line (); |
| 6071 | return; |
| 6072 | } |
| 6073 | |
| 6074 | /* It's a conditional. */ |
| 6075 | s_if (O_ne); |
| 6076 | return; |
| 6077 | } |
| 6078 | |
| 6079 | /* Since this might be a conditional if, this pseudo-op will be |
| 6080 | called even if we are supported to be ignoring input. Double |
| 6081 | check now. Clobber *input_line_pointer so that ignore_input |
| 6082 | thinks that this is not a special pseudo-op. */ |
| 6083 | c = *input_line_pointer; |
| 6084 | *input_line_pointer = 0; |
| 6085 | if (ignore_input ()) |
| 6086 | { |
| 6087 | *input_line_pointer = c; |
| 6088 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) |
| 6089 | ++input_line_pointer; |
| 6090 | demand_empty_rest_of_line (); |
| 6091 | return; |
| 6092 | } |
| 6093 | *input_line_pointer = c; |
| 6094 | |
| 6095 | n = push_mri_control (mri_if); |
| 6096 | |
| 6097 | parse_mri_control_expression (s - 3, qual, (const char *) NULL, |
| 6098 | n->next, s[1] == '.' ? s[2] : '\0'); |
| 6099 | |
| 6100 | if (s[1] == '.') |
| 6101 | input_line_pointer = s + 3; |
| 6102 | else |
| 6103 | input_line_pointer = s + 1; |
| 6104 | |
| 6105 | if (flag_mri) |
| 6106 | { |
| 6107 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) |
| 6108 | ++input_line_pointer; |
| 6109 | } |
| 6110 | |
| 6111 | demand_empty_rest_of_line (); |
| 6112 | } |
| 6113 | |
| 6114 | /* Handle the MRI else pseudo-op. If we are currently doing an MRI |
| 6115 | structured IF, associate the ELSE with the IF. Otherwise, assume |
| 6116 | it is a conditional else. */ |
| 6117 | |
| 6118 | static void |
| 6119 | s_mri_else (qual) |
| 6120 | int qual; |
| 6121 | { |
| 6122 | int c; |
| 6123 | char *buf; |
| 6124 | char q[2]; |
| 6125 | |
| 6126 | if (qual == '\0' |
| 6127 | && (mri_control_stack == NULL |
| 6128 | || mri_control_stack->type != mri_if |
| 6129 | || mri_control_stack->else_seen)) |
| 6130 | { |
| 6131 | s_else (0); |
| 6132 | return; |
| 6133 | } |
| 6134 | |
| 6135 | c = *input_line_pointer; |
| 6136 | *input_line_pointer = 0; |
| 6137 | if (ignore_input ()) |
| 6138 | { |
| 6139 | *input_line_pointer = c; |
| 6140 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) |
| 6141 | ++input_line_pointer; |
| 6142 | demand_empty_rest_of_line (); |
| 6143 | return; |
| 6144 | } |
| 6145 | *input_line_pointer = c; |
| 6146 | |
| 6147 | if (mri_control_stack == NULL |
| 6148 | || mri_control_stack->type != mri_if |
| 6149 | || mri_control_stack->else_seen) |
| 6150 | { |
| 6151 | as_bad (_("else without matching if")); |
| 6152 | ignore_rest_of_line (); |
| 6153 | return; |
| 6154 | } |
| 6155 | |
| 6156 | mri_control_stack->else_seen = 1; |
| 6157 | |
| 6158 | buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom)); |
| 6159 | q[0] = TOLOWER (qual); |
| 6160 | q[1] = '\0'; |
| 6161 | sprintf (buf, "bra%s %s", q, mri_control_stack->bottom); |
| 6162 | mri_assemble (buf); |
| 6163 | free (buf); |
| 6164 | |
| 6165 | colon (mri_control_stack->next); |
| 6166 | |
| 6167 | if (flag_mri) |
| 6168 | { |
| 6169 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) |
| 6170 | ++input_line_pointer; |
| 6171 | } |
| 6172 | |
| 6173 | demand_empty_rest_of_line (); |
| 6174 | } |
| 6175 | |
| 6176 | /* Handle the MRI ENDI pseudo-op. */ |
| 6177 | |
| 6178 | static void |
| 6179 | s_mri_endi (ignore) |
| 6180 | int ignore ATTRIBUTE_UNUSED; |
| 6181 | { |
| 6182 | if (mri_control_stack == NULL |
| 6183 | || mri_control_stack->type != mri_if) |
| 6184 | { |
| 6185 | as_bad (_("endi without matching if")); |
| 6186 | ignore_rest_of_line (); |
| 6187 | return; |
| 6188 | } |
| 6189 | |
| 6190 | /* ignore_input will not return true for ENDI, so we don't need to |
| 6191 | worry about checking it again here. */ |
| 6192 | |
| 6193 | if (! mri_control_stack->else_seen) |
| 6194 | colon (mri_control_stack->next); |
| 6195 | colon (mri_control_stack->bottom); |
| 6196 | |
| 6197 | pop_mri_control (); |
| 6198 | |
| 6199 | if (flag_mri) |
| 6200 | { |
| 6201 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) |
| 6202 | ++input_line_pointer; |
| 6203 | } |
| 6204 | |
| 6205 | demand_empty_rest_of_line (); |
| 6206 | } |
| 6207 | |
| 6208 | /* Handle the MRI BREAK pseudo-op. */ |
| 6209 | |
| 6210 | static void |
| 6211 | s_mri_break (extent) |
| 6212 | int extent; |
| 6213 | { |
| 6214 | struct mri_control_info *n; |
| 6215 | char *buf; |
| 6216 | char ex[2]; |
| 6217 | |
| 6218 | n = mri_control_stack; |
| 6219 | while (n != NULL |
| 6220 | && n->type != mri_for |
| 6221 | && n->type != mri_repeat |
| 6222 | && n->type != mri_while) |
| 6223 | n = n->outer; |
| 6224 | if (n == NULL) |
| 6225 | { |
| 6226 | as_bad (_("break outside of structured loop")); |
| 6227 | ignore_rest_of_line (); |
| 6228 | return; |
| 6229 | } |
| 6230 | |
| 6231 | buf = (char *) xmalloc (20 + strlen (n->bottom)); |
| 6232 | ex[0] = TOLOWER (extent); |
| 6233 | ex[1] = '\0'; |
| 6234 | sprintf (buf, "bra%s %s", ex, n->bottom); |
| 6235 | mri_assemble (buf); |
| 6236 | free (buf); |
| 6237 | |
| 6238 | if (flag_mri) |
| 6239 | { |
| 6240 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) |
| 6241 | ++input_line_pointer; |
| 6242 | } |
| 6243 | |
| 6244 | demand_empty_rest_of_line (); |
| 6245 | } |
| 6246 | |
| 6247 | /* Handle the MRI NEXT pseudo-op. */ |
| 6248 | |
| 6249 | static void |
| 6250 | s_mri_next (extent) |
| 6251 | int extent; |
| 6252 | { |
| 6253 | struct mri_control_info *n; |
| 6254 | char *buf; |
| 6255 | char ex[2]; |
| 6256 | |
| 6257 | n = mri_control_stack; |
| 6258 | while (n != NULL |
| 6259 | && n->type != mri_for |
| 6260 | && n->type != mri_repeat |
| 6261 | && n->type != mri_while) |
| 6262 | n = n->outer; |
| 6263 | if (n == NULL) |
| 6264 | { |
| 6265 | as_bad (_("next outside of structured loop")); |
| 6266 | ignore_rest_of_line (); |
| 6267 | return; |
| 6268 | } |
| 6269 | |
| 6270 | buf = (char *) xmalloc (20 + strlen (n->next)); |
| 6271 | ex[0] = TOLOWER (extent); |
| 6272 | ex[1] = '\0'; |
| 6273 | sprintf (buf, "bra%s %s", ex, n->next); |
| 6274 | mri_assemble (buf); |
| 6275 | free (buf); |
| 6276 | |
| 6277 | if (flag_mri) |
| 6278 | { |
| 6279 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) |
| 6280 | ++input_line_pointer; |
| 6281 | } |
| 6282 | |
| 6283 | demand_empty_rest_of_line (); |
| 6284 | } |
| 6285 | |
| 6286 | /* Handle the MRI FOR pseudo-op. */ |
| 6287 | |
| 6288 | static void |
| 6289 | s_mri_for (qual) |
| 6290 | int qual; |
| 6291 | { |
| 6292 | const char *varstart, *varstop; |
| 6293 | const char *initstart, *initstop; |
| 6294 | const char *endstart, *endstop; |
| 6295 | const char *bystart, *bystop; |
| 6296 | int up; |
| 6297 | int by; |
| 6298 | int extent; |
| 6299 | struct mri_control_info *n; |
| 6300 | char *buf; |
| 6301 | char *s; |
| 6302 | char ex[2]; |
| 6303 | |
| 6304 | /* The syntax is |
| 6305 | FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e |
| 6306 | */ |
| 6307 | |
| 6308 | SKIP_WHITESPACE (); |
| 6309 | varstart = input_line_pointer; |
| 6310 | |
| 6311 | /* Look for the '='. */ |
| 6312 | while (! is_end_of_line[(unsigned char) *input_line_pointer] |
| 6313 | && *input_line_pointer != '=') |
| 6314 | ++input_line_pointer; |
| 6315 | if (*input_line_pointer != '=') |
| 6316 | { |
| 6317 | as_bad (_("missing =")); |
| 6318 | ignore_rest_of_line (); |
| 6319 | return; |
| 6320 | } |
| 6321 | |
| 6322 | varstop = input_line_pointer; |
| 6323 | if (varstop > varstart |
| 6324 | && (varstop[-1] == ' ' || varstop[-1] == '\t')) |
| 6325 | --varstop; |
| 6326 | |
| 6327 | ++input_line_pointer; |
| 6328 | |
| 6329 | initstart = input_line_pointer; |
| 6330 | |
| 6331 | /* Look for TO or DOWNTO. */ |
| 6332 | up = 1; |
| 6333 | initstop = NULL; |
| 6334 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) |
| 6335 | { |
| 6336 | if (strncasecmp (input_line_pointer, "TO", 2) == 0 |
| 6337 | && ! is_part_of_name (input_line_pointer[2])) |
| 6338 | { |
| 6339 | initstop = input_line_pointer; |
| 6340 | input_line_pointer += 2; |
| 6341 | break; |
| 6342 | } |
| 6343 | if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0 |
| 6344 | && ! is_part_of_name (input_line_pointer[6])) |
| 6345 | { |
| 6346 | initstop = input_line_pointer; |
| 6347 | up = 0; |
| 6348 | input_line_pointer += 6; |
| 6349 | break; |
| 6350 | } |
| 6351 | ++input_line_pointer; |
| 6352 | } |
| 6353 | if (initstop == NULL) |
| 6354 | { |
| 6355 | as_bad (_("missing to or downto")); |
| 6356 | ignore_rest_of_line (); |
| 6357 | return; |
| 6358 | } |
| 6359 | if (initstop > initstart |
| 6360 | && (initstop[-1] == ' ' || initstop[-1] == '\t')) |
| 6361 | --initstop; |
| 6362 | |
| 6363 | SKIP_WHITESPACE (); |
| 6364 | endstart = input_line_pointer; |
| 6365 | |
| 6366 | /* Look for BY or DO. */ |
| 6367 | by = 0; |
| 6368 | endstop = NULL; |
| 6369 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) |
| 6370 | { |
| 6371 | if (strncasecmp (input_line_pointer, "BY", 2) == 0 |
| 6372 | && ! is_part_of_name (input_line_pointer[2])) |
| 6373 | { |
| 6374 | endstop = input_line_pointer; |
| 6375 | by = 1; |
| 6376 | input_line_pointer += 2; |
| 6377 | break; |
| 6378 | } |
| 6379 | if (strncasecmp (input_line_pointer, "DO", 2) == 0 |
| 6380 | && (input_line_pointer[2] == '.' |
| 6381 | || ! is_part_of_name (input_line_pointer[2]))) |
| 6382 | { |
| 6383 | endstop = input_line_pointer; |
| 6384 | input_line_pointer += 2; |
| 6385 | break; |
| 6386 | } |
| 6387 | ++input_line_pointer; |
| 6388 | } |
| 6389 | if (endstop == NULL) |
| 6390 | { |
| 6391 | as_bad (_("missing do")); |
| 6392 | ignore_rest_of_line (); |
| 6393 | return; |
| 6394 | } |
| 6395 | if (endstop > endstart |
| 6396 | && (endstop[-1] == ' ' || endstop[-1] == '\t')) |
| 6397 | --endstop; |
| 6398 | |
| 6399 | if (! by) |
| 6400 | { |
| 6401 | bystart = "#1"; |
| 6402 | bystop = bystart + 2; |
| 6403 | } |
| 6404 | else |
| 6405 | { |
| 6406 | SKIP_WHITESPACE (); |
| 6407 | bystart = input_line_pointer; |
| 6408 | |
| 6409 | /* Look for DO. */ |
| 6410 | bystop = NULL; |
| 6411 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) |
| 6412 | { |
| 6413 | if (strncasecmp (input_line_pointer, "DO", 2) == 0 |
| 6414 | && (input_line_pointer[2] == '.' |
| 6415 | || ! is_part_of_name (input_line_pointer[2]))) |
| 6416 | { |
| 6417 | bystop = input_line_pointer; |
| 6418 | input_line_pointer += 2; |
| 6419 | break; |
| 6420 | } |
| 6421 | ++input_line_pointer; |
| 6422 | } |
| 6423 | if (bystop == NULL) |
| 6424 | { |
| 6425 | as_bad (_("missing do")); |
| 6426 | ignore_rest_of_line (); |
| 6427 | return; |
| 6428 | } |
| 6429 | if (bystop > bystart |
| 6430 | && (bystop[-1] == ' ' || bystop[-1] == '\t')) |
| 6431 | --bystop; |
| 6432 | } |
| 6433 | |
| 6434 | if (*input_line_pointer != '.') |
| 6435 | extent = '\0'; |
| 6436 | else |
| 6437 | { |
| 6438 | extent = input_line_pointer[1]; |
| 6439 | input_line_pointer += 2; |
| 6440 | } |
| 6441 | |
| 6442 | /* We have fully parsed the FOR operands. Now build the loop. */ |
| 6443 | |
| 6444 | n = push_mri_control (mri_for); |
| 6445 | |
| 6446 | buf = (char *) xmalloc (50 + (input_line_pointer - varstart)); |
| 6447 | |
| 6448 | /* move init,var */ |
| 6449 | s = buf; |
| 6450 | *s++ = 'm'; |
| 6451 | *s++ = 'o'; |
| 6452 | *s++ = 'v'; |
| 6453 | *s++ = 'e'; |
| 6454 | if (qual != '\0') |
| 6455 | *s++ = TOLOWER (qual); |
| 6456 | *s++ = ' '; |
| 6457 | memcpy (s, initstart, initstop - initstart); |
| 6458 | s += initstop - initstart; |
| 6459 | *s++ = ','; |
| 6460 | memcpy (s, varstart, varstop - varstart); |
| 6461 | s += varstop - varstart; |
| 6462 | *s = '\0'; |
| 6463 | mri_assemble (buf); |
| 6464 | |
| 6465 | colon (n->top); |
| 6466 | |
| 6467 | /* cmp end,var */ |
| 6468 | s = buf; |
| 6469 | *s++ = 'c'; |
| 6470 | *s++ = 'm'; |
| 6471 | *s++ = 'p'; |
| 6472 | if (qual != '\0') |
| 6473 | *s++ = TOLOWER (qual); |
| 6474 | *s++ = ' '; |
| 6475 | memcpy (s, endstart, endstop - endstart); |
| 6476 | s += endstop - endstart; |
| 6477 | *s++ = ','; |
| 6478 | memcpy (s, varstart, varstop - varstart); |
| 6479 | s += varstop - varstart; |
| 6480 | *s = '\0'; |
| 6481 | mri_assemble (buf); |
| 6482 | |
| 6483 | /* bcc bottom */ |
| 6484 | ex[0] = TOLOWER (extent); |
| 6485 | ex[1] = '\0'; |
| 6486 | if (up) |
| 6487 | sprintf (buf, "blt%s %s", ex, n->bottom); |
| 6488 | else |
| 6489 | sprintf (buf, "bgt%s %s", ex, n->bottom); |
| 6490 | mri_assemble (buf); |
| 6491 | |
| 6492 | /* Put together the add or sub instruction used by ENDF. */ |
| 6493 | s = buf; |
| 6494 | if (up) |
| 6495 | strcpy (s, "add"); |
| 6496 | else |
| 6497 | strcpy (s, "sub"); |
| 6498 | s += 3; |
| 6499 | if (qual != '\0') |
| 6500 | *s++ = TOLOWER (qual); |
| 6501 | *s++ = ' '; |
| 6502 | memcpy (s, bystart, bystop - bystart); |
| 6503 | s += bystop - bystart; |
| 6504 | *s++ = ','; |
| 6505 | memcpy (s, varstart, varstop - varstart); |
| 6506 | s += varstop - varstart; |
| 6507 | *s = '\0'; |
| 6508 | n->incr = buf; |
| 6509 | |
| 6510 | if (flag_mri) |
| 6511 | { |
| 6512 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) |
| 6513 | ++input_line_pointer; |
| 6514 | } |
| 6515 | |
| 6516 | demand_empty_rest_of_line (); |
| 6517 | } |
| 6518 | |
| 6519 | /* Handle the MRI ENDF pseudo-op. */ |
| 6520 | |
| 6521 | static void |
| 6522 | s_mri_endf (ignore) |
| 6523 | int ignore ATTRIBUTE_UNUSED; |
| 6524 | { |
| 6525 | if (mri_control_stack == NULL |
| 6526 | || mri_control_stack->type != mri_for) |
| 6527 | { |
| 6528 | as_bad (_("endf without for")); |
| 6529 | ignore_rest_of_line (); |
| 6530 | return; |
| 6531 | } |
| 6532 | |
| 6533 | colon (mri_control_stack->next); |
| 6534 | |
| 6535 | mri_assemble (mri_control_stack->incr); |
| 6536 | |
| 6537 | sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top); |
| 6538 | mri_assemble (mri_control_stack->incr); |
| 6539 | |
| 6540 | free (mri_control_stack->incr); |
| 6541 | |
| 6542 | colon (mri_control_stack->bottom); |
| 6543 | |
| 6544 | pop_mri_control (); |
| 6545 | |
| 6546 | if (flag_mri) |
| 6547 | { |
| 6548 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) |
| 6549 | ++input_line_pointer; |
| 6550 | } |
| 6551 | |
| 6552 | demand_empty_rest_of_line (); |
| 6553 | } |
| 6554 | |
| 6555 | /* Handle the MRI REPEAT pseudo-op. */ |
| 6556 | |
| 6557 | static void |
| 6558 | s_mri_repeat (ignore) |
| 6559 | int ignore ATTRIBUTE_UNUSED; |
| 6560 | { |
| 6561 | struct mri_control_info *n; |
| 6562 | |
| 6563 | n = push_mri_control (mri_repeat); |
| 6564 | colon (n->top); |
| 6565 | if (flag_mri) |
| 6566 | { |
| 6567 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) |
| 6568 | ++input_line_pointer; |
| 6569 | } |
| 6570 | demand_empty_rest_of_line (); |
| 6571 | } |
| 6572 | |
| 6573 | /* Handle the MRI UNTIL pseudo-op. */ |
| 6574 | |
| 6575 | static void |
| 6576 | s_mri_until (qual) |
| 6577 | int qual; |
| 6578 | { |
| 6579 | char *s; |
| 6580 | |
| 6581 | if (mri_control_stack == NULL |
| 6582 | || mri_control_stack->type != mri_repeat) |
| 6583 | { |
| 6584 | as_bad (_("until without repeat")); |
| 6585 | ignore_rest_of_line (); |
| 6586 | return; |
| 6587 | } |
| 6588 | |
| 6589 | colon (mri_control_stack->next); |
| 6590 | |
| 6591 | for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++) |
| 6592 | ; |
| 6593 | |
| 6594 | parse_mri_control_expression (s, qual, (const char *) NULL, |
| 6595 | mri_control_stack->top, '\0'); |
| 6596 | |
| 6597 | colon (mri_control_stack->bottom); |
| 6598 | |
| 6599 | input_line_pointer = s; |
| 6600 | |
| 6601 | pop_mri_control (); |
| 6602 | |
| 6603 | if (flag_mri) |
| 6604 | { |
| 6605 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) |
| 6606 | ++input_line_pointer; |
| 6607 | } |
| 6608 | |
| 6609 | demand_empty_rest_of_line (); |
| 6610 | } |
| 6611 | |
| 6612 | /* Handle the MRI WHILE pseudo-op. */ |
| 6613 | |
| 6614 | static void |
| 6615 | s_mri_while (qual) |
| 6616 | int qual; |
| 6617 | { |
| 6618 | char *s; |
| 6619 | |
| 6620 | struct mri_control_info *n; |
| 6621 | |
| 6622 | s = input_line_pointer; |
| 6623 | /* We only accept '*' as introduction of comments if preceded by white space |
| 6624 | or at first column of a line (I think this can't actually happen here?) |
| 6625 | This is important when assembling: |
| 6626 | while d0 <ne> 12(a0,d0*2) do |
| 6627 | while d0 <ne> #CONST*20 do */ |
| 6628 | while ( ! ( is_end_of_line[(unsigned char) *s] |
| 6629 | || ( flag_mri |
| 6630 | && *s == '*' |
| 6631 | && ( s == input_line_pointer |
| 6632 | || *(s-1) == ' ' |
| 6633 | || *(s-1) == '\t')))) |
| 6634 | s++; |
| 6635 | --s; |
| 6636 | while (*s == ' ' || *s == '\t') |
| 6637 | --s; |
| 6638 | if (s - input_line_pointer > 1 |
| 6639 | && s[-1] == '.') |
| 6640 | s -= 2; |
| 6641 | if (s - input_line_pointer < 2 |
| 6642 | || strncasecmp (s - 1, "DO", 2) != 0) |
| 6643 | { |
| 6644 | as_bad (_("missing do")); |
| 6645 | ignore_rest_of_line (); |
| 6646 | return; |
| 6647 | } |
| 6648 | |
| 6649 | n = push_mri_control (mri_while); |
| 6650 | |
| 6651 | colon (n->next); |
| 6652 | |
| 6653 | parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom, |
| 6654 | s[1] == '.' ? s[2] : '\0'); |
| 6655 | |
| 6656 | input_line_pointer = s + 1; |
| 6657 | if (*input_line_pointer == '.') |
| 6658 | input_line_pointer += 2; |
| 6659 | |
| 6660 | if (flag_mri) |
| 6661 | { |
| 6662 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) |
| 6663 | ++input_line_pointer; |
| 6664 | } |
| 6665 | |
| 6666 | demand_empty_rest_of_line (); |
| 6667 | } |
| 6668 | |
| 6669 | /* Handle the MRI ENDW pseudo-op. */ |
| 6670 | |
| 6671 | static void |
| 6672 | s_mri_endw (ignore) |
| 6673 | int ignore ATTRIBUTE_UNUSED; |
| 6674 | { |
| 6675 | char *buf; |
| 6676 | |
| 6677 | if (mri_control_stack == NULL |
| 6678 | || mri_control_stack->type != mri_while) |
| 6679 | { |
| 6680 | as_bad (_("endw without while")); |
| 6681 | ignore_rest_of_line (); |
| 6682 | return; |
| 6683 | } |
| 6684 | |
| 6685 | buf = (char *) xmalloc (20 + strlen (mri_control_stack->next)); |
| 6686 | sprintf (buf, "bra %s", mri_control_stack->next); |
| 6687 | mri_assemble (buf); |
| 6688 | free (buf); |
| 6689 | |
| 6690 | colon (mri_control_stack->bottom); |
| 6691 | |
| 6692 | pop_mri_control (); |
| 6693 | |
| 6694 | if (flag_mri) |
| 6695 | { |
| 6696 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) |
| 6697 | ++input_line_pointer; |
| 6698 | } |
| 6699 | |
| 6700 | demand_empty_rest_of_line (); |
| 6701 | } |
| 6702 | \f |
| 6703 | /* |
| 6704 | * md_parse_option |
| 6705 | * Invocation line includes a switch not recognized by the base assembler. |
| 6706 | * See if it's a processor-specific option. These are: |
| 6707 | * |
| 6708 | * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040 |
| 6709 | * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851 |
| 6710 | * Select the architecture. Instructions or features not |
| 6711 | * supported by the selected architecture cause fatal |
| 6712 | * errors. More than one may be specified. The default is |
| 6713 | * -m68020 -m68851 -m68881. Note that -m68008 is a synonym |
| 6714 | * for -m68000, and -m68882 is a synonym for -m68881. |
| 6715 | * -[A]m[c]no-68851, -[A]m[c]no-68881 |
| 6716 | * Don't accept 688?1 instructions. (The "c" is kind of silly, |
| 6717 | * so don't use or document it, but that's the way the parsing |
| 6718 | * works). |
| 6719 | * |
| 6720 | * -pic Indicates PIC. |
| 6721 | * -k Indicates PIC. (Sun 3 only.) |
| 6722 | * --pcrel Never turn PC-relative branches into absolute jumps. |
| 6723 | * |
| 6724 | * --bitwise-or |
| 6725 | * Permit `|' to be used in expressions. |
| 6726 | * |
| 6727 | */ |
| 6728 | |
| 6729 | #ifdef OBJ_ELF |
| 6730 | CONST char *md_shortopts = "lSA:m:kQ:V"; |
| 6731 | #else |
| 6732 | CONST char *md_shortopts = "lSA:m:k"; |
| 6733 | #endif |
| 6734 | |
| 6735 | struct option md_longopts[] = { |
| 6736 | #define OPTION_PIC (OPTION_MD_BASE) |
| 6737 | {"pic", no_argument, NULL, OPTION_PIC}, |
| 6738 | #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1) |
| 6739 | {"register-prefix-optional", no_argument, NULL, |
| 6740 | OPTION_REGISTER_PREFIX_OPTIONAL}, |
| 6741 | #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2) |
| 6742 | {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR}, |
| 6743 | #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3) |
| 6744 | {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16}, |
| 6745 | #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4) |
| 6746 | {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32}, |
| 6747 | #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5) |
| 6748 | {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16}, |
| 6749 | #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6) |
| 6750 | {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32}, |
| 6751 | #define OPTION_PCREL (OPTION_MD_BASE + 7) |
| 6752 | {"pcrel", no_argument, NULL, OPTION_PCREL}, |
| 6753 | {NULL, no_argument, NULL, 0} |
| 6754 | }; |
| 6755 | size_t md_longopts_size = sizeof (md_longopts); |
| 6756 | |
| 6757 | int |
| 6758 | md_parse_option (c, arg) |
| 6759 | int c; |
| 6760 | char *arg; |
| 6761 | { |
| 6762 | switch (c) |
| 6763 | { |
| 6764 | case 'l': /* -l means keep external to 2 bit offset |
| 6765 | rather than 16 bit one */ |
| 6766 | flag_short_refs = 1; |
| 6767 | break; |
| 6768 | |
| 6769 | case 'S': /* -S means that jbsr's always turn into |
| 6770 | jsr's. */ |
| 6771 | flag_long_jumps = 1; |
| 6772 | break; |
| 6773 | |
| 6774 | case OPTION_PCREL: /* --pcrel means never turn PC-relative |
| 6775 | branches into absolute jumps. */ |
| 6776 | flag_keep_pcrel = 1; |
| 6777 | break; |
| 6778 | |
| 6779 | case 'A': |
| 6780 | if (*arg == 'm') |
| 6781 | arg++; |
| 6782 | /* intentional fall-through */ |
| 6783 | case 'm': |
| 6784 | |
| 6785 | if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-') |
| 6786 | { |
| 6787 | int i; |
| 6788 | unsigned long arch; |
| 6789 | const char *oarg = arg; |
| 6790 | |
| 6791 | arg += 3; |
| 6792 | if (*arg == 'm') |
| 6793 | { |
| 6794 | arg++; |
| 6795 | if (arg[0] == 'c' && arg[1] == '6') |
| 6796 | arg++; |
| 6797 | } |
| 6798 | for (i = 0; i < n_archs; i++) |
| 6799 | if (!strcmp (arg, archs[i].name)) |
| 6800 | break; |
| 6801 | if (i == n_archs) |
| 6802 | { |
| 6803 | unknown: |
| 6804 | as_bad (_("unrecognized option `%s'"), oarg); |
| 6805 | return 0; |
| 6806 | } |
| 6807 | arch = archs[i].arch; |
| 6808 | if (arch == m68881) |
| 6809 | no_68881 = 1; |
| 6810 | else if (arch == m68851) |
| 6811 | no_68851 = 1; |
| 6812 | else |
| 6813 | goto unknown; |
| 6814 | } |
| 6815 | else |
| 6816 | { |
| 6817 | int i; |
| 6818 | |
| 6819 | if (arg[0] == 'c' && arg[1] == '6') |
| 6820 | arg++; |
| 6821 | |
| 6822 | for (i = 0; i < n_archs; i++) |
| 6823 | if (!strcmp (arg, archs[i].name)) |
| 6824 | { |
| 6825 | unsigned long arch = archs[i].arch; |
| 6826 | if (cpu_of_arch (arch)) |
| 6827 | /* It's a cpu spec. */ |
| 6828 | { |
| 6829 | current_architecture &= ~m68000up; |
| 6830 | current_architecture |= arch; |
| 6831 | } |
| 6832 | else if (arch == m68881) |
| 6833 | { |
| 6834 | current_architecture |= m68881; |
| 6835 | no_68881 = 0; |
| 6836 | } |
| 6837 | else if (arch == m68851) |
| 6838 | { |
| 6839 | current_architecture |= m68851; |
| 6840 | no_68851 = 0; |
| 6841 | } |
| 6842 | else |
| 6843 | /* ??? */ |
| 6844 | abort (); |
| 6845 | break; |
| 6846 | } |
| 6847 | if (i == n_archs) |
| 6848 | { |
| 6849 | as_bad (_("unrecognized architecture specification `%s'"), arg); |
| 6850 | return 0; |
| 6851 | } |
| 6852 | } |
| 6853 | break; |
| 6854 | |
| 6855 | case OPTION_PIC: |
| 6856 | case 'k': |
| 6857 | flag_want_pic = 1; |
| 6858 | break; /* -pic, Position Independent Code */ |
| 6859 | |
| 6860 | case OPTION_REGISTER_PREFIX_OPTIONAL: |
| 6861 | flag_reg_prefix_optional = 1; |
| 6862 | reg_prefix_optional_seen = 1; |
| 6863 | break; |
| 6864 | |
| 6865 | /* -V: SVR4 argument to print version ID. */ |
| 6866 | case 'V': |
| 6867 | print_version_id (); |
| 6868 | break; |
| 6869 | |
| 6870 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
| 6871 | should be emitted or not. FIXME: Not implemented. */ |
| 6872 | case 'Q': |
| 6873 | break; |
| 6874 | |
| 6875 | case OPTION_BITWISE_OR: |
| 6876 | { |
| 6877 | char *n, *t; |
| 6878 | const char *s; |
| 6879 | |
| 6880 | n = (char *) xmalloc (strlen (m68k_comment_chars) + 1); |
| 6881 | t = n; |
| 6882 | for (s = m68k_comment_chars; *s != '\0'; s++) |
| 6883 | if (*s != '|') |
| 6884 | *t++ = *s; |
| 6885 | *t = '\0'; |
| 6886 | m68k_comment_chars = n; |
| 6887 | } |
| 6888 | break; |
| 6889 | |
| 6890 | case OPTION_BASE_SIZE_DEFAULT_16: |
| 6891 | m68k_index_width_default = SIZE_WORD; |
| 6892 | break; |
| 6893 | |
| 6894 | case OPTION_BASE_SIZE_DEFAULT_32: |
| 6895 | m68k_index_width_default = SIZE_LONG; |
| 6896 | break; |
| 6897 | |
| 6898 | case OPTION_DISP_SIZE_DEFAULT_16: |
| 6899 | m68k_rel32 = 0; |
| 6900 | m68k_rel32_from_cmdline = 1; |
| 6901 | break; |
| 6902 | |
| 6903 | case OPTION_DISP_SIZE_DEFAULT_32: |
| 6904 | m68k_rel32 = 1; |
| 6905 | m68k_rel32_from_cmdline = 1; |
| 6906 | break; |
| 6907 | |
| 6908 | default: |
| 6909 | return 0; |
| 6910 | } |
| 6911 | |
| 6912 | return 1; |
| 6913 | } |
| 6914 | |
| 6915 | void |
| 6916 | md_show_usage (stream) |
| 6917 | FILE *stream; |
| 6918 | { |
| 6919 | const char *default_cpu = TARGET_CPU; |
| 6920 | int default_arch, i; |
| 6921 | |
| 6922 | /* Get the canonical name for the default target CPU. */ |
| 6923 | if (*default_cpu == 'm') |
| 6924 | default_cpu++; |
| 6925 | for (i = 0; i < n_archs; i++) |
| 6926 | { |
| 6927 | if (strcasecmp (default_cpu, archs[i].name) == 0) |
| 6928 | { |
| 6929 | default_arch = archs[i].arch; |
| 6930 | for (i = 0; i < n_archs; i++) |
| 6931 | { |
| 6932 | if (archs[i].arch == default_arch |
| 6933 | && !archs[i].alias) |
| 6934 | { |
| 6935 | default_cpu = archs[i].name; |
| 6936 | break; |
| 6937 | } |
| 6938 | } |
| 6939 | } |
| 6940 | } |
| 6941 | |
| 6942 | fprintf (stream, _("\ |
| 6943 | 680X0 options:\n\ |
| 6944 | -l use 1 word for refs to undefined symbols [default 2]\n\ |
| 6945 | -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\ |
| 6946 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\ |
| 6947 | -m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m5307 | -m5407\n\ |
| 6948 | specify variant of 680X0 architecture [default %s]\n\ |
| 6949 | -m68881 | -m68882 | -mno-68881 | -mno-68882\n\ |
| 6950 | target has/lacks floating-point coprocessor\n\ |
| 6951 | [default yes for 68020, 68030, and cpu32]\n"), |
| 6952 | default_cpu); |
| 6953 | fprintf (stream, _("\ |
| 6954 | -m68851 | -mno-68851\n\ |
| 6955 | target has/lacks memory-management unit coprocessor\n\ |
| 6956 | [default yes for 68020 and up]\n\ |
| 6957 | -pic, -k generate position independent code\n\ |
| 6958 | -S turn jbsr into jsr\n\ |
| 6959 | --pcrel never turn PC-relative branches into absolute jumps\n\ |
| 6960 | --register-prefix-optional\n\ |
| 6961 | recognize register names without prefix character\n\ |
| 6962 | --bitwise-or do not treat `|' as a comment character\n")); |
| 6963 | fprintf (stream, _("\ |
| 6964 | --base-size-default-16 base reg without size is 16 bits\n\ |
| 6965 | --base-size-default-32 base reg without size is 32 bits (default)\n\ |
| 6966 | --disp-size-default-16 displacement with unknown size is 16 bits\n\ |
| 6967 | --disp-size-default-32 displacement with unknown size is 32 bits (default)\n")); |
| 6968 | } |
| 6969 | \f |
| 6970 | #ifdef TEST2 |
| 6971 | |
| 6972 | /* TEST2: Test md_assemble() */ |
| 6973 | /* Warning, this routine probably doesn't work anymore */ |
| 6974 | |
| 6975 | main () |
| 6976 | { |
| 6977 | struct m68k_it the_ins; |
| 6978 | char buf[120]; |
| 6979 | char *cp; |
| 6980 | int n; |
| 6981 | |
| 6982 | m68k_ip_begin (); |
| 6983 | for (;;) |
| 6984 | { |
| 6985 | if (!gets (buf) || !*buf) |
| 6986 | break; |
| 6987 | if (buf[0] == '|' || buf[1] == '.') |
| 6988 | continue; |
| 6989 | for (cp = buf; *cp; cp++) |
| 6990 | if (*cp == '\t') |
| 6991 | *cp = ' '; |
| 6992 | if (is_label (buf)) |
| 6993 | continue; |
| 6994 | memset (&the_ins, '\0', sizeof (the_ins)); |
| 6995 | m68k_ip (&the_ins, buf); |
| 6996 | if (the_ins.error) |
| 6997 | { |
| 6998 | printf (_("Error %s in %s\n"), the_ins.error, buf); |
| 6999 | } |
| 7000 | else |
| 7001 | { |
| 7002 | printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args); |
| 7003 | for (n = 0; n < the_ins.numo; n++) |
| 7004 | printf (" 0x%x", the_ins.opcode[n] & 0xffff); |
| 7005 | printf (" "); |
| 7006 | print_the_insn (&the_ins.opcode[0], stdout); |
| 7007 | (void) putchar ('\n'); |
| 7008 | } |
| 7009 | for (n = 0; n < strlen (the_ins.args) / 2; n++) |
| 7010 | { |
| 7011 | if (the_ins.operands[n].error) |
| 7012 | { |
| 7013 | printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf); |
| 7014 | continue; |
| 7015 | } |
| 7016 | printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg); |
| 7017 | if (the_ins.operands[n].b_const) |
| 7018 | printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const); |
| 7019 | printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul); |
| 7020 | if (the_ins.operands[n].b_iadd) |
| 7021 | printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd); |
| 7022 | (void) putchar ('\n'); |
| 7023 | } |
| 7024 | } |
| 7025 | m68k_ip_end (); |
| 7026 | return 0; |
| 7027 | } |
| 7028 | |
| 7029 | is_label (str) |
| 7030 | char *str; |
| 7031 | { |
| 7032 | while (*str == ' ') |
| 7033 | str++; |
| 7034 | while (*str && *str != ' ') |
| 7035 | str++; |
| 7036 | if (str[-1] == ':' || str[1] == '=') |
| 7037 | return 1; |
| 7038 | return 0; |
| 7039 | } |
| 7040 | |
| 7041 | #endif |
| 7042 | |
| 7043 | /* Possible states for relaxation: |
| 7044 | |
| 7045 | 0 0 branch offset byte (bra, etc) |
| 7046 | 0 1 word |
| 7047 | 0 2 long |
| 7048 | |
| 7049 | 1 0 indexed offsets byte a0@(32,d4:w:1) etc |
| 7050 | 1 1 word |
| 7051 | 1 2 long |
| 7052 | |
| 7053 | 2 0 two-offset index word-word a0@(32,d4)@(45) etc |
| 7054 | 2 1 word-long |
| 7055 | 2 2 long-word |
| 7056 | 2 3 long-long |
| 7057 | |
| 7058 | */ |
| 7059 | |
| 7060 | /* We have no need to default values of symbols. */ |
| 7061 | |
| 7062 | symbolS * |
| 7063 | md_undefined_symbol (name) |
| 7064 | char *name ATTRIBUTE_UNUSED; |
| 7065 | { |
| 7066 | return 0; |
| 7067 | } |
| 7068 | |
| 7069 | /* Round up a section size to the appropriate boundary. */ |
| 7070 | valueT |
| 7071 | md_section_align (segment, size) |
| 7072 | segT segment ATTRIBUTE_UNUSED; |
| 7073 | valueT size; |
| 7074 | { |
| 7075 | #ifdef OBJ_AOUT |
| 7076 | #ifdef BFD_ASSEMBLER |
| 7077 | /* For a.out, force the section size to be aligned. If we don't do |
| 7078 | this, BFD will align it for us, but it will not write out the |
| 7079 | final bytes of the section. This may be a bug in BFD, but it is |
| 7080 | easier to fix it here since that is how the other a.out targets |
| 7081 | work. */ |
| 7082 | int align; |
| 7083 | |
| 7084 | align = bfd_get_section_alignment (stdoutput, segment); |
| 7085 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); |
| 7086 | #endif |
| 7087 | #endif |
| 7088 | |
| 7089 | return size; |
| 7090 | } |
| 7091 | |
| 7092 | /* Exactly what point is a PC-relative offset relative TO? |
| 7093 | On the 68k, it is relative to the address of the first extension |
| 7094 | word. The difference between the addresses of the offset and the |
| 7095 | first extension word is stored in fx_pcrel_adjust. */ |
| 7096 | long |
| 7097 | md_pcrel_from (fixP) |
| 7098 | fixS *fixP; |
| 7099 | { |
| 7100 | int adjust; |
| 7101 | |
| 7102 | /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly |
| 7103 | sign extend the value here. */ |
| 7104 | adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80; |
| 7105 | if (adjust == 64) |
| 7106 | adjust = -1; |
| 7107 | return fixP->fx_where + fixP->fx_frag->fr_address - adjust; |
| 7108 | } |
| 7109 | |
| 7110 | #ifndef BFD_ASSEMBLER |
| 7111 | #ifdef OBJ_COFF |
| 7112 | |
| 7113 | void |
| 7114 | tc_coff_symbol_emit_hook (ignore) |
| 7115 | symbolS *ignore ATTRIBUTE_UNUSED; |
| 7116 | { |
| 7117 | } |
| 7118 | |
| 7119 | int |
| 7120 | tc_coff_sizemachdep (frag) |
| 7121 | fragS *frag; |
| 7122 | { |
| 7123 | switch (frag->fr_subtype & 0x3) |
| 7124 | { |
| 7125 | case BYTE: |
| 7126 | return 1; |
| 7127 | case SHORT: |
| 7128 | return 2; |
| 7129 | case LONG: |
| 7130 | return 4; |
| 7131 | default: |
| 7132 | abort (); |
| 7133 | return 0; |
| 7134 | } |
| 7135 | } |
| 7136 | |
| 7137 | #endif |
| 7138 | #endif |
| 7139 | #ifdef OBJ_ELF |
| 7140 | void m68k_elf_final_processing() |
| 7141 | { |
| 7142 | /* Set file-specific flags if this is a cpu32 processor */ |
| 7143 | if (cpu_of_arch (current_architecture) & cpu32) |
| 7144 | elf_elfheader (stdoutput)->e_flags |= EF_CPU32; |
| 7145 | else if ((cpu_of_arch (current_architecture) & m68000up) |
| 7146 | && !(cpu_of_arch (current_architecture) & m68020up)) |
| 7147 | elf_elfheader (stdoutput)->e_flags |= EF_M68000; |
| 7148 | } |
| 7149 | #endif |