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[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
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1/* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 1995 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
19 02111-1307, USA. */
20
21#include <ctype.h>
22#define NO_RELOC 0
23#include "as.h"
24#include "obstack.h"
25#include "subsegs.h"
26
27#include "opcode/m68k.h"
28#include "m68k-parse.h"
29
30/* This array holds the chars that always start a comment. If the
31 pre-processor is disabled, these aren't very useful */
32#if defined (OBJ_ELF) || defined (TE_DELTA)
33CONST char comment_chars[] = "|#";
34#else
35CONST char comment_chars[] = "|";
36#endif
37
38/* This array holds the chars that only start a comment at the beginning of
39 a line. If the line seems to have the form '# 123 filename'
40 .line and .file directives will appear in the pre-processed output */
41/* Note that input_file.c hand checks for '#' at the beginning of the
42 first line of the input file. This is because the compiler outputs
43 #NO_APP at the beginning of its output. */
44/* Also note that comments like this one will always work. */
45CONST char line_comment_chars[] = "#";
46
47CONST char line_separator_chars[] = "";
48
49/* Chars that can be used to separate mant from exp in floating point nums */
50CONST char EXP_CHARS[] = "eE";
51
52/* Chars that mean this number is a floating point constant, as
53 in "0f12.456" or "0d1.2345e12". */
54
55CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
56
57/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
58 changed in read.c . Ideally it shouldn't have to know about it at all,
59 but nothing is ideal around here. */
60
61const int md_reloc_size = 8; /* Size of relocation record */
62
63/* Are we trying to generate PIC code? If so, absolute references
64 ought to be made into linkage table references or pc-relative
65 references. */
66int flag_want_pic;
67
68static int flag_short_refs; /* -l option */
69static int flag_long_jumps; /* -S option */
70
71#ifdef REGISTER_PREFIX_OPTIONAL
72int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
73#else
74int flag_reg_prefix_optional;
75#endif
76
77/* The floating point coprocessor to use by default. */
78static enum m68k_register m68k_float_copnum = COP1;
79
80/* If this is non-zero, then references to number(%pc) will be taken
81 to refer to number, rather than to %pc + number. */
82static int m68k_abspcadd;
83
84/* If this is non-zero, then the quick forms of the move, add, and sub
85 instructions are used when possible. */
86static int m68k_quick = 1;
87
88/* If this is non-zero, then if the size is not specified for a base
89 or outer displacement, the assembler assumes that the size should
90 be 32 bits. */
91static int m68k_rel32 = 1;
92
93/* Its an arbitrary name: This means I don't approve of it */
94/* See flames below */
95static struct obstack robyn;
96
97#define TAB(x,y) (((x)<<2)+(y))
98#define TABTYPE(xy) ((xy) >> 2)
99#define BYTE 0
100#define SHORT 1
101#define LONG 2
102#define SZ_UNDEF 3
103#undef BRANCH
104/* Case `g' except when BCC68000 is applicable. */
105#define ABRANCH 1
106/* Coprocessor branches. */
107#define FBRANCH 2
108/* Mode 7.2 -- program counter indirect with (16-bit) displacement,
109 supported on all cpus. Widens to 32-bit absolute. */
110#define PCREL 3
111/* For inserting an extra jmp instruction with long offset on 68000,
112 for expanding conditional branches. (Not bsr or bra.) Since the
113 68000 doesn't support 32-bit displacements for conditional
114 branches, we fake it by reversing the condition and branching
115 around a jmp with an absolute long operand. */
116#define BCC68000 4
117/* For the DBcc "instructions". If the displacement requires 32 bits,
118 the branch-around-a-jump game is played here too. */
119#define DBCC 5
120/* Not currently used? */
121#define PCLEA 6
122/* Mode AINDX (apc-relative) using PC, with variable target, might fit
123 in 16 or 8 bits. */
124#define PCINDEX 7
125
126struct m68k_incant
127 {
128 const char *m_operands;
129 unsigned long m_opcode;
130 short m_opnum;
131 short m_codenum;
132 int m_arch;
133 struct m68k_incant *m_next;
134 };
135
136#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
137#define gettwo(x) (((x)->m_opcode)&0xffff)
138
139static const enum m68k_register m68000_control_regs[] = { 0 };
140static const enum m68k_register m68010_control_regs[] = {
141 SFC, DFC, USP, VBR,
142 0
143};
144static const enum m68k_register m68020_control_regs[] = {
145 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
146 0
147};
148static const enum m68k_register m68040_control_regs[] = {
149 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
150 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
151 0
152};
153static const enum m68k_register m68060_control_regs[] = {
154 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
155 USP, VBR, URP, SRP, PCR,
156 0
157};
158#define cpu32_control_regs m68010_control_regs
159
160static const enum m68k_register *control_regs;
161
162/* internal form of a 68020 instruction */
163struct m68k_it
164{
165 const char *error;
166 const char *args; /* list of opcode info */
167 int numargs;
168
169 int numo; /* Number of shorts in opcode */
170 short opcode[11];
171
172 struct m68k_op operands[6];
173
174 int nexp; /* number of exprs in use */
175 struct m68k_exp exprs[4];
176
177 int nfrag; /* Number of frags we have to produce */
178 struct
179 {
180 int fragoff; /* Where in the current opcode the frag ends */
181 symbolS *fadd;
182 long foff;
183 int fragty;
184 }
185 fragb[4];
186
187 int nrel; /* Num of reloc strucs in use */
188 struct
189 {
190 int n;
191 expressionS exp;
192 char wid;
193 char pcrel;
194 /* In a pc relative address the difference between the address
195 of the offset and the address that the offset is relative
196 to. This depends on the addressing mode. Basically this
197 is the value to put in the offset field to address the
198 first byte of the offset, without regarding the special
199 significance of some values (in the branch instruction, for
200 example). */
201 int pcrel_fix;
202 }
203 reloc[5]; /* Five is enough??? */
204};
205
206#define cpu_of_arch(x) ((x) & m68000up)
207#define float_of_arch(x) ((x) & mfloat)
208#define mmu_of_arch(x) ((x) & mmmu)
209
210static struct m68k_it the_ins; /* the instruction being assembled */
211
212#define op(ex) ((ex)->exp.X_op)
213#define adds(ex) ((ex)->exp.X_add_symbol)
214#define subs(ex) ((ex)->exp.X_op_symbol)
215#define offs(ex) ((ex)->exp.X_add_number)
216
217/* Macros for adding things to the m68k_it struct */
218
219#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
220
221/* Like addword, but goes BEFORE general operands */
222static void
223insop (w, opcode)
224 int w;
225 struct m68k_incant *opcode;
226{
227 int z;
228 for(z=the_ins.numo;z>opcode->m_codenum;--z)
229 the_ins.opcode[z]=the_ins.opcode[z-1];
230 for(z=0;z<the_ins.nrel;z++)
231 the_ins.reloc[z].n+=2;
232 for (z = 0; z < the_ins.nfrag; z++)
233 the_ins.fragb[z].fragoff++;
234 the_ins.opcode[opcode->m_codenum]=w;
235 the_ins.numo++;
236}
237
238/* The numo+1 kludge is so we can hit the low order byte of the prev word.
239 Blecch. */
240static void
241add_fix (width, exp, pc_rel, pc_fix)
242 char width;
243 struct m68k_exp *exp;
244 int pc_rel;
245 int pc_fix;
246{
247 the_ins.reloc[the_ins.nrel].n = (((width)=='B')
248 ? (the_ins.numo*2-1)
249 : (((width)=='b')
250 ? (the_ins.numo*2+1)
251 : (the_ins.numo*2)));
252 the_ins.reloc[the_ins.nrel].exp = exp->exp;
253 the_ins.reloc[the_ins.nrel].wid = width;
254 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
255 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
256}
257
258/* Cause an extra frag to be generated here, inserting up to 10 bytes
259 (that value is chosen in the frag_var call in md_assemble). TYPE
260 is the subtype of the frag to be generated; its primary type is
261 rs_machine_dependent.
262
263 The TYPE parameter is also used by md_convert_frag_1 and
264 md_estimate_size_before_relax. The appropriate type of fixup will
265 be emitted by md_convert_frag_1.
266
267 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
268static void
269add_frag(add,off,type)
270 symbolS *add;
271 long off;
272 int type;
273{
274 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
275 the_ins.fragb[the_ins.nfrag].fadd=add;
276 the_ins.fragb[the_ins.nfrag].foff=off;
277 the_ins.fragb[the_ins.nfrag++].fragty=type;
278}
279
280#define isvar(ex) \
281 (op (ex) != O_constant && op (ex) != O_big)
282
283static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
284static int get_num PARAMS ((struct m68k_exp *exp, int ok));
285static int reverse_16_bits PARAMS ((int in));
286static int reverse_8_bits PARAMS ((int in));
287static void install_gen_operand PARAMS ((int mode, int val));
288static void install_operand PARAMS ((int mode, int val));
289static void s_bss PARAMS ((int));
290static void s_data1 PARAMS ((int));
291static void s_data2 PARAMS ((int));
292static void s_even PARAMS ((int));
293static void s_proc PARAMS ((int));
294static void mri_chip PARAMS ((void));
295static void s_chip PARAMS ((int));
296static void s_fopt PARAMS ((int));
297static void s_opt PARAMS ((int));
298static void s_reg PARAMS ((int));
299static void s_restore PARAMS ((int));
300static void s_save PARAMS ((int));
301static void s_mri_if PARAMS ((int));
302static void s_mri_else PARAMS ((int));
303static void s_mri_endi PARAMS ((int));
304static void s_mri_break PARAMS ((int));
305static void s_mri_next PARAMS ((int));
306static void s_mri_for PARAMS ((int));
307static void s_mri_endf PARAMS ((int));
308static void s_mri_repeat PARAMS ((int));
309static void s_mri_until PARAMS ((int));
310static void s_mri_while PARAMS ((int));
311static void s_mri_endw PARAMS ((int));
312
313static int current_architecture;
314
315struct m68k_cpu {
316 unsigned long arch;
317 const char *name;
318};
319
320static const struct m68k_cpu archs[] = {
321 { m68000, "68000" },
322 { m68010, "68010" },
323 { m68020, "68020" },
324 { m68030, "68030" },
325 { m68040, "68040" },
326 { m68060, "68060" },
327 { cpu32, "cpu32" },
328 { m68881, "68881" },
329 { m68851, "68851" },
330 /* Aliases (effectively, so far as gas is concerned) for the above
331 cpus. */
332 { m68020, "68k" },
333 { m68000, "68302" },
334 { m68000, "68008" },
335 { m68000, "68ec000" },
336 { m68000, "68hc000" },
337 { m68000, "68hc001" },
338 { m68020, "68ec020" },
339 { m68030, "68ec030" },
340 { m68040, "68ec040" },
341 { cpu32, "68330" },
342 { cpu32, "68331" },
343 { cpu32, "68332" },
344 { cpu32, "68333" },
345 { cpu32, "68340" },
346 { cpu32, "68360" },
347 { m68881, "68882" },
348};
349
350static const int n_archs = sizeof (archs) / sizeof (archs[0]);
351
352/* BCC68000 is for patching in an extra jmp instruction for long offsets
353 on the 68000. The 68000 doesn't support long branches with branchs */
354
355/* This table desribes how you change sizes for the various types of variable
356 size expressions. This version only supports two kinds. */
357
358/* Note that calls to frag_var need to specify the maximum expansion
359 needed; this is currently 10 bytes for DBCC. */
360
361/* The fields are:
362 How far Forward this mode will reach:
363 How far Backward this mode will reach:
364 How many bytes this mode will add to the size of the frag
365 Which mode to go to if the offset won't fit in this one
366 */
367relax_typeS md_relax_table[] =
368{
369 {1, 1, 0, 0}, /* First entries aren't used */
370 {1, 1, 0, 0}, /* For no good reason except */
371 {1, 1, 0, 0}, /* that the VAX doesn't either */
372 {1, 1, 0, 0},
373
374 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
375 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
376 {0, 0, 4, 0},
377 {1, 1, 0, 0},
378
379 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
380 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
381 {0, 0, 4, 0},
382 {1, 1, 0, 0},
383
384 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
385 {(32767), (-32768), 2, TAB (PCREL, LONG)},
386 {0, 0, 4, 0},
387 {1, 1, 0, 0},
388
389 {(127), (-128), 0, TAB (BCC68000, SHORT)},
390 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
391 {0, 0, 6, 0}, /* jmp long space */
392 {1, 1, 0, 0},
393
394 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
395 {(32767), (-32768), 2, TAB (DBCC, LONG)},
396 {0, 0, 10, 0}, /* bra/jmp long space */
397 {1, 1, 0, 0},
398
399 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
400 {32767, -32768, 2, TAB (PCLEA, LONG)},
401 {0, 0, 6, 0},
402 {1, 1, 0, 0},
403
404 /* For, e.g., jmp pcrel indexed. */
405 {125, -130, 0, TAB (PCINDEX, SHORT)},
406 {32765, -32770, 2, TAB (PCINDEX, LONG)},
407 {0, 0, 4, 0},
408 {1, 1, 0, 0},
409};
410
411/* These are the machine dependent pseudo-ops. These are included so
412 the assembler can work on the output from the SUN C compiler, which
413 generates these.
414 */
415
416/* This table describes all the machine specific pseudo-ops the assembler
417 has to support. The fields are:
418 pseudo-op name without dot
419 function to call to execute this pseudo-op
420 Integer arg to pass to the function
421 */
422CONST pseudo_typeS md_pseudo_table[] =
423{
424 {"data1", s_data1, 0},
425 {"data2", s_data2, 0},
426 {"bss", s_bss, 0},
427 {"even", s_even, 0},
428 {"skip", s_space, 0},
429 {"proc", s_proc, 0},
430#ifdef TE_SUN3
431 {"align", s_align_bytes, 0},
432#endif
433#ifdef OBJ_ELF
434 {"swbeg", s_ignore, 0},
435#endif
436
437 /* The following pseudo-ops are supported for MRI compatibility. */
438 {"chip", s_chip, 0},
439 {"comline", s_space, 1},
440 {"fopt", s_fopt, 0},
441 {"mask2", s_ignore, 0},
442 {"opt", s_opt, 0},
443 {"reg", s_reg, 0},
444 {"restore", s_restore, 0},
445 {"save", s_save, 0},
446
447 {"if", s_mri_if, 0},
448 {"if.b", s_mri_if, 'b'},
449 {"if.w", s_mri_if, 'w'},
450 {"if.l", s_mri_if, 'l'},
451 {"else", s_mri_else, 0},
452 {"else.s", s_mri_else, 's'},
453 {"else.l", s_mri_else, 'l'},
454 {"endi", s_mri_endi, 0},
455 {"break", s_mri_break, 0},
456 {"break.s", s_mri_break, 's'},
457 {"break.l", s_mri_break, 'l'},
458 {"next", s_mri_next, 0},
459 {"next.s", s_mri_next, 's'},
460 {"next.l", s_mri_next, 'l'},
461 {"for", s_mri_for, 0},
462 {"for.b", s_mri_for, 'b'},
463 {"for.w", s_mri_for, 'w'},
464 {"for.l", s_mri_for, 'l'},
465 {"endf", s_mri_endf, 0},
466 {"repeat", s_mri_repeat, 0},
467 {"until", s_mri_until, 0},
468 {"until.b", s_mri_until, 'b'},
469 {"until.w", s_mri_until, 'w'},
470 {"until.l", s_mri_until, 'l'},
471 {"while", s_mri_while, 0},
472 {"while.b", s_mri_while, 'b'},
473 {"while.w", s_mri_while, 'w'},
474 {"while.l", s_mri_while, 'l'},
475 {"endw", s_mri_endw, 0},
476
477 {0, 0, 0}
478};
479
480
481/* The mote pseudo ops are put into the opcode table, since they
482 don't start with a . they look like opcodes to gas.
483 */
484extern void obj_coff_section ();
485
486CONST pseudo_typeS mote_pseudo_table[] =
487{
488
489 {"dcl", cons, 4},
490 {"dc", cons, 2},
491 {"dcw", cons, 2},
492 {"dcb", cons, 1},
493
494 {"dsl", s_space, 4},
495 {"ds", s_space, 2},
496 {"dsw", s_space, 2},
497 {"dsb", s_space, 1},
498
499 {"xdef", s_globl, 0},
500 {"align", s_align_ptwo, 0},
501#ifdef M68KCOFF
502 {"sect", obj_coff_section, 0},
503 {"section", obj_coff_section, 0},
504#endif
505 {0, 0, 0}
506};
507
508#define issbyte(x) ((x)>=-128 && (x)<=127)
509#define isubyte(x) ((x)>=0 && (x)<=255)
510#define issword(x) ((x)>=-32768 && (x)<=32767)
511#define isuword(x) ((x)>=0 && (x)<=65535)
512
513#define isbyte(x) ((x)>= -255 && (x)<=255)
514#define isword(x) ((x)>=-32768 && (x)<=65535)
515#define islong(x) (1)
516
517extern char *input_line_pointer;
518
519static char mklower_table[256];
520#define mklower(c) (mklower_table[(unsigned char)(c)])
521static char notend_table[256];
522static char alt_notend_table[256];
523#define notend(s) \
524 (! (notend_table[(unsigned char) *s] \
525 || (*s == ':' \
526 && alt_notend_table[(unsigned char) s[1]])))
527
528#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
529
530#ifdef NO_PCREL_RELOCS
531
532int
533make_pcrel_absolute(fixP, add_number)
534 fixS *fixP;
535 long *add_number;
536{
537 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
538
539 /* rewrite the PC relative instructions to absolute address ones.
540 * these are rumoured to be faster, and the apollo linker refuses
541 * to deal with the PC relative relocations.
542 */
543 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
544 {
545 opcode[0] = 0x4e;
546 opcode[1] = 0xf9;
547 }
548 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
549 {
550 opcode[0] = 0x4e;
551 opcode[1] = 0xb9;
552 }
553 else
554 as_fatal ("Unknown PC relative instruction");
555 *add_number -= 4;
556 return 0;
557}
558
559#endif /* NO_PCREL_RELOCS */
560
561short
562tc_coff_fix2rtype (fixP)
563 fixS *fixP;
564{
565#ifdef NO_PCREL_RELOCS
566 know (fixP->fx_pcrel == 0);
567 return (fixP->fx_size == 1 ? R_RELBYTE
568 : fixP->fx_size == 2 ? R_DIR16
569 : R_DIR32);
570#else
571 return (fixP->fx_pcrel ?
572 (fixP->fx_size == 1 ? R_PCRBYTE :
573 fixP->fx_size == 2 ? R_PCRWORD :
574 R_PCRLONG) :
575 (fixP->fx_size == 1 ? R_RELBYTE :
576 fixP->fx_size == 2 ? R_RELWORD :
577 R_RELLONG));
578#endif
579}
580
581#endif
582
583#ifdef BFD_ASSEMBLER
584
585arelent *
586tc_gen_reloc (section, fixp)
587 asection *section;
588 fixS *fixp;
589{
590 arelent *reloc;
591 bfd_reloc_code_real_type code;
592
593#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
594 switch (F (fixp->fx_size, fixp->fx_pcrel))
595 {
596#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
597 MAP (1, 0, BFD_RELOC_8);
598 MAP (2, 0, BFD_RELOC_16);
599 MAP (4, 0, BFD_RELOC_32);
600 MAP (1, 1, BFD_RELOC_8_PCREL);
601 MAP (2, 1, BFD_RELOC_16_PCREL);
602 MAP (4, 1, BFD_RELOC_32_PCREL);
603 default:
604 abort ();
605 }
606
607 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
608 assert (reloc != 0);
609 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
610 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
611 if (fixp->fx_pcrel)
612 reloc->addend = fixp->fx_addnumber;
613 else
614 reloc->addend = 0;
615
616 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
617 assert (reloc->howto != 0);
618
619 return reloc;
620}
621
622#endif /* BFD_ASSEMBLER */
623
624/* Handle of the OPCODE hash table. NULL means any use before
625 m68k_ip_begin() will crash. */
626static struct hash_control *op_hash;
627\f
628/* Assemble an m68k instruction. */
629
630void
631m68k_ip (instring)
632 char *instring;
633{
634 register char *p;
635 register struct m68k_op *opP;
636 register struct m68k_incant *opcode;
637 register const char *s;
638 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
639 char *pdot, *pdotmove;
640 enum m68k_size siz1, siz2;
641 char c;
642 int losing;
643 int opsfound;
644 char *crack_operand ();
645 LITTLENUM_TYPE words[6];
646 LITTLENUM_TYPE *wordp;
647 unsigned long ok_arch = 0;
648
649 if (*instring == ' ')
650 instring++; /* skip leading whitespace */
651
652 /* Scan up to end of operation-code, which MUST end in end-of-string
653 or exactly 1 space. */
654 pdot = 0;
655 for (p = instring; *p != '\0'; p++)
656 {
657 if (*p == ' ')
658 break;
659 if (*p == '.')
660 pdot = p;
661 }
662
663 if (p == instring)
664 {
665 the_ins.error = "No operator";
666 return;
667 }
668
669 /* p now points to the end of the opcode name, probably whitespace.
670 Make sure the name is null terminated by clobbering the
671 whitespace, look it up in the hash table, then fix it back.
672 Remove a dot, first, since the opcode tables have none. */
673 if (pdot != NULL)
674 {
675 for (pdotmove = pdot; pdotmove < p; pdotmove++)
676 *pdotmove = pdotmove[1];
677 p--;
678 }
679
680 c = *p;
681 *p = '\0';
682 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
683 *p = c;
684
685 if (pdot != NULL)
686 {
687 for (pdotmove = p; pdotmove > pdot; pdotmove--)
688 *pdotmove = pdotmove[-1];
689 *pdot = '.';
690 ++p;
691 }
692
693 if (opcode == NULL)
694 {
695 the_ins.error = "Unknown operator";
696 return;
697 }
698
699 /* found a legitimate opcode, start matching operands */
700 while (*p == ' ')
701 ++p;
702
703 if (opcode->m_operands == 0)
704 {
705 char *old = input_line_pointer;
706 *old = '\n';
707 input_line_pointer = p;
708 /* Ahh - it's a motorola style psuedo op */
709 mote_pseudo_table[opcode->m_opnum].poc_handler
710 (mote_pseudo_table[opcode->m_opnum].poc_val);
711 input_line_pointer = old;
712 *old = 0;
713
714 return;
715 }
716
717 if (flag_mri && opcode->m_opnum == 0)
718 {
719 /* In MRI mode, random garbage is allowed after an instruction
720 which accepts no operands. */
721 the_ins.args = opcode->m_operands;
722 the_ins.numargs = opcode->m_opnum;
723 the_ins.numo = opcode->m_codenum;
724 the_ins.opcode[0] = getone (opcode);
725 the_ins.opcode[1] = gettwo (opcode);
726 return;
727 }
728
729 for (opP = &the_ins.operands[0]; *p; opP++)
730 {
731 p = crack_operand (p, opP);
732
733 if (opP->error)
734 {
735 the_ins.error = opP->error;
736 return;
737 }
738 }
739
740 opsfound = opP - &the_ins.operands[0];
741
742 /* This ugly hack is to support the floating pt opcodes in their
743 standard form. Essentially, we fake a first enty of type COP#1 */
744 if (opcode->m_operands[0] == 'I')
745 {
746 int n;
747
748 for (n = opsfound; n > 0; --n)
749 the_ins.operands[n] = the_ins.operands[n - 1];
750
751 memset ((char *) (&the_ins.operands[0]), '\0',
752 sizeof (the_ins.operands[0]));
753 the_ins.operands[0].mode = CONTROL;
754 the_ins.operands[0].reg = m68k_float_copnum;
755 opsfound++;
756 }
757
758 /* We've got the operands. Find an opcode that'll accept them */
759 for (losing = 0;;)
760 {
761 /* If we didn't get the right number of ops, or we have no
762 common model with this pattern then reject this pattern. */
763
764 if (opsfound != opcode->m_opnum
765 || ((opcode->m_arch & current_architecture) == 0))
766 {
767 ++losing;
768 ok_arch |= opcode->m_arch;
769 }
770 else
771 {
772 for (s = opcode->m_operands, opP = &the_ins.operands[0];
773 *s && !losing;
774 s += 2, opP++)
775 {
776 /* Warning: this switch is huge! */
777 /* I've tried to organize the cases into this order:
778 non-alpha first, then alpha by letter. Lower-case
779 goes directly before uppercase counterpart. */
780 /* Code with multiple case ...: gets sorted by the lowest
781 case ... it belongs to. I hope this makes sense. */
782 switch (*s)
783 {
784 case '!':
785 switch (opP->mode)
786 {
787 case IMMED:
788 case DREG:
789 case AREG:
790 case FPREG:
791 case CONTROL:
792 case AINC:
793 case ADEC:
794 case REGLST:
795 losing++;
796 break;
797 default:
798 break;
799 }
800 break;
801
802 case '`':
803 switch (opP->mode)
804 {
805 case IMMED:
806 case DREG:
807 case AREG:
808 case FPREG:
809 case CONTROL:
810 case AINC:
811 case REGLST:
812 case AINDR:
813 losing++;
814 break;
815 default:
816 break;
817 }
818 break;
819
820 case '#':
821 if (opP->mode != IMMED)
822 losing++;
823 else if (s[1] == 'b'
824 && ! isvar (&opP->disp)
825 && (opP->disp.exp.X_op != O_constant
826 || ! isbyte (opP->disp.exp.X_add_number)))
827 losing++;
828 else if (s[1] == 'w'
829 && ! isvar (&opP->disp)
830 && (opP->disp.exp.X_op != O_constant
831 || ! isword (opP->disp.exp.X_add_number)))
832 losing++;
833 break;
834
835 case '^':
836 case 'T':
837 if (opP->mode != IMMED)
838 losing++;
839 break;
840
841 case '$':
842 if (opP->mode == AREG
843 || opP->mode == CONTROL
844 || opP->mode == FPREG
845 || opP->mode == IMMED
846 || opP->mode == REGLST
847 || (opP->mode != ABSL
848 && (opP->reg == PC
849 || opP->reg == ZPC)))
850 losing++;
851 break;
852
853 case '%':
854 if (opP->mode == CONTROL
855 || opP->mode == FPREG
856 || opP->mode == REGLST
857 || (opP->mode != ABSL
858 && opP->mode != IMMED
859 && (opP->reg == PC
860 || opP->reg == ZPC)))
861 losing++;
862 break;
863
864 case '&':
865 switch (opP->mode)
866 {
867 case DREG:
868 case AREG:
869 case FPREG:
870 case CONTROL:
871 case IMMED:
872 case AINC:
873 case ADEC:
874 case REGLST:
875 losing++;
876 break;
877 case ABSL:
878 break;
879 default:
880 if (opP->reg == PC
881 || opP->reg == ZPC)
882 losing++;
883 break;
884 }
885 break;
886
887 case '*':
888 if (opP->mode == CONTROL
889 || opP->mode == FPREG
890 || opP->mode == REGLST)
891 losing++;
892 break;
893
894 case '+':
895 if (opP->mode != AINC)
896 losing++;
897 break;
898
899 case '-':
900 if (opP->mode != ADEC)
901 losing++;
902 break;
903
904 case '/':
905 switch (opP->mode)
906 {
907 case AREG:
908 case CONTROL:
909 case FPREG:
910 case AINC:
911 case ADEC:
912 case IMMED:
913 case REGLST:
914 losing++;
915 break;
916 default:
917 break;
918 }
919 break;
920
921 case ';':
922 switch (opP->mode)
923 {
924 case AREG:
925 case CONTROL:
926 case FPREG:
927 case REGLST:
928 losing++;
929 break;
930 default:
931 break;
932 }
933 break;
934
935 case '?':
936 switch (opP->mode)
937 {
938 case AREG:
939 case CONTROL:
940 case FPREG:
941 case AINC:
942 case ADEC:
943 case IMMED:
944 case REGLST:
945 losing++;
946 break;
947 case ABSL:
948 break;
949 default:
950 if (opP->reg == PC || opP->reg == ZPC)
951 losing++;
952 break;
953 }
954 break;
955
956 case '@':
957 switch (opP->mode)
958 {
959 case AREG:
960 case CONTROL:
961 case FPREG:
962 case IMMED:
963 case REGLST:
964 losing++;
965 break;
966 default:
967 break;
968 }
969 break;
970
971 case '~': /* For now! (JF FOO is this right?) */
972 switch (opP->mode)
973 {
974 case DREG:
975 case AREG:
976 case CONTROL:
977 case FPREG:
978 case IMMED:
979 case REGLST:
980 losing++;
981 break;
982 case ABSL:
983 break;
984 default:
985 if (opP->reg == PC
986 || opP->reg == ZPC)
987 losing++;
988 break;
989 }
990 break;
991
992 case '3':
993 if (opP->mode != CONTROL
994 || (opP->reg != TT0 && opP->reg != TT1))
995 losing++;
996 break;
997
998 case 'A':
999 if (opP->mode != AREG)
1000 losing++;
1001 break;
1002
1003 case 'a':
1004 if (opP->mode != AINDR)
1005 ++losing;
1006 break;
1007
1008 case 'B': /* FOO */
1009 if (opP->mode != ABSL
1010 || (flag_long_jumps
1011 && strncmp (instring, "jbsr", 4) == 0))
1012 losing++;
1013 break;
1014
1015 case 'C':
1016 if (opP->mode != CONTROL || opP->reg != CCR)
1017 losing++;
1018 break;
1019
1020 case 'd':
1021 if (opP->mode != DISP
1022 || opP->reg < ADDR0
1023 || opP->reg > ADDR7)
1024 losing++;
1025 break;
1026
1027 case 'D':
1028 if (opP->mode != DREG)
1029 losing++;
1030 break;
1031
1032 case 'F':
1033 if (opP->mode != FPREG)
1034 losing++;
1035 break;
1036
1037 case 'I':
1038 if (opP->mode != CONTROL
1039 || opP->reg < COP0
1040 || opP->reg > COP7)
1041 losing++;
1042 break;
1043
1044 case 'J':
1045 if (opP->mode != CONTROL
1046 || opP->reg < USP
1047 || opP->reg > last_movec_reg)
1048 losing++;
1049 else
1050 {
1051 const enum m68k_register *rp;
1052 for (rp = control_regs; *rp; rp++)
1053 if (*rp == opP->reg)
1054 break;
1055 if (*rp == 0)
1056 losing++;
1057 }
1058 break;
1059
1060 case 'k':
1061 if (opP->mode != IMMED)
1062 losing++;
1063 break;
1064
1065 case 'l':
1066 case 'L':
1067 if (opP->mode == DREG
1068 || opP->mode == AREG
1069 || opP->mode == FPREG)
1070 {
1071 if (s[1] == '8')
1072 losing++;
1073 else
1074 {
1075 switch (opP->mode)
1076 {
1077 case DREG:
1078 opP->mask = 1 << (opP->reg - DATA0);
1079 break;
1080 case AREG:
1081 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1082 break;
1083 case FPREG:
1084 opP->mask = 1 << (opP->reg - FP0 + 16);
1085 break;
1086 default:
1087 abort ();
1088 }
1089 opP->mode = REGLST;
1090 }
1091 }
1092 else if (opP->mode == CONTROL)
1093 {
1094 if (s[1] != '8')
1095 losing++;
1096 else
1097 {
1098 switch (opP->reg)
1099 {
1100 case FPI:
1101 opP->mask = 1 << 24;
1102 break;
1103 case FPS:
1104 opP->mask = 1 << 25;
1105 break;
1106 case FPC:
1107 opP->mask = 1 << 26;
1108 break;
1109 default:
1110 losing++;
1111 break;
1112 }
1113 opP->mode = REGLST;
1114 }
1115 }
1116 else if (opP->mode == ABSL
1117 && opP->disp.size == SIZE_UNSPEC
1118 && opP->disp.exp.X_op == O_constant)
1119 {
1120 /* This is what the MRI REG pseudo-op generates. */
1121 opP->mode = REGLST;
1122 opP->mask = opP->disp.exp.X_add_number;
1123 }
1124 else if (opP->mode != REGLST)
1125 losing++;
1126 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1127 losing++;
1128 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1129 losing++;
1130 break;
1131
1132 case 'M':
1133 if (opP->mode != IMMED)
1134 losing++;
1135 else if (opP->disp.exp.X_op != O_constant
1136 || ! issbyte (opP->disp.exp.X_add_number))
1137 losing++;
1138 else if (! m68k_quick
1139 && instring[3] != 'q'
1140 && instring[4] != 'q')
1141 losing++;
1142 break;
1143
1144 case 'O':
1145 if (opP->mode != DREG && opP->mode != IMMED)
1146 losing++;
1147 break;
1148
1149 case 'Q':
1150 if (opP->mode != IMMED)
1151 losing++;
1152 else if (opP->disp.exp.X_op != O_constant
1153 || opP->disp.exp.X_add_number < 1
1154 || opP->disp.exp.X_add_number > 8)
1155 losing++;
1156 else if (! m68k_quick
1157 && (strncmp (instring, "add", 3) == 0
1158 || strncmp (instring, "sub", 3) == 0)
1159 && instring[3] != 'q')
1160 losing++;
1161 break;
1162
1163 case 'R':
1164 if (opP->mode != DREG && opP->mode != AREG)
1165 losing++;
1166 break;
1167
1168 case 'r':
1169 if (opP->mode != AINDR
1170 && (opP->mode != BASE
1171 || (opP->reg != 0
1172 && opP->reg != ZADDR0)
1173 || opP->disp.exp.X_op != O_absent
1174 || ((opP->index.reg < DATA0
1175 || opP->index.reg > DATA7)
1176 && (opP->index.reg < ADDR0
1177 || opP->index.reg > ADDR7))
1178 || opP->index.size != SIZE_UNSPEC
1179 || opP->index.scale != 1))
1180 losing++;
1181 break;
1182
1183 case 's':
1184 if (opP->mode != CONTROL
1185 || ! (opP->reg == FPI
1186 || opP->reg == FPS
1187 || opP->reg == FPC))
1188 losing++;
1189 break;
1190
1191 case 'S':
1192 if (opP->mode != CONTROL || opP->reg != SR)
1193 losing++;
1194 break;
1195
1196 case 't':
1197 if (opP->mode != IMMED)
1198 losing++;
1199 else if (opP->disp.exp.X_op != O_constant
1200 || opP->disp.exp.X_add_number < 0
1201 || opP->disp.exp.X_add_number > 7)
1202 losing++;
1203 break;
1204
1205 case 'U':
1206 if (opP->mode != CONTROL || opP->reg != USP)
1207 losing++;
1208 break;
1209
1210 /* JF these are out of order. We could put them
1211 in order if we were willing to put up with
1212 bunches of #ifdef m68851s in the code.
1213
1214 Don't forget that you need these operands
1215 to use 68030 MMU instructions. */
1216#ifndef NO_68851
1217 /* Memory addressing mode used by pflushr */
1218 case '|':
1219 if (opP->mode == CONTROL
1220 || opP->mode == FPREG
1221 || opP->mode == DREG
1222 || opP->mode == AREG
1223 || opP->mode == REGLST)
1224 losing++;
1225 break;
1226
1227 case 'f':
1228 if (opP->mode != CONTROL
1229 || (opP->reg != SFC && opP->reg != DFC))
1230 losing++;
1231 break;
1232
1233 case 'P':
1234 if (opP->mode != CONTROL
1235 || (opP->reg != TC
1236 && opP->reg != CAL
1237 && opP->reg != VAL
1238 && opP->reg != SCC
1239 && opP->reg != AC))
1240 losing++;
1241 break;
1242
1243 case 'V':
1244 if (opP->mode != CONTROL
1245 || opP->reg != VAL)
1246 losing++;
1247 break;
1248
1249 case 'W':
1250 if (opP->mode != CONTROL
1251 || (opP->reg != DRP
1252 && opP->reg != SRP
1253 && opP->reg != CRP))
1254 losing++;
1255 break;
1256
1257 case 'X':
1258 if (opP->mode != CONTROL
1259 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1260 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1261 losing++;
1262 break;
1263
1264 case 'Y':
1265 if (opP->mode != CONTROL || opP->reg != PSR)
1266 losing++;
1267 break;
1268
1269 case 'Z':
1270 if (opP->mode != CONTROL || opP->reg != PCSR)
1271 losing++;
1272 break;
1273#endif
1274 case 'c':
1275 if (opP->mode != CONTROL
1276 || (opP->reg != NC
1277 && opP->reg != IC
1278 && opP->reg != DC
1279 && opP->reg != BC))
1280 {
1281 losing++;
1282 } /* not a cache specifier. */
1283 break;
1284
1285 case '_':
1286 if (opP->mode != ABSL)
1287 ++losing;
1288 break;
1289
1290 default:
1291 abort ();
1292 } /* switch on type of operand */
1293
1294 if (losing)
1295 break;
1296 } /* for each operand */
1297 } /* if immediately wrong */
1298
1299 if (!losing)
1300 {
1301 break;
1302 } /* got it. */
1303
1304 opcode = opcode->m_next;
1305
1306 if (!opcode)
1307 {
1308 if (ok_arch
1309 && !(ok_arch & current_architecture))
1310 {
1311 char buf[200], *cp;
1312 int len;
1313 strcpy (buf,
1314 "invalid instruction for this architecture; needs ");
1315 cp = buf + strlen (buf);
1316 switch (ok_arch)
1317 {
1318 case mfloat:
1319 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1320 break;
1321 case mmmu:
1322 strcpy (cp, "mmu (68030 or 68851)");
1323 break;
1324 case m68020up:
1325 strcpy (cp, "68020 or higher");
1326 break;
1327 case m68000up:
1328 strcpy (cp, "68000 or higher");
1329 break;
1330 case m68010up:
1331 strcpy (cp, "68010 or higher");
1332 break;
1333 default:
1334 {
1335 int got_one = 0, idx;
1336 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1337 idx++)
1338 {
1339 if (archs[idx].arch & ok_arch)
1340 {
1341 if (got_one)
1342 {
1343 strcpy (cp, " or ");
1344 cp += strlen (cp);
1345 }
1346 got_one = 1;
1347 strcpy (cp, archs[idx].name);
1348 cp += strlen (cp);
1349 }
1350 }
1351 }
1352 }
1353 len = cp - buf + 1;
1354 cp = malloc (len);
1355 strcpy (cp, buf);
1356 the_ins.error = cp;
1357 }
1358 else
1359 the_ins.error = "operands mismatch";
1360 return;
1361 } /* Fell off the end */
1362
1363 losing = 0;
1364 }
1365
1366 /* now assemble it */
1367
1368 the_ins.args = opcode->m_operands;
1369 the_ins.numargs = opcode->m_opnum;
1370 the_ins.numo = opcode->m_codenum;
1371 the_ins.opcode[0] = getone (opcode);
1372 the_ins.opcode[1] = gettwo (opcode);
1373
1374 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1375 {
1376 /* This switch is a doozy.
1377 Watch the first step; its a big one! */
1378 switch (s[0])
1379 {
1380
1381 case '*':
1382 case '~':
1383 case '%':
1384 case ';':
1385 case '@':
1386 case '!':
1387 case '&':
1388 case '$':
1389 case '?':
1390 case '/':
1391 case '`':
1392#ifndef NO_68851
1393 case '|':
1394#endif
1395 switch (opP->mode)
1396 {
1397 case IMMED:
1398 tmpreg = 0x3c; /* 7.4 */
1399 if (strchr ("bwl", s[1]))
1400 nextword = get_num (&opP->disp, 80);
1401 else
1402 nextword = get_num (&opP->disp, 0);
1403 if (isvar (&opP->disp))
1404 add_fix (s[1], &opP->disp, 0, 0);
1405 switch (s[1])
1406 {
1407 case 'b':
1408 if (!isbyte (nextword))
1409 opP->error = "operand out of range";
1410 addword (nextword);
1411 baseo = 0;
1412 break;
1413 case 'w':
1414 if (!isword (nextword))
1415 opP->error = "operand out of range";
1416 addword (nextword);
1417 baseo = 0;
1418 break;
1419 case 'l':
1420 addword (nextword >> 16);
1421 addword (nextword);
1422 baseo = 0;
1423 break;
1424
1425 case 'f':
1426 baseo = 2;
1427 outro = 8;
1428 break;
1429 case 'F':
1430 baseo = 4;
1431 outro = 11;
1432 break;
1433 case 'x':
1434 baseo = 6;
1435 outro = 15;
1436 break;
1437 case 'p':
1438 baseo = 6;
1439 outro = -1;
1440 break;
1441 default:
1442 abort ();
1443 }
1444 if (!baseo)
1445 break;
1446
1447 /* We gotta put out some float */
1448 if (op (&opP->disp) != O_big)
1449 {
1450 valueT val;
1451 int gencnt;
1452
1453 /* Can other cases happen here? */
1454 if (op (&opP->disp) != O_constant)
1455 abort ();
1456
1457 val = (valueT) offs (&opP->disp);
1458 gencnt = 0;
1459 do
1460 {
1461 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1462 val >>= LITTLENUM_NUMBER_OF_BITS;
1463 ++gencnt;
1464 }
1465 while (val != 0);
1466 offs (&opP->disp) = gencnt;
1467 }
1468 if (offs (&opP->disp) > 0)
1469 {
1470 if (offs (&opP->disp) > baseo)
1471 {
1472 as_warn ("Bignum too big for %c format; truncated",
1473 s[1]);
1474 offs (&opP->disp) = baseo;
1475 }
1476 baseo -= offs (&opP->disp);
1477 while (baseo--)
1478 addword (0);
1479 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1480 offs (&opP->disp)--;
1481 --wordp)
1482 addword (*wordp);
1483 break;
1484 }
1485 gen_to_words (words, baseo, (long) outro);
1486 for (wordp = words; baseo--; wordp++)
1487 addword (*wordp);
1488 break;
1489 case DREG:
1490 tmpreg = opP->reg - DATA; /* 0.dreg */
1491 break;
1492 case AREG:
1493 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1494 break;
1495 case AINDR:
1496 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1497 break;
1498 case ADEC:
1499 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1500 break;
1501 case AINC:
1502 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1503 break;
1504 case DISP:
1505
1506 nextword = get_num (&opP->disp, 80);
1507
1508 if (opP->reg == PC
1509 && ! isvar (&opP->disp)
1510 && m68k_abspcadd)
1511 {
1512 opP->disp.exp.X_op = O_symbol;
1513#ifndef BFD_ASSEMBLER
1514 opP->disp.exp.X_add_symbol = &abs_symbol;
1515#else
1516 opP->disp.exp.X_add_symbol =
1517 section_symbol (absolute_section);
1518#endif
1519 }
1520
1521 /* Force into index mode. Hope this works */
1522
1523 /* We do the first bit for 32-bit displacements, and the
1524 second bit for 16 bit ones. It is possible that we
1525 should make the default be WORD instead of LONG, but
1526 I think that'd break GCC, so we put up with a little
1527 inefficiency for the sake of working output. */
1528
1529 if (!issword (nextword)
1530 || (isvar (&opP->disp)
1531 && ((opP->disp.size == SIZE_UNSPEC
1532 && flag_short_refs == 0
1533 && cpu_of_arch (current_architecture) >= m68020)
1534 || opP->disp.size == SIZE_LONG)))
1535 {
1536 if (opP->reg == PC)
1537 tmpreg = 0x3B; /* 7.3 */
1538 else
1539 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1540 if (isvar (&opP->disp))
1541 {
1542 if (opP->reg == PC)
1543 {
1544#if 0
1545 addword (0x0170);
1546 add_fix ('l', &opP->disp, 1, 2);
1547 addword (0), addword (0);
1548#else
1549 add_frag (adds (&opP->disp),
1550 offs (&opP->disp),
1551 TAB (PCLEA, SZ_UNDEF));
1552#endif
1553 break;
1554 }
1555 else
1556 {
1557 addword (0x0170);
1558 add_fix ('l', &opP->disp, 0, 0);
1559 }
1560 }
1561 else
1562 addword (0x0170);
1563 addword (nextword >> 16);
1564 }
1565 else
1566 {
1567 if (opP->reg == PC)
1568 tmpreg = 0x3A; /* 7.2 */
1569 else
1570 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1571
1572 if (isvar (&opP->disp))
1573 {
1574 if (opP->reg == PC)
1575 {
1576 add_fix ('w', &opP->disp, 1, 0);
1577 }
1578 else
1579 add_fix ('w', &opP->disp, 0, 0);
1580 }
1581 }
1582 addword (nextword);
1583 break;
1584
1585 case POST:
1586 case PRE:
1587 case BASE:
1588 nextword = 0;
1589 baseo = get_num (&opP->disp, 80);
1590 if (opP->mode == POST || opP->mode == PRE)
1591 outro = get_num (&opP->odisp, 80);
1592 /* Figure out the `addressing mode'.
1593 Also turn on the BASE_DISABLE bit, if needed. */
1594 if (opP->reg == PC || opP->reg == ZPC)
1595 {
1596 tmpreg = 0x3b; /* 7.3 */
1597 if (opP->reg == ZPC)
1598 nextword |= 0x80;
1599 }
1600 else if (opP->reg == 0)
1601 {
1602 nextword |= 0x80;
1603 tmpreg = 0x30; /* 6.garbage */
1604 }
1605 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
1606 {
1607 nextword |= 0x80;
1608 tmpreg = 0x30 + opP->reg - ZADDR0;
1609 }
1610 else
1611 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1612
1613 siz1 = opP->disp.size;
1614 if (opP->mode == POST || opP->mode == PRE)
1615 siz2 = opP->odisp.size;
1616 else
1617 siz2 = SIZE_UNSPEC;
1618
1619 /* Index register stuff */
1620 if (opP->index.reg != 0
1621 && opP->index.reg >= DATA
1622 && opP->index.reg <= ADDR7)
1623 {
1624 nextword |= (opP->index.reg - DATA) << 12;
1625
1626 if (opP->index.size == SIZE_UNSPEC
1627 || opP->index.size == SIZE_LONG)
1628 nextword |= 0x800;
1629
1630 if (cpu_of_arch (current_architecture) < m68020)
1631 {
1632 if (opP->index.scale != 1)
1633 {
1634 opP->error =
1635 "scale factor invalid on this architecture; needs 68020 or higher";
1636 }
1637 }
1638
1639 switch (opP->index.scale)
1640 {
1641 case 1:
1642 break;
1643 case 2:
1644 nextword |= 0x200;
1645 break;
1646 case 4:
1647 nextword |= 0x400;
1648 break;
1649 case 8:
1650 nextword |= 0x600;
1651 break;
1652 default:
1653 abort ();
1654 }
1655 /* IF its simple,
1656 GET US OUT OF HERE! */
1657
1658 /* Must be INDEX, with an index register. Address
1659 register cannot be ZERO-PC, and either :b was
1660 forced, or we know it will fit. For a 68000 or
1661 68010, force this mode anyways, because the
1662 larger modes aren't supported. */
1663 if (opP->mode == BASE
1664 && ((opP->reg >= ADDR0
1665 && opP->reg <= ADDR7)
1666 || opP->reg == PC))
1667 {
1668 if (siz1 == SIZE_BYTE
1669 || cpu_of_arch (current_architecture) < m68020
1670 || (siz1 == SIZE_UNSPEC
1671 && ! isvar (&opP->disp)
1672 && issbyte (baseo)))
1673 {
1674 nextword += baseo & 0xff;
1675 addword (nextword);
1676 if (isvar (&opP->disp))
1677 {
1678 /* Do a byte relocation. If it doesn't
1679 fit (possible on m68000) let the
1680 fixup processing complain later. */
1681 if (opP->reg == PC)
1682 add_fix ('B', &opP->disp, 1, 1);
1683 else
1684 add_fix ('B', &opP->disp, 0, 0);
1685 }
1686 else if (siz1 != SIZE_BYTE)
1687 {
1688 if (siz1 != SIZE_UNSPEC)
1689 as_warn ("Forcing byte displacement");
1690 if (! issbyte (baseo))
1691 opP->error = "byte displacement out of range";
1692 }
1693
1694 break;
1695 }
1696 else if (siz1 == SIZE_UNSPEC
1697 && opP->reg == PC
1698 && isvar (&opP->disp)
1699 && subs (&opP->disp) == NULL)
1700 {
1701 nextword += baseo & 0xff;
1702 addword (nextword);
1703 add_frag (adds (&opP->disp), offs (&opP->disp),
1704 TAB (PCINDEX, SZ_UNDEF));
1705
1706 break;
1707 }
1708 }
1709 }
1710 else
1711 {
1712 nextword |= 0x40; /* No index reg */
1713 if (opP->index.reg >= ZDATA0
1714 && opP->index.reg <= ZDATA7)
1715 nextword |= (opP->index.reg - ZDATA0) << 12;
1716 else if (opP->index.reg >= ZADDR0
1717 || opP->index.reg <= ZADDR7)
1718 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
1719 }
1720
1721 /* It isn't simple. */
1722
1723 if (cpu_of_arch (current_architecture) < m68020)
1724 opP->error =
1725 "invalid operand mode for this architecture; needs 68020 or higher";
1726
1727 nextword |= 0x100;
1728 /* If the guy specified a width, we assume that it is
1729 wide enough. Maybe it isn't. If so, we lose. */
1730 switch (siz1)
1731 {
1732 case SIZE_UNSPEC:
1733 if (isvar (&opP->disp)
1734 ? m68k_rel32
1735 : ! issword (baseo))
1736 {
1737 siz1 = SIZE_LONG;
1738 nextword |= 0x30;
1739 }
1740 else if (! isvar (&opP->disp) && baseo == 0)
1741 nextword |= 0x10;
1742 else
1743 {
1744 nextword |= 0x20;
1745 siz1 = SIZE_WORD;
1746 }
1747 break;
1748 case SIZE_BYTE:
1749 as_warn (":b not permitted; defaulting to :w");
1750 /* Fall through. */
1751 case SIZE_WORD:
1752 nextword |= 0x20;
1753 break;
1754 case SIZE_LONG:
1755 nextword |= 0x30;
1756 break;
1757 }
1758
1759 /* Figure out innner displacement stuff */
1760 if (opP->mode == POST || opP->mode == PRE)
1761 {
1762 switch (siz2)
1763 {
1764 case SIZE_UNSPEC:
1765 if (isvar (&opP->odisp)
1766 ? m68k_rel32
1767 : ! issword (outro))
1768 {
1769 siz2 = SIZE_LONG;
1770 nextword |= 0x3;
1771 }
1772 else if (! isvar (&opP->odisp) && outro == 0)
1773 nextword |= 0x1;
1774 else
1775 {
1776 nextword |= 0x2;
1777 siz2 = SIZE_WORD;
1778 }
1779 break;
1780 case 1:
1781 as_warn (":b not permitted; defaulting to :w");
1782 /* Fall through. */
1783 case 2:
1784 nextword |= 0x2;
1785 break;
1786 case 3:
1787 nextword |= 0x3;
1788 break;
1789 }
1790 if (opP->mode == POST
1791 && (nextword & 0x40) == 0)
1792 nextword |= 0x04;
1793 }
1794 addword (nextword);
1795
1796 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
1797 {
1798 if (opP->reg == PC || opP->reg == ZPC)
1799 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
1800 else
1801 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
1802 }
1803 if (siz1 == SIZE_LONG)
1804 addword (baseo >> 16);
1805 if (siz1 != SIZE_UNSPEC)
1806 addword (baseo);
1807
1808 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
1809 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
1810 if (siz2 == SIZE_LONG)
1811 addword (outro >> 16);
1812 if (siz2 != SIZE_UNSPEC)
1813 addword (outro);
1814
1815 break;
1816
1817 case ABSL:
1818 nextword = get_num (&opP->disp, 80);
1819 switch (opP->disp.size)
1820 {
1821 default:
1822 abort ();
1823 case SIZE_UNSPEC:
1824 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
1825 {
1826 tmpreg = 0x38; /* 7.0 */
1827 addword (nextword);
1828 break;
1829 }
1830 /* Don't generate pc relative code on 68010 and
1831 68000. */
1832 if (isvar (&opP->disp)
1833 && !subs (&opP->disp)
1834 && adds (&opP->disp)
1835 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
1836 && cpu_of_arch (current_architecture) >= m68020
1837 && !flag_long_jumps
1838 && !strchr ("~%&$?", s[0]))
1839 {
1840 tmpreg = 0x3A; /* 7.2 */
1841 add_frag (adds (&opP->disp),
1842 offs (&opP->disp),
1843 TAB (PCREL, SZ_UNDEF));
1844 break;
1845 }
1846 /* Fall through into long */
1847 case SIZE_LONG:
1848 if (isvar (&opP->disp))
1849 add_fix ('l', &opP->disp, 0, 0);
1850
1851 tmpreg = 0x39;/* 7.1 mode */
1852 addword (nextword >> 16);
1853 addword (nextword);
1854 break;
1855
1856 case SIZE_WORD: /* Word */
1857 if (isvar (&opP->disp))
1858 add_fix ('w', &opP->disp, 0, 0);
1859
1860 tmpreg = 0x38;/* 7.0 mode */
1861 addword (nextword);
1862 break;
1863 }
1864 break;
1865 case CONTROL:
1866 case FPREG:
1867 default:
1868 as_bad ("unknown/incorrect operand");
1869 /* abort(); */
1870 }
1871 install_gen_operand (s[1], tmpreg);
1872 break;
1873
1874 case '#':
1875 case '^':
1876 switch (s[1])
1877 { /* JF: I hate floating point! */
1878 case 'j':
1879 tmpreg = 70;
1880 break;
1881 case '8':
1882 tmpreg = 20;
1883 break;
1884 case 'C':
1885 tmpreg = 50;
1886 break;
1887 case '3':
1888 default:
1889 tmpreg = 80;
1890 break;
1891 }
1892 tmpreg = get_num (&opP->disp, tmpreg);
1893 if (isvar (&opP->disp))
1894 add_fix (s[1], &opP->disp, 0, 0);
1895 switch (s[1])
1896 {
1897 case 'b': /* Danger: These do no check for
1898 certain types of overflow.
1899 user beware! */
1900 if (!isbyte (tmpreg))
1901 opP->error = "out of range";
1902 insop (tmpreg, opcode);
1903 if (isvar (&opP->disp))
1904 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1905 break;
1906 case 'w':
1907 if (!isword (tmpreg))
1908 opP->error = "out of range";
1909 insop (tmpreg, opcode);
1910 if (isvar (&opP->disp))
1911 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1912 break;
1913 case 'l':
1914 /* Because of the way insop works, we put these two out
1915 backwards. */
1916 insop (tmpreg, opcode);
1917 insop (tmpreg >> 16, opcode);
1918 if (isvar (&opP->disp))
1919 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1920 break;
1921 case '3':
1922 tmpreg &= 0xFF;
1923 case '8':
1924 case 'C':
1925 install_operand (s[1], tmpreg);
1926 break;
1927 default:
1928 abort ();
1929 }
1930 break;
1931
1932 case '+':
1933 case '-':
1934 case 'A':
1935 case 'a':
1936 install_operand (s[1], opP->reg - ADDR);
1937 break;
1938
1939 case 'B':
1940 tmpreg = get_num (&opP->disp, 80);
1941 switch (s[1])
1942 {
1943 case 'B':
1944 /* The pc_fix argument winds up in fx_pcrel_adjust,
1945 which is a char, and may therefore be unsigned. We
1946 want to pass -1, but we pass 64 instead, and convert
1947 back in md_pcrel_from. */
1948 add_fix ('B', &opP->disp, 1, 64);
1949 break;
1950 case 'W':
1951 add_fix ('w', &opP->disp, 1, 0);
1952 addword (0);
1953 break;
1954 case 'L':
1955 long_branch:
1956 if (cpu_of_arch (current_architecture) < m68020)
1957 as_warn ("Can't use long branches on 68000/68010");
1958 the_ins.opcode[the_ins.numo - 1] |= 0xff;
1959 add_fix ('l', &opP->disp, 1, 0);
1960 addword (0);
1961 addword (0);
1962 break;
1963 case 'g':
1964 if (subs (&opP->disp)) /* We can't relax it */
1965 goto long_branch;
1966
1967 /* This could either be a symbol, or an absolute
1968 address. No matter, the frag hacking will finger it
1969 out. Not quite: it can't switch from BRANCH to
1970 BCC68000 for the case where opnd is absolute (it
1971 needs to use the 68000 hack since no conditional abs
1972 jumps). */
1973 if (((cpu_of_arch (current_architecture) < m68020)
1974 || (0 == adds (&opP->disp)))
1975 && (the_ins.opcode[0] >= 0x6200)
1976 && (the_ins.opcode[0] <= 0x6f00))
1977 add_frag (adds (&opP->disp), offs (&opP->disp),
1978 TAB (BCC68000, SZ_UNDEF));
1979 else
1980 add_frag (adds (&opP->disp), offs (&opP->disp),
1981 TAB (ABRANCH, SZ_UNDEF));
1982 break;
1983 case 'w':
1984 if (isvar (&opP->disp))
1985 {
1986#if 1
1987 /* check for DBcc instruction */
1988 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
1989 {
1990 /* size varies if patch */
1991 /* needed for long form */
1992 add_frag (adds (&opP->disp), offs (&opP->disp),
1993 TAB (DBCC, SZ_UNDEF));
1994 break;
1995 }
1996#endif
1997 add_fix ('w', &opP->disp, 1, 0);
1998 }
1999 addword (0);
2000 break;
2001 case 'C': /* Fixed size LONG coproc branches */
2002 add_fix ('l', &opP->disp, 1, 0);
2003 addword (0);
2004 addword (0);
2005 break;
2006 case 'c': /* Var size Coprocesssor branches */
2007 if (subs (&opP->disp))
2008 {
2009 add_fix ('l', &opP->disp, 1, 0);
2010 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2011 }
2012 else if (adds (&opP->disp))
2013 add_frag (adds (&opP->disp), offs (&opP->disp),
2014 TAB (FBRANCH, SZ_UNDEF));
2015 else
2016 {
2017 /* add_frag((symbolS *) 0, offs(&opP->disp),
2018 TAB(FBRANCH,SHORT)); */
2019 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2020 add_fix ('l', &opP->disp, 1, 0);
2021 addword (0);
2022 addword (0);
2023 }
2024 break;
2025 default:
2026 abort ();
2027 }
2028 break;
2029
2030 case 'C': /* Ignore it */
2031 break;
2032
2033 case 'd': /* JF this is a kludge */
2034 install_operand ('s', opP->reg - ADDR);
2035 tmpreg = get_num (&opP->disp, 80);
2036 if (!issword (tmpreg))
2037 {
2038 as_warn ("Expression out of range, using 0");
2039 tmpreg = 0;
2040 }
2041 addword (tmpreg);
2042 break;
2043
2044 case 'D':
2045 install_operand (s[1], opP->reg - DATA);
2046 break;
2047
2048 case 'F':
2049 install_operand (s[1], opP->reg - FP0);
2050 break;
2051
2052 case 'I':
2053 tmpreg = opP->reg - COP0;
2054 install_operand (s[1], tmpreg);
2055 break;
2056
2057 case 'J': /* JF foo */
2058 switch (opP->reg)
2059 {
2060 case SFC:
2061 tmpreg = 0x000;
2062 break;
2063 case DFC:
2064 tmpreg = 0x001;
2065 break;
2066 case CACR:
2067 tmpreg = 0x002;
2068 break;
2069 case TC:
2070 tmpreg = 0x003;
2071 break;
2072 case ITT0:
2073 tmpreg = 0x004;
2074 break;
2075 case ITT1:
2076 tmpreg = 0x005;
2077 break;
2078 case DTT0:
2079 tmpreg = 0x006;
2080 break;
2081 case DTT1:
2082 tmpreg = 0x007;
2083 break;
2084 case BUSCR:
2085 tmpreg = 0x008;
2086 break;
2087
2088 case USP:
2089 tmpreg = 0x800;
2090 break;
2091 case VBR:
2092 tmpreg = 0x801;
2093 break;
2094 case CAAR:
2095 tmpreg = 0x802;
2096 break;
2097 case MSP:
2098 tmpreg = 0x803;
2099 break;
2100 case ISP:
2101 tmpreg = 0x804;
2102 break;
2103 case MMUSR:
2104 tmpreg = 0x805;
2105 break;
2106 case URP:
2107 tmpreg = 0x806;
2108 break;
2109 case SRP:
2110 tmpreg = 0x807;
2111 break;
2112 case PCR:
2113 tmpreg = 0x808;
2114 break;
2115 default:
2116 abort ();
2117 }
2118 install_operand (s[1], tmpreg);
2119 break;
2120
2121 case 'k':
2122 tmpreg = get_num (&opP->disp, 55);
2123 install_operand (s[1], tmpreg & 0x7f);
2124 break;
2125
2126 case 'l':
2127 tmpreg = opP->mask;
2128 if (s[1] == 'w')
2129 {
2130 if (tmpreg & 0x7FF0000)
2131 as_bad ("Floating point register in register list");
2132 insop (reverse_16_bits (tmpreg), opcode);
2133 }
2134 else
2135 {
2136 if (tmpreg & 0x700FFFF)
2137 as_bad ("Wrong register in floating-point reglist");
2138 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2139 }
2140 break;
2141
2142 case 'L':
2143 tmpreg = opP->mask;
2144 if (s[1] == 'w')
2145 {
2146 if (tmpreg & 0x7FF0000)
2147 as_bad ("Floating point register in register list");
2148 insop (tmpreg, opcode);
2149 }
2150 else if (s[1] == '8')
2151 {
2152 if (tmpreg & 0x0FFFFFF)
2153 as_bad ("incorrect register in reglist");
2154 install_operand (s[1], tmpreg >> 24);
2155 }
2156 else
2157 {
2158 if (tmpreg & 0x700FFFF)
2159 as_bad ("wrong register in floating-point reglist");
2160 else
2161 install_operand (s[1], tmpreg >> 16);
2162 }
2163 break;
2164
2165 case 'M':
2166 install_operand (s[1], get_num (&opP->disp, 60));
2167 break;
2168
2169 case 'O':
2170 tmpreg = ((opP->mode == DREG)
2171 ? 0x20 + opP->reg - DATA
2172 : (get_num (&opP->disp, 40) & 0x1F));
2173 install_operand (s[1], tmpreg);
2174 break;
2175
2176 case 'Q':
2177 tmpreg = get_num (&opP->disp, 10);
2178 if (tmpreg == 8)
2179 tmpreg = 0;
2180 install_operand (s[1], tmpreg);
2181 break;
2182
2183 case 'R':
2184 /* This depends on the fact that ADDR registers are eight
2185 more than their corresponding DATA regs, so the result
2186 will have the ADDR_REG bit set */
2187 install_operand (s[1], opP->reg - DATA);
2188 break;
2189
2190 case 'r':
2191 if (opP->mode == AINDR)
2192 install_operand (s[1], opP->reg - DATA);
2193 else
2194 install_operand (s[1], opP->index.reg - DATA);
2195 break;
2196
2197 case 's':
2198 if (opP->reg == FPI)
2199 tmpreg = 0x1;
2200 else if (opP->reg == FPS)
2201 tmpreg = 0x2;
2202 else if (opP->reg == FPC)
2203 tmpreg = 0x4;
2204 else
2205 abort ();
2206 install_operand (s[1], tmpreg);
2207 break;
2208
2209 case 'S': /* Ignore it */
2210 break;
2211
2212 case 'T':
2213 install_operand (s[1], get_num (&opP->disp, 30));
2214 break;
2215
2216 case 'U': /* Ignore it */
2217 break;
2218
2219 case 'c':
2220 switch (opP->reg)
2221 {
2222 case NC:
2223 tmpreg = 0;
2224 break;
2225 case DC:
2226 tmpreg = 1;
2227 break;
2228 case IC:
2229 tmpreg = 2;
2230 break;
2231 case BC:
2232 tmpreg = 3;
2233 break;
2234 default:
2235 as_fatal ("failed sanity check");
2236 } /* switch on cache token */
2237 install_operand (s[1], tmpreg);
2238 break;
2239#ifndef NO_68851
2240 /* JF: These are out of order, I fear. */
2241 case 'f':
2242 switch (opP->reg)
2243 {
2244 case SFC:
2245 tmpreg = 0;
2246 break;
2247 case DFC:
2248 tmpreg = 1;
2249 break;
2250 default:
2251 abort ();
2252 }
2253 install_operand (s[1], tmpreg);
2254 break;
2255
2256 case 'P':
2257 switch (opP->reg)
2258 {
2259 case TC:
2260 tmpreg = 0;
2261 break;
2262 case CAL:
2263 tmpreg = 4;
2264 break;
2265 case VAL:
2266 tmpreg = 5;
2267 break;
2268 case SCC:
2269 tmpreg = 6;
2270 break;
2271 case AC:
2272 tmpreg = 7;
2273 break;
2274 default:
2275 abort ();
2276 }
2277 install_operand (s[1], tmpreg);
2278 break;
2279
2280 case 'V':
2281 if (opP->reg == VAL)
2282 break;
2283 abort ();
2284
2285 case 'W':
2286 switch (opP->reg)
2287 {
2288 case DRP:
2289 tmpreg = 1;
2290 break;
2291 case SRP:
2292 tmpreg = 2;
2293 break;
2294 case CRP:
2295 tmpreg = 3;
2296 break;
2297 default:
2298 abort ();
2299 }
2300 install_operand (s[1], tmpreg);
2301 break;
2302
2303 case 'X':
2304 switch (opP->reg)
2305 {
2306 case BAD:
2307 case BAD + 1:
2308 case BAD + 2:
2309 case BAD + 3:
2310 case BAD + 4:
2311 case BAD + 5:
2312 case BAD + 6:
2313 case BAD + 7:
2314 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2315 break;
2316
2317 case BAC:
2318 case BAC + 1:
2319 case BAC + 2:
2320 case BAC + 3:
2321 case BAC + 4:
2322 case BAC + 5:
2323 case BAC + 6:
2324 case BAC + 7:
2325 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2326 break;
2327
2328 default:
2329 abort ();
2330 }
2331 install_operand (s[1], tmpreg);
2332 break;
2333 case 'Y':
2334 know (opP->reg == PSR);
2335 break;
2336 case 'Z':
2337 know (opP->reg == PCSR);
2338 break;
2339#endif /* m68851 */
2340 case '3':
2341 switch (opP->reg)
2342 {
2343 case TT0:
2344 tmpreg = 2;
2345 break;
2346 case TT1:
2347 tmpreg = 3;
2348 break;
2349 default:
2350 abort ();
2351 }
2352 install_operand (s[1], tmpreg);
2353 break;
2354 case 't':
2355 tmpreg = get_num (&opP->disp, 20);
2356 install_operand (s[1], tmpreg);
2357 break;
2358 case '_': /* used only for move16 absolute 32-bit address */
2359 tmpreg = get_num (&opP->disp, 80);
2360 addword (tmpreg >> 16);
2361 addword (tmpreg & 0xFFFF);
2362 break;
2363 default:
2364 abort ();
2365 }
2366 }
2367
2368 /* By the time whe get here (FINALLY) the_ins contains the complete
2369 instruction, ready to be emitted. . . */
2370}
2371
2372static int
2373reverse_16_bits (in)
2374 int in;
2375{
2376 int out = 0;
2377 int n;
2378
2379 static int mask[16] =
2380 {
2381 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2382 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2383 };
2384 for (n = 0; n < 16; n++)
2385 {
2386 if (in & mask[n])
2387 out |= mask[15 - n];
2388 }
2389 return out;
2390} /* reverse_16_bits() */
2391
2392static int
2393reverse_8_bits (in)
2394 int in;
2395{
2396 int out = 0;
2397 int n;
2398
2399 static int mask[8] =
2400 {
2401 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2402 };
2403
2404 for (n = 0; n < 8; n++)
2405 {
2406 if (in & mask[n])
2407 out |= mask[7 - n];
2408 }
2409 return out;
2410} /* reverse_8_bits() */
2411
2412/* Cause an extra frag to be generated here, inserting up to 10 bytes
2413 (that value is chosen in the frag_var call in md_assemble). TYPE
2414 is the subtype of the frag to be generated; its primary type is
2415 rs_machine_dependent.
2416
2417 The TYPE parameter is also used by md_convert_frag_1 and
2418 md_estimate_size_before_relax. The appropriate type of fixup will
2419 be emitted by md_convert_frag_1.
2420
2421 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2422static void
2423install_operand (mode, val)
2424 int mode;
2425 int val;
2426{
2427 switch (mode)
2428 {
2429 case 's':
2430 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2431 break;
2432 case 'd':
2433 the_ins.opcode[0] |= val << 9;
2434 break;
2435 case '1':
2436 the_ins.opcode[1] |= val << 12;
2437 break;
2438 case '2':
2439 the_ins.opcode[1] |= val << 6;
2440 break;
2441 case '3':
2442 the_ins.opcode[1] |= val;
2443 break;
2444 case '4':
2445 the_ins.opcode[2] |= val << 12;
2446 break;
2447 case '5':
2448 the_ins.opcode[2] |= val << 6;
2449 break;
2450 case '6':
2451 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2452 three words long! */
2453 the_ins.numo++;
2454 the_ins.opcode[2] |= val;
2455 break;
2456 case '7':
2457 the_ins.opcode[1] |= val << 7;
2458 break;
2459 case '8':
2460 the_ins.opcode[1] |= val << 10;
2461 break;
2462#ifndef NO_68851
2463 case '9':
2464 the_ins.opcode[1] |= val << 5;
2465 break;
2466#endif
2467
2468 case 't':
2469 the_ins.opcode[1] |= (val << 10) | (val << 7);
2470 break;
2471 case 'D':
2472 the_ins.opcode[1] |= (val << 12) | val;
2473 break;
2474 case 'g':
2475 the_ins.opcode[0] |= val = 0xff;
2476 break;
2477 case 'i':
2478 the_ins.opcode[0] |= val << 9;
2479 break;
2480 case 'C':
2481 the_ins.opcode[1] |= val;
2482 break;
2483 case 'j':
2484 the_ins.opcode[1] |= val;
2485 the_ins.numo++; /* What a hack */
2486 break;
2487 case 'k':
2488 the_ins.opcode[1] |= val << 4;
2489 break;
2490 case 'b':
2491 case 'w':
2492 case 'l':
2493 break;
2494 case 'e':
2495 the_ins.opcode[0] |= (val << 6);
2496 break;
2497 case 'L':
2498 the_ins.opcode[1] = (val >> 16);
2499 the_ins.opcode[2] = val & 0xffff;
2500 break;
2501 case 'c':
2502 default:
2503 as_fatal ("failed sanity check.");
2504 }
2505} /* install_operand() */
2506
2507static void
2508install_gen_operand (mode, val)
2509 int mode;
2510 int val;
2511{
2512 switch (mode)
2513 {
2514 case 's':
2515 the_ins.opcode[0] |= val;
2516 break;
2517 case 'd':
2518 /* This is a kludge!!! */
2519 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2520 break;
2521 case 'b':
2522 case 'w':
2523 case 'l':
2524 case 'f':
2525 case 'F':
2526 case 'x':
2527 case 'p':
2528 the_ins.opcode[0] |= val;
2529 break;
2530 /* more stuff goes here */
2531 default:
2532 as_fatal ("failed sanity check.");
2533 }
2534} /* install_gen_operand() */
2535
2536/*
2537 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2538 * then deal with the bitfield hack.
2539 */
2540
2541static char *
2542crack_operand (str, opP)
2543 register char *str;
2544 register struct m68k_op *opP;
2545{
2546 register int parens;
2547 register int c;
2548 register char *beg_str;
2549 int inquote = 0;
2550
2551 if (!str)
2552 {
2553 return str;
2554 }
2555 beg_str = str;
2556 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
2557 {
2558 if (! inquote)
2559 {
2560 if (*str == '(')
2561 parens++;
2562 else if (*str == ')')
2563 {
2564 if (!parens)
2565 { /* ERROR */
2566 opP->error = "Extra )";
2567 return str;
2568 }
2569 --parens;
2570 }
2571 }
2572 if (flag_mri && *str == '\'')
2573 inquote = ! inquote;
2574 }
2575 if (!*str && parens)
2576 { /* ERROR */
2577 opP->error = "Missing )";
2578 return str;
2579 }
2580 c = *str;
2581 *str = '\0';
2582 if (m68k_ip_op (beg_str, opP) != 0)
2583 {
2584 *str = c;
2585 return str;
2586 }
2587 *str = c;
2588 if (c == '}')
2589 c = *++str; /* JF bitfield hack */
2590 if (c)
2591 {
2592 c = *++str;
2593 if (!c)
2594 as_bad ("Missing operand");
2595 }
2596 return str;
2597}
2598
2599/* This is the guts of the machine-dependent assembler. STR points to a
2600 machine dependent instruction. This function is supposed to emit
2601 the frags/bytes it assembles to.
2602 */
2603
2604void
2605insert_reg (regname, regnum)
2606 char *regname;
2607 int regnum;
2608{
2609 char buf[100];
2610 int i;
2611
2612#ifdef REGISTER_PREFIX
2613 if (!flag_reg_prefix_optional)
2614 {
2615 buf[0] = REGISTER_PREFIX;
2616 strcpy (buf + 1, regname);
2617 regname = buf;
2618 }
2619#endif
2620
2621 symbol_table_insert (symbol_new (regname, reg_section, regnum,
2622 &zero_address_frag));
2623
2624 for (i = 0; regname[i]; i++)
2625 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
2626 buf[i] = '\0';
2627
2628 symbol_table_insert (symbol_new (buf, reg_section, regnum,
2629 &zero_address_frag));
2630}
2631
2632struct init_entry
2633 {
2634 const char *name;
2635 int number;
2636 };
2637
2638static const struct init_entry init_table[] =
2639{
2640 { "d0", DATA0 },
2641 { "d1", DATA1 },
2642 { "d2", DATA2 },
2643 { "d3", DATA3 },
2644 { "d4", DATA4 },
2645 { "d5", DATA5 },
2646 { "d6", DATA6 },
2647 { "d7", DATA7 },
2648 { "a0", ADDR0 },
2649 { "a1", ADDR1 },
2650 { "a2", ADDR2 },
2651 { "a3", ADDR3 },
2652 { "a4", ADDR4 },
2653 { "a5", ADDR5 },
2654 { "a6", ADDR6 },
2655 { "fp", ADDR6 },
2656 { "a7", ADDR7 },
2657 { "sp", ADDR7 },
2658 { "ssp", ADDR7 },
2659 { "fp0", FP0 },
2660 { "fp1", FP1 },
2661 { "fp2", FP2 },
2662 { "fp3", FP3 },
2663 { "fp4", FP4 },
2664 { "fp5", FP5 },
2665 { "fp6", FP6 },
2666 { "fp7", FP7 },
2667 { "fpi", FPI },
2668 { "fpiar", FPI },
2669 { "fpc", FPI },
2670 { "fps", FPS },
2671 { "fpsr", FPS },
2672 { "fpc", FPC },
2673 { "fpcr", FPC },
2674 { "control", FPC },
2675 { "status", FPS },
2676 { "iaddr", FPI },
2677
2678 { "cop0", COP0 },
2679 { "cop1", COP1 },
2680 { "cop2", COP2 },
2681 { "cop3", COP3 },
2682 { "cop4", COP4 },
2683 { "cop5", COP5 },
2684 { "cop6", COP6 },
2685 { "cop7", COP7 },
2686 { "pc", PC },
2687 { "zpc", ZPC },
2688 { "sr", SR },
2689
2690 { "ccr", CCR },
2691 { "cc", CCR },
2692
2693 { "usp", USP },
2694 { "isp", ISP },
2695 { "sfc", SFC },
2696 { "sfcr", SFC },
2697 { "dfc", DFC },
2698 { "dfcr", DFC },
2699 { "cacr", CACR },
2700 { "caar", CAAR },
2701
2702 { "vbr", VBR },
2703
2704 { "msp", MSP },
2705 { "itt0", ITT0 },
2706 { "itt1", ITT1 },
2707 { "dtt0", DTT0 },
2708 { "dtt1", DTT1 },
2709 { "mmusr", MMUSR },
2710 { "tc", TC },
2711 { "srp", SRP },
2712 { "urp", URP },
2713 { "buscr", BUSCR },
2714 { "pcr", PCR },
2715
2716 { "ac", AC },
2717 { "bc", BC },
2718 { "cal", CAL },
2719 { "crp", CRP },
2720 { "drp", DRP },
2721 { "pcsr", PCSR },
2722 { "psr", PSR },
2723 { "scc", SCC },
2724 { "val", VAL },
2725 { "bad0", BAD0 },
2726 { "bad1", BAD1 },
2727 { "bad2", BAD2 },
2728 { "bad3", BAD3 },
2729 { "bad4", BAD4 },
2730 { "bad5", BAD5 },
2731 { "bad6", BAD6 },
2732 { "bad7", BAD7 },
2733 { "bac0", BAC0 },
2734 { "bac1", BAC1 },
2735 { "bac2", BAC2 },
2736 { "bac3", BAC3 },
2737 { "bac4", BAC4 },
2738 { "bac5", BAC5 },
2739 { "bac6", BAC6 },
2740 { "bac7", BAC7 },
2741
2742 { "ic", IC },
2743 { "dc", DC },
2744 { "nc", NC },
2745
2746 { "tt0", TT0 },
2747 { "tt1", TT1 },
2748 /* 68ec030 versions of same */
2749 { "ac0", TT0 },
2750 { "ac1", TT1 },
2751 /* 68ec030 access control unit, identical to 030 MMU status reg */
2752 { "acusr", PSR },
2753
2754 /* Suppressed data and address registers. */
2755 { "zd0", ZDATA0 },
2756 { "zd1", ZDATA1 },
2757 { "zd2", ZDATA2 },
2758 { "zd3", ZDATA3 },
2759 { "zd4", ZDATA4 },
2760 { "zd5", ZDATA5 },
2761 { "zd6", ZDATA6 },
2762 { "zd7", ZDATA7 },
2763 { "za0", ZADDR0 },
2764 { "za1", ZADDR1 },
2765 { "za2", ZADDR2 },
2766 { "za3", ZADDR3 },
2767 { "za4", ZADDR4 },
2768 { "za5", ZADDR5 },
2769 { "za6", ZADDR6 },
2770 { "za7", ZADDR7 },
2771
2772 { 0, 0 }
2773};
2774
2775void
2776init_regtable ()
2777{
2778 int i;
2779 for (i = 0; init_table[i].name; i++)
2780 insert_reg (init_table[i].name, init_table[i].number);
2781}
2782
2783static int no_68851, no_68881;
2784
2785#ifdef OBJ_AOUT
2786/* a.out machine type. Default to 68020. */
2787int m68k_aout_machtype = 2;
2788#endif
2789
2790void
2791md_assemble (str)
2792 char *str;
2793{
2794 const char *er;
2795 short *fromP;
2796 char *toP = NULL;
2797 int m, n = 0;
2798 char *to_beg_P;
2799 int shorts_this_frag;
2800 fixS *fixP;
2801
2802 /* In MRI mode, the instruction and operands are separated by a
2803 space. Anything following the operands is a comment. The label
2804 has already been removed. */
2805 if (flag_mri)
2806 {
2807 char *s;
2808 int fields = 0;
2809 int infield = 0;
2810 int inquote = 0;
2811
2812 for (s = str; *s != '\0'; s++)
2813 {
2814 if ((*s == ' ' || *s == '\t') && ! inquote)
2815 {
2816 if (infield)
2817 {
2818 ++fields;
2819 if (fields >= 2)
2820 {
2821 *s = '\0';
2822 break;
2823 }
2824 infield = 0;
2825 }
2826 }
2827 else
2828 {
2829 if (! infield)
2830 infield = 1;
2831 if (*s == '\'')
2832 inquote = ! inquote;
2833 }
2834 }
2835 }
2836
2837 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
2838 m68k_ip (str);
2839 er = the_ins.error;
2840 if (!er)
2841 {
2842 for (n = 0; n < the_ins.numargs; n++)
2843 if (the_ins.operands[n].error)
2844 {
2845 er = the_ins.operands[n].error;
2846 break;
2847 }
2848 }
2849 if (er)
2850 {
2851 as_bad ("%s -- statement `%s' ignored", er, str);
2852 return;
2853 }
2854
2855 if (the_ins.nfrag == 0)
2856 {
2857 /* No frag hacking involved; just put it out */
2858 toP = frag_more (2 * the_ins.numo);
2859 fromP = &the_ins.opcode[0];
2860 for (m = the_ins.numo; m; --m)
2861 {
2862 md_number_to_chars (toP, (long) (*fromP), 2);
2863 toP += 2;
2864 fromP++;
2865 }
2866 /* put out symbol-dependent info */
2867 for (m = 0; m < the_ins.nrel; m++)
2868 {
2869 switch (the_ins.reloc[m].wid)
2870 {
2871 case 'B':
2872 n = 1;
2873 break;
2874 case 'b':
2875 n = 1;
2876 break;
2877 case '3':
2878 n = 2;
2879 break;
2880 case 'w':
2881 n = 2;
2882 break;
2883 case 'l':
2884 n = 4;
2885 break;
2886 default:
2887 as_fatal ("Don't know how to figure width of %c in md_assemble()",
2888 the_ins.reloc[m].wid);
2889 }
2890
2891 fixP = fix_new_exp (frag_now,
2892 ((toP - frag_now->fr_literal)
2893 - the_ins.numo * 2 + the_ins.reloc[m].n),
2894 n,
2895 &the_ins.reloc[m].exp,
2896 the_ins.reloc[m].pcrel,
2897 NO_RELOC);
2898 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2899 }
2900 return;
2901 }
2902
2903 /* There's some frag hacking */
2904 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
2905 {
2906 int wid;
2907
2908 if (n == 0)
2909 wid = 2 * the_ins.fragb[n].fragoff;
2910 else
2911 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
2912 toP = frag_more (wid);
2913 to_beg_P = toP;
2914 shorts_this_frag = 0;
2915 for (m = wid / 2; m; --m)
2916 {
2917 md_number_to_chars (toP, (long) (*fromP), 2);
2918 toP += 2;
2919 fromP++;
2920 shorts_this_frag++;
2921 }
2922 for (m = 0; m < the_ins.nrel; m++)
2923 {
2924 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
2925 {
2926 the_ins.reloc[m].n -= 2 * shorts_this_frag;
2927 break;
2928 }
2929 wid = the_ins.reloc[m].wid;
2930 if (wid == 0)
2931 continue;
2932 the_ins.reloc[m].wid = 0;
2933 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
2934
2935 fixP = fix_new_exp (frag_now,
2936 ((toP - frag_now->fr_literal)
2937 - the_ins.numo * 2 + the_ins.reloc[m].n),
2938 wid,
2939 &the_ins.reloc[m].exp,
2940 the_ins.reloc[m].pcrel,
2941 NO_RELOC);
2942 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2943 }
2944 (void) frag_var (rs_machine_dependent, 10, 0,
2945 (relax_substateT) (the_ins.fragb[n].fragty),
2946 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
2947 }
2948 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
2949 shorts_this_frag = 0;
2950 if (n)
2951 {
2952 toP = frag_more (n * sizeof (short));
2953 while (n--)
2954 {
2955 md_number_to_chars (toP, (long) (*fromP), 2);
2956 toP += 2;
2957 fromP++;
2958 shorts_this_frag++;
2959 }
2960 }
2961 for (m = 0; m < the_ins.nrel; m++)
2962 {
2963 int wid;
2964
2965 wid = the_ins.reloc[m].wid;
2966 if (wid == 0)
2967 continue;
2968 the_ins.reloc[m].wid = 0;
2969 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
2970
2971 fixP = fix_new_exp (frag_now,
2972 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
2973 - shorts_this_frag * 2),
2974 wid,
2975 &the_ins.reloc[m].exp,
2976 the_ins.reloc[m].pcrel,
2977 NO_RELOC);
2978 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2979 }
2980}
2981
2982void
2983md_begin ()
2984{
2985 /*
2986 * md_begin -- set up hash tables with 68000 instructions.
2987 * similar to what the vax assembler does. ---phr
2988 */
2989 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
2990 a copy of it at runtime, adding in the information we want but isn't
2991 there. I think it'd be better to have an awk script hack the table
2992 at compile time. Or even just xstr the table and use it as-is. But
2993 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
2994 names. */
2995
2996 register const struct m68k_opcode *ins;
2997 register struct m68k_incant *hack, *slak;
2998 register const char *retval = 0; /* empty string, or error msg text */
2999 register unsigned int i;
3000 register char c;
3001
3002 if (flag_mri)
3003 {
3004 flag_reg_prefix_optional = 1;
3005 m68k_abspcadd = 1;
3006 m68k_rel32 = 0;
3007 }
3008
3009 op_hash = hash_new ();
3010
3011 obstack_begin (&robyn, 4000);
3012 for (i = 0; i < m68k_numopcodes; i++)
3013 {
3014 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3015 do
3016 {
3017 ins = &m68k_opcodes[i];
3018 /* We *could* ignore insns that don't match our arch here
3019 but just leaving them out of the hash. */
3020 slak->m_operands = ins->args;
3021 slak->m_opnum = strlen (slak->m_operands) / 2;
3022 slak->m_arch = ins->arch;
3023 slak->m_opcode = ins->opcode;
3024 /* This is kludgey */
3025 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3026 if (i + 1 != m68k_numopcodes
3027 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3028 {
3029 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3030 i++;
3031 }
3032 else
3033 slak->m_next = 0;
3034 slak = slak->m_next;
3035 }
3036 while (slak);
3037
3038 retval = hash_insert (op_hash, ins->name, (char *) hack);
3039 if (retval)
3040 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3041 }
3042
3043 for (i = 0; i < m68k_numaliases; i++)
3044 {
3045 const char *name = m68k_opcode_aliases[i].primary;
3046 const char *alias = m68k_opcode_aliases[i].alias;
3047 PTR val = hash_find (op_hash, name);
3048 if (!val)
3049 as_fatal ("Internal Error: Can't find %s in hash table", name);
3050 retval = hash_insert (op_hash, alias, val);
3051 if (retval)
3052 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3053 }
3054
3055 /* In MRI mode, all unsized branches are variable sized. Normally,
3056 they are word sized. */
3057 if (flag_mri)
3058 {
3059 static struct m68k_opcode_alias mri_aliases[] =
3060 {
3061 { "bhi", "jhi", },
3062 { "bls", "jls", },
3063 { "bcc", "jcc", },
3064 { "bcs", "jcs", },
3065 { "bne", "jne", },
3066 { "beq", "jeq", },
3067 { "bvc", "jvc", },
3068 { "bvs", "jvs", },
3069 { "bpl", "jpl", },
3070 { "bmi", "jmi", },
3071 { "bge", "jge", },
3072 { "blt", "jlt", },
3073 { "bgt", "jgt", },
3074 { "ble", "jle", },
3075 { "bra", "jra", },
3076 { "bsr", "jbsr", },
3077 };
3078
3079 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3080 {
3081 const char *name = mri_aliases[i].primary;
3082 const char *alias = mri_aliases[i].alias;
3083 PTR val = hash_find (op_hash, name);
3084 if (!val)
3085 as_fatal ("Internal Error: Can't find %s in hash table", name);
3086 retval = hash_jam (op_hash, alias, val);
3087 if (retval)
3088 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3089 }
3090 }
3091
3092 for (i = 0; i < sizeof (mklower_table); i++)
3093 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3094
3095 for (i = 0; i < sizeof (notend_table); i++)
3096 {
3097 notend_table[i] = 0;
3098 alt_notend_table[i] = 0;
3099 }
3100 notend_table[','] = 1;
3101 notend_table['{'] = 1;
3102 notend_table['}'] = 1;
3103 alt_notend_table['a'] = 1;
3104 alt_notend_table['A'] = 1;
3105 alt_notend_table['d'] = 1;
3106 alt_notend_table['D'] = 1;
3107 alt_notend_table['#'] = 1;
3108 alt_notend_table['&'] = 1;
3109 alt_notend_table['f'] = 1;
3110 alt_notend_table['F'] = 1;
3111#ifdef REGISTER_PREFIX
3112 alt_notend_table[REGISTER_PREFIX] = 1;
3113#endif
3114
3115 /* We need to put '(' in alt_notend_table to handle
3116 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3117 */
3118 alt_notend_table['('] = 1;
3119
3120 /* We need to put '@' in alt_notend_table to handle
3121 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3122 */
3123 alt_notend_table['@'] = 1;
3124
3125#ifndef MIT_SYNTAX_ONLY
3126 /* Insert pseudo ops, these have to go into the opcode table since
3127 gas expects pseudo ops to start with a dot */
3128 {
3129 int n = 0;
3130 while (mote_pseudo_table[n].poc_name)
3131 {
3132 hack = (struct m68k_incant *)
3133 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3134 hash_insert (op_hash,
3135 mote_pseudo_table[n].poc_name, (char *) hack);
3136 hack->m_operands = 0;
3137 hack->m_opnum = n;
3138 n++;
3139 }
3140 }
3141#endif
3142
3143 init_regtable ();
3144}
3145
3146void
3147m68k_init_after_args ()
3148{
3149 if (cpu_of_arch (current_architecture) == 0)
3150 {
3151 int i;
3152 const char *default_cpu = TARGET_CPU;
3153
3154 if (*default_cpu == 'm')
3155 default_cpu++;
3156 for (i = 0; i < n_archs; i++)
3157 if (strcasecmp (default_cpu, archs[i].name) == 0)
3158 break;
3159 if (i == n_archs)
3160 {
3161 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3162 current_architecture |= m68020;
3163 }
3164 else
3165 current_architecture |= archs[i].arch;
3166 }
3167 /* Permit m68881 specification with all cpus; those that can't work
3168 with a coprocessor could be doing emulation. */
3169 if (current_architecture & m68851)
3170 {
3171 if (current_architecture & m68040)
3172 {
3173 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3174 }
3175 }
3176 /* What other incompatibilities could we check for? */
3177
3178 /* Toss in some default assumptions about coprocessors. */
3179 if (!no_68881
3180 && (cpu_of_arch (current_architecture)
3181 /* Can CPU32 have a 68881 coprocessor?? */
3182 & (m68020 | m68030 | cpu32)))
3183 {
3184 current_architecture |= m68881;
3185 }
3186 if (!no_68851
3187 && (cpu_of_arch (current_architecture) & m68020up) != 0
3188 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3189 {
3190 current_architecture |= m68851;
3191 }
3192 if (no_68881 && (current_architecture & m68881))
3193 as_bad ("options for 68881 and no-68881 both given");
3194 if (no_68851 && (current_architecture & m68851))
3195 as_bad ("options for 68851 and no-68851 both given");
3196
3197#ifdef OBJ_AOUT
3198 /* Work out the magic number. This isn't very general. */
3199 if (current_architecture & m68000)
3200 m68k_aout_machtype = 0;
3201 else if (current_architecture & m68010)
3202 m68k_aout_machtype = 1;
3203 else if (current_architecture & m68020)
3204 m68k_aout_machtype = 2;
3205 else
3206 m68k_aout_machtype = 2;
3207#endif
3208
3209 /* Note which set of "movec" control registers is available. */
3210 switch (cpu_of_arch (current_architecture))
3211 {
3212 case m68000:
3213 control_regs = m68000_control_regs;
3214 break;
3215 case m68010:
3216 control_regs = m68010_control_regs;
3217 break;
3218 case m68020:
3219 case m68030:
3220 control_regs = m68020_control_regs;
3221 break;
3222 case m68040:
3223 control_regs = m68040_control_regs;
3224 break;
3225 case m68060:
3226 control_regs = m68060_control_regs;
3227 break;
3228 case cpu32:
3229 control_regs = cpu32_control_regs;
3230 break;
3231 default:
3232 abort ();
3233 }
3234
3235 if (cpu_of_arch (current_architecture) < m68020)
3236 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3237}
3238
3239/* Equal to MAX_PRECISION in atof-ieee.c */
3240#define MAX_LITTLENUMS 6
3241
3242/* Turn a string in input_line_pointer into a floating point constant
3243 of type type, and store the appropriate bytes in *litP. The number
3244 of LITTLENUMS emitted is stored in *sizeP . An error message is
3245 returned, or NULL on OK. */
3246
3247char *
3248md_atof (type, litP, sizeP)
3249 char type;
3250 char *litP;
3251 int *sizeP;
3252{
3253 int prec;
3254 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3255 LITTLENUM_TYPE *wordP;
3256 char *t;
3257 char *atof_ieee ();
3258
3259 switch (type)
3260 {
3261 case 'f':
3262 case 'F':
3263 case 's':
3264 case 'S':
3265 prec = 2;
3266 break;
3267
3268 case 'd':
3269 case 'D':
3270 case 'r':
3271 case 'R':
3272 prec = 4;
3273 break;
3274
3275 case 'x':
3276 case 'X':
3277 prec = 6;
3278 break;
3279
3280 case 'p':
3281 case 'P':
3282 prec = 6;
3283 break;
3284
3285 default:
3286 *sizeP = 0;
3287 return "Bad call to MD_ATOF()";
3288 }
3289 t = atof_ieee (input_line_pointer, type, words);
3290 if (t)
3291 input_line_pointer = t;
3292
3293 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3294 for (wordP = words; prec--;)
3295 {
3296 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3297 litP += sizeof (LITTLENUM_TYPE);
3298 }
3299 return 0;
3300}
3301
3302void
3303md_number_to_chars (buf, val, n)
3304 char *buf;
3305 valueT val;
3306 int n;
3307{
3308 number_to_chars_bigendian (buf, val, n);
3309}
3310
3311static void
3312md_apply_fix_2 (fixP, val)
3313 fixS *fixP;
3314 offsetT val;
3315{
3316 addressT upper_limit;
3317 offsetT lower_limit;
3318
3319 /* This is unnecessary but it convinces the native rs6000 compiler
3320 to generate the code we want. */
3321 char *buf = fixP->fx_frag->fr_literal;
3322 buf += fixP->fx_where;
3323 /* end ibm compiler workaround */
3324
3325 if (val & 0x80000000)
3326 val |= ~(addressT)0x7fffffff;
3327 else
3328 val &= 0x7fffffff;
3329
3330 switch (fixP->fx_size)
3331 {
3332 /* The cast to offsetT below are necessary to make code correct for
3333 machines where ints are smaller than offsetT */
3334 case 1:
3335 *buf++ = val;
3336 upper_limit = 0x7f;
3337 lower_limit = - (offsetT) 0x80;
3338 break;
3339 case 2:
3340 *buf++ = (val >> 8);
3341 *buf++ = val;
3342 upper_limit = 0x7fff;
3343 lower_limit = - (offsetT) 0x8000;
3344 break;
3345 case 4:
3346 *buf++ = (val >> 24);
3347 *buf++ = (val >> 16);
3348 *buf++ = (val >> 8);
3349 *buf++ = val;
3350 upper_limit = 0x7fffffff;
3351 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
3352 break;
3353 default:
3354 BAD_CASE (fixP->fx_size);
3355 }
3356
3357 /* For non-pc-relative values, it's conceivable we might get something
3358 like "0xff" for a byte field. So extend the upper part of the range
3359 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3360 so that we can do any range checking at all. */
3361 if (!fixP->fx_pcrel)
3362 upper_limit = upper_limit * 2 + 1;
3363
3364 if ((addressT) val > upper_limit
3365 && (val > 0 || val < lower_limit))
3366 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
3367
3368 /* A one byte PC-relative reloc means a short branch. We can't use
3369 a short branch with a value of 0 or -1, because those indicate
3370 different opcodes (branches with longer offsets). */
3371 if (fixP->fx_pcrel
3372 && fixP->fx_size == 1
3373 && (fixP->fx_addsy == NULL
3374 || S_IS_DEFINED (fixP->fx_addsy))
3375 && (val == 0 || val == -1))
3376 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
3377}
3378
3379#ifdef BFD_ASSEMBLER
3380int
3381md_apply_fix (fixP, valp)
3382 fixS *fixP;
3383 valueT *valp;
3384{
3385 md_apply_fix_2 (fixP, (addressT) *valp);
3386 return 1;
3387}
3388#else
3389void md_apply_fix (fixP, val)
3390 fixS *fixP;
3391 long val;
3392{
3393 md_apply_fix_2 (fixP, (addressT) val);
3394}
3395#endif
3396
3397/* *fragP has been relaxed to its final size, and now needs to have
3398 the bytes inside it modified to conform to the new size There is UGLY
3399 MAGIC here. ..
3400 */
3401void
3402md_convert_frag_1 (fragP)
3403 register fragS *fragP;
3404{
3405 long disp;
3406 long ext = 0;
3407 fixS *fixP;
3408
3409 /* Address in object code of the displacement. */
3410 register int object_address = fragP->fr_fix + fragP->fr_address;
3411
3412 /* Address in gas core of the place to store the displacement. */
3413 /* This convinces the native rs6000 compiler to generate the code we
3414 want. */
3415 register char *buffer_address = fragP->fr_literal;
3416 buffer_address += fragP->fr_fix;
3417 /* end ibm compiler workaround */
3418
3419 /* The displacement of the address, from current location. */
3420 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
3421 disp = (disp + fragP->fr_offset) - object_address;
3422
3423#ifdef BFD_ASSEMBLER
3424 disp += fragP->fr_symbol->sy_frag->fr_address;
3425#endif
3426
3427 switch (fragP->fr_subtype)
3428 {
3429 case TAB (BCC68000, BYTE):
3430 case TAB (ABRANCH, BYTE):
3431 know (issbyte (disp));
3432 if (disp == 0)
3433 as_bad ("short branch with zero offset: use :w");
3434 fragP->fr_opcode[1] = disp;
3435 ext = 0;
3436 break;
3437 case TAB (DBCC, SHORT):
3438 know (issword (disp));
3439 ext = 2;
3440 break;
3441 case TAB (BCC68000, SHORT):
3442 case TAB (ABRANCH, SHORT):
3443 know (issword (disp));
3444 fragP->fr_opcode[1] = 0x00;
3445 ext = 2;
3446 break;
3447 case TAB (ABRANCH, LONG):
3448 if (cpu_of_arch (current_architecture) < m68020)
3449 {
3450 if (fragP->fr_opcode[0] == 0x61)
3451 /* BSR */
3452 {
3453 fragP->fr_opcode[0] = 0x4E;
3454 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3455
3456 fix_new (fragP,
3457 fragP->fr_fix,
3458 4,
3459 fragP->fr_symbol,
3460 fragP->fr_offset,
3461 0,
3462 NO_RELOC);
3463
3464 fragP->fr_fix += 4;
3465 ext = 0;
3466 }
3467 /* BRA */
3468 else if (fragP->fr_opcode[0] == 0x60)
3469 {
3470 fragP->fr_opcode[0] = 0x4E;
3471 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3472 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3473 fragP->fr_offset, 0, NO_RELOC);
3474 fragP->fr_fix += 4;
3475 ext = 0;
3476 }
3477 else
3478 {
3479 as_bad ("Long branch offset not supported.");
3480 }
3481 }
3482 else
3483 {
3484 fragP->fr_opcode[1] = (char) 0xff;
3485 ext = 4;
3486 }
3487 break;
3488 case TAB (BCC68000, LONG):
3489 /* only Bcc 68000 instructions can come here */
3490 /* change bcc into b!cc/jmp absl long */
3491 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3492 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
3493
3494 /* JF: these used to be fr_opcode[2,3], but they may be in a
3495 different frag, in which case refering to them is a no-no.
3496 Only fr_opcode[0,1] are guaranteed to work. */
3497 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3498 *buffer_address++ = (char) 0xf9;
3499 fragP->fr_fix += 2; /* account for jmp instruction */
3500 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3501 fragP->fr_offset, 0, NO_RELOC);
3502 fragP->fr_fix += 4;
3503 ext = 0;
3504 break;
3505 case TAB (DBCC, LONG):
3506 /* only DBcc 68000 instructions can come here */
3507 /* change dbcc into dbcc/jmp absl long */
3508 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3509 *buffer_address++ = 0x00; /* branch offset = 4 */
3510 *buffer_address++ = 0x04;
3511 *buffer_address++ = 0x60; /* put in bra pc+6 */
3512 *buffer_address++ = 0x06;
3513 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3514 *buffer_address++ = (char) 0xf9;
3515
3516 fragP->fr_fix += 6; /* account for bra/jmp instructions */
3517 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3518 fragP->fr_offset, 0, NO_RELOC);
3519 fragP->fr_fix += 4;
3520 ext = 0;
3521 break;
3522 case TAB (FBRANCH, SHORT):
3523 know ((fragP->fr_opcode[1] & 0x40) == 0);
3524 ext = 2;
3525 break;
3526 case TAB (FBRANCH, LONG):
3527 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3528 ext = 4;
3529 break;
3530 case TAB (PCREL, SHORT):
3531 ext = 2;
3532 break;
3533 case TAB (PCREL, LONG):
3534 /* The thing to do here is force it to ABSOLUTE LONG, since
3535 PCREL is really trying to shorten an ABSOLUTE address anyway */
3536 /* JF FOO This code has not been tested */
3537 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3538 0, NO_RELOC);
3539 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
3540 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
3541 (unsigned) fragP->fr_opcode[0],
3542 (unsigned long) fragP->fr_address);
3543 fragP->fr_opcode[1] &= ~0x3F;
3544 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
3545 fragP->fr_fix += 4;
3546 ext = 0;
3547 break;
3548 case TAB (PCLEA, SHORT):
3549 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3550 fragP->fr_offset, 1, NO_RELOC);
3551 fragP->fr_opcode[1] &= ~0x3F;
3552 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
3553 ext = 2;
3554 break;
3555 case TAB (PCLEA, LONG):
3556 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
3557 fragP->fr_offset, 1, NO_RELOC);
3558 fixP->fx_pcrel_adjust = 2;
3559 /* Already set to mode 7.3; this indicates: PC indirect with
3560 suppressed index, 32-bit displacement. */
3561 *buffer_address++ = 0x01;
3562 *buffer_address++ = 0x70;
3563 fragP->fr_fix += 2;
3564 ext = 4;
3565 break;
3566
3567 case TAB (PCINDEX, BYTE):
3568 disp += 2;
3569 if (!issbyte (disp))
3570 {
3571 as_bad ("displacement doesn't fit in one byte");
3572 disp = 0;
3573 }
3574 assert (fragP->fr_fix >= 2);
3575 buffer_address[-2] &= ~1;
3576 buffer_address[-1] = disp;
3577 ext = 0;
3578 break;
3579 case TAB (PCINDEX, SHORT):
3580 disp += 2;
3581 assert (issword (disp));
3582 assert (fragP->fr_fix >= 2);
3583 buffer_address[-2] |= 0x1;
3584 buffer_address[-1] = 0x20;
3585 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3586 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3587 NO_RELOC);
3588 fixP->fx_pcrel_adjust = 2;
3589 ext = 2;
3590 break;
3591 case TAB (PCINDEX, LONG):
3592 disp += 2;
3593 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3594 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3595 NO_RELOC);
3596 fixP->fx_pcrel_adjust = 2;
3597 assert (fragP->fr_fix >= 2);
3598 buffer_address[-2] |= 0x1;
3599 buffer_address[-1] = 0x30;
3600 ext = 4;
3601 break;
3602 }
3603
3604 if (ext)
3605 {
3606 md_number_to_chars (buffer_address, (long) disp, (int) ext);
3607 fragP->fr_fix += ext;
3608 }
3609}
3610
3611#ifndef BFD_ASSEMBLER
3612
3613void
3614md_convert_frag (headers, sec, fragP)
3615 object_headers *headers;
3616 segT sec;
3617 fragS *fragP;
3618{
3619 md_convert_frag_1 (fragP);
3620}
3621
3622#else
3623
3624void
3625md_convert_frag (abfd, sec, fragP)
3626 bfd *abfd;
3627 segT sec;
3628 fragS *fragP;
3629{
3630 md_convert_frag_1 (fragP);
3631}
3632#endif
3633
3634/* Force truly undefined symbols to their maximum size, and generally set up
3635 the frag list to be relaxed
3636 */
3637int
3638md_estimate_size_before_relax (fragP, segment)
3639 register fragS *fragP;
3640 segT segment;
3641{
3642 int old_fix;
3643 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
3644
3645 old_fix = fragP->fr_fix;
3646
3647 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3648 switch (fragP->fr_subtype)
3649 {
3650
3651 case TAB (ABRANCH, SZ_UNDEF):
3652 {
3653 if ((fragP->fr_symbol != NULL) /* Not absolute */
3654 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3655 {
3656 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
3657 break;
3658 }
3659 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
3660 {
3661 /* On 68000, or for absolute value, switch to abs long */
3662 /* FIXME, we should check abs val, pick short or long */
3663 if (fragP->fr_opcode[0] == 0x61)
3664 {
3665 fragP->fr_opcode[0] = 0x4E;
3666 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3667 fix_new (fragP, fragP->fr_fix, 4,
3668 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3669 fragP->fr_fix += 4;
3670 frag_wane (fragP);
3671 }
3672 else if (fragP->fr_opcode[0] == 0x60)
3673 {
3674 fragP->fr_opcode[0] = 0x4E;
3675 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3676 fix_new (fragP, fragP->fr_fix, 4,
3677 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3678 fragP->fr_fix += 4;
3679 frag_wane (fragP);
3680 }
3681 else
3682 {
3683 as_warn ("Long branch offset to extern symbol not supported.");
3684 }
3685 }
3686 else
3687 { /* Symbol is still undefined. Make it simple */
3688 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3689 fragP->fr_offset, 1, NO_RELOC);
3690 fragP->fr_fix += 4;
3691 fragP->fr_opcode[1] = (char) 0xff;
3692 frag_wane (fragP);
3693 break;
3694 }
3695
3696 break;
3697 } /* case TAB(ABRANCH,SZ_UNDEF) */
3698
3699 case TAB (FBRANCH, SZ_UNDEF):
3700 {
3701 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
3702 {
3703 fragP->fr_subtype = TAB (FBRANCH, SHORT);
3704 fragP->fr_var += 2;
3705 }
3706 else
3707 {
3708 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
3709 fragP->fr_offset, 1, NO_RELOC);
3710 fragP->fr_fix += 4;
3711 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3712 frag_wane (fragP);
3713 }
3714 break;
3715 } /* TAB(FBRANCH,SZ_UNDEF) */
3716
3717 case TAB (PCREL, SZ_UNDEF):
3718 {
3719 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
3720 || flag_short_refs
3721 || cpu_of_arch (current_architecture) < m68020)
3722 {
3723 fragP->fr_subtype = TAB (PCREL, SHORT);
3724 fragP->fr_var += 2;
3725 }
3726 else
3727 {
3728 fragP->fr_subtype = TAB (PCREL, LONG);
3729 fragP->fr_var += 4;
3730 }
3731 break;
3732 } /* TAB(PCREL,SZ_UNDEF) */
3733
3734 case TAB (BCC68000, SZ_UNDEF):
3735 {
3736 if ((fragP->fr_symbol != NULL)
3737 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3738 {
3739 fragP->fr_subtype = TAB (BCC68000, BYTE);
3740 break;
3741 }
3742 /* only Bcc 68000 instructions can come here */
3743 /* change bcc into b!cc/jmp absl long */
3744 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3745 if (flag_short_refs)
3746 {
3747 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
3748 /* JF: these were fr_opcode[2,3] */
3749 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3750 buffer_address[1] = (char) 0xf8;
3751 fragP->fr_fix += 2; /* account for jmp instruction */
3752 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
3753 fragP->fr_offset, 0, NO_RELOC);
3754 fragP->fr_fix += 2;
3755 }
3756 else
3757 {
3758 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
3759 /* JF: these were fr_opcode[2,3] */
3760 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3761 buffer_address[1] = (char) 0xf9;
3762 fragP->fr_fix += 2; /* account for jmp instruction */
3763 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3764 fragP->fr_offset, 0, NO_RELOC);
3765 fragP->fr_fix += 4;
3766 }
3767 frag_wane (fragP);
3768 break;
3769 } /* case TAB(BCC68000,SZ_UNDEF) */
3770
3771 case TAB (DBCC, SZ_UNDEF):
3772 {
3773 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3774 {
3775 fragP->fr_subtype = TAB (DBCC, SHORT);
3776 fragP->fr_var += 2;
3777 break;
3778 }
3779 /* only DBcc 68000 instructions can come here */
3780 /* change dbcc into dbcc/jmp absl long */
3781 /* JF: these used to be fr_opcode[2-4], which is wrong. */
3782 buffer_address[0] = 0x00; /* branch offset = 4 */
3783 buffer_address[1] = 0x04;
3784 buffer_address[2] = 0x60; /* put in bra pc + ... */
3785
3786 if (flag_short_refs)
3787 {
3788 /* JF: these were fr_opcode[5-7] */
3789 buffer_address[3] = 0x04; /* plus 4 */
3790 buffer_address[4] = 0x4e; /* Put in Jump Word */
3791 buffer_address[5] = (char) 0xf8;
3792 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3793 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
3794 fragP->fr_offset, 0, NO_RELOC);
3795 fragP->fr_fix += 2;
3796 }
3797 else
3798 {
3799 /* JF: these were fr_opcode[5-7] */
3800 buffer_address[3] = 0x06; /* Plus 6 */
3801 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
3802 buffer_address[5] = (char) 0xf9;
3803 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3804 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3805 fragP->fr_offset, 0, NO_RELOC);
3806 fragP->fr_fix += 4;
3807 }
3808
3809 frag_wane (fragP);
3810 break;
3811 } /* case TAB(DBCC,SZ_UNDEF) */
3812
3813 case TAB (PCLEA, SZ_UNDEF):
3814 {
3815 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
3816 || flag_short_refs
3817 || cpu_of_arch (current_architecture) < m68020)
3818 {
3819 fragP->fr_subtype = TAB (PCLEA, SHORT);
3820 fragP->fr_var += 2;
3821 }
3822 else
3823 {
3824 fragP->fr_subtype = TAB (PCLEA, LONG);
3825 fragP->fr_var += 6;
3826 }
3827 break;
3828 } /* TAB(PCLEA,SZ_UNDEF) */
3829
3830 case TAB (PCINDEX, SZ_UNDEF):
3831 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
3832 || cpu_of_arch (current_architecture) < m68020)
3833 {
3834 fragP->fr_subtype = TAB (PCINDEX, BYTE);
3835 }
3836 else
3837 {
3838 fragP->fr_subtype = TAB (PCINDEX, LONG);
3839 fragP->fr_var += 4;
3840 }
3841 break;
3842
3843 default:
3844 break;
3845 }
3846
3847 /* now that SZ_UNDEF are taken care of, check others */
3848 switch (fragP->fr_subtype)
3849 {
3850 case TAB (BCC68000, BYTE):
3851 case TAB (ABRANCH, BYTE):
3852 /* We can't do a short jump to the next instruction,
3853 so we force word mode. */
3854 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0 &&
3855 fragP->fr_symbol->sy_frag == fragP->fr_next)
3856 {
3857 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
3858 fragP->fr_var += 2;
3859 }
3860 break;
3861 default:
3862 break;
3863 }
3864 return fragP->fr_var + fragP->fr_fix - old_fix;
3865}
3866
3867#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
3868/* the bit-field entries in the relocation_info struct plays hell
3869 with the byte-order problems of cross-assembly. So as a hack,
3870 I added this mach. dependent ri twiddler. Ugly, but it gets
3871 you there. -KWK */
3872/* on m68k: first 4 bytes are normal unsigned long, next three bytes
3873 are symbolnum, most sig. byte first. Last byte is broken up with
3874 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
3875 nibble as nuthin. (on Sun 3 at least) */
3876/* Translate the internal relocation information into target-specific
3877 format. */
3878#ifdef comment
3879void
3880md_ri_to_chars (the_bytes, ri)
3881 char *the_bytes;
3882 struct reloc_info_generic *ri;
3883{
3884 /* this is easy */
3885 md_number_to_chars (the_bytes, ri->r_address, 4);
3886 /* now the fun stuff */
3887 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
3888 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
3889 the_bytes[6] = ri->r_symbolnum & 0x0ff;
3890 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
3891 ((ri->r_extern << 4) & 0x10));
3892}
3893
3894#endif /* comment */
3895
3896#ifndef BFD_ASSEMBLER
3897void
3898tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
3899 char *where;
3900 fixS *fixP;
3901 relax_addressT segment_address_in_file;
3902{
3903 /*
3904 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3905 * Out: GNU LD relocation length code: 0, 1, or 2.
3906 */
3907
3908 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
3909 long r_symbolnum;
3910
3911 know (fixP->fx_addsy != NULL);
3912
3913 md_number_to_chars (where,
3914 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
3915 4);
3916
3917 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
3918 ? S_GET_TYPE (fixP->fx_addsy)
3919 : fixP->fx_addsy->sy_number);
3920
3921 where[4] = (r_symbolnum >> 16) & 0x0ff;
3922 where[5] = (r_symbolnum >> 8) & 0x0ff;
3923 where[6] = r_symbolnum & 0x0ff;
3924 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
3925 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
3926}
3927#endif
3928
3929#endif /* OBJ_AOUT or OBJ_BOUT */
3930
3931#ifndef WORKING_DOT_WORD
3932CONST int md_short_jump_size = 4;
3933CONST int md_long_jump_size = 6;
3934
3935void
3936md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
3937 char *ptr;
3938 addressT from_addr, to_addr;
3939 fragS *frag;
3940 symbolS *to_symbol;
3941{
3942 valueT offset;
3943
3944 offset = to_addr - (from_addr + 2);
3945
3946 md_number_to_chars (ptr, (valueT) 0x6000, 2);
3947 md_number_to_chars (ptr + 2, (valueT) offset, 2);
3948}
3949
3950void
3951md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
3952 char *ptr;
3953 addressT from_addr, to_addr;
3954 fragS *frag;
3955 symbolS *to_symbol;
3956{
3957 valueT offset;
3958
3959 if (cpu_of_arch (current_architecture) < m68020)
3960 {
3961 offset = to_addr - S_GET_VALUE (to_symbol);
3962 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
3963 md_number_to_chars (ptr + 2, (valueT) offset, 4);
3964 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
3965 0, NO_RELOC);
3966 }
3967 else
3968 {
3969 offset = to_addr - (from_addr + 2);
3970 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
3971 md_number_to_chars (ptr + 2, (valueT) offset, 4);
3972 }
3973}
3974
3975#endif
3976
3977/* Different values of OK tell what its OK to return. Things that
3978 aren't OK are an error (what a shock, no?)
3979
3980 0: Everything is OK
3981 10: Absolute 1:8 only
3982 20: Absolute 0:7 only
3983 30: absolute 0:15 only
3984 40: Absolute 0:31 only
3985 50: absolute 0:127 only
3986 55: absolute -64:63 only
3987 60: absolute -128:127 only
3988 70: absolute 0:4095 only
3989 80: No bignums
3990
3991 */
3992
3993static int
3994get_num (exp, ok)
3995 struct m68k_exp *exp;
3996 int ok;
3997{
3998 if (exp->exp.X_op == O_absent)
3999 {
4000 /* Do the same thing the VAX asm does */
4001 op (exp) = O_constant;
4002 adds (exp) = 0;
4003 subs (exp) = 0;
4004 offs (exp) = 0;
4005 if (ok == 10)
4006 {
4007 as_warn ("expression out of range: defaulting to 1");
4008 offs (exp) = 1;
4009 }
4010 }
4011 else if (exp->exp.X_op == O_constant)
4012 {
4013 switch (ok)
4014 {
4015 case 10:
4016 if (offs (exp) < 1 || offs (exp) > 8)
4017 {
4018 as_warn ("expression out of range: defaulting to 1");
4019 offs (exp) = 1;
4020 }
4021 break;
4022 case 20:
4023 if (offs (exp) < 0 || offs (exp) > 7)
4024 goto outrange;
4025 break;
4026 case 30:
4027 if (offs (exp) < 0 || offs (exp) > 15)
4028 goto outrange;
4029 break;
4030 case 40:
4031 if (offs (exp) < 0 || offs (exp) > 32)
4032 goto outrange;
4033 break;
4034 case 50:
4035 if (offs (exp) < 0 || offs (exp) > 127)
4036 goto outrange;
4037 break;
4038 case 55:
4039 if (offs (exp) < -64 || offs (exp) > 63)
4040 goto outrange;
4041 break;
4042 case 60:
4043 if (offs (exp) < -128 || offs (exp) > 127)
4044 goto outrange;
4045 break;
4046 case 70:
4047 if (offs (exp) < 0 || offs (exp) > 4095)
4048 {
4049 outrange:
4050 as_warn ("expression out of range: defaulting to 0");
4051 offs (exp) = 0;
4052 }
4053 break;
4054 default:
4055 break;
4056 }
4057 }
4058 else if (exp->exp.X_op == O_big)
4059 {
4060 if (offs (exp) <= 0 /* flonum */
4061 && (ok == 80 /* no bignums */
4062 || (ok > 10 /* small-int ranges including 0 ok */
4063 /* If we have a flonum zero, a zero integer should
4064 do as well (e.g., in moveq). */
4065 && generic_floating_point_number.exponent == 0
4066 && generic_floating_point_number.low[0] == 0)))
4067 {
4068 /* HACK! Turn it into a long */
4069 LITTLENUM_TYPE words[6];
4070
4071 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4072 op (exp) = O_constant;
4073 adds (exp) = 0;
4074 subs (exp) = 0;
4075 offs (exp) = words[1] | (words[0] << 16);
4076 }
4077 else if (ok != 0)
4078 {
4079 op (exp) = O_constant;
4080 adds (exp) = 0;
4081 subs (exp) = 0;
4082 offs (exp) = (ok == 10) ? 1 : 0;
4083 as_warn ("Can't deal with expression; defaulting to %ld",
4084 offs (exp));
4085 }
4086 }
4087 else
4088 {
4089 if (ok >= 10 && ok <= 70)
4090 {
4091 op (exp) = O_constant;
4092 adds (exp) = 0;
4093 subs (exp) = 0;
4094 offs (exp) = (ok == 10) ? 1 : 0;
4095 as_warn ("Can't deal with expression; defaulting to %ld",
4096 offs (exp));
4097 }
4098 }
4099
4100 if (exp->size != SIZE_UNSPEC)
4101 {
4102 switch (exp->size)
4103 {
4104 case SIZE_UNSPEC:
4105 case SIZE_LONG:
4106 break;
4107 case SIZE_BYTE:
4108 if (!isbyte (offs (exp)))
4109 as_warn ("expression doesn't fit in BYTE");
4110 break;
4111 case SIZE_WORD:
4112 if (!isword (offs (exp)))
4113 as_warn ("expression doesn't fit in WORD");
4114 break;
4115 }
4116 }
4117
4118 return offs (exp);
4119}
4120
4121/* These are the back-ends for the various machine dependent pseudo-ops. */
4122void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4123
4124static void
4125s_data1 (ignore)
4126 int ignore;
4127{
4128 subseg_set (data_section, 1);
4129 demand_empty_rest_of_line ();
4130}
4131
4132static void
4133s_data2 (ignore)
4134 int ignore;
4135{
4136 subseg_set (data_section, 2);
4137 demand_empty_rest_of_line ();
4138}
4139
4140static void
4141s_bss (ignore)
4142 int ignore;
4143{
4144 /* We don't support putting frags in the BSS segment, we fake it
4145 by marking in_bss, then looking at s_skip for clues. */
4146
4147 subseg_set (bss_section, 0);
4148 demand_empty_rest_of_line ();
4149}
4150
4151static void
4152s_even (ignore)
4153 int ignore;
4154{
4155 register int temp;
4156 register long temp_fill;
4157
4158 temp = 1; /* JF should be 2? */
4159 temp_fill = get_absolute_expression ();
4160 if (!need_pass_2) /* Never make frag if expect extra pass. */
4161 frag_align (temp, (int) temp_fill);
4162 demand_empty_rest_of_line ();
4163}
4164
4165static void
4166s_proc (ignore)
4167 int ignore;
4168{
4169 demand_empty_rest_of_line ();
4170}
4171\f
4172/* Pseudo-ops handled for MRI compatibility. */
4173
4174/* Handle an MRI style chip specification. */
4175
4176static void
4177mri_chip ()
4178{
4179 char *s;
4180 char c;
4181 int i;
4182
4183 s = input_line_pointer;
4184 c = get_symbol_end ();
4185 for (i = 0; i < n_archs; i++)
4186 if (strcasecmp (s, archs[i].name) == 0)
4187 break;
4188 if (i >= n_archs)
4189 {
4190 as_bad ("%s: unrecognized processor name", s);
4191 *input_line_pointer = c;
4192 ignore_rest_of_line ();
4193 return;
4194 }
4195 *input_line_pointer = c;
4196
4197 if (*input_line_pointer == '/')
4198 current_architecture = 0;
4199 else
4200 current_architecture &= m68881 | m68851;
4201 current_architecture |= archs[i].arch;
4202
4203 while (*input_line_pointer == '/')
4204 {
4205 ++input_line_pointer;
4206 s = input_line_pointer;
4207 c = get_symbol_end ();
4208 if (strcmp (s, "68881") == 0)
4209 current_architecture |= m68881;
4210 else if (strcmp (s, "68851") == 0)
4211 current_architecture |= m68851;
4212 *input_line_pointer = c;
4213 }
4214}
4215
4216/* The MRI CHIP pseudo-op. */
4217
4218static void
4219s_chip (ignore)
4220 int ignore;
4221{
4222 mri_chip ();
4223 demand_empty_rest_of_line ();
4224}
4225
4226/* The MRI FOPT pseudo-op. */
4227
4228static void
4229s_fopt (ignore)
4230 int ignore;
4231{
4232 SKIP_WHITESPACE ();
4233
4234 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4235 {
4236 int temp;
4237
4238 input_line_pointer += 3;
4239 temp = get_absolute_expression ();
4240 if (temp < 0 || temp > 7)
4241 as_bad ("bad coprocessor id");
4242 else
4243 m68k_float_copnum = COP0 + temp;
4244 }
4245 else
4246 {
4247 as_bad ("unrecognized fopt option");
4248 ignore_rest_of_line ();
4249 return;
4250 }
4251
4252 demand_empty_rest_of_line ();
4253}
4254
4255/* The structure used to handle the MRI OPT pseudo-op. */
4256
4257struct opt_action
4258{
4259 /* The name of the option. */
4260 const char *name;
4261
4262 /* If this is not NULL, just call this function. The first argument
4263 is the ARG field of this structure, the second argument is
4264 whether the option was negated. */
4265 void (*pfn) PARAMS ((int arg, int on));
4266
4267 /* If this is not NULL, and the PFN field is NULL, set the variable
4268 this points to. Set it to the ARG field if the option was not
4269 negated, and the NOTARG field otherwise. */
4270 int *pvar;
4271
4272 /* The value to pass to PFN or to assign to *PVAR. */
4273 int arg;
4274
4275 /* The value to assign to *PVAR if the option is negated. If PFN is
4276 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4277 the option may not be negated. */
4278 int notarg;
4279};
4280
4281/* The table used to handle the MRI OPT pseudo-op. */
4282
4283static void skip_to_comma PARAMS ((int, int));
4284static void opt_nest PARAMS ((int, int));
4285static void opt_chip PARAMS ((int, int));
4286static void opt_list PARAMS ((int, int));
4287static void opt_list_symbols PARAMS ((int, int));
4288
4289static const struct opt_action opt_table[] =
4290{
4291 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
4292
4293 /* We do relaxing, so there is little use for these options. */
4294 { "b", 0, 0, 0, 0 },
4295 { "brs", 0, 0, 0, 0 },
4296 { "brb", 0, 0, 0, 0 },
4297 { "brl", 0, 0, 0, 0 },
4298 { "brw", 0, 0, 0, 0 },
4299
4300 { "c", 0, 0, 0, 0 },
4301 { "cex", 0, 0, 0, 0 },
4302 { "case", 0, &symbols_case_sensitive, 1, 0 },
4303 { "cl", 0, 0, 0, 0 },
4304 { "cre", 0, 0, 0, 0 },
4305 { "d", 0, &flag_keep_locals, 1, 0 },
4306 { "e", 0, 0, 0, 0 },
4307 { "f", 0, &flag_short_refs, 1, 0 },
4308 { "frs", 0, &flag_short_refs, 1, 0 },
4309 { "frl", 0, &flag_short_refs, 0, 1 },
4310 { "g", 0, 0, 0, 0 },
4311 { "i", 0, 0, 0, 0 },
4312 { "m", 0, 0, 0, 0 },
4313 { "mex", 0, 0, 0, 0 },
4314 { "mc", 0, 0, 0, 0 },
4315 { "md", 0, 0, 0, 0 },
4316 { "nest", opt_nest, 0, 0, 0 },
4317 { "next", skip_to_comma, 0, 0, 0 },
4318 { "o", 0, 0, 0, 0 },
4319 { "old", 0, 0, 0, 0 },
4320 { "op", skip_to_comma, 0, 0, 0 },
4321 { "pco", 0, 0, 0, 0 },
4322 { "p", opt_chip, 0, 0, 0 },
4323 { "pcr", 0, 0, 0, 0 },
4324 { "pcs", 0, 0, 0, 0 },
4325 { "r", 0, 0, 0, 0 },
4326 { "quick", 0, &m68k_quick, 1, 0 },
4327 { "rel32", 0, &m68k_rel32, 1, 0 },
4328 { "s", opt_list, 0, 0, 0 },
4329 { "t", opt_list_symbols, 0, 0, 0 },
4330 { "w", 0, &flag_no_warnings, 0, 1 },
4331 { "x", 0, 0, 0, 0 }
4332};
4333
4334#define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
4335
4336/* The MRI OPT pseudo-op. */
4337
4338static void
4339s_opt (ignore)
4340 int ignore;
4341{
4342 do
4343 {
4344 int t;
4345 char *s;
4346 char c;
4347 int i;
4348 const struct opt_action *o;
4349
4350 SKIP_WHITESPACE ();
4351
4352 t = 1;
4353 if (*input_line_pointer == '-')
4354 {
4355 ++input_line_pointer;
4356 t = 0;
4357 }
4358 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
4359 {
4360 input_line_pointer += 2;
4361 t = 0;
4362 }
4363
4364 s = input_line_pointer;
4365 c = get_symbol_end ();
4366
4367 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
4368 {
4369 if (strcasecmp (s, o->name) == 0)
4370 {
4371 if (o->pfn)
4372 {
4373 /* Restore input_line_pointer now in case the option
4374 takes arguments. */
4375 *input_line_pointer = c;
4376 (*o->pfn) (o->arg, t);
4377 }
4378 else if (o->pvar != NULL)
4379 {
4380 if (! t && o->arg == o->notarg)
4381 as_bad ("option `%s' may not be negated", s);
4382 *input_line_pointer = c;
4383 *o->pvar = t ? o->arg : o->notarg;
4384 }
4385 else
4386 *input_line_pointer = c;
4387 break;
4388 }
4389 }
4390 if (i >= OPTCOUNT)
4391 {
4392 as_bad ("option `%s' not recognized", s);
4393 *input_line_pointer = c;
4394 }
4395 }
4396 while (*input_line_pointer++ == ',');
4397
4398 /* Move back to terminating character. */
4399 --input_line_pointer;
4400 demand_empty_rest_of_line ();
4401}
4402
4403/* Skip ahead to a comma. This is used for OPT options which we do
4404 not suppor tand which take arguments. */
4405
4406static void
4407skip_to_comma (arg, on)
4408 int arg;
4409 int on;
4410{
4411 while (*input_line_pointer != ','
4412 && ! is_end_of_line[(unsigned char) *input_line_pointer])
4413 ++input_line_pointer;
4414}
4415
4416/* Handle the OPT NEST=depth option. */
4417
4418static void
4419opt_nest (arg, on)
4420 int arg;
4421 int on;
4422{
4423 if (*input_line_pointer != '=')
4424 {
4425 as_bad ("bad format of OPT NEST=depth");
4426 return;
4427 }
4428
4429 ++input_line_pointer;
4430 max_macro_nest = get_absolute_expression ();
4431}
4432
4433/* Handle the OPT P=chip option. */
4434
4435static void
4436opt_chip (arg, on)
4437 int arg;
4438 int on;
4439{
4440 if (*input_line_pointer != '=')
4441 {
4442 /* This is just OPT P, which we do not support. */
4443 return;
4444 }
4445
4446 ++input_line_pointer;
4447 mri_chip ();
4448}
4449
4450/* Handle the OPT S option. */
4451
4452static void
4453opt_list (arg, on)
4454 int arg;
4455 int on;
4456{
4457 listing_list (on);
4458}
4459
4460/* Handle the OPT T option. */
4461
4462static void
4463opt_list_symbols (arg, on)
4464 int arg;
4465 int on;
4466{
4467 if (on)
4468 listing |= LISTING_SYMBOLS;
4469 else
4470 listing &=~ LISTING_SYMBOLS;
4471}
4472
4473/* Handle the MRI REG pseudo-op. */
4474
4475static void
4476s_reg (ignore)
4477 int ignore;
4478{
4479 char *s;
4480 int c;
4481 struct m68k_op rop;
4482 unsigned long mask;
4483
4484 if (line_label == NULL)
4485 {
4486 as_bad ("missing label");
4487 ignore_rest_of_line ();
4488 return;
4489 }
4490
4491 SKIP_WHITESPACE ();
4492
4493 s = input_line_pointer;
4494 while (isalnum ((unsigned char) *input_line_pointer)
4495#ifdef REGISTER_PREFIX
4496 || *input_line_pointer == REGISTER_PREFIX
4497#endif
4498 || *input_line_pointer == '/'
4499 || *input_line_pointer == '-')
4500 ++input_line_pointer;
4501 c = *input_line_pointer;
4502 *input_line_pointer = '\0';
4503
4504 if (m68k_ip_op (s, &rop) != 0)
4505 {
4506 if (rop.error == NULL)
4507 as_bad ("bad register list");
4508 else
4509 as_bad ("bad register list: %s", rop.error);
4510 *input_line_pointer = c;
4511 ignore_rest_of_line ();
4512 return;
4513 }
4514
4515 *input_line_pointer = c;
4516
4517 if (rop.mode == REGLST)
4518 mask = rop.mask;
4519 else if (rop.mode == DREG)
4520 mask = 1 << (rop.reg - DATA0);
4521 else if (rop.mode == AREG)
4522 mask = 1 << (rop.reg - ADDR0 + 8);
4523 else if (rop.mode == FPREG)
4524 mask = 1 << (rop.reg - FP0 + 16);
4525 else if (rop.mode == CONTROL
4526 && rop.reg == FPI)
4527 mask = 1 << 24;
4528 else if (rop.mode == CONTROL
4529 && rop.reg == FPS)
4530 mask = 1 << 25;
4531 else if (rop.mode == CONTROL
4532 && rop.reg == FPC)
4533 mask = 1 << 26;
4534 else
4535 {
4536 as_bad ("bad register list");
4537 ignore_rest_of_line ();
4538 return;
4539 }
4540
4541 S_SET_SEGMENT (line_label, absolute_section);
4542 S_SET_VALUE (line_label, mask);
4543 line_label->sy_frag = &zero_address_frag;
4544
4545 demand_empty_rest_of_line ();
4546}
4547
4548/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
4549
4550struct save_opts
4551{
4552 struct save_opts *next;
4553 int abspcadd;
4554 int symbols_case_sensitive;
4555 int keep_locals;
4556 int short_refs;
4557 int architecture;
4558 int quick;
4559 int rel32;
4560 int listing;
4561 int no_warnings;
4562 /* FIXME: We don't save OPT S. */
4563};
4564
4565/* This variable holds the stack of saved options. */
4566
4567static struct save_opts *save_stack;
4568
4569/* The MRI SAVE pseudo-op. */
4570
4571static void
4572s_save (ignore)
4573 int ignore;
4574{
4575 struct save_opts *s;
4576
4577 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
4578 s->abspcadd = m68k_abspcadd;
4579 s->symbols_case_sensitive = symbols_case_sensitive;
4580 s->keep_locals = flag_keep_locals;
4581 s->short_refs = flag_short_refs;
4582 s->architecture = current_architecture;
4583 s->quick = m68k_quick;
4584 s->rel32 = m68k_rel32;
4585 s->listing = listing;
4586 s->no_warnings = flag_no_warnings;
4587
4588 s->next = save_stack;
4589 save_stack = s;
4590
4591 demand_empty_rest_of_line ();
4592}
4593
4594/* The MRI RESTORE pseudo-op. */
4595
4596static void
4597s_restore (ignore)
4598 int ignore;
4599{
4600 struct save_opts *s;
4601
4602 if (save_stack == NULL)
4603 {
4604 as_bad ("restore without save");
4605 ignore_rest_of_line ();
4606 return;
4607 }
4608
4609 s = save_stack;
4610 save_stack = s->next;
4611
4612 m68k_abspcadd = s->abspcadd;
4613 symbols_case_sensitive = s->symbols_case_sensitive;
4614 flag_keep_locals = s->keep_locals;
4615 flag_short_refs = s->short_refs;
4616 current_architecture = s->architecture;
4617 m68k_quick = s->quick;
4618 m68k_rel32 = s->rel32;
4619 listing = s->listing;
4620 flag_no_warnings = s->no_warnings;
4621
4622 free (s);
4623
4624 demand_empty_rest_of_line ();
4625}
4626
4627/* Types of MRI structured control directives. */
4628
4629enum mri_control_type
4630{
4631 mri_for,
4632 mri_if,
4633 mri_repeat,
4634 mri_while
4635};
4636
4637/* This structure is used to stack the MRI structured control
4638 directives. */
4639
4640struct mri_control_info
4641{
4642 /* The directive within which this one is enclosed. */
4643 struct mri_control_info *outer;
4644
4645 /* The type of directive. */
4646 enum mri_control_type type;
4647
4648 /* Whether an ELSE has been in an IF. */
4649 int else_seen;
4650
4651 /* The add or sub statement at the end of a FOR. */
4652 char *incr;
4653
4654 /* The label of the top of a FOR or REPEAT loop. */
4655 char *top;
4656
4657 /* The label to jump to for the next iteration, or the else
4658 expression of a conditional. */
4659 char *next;
4660
4661 /* The label to jump to to break out of the loop, or the label past
4662 the end of a conditional. */
4663 char *bottom;
4664};
4665
4666/* The stack of MRI structured control directives. */
4667
4668static struct mri_control_info *mri_control_stack;
4669
4670/* The current MRI structured control directive index number, used to
4671 generate label names. */
4672
4673static int mri_control_index;
4674
4675/* Some function prototypes. */
4676
4677static char *mri_control_label PARAMS ((void));
4678static struct mri_control_info *push_mri_control
4679 PARAMS ((enum mri_control_type));
4680static void pop_mri_control PARAMS ((void));
4681static int parse_mri_condition PARAMS ((int *));
4682static int parse_mri_control_operand
4683 PARAMS ((int *, const char **, const char **, const char **, const char **));
4684static int swap_mri_condition PARAMS ((int));
4685static int reverse_mri_condition PARAMS ((int));
4686static void build_mri_control_operand
4687 PARAMS ((int, int, const char *, const char *, const char *, const char *,
4688 const char *, const char *, int));
4689static void parse_mri_control_expression
4690 PARAMS ((char *, int, const char *, const char *, int));
4691
4692/* Generate a new MRI label structured control directive label name. */
4693
4694static char *
4695mri_control_label ()
4696{
4697 char *n;
4698
4699 n = (char *) xmalloc (20);
4700 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
4701 ++mri_control_index;
4702 return n;
4703}
4704
4705/* Create a new MRI structured control directive. */
4706
4707static struct mri_control_info *
4708push_mri_control (type)
4709 enum mri_control_type type;
4710{
4711 struct mri_control_info *n;
4712
4713 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
4714
4715 n->type = type;
4716 n->else_seen = 0;
4717 if (type == mri_if || type == mri_while)
4718 n->top = NULL;
4719 else
4720 n->top = mri_control_label ();
4721 n->next = mri_control_label ();
4722 n->bottom = mri_control_label ();
4723
4724 n->outer = mri_control_stack;
4725 mri_control_stack = n;
4726
4727 return n;
4728}
4729
4730/* Pop off the stack of MRI structured control directives. */
4731
4732static void
4733pop_mri_control ()
4734{
4735 struct mri_control_info *n;
4736
4737 n = mri_control_stack;
4738 mri_control_stack = n->outer;
4739 if (n->top != NULL)
4740 free (n->top);
4741 free (n->next);
4742 free (n->bottom);
4743 free (n);
4744}
4745
4746/* Recognize a condition code in an MRI structured control expression. */
4747
4748static int
4749parse_mri_condition (pcc)
4750 int *pcc;
4751{
4752 char c1, c2;
4753
4754 know (*input_line_pointer == '<');
4755
4756 ++input_line_pointer;
4757 c1 = *input_line_pointer++;
4758 c2 = *input_line_pointer++;
4759
4760 if (*input_line_pointer != '>')
4761 {
4762 as_bad ("syntax error in structured control directive");
4763 return 0;
4764 }
4765
4766 ++input_line_pointer;
4767 SKIP_WHITESPACE ();
4768
4769 if (isupper (c1))
4770 c1 = tolower (c1);
4771 if (isupper (c2))
4772 c2 = tolower (c2);
4773
4774 *pcc = (c1 << 8) | c2;
4775
4776 return 1;
4777}
4778
4779/* Parse a single operand in an MRI structured control expression. */
4780
4781static int
4782parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
4783 int *pcc;
4784 const char **leftstart;
4785 const char **leftstop;
4786 const char **rightstart;
4787 const char **rightstop;
4788{
4789 char *s;
4790
4791 SKIP_WHITESPACE ();
4792
4793 *pcc = -1;
4794 *leftstart = NULL;
4795 *leftstop = NULL;
4796 *rightstart = NULL;
4797 *rightstop = NULL;
4798
4799 if (*input_line_pointer == '<')
4800 {
4801 /* It's just a condition code. */
4802 return parse_mri_condition (pcc);
4803 }
4804
4805 /* Look ahead for the condition code. */
4806 for (s = input_line_pointer; *s != '\0'; ++s)
4807 {
4808 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
4809 break;
4810 }
4811 if (*s == '\0')
4812 {
4813 as_bad ("missing condition code in structured control directive");
4814 return 0;
4815 }
4816
4817 *leftstart = input_line_pointer;
4818 *leftstop = s;
4819 if (*leftstop > *leftstart
4820 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
4821 --*leftstop;
4822
4823 input_line_pointer = s;
4824 if (! parse_mri_condition (pcc))
4825 return 0;
4826
4827 /* Look ahead for AND or OR or end of line. */
4828 for (s = input_line_pointer; *s != '\0'; ++s)
4829 {
4830 if ((strncasecmp (s, "AND", 3) == 0
4831 && (s[3] == '.' || ! is_part_of_name (s[3])))
4832 || (strncasecmp (s, "OR", 2) == 0
4833 && (s[2] == '.' || ! is_part_of_name (s[2]))))
4834 break;
4835 }
4836
4837 *rightstart = input_line_pointer;
4838 *rightstop = s;
4839 if (*rightstop > *rightstart
4840 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
4841 --*rightstop;
4842
4843 input_line_pointer = s;
4844
4845 return 1;
4846}
4847
4848#define MCC(b1, b2) (((b1) << 8) | (b2))
4849
4850/* Swap the sense of a condition. This changes the condition so that
4851 it generates the same result when the operands are swapped. */
4852
4853static int
4854swap_mri_condition (cc)
4855 int cc;
4856{
4857 switch (cc)
4858 {
4859 case MCC ('h', 'i'): return MCC ('c', 's');
4860 case MCC ('l', 's'): return MCC ('c', 'c');
4861 case MCC ('c', 'c'): return MCC ('l', 's');
4862 case MCC ('c', 's'): return MCC ('h', 'i');
4863 case MCC ('p', 'l'): return MCC ('m', 'i');
4864 case MCC ('m', 'i'): return MCC ('p', 'l');
4865 case MCC ('g', 'e'): return MCC ('l', 'e');
4866 case MCC ('l', 't'): return MCC ('g', 't');
4867 case MCC ('g', 't'): return MCC ('l', 't');
4868 case MCC ('l', 'e'): return MCC ('g', 'e');
4869 }
4870 return cc;
4871}
4872
4873/* Reverse the sense of a condition. */
4874
4875static int
4876reverse_mri_condition (cc)
4877 int cc;
4878{
4879 switch (cc)
4880 {
4881 case MCC ('h', 'i'): return MCC ('l', 's');
4882 case MCC ('l', 's'): return MCC ('h', 'i');
4883 case MCC ('c', 'c'): return MCC ('c', 's');
4884 case MCC ('c', 's'): return MCC ('c', 'c');
4885 case MCC ('n', 'e'): return MCC ('e', 'q');
4886 case MCC ('e', 'q'): return MCC ('n', 'e');
4887 case MCC ('v', 'c'): return MCC ('v', 's');
4888 case MCC ('v', 's'): return MCC ('v', 'c');
4889 case MCC ('p', 'l'): return MCC ('m', 'i');
4890 case MCC ('m', 'i'): return MCC ('p', 'l');
4891 case MCC ('g', 'e'): return MCC ('l', 't');
4892 case MCC ('l', 't'): return MCC ('g', 'e');
4893 case MCC ('g', 't'): return MCC ('l', 'e');
4894 case MCC ('l', 'e'): return MCC ('g', 't');
4895 }
4896 return cc;
4897}
4898
4899/* Build an MRI structured control expression. This generates test
4900 and branch instructions. It goes to TRUELAB if the condition is
4901 true, and to FALSELAB if the condition is false. Exactly one of
4902 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
4903 is the size qualifier for the expression. EXTENT is the size to
4904 use for the branch. */
4905
4906static void
4907build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
4908 rightstop, truelab, falselab, extent)
4909 int qual;
4910 int cc;
4911 const char *leftstart;
4912 const char *leftstop;
4913 const char *rightstart;
4914 const char *rightstop;
4915 const char *truelab;
4916 const char *falselab;
4917 int extent;
4918{
4919 char *buf;
4920 char *s;
4921
4922 /* The 68k can't do a general comparision with an immediate operand
4923 on the right hand side. */
4924 if (rightstart != NULL && *rightstart == '#')
4925 {
4926 const char *temp;
4927
4928 cc = swap_mri_condition (cc);
4929 temp = leftstart;
4930 leftstart = rightstart;
4931 rightstart = temp;
4932 temp = leftstop;
4933 leftstop = rightstop;
4934 rightstop = temp;
4935 }
4936
4937 if (truelab == NULL)
4938 {
4939 cc = reverse_mri_condition (cc);
4940 truelab = falselab;
4941 }
4942
4943 if (leftstart != NULL)
4944 {
4945 buf = (char *) xmalloc (20
4946 + (leftstop - leftstart)
4947 + (rightstop - rightstart));
4948 s = buf;
4949 *s++ = 'c';
4950 *s++ = 'm';
4951 *s++ = 'p';
4952 if (qual != '\0')
4953 *s++ = qual;
4954 *s++ = ' ';
4955 memcpy (s, leftstart, leftstop - leftstart);
4956 s += leftstop - leftstart;
4957 *s++ = ',';
4958 memcpy (s, rightstart, rightstop - rightstart);
4959 s += rightstop - rightstart;
4960 *s = '\0';
4961 md_assemble (buf);
4962 free (buf);
4963 }
4964
4965 buf = (char *) xmalloc (20 + strlen (truelab));
4966 s = buf;
4967 *s++ = 'b';
4968 *s++ = cc >> 8;
4969 *s++ = cc & 0xff;
4970 if (extent != '\0')
4971 *s++ = extent;
4972 *s++ = ' ';
4973 strcpy (s, truelab);
4974 md_assemble (buf);
4975 free (buf);
4976}
4977
4978/* Parse an MRI structured control expression. This generates test
4979 and branch instructions. STOP is where the expression ends. It
4980 goes to TRUELAB if the condition is true, and to FALSELAB if the
4981 condition is false. Exactly one of TRUELAB and FALSELAB will be
4982 NULL, meaning to fall through. QUAL is the size qualifier for the
4983 expression. EXTENT is the size to use for the branch. */
4984
4985static void
4986parse_mri_control_expression (stop, qual, truelab, falselab, extent)
4987 char *stop;
4988 int qual;
4989 const char *truelab;
4990 const char *falselab;
4991 int extent;
4992{
4993 int c;
4994 int cc;
4995 const char *leftstart;
4996 const char *leftstop;
4997 const char *rightstart;
4998 const char *rightstop;
4999
5000 c = *stop;
5001 *stop = '\0';
5002
5003 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5004 &rightstart, &rightstop))
5005 {
5006 *stop = c;
5007 return;
5008 }
5009
5010 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5011 {
5012 const char *flab;
5013
5014 if (falselab != NULL)
5015 flab = falselab;
5016 else
5017 flab = mri_control_label ();
5018
5019 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5020 rightstop, (const char *) NULL, flab, extent);
5021
5022 input_line_pointer += 3;
5023 if (*input_line_pointer != '.'
5024 || input_line_pointer[1] == '\0')
5025 qual = '\0';
5026 else
5027 {
5028 qual = input_line_pointer[1];
5029 input_line_pointer += 2;
5030 }
5031
5032 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5033 &rightstart, &rightstop))
5034 {
5035 *stop = c;
5036 return;
5037 }
5038
5039 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5040 rightstop, truelab, falselab, extent);
5041
5042 if (falselab == NULL)
5043 colon (flab);
5044 }
5045 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5046 {
5047 const char *tlab;
5048
5049 if (truelab != NULL)
5050 tlab = truelab;
5051 else
5052 tlab = mri_control_label ();
5053
5054 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5055 rightstop, tlab, (const char *) NULL, extent);
5056
5057 input_line_pointer += 2;
5058 if (*input_line_pointer != '.'
5059 || input_line_pointer[1] == '\0')
5060 qual = '\0';
5061 else
5062 {
5063 qual = input_line_pointer[1];
5064 input_line_pointer += 2;
5065 }
5066
5067 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5068 &rightstart, &rightstop))
5069 {
5070 *stop = c;
5071 return;
5072 }
5073
5074 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5075 rightstop, truelab, falselab, extent);
5076
5077 if (truelab == NULL)
5078 colon (tlab);
5079 }
5080 else
5081 {
5082 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5083 rightstop, truelab, falselab, extent);
5084 }
5085
5086 *stop = c;
5087 if (input_line_pointer != stop)
5088 as_bad ("syntax error in structured control directive");
5089}
5090
5091/* Handle the MRI IF pseudo-op. This may be a structured control
5092 directive, or it may be a regular assembler conditional, depending
5093 on its operands. */
5094
5095static void
5096s_mri_if (qual)
5097 int qual;
5098{
5099 char *s;
5100 int c;
5101 struct mri_control_info *n;
5102
5103 /* A structured control directive must end with THEN with an
5104 optional qualifier. */
5105 s = input_line_pointer;
5106 while (! is_end_of_line[(unsigned char) *s])
5107 ++s;
5108 --s;
5109 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5110 --s;
5111
5112 if (s - input_line_pointer > 1
5113 && s[-1] == '.')
5114 s -= 2;
5115
5116 if (s - input_line_pointer < 3
5117 || strncasecmp (s - 3, "THEN", 4) != 0)
5118 {
5119 if (qual != '\0')
5120 {
5121 as_bad ("missing then");
5122 ignore_rest_of_line ();
5123 return;
5124 }
5125
5126 /* It's a conditional. */
5127 s_if (O_ne);
5128 return;
5129 }
5130
5131 /* Since this might be a conditional if, this pseudo-op will be
5132 called even if we are supported to be ignoring input. Double
5133 check now. Clobber *input_line_pointer so that ignore_input
5134 thinks that this is not a special pseudo-op. */
5135 c = *input_line_pointer;
5136 *input_line_pointer = 0;
5137 if (ignore_input ())
5138 {
5139 *input_line_pointer = c;
5140 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5141 ++input_line_pointer;
5142 demand_empty_rest_of_line ();
5143 return;
5144 }
5145 *input_line_pointer = c;
5146
5147 n = push_mri_control (mri_if);
5148
5149 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5150 n->next, s[1] == '.' ? s[2] : '\0');
5151
5152 if (s[1] == '.')
5153 input_line_pointer = s + 3;
5154 else
5155 input_line_pointer = s + 1;
5156
5157 demand_empty_rest_of_line ();
5158}
5159
5160/* Handle the MRI else pseudo-op. If we are currently doing an MRI
5161 structured IF, associate the ELSE with the IF. Otherwise, assume
5162 it is a conditional else. */
5163
5164static void
5165s_mri_else (qual)
5166 int qual;
5167{
5168 int c;
5169 char *buf;
5170 char q[2];
5171
5172 if (qual == '\0'
5173 && (mri_control_stack == NULL
5174 || mri_control_stack->type != mri_if
5175 || mri_control_stack->else_seen))
5176 {
5177 s_else (0);
5178 return;
5179 }
5180
5181 c = *input_line_pointer;
5182 *input_line_pointer = 0;
5183 if (ignore_input ())
5184 {
5185 *input_line_pointer = c;
5186 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5187 ++input_line_pointer;
5188 demand_empty_rest_of_line ();
5189 return;
5190 }
5191 *input_line_pointer = c;
5192
5193 if (mri_control_stack == NULL
5194 || mri_control_stack->type != mri_if
5195 || mri_control_stack->else_seen)
5196 {
5197 as_bad ("else without matching if");
5198 ignore_rest_of_line ();
5199 return;
5200 }
5201
5202 mri_control_stack->else_seen = 1;
5203
5204 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5205 q[0] = qual;
5206 q[1] = '\0';
5207 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5208 md_assemble (buf);
5209 free (buf);
5210
5211 colon (mri_control_stack->next);
5212
5213 demand_empty_rest_of_line ();
5214}
5215
5216/* Handle the MRI ENDI pseudo-op. */
5217
5218static void
5219s_mri_endi (ignore)
5220 int ignore;
5221{
5222 if (mri_control_stack == NULL
5223 || mri_control_stack->type != mri_if)
5224 {
5225 as_bad ("endi without matching if");
5226 ignore_rest_of_line ();
5227 return;
5228 }
5229
5230 /* ignore_input will not return true for ENDI, so we don't need to
5231 worry about checking it again here. */
5232
5233 if (! mri_control_stack->else_seen)
5234 colon (mri_control_stack->next);
5235 colon (mri_control_stack->bottom);
5236
5237 pop_mri_control ();
5238
5239 demand_empty_rest_of_line ();
5240}
5241
5242/* Handle the MRI BREAK pseudo-op. */
5243
5244static void
5245s_mri_break (extent)
5246 int extent;
5247{
5248 struct mri_control_info *n;
5249 char *buf;
5250 char ex[2];
5251
5252 n = mri_control_stack;
5253 while (n != NULL
5254 && n->type != mri_for
5255 && n->type != mri_repeat
5256 && n->type != mri_while)
5257 n = n->outer;
5258 if (n == NULL)
5259 {
5260 as_bad ("break outside of structured loop");
5261 ignore_rest_of_line ();
5262 return;
5263 }
5264
5265 buf = (char *) xmalloc (20 + strlen (n->bottom));
5266 ex[0] = extent;
5267 ex[1] = '\0';
5268 sprintf (buf, "bra%s %s", ex, n->bottom);
5269 md_assemble (buf);
5270 free (buf);
5271
5272 demand_empty_rest_of_line ();
5273}
5274
5275/* Handle the MRI NEXT pseudo-op. */
5276
5277static void
5278s_mri_next (extent)
5279 int extent;
5280{
5281 struct mri_control_info *n;
5282 char *buf;
5283 char ex[2];
5284
5285 n = mri_control_stack;
5286 while (n != NULL
5287 && n->type != mri_for
5288 && n->type != mri_repeat
5289 && n->type != mri_while)
5290 n = n->outer;
5291 if (n == NULL)
5292 {
5293 as_bad ("next outside of structured loop");
5294 ignore_rest_of_line ();
5295 return;
5296 }
5297
5298 buf = (char *) xmalloc (20 + strlen (n->next));
5299 ex[0] = extent;
5300 ex[1] = '\0';
5301 sprintf (buf, "bra%s %s", ex, n->next);
5302 md_assemble (buf);
5303 free (buf);
5304
5305 demand_empty_rest_of_line ();
5306}
5307
5308/* Handle the MRI FOR pseudo-op. */
5309
5310static void
5311s_mri_for (qual)
5312 int qual;
5313{
5314 const char *varstart, *varstop;
5315 const char *initstart, *initstop;
5316 const char *endstart, *endstop;
5317 const char *bystart, *bystop;
5318 int up;
5319 int by;
5320 int extent;
5321 struct mri_control_info *n;
5322 char *buf;
5323 char *s;
5324 char ex[2];
5325
5326 /* The syntax is
5327 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
5328 */
5329
5330 SKIP_WHITESPACE ();
5331 varstart = input_line_pointer;
5332
5333 /* Look for the '='. */
5334 while (! is_end_of_line[(unsigned char) *input_line_pointer]
5335 && *input_line_pointer != '=')
5336 ++input_line_pointer;
5337 if (*input_line_pointer != '=')
5338 {
5339 as_bad ("missing =");
5340 ignore_rest_of_line ();
5341 return;
5342 }
5343
5344 varstop = input_line_pointer;
5345 if (varstop > varstart
5346 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
5347 --varstop;
5348
5349 ++input_line_pointer;
5350
5351 initstart = input_line_pointer;
5352
5353 /* Look for TO or DOWNTO. */
5354 up = 1;
5355 initstop = NULL;
5356 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5357 {
5358 if (strncasecmp (input_line_pointer, "TO", 2) == 0
5359 && ! is_part_of_name (input_line_pointer[2]))
5360 {
5361 initstop = input_line_pointer;
5362 input_line_pointer += 2;
5363 break;
5364 }
5365 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
5366 && ! is_part_of_name (input_line_pointer[6]))
5367 {
5368 initstop = input_line_pointer;
5369 up = 0;
5370 input_line_pointer += 6;
5371 break;
5372 }
5373 ++input_line_pointer;
5374 }
5375 if (initstop == NULL)
5376 {
5377 as_bad ("missing to or downto");
5378 ignore_rest_of_line ();
5379 return;
5380 }
5381 if (initstop > initstart
5382 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
5383 --initstop;
5384
5385 SKIP_WHITESPACE ();
5386 endstart = input_line_pointer;
5387
5388 /* Look for BY or DO. */
5389 by = 0;
5390 endstop = NULL;
5391 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5392 {
5393 if (strncasecmp (input_line_pointer, "BY", 2) == 0
5394 && ! is_part_of_name (input_line_pointer[2]))
5395 {
5396 endstop = input_line_pointer;
5397 by = 1;
5398 input_line_pointer += 2;
5399 break;
5400 }
5401 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5402 && (input_line_pointer[2] == '.'
5403 || ! is_part_of_name (input_line_pointer[2])))
5404 {
5405 endstop = input_line_pointer;
5406 input_line_pointer += 2;
5407 break;
5408 }
5409 ++input_line_pointer;
5410 }
5411 if (endstop == NULL)
5412 {
5413 as_bad ("missing do");
5414 ignore_rest_of_line ();
5415 return;
5416 }
5417 if (endstop > endstart
5418 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
5419 --endstop;
5420
5421 if (! by)
5422 {
5423 bystart = "#1";
5424 bystop = bystart + 2;
5425 }
5426 else
5427 {
5428 SKIP_WHITESPACE ();
5429 bystart = input_line_pointer;
5430
5431 /* Look for DO. */
5432 bystop = NULL;
5433 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5434 {
5435 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5436 && (input_line_pointer[2] == '.'
5437 || ! is_part_of_name (input_line_pointer[2])))
5438 {
5439 bystop = input_line_pointer;
5440 input_line_pointer += 2;
5441 break;
5442 }
5443 ++input_line_pointer;
5444 }
5445 if (bystop == NULL)
5446 {
5447 as_bad ("missing do");
5448 ignore_rest_of_line ();
5449 return;
5450 }
5451 if (bystop > bystart
5452 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
5453 --bystop;
5454 }
5455
5456 if (*input_line_pointer != '.')
5457 extent = '\0';
5458 else
5459 {
5460 extent = input_line_pointer[1];
5461 input_line_pointer += 2;
5462 }
5463
5464 /* We have fully parsed the FOR operands. Now build the loop. */
5465
5466 n = push_mri_control (mri_for);
5467
5468 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
5469
5470 /* move init,var */
5471 s = buf;
5472 *s++ = 'm';
5473 *s++ = 'o';
5474 *s++ = 'v';
5475 *s++ = 'e';
5476 if (qual != '\0')
5477 *s++ = qual;
5478 *s++ = ' ';
5479 memcpy (s, initstart, initstop - initstart);
5480 s += initstop - initstart;
5481 *s++ = ',';
5482 memcpy (s, varstart, varstop - varstart);
5483 s += varstop - varstart;
5484 *s = '\0';
5485 md_assemble (buf);
5486
5487 colon (n->top);
5488
5489 /* cmp end,var */
5490 s = buf;
5491 *s++ = 'c';
5492 *s++ = 'm';
5493 *s++ = 'p';
5494 if (qual != '\0')
5495 *s++ = qual;
5496 *s++ = ' ';
5497 memcpy (s, endstart, endstop - endstart);
5498 s += endstop - endstart;
5499 *s++ = ',';
5500 memcpy (s, varstart, varstop - varstart);
5501 s += varstop - varstart;
5502 *s = '\0';
5503 md_assemble (buf);
5504
5505 /* bcc bottom */
5506 ex[0] = extent;
5507 ex[1] = '\0';
5508 if (up)
5509 sprintf (buf, "blt%s %s", ex, n->bottom);
5510 else
5511 sprintf (buf, "bgt%s %s", ex, n->bottom);
5512 md_assemble (buf);
5513
5514 /* Put together the add or sub instruction used by ENDF. */
5515 s = buf;
5516 if (up)
5517 strcpy (s, "add");
5518 else
5519 strcpy (s, "sub");
5520 s += 3;
5521 if (qual != '\0')
5522 *s++ = qual;
5523 *s++ = ' ';
5524 memcpy (s, bystart, bystop - bystart);
5525 s += bystop - bystart;
5526 *s++ = ',';
5527 memcpy (s, varstart, varstop - varstart);
5528 s += varstop - varstart;
5529 *s = '\0';
5530 n->incr = buf;
5531
5532 demand_empty_rest_of_line ();
5533}
5534
5535/* Handle the MRI ENDF pseudo-op. */
5536
5537static void
5538s_mri_endf (ignore)
5539 int ignore;
5540{
5541 if (mri_control_stack == NULL
5542 || mri_control_stack->type != mri_for)
5543 {
5544 as_bad ("endf without for");
5545 ignore_rest_of_line ();
5546 return;
5547 }
5548
5549 colon (mri_control_stack->next);
5550
5551 md_assemble (mri_control_stack->incr);
5552
5553 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
5554 md_assemble (mri_control_stack->incr);
5555
5556 free (mri_control_stack->incr);
5557
5558 colon (mri_control_stack->bottom);
5559
5560 pop_mri_control ();
5561
5562 demand_empty_rest_of_line ();
5563}
5564
5565/* Handle the MRI REPEAT pseudo-op. */
5566
5567static void
5568s_mri_repeat (ignore)
5569 int ignore;
5570{
5571 struct mri_control_info *n;
5572
5573 n = push_mri_control (mri_repeat);
5574 colon (n->top);
5575 demand_empty_rest_of_line ();
5576}
5577
5578/* Handle the MRI UNTIL pseudo-op. */
5579
5580static void
5581s_mri_until (qual)
5582 int qual;
5583{
5584 char *s;
5585
5586 if (mri_control_stack == NULL
5587 || mri_control_stack->type != mri_repeat)
5588 {
5589 as_bad ("until without repeat");
5590 ignore_rest_of_line ();
5591 return;
5592 }
5593
5594 colon (mri_control_stack->next);
5595
5596 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
5597 ;
5598
5599 parse_mri_control_expression (s, qual, (const char *) NULL,
5600 mri_control_stack->top, '\0');
5601
5602 colon (mri_control_stack->bottom);
5603
5604 input_line_pointer = s;
5605
5606 demand_empty_rest_of_line ();
5607}
5608
5609/* Handle the MRI WHILE pseudo-op. */
5610
5611static void
5612s_mri_while (qual)
5613 int qual;
5614{
5615 char *s;
5616
5617 struct mri_control_info *n;
5618
5619 s = input_line_pointer;
5620 while (! is_end_of_line[(unsigned char) *s])
5621 s++;
5622 --s;
5623 while (*s == ' ' || *s == '\t')
5624 --s;
5625 if (s - input_line_pointer > 1
5626 && s[-1] == '.')
5627 s -= 2;
5628 if (s - input_line_pointer < 2
5629 || strncasecmp (s - 1, "DO", 2) != 0)
5630 {
5631 as_bad ("missing do");
5632 ignore_rest_of_line ();
5633 return;
5634 }
5635
5636 n = push_mri_control (mri_while);
5637
5638 colon (n->next);
5639
5640 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
5641 s[1] == '.' ? s[2] : '\0');
5642
5643 input_line_pointer = s + 1;
5644 if (*input_line_pointer == '.')
5645 input_line_pointer += 2;
5646
5647 demand_empty_rest_of_line ();
5648}
5649
5650/* Handle the MRI ENDW pseudo-op. */
5651
5652static void
5653s_mri_endw (ignore)
5654 int ignore;
5655{
5656 char *buf;
5657
5658 if (mri_control_stack == NULL
5659 || mri_control_stack->type != mri_while)
5660 {
5661 as_bad ("endw without while");
5662 ignore_rest_of_line ();
5663 return;
5664 }
5665
5666 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
5667 sprintf (buf, "bra %s", mri_control_stack->next);
5668 md_assemble (buf);
5669 free (buf);
5670
5671 colon (mri_control_stack->bottom);
5672
5673 pop_mri_control ();
5674
5675 demand_empty_rest_of_line ();
5676}
5677\f
5678/*
5679 * md_parse_option
5680 * Invocation line includes a switch not recognized by the base assembler.
5681 * See if it's a processor-specific option. These are:
5682 *
5683 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
5684 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
5685 * Select the architecture. Instructions or features not
5686 * supported by the selected architecture cause fatal
5687 * errors. More than one may be specified. The default is
5688 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
5689 * for -m68000, and -m68882 is a synonym for -m68881.
5690 * -[A]m[c]no-68851, -[A]m[c]no-68881
5691 * Don't accept 688?1 instructions. (The "c" is kind of silly,
5692 * so don't use or document it, but that's the way the parsing
5693 * works).
5694 *
5695 * -pic Indicates PIC.
5696 * -k Indicates PIC. (Sun 3 only.)
5697 *
5698 */
5699
5700#ifdef OBJ_ELF
5701CONST char *md_shortopts = "lSA:m:kQ:V";
5702#else
5703CONST char *md_shortopts = "lSA:m:k";
5704#endif
5705
5706struct option md_longopts[] = {
5707#define OPTION_PIC (OPTION_MD_BASE)
5708 {"pic", no_argument, NULL, OPTION_PIC},
5709#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
5710 {"register-prefix-optional", no_argument, NULL,
5711 OPTION_REGISTER_PREFIX_OPTIONAL},
5712 {NULL, no_argument, NULL, 0}
5713};
5714size_t md_longopts_size = sizeof(md_longopts);
5715
5716int
5717md_parse_option (c, arg)
5718 int c;
5719 char *arg;
5720{
5721 switch (c)
5722 {
5723 case 'l': /* -l means keep external to 2 bit offset
5724 rather than 16 bit one */
5725 flag_short_refs = 1;
5726 break;
5727
5728 case 'S': /* -S means that jbsr's always turn into
5729 jsr's. */
5730 flag_long_jumps = 1;
5731 break;
5732
5733 case 'A':
5734 if (*arg == 'm')
5735 arg++;
5736 /* intentional fall-through */
5737 case 'm':
5738
5739 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
5740 {
5741 int i;
5742 unsigned long arch;
5743 const char *oarg = arg;
5744
5745 arg += 3;
5746 if (*arg == 'm')
5747 {
5748 arg++;
5749 if (arg[0] == 'c' && arg[1] == '6')
5750 arg++;
5751 }
5752 for (i = 0; i < n_archs; i++)
5753 if (!strcmp (arg, archs[i].name))
5754 break;
5755 if (i == n_archs)
5756 {
5757 unknown:
5758 as_bad ("unrecognized option `%s'", oarg);
5759 return 0;
5760 }
5761 arch = archs[i].arch;
5762 if (arch == m68881)
5763 no_68881 = 1;
5764 else if (arch == m68851)
5765 no_68851 = 1;
5766 else
5767 goto unknown;
5768 }
5769 else
5770 {
5771 int i;
5772
5773 if (arg[0] == 'c' && arg[1] == '6')
5774 arg++;
5775
5776 for (i = 0; i < n_archs; i++)
5777 if (!strcmp (arg, archs[i].name))
5778 {
5779 unsigned long arch = archs[i].arch;
5780 if (cpu_of_arch (arch))
5781 /* It's a cpu spec. */
5782 {
5783 current_architecture &= ~m68000up;
5784 current_architecture |= arch;
5785 }
5786 else if (arch == m68881)
5787 {
5788 current_architecture |= m68881;
5789 no_68881 = 0;
5790 }
5791 else if (arch == m68851)
5792 {
5793 current_architecture |= m68851;
5794 no_68851 = 0;
5795 }
5796 else
5797 /* ??? */
5798 abort ();
5799 break;
5800 }
5801 if (i == n_archs)
5802 {
5803 as_bad ("unrecognized architecture specification `%s'", arg);
5804 return 0;
5805 }
5806 }
5807 break;
5808
5809 case OPTION_PIC:
5810 case 'k':
5811 flag_want_pic = 1;
5812 break; /* -pic, Position Independent Code */
5813
5814 case OPTION_REGISTER_PREFIX_OPTIONAL:
5815 flag_reg_prefix_optional = 1;
5816 break;
5817
5818 case 'Q':
5819 case 'V':
5820 break;
5821
5822 default:
5823 return 0;
5824 }
5825
5826 return 1;
5827}
5828
5829void
5830md_show_usage (stream)
5831 FILE *stream;
5832{
5833 fprintf(stream, "\
5834680X0 options:\n\
5835-l use 1 word for refs to undefined symbols [default 2]\n\
5836-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
5837 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
5838 | -mcpu32\n\
5839 specify variant of 680X0 architecture [default 68020]\n\
5840-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
5841 target has/lacks floating-point coprocessor\n\
5842 [default yes for 68020, 68030, and cpu32]\n");
5843 fprintf(stream, "\
5844-m68851 | -mno-68851\n\
5845 target has/lacks memory-management unit coprocessor\n\
5846 [default yes for 68020 and up]\n\
5847-pic, -k generate position independent code\n\
5848-S turn jbsr into jsr\n\
5849--register-prefix-optional\n\
5850 recognize register names without prefix character\n");
5851}
5852\f
5853#ifdef TEST2
5854
5855/* TEST2: Test md_assemble() */
5856/* Warning, this routine probably doesn't work anymore */
5857
5858main ()
5859{
5860 struct m68k_it the_ins;
5861 char buf[120];
5862 char *cp;
5863 int n;
5864
5865 m68k_ip_begin ();
5866 for (;;)
5867 {
5868 if (!gets (buf) || !*buf)
5869 break;
5870 if (buf[0] == '|' || buf[1] == '.')
5871 continue;
5872 for (cp = buf; *cp; cp++)
5873 if (*cp == '\t')
5874 *cp = ' ';
5875 if (is_label (buf))
5876 continue;
5877 memset (&the_ins, '\0', sizeof (the_ins));
5878 m68k_ip (&the_ins, buf);
5879 if (the_ins.error)
5880 {
5881 printf ("Error %s in %s\n", the_ins.error, buf);
5882 }
5883 else
5884 {
5885 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
5886 for (n = 0; n < the_ins.numo; n++)
5887 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
5888 printf (" ");
5889 print_the_insn (&the_ins.opcode[0], stdout);
5890 (void) putchar ('\n');
5891 }
5892 for (n = 0; n < strlen (the_ins.args) / 2; n++)
5893 {
5894 if (the_ins.operands[n].error)
5895 {
5896 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
5897 continue;
5898 }
5899 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
5900 if (the_ins.operands[n].b_const)
5901 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
5902 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
5903 if (the_ins.operands[n].b_iadd)
5904 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
5905 (void) putchar ('\n');
5906 }
5907 }
5908 m68k_ip_end ();
5909 return 0;
5910}
5911
5912is_label (str)
5913 char *str;
5914{
5915 while (*str == ' ')
5916 str++;
5917 while (*str && *str != ' ')
5918 str++;
5919 if (str[-1] == ':' || str[1] == '=')
5920 return 1;
5921 return 0;
5922}
5923
5924#endif
5925
5926/* Possible states for relaxation:
5927
5928 0 0 branch offset byte (bra, etc)
5929 0 1 word
5930 0 2 long
5931
5932 1 0 indexed offsets byte a0@(32,d4:w:1) etc
5933 1 1 word
5934 1 2 long
5935
5936 2 0 two-offset index word-word a0@(32,d4)@(45) etc
5937 2 1 word-long
5938 2 2 long-word
5939 2 3 long-long
5940
5941 */
5942
5943/* We have no need to default values of symbols. */
5944
5945/* ARGSUSED */
5946symbolS *
5947md_undefined_symbol (name)
5948 char *name;
5949{
5950 return 0;
5951}
5952
5953/* Round up a section size to the appropriate boundary. */
5954valueT
5955md_section_align (segment, size)
5956 segT segment;
5957 valueT size;
5958{
5959 return size; /* Byte alignment is fine */
5960}
5961
5962/* Exactly what point is a PC-relative offset relative TO?
5963 On the 68k, it is relative to the address of the first extension
5964 word. The difference between the addresses of the offset and the
5965 first extension word is stored in fx_pcrel_adjust. */
5966long
5967md_pcrel_from (fixP)
5968 fixS *fixP;
5969{
5970 int adjust;
5971
5972 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
5973 -1 as 64. */
5974 adjust = fixP->fx_pcrel_adjust;
5975 if (adjust == 64)
5976 adjust = -1;
5977 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
5978}
5979
5980#ifndef BFD_ASSEMBLER
5981/*ARGSUSED*/
5982void
5983tc_coff_symbol_emit_hook (ignore)
5984 symbolS *ignore;
5985{
5986}
5987
5988int
5989tc_coff_sizemachdep (frag)
5990 fragS *frag;
5991{
5992 switch (frag->fr_subtype & 0x3)
5993 {
5994 case BYTE:
5995 return 1;
5996 case SHORT:
5997 return 2;
5998 case LONG:
5999 return 4;
6000 default:
6001 abort ();
6002 return 0;
6003 }
6004}
6005#endif
6006
6007/* end of tc-m68k.c */
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