| 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
| 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 |
| 3 | Free Software Foundation, Inc. |
| 4 | Contributed by the OSF and Ralph Campbell. |
| 5 | Written by Keith Knowles and Ralph Campbell, working independently. |
| 6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
| 7 | Support. |
| 8 | |
| 9 | This file is part of GAS. |
| 10 | |
| 11 | GAS is free software; you can redistribute it and/or modify |
| 12 | it under the terms of the GNU General Public License as published by |
| 13 | the Free Software Foundation; either version 2, or (at your option) |
| 14 | any later version. |
| 15 | |
| 16 | GAS is distributed in the hope that it will be useful, |
| 17 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | GNU General Public License for more details. |
| 20 | |
| 21 | You should have received a copy of the GNU General Public License |
| 22 | along with GAS; see the file COPYING. If not, write to the Free |
| 23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA |
| 24 | 02111-1307, USA. */ |
| 25 | |
| 26 | #include "as.h" |
| 27 | #include "config.h" |
| 28 | #include "subsegs.h" |
| 29 | #include "safe-ctype.h" |
| 30 | |
| 31 | #ifdef USE_STDARG |
| 32 | #include <stdarg.h> |
| 33 | #endif |
| 34 | #ifdef USE_VARARGS |
| 35 | #include <varargs.h> |
| 36 | #endif |
| 37 | |
| 38 | #include "opcode/mips.h" |
| 39 | #include "itbl-ops.h" |
| 40 | #include "dwarf2dbg.h" |
| 41 | |
| 42 | #ifdef DEBUG |
| 43 | #define DBG(x) printf x |
| 44 | #else |
| 45 | #define DBG(x) |
| 46 | #endif |
| 47 | |
| 48 | #ifdef OBJ_MAYBE_ELF |
| 49 | /* Clean up namespace so we can include obj-elf.h too. */ |
| 50 | static int mips_output_flavor PARAMS ((void)); |
| 51 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } |
| 52 | #undef OBJ_PROCESS_STAB |
| 53 | #undef OUTPUT_FLAVOR |
| 54 | #undef S_GET_ALIGN |
| 55 | #undef S_GET_SIZE |
| 56 | #undef S_SET_ALIGN |
| 57 | #undef S_SET_SIZE |
| 58 | #undef obj_frob_file |
| 59 | #undef obj_frob_file_after_relocs |
| 60 | #undef obj_frob_symbol |
| 61 | #undef obj_pop_insert |
| 62 | #undef obj_sec_sym_ok_for_reloc |
| 63 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES |
| 64 | |
| 65 | #include "obj-elf.h" |
| 66 | /* Fix any of them that we actually care about. */ |
| 67 | #undef OUTPUT_FLAVOR |
| 68 | #define OUTPUT_FLAVOR mips_output_flavor() |
| 69 | #endif |
| 70 | |
| 71 | #if defined (OBJ_ELF) |
| 72 | #include "elf/mips.h" |
| 73 | #endif |
| 74 | |
| 75 | #ifndef ECOFF_DEBUGGING |
| 76 | #define NO_ECOFF_DEBUGGING |
| 77 | #define ECOFF_DEBUGGING 0 |
| 78 | #endif |
| 79 | |
| 80 | int mips_flag_mdebug = -1; |
| 81 | |
| 82 | #include "ecoff.h" |
| 83 | |
| 84 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 85 | static char *mips_regmask_frag; |
| 86 | #endif |
| 87 | |
| 88 | #define ZERO 0 |
| 89 | #define AT 1 |
| 90 | #define TREG 24 |
| 91 | #define PIC_CALL_REG 25 |
| 92 | #define KT0 26 |
| 93 | #define KT1 27 |
| 94 | #define GP 28 |
| 95 | #define SP 29 |
| 96 | #define FP 30 |
| 97 | #define RA 31 |
| 98 | |
| 99 | #define ILLEGAL_REG (32) |
| 100 | |
| 101 | /* Allow override of standard little-endian ECOFF format. */ |
| 102 | |
| 103 | #ifndef ECOFF_LITTLE_FORMAT |
| 104 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" |
| 105 | #endif |
| 106 | |
| 107 | extern int target_big_endian; |
| 108 | |
| 109 | /* The name of the readonly data section. */ |
| 110 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ |
| 111 | ? ".data" \ |
| 112 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
| 113 | ? ".rdata" \ |
| 114 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
| 115 | ? ".rdata" \ |
| 116 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
| 117 | ? ".rodata" \ |
| 118 | : (abort (), "")) |
| 119 | |
| 120 | /* The ABI to use. */ |
| 121 | enum mips_abi_level |
| 122 | { |
| 123 | NO_ABI = 0, |
| 124 | O32_ABI, |
| 125 | O64_ABI, |
| 126 | N32_ABI, |
| 127 | N64_ABI, |
| 128 | EABI_ABI |
| 129 | }; |
| 130 | |
| 131 | /* MIPS ABI we are using for this output file. */ |
| 132 | static enum mips_abi_level mips_abi = NO_ABI; |
| 133 | |
| 134 | /* This is the set of options which may be modified by the .set |
| 135 | pseudo-op. We use a struct so that .set push and .set pop are more |
| 136 | reliable. */ |
| 137 | |
| 138 | struct mips_set_options |
| 139 | { |
| 140 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
| 141 | if it has not been initialized. Changed by `.set mipsN', and the |
| 142 | -mipsN command line option, and the default CPU. */ |
| 143 | int isa; |
| 144 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
| 145 | if they have not been initialized. Changed by `.set <asename>', by |
| 146 | command line options, and based on the default architecture. */ |
| 147 | int ase_mips3d; |
| 148 | int ase_mdmx; |
| 149 | /* Whether we are assembling for the mips16 processor. 0 if we are |
| 150 | not, 1 if we are, and -1 if the value has not been initialized. |
| 151 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and |
| 152 | -nomips16 command line options, and the default CPU. */ |
| 153 | int mips16; |
| 154 | /* Non-zero if we should not reorder instructions. Changed by `.set |
| 155 | reorder' and `.set noreorder'. */ |
| 156 | int noreorder; |
| 157 | /* Non-zero if we should not permit the $at ($1) register to be used |
| 158 | in instructions. Changed by `.set at' and `.set noat'. */ |
| 159 | int noat; |
| 160 | /* Non-zero if we should warn when a macro instruction expands into |
| 161 | more than one machine instruction. Changed by `.set nomacro' and |
| 162 | `.set macro'. */ |
| 163 | int warn_about_macros; |
| 164 | /* Non-zero if we should not move instructions. Changed by `.set |
| 165 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ |
| 166 | int nomove; |
| 167 | /* Non-zero if we should not optimize branches by moving the target |
| 168 | of the branch into the delay slot. Actually, we don't perform |
| 169 | this optimization anyhow. Changed by `.set bopt' and `.set |
| 170 | nobopt'. */ |
| 171 | int nobopt; |
| 172 | /* Non-zero if we should not autoextend mips16 instructions. |
| 173 | Changed by `.set autoextend' and `.set noautoextend'. */ |
| 174 | int noautoextend; |
| 175 | /* Restrict general purpose registers and floating point registers |
| 176 | to 32 bit. This is initially determined when -mgp32 or -mfp32 |
| 177 | is passed but can changed if the assembler code uses .set mipsN. */ |
| 178 | int gp32; |
| 179 | int fp32; |
| 180 | }; |
| 181 | |
| 182 | /* True if -mgp32 was passed. */ |
| 183 | static int file_mips_gp32 = -1; |
| 184 | |
| 185 | /* True if -mfp32 was passed. */ |
| 186 | static int file_mips_fp32 = -1; |
| 187 | |
| 188 | /* This is the struct we use to hold the current set of options. Note |
| 189 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
| 190 | -1 to indicate that they have not been initialized. */ |
| 191 | |
| 192 | static struct mips_set_options mips_opts = |
| 193 | { |
| 194 | ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0 |
| 195 | }; |
| 196 | |
| 197 | /* These variables are filled in with the masks of registers used. |
| 198 | The object format code reads them and puts them in the appropriate |
| 199 | place. */ |
| 200 | unsigned long mips_gprmask; |
| 201 | unsigned long mips_cprmask[4]; |
| 202 | |
| 203 | /* MIPS ISA we are using for this output file. */ |
| 204 | static int file_mips_isa = ISA_UNKNOWN; |
| 205 | |
| 206 | /* True if -mips16 was passed or implied by arguments passed on the |
| 207 | command line (e.g., by -march). */ |
| 208 | static int file_ase_mips16; |
| 209 | |
| 210 | /* True if -mips3d was passed or implied by arguments passed on the |
| 211 | command line (e.g., by -march). */ |
| 212 | static int file_ase_mips3d; |
| 213 | |
| 214 | /* True if -mdmx was passed or implied by arguments passed on the |
| 215 | command line (e.g., by -march). */ |
| 216 | static int file_ase_mdmx; |
| 217 | |
| 218 | /* The argument of the -march= flag. The architecture we are assembling. */ |
| 219 | static int mips_arch = CPU_UNKNOWN; |
| 220 | static const char *mips_arch_string; |
| 221 | static const struct mips_cpu_info *mips_arch_info; |
| 222 | |
| 223 | /* The argument of the -mtune= flag. The architecture for which we |
| 224 | are optimizing. */ |
| 225 | static int mips_tune = CPU_UNKNOWN; |
| 226 | static const char *mips_tune_string; |
| 227 | static const struct mips_cpu_info *mips_tune_info; |
| 228 | |
| 229 | /* True when generating 32-bit code for a 64-bit processor. */ |
| 230 | static int mips_32bitmode = 0; |
| 231 | |
| 232 | /* Some ISA's have delay slots for instructions which read or write |
| 233 | from a coprocessor (eg. mips1-mips3); some don't (eg mips4). |
| 234 | Return true if instructions marked INSN_LOAD_COPROC_DELAY, |
| 235 | INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a |
| 236 | delay slot in this ISA. The uses of this macro assume that any |
| 237 | ISA that has delay slots for one of these, has them for all. They |
| 238 | also assume that ISAs which don't have delays for these insns, don't |
| 239 | have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */ |
| 240 | #define ISA_HAS_COPROC_DELAYS(ISA) ( \ |
| 241 | (ISA) == ISA_MIPS1 \ |
| 242 | || (ISA) == ISA_MIPS2 \ |
| 243 | || (ISA) == ISA_MIPS3 \ |
| 244 | ) |
| 245 | |
| 246 | /* True if the given ABI requires 32-bit registers. */ |
| 247 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) |
| 248 | |
| 249 | /* Likewise 64-bit registers. */ |
| 250 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
| 251 | ((ABI) == N32_ABI \ |
| 252 | || (ABI) == N64_ABI \ |
| 253 | || (ABI) == O64_ABI) |
| 254 | |
| 255 | /* Return true if ISA supports 64 bit gp register instructions. */ |
| 256 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
| 257 | (ISA) == ISA_MIPS3 \ |
| 258 | || (ISA) == ISA_MIPS4 \ |
| 259 | || (ISA) == ISA_MIPS5 \ |
| 260 | || (ISA) == ISA_MIPS64 \ |
| 261 | ) |
| 262 | |
| 263 | #define HAVE_32BIT_GPRS \ |
| 264 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
| 265 | |
| 266 | #define HAVE_32BIT_FPRS \ |
| 267 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
| 268 | |
| 269 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) |
| 270 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) |
| 271 | |
| 272 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
| 273 | |
| 274 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
| 275 | |
| 276 | /* We can only have 64bit addresses if the object file format |
| 277 | supports it. */ |
| 278 | #define HAVE_32BIT_ADDRESSES \ |
| 279 | (HAVE_32BIT_GPRS \ |
| 280 | || ((bfd_arch_bits_per_address (stdoutput) == 32 \ |
| 281 | || ! HAVE_64BIT_OBJECTS) \ |
| 282 | && mips_pic != EMBEDDED_PIC)) |
| 283 | |
| 284 | #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES) |
| 285 | |
| 286 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
| 287 | #define CPU_HAS_MIPS16(cpu) \ |
| 288 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0) |
| 289 | |
| 290 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
| 291 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ |
| 292 | ) |
| 293 | |
| 294 | /* Return true if the given CPU supports the MDMX ASE. */ |
| 295 | #define CPU_HAS_MDMX(cpu) (false \ |
| 296 | ) |
| 297 | |
| 298 | /* Whether the processor uses hardware interlocks to protect |
| 299 | reads from the HI and LO registers, and thus does not |
| 300 | require nops to be inserted. */ |
| 301 | |
| 302 | #define hilo_interlocks (mips_arch == CPU_R4010 \ |
| 303 | || mips_arch == CPU_SB1 \ |
| 304 | ) |
| 305 | |
| 306 | /* Whether the processor uses hardware interlocks to protect reads |
| 307 | from the GPRs, and thus does not require nops to be inserted. */ |
| 308 | #define gpr_interlocks \ |
| 309 | (mips_opts.isa != ISA_MIPS1 \ |
| 310 | || mips_arch == CPU_R3900) |
| 311 | |
| 312 | /* As with other "interlocks" this is used by hardware that has FP |
| 313 | (co-processor) interlocks. */ |
| 314 | /* Itbl support may require additional care here. */ |
| 315 | #define cop_interlocks (mips_arch == CPU_R4300 \ |
| 316 | || mips_arch == CPU_SB1 \ |
| 317 | ) |
| 318 | |
| 319 | /* Is this a mfhi or mflo instruction? */ |
| 320 | #define MF_HILO_INSN(PINFO) \ |
| 321 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
| 322 | |
| 323 | /* MIPS PIC level. */ |
| 324 | |
| 325 | enum mips_pic_level |
| 326 | { |
| 327 | /* Do not generate PIC code. */ |
| 328 | NO_PIC, |
| 329 | |
| 330 | /* Generate PIC code as in the SVR4 MIPS ABI. */ |
| 331 | SVR4_PIC, |
| 332 | |
| 333 | /* Generate PIC code without using a global offset table: the data |
| 334 | segment has a maximum size of 64K, all data references are off |
| 335 | the $gp register, and all text references are PC relative. This |
| 336 | is used on some embedded systems. */ |
| 337 | EMBEDDED_PIC |
| 338 | }; |
| 339 | |
| 340 | static enum mips_pic_level mips_pic; |
| 341 | |
| 342 | /* Warn about all NOPS that the assembler generates. */ |
| 343 | static int warn_nops = 0; |
| 344 | |
| 345 | /* 1 if we should generate 32 bit offsets from the $gp register in |
| 346 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
| 347 | static int mips_big_got = 0; |
| 348 | |
| 349 | /* 1 if trap instructions should used for overflow rather than break |
| 350 | instructions. */ |
| 351 | static int mips_trap = 0; |
| 352 | |
| 353 | /* 1 if double width floating point constants should not be constructed |
| 354 | by assembling two single width halves into two single width floating |
| 355 | point registers which just happen to alias the double width destination |
| 356 | register. On some architectures this aliasing can be disabled by a bit |
| 357 | in the status register, and the setting of this bit cannot be determined |
| 358 | automatically at assemble time. */ |
| 359 | static int mips_disable_float_construction; |
| 360 | |
| 361 | /* Non-zero if any .set noreorder directives were used. */ |
| 362 | |
| 363 | static int mips_any_noreorder; |
| 364 | |
| 365 | /* Non-zero if nops should be inserted when the register referenced in |
| 366 | an mfhi/mflo instruction is read in the next two instructions. */ |
| 367 | static int mips_7000_hilo_fix; |
| 368 | |
| 369 | /* The size of the small data section. */ |
| 370 | static unsigned int g_switch_value = 8; |
| 371 | /* Whether the -G option was used. */ |
| 372 | static int g_switch_seen = 0; |
| 373 | |
| 374 | #define N_RMASK 0xc4 |
| 375 | #define N_VFP 0xd4 |
| 376 | |
| 377 | /* If we can determine in advance that GP optimization won't be |
| 378 | possible, we can skip the relaxation stuff that tries to produce |
| 379 | GP-relative references. This makes delay slot optimization work |
| 380 | better. |
| 381 | |
| 382 | This function can only provide a guess, but it seems to work for |
| 383 | gcc output. It needs to guess right for gcc, otherwise gcc |
| 384 | will put what it thinks is a GP-relative instruction in a branch |
| 385 | delay slot. |
| 386 | |
| 387 | I don't know if a fix is needed for the SVR4_PIC mode. I've only |
| 388 | fixed it for the non-PIC mode. KR 95/04/07 */ |
| 389 | static int nopic_need_relax PARAMS ((symbolS *, int)); |
| 390 | |
| 391 | /* handle of the OPCODE hash table */ |
| 392 | static struct hash_control *op_hash = NULL; |
| 393 | |
| 394 | /* The opcode hash table we use for the mips16. */ |
| 395 | static struct hash_control *mips16_op_hash = NULL; |
| 396 | |
| 397 | /* This array holds the chars that always start a comment. If the |
| 398 | pre-processor is disabled, these aren't very useful */ |
| 399 | const char comment_chars[] = "#"; |
| 400 | |
| 401 | /* This array holds the chars that only start a comment at the beginning of |
| 402 | a line. If the line seems to have the form '# 123 filename' |
| 403 | .line and .file directives will appear in the pre-processed output */ |
| 404 | /* Note that input_file.c hand checks for '#' at the beginning of the |
| 405 | first line of the input file. This is because the compiler outputs |
| 406 | #NO_APP at the beginning of its output. */ |
| 407 | /* Also note that C style comments are always supported. */ |
| 408 | const char line_comment_chars[] = "#"; |
| 409 | |
| 410 | /* This array holds machine specific line separator characters. */ |
| 411 | const char line_separator_chars[] = ";"; |
| 412 | |
| 413 | /* Chars that can be used to separate mant from exp in floating point nums */ |
| 414 | const char EXP_CHARS[] = "eE"; |
| 415 | |
| 416 | /* Chars that mean this number is a floating point constant */ |
| 417 | /* As in 0f12.456 */ |
| 418 | /* or 0d1.2345e12 */ |
| 419 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
| 420 | |
| 421 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be |
| 422 | changed in read.c . Ideally it shouldn't have to know about it at all, |
| 423 | but nothing is ideal around here. |
| 424 | */ |
| 425 | |
| 426 | static char *insn_error; |
| 427 | |
| 428 | static int auto_align = 1; |
| 429 | |
| 430 | /* When outputting SVR4 PIC code, the assembler needs to know the |
| 431 | offset in the stack frame from which to restore the $gp register. |
| 432 | This is set by the .cprestore pseudo-op, and saved in this |
| 433 | variable. */ |
| 434 | static offsetT mips_cprestore_offset = -1; |
| 435 | |
| 436 | /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
| 437 | more optimizations, it can use a register value instead of a memory-saved |
| 438 | offset and even an other register than $gp as global pointer. */ |
| 439 | static offsetT mips_cpreturn_offset = -1; |
| 440 | static int mips_cpreturn_register = -1; |
| 441 | static int mips_gp_register = GP; |
| 442 | static int mips_gprel_offset = 0; |
| 443 | |
| 444 | /* Whether mips_cprestore_offset has been set in the current function |
| 445 | (or whether it has already been warned about, if not). */ |
| 446 | static int mips_cprestore_valid = 0; |
| 447 | |
| 448 | /* This is the register which holds the stack frame, as set by the |
| 449 | .frame pseudo-op. This is needed to implement .cprestore. */ |
| 450 | static int mips_frame_reg = SP; |
| 451 | |
| 452 | /* Whether mips_frame_reg has been set in the current function |
| 453 | (or whether it has already been warned about, if not). */ |
| 454 | static int mips_frame_reg_valid = 0; |
| 455 | |
| 456 | /* To output NOP instructions correctly, we need to keep information |
| 457 | about the previous two instructions. */ |
| 458 | |
| 459 | /* Whether we are optimizing. The default value of 2 means to remove |
| 460 | unneeded NOPs and swap branch instructions when possible. A value |
| 461 | of 1 means to not swap branches. A value of 0 means to always |
| 462 | insert NOPs. */ |
| 463 | static int mips_optimize = 2; |
| 464 | |
| 465 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is |
| 466 | equivalent to seeing no -g option at all. */ |
| 467 | static int mips_debug = 0; |
| 468 | |
| 469 | /* The previous instruction. */ |
| 470 | static struct mips_cl_insn prev_insn; |
| 471 | |
| 472 | /* The instruction before prev_insn. */ |
| 473 | static struct mips_cl_insn prev_prev_insn; |
| 474 | |
| 475 | /* If we don't want information for prev_insn or prev_prev_insn, we |
| 476 | point the insn_mo field at this dummy integer. */ |
| 477 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; |
| 478 | |
| 479 | /* Non-zero if prev_insn is valid. */ |
| 480 | static int prev_insn_valid; |
| 481 | |
| 482 | /* The frag for the previous instruction. */ |
| 483 | static struct frag *prev_insn_frag; |
| 484 | |
| 485 | /* The offset into prev_insn_frag for the previous instruction. */ |
| 486 | static long prev_insn_where; |
| 487 | |
| 488 | /* The reloc type for the previous instruction, if any. */ |
| 489 | static bfd_reloc_code_real_type prev_insn_reloc_type[3]; |
| 490 | |
| 491 | /* The reloc for the previous instruction, if any. */ |
| 492 | static fixS *prev_insn_fixp[3]; |
| 493 | |
| 494 | /* Non-zero if the previous instruction was in a delay slot. */ |
| 495 | static int prev_insn_is_delay_slot; |
| 496 | |
| 497 | /* Non-zero if the previous instruction was in a .set noreorder. */ |
| 498 | static int prev_insn_unreordered; |
| 499 | |
| 500 | /* Non-zero if the previous instruction uses an extend opcode (if |
| 501 | mips16). */ |
| 502 | static int prev_insn_extended; |
| 503 | |
| 504 | /* Non-zero if the previous previous instruction was in a .set |
| 505 | noreorder. */ |
| 506 | static int prev_prev_insn_unreordered; |
| 507 | |
| 508 | /* If this is set, it points to a frag holding nop instructions which |
| 509 | were inserted before the start of a noreorder section. If those |
| 510 | nops turn out to be unnecessary, the size of the frag can be |
| 511 | decreased. */ |
| 512 | static fragS *prev_nop_frag; |
| 513 | |
| 514 | /* The number of nop instructions we created in prev_nop_frag. */ |
| 515 | static int prev_nop_frag_holds; |
| 516 | |
| 517 | /* The number of nop instructions that we know we need in |
| 518 | prev_nop_frag. */ |
| 519 | static int prev_nop_frag_required; |
| 520 | |
| 521 | /* The number of instructions we've seen since prev_nop_frag. */ |
| 522 | static int prev_nop_frag_since; |
| 523 | |
| 524 | /* For ECOFF and ELF, relocations against symbols are done in two |
| 525 | parts, with a HI relocation and a LO relocation. Each relocation |
| 526 | has only 16 bits of space to store an addend. This means that in |
| 527 | order for the linker to handle carries correctly, it must be able |
| 528 | to locate both the HI and the LO relocation. This means that the |
| 529 | relocations must appear in order in the relocation table. |
| 530 | |
| 531 | In order to implement this, we keep track of each unmatched HI |
| 532 | relocation. We then sort them so that they immediately precede the |
| 533 | corresponding LO relocation. */ |
| 534 | |
| 535 | struct mips_hi_fixup |
| 536 | { |
| 537 | /* Next HI fixup. */ |
| 538 | struct mips_hi_fixup *next; |
| 539 | /* This fixup. */ |
| 540 | fixS *fixp; |
| 541 | /* The section this fixup is in. */ |
| 542 | segT seg; |
| 543 | }; |
| 544 | |
| 545 | /* The list of unmatched HI relocs. */ |
| 546 | |
| 547 | static struct mips_hi_fixup *mips_hi_fixup_list; |
| 548 | |
| 549 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
| 550 | |
| 551 | #define X ILLEGAL_REG |
| 552 | static const int mips32_to_16_reg_map[] = |
| 553 | { |
| 554 | X, X, 2, 3, 4, 5, 6, 7, |
| 555 | X, X, X, X, X, X, X, X, |
| 556 | 0, 1, X, X, X, X, X, X, |
| 557 | X, X, X, X, X, X, X, X |
| 558 | }; |
| 559 | #undef X |
| 560 | |
| 561 | /* Map mips16 register numbers to normal MIPS register numbers. */ |
| 562 | |
| 563 | static const unsigned int mips16_to_32_reg_map[] = |
| 564 | { |
| 565 | 16, 17, 2, 3, 4, 5, 6, 7 |
| 566 | }; |
| 567 | \f |
| 568 | /* Since the MIPS does not have multiple forms of PC relative |
| 569 | instructions, we do not have to do relaxing as is done on other |
| 570 | platforms. However, we do have to handle GP relative addressing |
| 571 | correctly, which turns out to be a similar problem. |
| 572 | |
| 573 | Every macro that refers to a symbol can occur in (at least) two |
| 574 | forms, one with GP relative addressing and one without. For |
| 575 | example, loading a global variable into a register generally uses |
| 576 | a macro instruction like this: |
| 577 | lw $4,i |
| 578 | If i can be addressed off the GP register (this is true if it is in |
| 579 | the .sbss or .sdata section, or if it is known to be smaller than |
| 580 | the -G argument) this will generate the following instruction: |
| 581 | lw $4,i($gp) |
| 582 | This instruction will use a GPREL reloc. If i can not be addressed |
| 583 | off the GP register, the following instruction sequence will be used: |
| 584 | lui $at,i |
| 585 | lw $4,i($at) |
| 586 | In this case the first instruction will have a HI16 reloc, and the |
| 587 | second reloc will have a LO16 reloc. Both relocs will be against |
| 588 | the symbol i. |
| 589 | |
| 590 | The issue here is that we may not know whether i is GP addressable |
| 591 | until after we see the instruction that uses it. Therefore, we |
| 592 | want to be able to choose the final instruction sequence only at |
| 593 | the end of the assembly. This is similar to the way other |
| 594 | platforms choose the size of a PC relative instruction only at the |
| 595 | end of assembly. |
| 596 | |
| 597 | When generating position independent code we do not use GP |
| 598 | addressing in quite the same way, but the issue still arises as |
| 599 | external symbols and local symbols must be handled differently. |
| 600 | |
| 601 | We handle these issues by actually generating both possible |
| 602 | instruction sequences. The longer one is put in a frag_var with |
| 603 | type rs_machine_dependent. We encode what to do with the frag in |
| 604 | the subtype field. We encode (1) the number of existing bytes to |
| 605 | replace, (2) the number of new bytes to use, (3) the offset from |
| 606 | the start of the existing bytes to the first reloc we must generate |
| 607 | (that is, the offset is applied from the start of the existing |
| 608 | bytes after they are replaced by the new bytes, if any), (4) the |
| 609 | offset from the start of the existing bytes to the second reloc, |
| 610 | (5) whether a third reloc is needed (the third reloc is always four |
| 611 | bytes after the second reloc), and (6) whether to warn if this |
| 612 | variant is used (this is sometimes needed if .set nomacro or .set |
| 613 | noat is in effect). All these numbers are reasonably small. |
| 614 | |
| 615 | Generating two instruction sequences must be handled carefully to |
| 616 | ensure that delay slots are handled correctly. Fortunately, there |
| 617 | are a limited number of cases. When the second instruction |
| 618 | sequence is generated, append_insn is directed to maintain the |
| 619 | existing delay slot information, so it continues to apply to any |
| 620 | code after the second instruction sequence. This means that the |
| 621 | second instruction sequence must not impose any requirements not |
| 622 | required by the first instruction sequence. |
| 623 | |
| 624 | These variant frags are then handled in functions called by the |
| 625 | machine independent code. md_estimate_size_before_relax returns |
| 626 | the final size of the frag. md_convert_frag sets up the final form |
| 627 | of the frag. tc_gen_reloc adjust the first reloc and adds a second |
| 628 | one if needed. */ |
| 629 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ |
| 630 | ((relax_substateT) \ |
| 631 | (((old) << 23) \ |
| 632 | | ((new) << 16) \ |
| 633 | | (((reloc1) + 64) << 9) \ |
| 634 | | (((reloc2) + 64) << 2) \ |
| 635 | | ((reloc3) ? (1 << 1) : 0) \ |
| 636 | | ((warn) ? 1 : 0))) |
| 637 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) |
| 638 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) |
| 639 | #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64) |
| 640 | #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64) |
| 641 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
| 642 | #define RELAX_WARN(i) ((i) & 1) |
| 643 | |
| 644 | /* For mips16 code, we use an entirely different form of relaxation. |
| 645 | mips16 supports two versions of most instructions which take |
| 646 | immediate values: a small one which takes some small value, and a |
| 647 | larger one which takes a 16 bit value. Since branches also follow |
| 648 | this pattern, relaxing these values is required. |
| 649 | |
| 650 | We can assemble both mips16 and normal MIPS code in a single |
| 651 | object. Therefore, we need to support this type of relaxation at |
| 652 | the same time that we support the relaxation described above. We |
| 653 | use the high bit of the subtype field to distinguish these cases. |
| 654 | |
| 655 | The information we store for this type of relaxation is the |
| 656 | argument code found in the opcode file for this relocation, whether |
| 657 | the user explicitly requested a small or extended form, and whether |
| 658 | the relocation is in a jump or jal delay slot. That tells us the |
| 659 | size of the value, and how it should be stored. We also store |
| 660 | whether the fragment is considered to be extended or not. We also |
| 661 | store whether this is known to be a branch to a different section, |
| 662 | whether we have tried to relax this frag yet, and whether we have |
| 663 | ever extended a PC relative fragment because of a shift count. */ |
| 664 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ |
| 665 | (0x80000000 \ |
| 666 | | ((type) & 0xff) \ |
| 667 | | ((small) ? 0x100 : 0) \ |
| 668 | | ((ext) ? 0x200 : 0) \ |
| 669 | | ((dslot) ? 0x400 : 0) \ |
| 670 | | ((jal_dslot) ? 0x800 : 0)) |
| 671 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) |
| 672 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
| 673 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) |
| 674 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) |
| 675 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) |
| 676 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) |
| 677 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) |
| 678 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) |
| 679 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) |
| 680 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) |
| 681 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) |
| 682 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) |
| 683 | \f |
| 684 | /* Prototypes for static functions. */ |
| 685 | |
| 686 | #ifdef __STDC__ |
| 687 | #define internalError() \ |
| 688 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
| 689 | #else |
| 690 | #define internalError() as_fatal (_("MIPS internal Error")); |
| 691 | #endif |
| 692 | |
| 693 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
| 694 | |
| 695 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
| 696 | unsigned int reg, enum mips_regclass class)); |
| 697 | static int reg_needs_delay PARAMS ((unsigned int)); |
| 698 | static void mips16_mark_labels PARAMS ((void)); |
| 699 | static void append_insn PARAMS ((char *place, |
| 700 | struct mips_cl_insn * ip, |
| 701 | expressionS * p, |
| 702 | bfd_reloc_code_real_type *r, |
| 703 | boolean)); |
| 704 | static void mips_no_prev_insn PARAMS ((int)); |
| 705 | static void mips_emit_delays PARAMS ((boolean)); |
| 706 | #ifdef USE_STDARG |
| 707 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
| 708 | const char *name, const char *fmt, |
| 709 | ...)); |
| 710 | #else |
| 711 | static void macro_build (); |
| 712 | #endif |
| 713 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, |
| 714 | const char *, const char *, |
| 715 | va_list)); |
| 716 | static void macro_build_jalr PARAMS ((int, expressionS *)); |
| 717 | static void macro_build_lui PARAMS ((char *place, int *counter, |
| 718 | expressionS * ep, int regnum)); |
| 719 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
| 720 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
| 721 | expressionS *)); |
| 722 | static void load_register PARAMS ((int *, int, expressionS *, int)); |
| 723 | static void load_address PARAMS ((int *, int, expressionS *, int *)); |
| 724 | static void move_register PARAMS ((int *, int, int)); |
| 725 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
| 726 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); |
| 727 | #ifdef LOSING_COMPILER |
| 728 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); |
| 729 | #endif |
| 730 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
| 731 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
| 732 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, |
| 733 | boolean, boolean, unsigned long *, |
| 734 | boolean *, unsigned short *)); |
| 735 | static int my_getPercentOp PARAMS ((char **, unsigned int *, int *)); |
| 736 | static int my_getSmallParser PARAMS ((char **, unsigned int *, int *)); |
| 737 | static int my_getSmallExpression PARAMS ((expressionS *, char *)); |
| 738 | static void my_getExpression PARAMS ((expressionS *, char *)); |
| 739 | #ifdef OBJ_ELF |
| 740 | static int support_64bit_objects PARAMS((void)); |
| 741 | #endif |
| 742 | static void mips_set_option_string PARAMS ((const char **, const char *)); |
| 743 | static symbolS *get_symbol PARAMS ((void)); |
| 744 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
| 745 | static void s_align PARAMS ((int)); |
| 746 | static void s_change_sec PARAMS ((int)); |
| 747 | static void s_cons PARAMS ((int)); |
| 748 | static void s_float_cons PARAMS ((int)); |
| 749 | static void s_mips_globl PARAMS ((int)); |
| 750 | static void s_option PARAMS ((int)); |
| 751 | static void s_mipsset PARAMS ((int)); |
| 752 | static void s_abicalls PARAMS ((int)); |
| 753 | static void s_cpload PARAMS ((int)); |
| 754 | static void s_cpsetup PARAMS ((int)); |
| 755 | static void s_cplocal PARAMS ((int)); |
| 756 | static void s_cprestore PARAMS ((int)); |
| 757 | static void s_cpreturn PARAMS ((int)); |
| 758 | static void s_gpvalue PARAMS ((int)); |
| 759 | static void s_gpword PARAMS ((int)); |
| 760 | static void s_cpadd PARAMS ((int)); |
| 761 | static void s_insn PARAMS ((int)); |
| 762 | static void md_obj_begin PARAMS ((void)); |
| 763 | static void md_obj_end PARAMS ((void)); |
| 764 | static long get_number PARAMS ((void)); |
| 765 | static void s_mips_ent PARAMS ((int)); |
| 766 | static void s_mips_end PARAMS ((int)); |
| 767 | static void s_mips_frame PARAMS ((int)); |
| 768 | static void s_mips_mask PARAMS ((int)); |
| 769 | static void s_mips_stab PARAMS ((int)); |
| 770 | static void s_mips_weakext PARAMS ((int)); |
| 771 | static void s_mips_file PARAMS ((int)); |
| 772 | static void s_mips_loc PARAMS ((int)); |
| 773 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); |
| 774 | static int validate_mips_insn PARAMS ((const struct mips_opcode *)); |
| 775 | static void show PARAMS ((FILE *, const char *, int *, int *)); |
| 776 | #ifdef OBJ_ELF |
| 777 | static int mips_need_elf_addend_fixup PARAMS ((fixS *)); |
| 778 | #endif |
| 779 | |
| 780 | /* Return values of my_getSmallExpression(). */ |
| 781 | |
| 782 | enum small_ex_type |
| 783 | { |
| 784 | S_EX_NONE = 0, |
| 785 | S_EX_REGISTER, |
| 786 | |
| 787 | /* Direct relocation creation by %percent_op(). */ |
| 788 | S_EX_HALF, |
| 789 | S_EX_HI, |
| 790 | S_EX_LO, |
| 791 | S_EX_GP_REL, |
| 792 | S_EX_GOT, |
| 793 | S_EX_CALL16, |
| 794 | S_EX_GOT_DISP, |
| 795 | S_EX_GOT_PAGE, |
| 796 | S_EX_GOT_OFST, |
| 797 | S_EX_GOT_HI, |
| 798 | S_EX_GOT_LO, |
| 799 | S_EX_NEG, |
| 800 | S_EX_HIGHER, |
| 801 | S_EX_HIGHEST, |
| 802 | S_EX_CALL_HI, |
| 803 | S_EX_CALL_LO |
| 804 | }; |
| 805 | |
| 806 | /* Table and functions used to map between CPU/ISA names, and |
| 807 | ISA levels, and CPU numbers. */ |
| 808 | |
| 809 | struct mips_cpu_info |
| 810 | { |
| 811 | const char *name; /* CPU or ISA name. */ |
| 812 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ |
| 813 | int isa; /* ISA level. */ |
| 814 | int cpu; /* CPU number (default CPU if ISA). */ |
| 815 | }; |
| 816 | |
| 817 | static void mips_set_architecture PARAMS ((const struct mips_cpu_info *)); |
| 818 | static void mips_set_tune PARAMS ((const struct mips_cpu_info *)); |
| 819 | static boolean mips_strict_matching_cpu_name_p PARAMS ((const char *, |
| 820 | const char *)); |
| 821 | static boolean mips_matching_cpu_name_p PARAMS ((const char *, const char *)); |
| 822 | static const struct mips_cpu_info *mips_parse_cpu PARAMS ((const char *, |
| 823 | const char *)); |
| 824 | static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int)); |
| 825 | \f |
| 826 | /* Pseudo-op table. |
| 827 | |
| 828 | The following pseudo-ops from the Kane and Heinrich MIPS book |
| 829 | should be defined here, but are currently unsupported: .alias, |
| 830 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. |
| 831 | |
| 832 | The following pseudo-ops from the Kane and Heinrich MIPS book are |
| 833 | specific to the type of debugging information being generated, and |
| 834 | should be defined by the object format: .aent, .begin, .bend, |
| 835 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, |
| 836 | .vreg. |
| 837 | |
| 838 | The following pseudo-ops from the Kane and Heinrich MIPS book are |
| 839 | not MIPS CPU specific, but are also not specific to the object file |
| 840 | format. This file is probably the best place to define them, but |
| 841 | they are not currently supported: .asm0, .endr, .lab, .repeat, |
| 842 | .struct. */ |
| 843 | |
| 844 | static const pseudo_typeS mips_pseudo_table[] = |
| 845 | { |
| 846 | /* MIPS specific pseudo-ops. */ |
| 847 | {"option", s_option, 0}, |
| 848 | {"set", s_mipsset, 0}, |
| 849 | {"rdata", s_change_sec, 'r'}, |
| 850 | {"sdata", s_change_sec, 's'}, |
| 851 | {"livereg", s_ignore, 0}, |
| 852 | {"abicalls", s_abicalls, 0}, |
| 853 | {"cpload", s_cpload, 0}, |
| 854 | {"cpsetup", s_cpsetup, 0}, |
| 855 | {"cplocal", s_cplocal, 0}, |
| 856 | {"cprestore", s_cprestore, 0}, |
| 857 | {"cpreturn", s_cpreturn, 0}, |
| 858 | {"gpvalue", s_gpvalue, 0}, |
| 859 | {"gpword", s_gpword, 0}, |
| 860 | {"cpadd", s_cpadd, 0}, |
| 861 | {"insn", s_insn, 0}, |
| 862 | |
| 863 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
| 864 | chips. */ |
| 865 | {"asciiz", stringer, 1}, |
| 866 | {"bss", s_change_sec, 'b'}, |
| 867 | {"err", s_err, 0}, |
| 868 | {"half", s_cons, 1}, |
| 869 | {"dword", s_cons, 3}, |
| 870 | {"weakext", s_mips_weakext, 0}, |
| 871 | |
| 872 | /* These pseudo-ops are defined in read.c, but must be overridden |
| 873 | here for one reason or another. */ |
| 874 | {"align", s_align, 0}, |
| 875 | {"byte", s_cons, 0}, |
| 876 | {"data", s_change_sec, 'd'}, |
| 877 | {"double", s_float_cons, 'd'}, |
| 878 | {"float", s_float_cons, 'f'}, |
| 879 | {"globl", s_mips_globl, 0}, |
| 880 | {"global", s_mips_globl, 0}, |
| 881 | {"hword", s_cons, 1}, |
| 882 | {"int", s_cons, 2}, |
| 883 | {"long", s_cons, 2}, |
| 884 | {"octa", s_cons, 4}, |
| 885 | {"quad", s_cons, 3}, |
| 886 | {"short", s_cons, 1}, |
| 887 | {"single", s_float_cons, 'f'}, |
| 888 | {"stabn", s_mips_stab, 'n'}, |
| 889 | {"text", s_change_sec, 't'}, |
| 890 | {"word", s_cons, 2}, |
| 891 | |
| 892 | { "extern", ecoff_directive_extern, 0}, |
| 893 | |
| 894 | { NULL, NULL, 0 }, |
| 895 | }; |
| 896 | |
| 897 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
| 898 | { |
| 899 | /* These pseudo-ops should be defined by the object file format. |
| 900 | However, a.out doesn't support them, so we have versions here. */ |
| 901 | {"aent", s_mips_ent, 1}, |
| 902 | {"bgnb", s_ignore, 0}, |
| 903 | {"end", s_mips_end, 0}, |
| 904 | {"endb", s_ignore, 0}, |
| 905 | {"ent", s_mips_ent, 0}, |
| 906 | {"file", s_mips_file, 0}, |
| 907 | {"fmask", s_mips_mask, 'F'}, |
| 908 | {"frame", s_mips_frame, 0}, |
| 909 | {"loc", s_mips_loc, 0}, |
| 910 | {"mask", s_mips_mask, 'R'}, |
| 911 | {"verstamp", s_ignore, 0}, |
| 912 | { NULL, NULL, 0 }, |
| 913 | }; |
| 914 | |
| 915 | extern void pop_insert PARAMS ((const pseudo_typeS *)); |
| 916 | |
| 917 | void |
| 918 | mips_pop_insert () |
| 919 | { |
| 920 | pop_insert (mips_pseudo_table); |
| 921 | if (! ECOFF_DEBUGGING) |
| 922 | pop_insert (mips_nonecoff_pseudo_table); |
| 923 | } |
| 924 | \f |
| 925 | /* Symbols labelling the current insn. */ |
| 926 | |
| 927 | struct insn_label_list |
| 928 | { |
| 929 | struct insn_label_list *next; |
| 930 | symbolS *label; |
| 931 | }; |
| 932 | |
| 933 | static struct insn_label_list *insn_labels; |
| 934 | static struct insn_label_list *free_insn_labels; |
| 935 | |
| 936 | static void mips_clear_insn_labels PARAMS ((void)); |
| 937 | |
| 938 | static inline void |
| 939 | mips_clear_insn_labels () |
| 940 | { |
| 941 | register struct insn_label_list **pl; |
| 942 | |
| 943 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) |
| 944 | ; |
| 945 | *pl = insn_labels; |
| 946 | insn_labels = NULL; |
| 947 | } |
| 948 | \f |
| 949 | static char *expr_end; |
| 950 | |
| 951 | /* Expressions which appear in instructions. These are set by |
| 952 | mips_ip. */ |
| 953 | |
| 954 | static expressionS imm_expr; |
| 955 | static expressionS offset_expr; |
| 956 | |
| 957 | /* Relocs associated with imm_expr and offset_expr. */ |
| 958 | |
| 959 | static bfd_reloc_code_real_type imm_reloc[3] |
| 960 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; |
| 961 | static bfd_reloc_code_real_type offset_reloc[3] |
| 962 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; |
| 963 | |
| 964 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ |
| 965 | |
| 966 | static boolean imm_unmatched_hi; |
| 967 | |
| 968 | /* These are set by mips16_ip if an explicit extension is used. */ |
| 969 | |
| 970 | static boolean mips16_small, mips16_ext; |
| 971 | |
| 972 | /* The pdr segment for per procedure frame/regmask info. Not used for |
| 973 | ECOFF debugging. */ |
| 974 | |
| 975 | static segT pdr_seg; |
| 976 | |
| 977 | /* The default target format to use. */ |
| 978 | |
| 979 | const char * |
| 980 | mips_target_format () |
| 981 | { |
| 982 | switch (OUTPUT_FLAVOR) |
| 983 | { |
| 984 | case bfd_target_aout_flavour: |
| 985 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; |
| 986 | case bfd_target_ecoff_flavour: |
| 987 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; |
| 988 | case bfd_target_coff_flavour: |
| 989 | return "pe-mips"; |
| 990 | case bfd_target_elf_flavour: |
| 991 | #ifdef TE_TMIPS |
| 992 | /* This is traditional mips. */ |
| 993 | return (target_big_endian |
| 994 | ? (HAVE_64BIT_OBJECTS |
| 995 | ? "elf64-tradbigmips" |
| 996 | : (HAVE_NEWABI |
| 997 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) |
| 998 | : (HAVE_64BIT_OBJECTS |
| 999 | ? "elf64-tradlittlemips" |
| 1000 | : (HAVE_NEWABI |
| 1001 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); |
| 1002 | #else |
| 1003 | return (target_big_endian |
| 1004 | ? (HAVE_64BIT_OBJECTS |
| 1005 | ? "elf64-bigmips" |
| 1006 | : (HAVE_NEWABI |
| 1007 | ? "elf32-nbigmips" : "elf32-bigmips")) |
| 1008 | : (HAVE_64BIT_OBJECTS |
| 1009 | ? "elf64-littlemips" |
| 1010 | : (HAVE_NEWABI |
| 1011 | ? "elf32-nlittlemips" : "elf32-littlemips"))); |
| 1012 | #endif |
| 1013 | default: |
| 1014 | abort (); |
| 1015 | return NULL; |
| 1016 | } |
| 1017 | } |
| 1018 | |
| 1019 | /* This function is called once, at assembler startup time. It should |
| 1020 | set up all the tables, etc. that the MD part of the assembler will need. */ |
| 1021 | |
| 1022 | void |
| 1023 | md_begin () |
| 1024 | { |
| 1025 | register const char *retval = NULL; |
| 1026 | int i = 0; |
| 1027 | int broken = 0; |
| 1028 | |
| 1029 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch)) |
| 1030 | as_warn (_("Could not set architecture and machine")); |
| 1031 | |
| 1032 | op_hash = hash_new (); |
| 1033 | |
| 1034 | for (i = 0; i < NUMOPCODES;) |
| 1035 | { |
| 1036 | const char *name = mips_opcodes[i].name; |
| 1037 | |
| 1038 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
| 1039 | if (retval != NULL) |
| 1040 | { |
| 1041 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), |
| 1042 | mips_opcodes[i].name, retval); |
| 1043 | /* Probably a memory allocation problem? Give up now. */ |
| 1044 | as_fatal (_("Broken assembler. No assembly attempted.")); |
| 1045 | } |
| 1046 | do |
| 1047 | { |
| 1048 | if (mips_opcodes[i].pinfo != INSN_MACRO) |
| 1049 | { |
| 1050 | if (!validate_mips_insn (&mips_opcodes[i])) |
| 1051 | broken = 1; |
| 1052 | } |
| 1053 | ++i; |
| 1054 | } |
| 1055 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); |
| 1056 | } |
| 1057 | |
| 1058 | mips16_op_hash = hash_new (); |
| 1059 | |
| 1060 | i = 0; |
| 1061 | while (i < bfd_mips16_num_opcodes) |
| 1062 | { |
| 1063 | const char *name = mips16_opcodes[i].name; |
| 1064 | |
| 1065 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); |
| 1066 | if (retval != NULL) |
| 1067 | as_fatal (_("internal: can't hash `%s': %s"), |
| 1068 | mips16_opcodes[i].name, retval); |
| 1069 | do |
| 1070 | { |
| 1071 | if (mips16_opcodes[i].pinfo != INSN_MACRO |
| 1072 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) |
| 1073 | != mips16_opcodes[i].match)) |
| 1074 | { |
| 1075 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), |
| 1076 | mips16_opcodes[i].name, mips16_opcodes[i].args); |
| 1077 | broken = 1; |
| 1078 | } |
| 1079 | ++i; |
| 1080 | } |
| 1081 | while (i < bfd_mips16_num_opcodes |
| 1082 | && strcmp (mips16_opcodes[i].name, name) == 0); |
| 1083 | } |
| 1084 | |
| 1085 | if (broken) |
| 1086 | as_fatal (_("Broken assembler. No assembly attempted.")); |
| 1087 | |
| 1088 | /* We add all the general register names to the symbol table. This |
| 1089 | helps us detect invalid uses of them. */ |
| 1090 | for (i = 0; i < 32; i++) |
| 1091 | { |
| 1092 | char buf[5]; |
| 1093 | |
| 1094 | sprintf (buf, "$%d", i); |
| 1095 | symbol_table_insert (symbol_new (buf, reg_section, i, |
| 1096 | &zero_address_frag)); |
| 1097 | } |
| 1098 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
| 1099 | &zero_address_frag)); |
| 1100 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
| 1101 | &zero_address_frag)); |
| 1102 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, |
| 1103 | &zero_address_frag)); |
| 1104 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, |
| 1105 | &zero_address_frag)); |
| 1106 | symbol_table_insert (symbol_new ("$at", reg_section, AT, |
| 1107 | &zero_address_frag)); |
| 1108 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, |
| 1109 | &zero_address_frag)); |
| 1110 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, |
| 1111 | &zero_address_frag)); |
| 1112 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
| 1113 | &zero_address_frag)); |
| 1114 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
| 1115 | &zero_address_frag)); |
| 1116 | |
| 1117 | mips_no_prev_insn (false); |
| 1118 | |
| 1119 | mips_gprmask = 0; |
| 1120 | mips_cprmask[0] = 0; |
| 1121 | mips_cprmask[1] = 0; |
| 1122 | mips_cprmask[2] = 0; |
| 1123 | mips_cprmask[3] = 0; |
| 1124 | |
| 1125 | /* set the default alignment for the text section (2**2) */ |
| 1126 | record_alignment (text_section, 2); |
| 1127 | |
| 1128 | if (USE_GLOBAL_POINTER_OPT) |
| 1129 | bfd_set_gp_size (stdoutput, g_switch_value); |
| 1130 | |
| 1131 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
| 1132 | { |
| 1133 | /* On a native system, sections must be aligned to 16 byte |
| 1134 | boundaries. When configured for an embedded ELF target, we |
| 1135 | don't bother. */ |
| 1136 | if (strcmp (TARGET_OS, "elf") != 0) |
| 1137 | { |
| 1138 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); |
| 1139 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); |
| 1140 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); |
| 1141 | } |
| 1142 | |
| 1143 | /* Create a .reginfo section for register masks and a .mdebug |
| 1144 | section for debugging information. */ |
| 1145 | { |
| 1146 | segT seg; |
| 1147 | subsegT subseg; |
| 1148 | flagword flags; |
| 1149 | segT sec; |
| 1150 | |
| 1151 | seg = now_seg; |
| 1152 | subseg = now_subseg; |
| 1153 | |
| 1154 | /* The ABI says this section should be loaded so that the |
| 1155 | running program can access it. However, we don't load it |
| 1156 | if we are configured for an embedded target */ |
| 1157 | flags = SEC_READONLY | SEC_DATA; |
| 1158 | if (strcmp (TARGET_OS, "elf") != 0) |
| 1159 | flags |= SEC_ALLOC | SEC_LOAD; |
| 1160 | |
| 1161 | if (mips_abi != N64_ABI) |
| 1162 | { |
| 1163 | sec = subseg_new (".reginfo", (subsegT) 0); |
| 1164 | |
| 1165 | bfd_set_section_flags (stdoutput, sec, flags); |
| 1166 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); |
| 1167 | |
| 1168 | #ifdef OBJ_ELF |
| 1169 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
| 1170 | #endif |
| 1171 | } |
| 1172 | else |
| 1173 | { |
| 1174 | /* The 64-bit ABI uses a .MIPS.options section rather than |
| 1175 | .reginfo section. */ |
| 1176 | sec = subseg_new (".MIPS.options", (subsegT) 0); |
| 1177 | bfd_set_section_flags (stdoutput, sec, flags); |
| 1178 | bfd_set_section_alignment (stdoutput, sec, 3); |
| 1179 | |
| 1180 | #ifdef OBJ_ELF |
| 1181 | /* Set up the option header. */ |
| 1182 | { |
| 1183 | Elf_Internal_Options opthdr; |
| 1184 | char *f; |
| 1185 | |
| 1186 | opthdr.kind = ODK_REGINFO; |
| 1187 | opthdr.size = (sizeof (Elf_External_Options) |
| 1188 | + sizeof (Elf64_External_RegInfo)); |
| 1189 | opthdr.section = 0; |
| 1190 | opthdr.info = 0; |
| 1191 | f = frag_more (sizeof (Elf_External_Options)); |
| 1192 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, |
| 1193 | (Elf_External_Options *) f); |
| 1194 | |
| 1195 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); |
| 1196 | } |
| 1197 | #endif |
| 1198 | } |
| 1199 | |
| 1200 | if (ECOFF_DEBUGGING) |
| 1201 | { |
| 1202 | sec = subseg_new (".mdebug", (subsegT) 0); |
| 1203 | (void) bfd_set_section_flags (stdoutput, sec, |
| 1204 | SEC_HAS_CONTENTS | SEC_READONLY); |
| 1205 | (void) bfd_set_section_alignment (stdoutput, sec, 2); |
| 1206 | } |
| 1207 | #ifdef OBJ_ELF |
| 1208 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
| 1209 | { |
| 1210 | pdr_seg = subseg_new (".pdr", (subsegT) 0); |
| 1211 | (void) bfd_set_section_flags (stdoutput, pdr_seg, |
| 1212 | SEC_READONLY | SEC_RELOC |
| 1213 | | SEC_DEBUGGING); |
| 1214 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); |
| 1215 | } |
| 1216 | #endif |
| 1217 | |
| 1218 | subseg_set (seg, subseg); |
| 1219 | } |
| 1220 | } |
| 1221 | |
| 1222 | if (! ECOFF_DEBUGGING) |
| 1223 | md_obj_begin (); |
| 1224 | } |
| 1225 | |
| 1226 | void |
| 1227 | md_mips_end () |
| 1228 | { |
| 1229 | if (! ECOFF_DEBUGGING) |
| 1230 | md_obj_end (); |
| 1231 | } |
| 1232 | |
| 1233 | void |
| 1234 | md_assemble (str) |
| 1235 | char *str; |
| 1236 | { |
| 1237 | struct mips_cl_insn insn; |
| 1238 | bfd_reloc_code_real_type unused_reloc[3] |
| 1239 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; |
| 1240 | |
| 1241 | imm_expr.X_op = O_absent; |
| 1242 | imm_unmatched_hi = false; |
| 1243 | offset_expr.X_op = O_absent; |
| 1244 | imm_reloc[0] = BFD_RELOC_UNUSED; |
| 1245 | imm_reloc[1] = BFD_RELOC_UNUSED; |
| 1246 | imm_reloc[2] = BFD_RELOC_UNUSED; |
| 1247 | offset_reloc[0] = BFD_RELOC_UNUSED; |
| 1248 | offset_reloc[1] = BFD_RELOC_UNUSED; |
| 1249 | offset_reloc[2] = BFD_RELOC_UNUSED; |
| 1250 | |
| 1251 | if (mips_opts.mips16) |
| 1252 | mips16_ip (str, &insn); |
| 1253 | else |
| 1254 | { |
| 1255 | mips_ip (str, &insn); |
| 1256 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
| 1257 | str, insn.insn_opcode)); |
| 1258 | } |
| 1259 | |
| 1260 | if (insn_error) |
| 1261 | { |
| 1262 | as_bad ("%s `%s'", insn_error, str); |
| 1263 | return; |
| 1264 | } |
| 1265 | |
| 1266 | if (insn.insn_mo->pinfo == INSN_MACRO) |
| 1267 | { |
| 1268 | if (mips_opts.mips16) |
| 1269 | mips16_macro (&insn); |
| 1270 | else |
| 1271 | macro (&insn); |
| 1272 | } |
| 1273 | else |
| 1274 | { |
| 1275 | if (imm_expr.X_op != O_absent) |
| 1276 | append_insn (NULL, &insn, &imm_expr, imm_reloc, imm_unmatched_hi); |
| 1277 | else if (offset_expr.X_op != O_absent) |
| 1278 | append_insn (NULL, &insn, &offset_expr, offset_reloc, false); |
| 1279 | else |
| 1280 | append_insn (NULL, &insn, NULL, unused_reloc, false); |
| 1281 | } |
| 1282 | } |
| 1283 | |
| 1284 | /* See whether instruction IP reads register REG. CLASS is the type |
| 1285 | of register. */ |
| 1286 | |
| 1287 | static int |
| 1288 | insn_uses_reg (ip, reg, class) |
| 1289 | struct mips_cl_insn *ip; |
| 1290 | unsigned int reg; |
| 1291 | enum mips_regclass class; |
| 1292 | { |
| 1293 | if (class == MIPS16_REG) |
| 1294 | { |
| 1295 | assert (mips_opts.mips16); |
| 1296 | reg = mips16_to_32_reg_map[reg]; |
| 1297 | class = MIPS_GR_REG; |
| 1298 | } |
| 1299 | |
| 1300 | /* Don't report on general register ZERO, since it never changes. */ |
| 1301 | if (class == MIPS_GR_REG && reg == ZERO) |
| 1302 | return 0; |
| 1303 | |
| 1304 | if (class == MIPS_FP_REG) |
| 1305 | { |
| 1306 | assert (! mips_opts.mips16); |
| 1307 | /* If we are called with either $f0 or $f1, we must check $f0. |
| 1308 | This is not optimal, because it will introduce an unnecessary |
| 1309 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would |
| 1310 | need to distinguish reading both $f0 and $f1 or just one of |
| 1311 | them. Note that we don't have to check the other way, |
| 1312 | because there is no instruction that sets both $f0 and $f1 |
| 1313 | and requires a delay. */ |
| 1314 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) |
| 1315 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) |
| 1316 | == (reg &~ (unsigned) 1))) |
| 1317 | return 1; |
| 1318 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) |
| 1319 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) |
| 1320 | == (reg &~ (unsigned) 1))) |
| 1321 | return 1; |
| 1322 | } |
| 1323 | else if (! mips_opts.mips16) |
| 1324 | { |
| 1325 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) |
| 1326 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) |
| 1327 | return 1; |
| 1328 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) |
| 1329 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) |
| 1330 | return 1; |
| 1331 | } |
| 1332 | else |
| 1333 | { |
| 1334 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) |
| 1335 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) |
| 1336 | & MIPS16OP_MASK_RX)] |
| 1337 | == reg)) |
| 1338 | return 1; |
| 1339 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) |
| 1340 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) |
| 1341 | & MIPS16OP_MASK_RY)] |
| 1342 | == reg)) |
| 1343 | return 1; |
| 1344 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) |
| 1345 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) |
| 1346 | & MIPS16OP_MASK_MOVE32Z)] |
| 1347 | == reg)) |
| 1348 | return 1; |
| 1349 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) |
| 1350 | return 1; |
| 1351 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) |
| 1352 | return 1; |
| 1353 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) |
| 1354 | return 1; |
| 1355 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) |
| 1356 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) |
| 1357 | & MIPS16OP_MASK_REGR32) == reg) |
| 1358 | return 1; |
| 1359 | } |
| 1360 | |
| 1361 | return 0; |
| 1362 | } |
| 1363 | |
| 1364 | /* This function returns true if modifying a register requires a |
| 1365 | delay. */ |
| 1366 | |
| 1367 | static int |
| 1368 | reg_needs_delay (reg) |
| 1369 | unsigned int reg; |
| 1370 | { |
| 1371 | unsigned long prev_pinfo; |
| 1372 | |
| 1373 | prev_pinfo = prev_insn.insn_mo->pinfo; |
| 1374 | if (! mips_opts.noreorder |
| 1375 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
| 1376 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
| 1377 | || (! gpr_interlocks |
| 1378 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) |
| 1379 | { |
| 1380 | /* A load from a coprocessor or from memory. All load |
| 1381 | delays delay the use of general register rt for one |
| 1382 | instruction on the r3000. The r6000 and r4000 use |
| 1383 | interlocks. */ |
| 1384 | /* Itbl support may require additional care here. */ |
| 1385 | know (prev_pinfo & INSN_WRITE_GPR_T); |
| 1386 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) |
| 1387 | return 1; |
| 1388 | } |
| 1389 | |
| 1390 | return 0; |
| 1391 | } |
| 1392 | |
| 1393 | /* Mark instruction labels in mips16 mode. This permits the linker to |
| 1394 | handle them specially, such as generating jalx instructions when |
| 1395 | needed. We also make them odd for the duration of the assembly, in |
| 1396 | order to generate the right sort of code. We will make them even |
| 1397 | in the adjust_symtab routine, while leaving them marked. This is |
| 1398 | convenient for the debugger and the disassembler. The linker knows |
| 1399 | to make them odd again. */ |
| 1400 | |
| 1401 | static void |
| 1402 | mips16_mark_labels () |
| 1403 | { |
| 1404 | if (mips_opts.mips16) |
| 1405 | { |
| 1406 | struct insn_label_list *l; |
| 1407 | valueT val; |
| 1408 | |
| 1409 | for (l = insn_labels; l != NULL; l = l->next) |
| 1410 | { |
| 1411 | #ifdef OBJ_ELF |
| 1412 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
| 1413 | S_SET_OTHER (l->label, STO_MIPS16); |
| 1414 | #endif |
| 1415 | val = S_GET_VALUE (l->label); |
| 1416 | if ((val & 1) == 0) |
| 1417 | S_SET_VALUE (l->label, val + 1); |
| 1418 | } |
| 1419 | } |
| 1420 | } |
| 1421 | |
| 1422 | /* Output an instruction. PLACE is where to put the instruction; if |
| 1423 | it is NULL, this uses frag_more to get room. IP is the instruction |
| 1424 | information. ADDRESS_EXPR is an operand of the instruction to be |
| 1425 | used with RELOC_TYPE. */ |
| 1426 | |
| 1427 | static void |
| 1428 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) |
| 1429 | char *place; |
| 1430 | struct mips_cl_insn *ip; |
| 1431 | expressionS *address_expr; |
| 1432 | bfd_reloc_code_real_type *reloc_type; |
| 1433 | boolean unmatched_hi; |
| 1434 | { |
| 1435 | register unsigned long prev_pinfo, pinfo; |
| 1436 | char *f; |
| 1437 | fixS *fixp[3]; |
| 1438 | int nops = 0; |
| 1439 | |
| 1440 | /* Mark instruction labels in mips16 mode. */ |
| 1441 | mips16_mark_labels (); |
| 1442 | |
| 1443 | prev_pinfo = prev_insn.insn_mo->pinfo; |
| 1444 | pinfo = ip->insn_mo->pinfo; |
| 1445 | |
| 1446 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) |
| 1447 | { |
| 1448 | int prev_prev_nop; |
| 1449 | |
| 1450 | /* If the previous insn required any delay slots, see if we need |
| 1451 | to insert a NOP or two. There are eight kinds of possible |
| 1452 | hazards, of which an instruction can have at most one type. |
| 1453 | (1) a load from memory delay |
| 1454 | (2) a load from a coprocessor delay |
| 1455 | (3) an unconditional branch delay |
| 1456 | (4) a conditional branch delay |
| 1457 | (5) a move to coprocessor register delay |
| 1458 | (6) a load coprocessor register from memory delay |
| 1459 | (7) a coprocessor condition code delay |
| 1460 | (8) a HI/LO special register delay |
| 1461 | |
| 1462 | There are a lot of optimizations we could do that we don't. |
| 1463 | In particular, we do not, in general, reorder instructions. |
| 1464 | If you use gcc with optimization, it will reorder |
| 1465 | instructions and generally do much more optimization then we |
| 1466 | do here; repeating all that work in the assembler would only |
| 1467 | benefit hand written assembly code, and does not seem worth |
| 1468 | it. */ |
| 1469 | |
| 1470 | /* This is how a NOP is emitted. */ |
| 1471 | #define emit_nop() \ |
| 1472 | (mips_opts.mips16 \ |
| 1473 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ |
| 1474 | : md_number_to_chars (frag_more (4), 0, 4)) |
| 1475 | |
| 1476 | /* The previous insn might require a delay slot, depending upon |
| 1477 | the contents of the current insn. */ |
| 1478 | if (! mips_opts.mips16 |
| 1479 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
| 1480 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
| 1481 | && ! cop_interlocks) |
| 1482 | || (! gpr_interlocks |
| 1483 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) |
| 1484 | { |
| 1485 | /* A load from a coprocessor or from memory. All load |
| 1486 | delays delay the use of general register rt for one |
| 1487 | instruction on the r3000. The r6000 and r4000 use |
| 1488 | interlocks. */ |
| 1489 | /* Itbl support may require additional care here. */ |
| 1490 | know (prev_pinfo & INSN_WRITE_GPR_T); |
| 1491 | if (mips_optimize == 0 |
| 1492 | || insn_uses_reg (ip, |
| 1493 | ((prev_insn.insn_opcode >> OP_SH_RT) |
| 1494 | & OP_MASK_RT), |
| 1495 | MIPS_GR_REG)) |
| 1496 | ++nops; |
| 1497 | } |
| 1498 | else if (! mips_opts.mips16 |
| 1499 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
| 1500 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
| 1501 | && ! cop_interlocks) |
| 1502 | || (mips_opts.isa == ISA_MIPS1 |
| 1503 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
| 1504 | { |
| 1505 | /* A generic coprocessor delay. The previous instruction |
| 1506 | modified a coprocessor general or control register. If |
| 1507 | it modified a control register, we need to avoid any |
| 1508 | coprocessor instruction (this is probably not always |
| 1509 | required, but it sometimes is). If it modified a general |
| 1510 | register, we avoid using that register. |
| 1511 | |
| 1512 | On the r6000 and r4000 loading a coprocessor register |
| 1513 | from memory is interlocked, and does not require a delay. |
| 1514 | |
| 1515 | This case is not handled very well. There is no special |
| 1516 | knowledge of CP0 handling, and the coprocessors other |
| 1517 | than the floating point unit are not distinguished at |
| 1518 | all. */ |
| 1519 | /* Itbl support may require additional care here. FIXME! |
| 1520 | Need to modify this to include knowledge about |
| 1521 | user specified delays! */ |
| 1522 | if (prev_pinfo & INSN_WRITE_FPR_T) |
| 1523 | { |
| 1524 | if (mips_optimize == 0 |
| 1525 | || insn_uses_reg (ip, |
| 1526 | ((prev_insn.insn_opcode >> OP_SH_FT) |
| 1527 | & OP_MASK_FT), |
| 1528 | MIPS_FP_REG)) |
| 1529 | ++nops; |
| 1530 | } |
| 1531 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
| 1532 | { |
| 1533 | if (mips_optimize == 0 |
| 1534 | || insn_uses_reg (ip, |
| 1535 | ((prev_insn.insn_opcode >> OP_SH_FS) |
| 1536 | & OP_MASK_FS), |
| 1537 | MIPS_FP_REG)) |
| 1538 | ++nops; |
| 1539 | } |
| 1540 | else |
| 1541 | { |
| 1542 | /* We don't know exactly what the previous instruction |
| 1543 | does. If the current instruction uses a coprocessor |
| 1544 | register, we must insert a NOP. If previous |
| 1545 | instruction may set the condition codes, and the |
| 1546 | current instruction uses them, we must insert two |
| 1547 | NOPS. */ |
| 1548 | /* Itbl support may require additional care here. */ |
| 1549 | if (mips_optimize == 0 |
| 1550 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
| 1551 | && (pinfo & INSN_READ_COND_CODE))) |
| 1552 | nops += 2; |
| 1553 | else if (pinfo & INSN_COP) |
| 1554 | ++nops; |
| 1555 | } |
| 1556 | } |
| 1557 | else if (! mips_opts.mips16 |
| 1558 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
| 1559 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
| 1560 | && ! cop_interlocks) |
| 1561 | { |
| 1562 | /* The previous instruction sets the coprocessor condition |
| 1563 | codes, but does not require a general coprocessor delay |
| 1564 | (this means it is a floating point comparison |
| 1565 | instruction). If this instruction uses the condition |
| 1566 | codes, we need to insert a single NOP. */ |
| 1567 | /* Itbl support may require additional care here. */ |
| 1568 | if (mips_optimize == 0 |
| 1569 | || (pinfo & INSN_READ_COND_CODE)) |
| 1570 | ++nops; |
| 1571 | } |
| 1572 | |
| 1573 | /* If we're fixing up mfhi/mflo for the r7000 and the |
| 1574 | previous insn was an mfhi/mflo and the current insn |
| 1575 | reads the register that the mfhi/mflo wrote to, then |
| 1576 | insert two nops. */ |
| 1577 | |
| 1578 | else if (mips_7000_hilo_fix |
| 1579 | && MF_HILO_INSN (prev_pinfo) |
| 1580 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) |
| 1581 | & OP_MASK_RD), |
| 1582 | MIPS_GR_REG)) |
| 1583 | { |
| 1584 | nops += 2; |
| 1585 | } |
| 1586 | |
| 1587 | /* If we're fixing up mfhi/mflo for the r7000 and the |
| 1588 | 2nd previous insn was an mfhi/mflo and the current insn |
| 1589 | reads the register that the mfhi/mflo wrote to, then |
| 1590 | insert one nop. */ |
| 1591 | |
| 1592 | else if (mips_7000_hilo_fix |
| 1593 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) |
| 1594 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) |
| 1595 | & OP_MASK_RD), |
| 1596 | MIPS_GR_REG)) |
| 1597 | |
| 1598 | { |
| 1599 | ++nops; |
| 1600 | } |
| 1601 | |
| 1602 | else if (prev_pinfo & INSN_READ_LO) |
| 1603 | { |
| 1604 | /* The previous instruction reads the LO register; if the |
| 1605 | current instruction writes to the LO register, we must |
| 1606 | insert two NOPS. Some newer processors have interlocks. |
| 1607 | Also the tx39's multiply instructions can be exectuted |
| 1608 | immediatly after a read from HI/LO (without the delay), |
| 1609 | though the tx39's divide insns still do require the |
| 1610 | delay. */ |
| 1611 | if (! (hilo_interlocks |
| 1612 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
| 1613 | && (mips_optimize == 0 |
| 1614 | || (pinfo & INSN_WRITE_LO))) |
| 1615 | nops += 2; |
| 1616 | /* Most mips16 branch insns don't have a delay slot. |
| 1617 | If a read from LO is immediately followed by a branch |
| 1618 | to a write to LO we have a read followed by a write |
| 1619 | less than 2 insns away. We assume the target of |
| 1620 | a branch might be a write to LO, and insert a nop |
| 1621 | between a read and an immediately following branch. */ |
| 1622 | else if (mips_opts.mips16 |
| 1623 | && (mips_optimize == 0 |
| 1624 | || (pinfo & MIPS16_INSN_BRANCH))) |
| 1625 | ++nops; |
| 1626 | } |
| 1627 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) |
| 1628 | { |
| 1629 | /* The previous instruction reads the HI register; if the |
| 1630 | current instruction writes to the HI register, we must |
| 1631 | insert a NOP. Some newer processors have interlocks. |
| 1632 | Also the note tx39's multiply above. */ |
| 1633 | if (! (hilo_interlocks |
| 1634 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
| 1635 | && (mips_optimize == 0 |
| 1636 | || (pinfo & INSN_WRITE_HI))) |
| 1637 | nops += 2; |
| 1638 | /* Most mips16 branch insns don't have a delay slot. |
| 1639 | If a read from HI is immediately followed by a branch |
| 1640 | to a write to HI we have a read followed by a write |
| 1641 | less than 2 insns away. We assume the target of |
| 1642 | a branch might be a write to HI, and insert a nop |
| 1643 | between a read and an immediately following branch. */ |
| 1644 | else if (mips_opts.mips16 |
| 1645 | && (mips_optimize == 0 |
| 1646 | || (pinfo & MIPS16_INSN_BRANCH))) |
| 1647 | ++nops; |
| 1648 | } |
| 1649 | |
| 1650 | /* If the previous instruction was in a noreorder section, then |
| 1651 | we don't want to insert the nop after all. */ |
| 1652 | /* Itbl support may require additional care here. */ |
| 1653 | if (prev_insn_unreordered) |
| 1654 | nops = 0; |
| 1655 | |
| 1656 | /* There are two cases which require two intervening |
| 1657 | instructions: 1) setting the condition codes using a move to |
| 1658 | coprocessor instruction which requires a general coprocessor |
| 1659 | delay and then reading the condition codes 2) reading the HI |
| 1660 | or LO register and then writing to it (except on processors |
| 1661 | which have interlocks). If we are not already emitting a NOP |
| 1662 | instruction, we must check for these cases compared to the |
| 1663 | instruction previous to the previous instruction. */ |
| 1664 | if ((! mips_opts.mips16 |
| 1665 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
| 1666 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
| 1667 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
| 1668 | && (pinfo & INSN_READ_COND_CODE) |
| 1669 | && ! cop_interlocks) |
| 1670 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) |
| 1671 | && (pinfo & INSN_WRITE_LO) |
| 1672 | && ! (hilo_interlocks |
| 1673 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))) |
| 1674 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
| 1675 | && (pinfo & INSN_WRITE_HI) |
| 1676 | && ! (hilo_interlocks |
| 1677 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))) |
| 1678 | prev_prev_nop = 1; |
| 1679 | else |
| 1680 | prev_prev_nop = 0; |
| 1681 | |
| 1682 | if (prev_prev_insn_unreordered) |
| 1683 | prev_prev_nop = 0; |
| 1684 | |
| 1685 | if (prev_prev_nop && nops == 0) |
| 1686 | ++nops; |
| 1687 | |
| 1688 | /* If we are being given a nop instruction, don't bother with |
| 1689 | one of the nops we would otherwise output. This will only |
| 1690 | happen when a nop instruction is used with mips_optimize set |
| 1691 | to 0. */ |
| 1692 | if (nops > 0 |
| 1693 | && ! mips_opts.noreorder |
| 1694 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
| 1695 | --nops; |
| 1696 | |
| 1697 | /* Now emit the right number of NOP instructions. */ |
| 1698 | if (nops > 0 && ! mips_opts.noreorder) |
| 1699 | { |
| 1700 | fragS *old_frag; |
| 1701 | unsigned long old_frag_offset; |
| 1702 | int i; |
| 1703 | struct insn_label_list *l; |
| 1704 | |
| 1705 | old_frag = frag_now; |
| 1706 | old_frag_offset = frag_now_fix (); |
| 1707 | |
| 1708 | for (i = 0; i < nops; i++) |
| 1709 | emit_nop (); |
| 1710 | |
| 1711 | if (listing) |
| 1712 | { |
| 1713 | listing_prev_line (); |
| 1714 | /* We may be at the start of a variant frag. In case we |
| 1715 | are, make sure there is enough space for the frag |
| 1716 | after the frags created by listing_prev_line. The |
| 1717 | argument to frag_grow here must be at least as large |
| 1718 | as the argument to all other calls to frag_grow in |
| 1719 | this file. We don't have to worry about being in the |
| 1720 | middle of a variant frag, because the variants insert |
| 1721 | all needed nop instructions themselves. */ |
| 1722 | frag_grow (40); |
| 1723 | } |
| 1724 | |
| 1725 | for (l = insn_labels; l != NULL; l = l->next) |
| 1726 | { |
| 1727 | valueT val; |
| 1728 | |
| 1729 | assert (S_GET_SEGMENT (l->label) == now_seg); |
| 1730 | symbol_set_frag (l->label, frag_now); |
| 1731 | val = (valueT) frag_now_fix (); |
| 1732 | /* mips16 text labels are stored as odd. */ |
| 1733 | if (mips_opts.mips16) |
| 1734 | ++val; |
| 1735 | S_SET_VALUE (l->label, val); |
| 1736 | } |
| 1737 | |
| 1738 | #ifndef NO_ECOFF_DEBUGGING |
| 1739 | if (ECOFF_DEBUGGING) |
| 1740 | ecoff_fix_loc (old_frag, old_frag_offset); |
| 1741 | #endif |
| 1742 | } |
| 1743 | else if (prev_nop_frag != NULL) |
| 1744 | { |
| 1745 | /* We have a frag holding nops we may be able to remove. If |
| 1746 | we don't need any nops, we can decrease the size of |
| 1747 | prev_nop_frag by the size of one instruction. If we do |
| 1748 | need some nops, we count them in prev_nops_required. */ |
| 1749 | if (prev_nop_frag_since == 0) |
| 1750 | { |
| 1751 | if (nops == 0) |
| 1752 | { |
| 1753 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; |
| 1754 | --prev_nop_frag_holds; |
| 1755 | } |
| 1756 | else |
| 1757 | prev_nop_frag_required += nops; |
| 1758 | } |
| 1759 | else |
| 1760 | { |
| 1761 | if (prev_prev_nop == 0) |
| 1762 | { |
| 1763 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; |
| 1764 | --prev_nop_frag_holds; |
| 1765 | } |
| 1766 | else |
| 1767 | ++prev_nop_frag_required; |
| 1768 | } |
| 1769 | |
| 1770 | if (prev_nop_frag_holds <= prev_nop_frag_required) |
| 1771 | prev_nop_frag = NULL; |
| 1772 | |
| 1773 | ++prev_nop_frag_since; |
| 1774 | |
| 1775 | /* Sanity check: by the time we reach the second instruction |
| 1776 | after prev_nop_frag, we should have used up all the nops |
| 1777 | one way or another. */ |
| 1778 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); |
| 1779 | } |
| 1780 | } |
| 1781 | |
| 1782 | if (*reloc_type > BFD_RELOC_UNUSED) |
| 1783 | { |
| 1784 | /* We need to set up a variant frag. */ |
| 1785 | assert (mips_opts.mips16 && address_expr != NULL); |
| 1786 | f = frag_var (rs_machine_dependent, 4, 0, |
| 1787 | RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED, |
| 1788 | mips16_small, mips16_ext, |
| 1789 | (prev_pinfo |
| 1790 | & INSN_UNCOND_BRANCH_DELAY), |
| 1791 | (*prev_insn_reloc_type |
| 1792 | == BFD_RELOC_MIPS16_JMP)), |
| 1793 | make_expr_symbol (address_expr), 0, NULL); |
| 1794 | } |
| 1795 | else if (place != NULL) |
| 1796 | f = place; |
| 1797 | else if (mips_opts.mips16 |
| 1798 | && ! ip->use_extend |
| 1799 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
| 1800 | { |
| 1801 | /* Make sure there is enough room to swap this instruction with |
| 1802 | a following jump instruction. */ |
| 1803 | frag_grow (6); |
| 1804 | f = frag_more (2); |
| 1805 | } |
| 1806 | else |
| 1807 | { |
| 1808 | if (mips_opts.mips16 |
| 1809 | && mips_opts.noreorder |
| 1810 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) |
| 1811 | as_warn (_("extended instruction in delay slot")); |
| 1812 | |
| 1813 | f = frag_more (4); |
| 1814 | } |
| 1815 | |
| 1816 | fixp[0] = fixp[1] = fixp[2] = NULL; |
| 1817 | if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED) |
| 1818 | { |
| 1819 | if (address_expr->X_op == O_constant) |
| 1820 | { |
| 1821 | valueT tmp; |
| 1822 | |
| 1823 | switch (*reloc_type) |
| 1824 | { |
| 1825 | case BFD_RELOC_32: |
| 1826 | ip->insn_opcode |= address_expr->X_add_number; |
| 1827 | break; |
| 1828 | |
| 1829 | case BFD_RELOC_MIPS_HIGHEST: |
| 1830 | tmp = (address_expr->X_add_number + 0x800080008000) >> 16; |
| 1831 | tmp >>= 16; |
| 1832 | ip->insn_opcode |= (tmp >> 16) & 0xffff; |
| 1833 | break; |
| 1834 | |
| 1835 | case BFD_RELOC_MIPS_HIGHER: |
| 1836 | tmp = (address_expr->X_add_number + 0x80008000) >> 16; |
| 1837 | ip->insn_opcode |= (tmp >> 16) & 0xffff; |
| 1838 | break; |
| 1839 | |
| 1840 | case BFD_RELOC_HI16_S: |
| 1841 | ip->insn_opcode |= ((address_expr->X_add_number + 0x8000) |
| 1842 | >> 16) & 0xffff; |
| 1843 | break; |
| 1844 | |
| 1845 | case BFD_RELOC_HI16: |
| 1846 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; |
| 1847 | break; |
| 1848 | |
| 1849 | case BFD_RELOC_LO16: |
| 1850 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
| 1851 | break; |
| 1852 | |
| 1853 | case BFD_RELOC_MIPS_JMP: |
| 1854 | if ((address_expr->X_add_number & 3) != 0) |
| 1855 | as_bad (_("jump to misaligned address (0x%lx)"), |
| 1856 | (unsigned long) address_expr->X_add_number); |
| 1857 | if (address_expr->X_add_number & ~0xfffffff |
| 1858 | || address_expr->X_add_number > 0x7fffffc) |
| 1859 | as_bad (_("jump address range overflow (0x%lx)"), |
| 1860 | (unsigned long) address_expr->X_add_number); |
| 1861 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
| 1862 | break; |
| 1863 | |
| 1864 | case BFD_RELOC_MIPS16_JMP: |
| 1865 | if ((address_expr->X_add_number & 3) != 0) |
| 1866 | as_bad (_("jump to misaligned address (0x%lx)"), |
| 1867 | (unsigned long) address_expr->X_add_number); |
| 1868 | if (address_expr->X_add_number & ~0xfffffff |
| 1869 | || address_expr->X_add_number > 0x7fffffc) |
| 1870 | as_bad (_("jump address range overflow (0x%lx)"), |
| 1871 | (unsigned long) address_expr->X_add_number); |
| 1872 | ip->insn_opcode |= |
| 1873 | (((address_expr->X_add_number & 0x7c0000) << 3) |
| 1874 | | ((address_expr->X_add_number & 0xf800000) >> 7) |
| 1875 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); |
| 1876 | break; |
| 1877 | |
| 1878 | case BFD_RELOC_16_PCREL: |
| 1879 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
| 1880 | break; |
| 1881 | |
| 1882 | case BFD_RELOC_16_PCREL_S2: |
| 1883 | goto need_reloc; |
| 1884 | |
| 1885 | default: |
| 1886 | internalError (); |
| 1887 | } |
| 1888 | } |
| 1889 | else |
| 1890 | { |
| 1891 | need_reloc: |
| 1892 | /* Don't generate a reloc if we are writing into a variant frag. */ |
| 1893 | if (place == NULL) |
| 1894 | { |
| 1895 | fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, |
| 1896 | address_expr, |
| 1897 | (*reloc_type == BFD_RELOC_16_PCREL |
| 1898 | || *reloc_type == BFD_RELOC_16_PCREL_S2), |
| 1899 | reloc_type[0]); |
| 1900 | |
| 1901 | /* These relocations can have an addend that won't fit in |
| 1902 | 4 octets for 64bit assembly. */ |
| 1903 | if (HAVE_64BIT_GPRS && |
| 1904 | (*reloc_type == BFD_RELOC_16 |
| 1905 | || *reloc_type == BFD_RELOC_32 |
| 1906 | || *reloc_type == BFD_RELOC_MIPS_JMP |
| 1907 | || *reloc_type == BFD_RELOC_HI16_S |
| 1908 | || *reloc_type == BFD_RELOC_LO16 |
| 1909 | || *reloc_type == BFD_RELOC_GPREL16 |
| 1910 | || *reloc_type == BFD_RELOC_MIPS_LITERAL |
| 1911 | || *reloc_type == BFD_RELOC_GPREL32 |
| 1912 | || *reloc_type == BFD_RELOC_64 |
| 1913 | || *reloc_type == BFD_RELOC_CTOR |
| 1914 | || *reloc_type == BFD_RELOC_MIPS_SUB |
| 1915 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST |
| 1916 | || *reloc_type == BFD_RELOC_MIPS_HIGHER |
| 1917 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP |
| 1918 | || *reloc_type == BFD_RELOC_MIPS_REL16 |
| 1919 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) |
| 1920 | fixp[0]->fx_no_overflow = 1; |
| 1921 | |
| 1922 | if (unmatched_hi) |
| 1923 | { |
| 1924 | struct mips_hi_fixup *hi_fixup; |
| 1925 | |
| 1926 | assert (*reloc_type == BFD_RELOC_HI16_S); |
| 1927 | hi_fixup = ((struct mips_hi_fixup *) |
| 1928 | xmalloc (sizeof (struct mips_hi_fixup))); |
| 1929 | hi_fixup->fixp = fixp[0]; |
| 1930 | hi_fixup->seg = now_seg; |
| 1931 | hi_fixup->next = mips_hi_fixup_list; |
| 1932 | mips_hi_fixup_list = hi_fixup; |
| 1933 | } |
| 1934 | |
| 1935 | if (reloc_type[1] != BFD_RELOC_UNUSED) |
| 1936 | { |
| 1937 | /* FIXME: This symbol can be one of |
| 1938 | RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */ |
| 1939 | address_expr->X_op = O_absent; |
| 1940 | address_expr->X_add_symbol = 0; |
| 1941 | address_expr->X_add_number = 0; |
| 1942 | |
| 1943 | fixp[1] = fix_new_exp (frag_now, f - frag_now->fr_literal, |
| 1944 | 4, address_expr, false, |
| 1945 | reloc_type[1]); |
| 1946 | |
| 1947 | /* These relocations can have an addend that won't fit in |
| 1948 | 4 octets for 64bit assembly. */ |
| 1949 | if (HAVE_64BIT_GPRS && |
| 1950 | (*reloc_type == BFD_RELOC_16 |
| 1951 | || *reloc_type == BFD_RELOC_32 |
| 1952 | || *reloc_type == BFD_RELOC_MIPS_JMP |
| 1953 | || *reloc_type == BFD_RELOC_HI16_S |
| 1954 | || *reloc_type == BFD_RELOC_LO16 |
| 1955 | || *reloc_type == BFD_RELOC_GPREL16 |
| 1956 | || *reloc_type == BFD_RELOC_MIPS_LITERAL |
| 1957 | || *reloc_type == BFD_RELOC_GPREL32 |
| 1958 | || *reloc_type == BFD_RELOC_64 |
| 1959 | || *reloc_type == BFD_RELOC_CTOR |
| 1960 | || *reloc_type == BFD_RELOC_MIPS_SUB |
| 1961 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST |
| 1962 | || *reloc_type == BFD_RELOC_MIPS_HIGHER |
| 1963 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP |
| 1964 | || *reloc_type == BFD_RELOC_MIPS_REL16 |
| 1965 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) |
| 1966 | fixp[1]->fx_no_overflow = 1; |
| 1967 | |
| 1968 | if (reloc_type[2] != BFD_RELOC_UNUSED) |
| 1969 | { |
| 1970 | address_expr->X_op = O_absent; |
| 1971 | address_expr->X_add_symbol = 0; |
| 1972 | address_expr->X_add_number = 0; |
| 1973 | |
| 1974 | fixp[2] = fix_new_exp (frag_now, |
| 1975 | f - frag_now->fr_literal, 4, |
| 1976 | address_expr, false, |
| 1977 | reloc_type[2]); |
| 1978 | |
| 1979 | /* These relocations can have an addend that won't fit in |
| 1980 | 4 octets for 64bit assembly. */ |
| 1981 | if (HAVE_64BIT_GPRS && |
| 1982 | (*reloc_type == BFD_RELOC_16 |
| 1983 | || *reloc_type == BFD_RELOC_32 |
| 1984 | || *reloc_type == BFD_RELOC_MIPS_JMP |
| 1985 | || *reloc_type == BFD_RELOC_HI16_S |
| 1986 | || *reloc_type == BFD_RELOC_LO16 |
| 1987 | || *reloc_type == BFD_RELOC_GPREL16 |
| 1988 | || *reloc_type == BFD_RELOC_MIPS_LITERAL |
| 1989 | || *reloc_type == BFD_RELOC_GPREL32 |
| 1990 | || *reloc_type == BFD_RELOC_64 |
| 1991 | || *reloc_type == BFD_RELOC_CTOR |
| 1992 | || *reloc_type == BFD_RELOC_MIPS_SUB |
| 1993 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST |
| 1994 | || *reloc_type == BFD_RELOC_MIPS_HIGHER |
| 1995 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP |
| 1996 | || *reloc_type == BFD_RELOC_MIPS_REL16 |
| 1997 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) |
| 1998 | fixp[2]->fx_no_overflow = 1; |
| 1999 | } |
| 2000 | } |
| 2001 | } |
| 2002 | } |
| 2003 | } |
| 2004 | |
| 2005 | if (! mips_opts.mips16) |
| 2006 | { |
| 2007 | md_number_to_chars (f, ip->insn_opcode, 4); |
| 2008 | #ifdef OBJ_ELF |
| 2009 | dwarf2_emit_insn (4); |
| 2010 | #endif |
| 2011 | } |
| 2012 | else if (*reloc_type == BFD_RELOC_MIPS16_JMP) |
| 2013 | { |
| 2014 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); |
| 2015 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); |
| 2016 | #ifdef OBJ_ELF |
| 2017 | dwarf2_emit_insn (4); |
| 2018 | #endif |
| 2019 | } |
| 2020 | else |
| 2021 | { |
| 2022 | if (ip->use_extend) |
| 2023 | { |
| 2024 | md_number_to_chars (f, 0xf000 | ip->extend, 2); |
| 2025 | f += 2; |
| 2026 | } |
| 2027 | md_number_to_chars (f, ip->insn_opcode, 2); |
| 2028 | #ifdef OBJ_ELF |
| 2029 | dwarf2_emit_insn (ip->use_extend ? 4 : 2); |
| 2030 | #endif |
| 2031 | } |
| 2032 | |
| 2033 | /* Update the register mask information. */ |
| 2034 | if (! mips_opts.mips16) |
| 2035 | { |
| 2036 | if (pinfo & INSN_WRITE_GPR_D) |
| 2037 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); |
| 2038 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) |
| 2039 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); |
| 2040 | if (pinfo & INSN_READ_GPR_S) |
| 2041 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); |
| 2042 | if (pinfo & INSN_WRITE_GPR_31) |
| 2043 | mips_gprmask |= 1 << RA; |
| 2044 | if (pinfo & INSN_WRITE_FPR_D) |
| 2045 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); |
| 2046 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) |
| 2047 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); |
| 2048 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) |
| 2049 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); |
| 2050 | if ((pinfo & INSN_READ_FPR_R) != 0) |
| 2051 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); |
| 2052 | if (pinfo & INSN_COP) |
| 2053 | { |
| 2054 | /* We don't keep enough information to sort these cases out. |
| 2055 | The itbl support does keep this information however, although |
| 2056 | we currently don't support itbl fprmats as part of the cop |
| 2057 | instruction. May want to add this support in the future. */ |
| 2058 | } |
| 2059 | /* Never set the bit for $0, which is always zero. */ |
| 2060 | mips_gprmask &= ~1 << 0; |
| 2061 | } |
| 2062 | else |
| 2063 | { |
| 2064 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) |
| 2065 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) |
| 2066 | & MIPS16OP_MASK_RX); |
| 2067 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) |
| 2068 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) |
| 2069 | & MIPS16OP_MASK_RY); |
| 2070 | if (pinfo & MIPS16_INSN_WRITE_Z) |
| 2071 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) |
| 2072 | & MIPS16OP_MASK_RZ); |
| 2073 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) |
| 2074 | mips_gprmask |= 1 << TREG; |
| 2075 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) |
| 2076 | mips_gprmask |= 1 << SP; |
| 2077 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) |
| 2078 | mips_gprmask |= 1 << RA; |
| 2079 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) |
| 2080 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); |
| 2081 | if (pinfo & MIPS16_INSN_READ_Z) |
| 2082 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) |
| 2083 | & MIPS16OP_MASK_MOVE32Z); |
| 2084 | if (pinfo & MIPS16_INSN_READ_GPR_X) |
| 2085 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) |
| 2086 | & MIPS16OP_MASK_REGR32); |
| 2087 | } |
| 2088 | |
| 2089 | if (place == NULL && ! mips_opts.noreorder) |
| 2090 | { |
| 2091 | /* Filling the branch delay slot is more complex. We try to |
| 2092 | switch the branch with the previous instruction, which we can |
| 2093 | do if the previous instruction does not set up a condition |
| 2094 | that the branch tests and if the branch is not itself the |
| 2095 | target of any branch. */ |
| 2096 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
| 2097 | || (pinfo & INSN_COND_BRANCH_DELAY)) |
| 2098 | { |
| 2099 | if (mips_optimize < 2 |
| 2100 | /* If we have seen .set volatile or .set nomove, don't |
| 2101 | optimize. */ |
| 2102 | || mips_opts.nomove != 0 |
| 2103 | /* If we had to emit any NOP instructions, then we |
| 2104 | already know we can not swap. */ |
| 2105 | || nops != 0 |
| 2106 | /* If we don't even know the previous insn, we can not |
| 2107 | swap. */ |
| 2108 | || ! prev_insn_valid |
| 2109 | /* If the previous insn is already in a branch delay |
| 2110 | slot, then we can not swap. */ |
| 2111 | || prev_insn_is_delay_slot |
| 2112 | /* If the previous previous insn was in a .set |
| 2113 | noreorder, we can't swap. Actually, the MIPS |
| 2114 | assembler will swap in this situation. However, gcc |
| 2115 | configured -with-gnu-as will generate code like |
| 2116 | .set noreorder |
| 2117 | lw $4,XXX |
| 2118 | .set reorder |
| 2119 | INSN |
| 2120 | bne $4,$0,foo |
| 2121 | in which we can not swap the bne and INSN. If gcc is |
| 2122 | not configured -with-gnu-as, it does not output the |
| 2123 | .set pseudo-ops. We don't have to check |
| 2124 | prev_insn_unreordered, because prev_insn_valid will |
| 2125 | be 0 in that case. We don't want to use |
| 2126 | prev_prev_insn_valid, because we do want to be able |
| 2127 | to swap at the start of a function. */ |
| 2128 | || prev_prev_insn_unreordered |
| 2129 | /* If the branch is itself the target of a branch, we |
| 2130 | can not swap. We cheat on this; all we check for is |
| 2131 | whether there is a label on this instruction. If |
| 2132 | there are any branches to anything other than a |
| 2133 | label, users must use .set noreorder. */ |
| 2134 | || insn_labels != NULL |
| 2135 | /* If the previous instruction is in a variant frag, we |
| 2136 | can not do the swap. This does not apply to the |
| 2137 | mips16, which uses variant frags for different |
| 2138 | purposes. */ |
| 2139 | || (! mips_opts.mips16 |
| 2140 | && prev_insn_frag->fr_type == rs_machine_dependent) |
| 2141 | /* If the branch reads the condition codes, we don't |
| 2142 | even try to swap, because in the sequence |
| 2143 | ctc1 $X,$31 |
| 2144 | INSN |
| 2145 | INSN |
| 2146 | bc1t LABEL |
| 2147 | we can not swap, and I don't feel like handling that |
| 2148 | case. */ |
| 2149 | || (! mips_opts.mips16 |
| 2150 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
| 2151 | && (pinfo & INSN_READ_COND_CODE)) |
| 2152 | /* We can not swap with an instruction that requires a |
| 2153 | delay slot, becase the target of the branch might |
| 2154 | interfere with that instruction. */ |
| 2155 | || (! mips_opts.mips16 |
| 2156 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
| 2157 | && (prev_pinfo |
| 2158 | /* Itbl support may require additional care here. */ |
| 2159 | & (INSN_LOAD_COPROC_DELAY |
| 2160 | | INSN_COPROC_MOVE_DELAY |
| 2161 | | INSN_WRITE_COND_CODE))) |
| 2162 | || (! (hilo_interlocks |
| 2163 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
| 2164 | && (prev_pinfo |
| 2165 | & (INSN_READ_LO |
| 2166 | | INSN_READ_HI))) |
| 2167 | || (! mips_opts.mips16 |
| 2168 | && ! gpr_interlocks |
| 2169 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) |
| 2170 | || (! mips_opts.mips16 |
| 2171 | && mips_opts.isa == ISA_MIPS1 |
| 2172 | /* Itbl support may require additional care here. */ |
| 2173 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) |
| 2174 | /* We can not swap with a branch instruction. */ |
| 2175 | || (prev_pinfo |
| 2176 | & (INSN_UNCOND_BRANCH_DELAY |
| 2177 | | INSN_COND_BRANCH_DELAY |
| 2178 | | INSN_COND_BRANCH_LIKELY)) |
| 2179 | /* We do not swap with a trap instruction, since it |
| 2180 | complicates trap handlers to have the trap |
| 2181 | instruction be in a delay slot. */ |
| 2182 | || (prev_pinfo & INSN_TRAP) |
| 2183 | /* If the branch reads a register that the previous |
| 2184 | instruction sets, we can not swap. */ |
| 2185 | || (! mips_opts.mips16 |
| 2186 | && (prev_pinfo & INSN_WRITE_GPR_T) |
| 2187 | && insn_uses_reg (ip, |
| 2188 | ((prev_insn.insn_opcode >> OP_SH_RT) |
| 2189 | & OP_MASK_RT), |
| 2190 | MIPS_GR_REG)) |
| 2191 | || (! mips_opts.mips16 |
| 2192 | && (prev_pinfo & INSN_WRITE_GPR_D) |
| 2193 | && insn_uses_reg (ip, |
| 2194 | ((prev_insn.insn_opcode >> OP_SH_RD) |
| 2195 | & OP_MASK_RD), |
| 2196 | MIPS_GR_REG)) |
| 2197 | || (mips_opts.mips16 |
| 2198 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) |
| 2199 | && insn_uses_reg (ip, |
| 2200 | ((prev_insn.insn_opcode |
| 2201 | >> MIPS16OP_SH_RX) |
| 2202 | & MIPS16OP_MASK_RX), |
| 2203 | MIPS16_REG)) |
| 2204 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) |
| 2205 | && insn_uses_reg (ip, |
| 2206 | ((prev_insn.insn_opcode |
| 2207 | >> MIPS16OP_SH_RY) |
| 2208 | & MIPS16OP_MASK_RY), |
| 2209 | MIPS16_REG)) |
| 2210 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) |
| 2211 | && insn_uses_reg (ip, |
| 2212 | ((prev_insn.insn_opcode |
| 2213 | >> MIPS16OP_SH_RZ) |
| 2214 | & MIPS16OP_MASK_RZ), |
| 2215 | MIPS16_REG)) |
| 2216 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) |
| 2217 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) |
| 2218 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) |
| 2219 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) |
| 2220 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) |
| 2221 | && insn_uses_reg (ip, |
| 2222 | MIPS16OP_EXTRACT_REG32R (prev_insn. |
| 2223 | insn_opcode), |
| 2224 | MIPS_GR_REG)))) |
| 2225 | /* If the branch writes a register that the previous |
| 2226 | instruction sets, we can not swap (we know that |
| 2227 | branches write only to RD or to $31). */ |
| 2228 | || (! mips_opts.mips16 |
| 2229 | && (prev_pinfo & INSN_WRITE_GPR_T) |
| 2230 | && (((pinfo & INSN_WRITE_GPR_D) |
| 2231 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
| 2232 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) |
| 2233 | || ((pinfo & INSN_WRITE_GPR_31) |
| 2234 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
| 2235 | & OP_MASK_RT) |
| 2236 | == RA)))) |
| 2237 | || (! mips_opts.mips16 |
| 2238 | && (prev_pinfo & INSN_WRITE_GPR_D) |
| 2239 | && (((pinfo & INSN_WRITE_GPR_D) |
| 2240 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
| 2241 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) |
| 2242 | || ((pinfo & INSN_WRITE_GPR_31) |
| 2243 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
| 2244 | & OP_MASK_RD) |
| 2245 | == RA)))) |
| 2246 | || (mips_opts.mips16 |
| 2247 | && (pinfo & MIPS16_INSN_WRITE_31) |
| 2248 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) |
| 2249 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) |
| 2250 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) |
| 2251 | == RA)))) |
| 2252 | /* If the branch writes a register that the previous |
| 2253 | instruction reads, we can not swap (we know that |
| 2254 | branches only write to RD or to $31). */ |
| 2255 | || (! mips_opts.mips16 |
| 2256 | && (pinfo & INSN_WRITE_GPR_D) |
| 2257 | && insn_uses_reg (&prev_insn, |
| 2258 | ((ip->insn_opcode >> OP_SH_RD) |
| 2259 | & OP_MASK_RD), |
| 2260 | MIPS_GR_REG)) |
| 2261 | || (! mips_opts.mips16 |
| 2262 | && (pinfo & INSN_WRITE_GPR_31) |
| 2263 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) |
| 2264 | || (mips_opts.mips16 |
| 2265 | && (pinfo & MIPS16_INSN_WRITE_31) |
| 2266 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) |
| 2267 | /* If we are generating embedded PIC code, the branch |
| 2268 | might be expanded into a sequence which uses $at, so |
| 2269 | we can't swap with an instruction which reads it. */ |
| 2270 | || (mips_pic == EMBEDDED_PIC |
| 2271 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) |
| 2272 | /* If the previous previous instruction has a load |
| 2273 | delay, and sets a register that the branch reads, we |
| 2274 | can not swap. */ |
| 2275 | || (! mips_opts.mips16 |
| 2276 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
| 2277 | /* Itbl support may require additional care here. */ |
| 2278 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
| 2279 | || (! gpr_interlocks |
| 2280 | && (prev_prev_insn.insn_mo->pinfo |
| 2281 | & INSN_LOAD_MEMORY_DELAY))) |
| 2282 | && insn_uses_reg (ip, |
| 2283 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) |
| 2284 | & OP_MASK_RT), |
| 2285 | MIPS_GR_REG)) |
| 2286 | /* If one instruction sets a condition code and the |
| 2287 | other one uses a condition code, we can not swap. */ |
| 2288 | || ((pinfo & INSN_READ_COND_CODE) |
| 2289 | && (prev_pinfo & INSN_WRITE_COND_CODE)) |
| 2290 | || ((pinfo & INSN_WRITE_COND_CODE) |
| 2291 | && (prev_pinfo & INSN_READ_COND_CODE)) |
| 2292 | /* If the previous instruction uses the PC, we can not |
| 2293 | swap. */ |
| 2294 | || (mips_opts.mips16 |
| 2295 | && (prev_pinfo & MIPS16_INSN_READ_PC)) |
| 2296 | /* If the previous instruction was extended, we can not |
| 2297 | swap. */ |
| 2298 | || (mips_opts.mips16 && prev_insn_extended) |
| 2299 | /* If the previous instruction had a fixup in mips16 |
| 2300 | mode, we can not swap. This normally means that the |
| 2301 | previous instruction was a 4 byte branch anyhow. */ |
| 2302 | || (mips_opts.mips16 && prev_insn_fixp[0]) |
| 2303 | /* If the previous instruction is a sync, sync.l, or |
| 2304 | sync.p, we can not swap. */ |
| 2305 | || (prev_pinfo & INSN_SYNC)) |
| 2306 | { |
| 2307 | /* We could do even better for unconditional branches to |
| 2308 | portions of this object file; we could pick up the |
| 2309 | instruction at the destination, put it in the delay |
| 2310 | slot, and bump the destination address. */ |
| 2311 | emit_nop (); |
| 2312 | /* Update the previous insn information. */ |
| 2313 | prev_prev_insn = *ip; |
| 2314 | prev_insn.insn_mo = &dummy_opcode; |
| 2315 | } |
| 2316 | else |
| 2317 | { |
| 2318 | /* It looks like we can actually do the swap. */ |
| 2319 | if (! mips_opts.mips16) |
| 2320 | { |
| 2321 | char *prev_f; |
| 2322 | char temp[4]; |
| 2323 | |
| 2324 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; |
| 2325 | memcpy (temp, prev_f, 4); |
| 2326 | memcpy (prev_f, f, 4); |
| 2327 | memcpy (f, temp, 4); |
| 2328 | if (prev_insn_fixp[0]) |
| 2329 | { |
| 2330 | prev_insn_fixp[0]->fx_frag = frag_now; |
| 2331 | prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal; |
| 2332 | } |
| 2333 | if (prev_insn_fixp[1]) |
| 2334 | { |
| 2335 | prev_insn_fixp[1]->fx_frag = frag_now; |
| 2336 | prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal; |
| 2337 | } |
| 2338 | if (prev_insn_fixp[2]) |
| 2339 | { |
| 2340 | prev_insn_fixp[2]->fx_frag = frag_now; |
| 2341 | prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal; |
| 2342 | } |
| 2343 | if (fixp[0]) |
| 2344 | { |
| 2345 | fixp[0]->fx_frag = prev_insn_frag; |
| 2346 | fixp[0]->fx_where = prev_insn_where; |
| 2347 | } |
| 2348 | if (fixp[1]) |
| 2349 | { |
| 2350 | fixp[1]->fx_frag = prev_insn_frag; |
| 2351 | fixp[1]->fx_where = prev_insn_where; |
| 2352 | } |
| 2353 | if (fixp[2]) |
| 2354 | { |
| 2355 | fixp[2]->fx_frag = prev_insn_frag; |
| 2356 | fixp[2]->fx_where = prev_insn_where; |
| 2357 | } |
| 2358 | } |
| 2359 | else |
| 2360 | { |
| 2361 | char *prev_f; |
| 2362 | char temp[2]; |
| 2363 | |
| 2364 | assert (prev_insn_fixp[0] == NULL); |
| 2365 | assert (prev_insn_fixp[1] == NULL); |
| 2366 | assert (prev_insn_fixp[2] == NULL); |
| 2367 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; |
| 2368 | memcpy (temp, prev_f, 2); |
| 2369 | memcpy (prev_f, f, 2); |
| 2370 | if (*reloc_type != BFD_RELOC_MIPS16_JMP) |
| 2371 | { |
| 2372 | assert (*reloc_type == BFD_RELOC_UNUSED); |
| 2373 | memcpy (f, temp, 2); |
| 2374 | } |
| 2375 | else |
| 2376 | { |
| 2377 | memcpy (f, f + 2, 2); |
| 2378 | memcpy (f + 2, temp, 2); |
| 2379 | } |
| 2380 | if (fixp[0]) |
| 2381 | { |
| 2382 | fixp[0]->fx_frag = prev_insn_frag; |
| 2383 | fixp[0]->fx_where = prev_insn_where; |
| 2384 | } |
| 2385 | if (fixp[1]) |
| 2386 | { |
| 2387 | fixp[1]->fx_frag = prev_insn_frag; |
| 2388 | fixp[1]->fx_where = prev_insn_where; |
| 2389 | } |
| 2390 | if (fixp[2]) |
| 2391 | { |
| 2392 | fixp[2]->fx_frag = prev_insn_frag; |
| 2393 | fixp[2]->fx_where = prev_insn_where; |
| 2394 | } |
| 2395 | } |
| 2396 | |
| 2397 | /* Update the previous insn information; leave prev_insn |
| 2398 | unchanged. */ |
| 2399 | prev_prev_insn = *ip; |
| 2400 | } |
| 2401 | prev_insn_is_delay_slot = 1; |
| 2402 | |
| 2403 | /* If that was an unconditional branch, forget the previous |
| 2404 | insn information. */ |
| 2405 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
| 2406 | { |
| 2407 | prev_prev_insn.insn_mo = &dummy_opcode; |
| 2408 | prev_insn.insn_mo = &dummy_opcode; |
| 2409 | } |
| 2410 | |
| 2411 | prev_insn_fixp[0] = NULL; |
| 2412 | prev_insn_fixp[1] = NULL; |
| 2413 | prev_insn_fixp[2] = NULL; |
| 2414 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; |
| 2415 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; |
| 2416 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; |
| 2417 | prev_insn_extended = 0; |
| 2418 | } |
| 2419 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
| 2420 | { |
| 2421 | /* We don't yet optimize a branch likely. What we should do |
| 2422 | is look at the target, copy the instruction found there |
| 2423 | into the delay slot, and increment the branch to jump to |
| 2424 | the next instruction. */ |
| 2425 | emit_nop (); |
| 2426 | /* Update the previous insn information. */ |
| 2427 | prev_prev_insn = *ip; |
| 2428 | prev_insn.insn_mo = &dummy_opcode; |
| 2429 | prev_insn_fixp[0] = NULL; |
| 2430 | prev_insn_fixp[1] = NULL; |
| 2431 | prev_insn_fixp[2] = NULL; |
| 2432 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; |
| 2433 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; |
| 2434 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; |
| 2435 | prev_insn_extended = 0; |
| 2436 | } |
| 2437 | else |
| 2438 | { |
| 2439 | /* Update the previous insn information. */ |
| 2440 | if (nops > 0) |
| 2441 | prev_prev_insn.insn_mo = &dummy_opcode; |
| 2442 | else |
| 2443 | prev_prev_insn = prev_insn; |
| 2444 | prev_insn = *ip; |
| 2445 | |
| 2446 | /* Any time we see a branch, we always fill the delay slot |
| 2447 | immediately; since this insn is not a branch, we know it |
| 2448 | is not in a delay slot. */ |
| 2449 | prev_insn_is_delay_slot = 0; |
| 2450 | |
| 2451 | prev_insn_fixp[0] = fixp[0]; |
| 2452 | prev_insn_fixp[1] = fixp[1]; |
| 2453 | prev_insn_fixp[2] = fixp[2]; |
| 2454 | prev_insn_reloc_type[0] = reloc_type[0]; |
| 2455 | prev_insn_reloc_type[1] = reloc_type[1]; |
| 2456 | prev_insn_reloc_type[2] = reloc_type[2]; |
| 2457 | if (mips_opts.mips16) |
| 2458 | prev_insn_extended = (ip->use_extend |
| 2459 | || *reloc_type > BFD_RELOC_UNUSED); |
| 2460 | } |
| 2461 | |
| 2462 | prev_prev_insn_unreordered = prev_insn_unreordered; |
| 2463 | prev_insn_unreordered = 0; |
| 2464 | prev_insn_frag = frag_now; |
| 2465 | prev_insn_where = f - frag_now->fr_literal; |
| 2466 | prev_insn_valid = 1; |
| 2467 | } |
| 2468 | else if (place == NULL) |
| 2469 | { |
| 2470 | /* We need to record a bit of information even when we are not |
| 2471 | reordering, in order to determine the base address for mips16 |
| 2472 | PC relative relocs. */ |
| 2473 | prev_prev_insn = prev_insn; |
| 2474 | prev_insn = *ip; |
| 2475 | prev_insn_reloc_type[0] = reloc_type[0]; |
| 2476 | prev_insn_reloc_type[1] = reloc_type[1]; |
| 2477 | prev_insn_reloc_type[2] = reloc_type[2]; |
| 2478 | prev_prev_insn_unreordered = prev_insn_unreordered; |
| 2479 | prev_insn_unreordered = 1; |
| 2480 | } |
| 2481 | |
| 2482 | /* We just output an insn, so the next one doesn't have a label. */ |
| 2483 | mips_clear_insn_labels (); |
| 2484 | |
| 2485 | /* We must ensure that a fixup associated with an unmatched %hi |
| 2486 | reloc does not become a variant frag. Otherwise, the |
| 2487 | rearrangement of %hi relocs in frob_file may confuse |
| 2488 | tc_gen_reloc. */ |
| 2489 | if (unmatched_hi) |
| 2490 | { |
| 2491 | frag_wane (frag_now); |
| 2492 | frag_new (0); |
| 2493 | } |
| 2494 | } |
| 2495 | |
| 2496 | /* This function forgets that there was any previous instruction or |
| 2497 | label. If PRESERVE is non-zero, it remembers enough information to |
| 2498 | know whether nops are needed before a noreorder section. */ |
| 2499 | |
| 2500 | static void |
| 2501 | mips_no_prev_insn (preserve) |
| 2502 | int preserve; |
| 2503 | { |
| 2504 | if (! preserve) |
| 2505 | { |
| 2506 | prev_insn.insn_mo = &dummy_opcode; |
| 2507 | prev_prev_insn.insn_mo = &dummy_opcode; |
| 2508 | prev_nop_frag = NULL; |
| 2509 | prev_nop_frag_holds = 0; |
| 2510 | prev_nop_frag_required = 0; |
| 2511 | prev_nop_frag_since = 0; |
| 2512 | } |
| 2513 | prev_insn_valid = 0; |
| 2514 | prev_insn_is_delay_slot = 0; |
| 2515 | prev_insn_unreordered = 0; |
| 2516 | prev_insn_extended = 0; |
| 2517 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; |
| 2518 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; |
| 2519 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; |
| 2520 | prev_prev_insn_unreordered = 0; |
| 2521 | mips_clear_insn_labels (); |
| 2522 | } |
| 2523 | |
| 2524 | /* This function must be called whenever we turn on noreorder or emit |
| 2525 | something other than instructions. It inserts any NOPS which might |
| 2526 | be needed by the previous instruction, and clears the information |
| 2527 | kept for the previous instructions. The INSNS parameter is true if |
| 2528 | instructions are to follow. */ |
| 2529 | |
| 2530 | static void |
| 2531 | mips_emit_delays (insns) |
| 2532 | boolean insns; |
| 2533 | { |
| 2534 | if (! mips_opts.noreorder) |
| 2535 | { |
| 2536 | int nops; |
| 2537 | |
| 2538 | nops = 0; |
| 2539 | if ((! mips_opts.mips16 |
| 2540 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
| 2541 | && (! cop_interlocks |
| 2542 | && (prev_insn.insn_mo->pinfo |
| 2543 | & (INSN_LOAD_COPROC_DELAY |
| 2544 | | INSN_COPROC_MOVE_DELAY |
| 2545 | | INSN_WRITE_COND_CODE)))) |
| 2546 | || (! hilo_interlocks |
| 2547 | && (prev_insn.insn_mo->pinfo |
| 2548 | & (INSN_READ_LO |
| 2549 | | INSN_READ_HI))) |
| 2550 | || (! mips_opts.mips16 |
| 2551 | && ! gpr_interlocks |
| 2552 | && (prev_insn.insn_mo->pinfo |
| 2553 | & INSN_LOAD_MEMORY_DELAY)) |
| 2554 | || (! mips_opts.mips16 |
| 2555 | && mips_opts.isa == ISA_MIPS1 |
| 2556 | && (prev_insn.insn_mo->pinfo |
| 2557 | & INSN_COPROC_MEMORY_DELAY))) |
| 2558 | { |
| 2559 | /* Itbl support may require additional care here. */ |
| 2560 | ++nops; |
| 2561 | if ((! mips_opts.mips16 |
| 2562 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
| 2563 | && (! cop_interlocks |
| 2564 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) |
| 2565 | || (! hilo_interlocks |
| 2566 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) |
| 2567 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) |
| 2568 | ++nops; |
| 2569 | |
| 2570 | if (prev_insn_unreordered) |
| 2571 | nops = 0; |
| 2572 | } |
| 2573 | else if ((! mips_opts.mips16 |
| 2574 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
| 2575 | && (! cop_interlocks |
| 2576 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) |
| 2577 | || (! hilo_interlocks |
| 2578 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
| 2579 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) |
| 2580 | { |
| 2581 | /* Itbl support may require additional care here. */ |
| 2582 | if (! prev_prev_insn_unreordered) |
| 2583 | ++nops; |
| 2584 | } |
| 2585 | |
| 2586 | if (nops > 0) |
| 2587 | { |
| 2588 | struct insn_label_list *l; |
| 2589 | |
| 2590 | if (insns) |
| 2591 | { |
| 2592 | /* Record the frag which holds the nop instructions, so |
| 2593 | that we can remove them if we don't need them. */ |
| 2594 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); |
| 2595 | prev_nop_frag = frag_now; |
| 2596 | prev_nop_frag_holds = nops; |
| 2597 | prev_nop_frag_required = 0; |
| 2598 | prev_nop_frag_since = 0; |
| 2599 | } |
| 2600 | |
| 2601 | for (; nops > 0; --nops) |
| 2602 | emit_nop (); |
| 2603 | |
| 2604 | if (insns) |
| 2605 | { |
| 2606 | /* Move on to a new frag, so that it is safe to simply |
| 2607 | decrease the size of prev_nop_frag. */ |
| 2608 | frag_wane (frag_now); |
| 2609 | frag_new (0); |
| 2610 | } |
| 2611 | |
| 2612 | for (l = insn_labels; l != NULL; l = l->next) |
| 2613 | { |
| 2614 | valueT val; |
| 2615 | |
| 2616 | assert (S_GET_SEGMENT (l->label) == now_seg); |
| 2617 | symbol_set_frag (l->label, frag_now); |
| 2618 | val = (valueT) frag_now_fix (); |
| 2619 | /* mips16 text labels are stored as odd. */ |
| 2620 | if (mips_opts.mips16) |
| 2621 | ++val; |
| 2622 | S_SET_VALUE (l->label, val); |
| 2623 | } |
| 2624 | } |
| 2625 | } |
| 2626 | |
| 2627 | /* Mark instruction labels in mips16 mode. */ |
| 2628 | if (insns) |
| 2629 | mips16_mark_labels (); |
| 2630 | |
| 2631 | mips_no_prev_insn (insns); |
| 2632 | } |
| 2633 | |
| 2634 | /* Build an instruction created by a macro expansion. This is passed |
| 2635 | a pointer to the count of instructions created so far, an |
| 2636 | expression, the name of the instruction to build, an operand format |
| 2637 | string, and corresponding arguments. */ |
| 2638 | |
| 2639 | #ifdef USE_STDARG |
| 2640 | static void |
| 2641 | macro_build (char *place, |
| 2642 | int *counter, |
| 2643 | expressionS * ep, |
| 2644 | const char *name, |
| 2645 | const char *fmt, |
| 2646 | ...) |
| 2647 | #else |
| 2648 | static void |
| 2649 | macro_build (place, counter, ep, name, fmt, va_alist) |
| 2650 | char *place; |
| 2651 | int *counter; |
| 2652 | expressionS *ep; |
| 2653 | const char *name; |
| 2654 | const char *fmt; |
| 2655 | va_dcl |
| 2656 | #endif |
| 2657 | { |
| 2658 | struct mips_cl_insn insn; |
| 2659 | bfd_reloc_code_real_type r[3]; |
| 2660 | va_list args; |
| 2661 | |
| 2662 | #ifdef USE_STDARG |
| 2663 | va_start (args, fmt); |
| 2664 | #else |
| 2665 | va_start (args); |
| 2666 | #endif |
| 2667 | |
| 2668 | /* |
| 2669 | * If the macro is about to expand into a second instruction, |
| 2670 | * print a warning if needed. We need to pass ip as a parameter |
| 2671 | * to generate a better warning message here... |
| 2672 | */ |
| 2673 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) |
| 2674 | as_warn (_("Macro instruction expanded into multiple instructions")); |
| 2675 | |
| 2676 | /* |
| 2677 | * If the macro is about to expand into a second instruction, |
| 2678 | * and it is in a delay slot, print a warning. |
| 2679 | */ |
| 2680 | if (place == NULL |
| 2681 | && *counter == 1 |
| 2682 | && mips_opts.noreorder |
| 2683 | && (prev_prev_insn.insn_mo->pinfo |
| 2684 | & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY |
| 2685 | | INSN_COND_BRANCH_LIKELY)) != 0) |
| 2686 | as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot")); |
| 2687 | |
| 2688 | if (place == NULL) |
| 2689 | ++*counter; /* bump instruction counter */ |
| 2690 | |
| 2691 | if (mips_opts.mips16) |
| 2692 | { |
| 2693 | mips16_macro_build (place, counter, ep, name, fmt, args); |
| 2694 | va_end (args); |
| 2695 | return; |
| 2696 | } |
| 2697 | |
| 2698 | r[0] = BFD_RELOC_UNUSED; |
| 2699 | r[1] = BFD_RELOC_UNUSED; |
| 2700 | r[2] = BFD_RELOC_UNUSED; |
| 2701 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
| 2702 | assert (insn.insn_mo); |
| 2703 | assert (strcmp (name, insn.insn_mo->name) == 0); |
| 2704 | |
| 2705 | /* Search until we get a match for NAME. */ |
| 2706 | while (1) |
| 2707 | { |
| 2708 | /* It is assumed here that macros will never generate |
| 2709 | MDMX or MIPS-3D instructions. */ |
| 2710 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
| 2711 | && insn.insn_mo->pinfo != INSN_MACRO |
| 2712 | && OPCODE_IS_MEMBER (insn.insn_mo, |
| 2713 | (mips_opts.isa |
| 2714 | | (mips_opts.mips16 ? INSN_MIPS16 : 0)), |
| 2715 | mips_arch) |
| 2716 | && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) |
| 2717 | break; |
| 2718 | |
| 2719 | ++insn.insn_mo; |
| 2720 | assert (insn.insn_mo->name); |
| 2721 | assert (strcmp (name, insn.insn_mo->name) == 0); |
| 2722 | } |
| 2723 | |
| 2724 | insn.insn_opcode = insn.insn_mo->match; |
| 2725 | for (;;) |
| 2726 | { |
| 2727 | switch (*fmt++) |
| 2728 | { |
| 2729 | case '\0': |
| 2730 | break; |
| 2731 | |
| 2732 | case ',': |
| 2733 | case '(': |
| 2734 | case ')': |
| 2735 | continue; |
| 2736 | |
| 2737 | case 't': |
| 2738 | case 'w': |
| 2739 | case 'E': |
| 2740 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; |
| 2741 | continue; |
| 2742 | |
| 2743 | case 'c': |
| 2744 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; |
| 2745 | continue; |
| 2746 | |
| 2747 | case 'T': |
| 2748 | case 'W': |
| 2749 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; |
| 2750 | continue; |
| 2751 | |
| 2752 | case 'd': |
| 2753 | case 'G': |
| 2754 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; |
| 2755 | continue; |
| 2756 | |
| 2757 | case 'U': |
| 2758 | { |
| 2759 | int tmp = va_arg (args, int); |
| 2760 | |
| 2761 | insn.insn_opcode |= tmp << OP_SH_RT; |
| 2762 | insn.insn_opcode |= tmp << OP_SH_RD; |
| 2763 | continue; |
| 2764 | } |
| 2765 | |
| 2766 | case 'V': |
| 2767 | case 'S': |
| 2768 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; |
| 2769 | continue; |
| 2770 | |
| 2771 | case 'z': |
| 2772 | continue; |
| 2773 | |
| 2774 | case '<': |
| 2775 | insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; |
| 2776 | continue; |
| 2777 | |
| 2778 | case 'D': |
| 2779 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; |
| 2780 | continue; |
| 2781 | |
| 2782 | case 'B': |
| 2783 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; |
| 2784 | continue; |
| 2785 | |
| 2786 | case 'J': |
| 2787 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; |
| 2788 | continue; |
| 2789 | |
| 2790 | case 'q': |
| 2791 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; |
| 2792 | continue; |
| 2793 | |
| 2794 | case 'b': |
| 2795 | case 's': |
| 2796 | case 'r': |
| 2797 | case 'v': |
| 2798 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; |
| 2799 | continue; |
| 2800 | |
| 2801 | case 'i': |
| 2802 | case 'j': |
| 2803 | case 'o': |
| 2804 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
| 2805 | assert (*r == BFD_RELOC_GPREL16 |
| 2806 | || *r == BFD_RELOC_MIPS_LITERAL |
| 2807 | || *r == BFD_RELOC_MIPS_HIGHER |
| 2808 | || *r == BFD_RELOC_HI16_S |
| 2809 | || *r == BFD_RELOC_LO16 |
| 2810 | || *r == BFD_RELOC_MIPS_GOT16 |
| 2811 | || *r == BFD_RELOC_MIPS_CALL16 |
| 2812 | || *r == BFD_RELOC_MIPS_GOT_DISP |
| 2813 | || *r == BFD_RELOC_MIPS_GOT_PAGE |
| 2814 | || *r == BFD_RELOC_MIPS_GOT_OFST |
| 2815 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
| 2816 | || *r == BFD_RELOC_MIPS_CALL_LO16 |
| 2817 | || (ep->X_op == O_subtract |
| 2818 | && *r == BFD_RELOC_PCREL_LO16)); |
| 2819 | continue; |
| 2820 | |
| 2821 | case 'u': |
| 2822 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
| 2823 | assert (ep != NULL |
| 2824 | && (ep->X_op == O_constant |
| 2825 | || (ep->X_op == O_symbol |
| 2826 | && (*r == BFD_RELOC_MIPS_HIGHEST |
| 2827 | || *r == BFD_RELOC_HI16_S |
| 2828 | || *r == BFD_RELOC_HI16 |
| 2829 | || *r == BFD_RELOC_GPREL16 |
| 2830 | || *r == BFD_RELOC_MIPS_GOT_HI16 |
| 2831 | || *r == BFD_RELOC_MIPS_CALL_HI16)) |
| 2832 | || (ep->X_op == O_subtract |
| 2833 | && *r == BFD_RELOC_PCREL_HI16_S))); |
| 2834 | continue; |
| 2835 | |
| 2836 | case 'p': |
| 2837 | assert (ep != NULL); |
| 2838 | /* |
| 2839 | * This allows macro() to pass an immediate expression for |
| 2840 | * creating short branches without creating a symbol. |
| 2841 | * Note that the expression still might come from the assembly |
| 2842 | * input, in which case the value is not checked for range nor |
| 2843 | * is a relocation entry generated (yuck). |
| 2844 | */ |
| 2845 | if (ep->X_op == O_constant) |
| 2846 | { |
| 2847 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
| 2848 | ep = NULL; |
| 2849 | } |
| 2850 | else |
| 2851 | if (mips_pic == EMBEDDED_PIC) |
| 2852 | *r = BFD_RELOC_16_PCREL_S2; |
| 2853 | else |
| 2854 | *r = BFD_RELOC_16_PCREL; |
| 2855 | continue; |
| 2856 | |
| 2857 | case 'a': |
| 2858 | assert (ep != NULL); |
| 2859 | *r = BFD_RELOC_MIPS_JMP; |
| 2860 | continue; |
| 2861 | |
| 2862 | case 'C': |
| 2863 | insn.insn_opcode |= va_arg (args, unsigned long); |
| 2864 | continue; |
| 2865 | |
| 2866 | default: |
| 2867 | internalError (); |
| 2868 | } |
| 2869 | break; |
| 2870 | } |
| 2871 | va_end (args); |
| 2872 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
| 2873 | |
| 2874 | append_insn (place, &insn, ep, r, false); |
| 2875 | } |
| 2876 | |
| 2877 | static void |
| 2878 | mips16_macro_build (place, counter, ep, name, fmt, args) |
| 2879 | char *place; |
| 2880 | int *counter ATTRIBUTE_UNUSED; |
| 2881 | expressionS *ep; |
| 2882 | const char *name; |
| 2883 | const char *fmt; |
| 2884 | va_list args; |
| 2885 | { |
| 2886 | struct mips_cl_insn insn; |
| 2887 | bfd_reloc_code_real_type r[3] |
| 2888 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; |
| 2889 | |
| 2890 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
| 2891 | assert (insn.insn_mo); |
| 2892 | assert (strcmp (name, insn.insn_mo->name) == 0); |
| 2893 | |
| 2894 | while (strcmp (fmt, insn.insn_mo->args) != 0 |
| 2895 | || insn.insn_mo->pinfo == INSN_MACRO) |
| 2896 | { |
| 2897 | ++insn.insn_mo; |
| 2898 | assert (insn.insn_mo->name); |
| 2899 | assert (strcmp (name, insn.insn_mo->name) == 0); |
| 2900 | } |
| 2901 | |
| 2902 | insn.insn_opcode = insn.insn_mo->match; |
| 2903 | insn.use_extend = false; |
| 2904 | |
| 2905 | for (;;) |
| 2906 | { |
| 2907 | int c; |
| 2908 | |
| 2909 | c = *fmt++; |
| 2910 | switch (c) |
| 2911 | { |
| 2912 | case '\0': |
| 2913 | break; |
| 2914 | |
| 2915 | case ',': |
| 2916 | case '(': |
| 2917 | case ')': |
| 2918 | continue; |
| 2919 | |
| 2920 | case 'y': |
| 2921 | case 'w': |
| 2922 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; |
| 2923 | continue; |
| 2924 | |
| 2925 | case 'x': |
| 2926 | case 'v': |
| 2927 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; |
| 2928 | continue; |
| 2929 | |
| 2930 | case 'z': |
| 2931 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; |
| 2932 | continue; |
| 2933 | |
| 2934 | case 'Z': |
| 2935 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; |
| 2936 | continue; |
| 2937 | |
| 2938 | case '0': |
| 2939 | case 'S': |
| 2940 | case 'P': |
| 2941 | case 'R': |
| 2942 | continue; |
| 2943 | |
| 2944 | case 'X': |
| 2945 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; |
| 2946 | continue; |
| 2947 | |
| 2948 | case 'Y': |
| 2949 | { |
| 2950 | int regno; |
| 2951 | |
| 2952 | regno = va_arg (args, int); |
| 2953 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
| 2954 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; |
| 2955 | } |
| 2956 | continue; |
| 2957 | |
| 2958 | case '<': |
| 2959 | case '>': |
| 2960 | case '4': |
| 2961 | case '5': |
| 2962 | case 'H': |
| 2963 | case 'W': |
| 2964 | case 'D': |
| 2965 | case 'j': |
| 2966 | case '8': |
| 2967 | case 'V': |
| 2968 | case 'C': |
| 2969 | case 'U': |
| 2970 | case 'k': |
| 2971 | case 'K': |
| 2972 | case 'p': |
| 2973 | case 'q': |
| 2974 | { |
| 2975 | assert (ep != NULL); |
| 2976 | |
| 2977 | if (ep->X_op != O_constant) |
| 2978 | *r = (int) BFD_RELOC_UNUSED + c; |
| 2979 | else |
| 2980 | { |
| 2981 | mips16_immed (NULL, 0, c, ep->X_add_number, false, false, |
| 2982 | false, &insn.insn_opcode, &insn.use_extend, |
| 2983 | &insn.extend); |
| 2984 | ep = NULL; |
| 2985 | *r = BFD_RELOC_UNUSED; |
| 2986 | } |
| 2987 | } |
| 2988 | continue; |
| 2989 | |
| 2990 | case '6': |
| 2991 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; |
| 2992 | continue; |
| 2993 | } |
| 2994 | |
| 2995 | break; |
| 2996 | } |
| 2997 | |
| 2998 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
| 2999 | |
| 3000 | append_insn (place, &insn, ep, r, false); |
| 3001 | } |
| 3002 | |
| 3003 | /* |
| 3004 | * Generate a "jalr" instruction with a relocation hint to the called |
| 3005 | * function. This occurs in NewABI PIC code. |
| 3006 | */ |
| 3007 | static void |
| 3008 | macro_build_jalr (icnt, ep) |
| 3009 | int icnt; |
| 3010 | expressionS *ep; |
| 3011 | { |
| 3012 | if (HAVE_NEWABI) |
| 3013 | frag_more (0); |
| 3014 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", "d,s", |
| 3015 | RA, PIC_CALL_REG); |
| 3016 | if (HAVE_NEWABI) |
| 3017 | fix_new_exp (frag_now, 0, 0, ep, false, BFD_RELOC_MIPS_JALR); |
| 3018 | } |
| 3019 | |
| 3020 | /* |
| 3021 | * Generate a "lui" instruction. |
| 3022 | */ |
| 3023 | static void |
| 3024 | macro_build_lui (place, counter, ep, regnum) |
| 3025 | char *place; |
| 3026 | int *counter; |
| 3027 | expressionS *ep; |
| 3028 | int regnum; |
| 3029 | { |
| 3030 | expressionS high_expr; |
| 3031 | struct mips_cl_insn insn; |
| 3032 | bfd_reloc_code_real_type r[3] |
| 3033 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; |
| 3034 | const char *name = "lui"; |
| 3035 | const char *fmt = "t,u"; |
| 3036 | |
| 3037 | assert (! mips_opts.mips16); |
| 3038 | |
| 3039 | if (place == NULL) |
| 3040 | high_expr = *ep; |
| 3041 | else |
| 3042 | { |
| 3043 | high_expr.X_op = O_constant; |
| 3044 | high_expr.X_add_number = ep->X_add_number; |
| 3045 | } |
| 3046 | |
| 3047 | if (high_expr.X_op == O_constant) |
| 3048 | { |
| 3049 | /* we can compute the instruction now without a relocation entry */ |
| 3050 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
| 3051 | >> 16) & 0xffff; |
| 3052 | *r = BFD_RELOC_UNUSED; |
| 3053 | } |
| 3054 | else if (! HAVE_NEWABI) |
| 3055 | { |
| 3056 | assert (ep->X_op == O_symbol); |
| 3057 | /* _gp_disp is a special case, used from s_cpload. */ |
| 3058 | assert (mips_pic == NO_PIC |
| 3059 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
| 3060 | *r = BFD_RELOC_HI16_S; |
| 3061 | } |
| 3062 | |
| 3063 | /* |
| 3064 | * If the macro is about to expand into a second instruction, |
| 3065 | * print a warning if needed. We need to pass ip as a parameter |
| 3066 | * to generate a better warning message here... |
| 3067 | */ |
| 3068 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) |
| 3069 | as_warn (_("Macro instruction expanded into multiple instructions")); |
| 3070 | |
| 3071 | if (place == NULL) |
| 3072 | ++*counter; /* bump instruction counter */ |
| 3073 | |
| 3074 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
| 3075 | assert (insn.insn_mo); |
| 3076 | assert (strcmp (name, insn.insn_mo->name) == 0); |
| 3077 | assert (strcmp (fmt, insn.insn_mo->args) == 0); |
| 3078 | |
| 3079 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
| 3080 | if (*r == BFD_RELOC_UNUSED) |
| 3081 | { |
| 3082 | insn.insn_opcode |= high_expr.X_add_number; |
| 3083 | append_insn (place, &insn, NULL, r, false); |
| 3084 | } |
| 3085 | else |
| 3086 | append_insn (place, &insn, &high_expr, r, false); |
| 3087 | } |
| 3088 | |
| 3089 | /* set_at() |
| 3090 | * Generates code to set the $at register to true (one) |
| 3091 | * if reg is less than the immediate expression. |
| 3092 | */ |
| 3093 | static void |
| 3094 | set_at (counter, reg, unsignedp) |
| 3095 | int *counter; |
| 3096 | int reg; |
| 3097 | int unsignedp; |
| 3098 | { |
| 3099 | if (imm_expr.X_op == O_constant |
| 3100 | && imm_expr.X_add_number >= -0x8000 |
| 3101 | && imm_expr.X_add_number < 0x8000) |
| 3102 | macro_build ((char *) NULL, counter, &imm_expr, |
| 3103 | unsignedp ? "sltiu" : "slti", |
| 3104 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
| 3105 | else |
| 3106 | { |
| 3107 | load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS); |
| 3108 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
| 3109 | unsignedp ? "sltu" : "slt", |
| 3110 | "d,v,t", AT, reg, AT); |
| 3111 | } |
| 3112 | } |
| 3113 | |
| 3114 | /* Warn if an expression is not a constant. */ |
| 3115 | |
| 3116 | static void |
| 3117 | check_absolute_expr (ip, ex) |
| 3118 | struct mips_cl_insn *ip; |
| 3119 | expressionS *ex; |
| 3120 | { |
| 3121 | if (ex->X_op == O_big) |
| 3122 | as_bad (_("unsupported large constant")); |
| 3123 | else if (ex->X_op != O_constant) |
| 3124 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); |
| 3125 | } |
| 3126 | |
| 3127 | /* Count the leading zeroes by performing a binary chop. This is a |
| 3128 | bulky bit of source, but performance is a LOT better for the |
| 3129 | majority of values than a simple loop to count the bits: |
| 3130 | for (lcnt = 0; (lcnt < 32); lcnt++) |
| 3131 | if ((v) & (1 << (31 - lcnt))) |
| 3132 | break; |
| 3133 | However it is not code size friendly, and the gain will drop a bit |
| 3134 | on certain cached systems. |
| 3135 | */ |
| 3136 | #define COUNT_TOP_ZEROES(v) \ |
| 3137 | (((v) & ~0xffff) == 0 \ |
| 3138 | ? ((v) & ~0xff) == 0 \ |
| 3139 | ? ((v) & ~0xf) == 0 \ |
| 3140 | ? ((v) & ~0x3) == 0 \ |
| 3141 | ? ((v) & ~0x1) == 0 \ |
| 3142 | ? !(v) \ |
| 3143 | ? 32 \ |
| 3144 | : 31 \ |
| 3145 | : 30 \ |
| 3146 | : ((v) & ~0x7) == 0 \ |
| 3147 | ? 29 \ |
| 3148 | : 28 \ |
| 3149 | : ((v) & ~0x3f) == 0 \ |
| 3150 | ? ((v) & ~0x1f) == 0 \ |
| 3151 | ? 27 \ |
| 3152 | : 26 \ |
| 3153 | : ((v) & ~0x7f) == 0 \ |
| 3154 | ? 25 \ |
| 3155 | : 24 \ |
| 3156 | : ((v) & ~0xfff) == 0 \ |
| 3157 | ? ((v) & ~0x3ff) == 0 \ |
| 3158 | ? ((v) & ~0x1ff) == 0 \ |
| 3159 | ? 23 \ |
| 3160 | : 22 \ |
| 3161 | : ((v) & ~0x7ff) == 0 \ |
| 3162 | ? 21 \ |
| 3163 | : 20 \ |
| 3164 | : ((v) & ~0x3fff) == 0 \ |
| 3165 | ? ((v) & ~0x1fff) == 0 \ |
| 3166 | ? 19 \ |
| 3167 | : 18 \ |
| 3168 | : ((v) & ~0x7fff) == 0 \ |
| 3169 | ? 17 \ |
| 3170 | : 16 \ |
| 3171 | : ((v) & ~0xffffff) == 0 \ |
| 3172 | ? ((v) & ~0xfffff) == 0 \ |
| 3173 | ? ((v) & ~0x3ffff) == 0 \ |
| 3174 | ? ((v) & ~0x1ffff) == 0 \ |
| 3175 | ? 15 \ |
| 3176 | : 14 \ |
| 3177 | : ((v) & ~0x7ffff) == 0 \ |
| 3178 | ? 13 \ |
| 3179 | : 12 \ |
| 3180 | : ((v) & ~0x3fffff) == 0 \ |
| 3181 | ? ((v) & ~0x1fffff) == 0 \ |
| 3182 | ? 11 \ |
| 3183 | : 10 \ |
| 3184 | : ((v) & ~0x7fffff) == 0 \ |
| 3185 | ? 9 \ |
| 3186 | : 8 \ |
| 3187 | : ((v) & ~0xfffffff) == 0 \ |
| 3188 | ? ((v) & ~0x3ffffff) == 0 \ |
| 3189 | ? ((v) & ~0x1ffffff) == 0 \ |
| 3190 | ? 7 \ |
| 3191 | : 6 \ |
| 3192 | : ((v) & ~0x7ffffff) == 0 \ |
| 3193 | ? 5 \ |
| 3194 | : 4 \ |
| 3195 | : ((v) & ~0x3fffffff) == 0 \ |
| 3196 | ? ((v) & ~0x1fffffff) == 0 \ |
| 3197 | ? 3 \ |
| 3198 | : 2 \ |
| 3199 | : ((v) & ~0x7fffffff) == 0 \ |
| 3200 | ? 1 \ |
| 3201 | : 0) |
| 3202 | |
| 3203 | /* Is the given value a sign-extended 32-bit value? */ |
| 3204 | #define IS_SEXT_32BIT_NUM(x) \ |
| 3205 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ |
| 3206 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) |
| 3207 | |
| 3208 | /* load_register() |
| 3209 | * This routine generates the least number of instructions neccessary to load |
| 3210 | * an absolute expression value into a register. |
| 3211 | */ |
| 3212 | static void |
| 3213 | load_register (counter, reg, ep, dbl) |
| 3214 | int *counter; |
| 3215 | int reg; |
| 3216 | expressionS *ep; |
| 3217 | int dbl; |
| 3218 | { |
| 3219 | int freg; |
| 3220 | expressionS hi32, lo32; |
| 3221 | |
| 3222 | if (ep->X_op != O_big) |
| 3223 | { |
| 3224 | assert (ep->X_op == O_constant); |
| 3225 | if (ep->X_add_number < 0x8000 |
| 3226 | && (ep->X_add_number >= 0 |
| 3227 | || (ep->X_add_number >= -0x8000 |
| 3228 | && (! dbl |
| 3229 | || ! ep->X_unsigned |
| 3230 | || sizeof (ep->X_add_number) > 4)))) |
| 3231 | { |
| 3232 | /* We can handle 16 bit signed values with an addiu to |
| 3233 | $zero. No need to ever use daddiu here, since $zero and |
| 3234 | the result are always correct in 32 bit mode. */ |
| 3235 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
| 3236 | (int) BFD_RELOC_LO16); |
| 3237 | return; |
| 3238 | } |
| 3239 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) |
| 3240 | { |
| 3241 | /* We can handle 16 bit unsigned values with an ori to |
| 3242 | $zero. */ |
| 3243 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, |
| 3244 | (int) BFD_RELOC_LO16); |
| 3245 | return; |
| 3246 | } |
| 3247 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number) |
| 3248 | && (! dbl |
| 3249 | || ! ep->X_unsigned |
| 3250 | || sizeof (ep->X_add_number) > 4 |
| 3251 | || (ep->X_add_number & 0x80000000) == 0)) |
| 3252 | || ((HAVE_32BIT_GPRS || ! dbl) |
| 3253 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
| 3254 | || (HAVE_32BIT_GPRS |
| 3255 | && ! dbl |
| 3256 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) |
| 3257 | == ~ (offsetT) 0xffffffff))) |
| 3258 | { |
| 3259 | /* 32 bit values require an lui. */ |
| 3260 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, |
| 3261 | (int) BFD_RELOC_HI16); |
| 3262 | if ((ep->X_add_number & 0xffff) != 0) |
| 3263 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, |
| 3264 | (int) BFD_RELOC_LO16); |
| 3265 | return; |
| 3266 | } |
| 3267 | } |
| 3268 | |
| 3269 | /* The value is larger than 32 bits. */ |
| 3270 | |
| 3271 | if (HAVE_32BIT_GPRS) |
| 3272 | { |
| 3273 | as_bad (_("Number (0x%lx) larger than 32 bits"), |
| 3274 | (unsigned long) ep->X_add_number); |
| 3275 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
| 3276 | (int) BFD_RELOC_LO16); |
| 3277 | return; |
| 3278 | } |
| 3279 | |
| 3280 | if (ep->X_op != O_big) |
| 3281 | { |
| 3282 | hi32 = *ep; |
| 3283 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; |
| 3284 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; |
| 3285 | hi32.X_add_number &= 0xffffffff; |
| 3286 | lo32 = *ep; |
| 3287 | lo32.X_add_number &= 0xffffffff; |
| 3288 | } |
| 3289 | else |
| 3290 | { |
| 3291 | assert (ep->X_add_number > 2); |
| 3292 | if (ep->X_add_number == 3) |
| 3293 | generic_bignum[3] = 0; |
| 3294 | else if (ep->X_add_number > 4) |
| 3295 | as_bad (_("Number larger than 64 bits")); |
| 3296 | lo32.X_op = O_constant; |
| 3297 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); |
| 3298 | hi32.X_op = O_constant; |
| 3299 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); |
| 3300 | } |
| 3301 | |
| 3302 | if (hi32.X_add_number == 0) |
| 3303 | freg = 0; |
| 3304 | else |
| 3305 | { |
| 3306 | int shift, bit; |
| 3307 | unsigned long hi, lo; |
| 3308 | |
| 3309 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
| 3310 | { |
| 3311 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) |
| 3312 | { |
| 3313 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", |
| 3314 | reg, 0, (int) BFD_RELOC_LO16); |
| 3315 | return; |
| 3316 | } |
| 3317 | if (lo32.X_add_number & 0x80000000) |
| 3318 | { |
| 3319 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, |
| 3320 | (int) BFD_RELOC_HI16); |
| 3321 | if (lo32.X_add_number & 0xffff) |
| 3322 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", |
| 3323 | reg, reg, (int) BFD_RELOC_LO16); |
| 3324 | return; |
| 3325 | } |
| 3326 | } |
| 3327 | |
| 3328 | /* Check for 16bit shifted constant. We know that hi32 is |
| 3329 | non-zero, so start the mask on the first bit of the hi32 |
| 3330 | value. */ |
| 3331 | shift = 17; |
| 3332 | do |
| 3333 | { |
| 3334 | unsigned long himask, lomask; |
| 3335 | |
| 3336 | if (shift < 32) |
| 3337 | { |
| 3338 | himask = 0xffff >> (32 - shift); |
| 3339 | lomask = (0xffff << shift) & 0xffffffff; |
| 3340 | } |
| 3341 | else |
| 3342 | { |
| 3343 | himask = 0xffff << (shift - 32); |
| 3344 | lomask = 0; |
| 3345 | } |
| 3346 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 |
| 3347 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) |
| 3348 | { |
| 3349 | expressionS tmp; |
| 3350 | |
| 3351 | tmp.X_op = O_constant; |
| 3352 | if (shift < 32) |
| 3353 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) |
| 3354 | | (lo32.X_add_number >> shift)); |
| 3355 | else |
| 3356 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); |
| 3357 | macro_build ((char *) NULL, counter, &tmp, |
| 3358 | "ori", "t,r,i", reg, 0, |
| 3359 | (int) BFD_RELOC_LO16); |
| 3360 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
| 3361 | (shift >= 32) ? "dsll32" : "dsll", |
| 3362 | "d,w,<", reg, reg, |
| 3363 | (shift >= 32) ? shift - 32 : shift); |
| 3364 | return; |
| 3365 | } |
| 3366 | ++shift; |
| 3367 | } |
| 3368 | while (shift <= (64 - 16)); |
| 3369 | |
| 3370 | /* Find the bit number of the lowest one bit, and store the |
| 3371 | shifted value in hi/lo. */ |
| 3372 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); |
| 3373 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); |
| 3374 | if (lo != 0) |
| 3375 | { |
| 3376 | bit = 0; |
| 3377 | while ((lo & 1) == 0) |
| 3378 | { |
| 3379 | lo >>= 1; |
| 3380 | ++bit; |
| 3381 | } |
| 3382 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); |
| 3383 | hi >>= bit; |
| 3384 | } |
| 3385 | else |
| 3386 | { |
| 3387 | bit = 32; |
| 3388 | while ((hi & 1) == 0) |
| 3389 | { |
| 3390 | hi >>= 1; |
| 3391 | ++bit; |
| 3392 | } |
| 3393 | lo = hi; |
| 3394 | hi = 0; |
| 3395 | } |
| 3396 | |
| 3397 | /* Optimize if the shifted value is a (power of 2) - 1. */ |
| 3398 | if ((hi == 0 && ((lo + 1) & lo) == 0) |
| 3399 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) |
| 3400 | { |
| 3401 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); |
| 3402 | if (shift != 0) |
| 3403 | { |
| 3404 | expressionS tmp; |
| 3405 | |
| 3406 | /* This instruction will set the register to be all |
| 3407 | ones. */ |
| 3408 | tmp.X_op = O_constant; |
| 3409 | tmp.X_add_number = (offsetT) -1; |
| 3410 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", |
| 3411 | reg, 0, (int) BFD_RELOC_LO16); |
| 3412 | if (bit != 0) |
| 3413 | { |
| 3414 | bit += shift; |
| 3415 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
| 3416 | (bit >= 32) ? "dsll32" : "dsll", |
| 3417 | "d,w,<", reg, reg, |
| 3418 | (bit >= 32) ? bit - 32 : bit); |
| 3419 | } |
| 3420 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
| 3421 | (shift >= 32) ? "dsrl32" : "dsrl", |
| 3422 | "d,w,<", reg, reg, |
| 3423 | (shift >= 32) ? shift - 32 : shift); |
| 3424 | return; |
| 3425 | } |
| 3426 | } |
| 3427 | |
| 3428 | /* Sign extend hi32 before calling load_register, because we can |
| 3429 | generally get better code when we load a sign extended value. */ |
| 3430 | if ((hi32.X_add_number & 0x80000000) != 0) |
| 3431 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
| 3432 | load_register (counter, reg, &hi32, 0); |
| 3433 | freg = reg; |
| 3434 | } |
| 3435 | if ((lo32.X_add_number & 0xffff0000) == 0) |
| 3436 | { |
| 3437 | if (freg != 0) |
| 3438 | { |
| 3439 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
| 3440 | "dsll32", "d,w,<", reg, freg, 0); |
| 3441 | freg = reg; |
| 3442 | } |
| 3443 | } |
| 3444 | else |
| 3445 | { |
| 3446 | expressionS mid16; |
| 3447 | |
| 3448 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
| 3449 | { |
| 3450 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, |
| 3451 | (int) BFD_RELOC_HI16); |
| 3452 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
| 3453 | "dsrl32", "d,w,<", reg, reg, 0); |
| 3454 | return; |
| 3455 | } |
| 3456 | |
| 3457 | if (freg != 0) |
| 3458 | { |
| 3459 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll", |
| 3460 | "d,w,<", reg, freg, 16); |
| 3461 | freg = reg; |
| 3462 | } |
| 3463 | mid16 = lo32; |
| 3464 | mid16.X_add_number >>= 16; |
| 3465 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, |
| 3466 | freg, (int) BFD_RELOC_LO16); |
| 3467 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll", |
| 3468 | "d,w,<", reg, reg, 16); |
| 3469 | freg = reg; |
| 3470 | } |
| 3471 | if ((lo32.X_add_number & 0xffff) != 0) |
| 3472 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
| 3473 | (int) BFD_RELOC_LO16); |
| 3474 | } |
| 3475 | |
| 3476 | /* Load an address into a register. */ |
| 3477 | |
| 3478 | static void |
| 3479 | load_address (counter, reg, ep, used_at) |
| 3480 | int *counter; |
| 3481 | int reg; |
| 3482 | expressionS *ep; |
| 3483 | int *used_at; |
| 3484 | { |
| 3485 | char *p = NULL; |
| 3486 | |
| 3487 | if (ep->X_op != O_constant |
| 3488 | && ep->X_op != O_symbol) |
| 3489 | { |
| 3490 | as_bad (_("expression too complex")); |
| 3491 | ep->X_op = O_constant; |
| 3492 | } |
| 3493 | |
| 3494 | if (ep->X_op == O_constant) |
| 3495 | { |
| 3496 | load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES); |
| 3497 | return; |
| 3498 | } |
| 3499 | |
| 3500 | if (mips_pic == NO_PIC) |
| 3501 | { |
| 3502 | /* If this is a reference to a GP relative symbol, we want |
| 3503 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
| 3504 | Otherwise we want |
| 3505 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
| 3506 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
| 3507 | If we have an addend, we always use the latter form. |
| 3508 | |
| 3509 | With 64bit address space and a usable $at we want |
| 3510 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) |
| 3511 | lui $at,<sym> (BFD_RELOC_HI16_S) |
| 3512 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) |
| 3513 | daddiu $at,<sym> (BFD_RELOC_LO16) |
| 3514 | dsll32 $reg,0 |
| 3515 | daddu $reg,$reg,$at |
| 3516 | |
| 3517 | If $at is already in use, we use an path which is suboptimal |
| 3518 | on superscalar processors. |
| 3519 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) |
| 3520 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) |
| 3521 | dsll $reg,16 |
| 3522 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) |
| 3523 | dsll $reg,16 |
| 3524 | daddiu $reg,<sym> (BFD_RELOC_LO16) |
| 3525 | */ |
| 3526 | if (HAVE_64BIT_ADDRESSES) |
| 3527 | { |
| 3528 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
| 3529 | hold the data for such large chunks. */ |
| 3530 | |
| 3531 | if (*used_at == 0 && ! mips_opts.noat) |
| 3532 | { |
| 3533 | macro_build (p, counter, ep, "lui", "t,u", |
| 3534 | reg, (int) BFD_RELOC_MIPS_HIGHEST); |
| 3535 | macro_build (p, counter, ep, "lui", "t,u", |
| 3536 | AT, (int) BFD_RELOC_HI16_S); |
| 3537 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
| 3538 | reg, reg, (int) BFD_RELOC_MIPS_HIGHER); |
| 3539 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
| 3540 | AT, AT, (int) BFD_RELOC_LO16); |
| 3541 | macro_build (p, counter, (expressionS *) NULL, "dsll32", |
| 3542 | "d,w,<", reg, reg, 0); |
| 3543 | macro_build (p, counter, (expressionS *) NULL, "daddu", |
| 3544 | "d,v,t", reg, reg, AT); |
| 3545 | *used_at = 1; |
| 3546 | } |
| 3547 | else |
| 3548 | { |
| 3549 | macro_build (p, counter, ep, "lui", "t,u", |
| 3550 | reg, (int) BFD_RELOC_MIPS_HIGHEST); |
| 3551 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
| 3552 | reg, reg, (int) BFD_RELOC_MIPS_HIGHER); |
| 3553 | macro_build (p, counter, (expressionS *) NULL, "dsll", |
| 3554 | "d,w,<", reg, reg, 16); |
| 3555 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
| 3556 | reg, reg, (int) BFD_RELOC_HI16_S); |
| 3557 | macro_build (p, counter, (expressionS *) NULL, "dsll", |
| 3558 | "d,w,<", reg, reg, 16); |
| 3559 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
| 3560 | reg, reg, (int) BFD_RELOC_LO16); |
| 3561 | } |
| 3562 | } |
| 3563 | else |
| 3564 | { |
| 3565 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
| 3566 | && ! nopic_need_relax (ep->X_add_symbol, 1)) |
| 3567 | { |
| 3568 | frag_grow (20); |
| 3569 | macro_build ((char *) NULL, counter, ep, |
| 3570 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", |
| 3571 | reg, mips_gp_register, (int) BFD_RELOC_GPREL16); |
| 3572 | p = frag_var (rs_machine_dependent, 8, 0, |
| 3573 | RELAX_ENCODE (4, 8, 0, 4, 0, |
| 3574 | mips_opts.warn_about_macros), |
| 3575 | ep->X_add_symbol, 0, NULL); |
| 3576 | } |
| 3577 | macro_build_lui (p, counter, ep, reg); |
| 3578 | if (p != NULL) |
| 3579 | p += 4; |
| 3580 | macro_build (p, counter, ep, |
| 3581 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 3582 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
| 3583 | } |
| 3584 | } |
| 3585 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
| 3586 | { |
| 3587 | expressionS ex; |
| 3588 | |
| 3589 | /* If this is a reference to an external symbol, we want |
| 3590 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 3591 | Otherwise we want |
| 3592 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 3593 | nop |
| 3594 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
| 3595 | If there is a constant, it must be added in after. */ |
| 3596 | ex.X_add_number = ep->X_add_number; |
| 3597 | ep->X_add_number = 0; |
| 3598 | frag_grow (20); |
| 3599 | macro_build ((char *) NULL, counter, ep, |
| 3600 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", |
| 3601 | reg, (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); |
| 3602 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); |
| 3603 | p = frag_var (rs_machine_dependent, 4, 0, |
| 3604 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), |
| 3605 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
| 3606 | macro_build (p, counter, ep, |
| 3607 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 3608 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
| 3609 | if (ex.X_add_number != 0) |
| 3610 | { |
| 3611 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
| 3612 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
| 3613 | ex.X_op = O_constant; |
| 3614 | macro_build ((char *) NULL, counter, &ex, |
| 3615 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 3616 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
| 3617 | } |
| 3618 | } |
| 3619 | else if (mips_pic == SVR4_PIC) |
| 3620 | { |
| 3621 | expressionS ex; |
| 3622 | int off; |
| 3623 | |
| 3624 | /* This is the large GOT case. If this is a reference to an |
| 3625 | external symbol, we want |
| 3626 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) |
| 3627 | addu $reg,$reg,$gp |
| 3628 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) |
| 3629 | Otherwise, for a reference to a local symbol, we want |
| 3630 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 3631 | nop |
| 3632 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
| 3633 | If we have NewABI, we want |
| 3634 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
| 3635 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) |
| 3636 | If there is a constant, it must be added in after. */ |
| 3637 | ex.X_add_number = ep->X_add_number; |
| 3638 | ep->X_add_number = 0; |
| 3639 | if (HAVE_NEWABI) |
| 3640 | { |
| 3641 | macro_build ((char *) NULL, counter, ep, |
| 3642 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg, |
| 3643 | (int) BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
| 3644 | macro_build (p, counter, ep, |
| 3645 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", |
| 3646 | reg, reg, (int) BFD_RELOC_MIPS_GOT_OFST); |
| 3647 | } |
| 3648 | else |
| 3649 | { |
| 3650 | if (reg_needs_delay (mips_gp_register)) |
| 3651 | off = 4; |
| 3652 | else |
| 3653 | off = 0; |
| 3654 | frag_grow (32); |
| 3655 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, |
| 3656 | (int) BFD_RELOC_MIPS_GOT_HI16); |
| 3657 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
| 3658 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", "d,v,t", reg, |
| 3659 | reg, mips_gp_register); |
| 3660 | macro_build ((char *) NULL, counter, ep, |
| 3661 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 3662 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); |
| 3663 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
| 3664 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, |
| 3665 | mips_opts.warn_about_macros), |
| 3666 | ep->X_add_symbol, 0, NULL); |
| 3667 | if (off > 0) |
| 3668 | { |
| 3669 | /* We need a nop before loading from $gp. This special |
| 3670 | check is required because the lui which starts the main |
| 3671 | instruction stream does not refer to $gp, and so will not |
| 3672 | insert the nop which may be required. */ |
| 3673 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); |
| 3674 | p += 4; |
| 3675 | } |
| 3676 | macro_build (p, counter, ep, |
| 3677 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg, |
| 3678 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); |
| 3679 | p += 4; |
| 3680 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); |
| 3681 | p += 4; |
| 3682 | macro_build (p, counter, ep, |
| 3683 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 3684 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
| 3685 | } |
| 3686 | |
| 3687 | if (ex.X_add_number != 0) |
| 3688 | { |
| 3689 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
| 3690 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
| 3691 | ex.X_op = O_constant; |
| 3692 | macro_build ((char *) NULL, counter, &ex, |
| 3693 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 3694 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
| 3695 | } |
| 3696 | } |
| 3697 | else if (mips_pic == EMBEDDED_PIC) |
| 3698 | { |
| 3699 | /* We always do |
| 3700 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
| 3701 | */ |
| 3702 | macro_build ((char *) NULL, counter, ep, |
| 3703 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 3704 | "t,r,j", reg, mips_gp_register, (int) BFD_RELOC_GPREL16); |
| 3705 | } |
| 3706 | else |
| 3707 | abort (); |
| 3708 | } |
| 3709 | |
| 3710 | /* Move the contents of register SOURCE into register DEST. */ |
| 3711 | |
| 3712 | static void |
| 3713 | move_register (counter, dest, source) |
| 3714 | int *counter; |
| 3715 | int dest; |
| 3716 | int source; |
| 3717 | { |
| 3718 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
| 3719 | HAVE_32BIT_GPRS ? "addu" : "daddu", |
| 3720 | "d,v,t", dest, source, 0); |
| 3721 | } |
| 3722 | |
| 3723 | /* |
| 3724 | * Build macros |
| 3725 | * This routine implements the seemingly endless macro or synthesized |
| 3726 | * instructions and addressing modes in the mips assembly language. Many |
| 3727 | * of these macros are simple and are similar to each other. These could |
| 3728 | * probably be handled by some kind of table or grammer aproach instead of |
| 3729 | * this verbose method. Others are not simple macros but are more like |
| 3730 | * optimizing code generation. |
| 3731 | * One interesting optimization is when several store macros appear |
| 3732 | * consecutivly that would load AT with the upper half of the same address. |
| 3733 | * The ensuing load upper instructions are ommited. This implies some kind |
| 3734 | * of global optimization. We currently only optimize within a single macro. |
| 3735 | * For many of the load and store macros if the address is specified as a |
| 3736 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we |
| 3737 | * first load register 'at' with zero and use it as the base register. The |
| 3738 | * mips assembler simply uses register $zero. Just one tiny optimization |
| 3739 | * we're missing. |
| 3740 | */ |
| 3741 | static void |
| 3742 | macro (ip) |
| 3743 | struct mips_cl_insn *ip; |
| 3744 | { |
| 3745 | register int treg, sreg, dreg, breg; |
| 3746 | int tempreg; |
| 3747 | int mask; |
| 3748 | int icnt = 0; |
| 3749 | int used_at = 0; |
| 3750 | expressionS expr1; |
| 3751 | const char *s; |
| 3752 | const char *s2; |
| 3753 | const char *fmt; |
| 3754 | int likely = 0; |
| 3755 | int dbl = 0; |
| 3756 | int coproc = 0; |
| 3757 | int lr = 0; |
| 3758 | int imm = 0; |
| 3759 | offsetT maxnum; |
| 3760 | int off; |
| 3761 | bfd_reloc_code_real_type r; |
| 3762 | int hold_mips_optimize; |
| 3763 | |
| 3764 | assert (! mips_opts.mips16); |
| 3765 | |
| 3766 | treg = (ip->insn_opcode >> 16) & 0x1f; |
| 3767 | dreg = (ip->insn_opcode >> 11) & 0x1f; |
| 3768 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; |
| 3769 | mask = ip->insn_mo->mask; |
| 3770 | |
| 3771 | expr1.X_op = O_constant; |
| 3772 | expr1.X_op_symbol = NULL; |
| 3773 | expr1.X_add_symbol = NULL; |
| 3774 | expr1.X_add_number = 1; |
| 3775 | |
| 3776 | switch (mask) |
| 3777 | { |
| 3778 | case M_DABS: |
| 3779 | dbl = 1; |
| 3780 | case M_ABS: |
| 3781 | /* bgez $a0,.+12 |
| 3782 | move v0,$a0 |
| 3783 | sub v0,$zero,$a0 |
| 3784 | */ |
| 3785 | |
| 3786 | mips_emit_delays (true); |
| 3787 | ++mips_opts.noreorder; |
| 3788 | mips_any_noreorder = 1; |
| 3789 | |
| 3790 | expr1.X_add_number = 8; |
| 3791 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
| 3792 | if (dreg == sreg) |
| 3793 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
| 3794 | 0); |
| 3795 | else |
| 3796 | move_register (&icnt, dreg, sreg); |
| 3797 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 3798 | dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); |
| 3799 | |
| 3800 | --mips_opts.noreorder; |
| 3801 | return; |
| 3802 | |
| 3803 | case M_ADD_I: |
| 3804 | s = "addi"; |
| 3805 | s2 = "add"; |
| 3806 | goto do_addi; |
| 3807 | case M_ADDU_I: |
| 3808 | s = "addiu"; |
| 3809 | s2 = "addu"; |
| 3810 | goto do_addi; |
| 3811 | case M_DADD_I: |
| 3812 | dbl = 1; |
| 3813 | s = "daddi"; |
| 3814 | s2 = "dadd"; |
| 3815 | goto do_addi; |
| 3816 | case M_DADDU_I: |
| 3817 | dbl = 1; |
| 3818 | s = "daddiu"; |
| 3819 | s2 = "daddu"; |
| 3820 | do_addi: |
| 3821 | if (imm_expr.X_op == O_constant |
| 3822 | && imm_expr.X_add_number >= -0x8000 |
| 3823 | && imm_expr.X_add_number < 0x8000) |
| 3824 | { |
| 3825 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
| 3826 | (int) BFD_RELOC_LO16); |
| 3827 | return; |
| 3828 | } |
| 3829 | load_register (&icnt, AT, &imm_expr, dbl); |
| 3830 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t", |
| 3831 | treg, sreg, AT); |
| 3832 | break; |
| 3833 | |
| 3834 | case M_AND_I: |
| 3835 | s = "andi"; |
| 3836 | s2 = "and"; |
| 3837 | goto do_bit; |
| 3838 | case M_OR_I: |
| 3839 | s = "ori"; |
| 3840 | s2 = "or"; |
| 3841 | goto do_bit; |
| 3842 | case M_NOR_I: |
| 3843 | s = ""; |
| 3844 | s2 = "nor"; |
| 3845 | goto do_bit; |
| 3846 | case M_XOR_I: |
| 3847 | s = "xori"; |
| 3848 | s2 = "xor"; |
| 3849 | do_bit: |
| 3850 | if (imm_expr.X_op == O_constant |
| 3851 | && imm_expr.X_add_number >= 0 |
| 3852 | && imm_expr.X_add_number < 0x10000) |
| 3853 | { |
| 3854 | if (mask != M_NOR_I) |
| 3855 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
| 3856 | sreg, (int) BFD_RELOC_LO16); |
| 3857 | else |
| 3858 | { |
| 3859 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
| 3860 | treg, sreg, (int) BFD_RELOC_LO16); |
| 3861 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nor", |
| 3862 | "d,v,t", treg, treg, 0); |
| 3863 | } |
| 3864 | return; |
| 3865 | } |
| 3866 | |
| 3867 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
| 3868 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t", |
| 3869 | treg, sreg, AT); |
| 3870 | break; |
| 3871 | |
| 3872 | case M_BEQ_I: |
| 3873 | s = "beq"; |
| 3874 | goto beq_i; |
| 3875 | case M_BEQL_I: |
| 3876 | s = "beql"; |
| 3877 | likely = 1; |
| 3878 | goto beq_i; |
| 3879 | case M_BNE_I: |
| 3880 | s = "bne"; |
| 3881 | goto beq_i; |
| 3882 | case M_BNEL_I: |
| 3883 | s = "bnel"; |
| 3884 | likely = 1; |
| 3885 | beq_i: |
| 3886 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
| 3887 | { |
| 3888 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
| 3889 | 0); |
| 3890 | return; |
| 3891 | } |
| 3892 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
| 3893 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
| 3894 | break; |
| 3895 | |
| 3896 | case M_BGEL: |
| 3897 | likely = 1; |
| 3898 | case M_BGE: |
| 3899 | if (treg == 0) |
| 3900 | { |
| 3901 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3902 | likely ? "bgezl" : "bgez", "s,p", sreg); |
| 3903 | return; |
| 3904 | } |
| 3905 | if (sreg == 0) |
| 3906 | { |
| 3907 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3908 | likely ? "blezl" : "blez", "s,p", treg); |
| 3909 | return; |
| 3910 | } |
| 3911 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
| 3912 | AT, sreg, treg); |
| 3913 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3914 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
| 3915 | break; |
| 3916 | |
| 3917 | case M_BGTL_I: |
| 3918 | likely = 1; |
| 3919 | case M_BGT_I: |
| 3920 | /* check for > max integer */ |
| 3921 | maxnum = 0x7fffffff; |
| 3922 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
| 3923 | { |
| 3924 | maxnum <<= 16; |
| 3925 | maxnum |= 0xffff; |
| 3926 | maxnum <<= 16; |
| 3927 | maxnum |= 0xffff; |
| 3928 | } |
| 3929 | if (imm_expr.X_op == O_constant |
| 3930 | && imm_expr.X_add_number >= maxnum |
| 3931 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
| 3932 | { |
| 3933 | do_false: |
| 3934 | /* result is always false */ |
| 3935 | if (! likely) |
| 3936 | { |
| 3937 | if (warn_nops) |
| 3938 | as_warn (_("Branch %s is always false (nop)"), |
| 3939 | ip->insn_mo->name); |
| 3940 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", |
| 3941 | "", 0); |
| 3942 | } |
| 3943 | else |
| 3944 | { |
| 3945 | if (warn_nops) |
| 3946 | as_warn (_("Branch likely %s is always false"), |
| 3947 | ip->insn_mo->name); |
| 3948 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
| 3949 | "s,t,p", 0, 0); |
| 3950 | } |
| 3951 | return; |
| 3952 | } |
| 3953 | if (imm_expr.X_op != O_constant) |
| 3954 | as_bad (_("Unsupported large constant")); |
| 3955 | ++imm_expr.X_add_number; |
| 3956 | /* FALLTHROUGH */ |
| 3957 | case M_BGE_I: |
| 3958 | case M_BGEL_I: |
| 3959 | if (mask == M_BGEL_I) |
| 3960 | likely = 1; |
| 3961 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
| 3962 | { |
| 3963 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3964 | likely ? "bgezl" : "bgez", "s,p", sreg); |
| 3965 | return; |
| 3966 | } |
| 3967 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
| 3968 | { |
| 3969 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3970 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
| 3971 | return; |
| 3972 | } |
| 3973 | maxnum = 0x7fffffff; |
| 3974 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
| 3975 | { |
| 3976 | maxnum <<= 16; |
| 3977 | maxnum |= 0xffff; |
| 3978 | maxnum <<= 16; |
| 3979 | maxnum |= 0xffff; |
| 3980 | } |
| 3981 | maxnum = - maxnum - 1; |
| 3982 | if (imm_expr.X_op == O_constant |
| 3983 | && imm_expr.X_add_number <= maxnum |
| 3984 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
| 3985 | { |
| 3986 | do_true: |
| 3987 | /* result is always true */ |
| 3988 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); |
| 3989 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
| 3990 | return; |
| 3991 | } |
| 3992 | set_at (&icnt, sreg, 0); |
| 3993 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3994 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
| 3995 | break; |
| 3996 | |
| 3997 | case M_BGEUL: |
| 3998 | likely = 1; |
| 3999 | case M_BGEU: |
| 4000 | if (treg == 0) |
| 4001 | goto do_true; |
| 4002 | if (sreg == 0) |
| 4003 | { |
| 4004 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4005 | likely ? "beql" : "beq", "s,t,p", 0, treg); |
| 4006 | return; |
| 4007 | } |
| 4008 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
| 4009 | "d,v,t", AT, sreg, treg); |
| 4010 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4011 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
| 4012 | break; |
| 4013 | |
| 4014 | case M_BGTUL_I: |
| 4015 | likely = 1; |
| 4016 | case M_BGTU_I: |
| 4017 | if (sreg == 0 |
| 4018 | || (HAVE_32BIT_GPRS |
| 4019 | && imm_expr.X_op == O_constant |
| 4020 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
| 4021 | goto do_false; |
| 4022 | if (imm_expr.X_op != O_constant) |
| 4023 | as_bad (_("Unsupported large constant")); |
| 4024 | ++imm_expr.X_add_number; |
| 4025 | /* FALLTHROUGH */ |
| 4026 | case M_BGEU_I: |
| 4027 | case M_BGEUL_I: |
| 4028 | if (mask == M_BGEUL_I) |
| 4029 | likely = 1; |
| 4030 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
| 4031 | goto do_true; |
| 4032 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
| 4033 | { |
| 4034 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4035 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
| 4036 | return; |
| 4037 | } |
| 4038 | set_at (&icnt, sreg, 1); |
| 4039 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4040 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
| 4041 | break; |
| 4042 | |
| 4043 | case M_BGTL: |
| 4044 | likely = 1; |
| 4045 | case M_BGT: |
| 4046 | if (treg == 0) |
| 4047 | { |
| 4048 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4049 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
| 4050 | return; |
| 4051 | } |
| 4052 | if (sreg == 0) |
| 4053 | { |
| 4054 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4055 | likely ? "bltzl" : "bltz", "s,p", treg); |
| 4056 | return; |
| 4057 | } |
| 4058 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
| 4059 | AT, treg, sreg); |
| 4060 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4061 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
| 4062 | break; |
| 4063 | |
| 4064 | case M_BGTUL: |
| 4065 | likely = 1; |
| 4066 | case M_BGTU: |
| 4067 | if (treg == 0) |
| 4068 | { |
| 4069 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4070 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
| 4071 | return; |
| 4072 | } |
| 4073 | if (sreg == 0) |
| 4074 | goto do_false; |
| 4075 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
| 4076 | "d,v,t", AT, treg, sreg); |
| 4077 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4078 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
| 4079 | break; |
| 4080 | |
| 4081 | case M_BLEL: |
| 4082 | likely = 1; |
| 4083 | case M_BLE: |
| 4084 | if (treg == 0) |
| 4085 | { |
| 4086 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4087 | likely ? "blezl" : "blez", "s,p", sreg); |
| 4088 | return; |
| 4089 | } |
| 4090 | if (sreg == 0) |
| 4091 | { |
| 4092 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4093 | likely ? "bgezl" : "bgez", "s,p", treg); |
| 4094 | return; |
| 4095 | } |
| 4096 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
| 4097 | AT, treg, sreg); |
| 4098 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4099 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
| 4100 | break; |
| 4101 | |
| 4102 | case M_BLEL_I: |
| 4103 | likely = 1; |
| 4104 | case M_BLE_I: |
| 4105 | maxnum = 0x7fffffff; |
| 4106 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
| 4107 | { |
| 4108 | maxnum <<= 16; |
| 4109 | maxnum |= 0xffff; |
| 4110 | maxnum <<= 16; |
| 4111 | maxnum |= 0xffff; |
| 4112 | } |
| 4113 | if (imm_expr.X_op == O_constant |
| 4114 | && imm_expr.X_add_number >= maxnum |
| 4115 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
| 4116 | goto do_true; |
| 4117 | if (imm_expr.X_op != O_constant) |
| 4118 | as_bad (_("Unsupported large constant")); |
| 4119 | ++imm_expr.X_add_number; |
| 4120 | /* FALLTHROUGH */ |
| 4121 | case M_BLT_I: |
| 4122 | case M_BLTL_I: |
| 4123 | if (mask == M_BLTL_I) |
| 4124 | likely = 1; |
| 4125 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
| 4126 | { |
| 4127 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4128 | likely ? "bltzl" : "bltz", "s,p", sreg); |
| 4129 | return; |
| 4130 | } |
| 4131 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
| 4132 | { |
| 4133 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4134 | likely ? "blezl" : "blez", "s,p", sreg); |
| 4135 | return; |
| 4136 | } |
| 4137 | set_at (&icnt, sreg, 0); |
| 4138 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4139 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
| 4140 | break; |
| 4141 | |
| 4142 | case M_BLEUL: |
| 4143 | likely = 1; |
| 4144 | case M_BLEU: |
| 4145 | if (treg == 0) |
| 4146 | { |
| 4147 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4148 | likely ? "beql" : "beq", "s,t,p", sreg, 0); |
| 4149 | return; |
| 4150 | } |
| 4151 | if (sreg == 0) |
| 4152 | goto do_true; |
| 4153 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
| 4154 | "d,v,t", AT, treg, sreg); |
| 4155 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4156 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
| 4157 | break; |
| 4158 | |
| 4159 | case M_BLEUL_I: |
| 4160 | likely = 1; |
| 4161 | case M_BLEU_I: |
| 4162 | if (sreg == 0 |
| 4163 | || (HAVE_32BIT_GPRS |
| 4164 | && imm_expr.X_op == O_constant |
| 4165 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
| 4166 | goto do_true; |
| 4167 | if (imm_expr.X_op != O_constant) |
| 4168 | as_bad (_("Unsupported large constant")); |
| 4169 | ++imm_expr.X_add_number; |
| 4170 | /* FALLTHROUGH */ |
| 4171 | case M_BLTU_I: |
| 4172 | case M_BLTUL_I: |
| 4173 | if (mask == M_BLTUL_I) |
| 4174 | likely = 1; |
| 4175 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
| 4176 | goto do_false; |
| 4177 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
| 4178 | { |
| 4179 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4180 | likely ? "beql" : "beq", |
| 4181 | "s,t,p", sreg, 0); |
| 4182 | return; |
| 4183 | } |
| 4184 | set_at (&icnt, sreg, 1); |
| 4185 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4186 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
| 4187 | break; |
| 4188 | |
| 4189 | case M_BLTL: |
| 4190 | likely = 1; |
| 4191 | case M_BLT: |
| 4192 | if (treg == 0) |
| 4193 | { |
| 4194 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4195 | likely ? "bltzl" : "bltz", "s,p", sreg); |
| 4196 | return; |
| 4197 | } |
| 4198 | if (sreg == 0) |
| 4199 | { |
| 4200 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4201 | likely ? "bgtzl" : "bgtz", "s,p", treg); |
| 4202 | return; |
| 4203 | } |
| 4204 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
| 4205 | AT, sreg, treg); |
| 4206 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4207 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
| 4208 | break; |
| 4209 | |
| 4210 | case M_BLTUL: |
| 4211 | likely = 1; |
| 4212 | case M_BLTU: |
| 4213 | if (treg == 0) |
| 4214 | goto do_false; |
| 4215 | if (sreg == 0) |
| 4216 | { |
| 4217 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4218 | likely ? "bnel" : "bne", "s,t,p", 0, treg); |
| 4219 | return; |
| 4220 | } |
| 4221 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
| 4222 | "d,v,t", AT, sreg, |
| 4223 | treg); |
| 4224 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4225 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
| 4226 | break; |
| 4227 | |
| 4228 | case M_DDIV_3: |
| 4229 | dbl = 1; |
| 4230 | case M_DIV_3: |
| 4231 | s = "mflo"; |
| 4232 | goto do_div3; |
| 4233 | case M_DREM_3: |
| 4234 | dbl = 1; |
| 4235 | case M_REM_3: |
| 4236 | s = "mfhi"; |
| 4237 | do_div3: |
| 4238 | if (treg == 0) |
| 4239 | { |
| 4240 | as_warn (_("Divide by zero.")); |
| 4241 | if (mips_trap) |
| 4242 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
| 4243 | "s,t,q", 0, 0, 7); |
| 4244 | else |
| 4245 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
| 4246 | "c", 7); |
| 4247 | return; |
| 4248 | } |
| 4249 | |
| 4250 | mips_emit_delays (true); |
| 4251 | ++mips_opts.noreorder; |
| 4252 | mips_any_noreorder = 1; |
| 4253 | if (mips_trap) |
| 4254 | { |
| 4255 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
| 4256 | "s,t,q", treg, 0, 7); |
| 4257 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4258 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
| 4259 | } |
| 4260 | else |
| 4261 | { |
| 4262 | expr1.X_add_number = 8; |
| 4263 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); |
| 4264 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4265 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
| 4266 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
| 4267 | "c", 7); |
| 4268 | } |
| 4269 | expr1.X_add_number = -1; |
| 4270 | macro_build ((char *) NULL, &icnt, &expr1, |
| 4271 | dbl ? "daddiu" : "addiu", |
| 4272 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
| 4273 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
| 4274 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
| 4275 | if (dbl) |
| 4276 | { |
| 4277 | expr1.X_add_number = 1; |
| 4278 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
| 4279 | (int) BFD_RELOC_LO16); |
| 4280 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsll32", |
| 4281 | "d,w,<", AT, AT, 31); |
| 4282 | } |
| 4283 | else |
| 4284 | { |
| 4285 | expr1.X_add_number = 0x80000000; |
| 4286 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
| 4287 | (int) BFD_RELOC_HI16); |
| 4288 | } |
| 4289 | if (mips_trap) |
| 4290 | { |
| 4291 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
| 4292 | "s,t,q", sreg, AT, 6); |
| 4293 | /* We want to close the noreorder block as soon as possible, so |
| 4294 | that later insns are available for delay slot filling. */ |
| 4295 | --mips_opts.noreorder; |
| 4296 | } |
| 4297 | else |
| 4298 | { |
| 4299 | expr1.X_add_number = 8; |
| 4300 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); |
| 4301 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
| 4302 | 0); |
| 4303 | |
| 4304 | /* We want to close the noreorder block as soon as possible, so |
| 4305 | that later insns are available for delay slot filling. */ |
| 4306 | --mips_opts.noreorder; |
| 4307 | |
| 4308 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
| 4309 | "c", 6); |
| 4310 | } |
| 4311 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d", dreg); |
| 4312 | break; |
| 4313 | |
| 4314 | case M_DIV_3I: |
| 4315 | s = "div"; |
| 4316 | s2 = "mflo"; |
| 4317 | goto do_divi; |
| 4318 | case M_DIVU_3I: |
| 4319 | s = "divu"; |
| 4320 | s2 = "mflo"; |
| 4321 | goto do_divi; |
| 4322 | case M_REM_3I: |
| 4323 | s = "div"; |
| 4324 | s2 = "mfhi"; |
| 4325 | goto do_divi; |
| 4326 | case M_REMU_3I: |
| 4327 | s = "divu"; |
| 4328 | s2 = "mfhi"; |
| 4329 | goto do_divi; |
| 4330 | case M_DDIV_3I: |
| 4331 | dbl = 1; |
| 4332 | s = "ddiv"; |
| 4333 | s2 = "mflo"; |
| 4334 | goto do_divi; |
| 4335 | case M_DDIVU_3I: |
| 4336 | dbl = 1; |
| 4337 | s = "ddivu"; |
| 4338 | s2 = "mflo"; |
| 4339 | goto do_divi; |
| 4340 | case M_DREM_3I: |
| 4341 | dbl = 1; |
| 4342 | s = "ddiv"; |
| 4343 | s2 = "mfhi"; |
| 4344 | goto do_divi; |
| 4345 | case M_DREMU_3I: |
| 4346 | dbl = 1; |
| 4347 | s = "ddivu"; |
| 4348 | s2 = "mfhi"; |
| 4349 | do_divi: |
| 4350 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
| 4351 | { |
| 4352 | as_warn (_("Divide by zero.")); |
| 4353 | if (mips_trap) |
| 4354 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
| 4355 | "s,t,q", 0, 0, 7); |
| 4356 | else |
| 4357 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
| 4358 | "c", 7); |
| 4359 | return; |
| 4360 | } |
| 4361 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
| 4362 | { |
| 4363 | if (strcmp (s2, "mflo") == 0) |
| 4364 | move_register (&icnt, dreg, sreg); |
| 4365 | else |
| 4366 | move_register (&icnt, dreg, 0); |
| 4367 | return; |
| 4368 | } |
| 4369 | if (imm_expr.X_op == O_constant |
| 4370 | && imm_expr.X_add_number == -1 |
| 4371 | && s[strlen (s) - 1] != 'u') |
| 4372 | { |
| 4373 | if (strcmp (s2, "mflo") == 0) |
| 4374 | { |
| 4375 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4376 | dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
| 4377 | } |
| 4378 | else |
| 4379 | move_register (&icnt, dreg, 0); |
| 4380 | return; |
| 4381 | } |
| 4382 | |
| 4383 | load_register (&icnt, AT, &imm_expr, dbl); |
| 4384 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
| 4385 | sreg, AT); |
| 4386 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg); |
| 4387 | break; |
| 4388 | |
| 4389 | case M_DIVU_3: |
| 4390 | s = "divu"; |
| 4391 | s2 = "mflo"; |
| 4392 | goto do_divu3; |
| 4393 | case M_REMU_3: |
| 4394 | s = "divu"; |
| 4395 | s2 = "mfhi"; |
| 4396 | goto do_divu3; |
| 4397 | case M_DDIVU_3: |
| 4398 | s = "ddivu"; |
| 4399 | s2 = "mflo"; |
| 4400 | goto do_divu3; |
| 4401 | case M_DREMU_3: |
| 4402 | s = "ddivu"; |
| 4403 | s2 = "mfhi"; |
| 4404 | do_divu3: |
| 4405 | mips_emit_delays (true); |
| 4406 | ++mips_opts.noreorder; |
| 4407 | mips_any_noreorder = 1; |
| 4408 | if (mips_trap) |
| 4409 | { |
| 4410 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
| 4411 | "s,t,q", treg, 0, 7); |
| 4412 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
| 4413 | sreg, treg); |
| 4414 | /* We want to close the noreorder block as soon as possible, so |
| 4415 | that later insns are available for delay slot filling. */ |
| 4416 | --mips_opts.noreorder; |
| 4417 | } |
| 4418 | else |
| 4419 | { |
| 4420 | expr1.X_add_number = 8; |
| 4421 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); |
| 4422 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
| 4423 | sreg, treg); |
| 4424 | |
| 4425 | /* We want to close the noreorder block as soon as possible, so |
| 4426 | that later insns are available for delay slot filling. */ |
| 4427 | --mips_opts.noreorder; |
| 4428 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
| 4429 | "c", 7); |
| 4430 | } |
| 4431 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg); |
| 4432 | return; |
| 4433 | |
| 4434 | case M_DLA_AB: |
| 4435 | dbl = 1; |
| 4436 | case M_LA_AB: |
| 4437 | /* Load the address of a symbol into a register. If breg is not |
| 4438 | zero, we then add a base register to it. */ |
| 4439 | |
| 4440 | if (dbl && HAVE_32BIT_GPRS) |
| 4441 | as_warn (_("dla used to load 32-bit register")); |
| 4442 | |
| 4443 | if (! dbl && HAVE_64BIT_OBJECTS) |
| 4444 | as_warn (_("la used to load 64-bit address")); |
| 4445 | |
| 4446 | if (treg == breg) |
| 4447 | { |
| 4448 | tempreg = AT; |
| 4449 | used_at = 1; |
| 4450 | } |
| 4451 | else |
| 4452 | { |
| 4453 | tempreg = treg; |
| 4454 | used_at = 0; |
| 4455 | } |
| 4456 | |
| 4457 | /* When generating embedded PIC code, we permit expressions of |
| 4458 | the form |
| 4459 | la $treg,foo-bar |
| 4460 | la $treg,foo-bar($breg) |
| 4461 | where bar is an address in the current section. These are used |
| 4462 | when getting the addresses of functions. We don't permit |
| 4463 | X_add_number to be non-zero, because if the symbol is |
| 4464 | external the relaxing code needs to know that any addend is |
| 4465 | purely the offset to X_op_symbol. */ |
| 4466 | if (mips_pic == EMBEDDED_PIC |
| 4467 | && offset_expr.X_op == O_subtract |
| 4468 | && (symbol_constant_p (offset_expr.X_op_symbol) |
| 4469 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg |
| 4470 | : (symbol_equated_p (offset_expr.X_op_symbol) |
| 4471 | && (S_GET_SEGMENT |
| 4472 | (symbol_get_value_expression (offset_expr.X_op_symbol) |
| 4473 | ->X_add_symbol) |
| 4474 | == now_seg))) |
| 4475 | && (offset_expr.X_add_number == 0 |
| 4476 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) |
| 4477 | { |
| 4478 | if (breg == 0) |
| 4479 | { |
| 4480 | tempreg = treg; |
| 4481 | used_at = 0; |
| 4482 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", |
| 4483 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); |
| 4484 | } |
| 4485 | else |
| 4486 | { |
| 4487 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", |
| 4488 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); |
| 4489 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4490 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu", |
| 4491 | "d,v,t", tempreg, tempreg, breg); |
| 4492 | } |
| 4493 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4494 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
| 4495 | "t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16); |
| 4496 | if (! used_at) |
| 4497 | return; |
| 4498 | break; |
| 4499 | } |
| 4500 | |
| 4501 | if (offset_expr.X_op != O_symbol |
| 4502 | && offset_expr.X_op != O_constant) |
| 4503 | { |
| 4504 | as_bad (_("expression too complex")); |
| 4505 | offset_expr.X_op = O_constant; |
| 4506 | } |
| 4507 | |
| 4508 | if (offset_expr.X_op == O_constant) |
| 4509 | load_register (&icnt, tempreg, &offset_expr, |
| 4510 | ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) |
| 4511 | ? (dbl || HAVE_64BIT_ADDRESSES) |
| 4512 | : HAVE_64BIT_ADDRESSES)); |
| 4513 | else if (mips_pic == NO_PIC) |
| 4514 | { |
| 4515 | /* If this is a reference to a GP relative symbol, we want |
| 4516 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
| 4517 | Otherwise we want |
| 4518 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
| 4519 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) |
| 4520 | If we have a constant, we need two instructions anyhow, |
| 4521 | so we may as well always use the latter form. |
| 4522 | |
| 4523 | With 64bit address space and a usable $at we want |
| 4524 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) |
| 4525 | lui $at,<sym> (BFD_RELOC_HI16_S) |
| 4526 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) |
| 4527 | daddiu $at,<sym> (BFD_RELOC_LO16) |
| 4528 | dsll32 $tempreg,0 |
| 4529 | daddu $tempreg,$tempreg,$at |
| 4530 | |
| 4531 | If $at is already in use, we use an path which is suboptimal |
| 4532 | on superscalar processors. |
| 4533 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) |
| 4534 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) |
| 4535 | dsll $tempreg,16 |
| 4536 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) |
| 4537 | dsll $tempreg,16 |
| 4538 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) |
| 4539 | */ |
| 4540 | char *p = NULL; |
| 4541 | if (HAVE_64BIT_ADDRESSES) |
| 4542 | { |
| 4543 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
| 4544 | hold the data for such large chunks. */ |
| 4545 | |
| 4546 | if (used_at == 0 && ! mips_opts.noat) |
| 4547 | { |
| 4548 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", |
| 4549 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); |
| 4550 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", |
| 4551 | AT, (int) BFD_RELOC_HI16_S); |
| 4552 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
| 4553 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); |
| 4554 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
| 4555 | AT, AT, (int) BFD_RELOC_LO16); |
| 4556 | macro_build (p, &icnt, (expressionS *) NULL, "dsll32", |
| 4557 | "d,w,<", tempreg, tempreg, 0); |
| 4558 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
| 4559 | "d,v,t", tempreg, tempreg, AT); |
| 4560 | used_at = 1; |
| 4561 | } |
| 4562 | else |
| 4563 | { |
| 4564 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", |
| 4565 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); |
| 4566 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
| 4567 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); |
| 4568 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<", |
| 4569 | tempreg, tempreg, 16); |
| 4570 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
| 4571 | tempreg, tempreg, (int) BFD_RELOC_HI16_S); |
| 4572 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<", |
| 4573 | tempreg, tempreg, 16); |
| 4574 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
| 4575 | tempreg, tempreg, (int) BFD_RELOC_LO16); |
| 4576 | } |
| 4577 | } |
| 4578 | else |
| 4579 | { |
| 4580 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
| 4581 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) |
| 4582 | { |
| 4583 | frag_grow (20); |
| 4584 | macro_build ((char *) NULL, &icnt, &offset_expr, "addiu", |
| 4585 | "t,r,j", tempreg, mips_gp_register, |
| 4586 | (int) BFD_RELOC_GPREL16); |
| 4587 | p = frag_var (rs_machine_dependent, 8, 0, |
| 4588 | RELAX_ENCODE (4, 8, 0, 4, 0, |
| 4589 | mips_opts.warn_about_macros), |
| 4590 | offset_expr.X_add_symbol, 0, NULL); |
| 4591 | } |
| 4592 | macro_build_lui (p, &icnt, &offset_expr, tempreg); |
| 4593 | if (p != NULL) |
| 4594 | p += 4; |
| 4595 | macro_build (p, &icnt, &offset_expr, "addiu", |
| 4596 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
| 4597 | } |
| 4598 | } |
| 4599 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
| 4600 | { |
| 4601 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
| 4602 | |
| 4603 | /* If this is a reference to an external symbol, and there |
| 4604 | is no constant, we want |
| 4605 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 4606 | or if tempreg is PIC_CALL_REG |
| 4607 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
| 4608 | For a local symbol, we want |
| 4609 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 4610 | nop |
| 4611 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) |
| 4612 | |
| 4613 | If we have a small constant, and this is a reference to |
| 4614 | an external symbol, we want |
| 4615 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 4616 | nop |
| 4617 | addiu $tempreg,$tempreg,<constant> |
| 4618 | For a local symbol, we want the same instruction |
| 4619 | sequence, but we output a BFD_RELOC_LO16 reloc on the |
| 4620 | addiu instruction. |
| 4621 | |
| 4622 | If we have a large constant, and this is a reference to |
| 4623 | an external symbol, we want |
| 4624 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 4625 | lui $at,<hiconstant> |
| 4626 | addiu $at,$at,<loconstant> |
| 4627 | addu $tempreg,$tempreg,$at |
| 4628 | For a local symbol, we want the same instruction |
| 4629 | sequence, but we output a BFD_RELOC_LO16 reloc on the |
| 4630 | addiu instruction. */ |
| 4631 | expr1.X_add_number = offset_expr.X_add_number; |
| 4632 | offset_expr.X_add_number = 0; |
| 4633 | frag_grow (32); |
| 4634 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
| 4635 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
| 4636 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4637 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 4638 | "t,o(b)", tempreg, lw_reloc_type, mips_gp_register); |
| 4639 | if (expr1.X_add_number == 0) |
| 4640 | { |
| 4641 | int off; |
| 4642 | char *p; |
| 4643 | |
| 4644 | if (breg == 0) |
| 4645 | off = 0; |
| 4646 | else |
| 4647 | { |
| 4648 | /* We're going to put in an addu instruction using |
| 4649 | tempreg, so we may as well insert the nop right |
| 4650 | now. */ |
| 4651 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4652 | "nop", ""); |
| 4653 | off = 4; |
| 4654 | } |
| 4655 | p = frag_var (rs_machine_dependent, 8 - off, 0, |
| 4656 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, |
| 4657 | (breg == 0 |
| 4658 | ? mips_opts.warn_about_macros |
| 4659 | : 0)), |
| 4660 | offset_expr.X_add_symbol, 0, NULL); |
| 4661 | if (breg == 0) |
| 4662 | { |
| 4663 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
| 4664 | p += 4; |
| 4665 | } |
| 4666 | macro_build (p, &icnt, &expr1, |
| 4667 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 4668 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
| 4669 | /* FIXME: If breg == 0, and the next instruction uses |
| 4670 | $tempreg, then if this variant case is used an extra |
| 4671 | nop will be generated. */ |
| 4672 | } |
| 4673 | else if (expr1.X_add_number >= -0x8000 |
| 4674 | && expr1.X_add_number < 0x8000) |
| 4675 | { |
| 4676 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4677 | "nop", ""); |
| 4678 | macro_build ((char *) NULL, &icnt, &expr1, |
| 4679 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 4680 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
| 4681 | frag_var (rs_machine_dependent, 0, 0, |
| 4682 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), |
| 4683 | offset_expr.X_add_symbol, 0, NULL); |
| 4684 | } |
| 4685 | else |
| 4686 | { |
| 4687 | int off1; |
| 4688 | |
| 4689 | /* If we are going to add in a base register, and the |
| 4690 | target register and the base register are the same, |
| 4691 | then we are using AT as a temporary register. Since |
| 4692 | we want to load the constant into AT, we add our |
| 4693 | current AT (from the global offset table) and the |
| 4694 | register into the register now, and pretend we were |
| 4695 | not using a base register. */ |
| 4696 | if (breg != treg) |
| 4697 | off1 = 0; |
| 4698 | else |
| 4699 | { |
| 4700 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4701 | "nop", ""); |
| 4702 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4703 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 4704 | "d,v,t", treg, AT, breg); |
| 4705 | breg = 0; |
| 4706 | tempreg = treg; |
| 4707 | off1 = -8; |
| 4708 | } |
| 4709 | |
| 4710 | /* Set mips_optimize around the lui instruction to avoid |
| 4711 | inserting an unnecessary nop after the lw. */ |
| 4712 | hold_mips_optimize = mips_optimize; |
| 4713 | mips_optimize = 2; |
| 4714 | macro_build_lui (NULL, &icnt, &expr1, AT); |
| 4715 | mips_optimize = hold_mips_optimize; |
| 4716 | |
| 4717 | macro_build ((char *) NULL, &icnt, &expr1, |
| 4718 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 4719 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
| 4720 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4721 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 4722 | "d,v,t", tempreg, tempreg, AT); |
| 4723 | frag_var (rs_machine_dependent, 0, 0, |
| 4724 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), |
| 4725 | offset_expr.X_add_symbol, 0, NULL); |
| 4726 | used_at = 1; |
| 4727 | } |
| 4728 | } |
| 4729 | else if (mips_pic == SVR4_PIC) |
| 4730 | { |
| 4731 | int gpdel; |
| 4732 | char *p; |
| 4733 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
| 4734 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; |
| 4735 | |
| 4736 | /* This is the large GOT case. If this is a reference to an |
| 4737 | external symbol, and there is no constant, we want |
| 4738 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) |
| 4739 | addu $tempreg,$tempreg,$gp |
| 4740 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) |
| 4741 | or if tempreg is PIC_CALL_REG |
| 4742 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
| 4743 | addu $tempreg,$tempreg,$gp |
| 4744 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) |
| 4745 | For a local symbol, we want |
| 4746 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 4747 | nop |
| 4748 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) |
| 4749 | |
| 4750 | If we have a small constant, and this is a reference to |
| 4751 | an external symbol, we want |
| 4752 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) |
| 4753 | addu $tempreg,$tempreg,$gp |
| 4754 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) |
| 4755 | nop |
| 4756 | addiu $tempreg,$tempreg,<constant> |
| 4757 | For a local symbol, we want |
| 4758 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 4759 | nop |
| 4760 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) |
| 4761 | |
| 4762 | If we have a large constant, and this is a reference to |
| 4763 | an external symbol, we want |
| 4764 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) |
| 4765 | addu $tempreg,$tempreg,$gp |
| 4766 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) |
| 4767 | lui $at,<hiconstant> |
| 4768 | addiu $at,$at,<loconstant> |
| 4769 | addu $tempreg,$tempreg,$at |
| 4770 | For a local symbol, we want |
| 4771 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 4772 | lui $at,<hiconstant> |
| 4773 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) |
| 4774 | addu $tempreg,$tempreg,$at |
| 4775 | |
| 4776 | For NewABI, we want for data addresses |
| 4777 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
| 4778 | If tempreg is PIC_CALL_REG pointing to a external symbol, we want |
| 4779 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
| 4780 | */ |
| 4781 | if (HAVE_NEWABI) |
| 4782 | { |
| 4783 | int reloc_type = (tempreg == PIC_CALL_REG |
| 4784 | ? BFD_RELOC_MIPS_CALL16 |
| 4785 | : BFD_RELOC_MIPS_GOT_DISP); |
| 4786 | |
| 4787 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4788 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 4789 | "t,o(b)", tempreg, reloc_type, mips_gp_register); |
| 4790 | |
| 4791 | if (breg != 0) |
| 4792 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4793 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 4794 | "d,v,t", treg, tempreg, breg); |
| 4795 | |
| 4796 | if (! used_at) |
| 4797 | return; |
| 4798 | |
| 4799 | break; |
| 4800 | } |
| 4801 | expr1.X_add_number = offset_expr.X_add_number; |
| 4802 | offset_expr.X_add_number = 0; |
| 4803 | frag_grow (52); |
| 4804 | if (reg_needs_delay (mips_gp_register)) |
| 4805 | gpdel = 4; |
| 4806 | else |
| 4807 | gpdel = 0; |
| 4808 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
| 4809 | { |
| 4810 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; |
| 4811 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; |
| 4812 | } |
| 4813 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", |
| 4814 | tempreg, lui_reloc_type); |
| 4815 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4816 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 4817 | "d,v,t", tempreg, tempreg, mips_gp_register); |
| 4818 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4819 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 4820 | "t,o(b)", tempreg, lw_reloc_type, tempreg); |
| 4821 | if (expr1.X_add_number == 0) |
| 4822 | { |
| 4823 | int off; |
| 4824 | |
| 4825 | if (breg == 0) |
| 4826 | off = 0; |
| 4827 | else |
| 4828 | { |
| 4829 | /* We're going to put in an addu instruction using |
| 4830 | tempreg, so we may as well insert the nop right |
| 4831 | now. */ |
| 4832 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4833 | "nop", ""); |
| 4834 | off = 4; |
| 4835 | } |
| 4836 | |
| 4837 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
| 4838 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, |
| 4839 | 8 + gpdel, 0, |
| 4840 | (breg == 0 |
| 4841 | ? mips_opts.warn_about_macros |
| 4842 | : 0)), |
| 4843 | offset_expr.X_add_symbol, 0, NULL); |
| 4844 | } |
| 4845 | else if (expr1.X_add_number >= -0x8000 |
| 4846 | && expr1.X_add_number < 0x8000) |
| 4847 | { |
| 4848 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4849 | "nop", ""); |
| 4850 | macro_build ((char *) NULL, &icnt, &expr1, |
| 4851 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 4852 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
| 4853 | |
| 4854 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
| 4855 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, |
| 4856 | (breg == 0 |
| 4857 | ? mips_opts.warn_about_macros |
| 4858 | : 0)), |
| 4859 | offset_expr.X_add_symbol, 0, NULL); |
| 4860 | } |
| 4861 | else |
| 4862 | { |
| 4863 | int adj, dreg; |
| 4864 | |
| 4865 | /* If we are going to add in a base register, and the |
| 4866 | target register and the base register are the same, |
| 4867 | then we are using AT as a temporary register. Since |
| 4868 | we want to load the constant into AT, we add our |
| 4869 | current AT (from the global offset table) and the |
| 4870 | register into the register now, and pretend we were |
| 4871 | not using a base register. */ |
| 4872 | if (breg != treg) |
| 4873 | { |
| 4874 | adj = 0; |
| 4875 | dreg = tempreg; |
| 4876 | } |
| 4877 | else |
| 4878 | { |
| 4879 | assert (tempreg == AT); |
| 4880 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4881 | "nop", ""); |
| 4882 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4883 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 4884 | "d,v,t", treg, AT, breg); |
| 4885 | dreg = treg; |
| 4886 | adj = 8; |
| 4887 | } |
| 4888 | |
| 4889 | /* Set mips_optimize around the lui instruction to avoid |
| 4890 | inserting an unnecessary nop after the lw. */ |
| 4891 | hold_mips_optimize = mips_optimize; |
| 4892 | mips_optimize = 2; |
| 4893 | macro_build_lui (NULL, &icnt, &expr1, AT); |
| 4894 | mips_optimize = hold_mips_optimize; |
| 4895 | |
| 4896 | macro_build ((char *) NULL, &icnt, &expr1, |
| 4897 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 4898 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
| 4899 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4900 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 4901 | "d,v,t", dreg, dreg, AT); |
| 4902 | |
| 4903 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, |
| 4904 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, |
| 4905 | 8 + gpdel, 0, |
| 4906 | (breg == 0 |
| 4907 | ? mips_opts.warn_about_macros |
| 4908 | : 0)), |
| 4909 | offset_expr.X_add_symbol, 0, NULL); |
| 4910 | |
| 4911 | used_at = 1; |
| 4912 | } |
| 4913 | |
| 4914 | if (gpdel > 0) |
| 4915 | { |
| 4916 | /* This is needed because this instruction uses $gp, but |
| 4917 | the first instruction on the main stream does not. */ |
| 4918 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
| 4919 | p += 4; |
| 4920 | } |
| 4921 | macro_build (p, &icnt, &offset_expr, |
| 4922 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 4923 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, |
| 4924 | mips_gp_register); |
| 4925 | p += 4; |
| 4926 | if (expr1.X_add_number >= -0x8000 |
| 4927 | && expr1.X_add_number < 0x8000) |
| 4928 | { |
| 4929 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
| 4930 | p += 4; |
| 4931 | macro_build (p, &icnt, &expr1, |
| 4932 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 4933 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
| 4934 | /* FIXME: If add_number is 0, and there was no base |
| 4935 | register, the external symbol case ended with a load, |
| 4936 | so if the symbol turns out to not be external, and |
| 4937 | the next instruction uses tempreg, an unnecessary nop |
| 4938 | will be inserted. */ |
| 4939 | } |
| 4940 | else |
| 4941 | { |
| 4942 | if (breg == treg) |
| 4943 | { |
| 4944 | /* We must add in the base register now, as in the |
| 4945 | external symbol case. */ |
| 4946 | assert (tempreg == AT); |
| 4947 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
| 4948 | p += 4; |
| 4949 | macro_build (p, &icnt, (expressionS *) NULL, |
| 4950 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 4951 | "d,v,t", treg, AT, breg); |
| 4952 | p += 4; |
| 4953 | tempreg = treg; |
| 4954 | /* We set breg to 0 because we have arranged to add |
| 4955 | it in in both cases. */ |
| 4956 | breg = 0; |
| 4957 | } |
| 4958 | |
| 4959 | macro_build_lui (p, &icnt, &expr1, AT); |
| 4960 | p += 4; |
| 4961 | macro_build (p, &icnt, &expr1, |
| 4962 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 4963 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
| 4964 | p += 4; |
| 4965 | macro_build (p, &icnt, (expressionS *) NULL, |
| 4966 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 4967 | "d,v,t", tempreg, tempreg, AT); |
| 4968 | p += 4; |
| 4969 | } |
| 4970 | } |
| 4971 | else if (mips_pic == EMBEDDED_PIC) |
| 4972 | { |
| 4973 | /* We use |
| 4974 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
| 4975 | */ |
| 4976 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4977 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", |
| 4978 | tempreg, mips_gp_register, (int) BFD_RELOC_GPREL16); |
| 4979 | } |
| 4980 | else |
| 4981 | abort (); |
| 4982 | |
| 4983 | if (breg != 0) |
| 4984 | { |
| 4985 | char *s; |
| 4986 | |
| 4987 | if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) |
| 4988 | s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu"; |
| 4989 | else |
| 4990 | s = HAVE_64BIT_ADDRESSES ? "daddu" : "addu"; |
| 4991 | |
| 4992 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, |
| 4993 | "d,v,t", treg, tempreg, breg); |
| 4994 | } |
| 4995 | |
| 4996 | if (! used_at) |
| 4997 | return; |
| 4998 | |
| 4999 | break; |
| 5000 | |
| 5001 | case M_J_A: |
| 5002 | /* The j instruction may not be used in PIC code, since it |
| 5003 | requires an absolute address. We convert it to a b |
| 5004 | instruction. */ |
| 5005 | if (mips_pic == NO_PIC) |
| 5006 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
| 5007 | else |
| 5008 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
| 5009 | return; |
| 5010 | |
| 5011 | /* The jal instructions must be handled as macros because when |
| 5012 | generating PIC code they expand to multi-instruction |
| 5013 | sequences. Normally they are simple instructions. */ |
| 5014 | case M_JAL_1: |
| 5015 | dreg = RA; |
| 5016 | /* Fall through. */ |
| 5017 | case M_JAL_2: |
| 5018 | if (mips_pic == NO_PIC |
| 5019 | || mips_pic == EMBEDDED_PIC) |
| 5020 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
| 5021 | "d,s", dreg, sreg); |
| 5022 | else if (mips_pic == SVR4_PIC) |
| 5023 | { |
| 5024 | if (sreg != PIC_CALL_REG) |
| 5025 | as_warn (_("MIPS PIC call to register other than $25")); |
| 5026 | |
| 5027 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
| 5028 | "d,s", dreg, sreg); |
| 5029 | if (! HAVE_NEWABI) |
| 5030 | { |
| 5031 | if (mips_cprestore_offset < 0) |
| 5032 | as_warn (_("No .cprestore pseudo-op used in PIC code")); |
| 5033 | else |
| 5034 | { |
| 5035 | if (! mips_frame_reg_valid) |
| 5036 | { |
| 5037 | as_warn (_("No .frame pseudo-op used in PIC code")); |
| 5038 | /* Quiet this warning. */ |
| 5039 | mips_frame_reg_valid = 1; |
| 5040 | } |
| 5041 | if (! mips_cprestore_valid) |
| 5042 | { |
| 5043 | as_warn (_("No .cprestore pseudo-op used in PIC code")); |
| 5044 | /* Quiet this warning. */ |
| 5045 | mips_cprestore_valid = 1; |
| 5046 | } |
| 5047 | expr1.X_add_number = mips_cprestore_offset; |
| 5048 | macro_build ((char *) NULL, &icnt, &expr1, |
| 5049 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", |
| 5050 | mips_gp_register, (int) BFD_RELOC_LO16, |
| 5051 | mips_frame_reg); |
| 5052 | } |
| 5053 | } |
| 5054 | } |
| 5055 | else |
| 5056 | abort (); |
| 5057 | |
| 5058 | return; |
| 5059 | |
| 5060 | case M_JAL_A: |
| 5061 | if (mips_pic == NO_PIC) |
| 5062 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); |
| 5063 | else if (mips_pic == SVR4_PIC) |
| 5064 | { |
| 5065 | char *p; |
| 5066 | |
| 5067 | /* If this is a reference to an external symbol, and we are |
| 5068 | using a small GOT, we want |
| 5069 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
| 5070 | nop |
| 5071 | jalr $ra,$25 |
| 5072 | nop |
| 5073 | lw $gp,cprestore($sp) |
| 5074 | The cprestore value is set using the .cprestore |
| 5075 | pseudo-op. If we are using a big GOT, we want |
| 5076 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
| 5077 | addu $25,$25,$gp |
| 5078 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) |
| 5079 | nop |
| 5080 | jalr $ra,$25 |
| 5081 | nop |
| 5082 | lw $gp,cprestore($sp) |
| 5083 | If the symbol is not external, we want |
| 5084 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 5085 | nop |
| 5086 | addiu $25,$25,<sym> (BFD_RELOC_LO16) |
| 5087 | jalr $ra,$25 |
| 5088 | nop |
| 5089 | lw $gp,cprestore($sp) |
| 5090 | For NewABI, we want |
| 5091 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
| 5092 | jalr $ra,$25 (BFD_RELOC_MIPS_JALR) |
| 5093 | */ |
| 5094 | if (HAVE_NEWABI) |
| 5095 | { |
| 5096 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 5097 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 5098 | "t,o(b)", PIC_CALL_REG, |
| 5099 | (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
| 5100 | macro_build_jalr (icnt, &offset_expr); |
| 5101 | } |
| 5102 | else |
| 5103 | { |
| 5104 | frag_grow (40); |
| 5105 | if (! mips_big_got) |
| 5106 | { |
| 5107 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 5108 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 5109 | "t,o(b)", PIC_CALL_REG, |
| 5110 | (int) BFD_RELOC_MIPS_CALL16, mips_gp_register); |
| 5111 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5112 | "nop", ""); |
| 5113 | p = frag_var (rs_machine_dependent, 4, 0, |
| 5114 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), |
| 5115 | offset_expr.X_add_symbol, 0, NULL); |
| 5116 | } |
| 5117 | else |
| 5118 | { |
| 5119 | int gpdel; |
| 5120 | |
| 5121 | if (reg_needs_delay (mips_gp_register)) |
| 5122 | gpdel = 4; |
| 5123 | else |
| 5124 | gpdel = 0; |
| 5125 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", |
| 5126 | "t,u", PIC_CALL_REG, |
| 5127 | (int) BFD_RELOC_MIPS_CALL_HI16); |
| 5128 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5129 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 5130 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, |
| 5131 | mips_gp_register); |
| 5132 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 5133 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 5134 | "t,o(b)", PIC_CALL_REG, |
| 5135 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); |
| 5136 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5137 | "nop", ""); |
| 5138 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
| 5139 | RELAX_ENCODE (16, 12 + gpdel, gpdel, |
| 5140 | 8 + gpdel, 0, 0), |
| 5141 | offset_expr.X_add_symbol, 0, NULL); |
| 5142 | if (gpdel > 0) |
| 5143 | { |
| 5144 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
| 5145 | p += 4; |
| 5146 | } |
| 5147 | macro_build (p, &icnt, &offset_expr, |
| 5148 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 5149 | "t,o(b)", PIC_CALL_REG, |
| 5150 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); |
| 5151 | p += 4; |
| 5152 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
| 5153 | p += 4; |
| 5154 | } |
| 5155 | macro_build (p, &icnt, &offset_expr, |
| 5156 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 5157 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, |
| 5158 | (int) BFD_RELOC_LO16); |
| 5159 | macro_build_jalr (icnt, &offset_expr); |
| 5160 | |
| 5161 | if (mips_cprestore_offset < 0) |
| 5162 | as_warn (_("No .cprestore pseudo-op used in PIC code")); |
| 5163 | else |
| 5164 | { |
| 5165 | if (! mips_frame_reg_valid) |
| 5166 | { |
| 5167 | as_warn (_("No .frame pseudo-op used in PIC code")); |
| 5168 | /* Quiet this warning. */ |
| 5169 | mips_frame_reg_valid = 1; |
| 5170 | } |
| 5171 | if (! mips_cprestore_valid) |
| 5172 | { |
| 5173 | as_warn (_("No .cprestore pseudo-op used in PIC code")); |
| 5174 | /* Quiet this warning. */ |
| 5175 | mips_cprestore_valid = 1; |
| 5176 | } |
| 5177 | if (mips_opts.noreorder) |
| 5178 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5179 | "nop", ""); |
| 5180 | expr1.X_add_number = mips_cprestore_offset; |
| 5181 | macro_build ((char *) NULL, &icnt, &expr1, |
| 5182 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", |
| 5183 | mips_gp_register, (int) BFD_RELOC_LO16, |
| 5184 | mips_frame_reg); |
| 5185 | } |
| 5186 | } |
| 5187 | } |
| 5188 | else if (mips_pic == EMBEDDED_PIC) |
| 5189 | { |
| 5190 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); |
| 5191 | /* The linker may expand the call to a longer sequence which |
| 5192 | uses $at, so we must break rather than return. */ |
| 5193 | break; |
| 5194 | } |
| 5195 | else |
| 5196 | abort (); |
| 5197 | |
| 5198 | return; |
| 5199 | |
| 5200 | case M_LB_AB: |
| 5201 | s = "lb"; |
| 5202 | goto ld; |
| 5203 | case M_LBU_AB: |
| 5204 | s = "lbu"; |
| 5205 | goto ld; |
| 5206 | case M_LH_AB: |
| 5207 | s = "lh"; |
| 5208 | goto ld; |
| 5209 | case M_LHU_AB: |
| 5210 | s = "lhu"; |
| 5211 | goto ld; |
| 5212 | case M_LW_AB: |
| 5213 | s = "lw"; |
| 5214 | goto ld; |
| 5215 | case M_LWC0_AB: |
| 5216 | s = "lwc0"; |
| 5217 | /* Itbl support may require additional care here. */ |
| 5218 | coproc = 1; |
| 5219 | goto ld; |
| 5220 | case M_LWC1_AB: |
| 5221 | s = "lwc1"; |
| 5222 | /* Itbl support may require additional care here. */ |
| 5223 | coproc = 1; |
| 5224 | goto ld; |
| 5225 | case M_LWC2_AB: |
| 5226 | s = "lwc2"; |
| 5227 | /* Itbl support may require additional care here. */ |
| 5228 | coproc = 1; |
| 5229 | goto ld; |
| 5230 | case M_LWC3_AB: |
| 5231 | s = "lwc3"; |
| 5232 | /* Itbl support may require additional care here. */ |
| 5233 | coproc = 1; |
| 5234 | goto ld; |
| 5235 | case M_LWL_AB: |
| 5236 | s = "lwl"; |
| 5237 | lr = 1; |
| 5238 | goto ld; |
| 5239 | case M_LWR_AB: |
| 5240 | s = "lwr"; |
| 5241 | lr = 1; |
| 5242 | goto ld; |
| 5243 | case M_LDC1_AB: |
| 5244 | if (mips_arch == CPU_R4650) |
| 5245 | { |
| 5246 | as_bad (_("opcode not supported on this processor")); |
| 5247 | return; |
| 5248 | } |
| 5249 | s = "ldc1"; |
| 5250 | /* Itbl support may require additional care here. */ |
| 5251 | coproc = 1; |
| 5252 | goto ld; |
| 5253 | case M_LDC2_AB: |
| 5254 | s = "ldc2"; |
| 5255 | /* Itbl support may require additional care here. */ |
| 5256 | coproc = 1; |
| 5257 | goto ld; |
| 5258 | case M_LDC3_AB: |
| 5259 | s = "ldc3"; |
| 5260 | /* Itbl support may require additional care here. */ |
| 5261 | coproc = 1; |
| 5262 | goto ld; |
| 5263 | case M_LDL_AB: |
| 5264 | s = "ldl"; |
| 5265 | lr = 1; |
| 5266 | goto ld; |
| 5267 | case M_LDR_AB: |
| 5268 | s = "ldr"; |
| 5269 | lr = 1; |
| 5270 | goto ld; |
| 5271 | case M_LL_AB: |
| 5272 | s = "ll"; |
| 5273 | goto ld; |
| 5274 | case M_LLD_AB: |
| 5275 | s = "lld"; |
| 5276 | goto ld; |
| 5277 | case M_LWU_AB: |
| 5278 | s = "lwu"; |
| 5279 | ld: |
| 5280 | if (breg == treg || coproc || lr) |
| 5281 | { |
| 5282 | tempreg = AT; |
| 5283 | used_at = 1; |
| 5284 | } |
| 5285 | else |
| 5286 | { |
| 5287 | tempreg = treg; |
| 5288 | used_at = 0; |
| 5289 | } |
| 5290 | goto ld_st; |
| 5291 | case M_SB_AB: |
| 5292 | s = "sb"; |
| 5293 | goto st; |
| 5294 | case M_SH_AB: |
| 5295 | s = "sh"; |
| 5296 | goto st; |
| 5297 | case M_SW_AB: |
| 5298 | s = "sw"; |
| 5299 | goto st; |
| 5300 | case M_SWC0_AB: |
| 5301 | s = "swc0"; |
| 5302 | /* Itbl support may require additional care here. */ |
| 5303 | coproc = 1; |
| 5304 | goto st; |
| 5305 | case M_SWC1_AB: |
| 5306 | s = "swc1"; |
| 5307 | /* Itbl support may require additional care here. */ |
| 5308 | coproc = 1; |
| 5309 | goto st; |
| 5310 | case M_SWC2_AB: |
| 5311 | s = "swc2"; |
| 5312 | /* Itbl support may require additional care here. */ |
| 5313 | coproc = 1; |
| 5314 | goto st; |
| 5315 | case M_SWC3_AB: |
| 5316 | s = "swc3"; |
| 5317 | /* Itbl support may require additional care here. */ |
| 5318 | coproc = 1; |
| 5319 | goto st; |
| 5320 | case M_SWL_AB: |
| 5321 | s = "swl"; |
| 5322 | goto st; |
| 5323 | case M_SWR_AB: |
| 5324 | s = "swr"; |
| 5325 | goto st; |
| 5326 | case M_SC_AB: |
| 5327 | s = "sc"; |
| 5328 | goto st; |
| 5329 | case M_SCD_AB: |
| 5330 | s = "scd"; |
| 5331 | goto st; |
| 5332 | case M_SDC1_AB: |
| 5333 | if (mips_arch == CPU_R4650) |
| 5334 | { |
| 5335 | as_bad (_("opcode not supported on this processor")); |
| 5336 | return; |
| 5337 | } |
| 5338 | s = "sdc1"; |
| 5339 | coproc = 1; |
| 5340 | /* Itbl support may require additional care here. */ |
| 5341 | goto st; |
| 5342 | case M_SDC2_AB: |
| 5343 | s = "sdc2"; |
| 5344 | /* Itbl support may require additional care here. */ |
| 5345 | coproc = 1; |
| 5346 | goto st; |
| 5347 | case M_SDC3_AB: |
| 5348 | s = "sdc3"; |
| 5349 | /* Itbl support may require additional care here. */ |
| 5350 | coproc = 1; |
| 5351 | goto st; |
| 5352 | case M_SDL_AB: |
| 5353 | s = "sdl"; |
| 5354 | goto st; |
| 5355 | case M_SDR_AB: |
| 5356 | s = "sdr"; |
| 5357 | st: |
| 5358 | tempreg = AT; |
| 5359 | used_at = 1; |
| 5360 | ld_st: |
| 5361 | /* Itbl support may require additional care here. */ |
| 5362 | if (mask == M_LWC1_AB |
| 5363 | || mask == M_SWC1_AB |
| 5364 | || mask == M_LDC1_AB |
| 5365 | || mask == M_SDC1_AB |
| 5366 | || mask == M_L_DAB |
| 5367 | || mask == M_S_DAB) |
| 5368 | fmt = "T,o(b)"; |
| 5369 | else if (coproc) |
| 5370 | fmt = "E,o(b)"; |
| 5371 | else |
| 5372 | fmt = "t,o(b)"; |
| 5373 | |
| 5374 | /* For embedded PIC, we allow loads where the offset is calculated |
| 5375 | by subtracting a symbol in the current segment from an unknown |
| 5376 | symbol, relative to a base register, e.g.: |
| 5377 | <op> $treg, <sym>-<localsym>($breg) |
| 5378 | This is used by the compiler for switch statements. */ |
| 5379 | if (mips_pic == EMBEDDED_PIC |
| 5380 | && offset_expr.X_op == O_subtract |
| 5381 | && (symbol_constant_p (offset_expr.X_op_symbol) |
| 5382 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg |
| 5383 | : (symbol_equated_p (offset_expr.X_op_symbol) |
| 5384 | && (S_GET_SEGMENT |
| 5385 | (symbol_get_value_expression (offset_expr.X_op_symbol) |
| 5386 | ->X_add_symbol) |
| 5387 | == now_seg))) |
| 5388 | && breg != 0 |
| 5389 | && (offset_expr.X_add_number == 0 |
| 5390 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) |
| 5391 | { |
| 5392 | /* For this case, we output the instructions: |
| 5393 | lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S) |
| 5394 | addiu $tempreg,$tempreg,$breg |
| 5395 | <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16) |
| 5396 | If the relocation would fit entirely in 16 bits, it would be |
| 5397 | nice to emit: |
| 5398 | <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16) |
| 5399 | instead, but that seems quite difficult. */ |
| 5400 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", |
| 5401 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); |
| 5402 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5403 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
| 5404 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
| 5405 | ? "addu" : "daddu"), |
| 5406 | "d,v,t", tempreg, tempreg, breg); |
| 5407 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg, |
| 5408 | (int) BFD_RELOC_PCREL_LO16, tempreg); |
| 5409 | if (! used_at) |
| 5410 | return; |
| 5411 | break; |
| 5412 | } |
| 5413 | |
| 5414 | if (offset_expr.X_op != O_constant |
| 5415 | && offset_expr.X_op != O_symbol) |
| 5416 | { |
| 5417 | as_bad (_("expression too complex")); |
| 5418 | offset_expr.X_op = O_constant; |
| 5419 | } |
| 5420 | |
| 5421 | /* A constant expression in PIC code can be handled just as it |
| 5422 | is in non PIC code. */ |
| 5423 | if (mips_pic == NO_PIC |
| 5424 | || offset_expr.X_op == O_constant) |
| 5425 | { |
| 5426 | char *p; |
| 5427 | |
| 5428 | /* If this is a reference to a GP relative symbol, and there |
| 5429 | is no base register, we want |
| 5430 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
| 5431 | Otherwise, if there is no base register, we want |
| 5432 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
| 5433 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) |
| 5434 | If we have a constant, we need two instructions anyhow, |
| 5435 | so we always use the latter form. |
| 5436 | |
| 5437 | If we have a base register, and this is a reference to a |
| 5438 | GP relative symbol, we want |
| 5439 | addu $tempreg,$breg,$gp |
| 5440 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
| 5441 | Otherwise we want |
| 5442 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
| 5443 | addu $tempreg,$tempreg,$breg |
| 5444 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) |
| 5445 | With a constant we always use the latter case. |
| 5446 | |
| 5447 | With 64bit address space and no base register and $at usable, |
| 5448 | we want |
| 5449 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) |
| 5450 | lui $at,<sym> (BFD_RELOC_HI16_S) |
| 5451 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) |
| 5452 | dsll32 $tempreg,0 |
| 5453 | daddu $tempreg,$at |
| 5454 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) |
| 5455 | If we have a base register, we want |
| 5456 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) |
| 5457 | lui $at,<sym> (BFD_RELOC_HI16_S) |
| 5458 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) |
| 5459 | daddu $at,$breg |
| 5460 | dsll32 $tempreg,0 |
| 5461 | daddu $tempreg,$at |
| 5462 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) |
| 5463 | |
| 5464 | Without $at we can't generate the optimal path for superscalar |
| 5465 | processors here since this would require two temporary registers. |
| 5466 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) |
| 5467 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) |
| 5468 | dsll $tempreg,16 |
| 5469 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) |
| 5470 | dsll $tempreg,16 |
| 5471 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) |
| 5472 | If we have a base register, we want |
| 5473 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) |
| 5474 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) |
| 5475 | dsll $tempreg,16 |
| 5476 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) |
| 5477 | dsll $tempreg,16 |
| 5478 | daddu $tempreg,$tempreg,$breg |
| 5479 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) |
| 5480 | |
| 5481 | If we have 64-bit addresses, as an optimization, for |
| 5482 | addresses which are 32-bit constants (e.g. kseg0/kseg1 |
| 5483 | addresses) we fall back to the 32-bit address generation |
| 5484 | mechanism since it is more efficient. Note that due to |
| 5485 | the signed offset used by memory operations, the 32-bit |
| 5486 | range is shifted down by 32768 here. This code should |
| 5487 | probably attempt to generate 64-bit constants more |
| 5488 | efficiently in general. |
| 5489 | */ |
| 5490 | if (HAVE_64BIT_ADDRESSES |
| 5491 | && !(offset_expr.X_op == O_constant |
| 5492 | && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) |
| 5493 | { |
| 5494 | p = NULL; |
| 5495 | |
| 5496 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
| 5497 | hold the data for such large chunks. */ |
| 5498 | |
| 5499 | if (used_at == 0 && ! mips_opts.noat) |
| 5500 | { |
| 5501 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", |
| 5502 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); |
| 5503 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", |
| 5504 | AT, (int) BFD_RELOC_HI16_S); |
| 5505 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
| 5506 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); |
| 5507 | if (breg != 0) |
| 5508 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
| 5509 | "d,v,t", AT, AT, breg); |
| 5510 | macro_build (p, &icnt, (expressionS *) NULL, "dsll32", |
| 5511 | "d,w,<", tempreg, tempreg, 0); |
| 5512 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
| 5513 | "d,v,t", tempreg, tempreg, AT); |
| 5514 | macro_build (p, &icnt, &offset_expr, s, |
| 5515 | fmt, treg, (int) BFD_RELOC_LO16, tempreg); |
| 5516 | used_at = 1; |
| 5517 | } |
| 5518 | else |
| 5519 | { |
| 5520 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", |
| 5521 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); |
| 5522 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
| 5523 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); |
| 5524 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", |
| 5525 | "d,w,<", tempreg, tempreg, 16); |
| 5526 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
| 5527 | tempreg, tempreg, (int) BFD_RELOC_HI16_S); |
| 5528 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", |
| 5529 | "d,w,<", tempreg, tempreg, 16); |
| 5530 | if (breg != 0) |
| 5531 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
| 5532 | "d,v,t", tempreg, tempreg, breg); |
| 5533 | macro_build (p, &icnt, &offset_expr, s, |
| 5534 | fmt, treg, (int) BFD_RELOC_LO16, tempreg); |
| 5535 | } |
| 5536 | |
| 5537 | return; |
| 5538 | } |
| 5539 | |
| 5540 | if (breg == 0) |
| 5541 | { |
| 5542 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
| 5543 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
| 5544 | p = NULL; |
| 5545 | else |
| 5546 | { |
| 5547 | frag_grow (20); |
| 5548 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
| 5549 | treg, (int) BFD_RELOC_GPREL16, |
| 5550 | mips_gp_register); |
| 5551 | p = frag_var (rs_machine_dependent, 8, 0, |
| 5552 | RELAX_ENCODE (4, 8, 0, 4, 0, |
| 5553 | (mips_opts.warn_about_macros |
| 5554 | || (used_at |
| 5555 | && mips_opts.noat))), |
| 5556 | offset_expr.X_add_symbol, 0, NULL); |
| 5557 | used_at = 0; |
| 5558 | } |
| 5559 | macro_build_lui (p, &icnt, &offset_expr, tempreg); |
| 5560 | if (p != NULL) |
| 5561 | p += 4; |
| 5562 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, |
| 5563 | (int) BFD_RELOC_LO16, tempreg); |
| 5564 | } |
| 5565 | else |
| 5566 | { |
| 5567 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
| 5568 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
| 5569 | p = NULL; |
| 5570 | else |
| 5571 | { |
| 5572 | frag_grow (28); |
| 5573 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5574 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 5575 | "d,v,t", tempreg, breg, mips_gp_register); |
| 5576 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
| 5577 | treg, (int) BFD_RELOC_GPREL16, tempreg); |
| 5578 | p = frag_var (rs_machine_dependent, 12, 0, |
| 5579 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), |
| 5580 | offset_expr.X_add_symbol, 0, NULL); |
| 5581 | } |
| 5582 | macro_build_lui (p, &icnt, &offset_expr, tempreg); |
| 5583 | if (p != NULL) |
| 5584 | p += 4; |
| 5585 | macro_build (p, &icnt, (expressionS *) NULL, |
| 5586 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 5587 | "d,v,t", tempreg, tempreg, breg); |
| 5588 | if (p != NULL) |
| 5589 | p += 4; |
| 5590 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, |
| 5591 | (int) BFD_RELOC_LO16, tempreg); |
| 5592 | } |
| 5593 | } |
| 5594 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
| 5595 | { |
| 5596 | char *p; |
| 5597 | |
| 5598 | /* If this is a reference to an external symbol, we want |
| 5599 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 5600 | nop |
| 5601 | <op> $treg,0($tempreg) |
| 5602 | Otherwise we want |
| 5603 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 5604 | nop |
| 5605 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) |
| 5606 | <op> $treg,0($tempreg) |
| 5607 | If there is a base register, we add it to $tempreg before |
| 5608 | the <op>. If there is a constant, we stick it in the |
| 5609 | <op> instruction. We don't handle constants larger than |
| 5610 | 16 bits, because we have no way to load the upper 16 bits |
| 5611 | (actually, we could handle them for the subset of cases |
| 5612 | in which we are not using $at). */ |
| 5613 | assert (offset_expr.X_op == O_symbol); |
| 5614 | expr1.X_add_number = offset_expr.X_add_number; |
| 5615 | offset_expr.X_add_number = 0; |
| 5616 | if (expr1.X_add_number < -0x8000 |
| 5617 | || expr1.X_add_number >= 0x8000) |
| 5618 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
| 5619 | frag_grow (20); |
| 5620 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 5621 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", tempreg, |
| 5622 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); |
| 5623 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
| 5624 | p = frag_var (rs_machine_dependent, 4, 0, |
| 5625 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), |
| 5626 | offset_expr.X_add_symbol, 0, NULL); |
| 5627 | macro_build (p, &icnt, &offset_expr, |
| 5628 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 5629 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
| 5630 | if (breg != 0) |
| 5631 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5632 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 5633 | "d,v,t", tempreg, tempreg, breg); |
| 5634 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
| 5635 | (int) BFD_RELOC_LO16, tempreg); |
| 5636 | } |
| 5637 | else if (mips_pic == SVR4_PIC) |
| 5638 | { |
| 5639 | int gpdel; |
| 5640 | char *p; |
| 5641 | |
| 5642 | /* If this is a reference to an external symbol, we want |
| 5643 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) |
| 5644 | addu $tempreg,$tempreg,$gp |
| 5645 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) |
| 5646 | <op> $treg,0($tempreg) |
| 5647 | Otherwise we want |
| 5648 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 5649 | nop |
| 5650 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) |
| 5651 | <op> $treg,0($tempreg) |
| 5652 | If there is a base register, we add it to $tempreg before |
| 5653 | the <op>. If there is a constant, we stick it in the |
| 5654 | <op> instruction. We don't handle constants larger than |
| 5655 | 16 bits, because we have no way to load the upper 16 bits |
| 5656 | (actually, we could handle them for the subset of cases |
| 5657 | in which we are not using $at). |
| 5658 | |
| 5659 | For NewABI, we want |
| 5660 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
| 5661 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST) |
| 5662 | <op> $treg,0($tempreg) |
| 5663 | */ |
| 5664 | assert (offset_expr.X_op == O_symbol); |
| 5665 | expr1.X_add_number = offset_expr.X_add_number; |
| 5666 | offset_expr.X_add_number = 0; |
| 5667 | if (expr1.X_add_number < -0x8000 |
| 5668 | || expr1.X_add_number >= 0x8000) |
| 5669 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
| 5670 | if (HAVE_NEWABI) |
| 5671 | { |
| 5672 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 5673 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 5674 | "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE, |
| 5675 | mips_gp_register); |
| 5676 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 5677 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 5678 | "t,r,j", tempreg, tempreg, |
| 5679 | BFD_RELOC_MIPS_GOT_OFST); |
| 5680 | if (breg != 0) |
| 5681 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5682 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 5683 | "d,v,t", tempreg, tempreg, breg); |
| 5684 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
| 5685 | (int) BFD_RELOC_LO16, tempreg); |
| 5686 | |
| 5687 | if (! used_at) |
| 5688 | return; |
| 5689 | |
| 5690 | break; |
| 5691 | } |
| 5692 | if (reg_needs_delay (mips_gp_register)) |
| 5693 | gpdel = 4; |
| 5694 | else |
| 5695 | gpdel = 0; |
| 5696 | frag_grow (36); |
| 5697 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", |
| 5698 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); |
| 5699 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5700 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 5701 | "d,v,t", tempreg, tempreg, mips_gp_register); |
| 5702 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 5703 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 5704 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
| 5705 | tempreg); |
| 5706 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
| 5707 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), |
| 5708 | offset_expr.X_add_symbol, 0, NULL); |
| 5709 | if (gpdel > 0) |
| 5710 | { |
| 5711 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
| 5712 | p += 4; |
| 5713 | } |
| 5714 | macro_build (p, &icnt, &offset_expr, |
| 5715 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 5716 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, |
| 5717 | mips_gp_register); |
| 5718 | p += 4; |
| 5719 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
| 5720 | p += 4; |
| 5721 | macro_build (p, &icnt, &offset_expr, |
| 5722 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 5723 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
| 5724 | if (breg != 0) |
| 5725 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5726 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 5727 | "d,v,t", tempreg, tempreg, breg); |
| 5728 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
| 5729 | (int) BFD_RELOC_LO16, tempreg); |
| 5730 | } |
| 5731 | else if (mips_pic == EMBEDDED_PIC) |
| 5732 | { |
| 5733 | /* If there is no base register, we want |
| 5734 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
| 5735 | If there is a base register, we want |
| 5736 | addu $tempreg,$breg,$gp |
| 5737 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
| 5738 | */ |
| 5739 | assert (offset_expr.X_op == O_symbol); |
| 5740 | if (breg == 0) |
| 5741 | { |
| 5742 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
| 5743 | treg, (int) BFD_RELOC_GPREL16, mips_gp_register); |
| 5744 | used_at = 0; |
| 5745 | } |
| 5746 | else |
| 5747 | { |
| 5748 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5749 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 5750 | "d,v,t", tempreg, breg, mips_gp_register); |
| 5751 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
| 5752 | treg, (int) BFD_RELOC_GPREL16, tempreg); |
| 5753 | } |
| 5754 | } |
| 5755 | else |
| 5756 | abort (); |
| 5757 | |
| 5758 | if (! used_at) |
| 5759 | return; |
| 5760 | |
| 5761 | break; |
| 5762 | |
| 5763 | case M_LI: |
| 5764 | case M_LI_S: |
| 5765 | load_register (&icnt, treg, &imm_expr, 0); |
| 5766 | return; |
| 5767 | |
| 5768 | case M_DLI: |
| 5769 | load_register (&icnt, treg, &imm_expr, 1); |
| 5770 | return; |
| 5771 | |
| 5772 | case M_LI_SS: |
| 5773 | if (imm_expr.X_op == O_constant) |
| 5774 | { |
| 5775 | load_register (&icnt, AT, &imm_expr, 0); |
| 5776 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5777 | "mtc1", "t,G", AT, treg); |
| 5778 | break; |
| 5779 | } |
| 5780 | else |
| 5781 | { |
| 5782 | assert (offset_expr.X_op == O_symbol |
| 5783 | && strcmp (segment_name (S_GET_SEGMENT |
| 5784 | (offset_expr.X_add_symbol)), |
| 5785 | ".lit4") == 0 |
| 5786 | && offset_expr.X_add_number == 0); |
| 5787 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
| 5788 | treg, (int) BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
| 5789 | return; |
| 5790 | } |
| 5791 | |
| 5792 | case M_LI_D: |
| 5793 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
| 5794 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high |
| 5795 | order 32 bits of the value and the low order 32 bits are either |
| 5796 | zero or in OFFSET_EXPR. */ |
| 5797 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
| 5798 | { |
| 5799 | if (HAVE_64BIT_GPRS) |
| 5800 | load_register (&icnt, treg, &imm_expr, 1); |
| 5801 | else |
| 5802 | { |
| 5803 | int hreg, lreg; |
| 5804 | |
| 5805 | if (target_big_endian) |
| 5806 | { |
| 5807 | hreg = treg; |
| 5808 | lreg = treg + 1; |
| 5809 | } |
| 5810 | else |
| 5811 | { |
| 5812 | hreg = treg + 1; |
| 5813 | lreg = treg; |
| 5814 | } |
| 5815 | |
| 5816 | if (hreg <= 31) |
| 5817 | load_register (&icnt, hreg, &imm_expr, 0); |
| 5818 | if (lreg <= 31) |
| 5819 | { |
| 5820 | if (offset_expr.X_op == O_absent) |
| 5821 | move_register (&icnt, lreg, 0); |
| 5822 | else |
| 5823 | { |
| 5824 | assert (offset_expr.X_op == O_constant); |
| 5825 | load_register (&icnt, lreg, &offset_expr, 0); |
| 5826 | } |
| 5827 | } |
| 5828 | } |
| 5829 | return; |
| 5830 | } |
| 5831 | |
| 5832 | /* We know that sym is in the .rdata section. First we get the |
| 5833 | upper 16 bits of the address. */ |
| 5834 | if (mips_pic == NO_PIC) |
| 5835 | { |
| 5836 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
| 5837 | } |
| 5838 | else if (mips_pic == SVR4_PIC) |
| 5839 | { |
| 5840 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 5841 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 5842 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, |
| 5843 | mips_gp_register); |
| 5844 | } |
| 5845 | else if (mips_pic == EMBEDDED_PIC) |
| 5846 | { |
| 5847 | /* For embedded PIC we pick up the entire address off $gp in |
| 5848 | a single instruction. */ |
| 5849 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 5850 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", AT, |
| 5851 | mips_gp_register, (int) BFD_RELOC_GPREL16); |
| 5852 | offset_expr.X_op = O_constant; |
| 5853 | offset_expr.X_add_number = 0; |
| 5854 | } |
| 5855 | else |
| 5856 | abort (); |
| 5857 | |
| 5858 | /* Now we load the register(s). */ |
| 5859 | if (HAVE_64BIT_GPRS) |
| 5860 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
| 5861 | treg, (int) BFD_RELOC_LO16, AT); |
| 5862 | else |
| 5863 | { |
| 5864 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
| 5865 | treg, (int) BFD_RELOC_LO16, AT); |
| 5866 | if (treg != RA) |
| 5867 | { |
| 5868 | /* FIXME: How in the world do we deal with the possible |
| 5869 | overflow here? */ |
| 5870 | offset_expr.X_add_number += 4; |
| 5871 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
| 5872 | treg + 1, (int) BFD_RELOC_LO16, AT); |
| 5873 | } |
| 5874 | } |
| 5875 | |
| 5876 | /* To avoid confusion in tc_gen_reloc, we must ensure that this |
| 5877 | does not become a variant frag. */ |
| 5878 | frag_wane (frag_now); |
| 5879 | frag_new (0); |
| 5880 | |
| 5881 | break; |
| 5882 | |
| 5883 | case M_LI_DD: |
| 5884 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
| 5885 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 |
| 5886 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of |
| 5887 | the value and the low order 32 bits are either zero or in |
| 5888 | OFFSET_EXPR. */ |
| 5889 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
| 5890 | { |
| 5891 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS); |
| 5892 | if (HAVE_64BIT_FPRS) |
| 5893 | { |
| 5894 | assert (HAVE_64BIT_GPRS); |
| 5895 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5896 | "dmtc1", "t,S", AT, treg); |
| 5897 | } |
| 5898 | else |
| 5899 | { |
| 5900 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5901 | "mtc1", "t,G", AT, treg + 1); |
| 5902 | if (offset_expr.X_op == O_absent) |
| 5903 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5904 | "mtc1", "t,G", 0, treg); |
| 5905 | else |
| 5906 | { |
| 5907 | assert (offset_expr.X_op == O_constant); |
| 5908 | load_register (&icnt, AT, &offset_expr, 0); |
| 5909 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5910 | "mtc1", "t,G", AT, treg); |
| 5911 | } |
| 5912 | } |
| 5913 | break; |
| 5914 | } |
| 5915 | |
| 5916 | assert (offset_expr.X_op == O_symbol |
| 5917 | && offset_expr.X_add_number == 0); |
| 5918 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
| 5919 | if (strcmp (s, ".lit8") == 0) |
| 5920 | { |
| 5921 | if (mips_opts.isa != ISA_MIPS1) |
| 5922 | { |
| 5923 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", |
| 5924 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, |
| 5925 | mips_gp_register); |
| 5926 | return; |
| 5927 | } |
| 5928 | breg = mips_gp_register; |
| 5929 | r = BFD_RELOC_MIPS_LITERAL; |
| 5930 | goto dob; |
| 5931 | } |
| 5932 | else |
| 5933 | { |
| 5934 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
| 5935 | if (mips_pic == SVR4_PIC) |
| 5936 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 5937 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 5938 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, |
| 5939 | mips_gp_register); |
| 5940 | else |
| 5941 | { |
| 5942 | /* FIXME: This won't work for a 64 bit address. */ |
| 5943 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
| 5944 | } |
| 5945 | |
| 5946 | if (mips_opts.isa != ISA_MIPS1) |
| 5947 | { |
| 5948 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", |
| 5949 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); |
| 5950 | |
| 5951 | /* To avoid confusion in tc_gen_reloc, we must ensure |
| 5952 | that this does not become a variant frag. */ |
| 5953 | frag_wane (frag_now); |
| 5954 | frag_new (0); |
| 5955 | |
| 5956 | break; |
| 5957 | } |
| 5958 | breg = AT; |
| 5959 | r = BFD_RELOC_LO16; |
| 5960 | goto dob; |
| 5961 | } |
| 5962 | |
| 5963 | case M_L_DOB: |
| 5964 | if (mips_arch == CPU_R4650) |
| 5965 | { |
| 5966 | as_bad (_("opcode not supported on this processor")); |
| 5967 | return; |
| 5968 | } |
| 5969 | /* Even on a big endian machine $fn comes before $fn+1. We have |
| 5970 | to adjust when loading from memory. */ |
| 5971 | r = BFD_RELOC_LO16; |
| 5972 | dob: |
| 5973 | assert (mips_opts.isa == ISA_MIPS1); |
| 5974 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
| 5975 | target_big_endian ? treg + 1 : treg, |
| 5976 | (int) r, breg); |
| 5977 | /* FIXME: A possible overflow which I don't know how to deal |
| 5978 | with. */ |
| 5979 | offset_expr.X_add_number += 4; |
| 5980 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
| 5981 | target_big_endian ? treg : treg + 1, |
| 5982 | (int) r, breg); |
| 5983 | |
| 5984 | /* To avoid confusion in tc_gen_reloc, we must ensure that this |
| 5985 | does not become a variant frag. */ |
| 5986 | frag_wane (frag_now); |
| 5987 | frag_new (0); |
| 5988 | |
| 5989 | if (breg != AT) |
| 5990 | return; |
| 5991 | break; |
| 5992 | |
| 5993 | case M_L_DAB: |
| 5994 | /* |
| 5995 | * The MIPS assembler seems to check for X_add_number not |
| 5996 | * being double aligned and generating: |
| 5997 | * lui at,%hi(foo+1) |
| 5998 | * addu at,at,v1 |
| 5999 | * addiu at,at,%lo(foo+1) |
| 6000 | * lwc1 f2,0(at) |
| 6001 | * lwc1 f3,4(at) |
| 6002 | * But, the resulting address is the same after relocation so why |
| 6003 | * generate the extra instruction? |
| 6004 | */ |
| 6005 | if (mips_arch == CPU_R4650) |
| 6006 | { |
| 6007 | as_bad (_("opcode not supported on this processor")); |
| 6008 | return; |
| 6009 | } |
| 6010 | /* Itbl support may require additional care here. */ |
| 6011 | coproc = 1; |
| 6012 | if (mips_opts.isa != ISA_MIPS1) |
| 6013 | { |
| 6014 | s = "ldc1"; |
| 6015 | goto ld; |
| 6016 | } |
| 6017 | |
| 6018 | s = "lwc1"; |
| 6019 | fmt = "T,o(b)"; |
| 6020 | goto ldd_std; |
| 6021 | |
| 6022 | case M_S_DAB: |
| 6023 | if (mips_arch == CPU_R4650) |
| 6024 | { |
| 6025 | as_bad (_("opcode not supported on this processor")); |
| 6026 | return; |
| 6027 | } |
| 6028 | |
| 6029 | if (mips_opts.isa != ISA_MIPS1) |
| 6030 | { |
| 6031 | s = "sdc1"; |
| 6032 | goto st; |
| 6033 | } |
| 6034 | |
| 6035 | s = "swc1"; |
| 6036 | fmt = "T,o(b)"; |
| 6037 | /* Itbl support may require additional care here. */ |
| 6038 | coproc = 1; |
| 6039 | goto ldd_std; |
| 6040 | |
| 6041 | case M_LD_AB: |
| 6042 | if (HAVE_64BIT_GPRS) |
| 6043 | { |
| 6044 | s = "ld"; |
| 6045 | goto ld; |
| 6046 | } |
| 6047 | |
| 6048 | s = "lw"; |
| 6049 | fmt = "t,o(b)"; |
| 6050 | goto ldd_std; |
| 6051 | |
| 6052 | case M_SD_AB: |
| 6053 | if (HAVE_64BIT_GPRS) |
| 6054 | { |
| 6055 | s = "sd"; |
| 6056 | goto st; |
| 6057 | } |
| 6058 | |
| 6059 | s = "sw"; |
| 6060 | fmt = "t,o(b)"; |
| 6061 | |
| 6062 | ldd_std: |
| 6063 | /* We do _not_ bother to allow embedded PIC (symbol-local_symbol) |
| 6064 | loads for the case of doing a pair of loads to simulate an 'ld'. |
| 6065 | This is not currently done by the compiler, and assembly coders |
| 6066 | writing embedded-pic code can cope. */ |
| 6067 | |
| 6068 | if (offset_expr.X_op != O_symbol |
| 6069 | && offset_expr.X_op != O_constant) |
| 6070 | { |
| 6071 | as_bad (_("expression too complex")); |
| 6072 | offset_expr.X_op = O_constant; |
| 6073 | } |
| 6074 | |
| 6075 | /* Even on a big endian machine $fn comes before $fn+1. We have |
| 6076 | to adjust when loading from memory. We set coproc if we must |
| 6077 | load $fn+1 first. */ |
| 6078 | /* Itbl support may require additional care here. */ |
| 6079 | if (! target_big_endian) |
| 6080 | coproc = 0; |
| 6081 | |
| 6082 | if (mips_pic == NO_PIC |
| 6083 | || offset_expr.X_op == O_constant) |
| 6084 | { |
| 6085 | char *p; |
| 6086 | |
| 6087 | /* If this is a reference to a GP relative symbol, we want |
| 6088 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
| 6089 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) |
| 6090 | If we have a base register, we use this |
| 6091 | addu $at,$breg,$gp |
| 6092 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
| 6093 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) |
| 6094 | If this is not a GP relative symbol, we want |
| 6095 | lui $at,<sym> (BFD_RELOC_HI16_S) |
| 6096 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) |
| 6097 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) |
| 6098 | If there is a base register, we add it to $at after the |
| 6099 | lui instruction. If there is a constant, we always use |
| 6100 | the last case. */ |
| 6101 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
| 6102 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
| 6103 | { |
| 6104 | p = NULL; |
| 6105 | used_at = 1; |
| 6106 | } |
| 6107 | else |
| 6108 | { |
| 6109 | int off; |
| 6110 | |
| 6111 | if (breg == 0) |
| 6112 | { |
| 6113 | frag_grow (28); |
| 6114 | tempreg = mips_gp_register; |
| 6115 | off = 0; |
| 6116 | used_at = 0; |
| 6117 | } |
| 6118 | else |
| 6119 | { |
| 6120 | frag_grow (36); |
| 6121 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 6122 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 6123 | "d,v,t", AT, breg, mips_gp_register); |
| 6124 | tempreg = AT; |
| 6125 | off = 4; |
| 6126 | used_at = 1; |
| 6127 | } |
| 6128 | |
| 6129 | /* Itbl support may require additional care here. */ |
| 6130 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
| 6131 | coproc ? treg + 1 : treg, |
| 6132 | (int) BFD_RELOC_GPREL16, tempreg); |
| 6133 | offset_expr.X_add_number += 4; |
| 6134 | |
| 6135 | /* Set mips_optimize to 2 to avoid inserting an |
| 6136 | undesired nop. */ |
| 6137 | hold_mips_optimize = mips_optimize; |
| 6138 | mips_optimize = 2; |
| 6139 | /* Itbl support may require additional care here. */ |
| 6140 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
| 6141 | coproc ? treg : treg + 1, |
| 6142 | (int) BFD_RELOC_GPREL16, tempreg); |
| 6143 | mips_optimize = hold_mips_optimize; |
| 6144 | |
| 6145 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
| 6146 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, |
| 6147 | used_at && mips_opts.noat), |
| 6148 | offset_expr.X_add_symbol, 0, NULL); |
| 6149 | |
| 6150 | /* We just generated two relocs. When tc_gen_reloc |
| 6151 | handles this case, it will skip the first reloc and |
| 6152 | handle the second. The second reloc already has an |
| 6153 | extra addend of 4, which we added above. We must |
| 6154 | subtract it out, and then subtract another 4 to make |
| 6155 | the first reloc come out right. The second reloc |
| 6156 | will come out right because we are going to add 4 to |
| 6157 | offset_expr when we build its instruction below. |
| 6158 | |
| 6159 | If we have a symbol, then we don't want to include |
| 6160 | the offset, because it will wind up being included |
| 6161 | when we generate the reloc. */ |
| 6162 | |
| 6163 | if (offset_expr.X_op == O_constant) |
| 6164 | offset_expr.X_add_number -= 8; |
| 6165 | else |
| 6166 | { |
| 6167 | offset_expr.X_add_number = -4; |
| 6168 | offset_expr.X_op = O_constant; |
| 6169 | } |
| 6170 | } |
| 6171 | macro_build_lui (p, &icnt, &offset_expr, AT); |
| 6172 | if (p != NULL) |
| 6173 | p += 4; |
| 6174 | if (breg != 0) |
| 6175 | { |
| 6176 | macro_build (p, &icnt, (expressionS *) NULL, |
| 6177 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 6178 | "d,v,t", AT, breg, AT); |
| 6179 | if (p != NULL) |
| 6180 | p += 4; |
| 6181 | } |
| 6182 | /* Itbl support may require additional care here. */ |
| 6183 | macro_build (p, &icnt, &offset_expr, s, fmt, |
| 6184 | coproc ? treg + 1 : treg, |
| 6185 | (int) BFD_RELOC_LO16, AT); |
| 6186 | if (p != NULL) |
| 6187 | p += 4; |
| 6188 | /* FIXME: How do we handle overflow here? */ |
| 6189 | offset_expr.X_add_number += 4; |
| 6190 | /* Itbl support may require additional care here. */ |
| 6191 | macro_build (p, &icnt, &offset_expr, s, fmt, |
| 6192 | coproc ? treg : treg + 1, |
| 6193 | (int) BFD_RELOC_LO16, AT); |
| 6194 | } |
| 6195 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
| 6196 | { |
| 6197 | int off; |
| 6198 | |
| 6199 | /* If this is a reference to an external symbol, we want |
| 6200 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 6201 | nop |
| 6202 | <op> $treg,0($at) |
| 6203 | <op> $treg+1,4($at) |
| 6204 | Otherwise we want |
| 6205 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 6206 | nop |
| 6207 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) |
| 6208 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) |
| 6209 | If there is a base register we add it to $at before the |
| 6210 | lwc1 instructions. If there is a constant we include it |
| 6211 | in the lwc1 instructions. */ |
| 6212 | used_at = 1; |
| 6213 | expr1.X_add_number = offset_expr.X_add_number; |
| 6214 | offset_expr.X_add_number = 0; |
| 6215 | if (expr1.X_add_number < -0x8000 |
| 6216 | || expr1.X_add_number >= 0x8000 - 4) |
| 6217 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
| 6218 | if (breg == 0) |
| 6219 | off = 0; |
| 6220 | else |
| 6221 | off = 4; |
| 6222 | frag_grow (24 + off); |
| 6223 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 6224 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", AT, |
| 6225 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); |
| 6226 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
| 6227 | if (breg != 0) |
| 6228 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 6229 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 6230 | "d,v,t", AT, breg, AT); |
| 6231 | /* Itbl support may require additional care here. */ |
| 6232 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
| 6233 | coproc ? treg + 1 : treg, |
| 6234 | (int) BFD_RELOC_LO16, AT); |
| 6235 | expr1.X_add_number += 4; |
| 6236 | |
| 6237 | /* Set mips_optimize to 2 to avoid inserting an undesired |
| 6238 | nop. */ |
| 6239 | hold_mips_optimize = mips_optimize; |
| 6240 | mips_optimize = 2; |
| 6241 | /* Itbl support may require additional care here. */ |
| 6242 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
| 6243 | coproc ? treg : treg + 1, |
| 6244 | (int) BFD_RELOC_LO16, AT); |
| 6245 | mips_optimize = hold_mips_optimize; |
| 6246 | |
| 6247 | (void) frag_var (rs_machine_dependent, 0, 0, |
| 6248 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), |
| 6249 | offset_expr.X_add_symbol, 0, NULL); |
| 6250 | } |
| 6251 | else if (mips_pic == SVR4_PIC) |
| 6252 | { |
| 6253 | int gpdel, off; |
| 6254 | char *p; |
| 6255 | |
| 6256 | /* If this is a reference to an external symbol, we want |
| 6257 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) |
| 6258 | addu $at,$at,$gp |
| 6259 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) |
| 6260 | nop |
| 6261 | <op> $treg,0($at) |
| 6262 | <op> $treg+1,4($at) |
| 6263 | Otherwise we want |
| 6264 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 6265 | nop |
| 6266 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) |
| 6267 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) |
| 6268 | If there is a base register we add it to $at before the |
| 6269 | lwc1 instructions. If there is a constant we include it |
| 6270 | in the lwc1 instructions. */ |
| 6271 | used_at = 1; |
| 6272 | expr1.X_add_number = offset_expr.X_add_number; |
| 6273 | offset_expr.X_add_number = 0; |
| 6274 | if (expr1.X_add_number < -0x8000 |
| 6275 | || expr1.X_add_number >= 0x8000 - 4) |
| 6276 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
| 6277 | if (reg_needs_delay (mips_gp_register)) |
| 6278 | gpdel = 4; |
| 6279 | else |
| 6280 | gpdel = 0; |
| 6281 | if (breg == 0) |
| 6282 | off = 0; |
| 6283 | else |
| 6284 | off = 4; |
| 6285 | frag_grow (56); |
| 6286 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", |
| 6287 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); |
| 6288 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 6289 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 6290 | "d,v,t", AT, AT, mips_gp_register); |
| 6291 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 6292 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 6293 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); |
| 6294 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
| 6295 | if (breg != 0) |
| 6296 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 6297 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 6298 | "d,v,t", AT, breg, AT); |
| 6299 | /* Itbl support may require additional care here. */ |
| 6300 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
| 6301 | coproc ? treg + 1 : treg, |
| 6302 | (int) BFD_RELOC_LO16, AT); |
| 6303 | expr1.X_add_number += 4; |
| 6304 | |
| 6305 | /* Set mips_optimize to 2 to avoid inserting an undesired |
| 6306 | nop. */ |
| 6307 | hold_mips_optimize = mips_optimize; |
| 6308 | mips_optimize = 2; |
| 6309 | /* Itbl support may require additional care here. */ |
| 6310 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
| 6311 | coproc ? treg : treg + 1, |
| 6312 | (int) BFD_RELOC_LO16, AT); |
| 6313 | mips_optimize = hold_mips_optimize; |
| 6314 | expr1.X_add_number -= 4; |
| 6315 | |
| 6316 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, |
| 6317 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, |
| 6318 | 8 + gpdel + off, 1, 0), |
| 6319 | offset_expr.X_add_symbol, 0, NULL); |
| 6320 | if (gpdel > 0) |
| 6321 | { |
| 6322 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
| 6323 | p += 4; |
| 6324 | } |
| 6325 | macro_build (p, &icnt, &offset_expr, |
| 6326 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 6327 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, |
| 6328 | mips_gp_register); |
| 6329 | p += 4; |
| 6330 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
| 6331 | p += 4; |
| 6332 | if (breg != 0) |
| 6333 | { |
| 6334 | macro_build (p, &icnt, (expressionS *) NULL, |
| 6335 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 6336 | "d,v,t", AT, breg, AT); |
| 6337 | p += 4; |
| 6338 | } |
| 6339 | /* Itbl support may require additional care here. */ |
| 6340 | macro_build (p, &icnt, &expr1, s, fmt, |
| 6341 | coproc ? treg + 1 : treg, |
| 6342 | (int) BFD_RELOC_LO16, AT); |
| 6343 | p += 4; |
| 6344 | expr1.X_add_number += 4; |
| 6345 | |
| 6346 | /* Set mips_optimize to 2 to avoid inserting an undesired |
| 6347 | nop. */ |
| 6348 | hold_mips_optimize = mips_optimize; |
| 6349 | mips_optimize = 2; |
| 6350 | /* Itbl support may require additional care here. */ |
| 6351 | macro_build (p, &icnt, &expr1, s, fmt, |
| 6352 | coproc ? treg : treg + 1, |
| 6353 | (int) BFD_RELOC_LO16, AT); |
| 6354 | mips_optimize = hold_mips_optimize; |
| 6355 | } |
| 6356 | else if (mips_pic == EMBEDDED_PIC) |
| 6357 | { |
| 6358 | /* If there is no base register, we use |
| 6359 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
| 6360 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) |
| 6361 | If we have a base register, we use |
| 6362 | addu $at,$breg,$gp |
| 6363 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
| 6364 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) |
| 6365 | */ |
| 6366 | if (breg == 0) |
| 6367 | { |
| 6368 | tempreg = mips_gp_register; |
| 6369 | used_at = 0; |
| 6370 | } |
| 6371 | else |
| 6372 | { |
| 6373 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 6374 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 6375 | "d,v,t", AT, breg, mips_gp_register); |
| 6376 | tempreg = AT; |
| 6377 | used_at = 1; |
| 6378 | } |
| 6379 | |
| 6380 | /* Itbl support may require additional care here. */ |
| 6381 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
| 6382 | coproc ? treg + 1 : treg, |
| 6383 | (int) BFD_RELOC_GPREL16, tempreg); |
| 6384 | offset_expr.X_add_number += 4; |
| 6385 | /* Itbl support may require additional care here. */ |
| 6386 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
| 6387 | coproc ? treg : treg + 1, |
| 6388 | (int) BFD_RELOC_GPREL16, tempreg); |
| 6389 | } |
| 6390 | else |
| 6391 | abort (); |
| 6392 | |
| 6393 | if (! used_at) |
| 6394 | return; |
| 6395 | |
| 6396 | break; |
| 6397 | |
| 6398 | case M_LD_OB: |
| 6399 | s = "lw"; |
| 6400 | goto sd_ob; |
| 6401 | case M_SD_OB: |
| 6402 | s = "sw"; |
| 6403 | sd_ob: |
| 6404 | assert (HAVE_32BIT_ADDRESSES); |
| 6405 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
| 6406 | (int) BFD_RELOC_LO16, breg); |
| 6407 | offset_expr.X_add_number += 4; |
| 6408 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, |
| 6409 | (int) BFD_RELOC_LO16, breg); |
| 6410 | return; |
| 6411 | |
| 6412 | /* New code added to support COPZ instructions. |
| 6413 | This code builds table entries out of the macros in mip_opcodes. |
| 6414 | R4000 uses interlocks to handle coproc delays. |
| 6415 | Other chips (like the R3000) require nops to be inserted for delays. |
| 6416 | |
| 6417 | FIXME: Currently, we require that the user handle delays. |
| 6418 | In order to fill delay slots for non-interlocked chips, |
| 6419 | we must have a way to specify delays based on the coprocessor. |
| 6420 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. |
| 6421 | What are the side-effects of the cop instruction? |
| 6422 | What cache support might we have and what are its effects? |
| 6423 | Both coprocessor & memory require delays. how long??? |
| 6424 | What registers are read/set/modified? |
| 6425 | |
| 6426 | If an itbl is provided to interpret cop instructions, |
| 6427 | this knowledge can be encoded in the itbl spec. */ |
| 6428 | |
| 6429 | case M_COP0: |
| 6430 | s = "c0"; |
| 6431 | goto copz; |
| 6432 | case M_COP1: |
| 6433 | s = "c1"; |
| 6434 | goto copz; |
| 6435 | case M_COP2: |
| 6436 | s = "c2"; |
| 6437 | goto copz; |
| 6438 | case M_COP3: |
| 6439 | s = "c3"; |
| 6440 | copz: |
| 6441 | /* For now we just do C (same as Cz). The parameter will be |
| 6442 | stored in insn_opcode by mips_ip. */ |
| 6443 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C", |
| 6444 | ip->insn_opcode); |
| 6445 | return; |
| 6446 | |
| 6447 | case M_MOVE: |
| 6448 | move_register (&icnt, dreg, sreg); |
| 6449 | return; |
| 6450 | |
| 6451 | #ifdef LOSING_COMPILER |
| 6452 | default: |
| 6453 | /* Try and see if this is a new itbl instruction. |
| 6454 | This code builds table entries out of the macros in mip_opcodes. |
| 6455 | FIXME: For now we just assemble the expression and pass it's |
| 6456 | value along as a 32-bit immediate. |
| 6457 | We may want to have the assembler assemble this value, |
| 6458 | so that we gain the assembler's knowledge of delay slots, |
| 6459 | symbols, etc. |
| 6460 | Would it be more efficient to use mask (id) here? */ |
| 6461 | if (itbl_have_entries |
| 6462 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
| 6463 | { |
| 6464 | s = ip->insn_mo->name; |
| 6465 | s2 = "cop3"; |
| 6466 | coproc = ITBL_DECODE_PNUM (immed_expr);; |
| 6467 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); |
| 6468 | return; |
| 6469 | } |
| 6470 | macro2 (ip); |
| 6471 | return; |
| 6472 | } |
| 6473 | if (mips_opts.noat) |
| 6474 | as_warn (_("Macro used $at after \".set noat\"")); |
| 6475 | } |
| 6476 | |
| 6477 | static void |
| 6478 | macro2 (ip) |
| 6479 | struct mips_cl_insn *ip; |
| 6480 | { |
| 6481 | register int treg, sreg, dreg, breg; |
| 6482 | int tempreg; |
| 6483 | int mask; |
| 6484 | int icnt = 0; |
| 6485 | int used_at; |
| 6486 | expressionS expr1; |
| 6487 | const char *s; |
| 6488 | const char *s2; |
| 6489 | const char *fmt; |
| 6490 | int likely = 0; |
| 6491 | int dbl = 0; |
| 6492 | int coproc = 0; |
| 6493 | int lr = 0; |
| 6494 | int imm = 0; |
| 6495 | int off; |
| 6496 | offsetT maxnum; |
| 6497 | bfd_reloc_code_real_type r; |
| 6498 | char *p; |
| 6499 | |
| 6500 | treg = (ip->insn_opcode >> 16) & 0x1f; |
| 6501 | dreg = (ip->insn_opcode >> 11) & 0x1f; |
| 6502 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; |
| 6503 | mask = ip->insn_mo->mask; |
| 6504 | |
| 6505 | expr1.X_op = O_constant; |
| 6506 | expr1.X_op_symbol = NULL; |
| 6507 | expr1.X_add_symbol = NULL; |
| 6508 | expr1.X_add_number = 1; |
| 6509 | |
| 6510 | switch (mask) |
| 6511 | { |
| 6512 | #endif /* LOSING_COMPILER */ |
| 6513 | |
| 6514 | case M_DMUL: |
| 6515 | dbl = 1; |
| 6516 | case M_MUL: |
| 6517 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 6518 | dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
| 6519 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", |
| 6520 | dreg); |
| 6521 | return; |
| 6522 | |
| 6523 | case M_DMUL_I: |
| 6524 | dbl = 1; |
| 6525 | case M_MUL_I: |
| 6526 | /* The MIPS assembler some times generates shifts and adds. I'm |
| 6527 | not trying to be that fancy. GCC should do this for us |
| 6528 | anyway. */ |
| 6529 | load_register (&icnt, AT, &imm_expr, dbl); |
| 6530 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 6531 | dbl ? "dmult" : "mult", "s,t", sreg, AT); |
| 6532 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", |
| 6533 | dreg); |
| 6534 | break; |
| 6535 | |
| 6536 | case M_DMULO_I: |
| 6537 | dbl = 1; |
| 6538 | case M_MULO_I: |
| 6539 | imm = 1; |
| 6540 | goto do_mulo; |
| 6541 | |
| 6542 | case M_DMULO: |
| 6543 | dbl = 1; |
| 6544 | case M_MULO: |
| 6545 | do_mulo: |
| 6546 | mips_emit_delays (true); |
| 6547 | ++mips_opts.noreorder; |
| 6548 | mips_any_noreorder = 1; |
| 6549 | if (imm) |
| 6550 | load_register (&icnt, AT, &imm_expr, dbl); |
| 6551 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 6552 | dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); |
| 6553 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", |
| 6554 | dreg); |
| 6555 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 6556 | dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); |
| 6557 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d", |
| 6558 | AT); |
| 6559 | if (mips_trap) |
| 6560 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", |
| 6561 | "s,t,q", dreg, AT, 6); |
| 6562 | else |
| 6563 | { |
| 6564 | expr1.X_add_number = 8; |
| 6565 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, |
| 6566 | AT); |
| 6567 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
| 6568 | 0); |
| 6569 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
| 6570 | "c", 6); |
| 6571 | } |
| 6572 | --mips_opts.noreorder; |
| 6573 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", dreg); |
| 6574 | break; |
| 6575 | |
| 6576 | case M_DMULOU_I: |
| 6577 | dbl = 1; |
| 6578 | case M_MULOU_I: |
| 6579 | imm = 1; |
| 6580 | goto do_mulou; |
| 6581 | |
| 6582 | case M_DMULOU: |
| 6583 | dbl = 1; |
| 6584 | case M_MULOU: |
| 6585 | do_mulou: |
| 6586 | mips_emit_delays (true); |
| 6587 | ++mips_opts.noreorder; |
| 6588 | mips_any_noreorder = 1; |
| 6589 | if (imm) |
| 6590 | load_register (&icnt, AT, &imm_expr, dbl); |
| 6591 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 6592 | dbl ? "dmultu" : "multu", |
| 6593 | "s,t", sreg, imm ? AT : treg); |
| 6594 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d", |
| 6595 | AT); |
| 6596 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", |
| 6597 | dreg); |
| 6598 | if (mips_trap) |
| 6599 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", |
| 6600 | "s,t,q", AT, 0, 6); |
| 6601 | else |
| 6602 | { |
| 6603 | expr1.X_add_number = 8; |
| 6604 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); |
| 6605 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
| 6606 | 0); |
| 6607 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
| 6608 | "c", 6); |
| 6609 | } |
| 6610 | --mips_opts.noreorder; |
| 6611 | break; |
| 6612 | |
| 6613 | case M_DROL: |
| 6614 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu", |
| 6615 | "d,v,t", AT, 0, treg); |
| 6616 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv", |
| 6617 | "d,t,s", AT, sreg, AT); |
| 6618 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv", |
| 6619 | "d,t,s", dreg, sreg, treg); |
| 6620 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", |
| 6621 | "d,v,t", dreg, dreg, AT); |
| 6622 | break; |
| 6623 | |
| 6624 | case M_ROL: |
| 6625 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu", |
| 6626 | "d,v,t", AT, 0, treg); |
| 6627 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv", |
| 6628 | "d,t,s", AT, sreg, AT); |
| 6629 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv", |
| 6630 | "d,t,s", dreg, sreg, treg); |
| 6631 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", |
| 6632 | "d,v,t", dreg, dreg, AT); |
| 6633 | break; |
| 6634 | |
| 6635 | case M_DROL_I: |
| 6636 | { |
| 6637 | unsigned int rot; |
| 6638 | char *l, *r; |
| 6639 | |
| 6640 | if (imm_expr.X_op != O_constant) |
| 6641 | as_bad (_("rotate count too large")); |
| 6642 | rot = imm_expr.X_add_number & 0x3f; |
| 6643 | if (! rot) |
| 6644 | break; |
| 6645 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
| 6646 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
| 6647 | rot &= 0x1f; |
| 6648 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l, |
| 6649 | "d,w,<", AT, sreg, rot); |
| 6650 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r, |
| 6651 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); |
| 6652 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", |
| 6653 | "d,v,t", dreg, dreg, AT); |
| 6654 | } |
| 6655 | break; |
| 6656 | |
| 6657 | case M_ROL_I: |
| 6658 | { |
| 6659 | unsigned int rot; |
| 6660 | |
| 6661 | if (imm_expr.X_op != O_constant) |
| 6662 | as_bad (_("rotate count too large")); |
| 6663 | rot = imm_expr.X_add_number & 0x1f; |
| 6664 | if (! rot) |
| 6665 | break; |
| 6666 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", |
| 6667 | "d,w,<", AT, sreg, rot); |
| 6668 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", |
| 6669 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); |
| 6670 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", |
| 6671 | "d,v,t", dreg, dreg, AT); |
| 6672 | } |
| 6673 | break; |
| 6674 | |
| 6675 | case M_DROR: |
| 6676 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu", |
| 6677 | "d,v,t", AT, 0, treg); |
| 6678 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv", |
| 6679 | "d,t,s", AT, sreg, AT); |
| 6680 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv", |
| 6681 | "d,t,s", dreg, sreg, treg); |
| 6682 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", |
| 6683 | "d,v,t", dreg, dreg, AT); |
| 6684 | break; |
| 6685 | |
| 6686 | case M_ROR: |
| 6687 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu", |
| 6688 | "d,v,t", AT, 0, treg); |
| 6689 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv", |
| 6690 | "d,t,s", AT, sreg, AT); |
| 6691 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv", |
| 6692 | "d,t,s", dreg, sreg, treg); |
| 6693 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", |
| 6694 | "d,v,t", dreg, dreg, AT); |
| 6695 | break; |
| 6696 | |
| 6697 | case M_DROR_I: |
| 6698 | { |
| 6699 | unsigned int rot; |
| 6700 | char *l, *r; |
| 6701 | |
| 6702 | if (imm_expr.X_op != O_constant) |
| 6703 | as_bad (_("rotate count too large")); |
| 6704 | rot = imm_expr.X_add_number & 0x3f; |
| 6705 | if (! rot) |
| 6706 | break; |
| 6707 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
| 6708 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
| 6709 | rot &= 0x1f; |
| 6710 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r, |
| 6711 | "d,w,<", AT, sreg, rot); |
| 6712 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l, |
| 6713 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); |
| 6714 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", |
| 6715 | "d,v,t", dreg, dreg, AT); |
| 6716 | } |
| 6717 | break; |
| 6718 | |
| 6719 | case M_ROR_I: |
| 6720 | { |
| 6721 | unsigned int rot; |
| 6722 | |
| 6723 | if (imm_expr.X_op != O_constant) |
| 6724 | as_bad (_("rotate count too large")); |
| 6725 | rot = imm_expr.X_add_number & 0x1f; |
| 6726 | if (! rot) |
| 6727 | break; |
| 6728 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", |
| 6729 | "d,w,<", AT, sreg, rot); |
| 6730 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", |
| 6731 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); |
| 6732 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", |
| 6733 | "d,v,t", dreg, dreg, AT); |
| 6734 | } |
| 6735 | break; |
| 6736 | |
| 6737 | case M_S_DOB: |
| 6738 | if (mips_arch == CPU_R4650) |
| 6739 | { |
| 6740 | as_bad (_("opcode not supported on this processor")); |
| 6741 | return; |
| 6742 | } |
| 6743 | assert (mips_opts.isa == ISA_MIPS1); |
| 6744 | /* Even on a big endian machine $fn comes before $fn+1. We have |
| 6745 | to adjust when storing to memory. */ |
| 6746 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
| 6747 | target_big_endian ? treg + 1 : treg, |
| 6748 | (int) BFD_RELOC_LO16, breg); |
| 6749 | offset_expr.X_add_number += 4; |
| 6750 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
| 6751 | target_big_endian ? treg : treg + 1, |
| 6752 | (int) BFD_RELOC_LO16, breg); |
| 6753 | return; |
| 6754 | |
| 6755 | case M_SEQ: |
| 6756 | if (sreg == 0) |
| 6757 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
| 6758 | treg, (int) BFD_RELOC_LO16); |
| 6759 | else if (treg == 0) |
| 6760 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
| 6761 | sreg, (int) BFD_RELOC_LO16); |
| 6762 | else |
| 6763 | { |
| 6764 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
| 6765 | "d,v,t", dreg, sreg, treg); |
| 6766 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
| 6767 | dreg, (int) BFD_RELOC_LO16); |
| 6768 | } |
| 6769 | return; |
| 6770 | |
| 6771 | case M_SEQ_I: |
| 6772 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
| 6773 | { |
| 6774 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
| 6775 | sreg, (int) BFD_RELOC_LO16); |
| 6776 | return; |
| 6777 | } |
| 6778 | if (sreg == 0) |
| 6779 | { |
| 6780 | as_warn (_("Instruction %s: result is always false"), |
| 6781 | ip->insn_mo->name); |
| 6782 | move_register (&icnt, dreg, 0); |
| 6783 | return; |
| 6784 | } |
| 6785 | if (imm_expr.X_op == O_constant |
| 6786 | && imm_expr.X_add_number >= 0 |
| 6787 | && imm_expr.X_add_number < 0x10000) |
| 6788 | { |
| 6789 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
| 6790 | sreg, (int) BFD_RELOC_LO16); |
| 6791 | used_at = 0; |
| 6792 | } |
| 6793 | else if (imm_expr.X_op == O_constant |
| 6794 | && imm_expr.X_add_number > -0x8000 |
| 6795 | && imm_expr.X_add_number < 0) |
| 6796 | { |
| 6797 | imm_expr.X_add_number = -imm_expr.X_add_number; |
| 6798 | macro_build ((char *) NULL, &icnt, &imm_expr, |
| 6799 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
| 6800 | "t,r,j", dreg, sreg, |
| 6801 | (int) BFD_RELOC_LO16); |
| 6802 | used_at = 0; |
| 6803 | } |
| 6804 | else |
| 6805 | { |
| 6806 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
| 6807 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
| 6808 | "d,v,t", dreg, sreg, AT); |
| 6809 | used_at = 1; |
| 6810 | } |
| 6811 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
| 6812 | (int) BFD_RELOC_LO16); |
| 6813 | if (used_at) |
| 6814 | break; |
| 6815 | return; |
| 6816 | |
| 6817 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ |
| 6818 | s = "slt"; |
| 6819 | goto sge; |
| 6820 | case M_SGEU: |
| 6821 | s = "sltu"; |
| 6822 | sge: |
| 6823 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
| 6824 | dreg, sreg, treg); |
| 6825 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
| 6826 | (int) BFD_RELOC_LO16); |
| 6827 | return; |
| 6828 | |
| 6829 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
| 6830 | case M_SGEU_I: |
| 6831 | if (imm_expr.X_op == O_constant |
| 6832 | && imm_expr.X_add_number >= -0x8000 |
| 6833 | && imm_expr.X_add_number < 0x8000) |
| 6834 | { |
| 6835 | macro_build ((char *) NULL, &icnt, &imm_expr, |
| 6836 | mask == M_SGE_I ? "slti" : "sltiu", |
| 6837 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
| 6838 | used_at = 0; |
| 6839 | } |
| 6840 | else |
| 6841 | { |
| 6842 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
| 6843 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 6844 | mask == M_SGE_I ? "slt" : "sltu", "d,v,t", dreg, sreg, |
| 6845 | AT); |
| 6846 | used_at = 1; |
| 6847 | } |
| 6848 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
| 6849 | (int) BFD_RELOC_LO16); |
| 6850 | if (used_at) |
| 6851 | break; |
| 6852 | return; |
| 6853 | |
| 6854 | case M_SGT: /* sreg > treg <==> treg < sreg */ |
| 6855 | s = "slt"; |
| 6856 | goto sgt; |
| 6857 | case M_SGTU: |
| 6858 | s = "sltu"; |
| 6859 | sgt: |
| 6860 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
| 6861 | dreg, treg, sreg); |
| 6862 | return; |
| 6863 | |
| 6864 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
| 6865 | s = "slt"; |
| 6866 | goto sgti; |
| 6867 | case M_SGTU_I: |
| 6868 | s = "sltu"; |
| 6869 | sgti: |
| 6870 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
| 6871 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
| 6872 | dreg, AT, sreg); |
| 6873 | break; |
| 6874 | |
| 6875 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
| 6876 | s = "slt"; |
| 6877 | goto sle; |
| 6878 | case M_SLEU: |
| 6879 | s = "sltu"; |
| 6880 | sle: |
| 6881 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
| 6882 | dreg, treg, sreg); |
| 6883 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
| 6884 | (int) BFD_RELOC_LO16); |
| 6885 | return; |
| 6886 | |
| 6887 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
| 6888 | s = "slt"; |
| 6889 | goto slei; |
| 6890 | case M_SLEU_I: |
| 6891 | s = "sltu"; |
| 6892 | slei: |
| 6893 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
| 6894 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
| 6895 | dreg, AT, sreg); |
| 6896 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
| 6897 | (int) BFD_RELOC_LO16); |
| 6898 | break; |
| 6899 | |
| 6900 | case M_SLT_I: |
| 6901 | if (imm_expr.X_op == O_constant |
| 6902 | && imm_expr.X_add_number >= -0x8000 |
| 6903 | && imm_expr.X_add_number < 0x8000) |
| 6904 | { |
| 6905 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
| 6906 | dreg, sreg, (int) BFD_RELOC_LO16); |
| 6907 | return; |
| 6908 | } |
| 6909 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
| 6910 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
| 6911 | dreg, sreg, AT); |
| 6912 | break; |
| 6913 | |
| 6914 | case M_SLTU_I: |
| 6915 | if (imm_expr.X_op == O_constant |
| 6916 | && imm_expr.X_add_number >= -0x8000 |
| 6917 | && imm_expr.X_add_number < 0x8000) |
| 6918 | { |
| 6919 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
| 6920 | dreg, sreg, (int) BFD_RELOC_LO16); |
| 6921 | return; |
| 6922 | } |
| 6923 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
| 6924 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
| 6925 | "d,v,t", dreg, sreg, AT); |
| 6926 | break; |
| 6927 | |
| 6928 | case M_SNE: |
| 6929 | if (sreg == 0) |
| 6930 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
| 6931 | "d,v,t", dreg, 0, treg); |
| 6932 | else if (treg == 0) |
| 6933 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
| 6934 | "d,v,t", dreg, 0, sreg); |
| 6935 | else |
| 6936 | { |
| 6937 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
| 6938 | "d,v,t", dreg, sreg, treg); |
| 6939 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
| 6940 | "d,v,t", dreg, 0, dreg); |
| 6941 | } |
| 6942 | return; |
| 6943 | |
| 6944 | case M_SNE_I: |
| 6945 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
| 6946 | { |
| 6947 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
| 6948 | "d,v,t", dreg, 0, sreg); |
| 6949 | return; |
| 6950 | } |
| 6951 | if (sreg == 0) |
| 6952 | { |
| 6953 | as_warn (_("Instruction %s: result is always true"), |
| 6954 | ip->insn_mo->name); |
| 6955 | macro_build ((char *) NULL, &icnt, &expr1, |
| 6956 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
| 6957 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
| 6958 | return; |
| 6959 | } |
| 6960 | if (imm_expr.X_op == O_constant |
| 6961 | && imm_expr.X_add_number >= 0 |
| 6962 | && imm_expr.X_add_number < 0x10000) |
| 6963 | { |
| 6964 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
| 6965 | dreg, sreg, (int) BFD_RELOC_LO16); |
| 6966 | used_at = 0; |
| 6967 | } |
| 6968 | else if (imm_expr.X_op == O_constant |
| 6969 | && imm_expr.X_add_number > -0x8000 |
| 6970 | && imm_expr.X_add_number < 0) |
| 6971 | { |
| 6972 | imm_expr.X_add_number = -imm_expr.X_add_number; |
| 6973 | macro_build ((char *) NULL, &icnt, &imm_expr, |
| 6974 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
| 6975 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
| 6976 | used_at = 0; |
| 6977 | } |
| 6978 | else |
| 6979 | { |
| 6980 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
| 6981 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
| 6982 | "d,v,t", dreg, sreg, AT); |
| 6983 | used_at = 1; |
| 6984 | } |
| 6985 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
| 6986 | "d,v,t", dreg, 0, dreg); |
| 6987 | if (used_at) |
| 6988 | break; |
| 6989 | return; |
| 6990 | |
| 6991 | case M_DSUB_I: |
| 6992 | dbl = 1; |
| 6993 | case M_SUB_I: |
| 6994 | if (imm_expr.X_op == O_constant |
| 6995 | && imm_expr.X_add_number > -0x8000 |
| 6996 | && imm_expr.X_add_number <= 0x8000) |
| 6997 | { |
| 6998 | imm_expr.X_add_number = -imm_expr.X_add_number; |
| 6999 | macro_build ((char *) NULL, &icnt, &imm_expr, |
| 7000 | dbl ? "daddi" : "addi", |
| 7001 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
| 7002 | return; |
| 7003 | } |
| 7004 | load_register (&icnt, AT, &imm_expr, dbl); |
| 7005 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 7006 | dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); |
| 7007 | break; |
| 7008 | |
| 7009 | case M_DSUBU_I: |
| 7010 | dbl = 1; |
| 7011 | case M_SUBU_I: |
| 7012 | if (imm_expr.X_op == O_constant |
| 7013 | && imm_expr.X_add_number > -0x8000 |
| 7014 | && imm_expr.X_add_number <= 0x8000) |
| 7015 | { |
| 7016 | imm_expr.X_add_number = -imm_expr.X_add_number; |
| 7017 | macro_build ((char *) NULL, &icnt, &imm_expr, |
| 7018 | dbl ? "daddiu" : "addiu", |
| 7019 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
| 7020 | return; |
| 7021 | } |
| 7022 | load_register (&icnt, AT, &imm_expr, dbl); |
| 7023 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 7024 | dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); |
| 7025 | break; |
| 7026 | |
| 7027 | case M_TEQ_I: |
| 7028 | s = "teq"; |
| 7029 | goto trap; |
| 7030 | case M_TGE_I: |
| 7031 | s = "tge"; |
| 7032 | goto trap; |
| 7033 | case M_TGEU_I: |
| 7034 | s = "tgeu"; |
| 7035 | goto trap; |
| 7036 | case M_TLT_I: |
| 7037 | s = "tlt"; |
| 7038 | goto trap; |
| 7039 | case M_TLTU_I: |
| 7040 | s = "tltu"; |
| 7041 | goto trap; |
| 7042 | case M_TNE_I: |
| 7043 | s = "tne"; |
| 7044 | trap: |
| 7045 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
| 7046 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "s,t", sreg, |
| 7047 | AT); |
| 7048 | break; |
| 7049 | |
| 7050 | case M_TRUNCWS: |
| 7051 | case M_TRUNCWD: |
| 7052 | assert (mips_opts.isa == ISA_MIPS1); |
| 7053 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
| 7054 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ |
| 7055 | |
| 7056 | /* |
| 7057 | * Is the double cfc1 instruction a bug in the mips assembler; |
| 7058 | * or is there a reason for it? |
| 7059 | */ |
| 7060 | mips_emit_delays (true); |
| 7061 | ++mips_opts.noreorder; |
| 7062 | mips_any_noreorder = 1; |
| 7063 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G", |
| 7064 | treg, RA); |
| 7065 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G", |
| 7066 | treg, RA); |
| 7067 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
| 7068 | expr1.X_add_number = 3; |
| 7069 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
| 7070 | (int) BFD_RELOC_LO16); |
| 7071 | expr1.X_add_number = 2; |
| 7072 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
| 7073 | (int) BFD_RELOC_LO16); |
| 7074 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G", |
| 7075 | AT, RA); |
| 7076 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
| 7077 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 7078 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
| 7079 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G", |
| 7080 | treg, RA); |
| 7081 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
| 7082 | --mips_opts.noreorder; |
| 7083 | break; |
| 7084 | |
| 7085 | case M_ULH: |
| 7086 | s = "lb"; |
| 7087 | goto ulh; |
| 7088 | case M_ULHU: |
| 7089 | s = "lbu"; |
| 7090 | ulh: |
| 7091 | if (offset_expr.X_add_number >= 0x7fff) |
| 7092 | as_bad (_("operand overflow")); |
| 7093 | /* avoid load delay */ |
| 7094 | if (! target_big_endian) |
| 7095 | ++offset_expr.X_add_number; |
| 7096 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
| 7097 | (int) BFD_RELOC_LO16, breg); |
| 7098 | if (! target_big_endian) |
| 7099 | --offset_expr.X_add_number; |
| 7100 | else |
| 7101 | ++offset_expr.X_add_number; |
| 7102 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
| 7103 | (int) BFD_RELOC_LO16, breg); |
| 7104 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
| 7105 | treg, treg, 8); |
| 7106 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", |
| 7107 | treg, treg, AT); |
| 7108 | break; |
| 7109 | |
| 7110 | case M_ULD: |
| 7111 | s = "ldl"; |
| 7112 | s2 = "ldr"; |
| 7113 | off = 7; |
| 7114 | goto ulw; |
| 7115 | case M_ULW: |
| 7116 | s = "lwl"; |
| 7117 | s2 = "lwr"; |
| 7118 | off = 3; |
| 7119 | ulw: |
| 7120 | if (offset_expr.X_add_number >= 0x8000 - off) |
| 7121 | as_bad (_("operand overflow")); |
| 7122 | if (! target_big_endian) |
| 7123 | offset_expr.X_add_number += off; |
| 7124 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
| 7125 | (int) BFD_RELOC_LO16, breg); |
| 7126 | if (! target_big_endian) |
| 7127 | offset_expr.X_add_number -= off; |
| 7128 | else |
| 7129 | offset_expr.X_add_number += off; |
| 7130 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, |
| 7131 | (int) BFD_RELOC_LO16, breg); |
| 7132 | return; |
| 7133 | |
| 7134 | case M_ULD_A: |
| 7135 | s = "ldl"; |
| 7136 | s2 = "ldr"; |
| 7137 | off = 7; |
| 7138 | goto ulwa; |
| 7139 | case M_ULW_A: |
| 7140 | s = "lwl"; |
| 7141 | s2 = "lwr"; |
| 7142 | off = 3; |
| 7143 | ulwa: |
| 7144 | used_at = 1; |
| 7145 | load_address (&icnt, AT, &offset_expr, &used_at); |
| 7146 | if (breg != 0) |
| 7147 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 7148 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 7149 | "d,v,t", AT, AT, breg); |
| 7150 | if (! target_big_endian) |
| 7151 | expr1.X_add_number = off; |
| 7152 | else |
| 7153 | expr1.X_add_number = 0; |
| 7154 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, |
| 7155 | (int) BFD_RELOC_LO16, AT); |
| 7156 | if (! target_big_endian) |
| 7157 | expr1.X_add_number = 0; |
| 7158 | else |
| 7159 | expr1.X_add_number = off; |
| 7160 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, |
| 7161 | (int) BFD_RELOC_LO16, AT); |
| 7162 | break; |
| 7163 | |
| 7164 | case M_ULH_A: |
| 7165 | case M_ULHU_A: |
| 7166 | used_at = 1; |
| 7167 | load_address (&icnt, AT, &offset_expr, &used_at); |
| 7168 | if (breg != 0) |
| 7169 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 7170 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 7171 | "d,v,t", AT, AT, breg); |
| 7172 | if (target_big_endian) |
| 7173 | expr1.X_add_number = 0; |
| 7174 | macro_build ((char *) NULL, &icnt, &expr1, |
| 7175 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, |
| 7176 | (int) BFD_RELOC_LO16, AT); |
| 7177 | if (target_big_endian) |
| 7178 | expr1.X_add_number = 1; |
| 7179 | else |
| 7180 | expr1.X_add_number = 0; |
| 7181 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, |
| 7182 | (int) BFD_RELOC_LO16, AT); |
| 7183 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
| 7184 | treg, treg, 8); |
| 7185 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", |
| 7186 | treg, treg, AT); |
| 7187 | break; |
| 7188 | |
| 7189 | case M_USH: |
| 7190 | if (offset_expr.X_add_number >= 0x7fff) |
| 7191 | as_bad (_("operand overflow")); |
| 7192 | if (target_big_endian) |
| 7193 | ++offset_expr.X_add_number; |
| 7194 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
| 7195 | (int) BFD_RELOC_LO16, breg); |
| 7196 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<", |
| 7197 | AT, treg, 8); |
| 7198 | if (target_big_endian) |
| 7199 | --offset_expr.X_add_number; |
| 7200 | else |
| 7201 | ++offset_expr.X_add_number; |
| 7202 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
| 7203 | (int) BFD_RELOC_LO16, breg); |
| 7204 | break; |
| 7205 | |
| 7206 | case M_USD: |
| 7207 | s = "sdl"; |
| 7208 | s2 = "sdr"; |
| 7209 | off = 7; |
| 7210 | goto usw; |
| 7211 | case M_USW: |
| 7212 | s = "swl"; |
| 7213 | s2 = "swr"; |
| 7214 | off = 3; |
| 7215 | usw: |
| 7216 | if (offset_expr.X_add_number >= 0x8000 - off) |
| 7217 | as_bad (_("operand overflow")); |
| 7218 | if (! target_big_endian) |
| 7219 | offset_expr.X_add_number += off; |
| 7220 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
| 7221 | (int) BFD_RELOC_LO16, breg); |
| 7222 | if (! target_big_endian) |
| 7223 | offset_expr.X_add_number -= off; |
| 7224 | else |
| 7225 | offset_expr.X_add_number += off; |
| 7226 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, |
| 7227 | (int) BFD_RELOC_LO16, breg); |
| 7228 | return; |
| 7229 | |
| 7230 | case M_USD_A: |
| 7231 | s = "sdl"; |
| 7232 | s2 = "sdr"; |
| 7233 | off = 7; |
| 7234 | goto uswa; |
| 7235 | case M_USW_A: |
| 7236 | s = "swl"; |
| 7237 | s2 = "swr"; |
| 7238 | off = 3; |
| 7239 | uswa: |
| 7240 | used_at = 1; |
| 7241 | load_address (&icnt, AT, &offset_expr, &used_at); |
| 7242 | if (breg != 0) |
| 7243 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 7244 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 7245 | "d,v,t", AT, AT, breg); |
| 7246 | if (! target_big_endian) |
| 7247 | expr1.X_add_number = off; |
| 7248 | else |
| 7249 | expr1.X_add_number = 0; |
| 7250 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, |
| 7251 | (int) BFD_RELOC_LO16, AT); |
| 7252 | if (! target_big_endian) |
| 7253 | expr1.X_add_number = 0; |
| 7254 | else |
| 7255 | expr1.X_add_number = off; |
| 7256 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, |
| 7257 | (int) BFD_RELOC_LO16, AT); |
| 7258 | break; |
| 7259 | |
| 7260 | case M_USH_A: |
| 7261 | used_at = 1; |
| 7262 | load_address (&icnt, AT, &offset_expr, &used_at); |
| 7263 | if (breg != 0) |
| 7264 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 7265 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 7266 | "d,v,t", AT, AT, breg); |
| 7267 | if (! target_big_endian) |
| 7268 | expr1.X_add_number = 0; |
| 7269 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, |
| 7270 | (int) BFD_RELOC_LO16, AT); |
| 7271 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<", |
| 7272 | treg, treg, 8); |
| 7273 | if (! target_big_endian) |
| 7274 | expr1.X_add_number = 1; |
| 7275 | else |
| 7276 | expr1.X_add_number = 0; |
| 7277 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, |
| 7278 | (int) BFD_RELOC_LO16, AT); |
| 7279 | if (! target_big_endian) |
| 7280 | expr1.X_add_number = 0; |
| 7281 | else |
| 7282 | expr1.X_add_number = 1; |
| 7283 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, |
| 7284 | (int) BFD_RELOC_LO16, AT); |
| 7285 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
| 7286 | treg, treg, 8); |
| 7287 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", |
| 7288 | treg, treg, AT); |
| 7289 | break; |
| 7290 | |
| 7291 | default: |
| 7292 | /* FIXME: Check if this is one of the itbl macros, since they |
| 7293 | are added dynamically. */ |
| 7294 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
| 7295 | break; |
| 7296 | } |
| 7297 | if (mips_opts.noat) |
| 7298 | as_warn (_("Macro used $at after \".set noat\"")); |
| 7299 | } |
| 7300 | |
| 7301 | /* Implement macros in mips16 mode. */ |
| 7302 | |
| 7303 | static void |
| 7304 | mips16_macro (ip) |
| 7305 | struct mips_cl_insn *ip; |
| 7306 | { |
| 7307 | int mask; |
| 7308 | int xreg, yreg, zreg, tmp; |
| 7309 | int icnt; |
| 7310 | expressionS expr1; |
| 7311 | int dbl; |
| 7312 | const char *s, *s2, *s3; |
| 7313 | |
| 7314 | mask = ip->insn_mo->mask; |
| 7315 | |
| 7316 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; |
| 7317 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; |
| 7318 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; |
| 7319 | |
| 7320 | icnt = 0; |
| 7321 | |
| 7322 | expr1.X_op = O_constant; |
| 7323 | expr1.X_op_symbol = NULL; |
| 7324 | expr1.X_add_symbol = NULL; |
| 7325 | expr1.X_add_number = 1; |
| 7326 | |
| 7327 | dbl = 0; |
| 7328 | |
| 7329 | switch (mask) |
| 7330 | { |
| 7331 | default: |
| 7332 | internalError (); |
| 7333 | |
| 7334 | case M_DDIV_3: |
| 7335 | dbl = 1; |
| 7336 | case M_DIV_3: |
| 7337 | s = "mflo"; |
| 7338 | goto do_div3; |
| 7339 | case M_DREM_3: |
| 7340 | dbl = 1; |
| 7341 | case M_REM_3: |
| 7342 | s = "mfhi"; |
| 7343 | do_div3: |
| 7344 | mips_emit_delays (true); |
| 7345 | ++mips_opts.noreorder; |
| 7346 | mips_any_noreorder = 1; |
| 7347 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 7348 | dbl ? "ddiv" : "div", |
| 7349 | "0,x,y", xreg, yreg); |
| 7350 | expr1.X_add_number = 2; |
| 7351 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
| 7352 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", "6", |
| 7353 | 7); |
| 7354 | |
| 7355 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
| 7356 | since that causes an overflow. We should do that as well, |
| 7357 | but I don't see how to do the comparisons without a temporary |
| 7358 | register. */ |
| 7359 | --mips_opts.noreorder; |
| 7360 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x", zreg); |
| 7361 | break; |
| 7362 | |
| 7363 | case M_DIVU_3: |
| 7364 | s = "divu"; |
| 7365 | s2 = "mflo"; |
| 7366 | goto do_divu3; |
| 7367 | case M_REMU_3: |
| 7368 | s = "divu"; |
| 7369 | s2 = "mfhi"; |
| 7370 | goto do_divu3; |
| 7371 | case M_DDIVU_3: |
| 7372 | s = "ddivu"; |
| 7373 | s2 = "mflo"; |
| 7374 | goto do_divu3; |
| 7375 | case M_DREMU_3: |
| 7376 | s = "ddivu"; |
| 7377 | s2 = "mfhi"; |
| 7378 | do_divu3: |
| 7379 | mips_emit_delays (true); |
| 7380 | ++mips_opts.noreorder; |
| 7381 | mips_any_noreorder = 1; |
| 7382 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "0,x,y", |
| 7383 | xreg, yreg); |
| 7384 | expr1.X_add_number = 2; |
| 7385 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
| 7386 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
| 7387 | "6", 7); |
| 7388 | --mips_opts.noreorder; |
| 7389 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "x", zreg); |
| 7390 | break; |
| 7391 | |
| 7392 | case M_DMUL: |
| 7393 | dbl = 1; |
| 7394 | case M_MUL: |
| 7395 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 7396 | dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
| 7397 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "x", |
| 7398 | zreg); |
| 7399 | return; |
| 7400 | |
| 7401 | case M_DSUBU_I: |
| 7402 | dbl = 1; |
| 7403 | goto do_subu; |
| 7404 | case M_SUBU_I: |
| 7405 | do_subu: |
| 7406 | if (imm_expr.X_op != O_constant) |
| 7407 | as_bad (_("Unsupported large constant")); |
| 7408 | imm_expr.X_add_number = -imm_expr.X_add_number; |
| 7409 | macro_build ((char *) NULL, &icnt, &imm_expr, |
| 7410 | dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
| 7411 | break; |
| 7412 | |
| 7413 | case M_SUBU_I_2: |
| 7414 | if (imm_expr.X_op != O_constant) |
| 7415 | as_bad (_("Unsupported large constant")); |
| 7416 | imm_expr.X_add_number = -imm_expr.X_add_number; |
| 7417 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", |
| 7418 | "x,k", xreg); |
| 7419 | break; |
| 7420 | |
| 7421 | case M_DSUBU_I_2: |
| 7422 | if (imm_expr.X_op != O_constant) |
| 7423 | as_bad (_("Unsupported large constant")); |
| 7424 | imm_expr.X_add_number = -imm_expr.X_add_number; |
| 7425 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", |
| 7426 | "y,j", yreg); |
| 7427 | break; |
| 7428 | |
| 7429 | case M_BEQ: |
| 7430 | s = "cmp"; |
| 7431 | s2 = "bteqz"; |
| 7432 | goto do_branch; |
| 7433 | case M_BNE: |
| 7434 | s = "cmp"; |
| 7435 | s2 = "btnez"; |
| 7436 | goto do_branch; |
| 7437 | case M_BLT: |
| 7438 | s = "slt"; |
| 7439 | s2 = "btnez"; |
| 7440 | goto do_branch; |
| 7441 | case M_BLTU: |
| 7442 | s = "sltu"; |
| 7443 | s2 = "btnez"; |
| 7444 | goto do_branch; |
| 7445 | case M_BLE: |
| 7446 | s = "slt"; |
| 7447 | s2 = "bteqz"; |
| 7448 | goto do_reverse_branch; |
| 7449 | case M_BLEU: |
| 7450 | s = "sltu"; |
| 7451 | s2 = "bteqz"; |
| 7452 | goto do_reverse_branch; |
| 7453 | case M_BGE: |
| 7454 | s = "slt"; |
| 7455 | s2 = "bteqz"; |
| 7456 | goto do_branch; |
| 7457 | case M_BGEU: |
| 7458 | s = "sltu"; |
| 7459 | s2 = "bteqz"; |
| 7460 | goto do_branch; |
| 7461 | case M_BGT: |
| 7462 | s = "slt"; |
| 7463 | s2 = "btnez"; |
| 7464 | goto do_reverse_branch; |
| 7465 | case M_BGTU: |
| 7466 | s = "sltu"; |
| 7467 | s2 = "btnez"; |
| 7468 | |
| 7469 | do_reverse_branch: |
| 7470 | tmp = xreg; |
| 7471 | xreg = yreg; |
| 7472 | yreg = tmp; |
| 7473 | |
| 7474 | do_branch: |
| 7475 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", |
| 7476 | xreg, yreg); |
| 7477 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); |
| 7478 | break; |
| 7479 | |
| 7480 | case M_BEQ_I: |
| 7481 | s = "cmpi"; |
| 7482 | s2 = "bteqz"; |
| 7483 | s3 = "x,U"; |
| 7484 | goto do_branch_i; |
| 7485 | case M_BNE_I: |
| 7486 | s = "cmpi"; |
| 7487 | s2 = "btnez"; |
| 7488 | s3 = "x,U"; |
| 7489 | goto do_branch_i; |
| 7490 | case M_BLT_I: |
| 7491 | s = "slti"; |
| 7492 | s2 = "btnez"; |
| 7493 | s3 = "x,8"; |
| 7494 | goto do_branch_i; |
| 7495 | case M_BLTU_I: |
| 7496 | s = "sltiu"; |
| 7497 | s2 = "btnez"; |
| 7498 | s3 = "x,8"; |
| 7499 | goto do_branch_i; |
| 7500 | case M_BLE_I: |
| 7501 | s = "slti"; |
| 7502 | s2 = "btnez"; |
| 7503 | s3 = "x,8"; |
| 7504 | goto do_addone_branch_i; |
| 7505 | case M_BLEU_I: |
| 7506 | s = "sltiu"; |
| 7507 | s2 = "btnez"; |
| 7508 | s3 = "x,8"; |
| 7509 | goto do_addone_branch_i; |
| 7510 | case M_BGE_I: |
| 7511 | s = "slti"; |
| 7512 | s2 = "bteqz"; |
| 7513 | s3 = "x,8"; |
| 7514 | goto do_branch_i; |
| 7515 | case M_BGEU_I: |
| 7516 | s = "sltiu"; |
| 7517 | s2 = "bteqz"; |
| 7518 | s3 = "x,8"; |
| 7519 | goto do_branch_i; |
| 7520 | case M_BGT_I: |
| 7521 | s = "slti"; |
| 7522 | s2 = "bteqz"; |
| 7523 | s3 = "x,8"; |
| 7524 | goto do_addone_branch_i; |
| 7525 | case M_BGTU_I: |
| 7526 | s = "sltiu"; |
| 7527 | s2 = "bteqz"; |
| 7528 | s3 = "x,8"; |
| 7529 | |
| 7530 | do_addone_branch_i: |
| 7531 | if (imm_expr.X_op != O_constant) |
| 7532 | as_bad (_("Unsupported large constant")); |
| 7533 | ++imm_expr.X_add_number; |
| 7534 | |
| 7535 | do_branch_i: |
| 7536 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); |
| 7537 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); |
| 7538 | break; |
| 7539 | |
| 7540 | case M_ABS: |
| 7541 | expr1.X_add_number = 0; |
| 7542 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); |
| 7543 | if (xreg != yreg) |
| 7544 | move_register (&icnt, xreg, yreg); |
| 7545 | expr1.X_add_number = 2; |
| 7546 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); |
| 7547 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 7548 | "neg", "x,w", xreg, xreg); |
| 7549 | } |
| 7550 | } |
| 7551 | |
| 7552 | /* For consistency checking, verify that all bits are specified either |
| 7553 | by the match/mask part of the instruction definition, or by the |
| 7554 | operand list. */ |
| 7555 | static int |
| 7556 | validate_mips_insn (opc) |
| 7557 | const struct mips_opcode *opc; |
| 7558 | { |
| 7559 | const char *p = opc->args; |
| 7560 | char c; |
| 7561 | unsigned long used_bits = opc->mask; |
| 7562 | |
| 7563 | if ((used_bits & opc->match) != opc->match) |
| 7564 | { |
| 7565 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), |
| 7566 | opc->name, opc->args); |
| 7567 | return 0; |
| 7568 | } |
| 7569 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) |
| 7570 | while (*p) |
| 7571 | switch (c = *p++) |
| 7572 | { |
| 7573 | case ',': break; |
| 7574 | case '(': break; |
| 7575 | case ')': break; |
| 7576 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
| 7577 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
| 7578 | case 'A': break; |
| 7579 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
| 7580 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
| 7581 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
| 7582 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
| 7583 | case 'F': break; |
| 7584 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
| 7585 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
| 7586 | case 'I': break; |
| 7587 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
| 7588 | case 'L': break; |
| 7589 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; |
| 7590 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; |
| 7591 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
| 7592 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); |
| 7593 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; |
| 7594 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
| 7595 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; |
| 7596 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; |
| 7597 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; |
| 7598 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; |
| 7599 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
| 7600 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; |
| 7601 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; |
| 7602 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
| 7603 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; |
| 7604 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; |
| 7605 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
| 7606 | case 'f': break; |
| 7607 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; |
| 7608 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; |
| 7609 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; |
| 7610 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; |
| 7611 | case 'l': break; |
| 7612 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; |
| 7613 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; |
| 7614 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; |
| 7615 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; |
| 7616 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; |
| 7617 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
| 7618 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; |
| 7619 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; |
| 7620 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
| 7621 | case 'x': break; |
| 7622 | case 'z': break; |
| 7623 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; |
| 7624 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
| 7625 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
| 7626 | default: |
| 7627 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), |
| 7628 | c, opc->name, opc->args); |
| 7629 | return 0; |
| 7630 | } |
| 7631 | #undef USE_BITS |
| 7632 | if (used_bits != 0xffffffff) |
| 7633 | { |
| 7634 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), |
| 7635 | ~used_bits & 0xffffffff, opc->name, opc->args); |
| 7636 | return 0; |
| 7637 | } |
| 7638 | return 1; |
| 7639 | } |
| 7640 | |
| 7641 | /* This routine assembles an instruction into its binary format. As a |
| 7642 | side effect, it sets one of the global variables imm_reloc or |
| 7643 | offset_reloc to the type of relocation to do if one of the operands |
| 7644 | is an address expression. */ |
| 7645 | |
| 7646 | static void |
| 7647 | mips_ip (str, ip) |
| 7648 | char *str; |
| 7649 | struct mips_cl_insn *ip; |
| 7650 | { |
| 7651 | char *s; |
| 7652 | const char *args; |
| 7653 | char c = 0; |
| 7654 | struct mips_opcode *insn; |
| 7655 | char *argsStart; |
| 7656 | unsigned int regno; |
| 7657 | unsigned int lastregno = 0; |
| 7658 | char *s_reset; |
| 7659 | char save_c = 0; |
| 7660 | |
| 7661 | insn_error = NULL; |
| 7662 | |
| 7663 | /* If the instruction contains a '.', we first try to match an instruction |
| 7664 | including the '.'. Then we try again without the '.'. */ |
| 7665 | insn = NULL; |
| 7666 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
| 7667 | continue; |
| 7668 | |
| 7669 | /* If we stopped on whitespace, then replace the whitespace with null for |
| 7670 | the call to hash_find. Save the character we replaced just in case we |
| 7671 | have to re-parse the instruction. */ |
| 7672 | if (ISSPACE (*s)) |
| 7673 | { |
| 7674 | save_c = *s; |
| 7675 | *s++ = '\0'; |
| 7676 | } |
| 7677 | |
| 7678 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
| 7679 | |
| 7680 | /* If we didn't find the instruction in the opcode table, try again, but |
| 7681 | this time with just the instruction up to, but not including the |
| 7682 | first '.'. */ |
| 7683 | if (insn == NULL) |
| 7684 | { |
| 7685 | /* Restore the character we overwrite above (if any). */ |
| 7686 | if (save_c) |
| 7687 | *(--s) = save_c; |
| 7688 | |
| 7689 | /* Scan up to the first '.' or whitespace. */ |
| 7690 | for (s = str; |
| 7691 | *s != '\0' && *s != '.' && !ISSPACE (*s); |
| 7692 | ++s) |
| 7693 | continue; |
| 7694 | |
| 7695 | /* If we did not find a '.', then we can quit now. */ |
| 7696 | if (*s != '.') |
| 7697 | { |
| 7698 | insn_error = "unrecognized opcode"; |
| 7699 | return; |
| 7700 | } |
| 7701 | |
| 7702 | /* Lookup the instruction in the hash table. */ |
| 7703 | *s++ = '\0'; |
| 7704 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) |
| 7705 | { |
| 7706 | insn_error = "unrecognized opcode"; |
| 7707 | return; |
| 7708 | } |
| 7709 | } |
| 7710 | |
| 7711 | argsStart = s; |
| 7712 | for (;;) |
| 7713 | { |
| 7714 | boolean ok; |
| 7715 | |
| 7716 | assert (strcmp (insn->name, str) == 0); |
| 7717 | |
| 7718 | if (OPCODE_IS_MEMBER (insn, |
| 7719 | (mips_opts.isa |
| 7720 | | (mips_opts.mips16 ? INSN_MIPS16 : 0) |
| 7721 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
| 7722 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
| 7723 | mips_arch)) |
| 7724 | ok = true; |
| 7725 | else |
| 7726 | ok = false; |
| 7727 | |
| 7728 | if (insn->pinfo != INSN_MACRO) |
| 7729 | { |
| 7730 | if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
| 7731 | ok = false; |
| 7732 | } |
| 7733 | |
| 7734 | if (! ok) |
| 7735 | { |
| 7736 | if (insn + 1 < &mips_opcodes[NUMOPCODES] |
| 7737 | && strcmp (insn->name, insn[1].name) == 0) |
| 7738 | { |
| 7739 | ++insn; |
| 7740 | continue; |
| 7741 | } |
| 7742 | else |
| 7743 | { |
| 7744 | if (!insn_error) |
| 7745 | { |
| 7746 | static char buf[100]; |
| 7747 | if (mips_arch_info->is_isa) |
| 7748 | sprintf (buf, |
| 7749 | _("opcode not supported at this ISA level (%s)"), |
| 7750 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
| 7751 | else |
| 7752 | sprintf (buf, |
| 7753 | _("opcode not supported on this processor: %s (%s)"), |
| 7754 | mips_arch_info->name, |
| 7755 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
| 7756 | insn_error = buf; |
| 7757 | } |
| 7758 | if (save_c) |
| 7759 | *(--s) = save_c; |
| 7760 | return; |
| 7761 | } |
| 7762 | } |
| 7763 | |
| 7764 | ip->insn_mo = insn; |
| 7765 | ip->insn_opcode = insn->match; |
| 7766 | insn_error = NULL; |
| 7767 | for (args = insn->args;; ++args) |
| 7768 | { |
| 7769 | int is_mdmx; |
| 7770 | |
| 7771 | s += strspn (s, " \t"); |
| 7772 | is_mdmx = 0; |
| 7773 | switch (*args) |
| 7774 | { |
| 7775 | case '\0': /* end of args */ |
| 7776 | if (*s == '\0') |
| 7777 | return; |
| 7778 | break; |
| 7779 | |
| 7780 | case ',': |
| 7781 | if (*s++ == *args) |
| 7782 | continue; |
| 7783 | s--; |
| 7784 | switch (*++args) |
| 7785 | { |
| 7786 | case 'r': |
| 7787 | case 'v': |
| 7788 | ip->insn_opcode |= lastregno << OP_SH_RS; |
| 7789 | continue; |
| 7790 | |
| 7791 | case 'w': |
| 7792 | ip->insn_opcode |= lastregno << OP_SH_RT; |
| 7793 | continue; |
| 7794 | |
| 7795 | case 'W': |
| 7796 | ip->insn_opcode |= lastregno << OP_SH_FT; |
| 7797 | continue; |
| 7798 | |
| 7799 | case 'V': |
| 7800 | ip->insn_opcode |= lastregno << OP_SH_FS; |
| 7801 | continue; |
| 7802 | } |
| 7803 | break; |
| 7804 | |
| 7805 | case '(': |
| 7806 | /* Handle optional base register. |
| 7807 | Either the base register is omitted or |
| 7808 | we must have a left paren. */ |
| 7809 | /* This is dependent on the next operand specifier |
| 7810 | is a base register specification. */ |
| 7811 | assert (args[1] == 'b' || args[1] == '5' |
| 7812 | || args[1] == '-' || args[1] == '4'); |
| 7813 | if (*s == '\0') |
| 7814 | return; |
| 7815 | |
| 7816 | case ')': /* these must match exactly */ |
| 7817 | if (*s++ == *args) |
| 7818 | continue; |
| 7819 | break; |
| 7820 | |
| 7821 | case '<': /* must be at least one digit */ |
| 7822 | /* |
| 7823 | * According to the manual, if the shift amount is greater |
| 7824 | * than 31 or less than 0, then the shift amount should be |
| 7825 | * mod 32. In reality the mips assembler issues an error. |
| 7826 | * We issue a warning and mask out all but the low 5 bits. |
| 7827 | */ |
| 7828 | my_getExpression (&imm_expr, s); |
| 7829 | check_absolute_expr (ip, &imm_expr); |
| 7830 | if ((unsigned long) imm_expr.X_add_number > 31) |
| 7831 | { |
| 7832 | as_warn (_("Improper shift amount (%lu)"), |
| 7833 | (unsigned long) imm_expr.X_add_number); |
| 7834 | imm_expr.X_add_number &= OP_MASK_SHAMT; |
| 7835 | } |
| 7836 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; |
| 7837 | imm_expr.X_op = O_absent; |
| 7838 | s = expr_end; |
| 7839 | continue; |
| 7840 | |
| 7841 | case '>': /* shift amount minus 32 */ |
| 7842 | my_getExpression (&imm_expr, s); |
| 7843 | check_absolute_expr (ip, &imm_expr); |
| 7844 | if ((unsigned long) imm_expr.X_add_number < 32 |
| 7845 | || (unsigned long) imm_expr.X_add_number > 63) |
| 7846 | break; |
| 7847 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; |
| 7848 | imm_expr.X_op = O_absent; |
| 7849 | s = expr_end; |
| 7850 | continue; |
| 7851 | |
| 7852 | case 'k': /* cache code */ |
| 7853 | case 'h': /* prefx code */ |
| 7854 | my_getExpression (&imm_expr, s); |
| 7855 | check_absolute_expr (ip, &imm_expr); |
| 7856 | if ((unsigned long) imm_expr.X_add_number > 31) |
| 7857 | { |
| 7858 | as_warn (_("Invalid value for `%s' (%lu)"), |
| 7859 | ip->insn_mo->name, |
| 7860 | (unsigned long) imm_expr.X_add_number); |
| 7861 | imm_expr.X_add_number &= 0x1f; |
| 7862 | } |
| 7863 | if (*args == 'k') |
| 7864 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; |
| 7865 | else |
| 7866 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; |
| 7867 | imm_expr.X_op = O_absent; |
| 7868 | s = expr_end; |
| 7869 | continue; |
| 7870 | |
| 7871 | case 'c': /* break code */ |
| 7872 | my_getExpression (&imm_expr, s); |
| 7873 | check_absolute_expr (ip, &imm_expr); |
| 7874 | if ((unsigned long) imm_expr.X_add_number > 1023) |
| 7875 | { |
| 7876 | as_warn (_("Illegal break code (%lu)"), |
| 7877 | (unsigned long) imm_expr.X_add_number); |
| 7878 | imm_expr.X_add_number &= OP_MASK_CODE; |
| 7879 | } |
| 7880 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; |
| 7881 | imm_expr.X_op = O_absent; |
| 7882 | s = expr_end; |
| 7883 | continue; |
| 7884 | |
| 7885 | case 'q': /* lower break code */ |
| 7886 | my_getExpression (&imm_expr, s); |
| 7887 | check_absolute_expr (ip, &imm_expr); |
| 7888 | if ((unsigned long) imm_expr.X_add_number > 1023) |
| 7889 | { |
| 7890 | as_warn (_("Illegal lower break code (%lu)"), |
| 7891 | (unsigned long) imm_expr.X_add_number); |
| 7892 | imm_expr.X_add_number &= OP_MASK_CODE2; |
| 7893 | } |
| 7894 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; |
| 7895 | imm_expr.X_op = O_absent; |
| 7896 | s = expr_end; |
| 7897 | continue; |
| 7898 | |
| 7899 | case 'B': /* 20-bit syscall/break code. */ |
| 7900 | my_getExpression (&imm_expr, s); |
| 7901 | check_absolute_expr (ip, &imm_expr); |
| 7902 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
| 7903 | as_warn (_("Illegal 20-bit code (%lu)"), |
| 7904 | (unsigned long) imm_expr.X_add_number); |
| 7905 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; |
| 7906 | imm_expr.X_op = O_absent; |
| 7907 | s = expr_end; |
| 7908 | continue; |
| 7909 | |
| 7910 | case 'C': /* Coprocessor code */ |
| 7911 | my_getExpression (&imm_expr, s); |
| 7912 | check_absolute_expr (ip, &imm_expr); |
| 7913 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
| 7914 | { |
| 7915 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
| 7916 | (unsigned long) imm_expr.X_add_number); |
| 7917 | imm_expr.X_add_number &= ((1 << 25) - 1); |
| 7918 | } |
| 7919 | ip->insn_opcode |= imm_expr.X_add_number; |
| 7920 | imm_expr.X_op = O_absent; |
| 7921 | s = expr_end; |
| 7922 | continue; |
| 7923 | |
| 7924 | case 'J': /* 19-bit wait code. */ |
| 7925 | my_getExpression (&imm_expr, s); |
| 7926 | check_absolute_expr (ip, &imm_expr); |
| 7927 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
| 7928 | as_warn (_("Illegal 19-bit code (%lu)"), |
| 7929 | (unsigned long) imm_expr.X_add_number); |
| 7930 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; |
| 7931 | imm_expr.X_op = O_absent; |
| 7932 | s = expr_end; |
| 7933 | continue; |
| 7934 | |
| 7935 | case 'P': /* Performance register */ |
| 7936 | my_getExpression (&imm_expr, s); |
| 7937 | check_absolute_expr (ip, &imm_expr); |
| 7938 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
| 7939 | { |
| 7940 | as_warn (_("Invalid performance register (%lu)"), |
| 7941 | (unsigned long) imm_expr.X_add_number); |
| 7942 | imm_expr.X_add_number &= OP_MASK_PERFREG; |
| 7943 | } |
| 7944 | ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); |
| 7945 | imm_expr.X_op = O_absent; |
| 7946 | s = expr_end; |
| 7947 | continue; |
| 7948 | |
| 7949 | case 'b': /* base register */ |
| 7950 | case 'd': /* destination register */ |
| 7951 | case 's': /* source register */ |
| 7952 | case 't': /* target register */ |
| 7953 | case 'r': /* both target and source */ |
| 7954 | case 'v': /* both dest and source */ |
| 7955 | case 'w': /* both dest and target */ |
| 7956 | case 'E': /* coprocessor target register */ |
| 7957 | case 'G': /* coprocessor destination register */ |
| 7958 | case 'x': /* ignore register name */ |
| 7959 | case 'z': /* must be zero register */ |
| 7960 | case 'U': /* destination register (clo/clz). */ |
| 7961 | s_reset = s; |
| 7962 | if (s[0] == '$') |
| 7963 | { |
| 7964 | |
| 7965 | if (ISDIGIT (s[1])) |
| 7966 | { |
| 7967 | ++s; |
| 7968 | regno = 0; |
| 7969 | do |
| 7970 | { |
| 7971 | regno *= 10; |
| 7972 | regno += *s - '0'; |
| 7973 | ++s; |
| 7974 | } |
| 7975 | while (ISDIGIT (*s)); |
| 7976 | if (regno > 31) |
| 7977 | as_bad (_("Invalid register number (%d)"), regno); |
| 7978 | } |
| 7979 | else if (*args == 'E' || *args == 'G') |
| 7980 | goto notreg; |
| 7981 | else |
| 7982 | { |
| 7983 | if (s[1] == 'r' && s[2] == 'a') |
| 7984 | { |
| 7985 | s += 3; |
| 7986 | regno = RA; |
| 7987 | } |
| 7988 | else if (s[1] == 'f' && s[2] == 'p') |
| 7989 | { |
| 7990 | s += 3; |
| 7991 | regno = FP; |
| 7992 | } |
| 7993 | else if (s[1] == 's' && s[2] == 'p') |
| 7994 | { |
| 7995 | s += 3; |
| 7996 | regno = SP; |
| 7997 | } |
| 7998 | else if (s[1] == 'g' && s[2] == 'p') |
| 7999 | { |
| 8000 | s += 3; |
| 8001 | regno = GP; |
| 8002 | } |
| 8003 | else if (s[1] == 'a' && s[2] == 't') |
| 8004 | { |
| 8005 | s += 3; |
| 8006 | regno = AT; |
| 8007 | } |
| 8008 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') |
| 8009 | { |
| 8010 | s += 4; |
| 8011 | regno = KT0; |
| 8012 | } |
| 8013 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') |
| 8014 | { |
| 8015 | s += 4; |
| 8016 | regno = KT1; |
| 8017 | } |
| 8018 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
| 8019 | { |
| 8020 | s += 5; |
| 8021 | regno = ZERO; |
| 8022 | } |
| 8023 | else if (itbl_have_entries) |
| 8024 | { |
| 8025 | char *p, *n; |
| 8026 | unsigned long r; |
| 8027 | |
| 8028 | p = s + 1; /* advance past '$' */ |
| 8029 | n = itbl_get_field (&p); /* n is name */ |
| 8030 | |
| 8031 | /* See if this is a register defined in an |
| 8032 | itbl entry. */ |
| 8033 | if (itbl_get_reg_val (n, &r)) |
| 8034 | { |
| 8035 | /* Get_field advances to the start of |
| 8036 | the next field, so we need to back |
| 8037 | rack to the end of the last field. */ |
| 8038 | if (p) |
| 8039 | s = p - 1; |
| 8040 | else |
| 8041 | s = strchr (s, '\0'); |
| 8042 | regno = r; |
| 8043 | } |
| 8044 | else |
| 8045 | goto notreg; |
| 8046 | } |
| 8047 | else |
| 8048 | goto notreg; |
| 8049 | } |
| 8050 | if (regno == AT |
| 8051 | && ! mips_opts.noat |
| 8052 | && *args != 'E' |
| 8053 | && *args != 'G') |
| 8054 | as_warn (_("Used $at without \".set noat\"")); |
| 8055 | c = *args; |
| 8056 | if (*s == ' ') |
| 8057 | ++s; |
| 8058 | if (args[1] != *s) |
| 8059 | { |
| 8060 | if (c == 'r' || c == 'v' || c == 'w') |
| 8061 | { |
| 8062 | regno = lastregno; |
| 8063 | s = s_reset; |
| 8064 | ++args; |
| 8065 | } |
| 8066 | } |
| 8067 | /* 'z' only matches $0. */ |
| 8068 | if (c == 'z' && regno != 0) |
| 8069 | break; |
| 8070 | |
| 8071 | /* Now that we have assembled one operand, we use the args string |
| 8072 | * to figure out where it goes in the instruction. */ |
| 8073 | switch (c) |
| 8074 | { |
| 8075 | case 'r': |
| 8076 | case 's': |
| 8077 | case 'v': |
| 8078 | case 'b': |
| 8079 | ip->insn_opcode |= regno << OP_SH_RS; |
| 8080 | break; |
| 8081 | case 'd': |
| 8082 | case 'G': |
| 8083 | ip->insn_opcode |= regno << OP_SH_RD; |
| 8084 | break; |
| 8085 | case 'U': |
| 8086 | ip->insn_opcode |= regno << OP_SH_RD; |
| 8087 | ip->insn_opcode |= regno << OP_SH_RT; |
| 8088 | break; |
| 8089 | case 'w': |
| 8090 | case 't': |
| 8091 | case 'E': |
| 8092 | ip->insn_opcode |= regno << OP_SH_RT; |
| 8093 | break; |
| 8094 | case 'x': |
| 8095 | /* This case exists because on the r3000 trunc |
| 8096 | expands into a macro which requires a gp |
| 8097 | register. On the r6000 or r4000 it is |
| 8098 | assembled into a single instruction which |
| 8099 | ignores the register. Thus the insn version |
| 8100 | is MIPS_ISA2 and uses 'x', and the macro |
| 8101 | version is MIPS_ISA1 and uses 't'. */ |
| 8102 | break; |
| 8103 | case 'z': |
| 8104 | /* This case is for the div instruction, which |
| 8105 | acts differently if the destination argument |
| 8106 | is $0. This only matches $0, and is checked |
| 8107 | outside the switch. */ |
| 8108 | break; |
| 8109 | case 'D': |
| 8110 | /* Itbl operand; not yet implemented. FIXME ?? */ |
| 8111 | break; |
| 8112 | /* What about all other operands like 'i', which |
| 8113 | can be specified in the opcode table? */ |
| 8114 | } |
| 8115 | lastregno = regno; |
| 8116 | continue; |
| 8117 | } |
| 8118 | notreg: |
| 8119 | switch (*args++) |
| 8120 | { |
| 8121 | case 'r': |
| 8122 | case 'v': |
| 8123 | ip->insn_opcode |= lastregno << OP_SH_RS; |
| 8124 | continue; |
| 8125 | case 'w': |
| 8126 | ip->insn_opcode |= lastregno << OP_SH_RT; |
| 8127 | continue; |
| 8128 | } |
| 8129 | break; |
| 8130 | |
| 8131 | case 'O': /* MDMX alignment immediate constant. */ |
| 8132 | my_getExpression (&imm_expr, s); |
| 8133 | check_absolute_expr (ip, &imm_expr); |
| 8134 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) |
| 8135 | { |
| 8136 | as_warn ("Improper align amount (%ld), using low bits", |
| 8137 | (long) imm_expr.X_add_number); |
| 8138 | imm_expr.X_add_number &= OP_MASK_ALN; |
| 8139 | } |
| 8140 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN; |
| 8141 | imm_expr.X_op = O_absent; |
| 8142 | s = expr_end; |
| 8143 | continue; |
| 8144 | |
| 8145 | case 'Q': /* MDMX vector, element sel, or const. */ |
| 8146 | if (s[0] != '$') |
| 8147 | { |
| 8148 | /* MDMX Immediate. */ |
| 8149 | my_getExpression (&imm_expr, s); |
| 8150 | check_absolute_expr (ip, &imm_expr); |
| 8151 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) |
| 8152 | { |
| 8153 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
| 8154 | (long) imm_expr.X_add_number); |
| 8155 | imm_expr.X_add_number &= OP_MASK_FT; |
| 8156 | } |
| 8157 | imm_expr.X_add_number &= OP_MASK_FT; |
| 8158 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
| 8159 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; |
| 8160 | else |
| 8161 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; |
| 8162 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT; |
| 8163 | imm_expr.X_op = O_absent; |
| 8164 | s = expr_end; |
| 8165 | continue; |
| 8166 | } |
| 8167 | /* Not MDMX Immediate. Fall through. */ |
| 8168 | case 'X': /* MDMX destination register. */ |
| 8169 | case 'Y': /* MDMX source register. */ |
| 8170 | case 'Z': /* MDMX target register. */ |
| 8171 | is_mdmx = 1; |
| 8172 | case 'D': /* floating point destination register */ |
| 8173 | case 'S': /* floating point source register */ |
| 8174 | case 'T': /* floating point target register */ |
| 8175 | case 'R': /* floating point source register */ |
| 8176 | case 'V': |
| 8177 | case 'W': |
| 8178 | s_reset = s; |
| 8179 | /* Accept $fN for FP and MDMX register numbers, and in |
| 8180 | addition accept $vN for MDMX register numbers. */ |
| 8181 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) |
| 8182 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' |
| 8183 | && ISDIGIT (s[2]))) |
| 8184 | { |
| 8185 | s += 2; |
| 8186 | regno = 0; |
| 8187 | do |
| 8188 | { |
| 8189 | regno *= 10; |
| 8190 | regno += *s - '0'; |
| 8191 | ++s; |
| 8192 | } |
| 8193 | while (ISDIGIT (*s)); |
| 8194 | |
| 8195 | if (regno > 31) |
| 8196 | as_bad (_("Invalid float register number (%d)"), regno); |
| 8197 | |
| 8198 | if ((regno & 1) != 0 |
| 8199 | && HAVE_32BIT_FPRS |
| 8200 | && ! (strcmp (str, "mtc1") == 0 |
| 8201 | || strcmp (str, "mfc1") == 0 |
| 8202 | || strcmp (str, "lwc1") == 0 |
| 8203 | || strcmp (str, "swc1") == 0 |
| 8204 | || strcmp (str, "l.s") == 0 |
| 8205 | || strcmp (str, "s.s") == 0)) |
| 8206 | as_warn (_("Float register should be even, was %d"), |
| 8207 | regno); |
| 8208 | |
| 8209 | c = *args; |
| 8210 | if (*s == ' ') |
| 8211 | ++s; |
| 8212 | if (args[1] != *s) |
| 8213 | { |
| 8214 | if (c == 'V' || c == 'W') |
| 8215 | { |
| 8216 | regno = lastregno; |
| 8217 | s = s_reset; |
| 8218 | ++args; |
| 8219 | } |
| 8220 | } |
| 8221 | switch (c) |
| 8222 | { |
| 8223 | case 'D': |
| 8224 | case 'X': |
| 8225 | ip->insn_opcode |= regno << OP_SH_FD; |
| 8226 | break; |
| 8227 | case 'V': |
| 8228 | case 'S': |
| 8229 | case 'Y': |
| 8230 | ip->insn_opcode |= regno << OP_SH_FS; |
| 8231 | break; |
| 8232 | case 'Q': |
| 8233 | /* This is like 'Z', but also needs to fix the MDMX |
| 8234 | vector/scalar select bits. Note that the |
| 8235 | scalar immediate case is handled above. */ |
| 8236 | if (*s == '[') |
| 8237 | { |
| 8238 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); |
| 8239 | int max_el = (is_qh ? 3 : 7); |
| 8240 | s++; |
| 8241 | my_getExpression(&imm_expr, s); |
| 8242 | check_absolute_expr (ip, &imm_expr); |
| 8243 | s = expr_end; |
| 8244 | if (imm_expr.X_add_number > max_el) |
| 8245 | as_bad(_("Bad element selector %ld"), |
| 8246 | (long) imm_expr.X_add_number); |
| 8247 | imm_expr.X_add_number &= max_el; |
| 8248 | ip->insn_opcode |= (imm_expr.X_add_number |
| 8249 | << (OP_SH_VSEL + |
| 8250 | (is_qh ? 2 : 1))); |
| 8251 | if (*s != ']') |
| 8252 | as_warn(_("Expecting ']' found '%s'"), s); |
| 8253 | else |
| 8254 | s++; |
| 8255 | } |
| 8256 | else |
| 8257 | { |
| 8258 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
| 8259 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH |
| 8260 | << OP_SH_VSEL); |
| 8261 | else |
| 8262 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << |
| 8263 | OP_SH_VSEL); |
| 8264 | } |
| 8265 | /* Fall through */ |
| 8266 | case 'W': |
| 8267 | case 'T': |
| 8268 | case 'Z': |
| 8269 | ip->insn_opcode |= regno << OP_SH_FT; |
| 8270 | break; |
| 8271 | case 'R': |
| 8272 | ip->insn_opcode |= regno << OP_SH_FR; |
| 8273 | break; |
| 8274 | } |
| 8275 | lastregno = regno; |
| 8276 | continue; |
| 8277 | } |
| 8278 | |
| 8279 | switch (*args++) |
| 8280 | { |
| 8281 | case 'V': |
| 8282 | ip->insn_opcode |= lastregno << OP_SH_FS; |
| 8283 | continue; |
| 8284 | case 'W': |
| 8285 | ip->insn_opcode |= lastregno << OP_SH_FT; |
| 8286 | continue; |
| 8287 | } |
| 8288 | break; |
| 8289 | |
| 8290 | case 'I': |
| 8291 | my_getExpression (&imm_expr, s); |
| 8292 | if (imm_expr.X_op != O_big |
| 8293 | && imm_expr.X_op != O_constant) |
| 8294 | insn_error = _("absolute expression required"); |
| 8295 | s = expr_end; |
| 8296 | continue; |
| 8297 | |
| 8298 | case 'A': |
| 8299 | my_getExpression (&offset_expr, s); |
| 8300 | *imm_reloc = BFD_RELOC_32; |
| 8301 | s = expr_end; |
| 8302 | continue; |
| 8303 | |
| 8304 | case 'F': |
| 8305 | case 'L': |
| 8306 | case 'f': |
| 8307 | case 'l': |
| 8308 | { |
| 8309 | int f64; |
| 8310 | int using_gprs; |
| 8311 | char *save_in; |
| 8312 | char *err; |
| 8313 | unsigned char temp[8]; |
| 8314 | int len; |
| 8315 | unsigned int length; |
| 8316 | segT seg; |
| 8317 | subsegT subseg; |
| 8318 | char *p; |
| 8319 | |
| 8320 | /* These only appear as the last operand in an |
| 8321 | instruction, and every instruction that accepts |
| 8322 | them in any variant accepts them in all variants. |
| 8323 | This means we don't have to worry about backing out |
| 8324 | any changes if the instruction does not match. |
| 8325 | |
| 8326 | The difference between them is the size of the |
| 8327 | floating point constant and where it goes. For 'F' |
| 8328 | and 'L' the constant is 64 bits; for 'f' and 'l' it |
| 8329 | is 32 bits. Where the constant is placed is based |
| 8330 | on how the MIPS assembler does things: |
| 8331 | F -- .rdata |
| 8332 | L -- .lit8 |
| 8333 | f -- immediate value |
| 8334 | l -- .lit4 |
| 8335 | |
| 8336 | The .lit4 and .lit8 sections are only used if |
| 8337 | permitted by the -G argument. |
| 8338 | |
| 8339 | When generating embedded PIC code, we use the |
| 8340 | .lit8 section but not the .lit4 section (we can do |
| 8341 | .lit4 inline easily; we need to put .lit8 |
| 8342 | somewhere in the data segment, and using .lit8 |
| 8343 | permits the linker to eventually combine identical |
| 8344 | .lit8 entries). |
| 8345 | |
| 8346 | The code below needs to know whether the target register |
| 8347 | is 32 or 64 bits wide. It relies on the fact 'f' and |
| 8348 | 'F' are used with GPR-based instructions and 'l' and |
| 8349 | 'L' are used with FPR-based instructions. */ |
| 8350 | |
| 8351 | f64 = *args == 'F' || *args == 'L'; |
| 8352 | using_gprs = *args == 'F' || *args == 'f'; |
| 8353 | |
| 8354 | save_in = input_line_pointer; |
| 8355 | input_line_pointer = s; |
| 8356 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
| 8357 | length = len; |
| 8358 | s = input_line_pointer; |
| 8359 | input_line_pointer = save_in; |
| 8360 | if (err != NULL && *err != '\0') |
| 8361 | { |
| 8362 | as_bad (_("Bad floating point constant: %s"), err); |
| 8363 | memset (temp, '\0', sizeof temp); |
| 8364 | length = f64 ? 8 : 4; |
| 8365 | } |
| 8366 | |
| 8367 | assert (length == (unsigned) (f64 ? 8 : 4)); |
| 8368 | |
| 8369 | if (*args == 'f' |
| 8370 | || (*args == 'l' |
| 8371 | && (! USE_GLOBAL_POINTER_OPT |
| 8372 | || mips_pic == EMBEDDED_PIC |
| 8373 | || g_switch_value < 4 |
| 8374 | || (temp[0] == 0 && temp[1] == 0) |
| 8375 | || (temp[2] == 0 && temp[3] == 0)))) |
| 8376 | { |
| 8377 | imm_expr.X_op = O_constant; |
| 8378 | if (! target_big_endian) |
| 8379 | imm_expr.X_add_number = bfd_getl32 (temp); |
| 8380 | else |
| 8381 | imm_expr.X_add_number = bfd_getb32 (temp); |
| 8382 | } |
| 8383 | else if (length > 4 |
| 8384 | && ! mips_disable_float_construction |
| 8385 | /* Constants can only be constructed in GPRs and |
| 8386 | copied to FPRs if the GPRs are at least as wide |
| 8387 | as the FPRs. Force the constant into memory if |
| 8388 | we are using 64-bit FPRs but the GPRs are only |
| 8389 | 32 bits wide. */ |
| 8390 | && (using_gprs |
| 8391 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
| 8392 | && ((temp[0] == 0 && temp[1] == 0) |
| 8393 | || (temp[2] == 0 && temp[3] == 0)) |
| 8394 | && ((temp[4] == 0 && temp[5] == 0) |
| 8395 | || (temp[6] == 0 && temp[7] == 0))) |
| 8396 | { |
| 8397 | /* The value is simple enough to load with a couple of |
| 8398 | instructions. If using 32-bit registers, set |
| 8399 | imm_expr to the high order 32 bits and offset_expr to |
| 8400 | the low order 32 bits. Otherwise, set imm_expr to |
| 8401 | the entire 64 bit constant. */ |
| 8402 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
| 8403 | { |
| 8404 | imm_expr.X_op = O_constant; |
| 8405 | offset_expr.X_op = O_constant; |
| 8406 | if (! target_big_endian) |
| 8407 | { |
| 8408 | imm_expr.X_add_number = bfd_getl32 (temp + 4); |
| 8409 | offset_expr.X_add_number = bfd_getl32 (temp); |
| 8410 | } |
| 8411 | else |
| 8412 | { |
| 8413 | imm_expr.X_add_number = bfd_getb32 (temp); |
| 8414 | offset_expr.X_add_number = bfd_getb32 (temp + 4); |
| 8415 | } |
| 8416 | if (offset_expr.X_add_number == 0) |
| 8417 | offset_expr.X_op = O_absent; |
| 8418 | } |
| 8419 | else if (sizeof (imm_expr.X_add_number) > 4) |
| 8420 | { |
| 8421 | imm_expr.X_op = O_constant; |
| 8422 | if (! target_big_endian) |
| 8423 | imm_expr.X_add_number = bfd_getl64 (temp); |
| 8424 | else |
| 8425 | imm_expr.X_add_number = bfd_getb64 (temp); |
| 8426 | } |
| 8427 | else |
| 8428 | { |
| 8429 | imm_expr.X_op = O_big; |
| 8430 | imm_expr.X_add_number = 4; |
| 8431 | if (! target_big_endian) |
| 8432 | { |
| 8433 | generic_bignum[0] = bfd_getl16 (temp); |
| 8434 | generic_bignum[1] = bfd_getl16 (temp + 2); |
| 8435 | generic_bignum[2] = bfd_getl16 (temp + 4); |
| 8436 | generic_bignum[3] = bfd_getl16 (temp + 6); |
| 8437 | } |
| 8438 | else |
| 8439 | { |
| 8440 | generic_bignum[0] = bfd_getb16 (temp + 6); |
| 8441 | generic_bignum[1] = bfd_getb16 (temp + 4); |
| 8442 | generic_bignum[2] = bfd_getb16 (temp + 2); |
| 8443 | generic_bignum[3] = bfd_getb16 (temp); |
| 8444 | } |
| 8445 | } |
| 8446 | } |
| 8447 | else |
| 8448 | { |
| 8449 | const char *newname; |
| 8450 | segT new_seg; |
| 8451 | |
| 8452 | /* Switch to the right section. */ |
| 8453 | seg = now_seg; |
| 8454 | subseg = now_subseg; |
| 8455 | switch (*args) |
| 8456 | { |
| 8457 | default: /* unused default case avoids warnings. */ |
| 8458 | case 'L': |
| 8459 | newname = RDATA_SECTION_NAME; |
| 8460 | if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
| 8461 | || mips_pic == EMBEDDED_PIC) |
| 8462 | newname = ".lit8"; |
| 8463 | break; |
| 8464 | case 'F': |
| 8465 | if (mips_pic == EMBEDDED_PIC) |
| 8466 | newname = ".lit8"; |
| 8467 | else |
| 8468 | newname = RDATA_SECTION_NAME; |
| 8469 | break; |
| 8470 | case 'l': |
| 8471 | assert (!USE_GLOBAL_POINTER_OPT |
| 8472 | || g_switch_value >= 4); |
| 8473 | newname = ".lit4"; |
| 8474 | break; |
| 8475 | } |
| 8476 | new_seg = subseg_new (newname, (subsegT) 0); |
| 8477 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
| 8478 | bfd_set_section_flags (stdoutput, new_seg, |
| 8479 | (SEC_ALLOC |
| 8480 | | SEC_LOAD |
| 8481 | | SEC_READONLY |
| 8482 | | SEC_DATA)); |
| 8483 | frag_align (*args == 'l' ? 2 : 3, 0, 0); |
| 8484 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
| 8485 | && strcmp (TARGET_OS, "elf") != 0) |
| 8486 | record_alignment (new_seg, 4); |
| 8487 | else |
| 8488 | record_alignment (new_seg, *args == 'l' ? 2 : 3); |
| 8489 | if (seg == now_seg) |
| 8490 | as_bad (_("Can't use floating point insn in this section")); |
| 8491 | |
| 8492 | /* Set the argument to the current address in the |
| 8493 | section. */ |
| 8494 | offset_expr.X_op = O_symbol; |
| 8495 | offset_expr.X_add_symbol = |
| 8496 | symbol_new ("L0\001", now_seg, |
| 8497 | (valueT) frag_now_fix (), frag_now); |
| 8498 | offset_expr.X_add_number = 0; |
| 8499 | |
| 8500 | /* Put the floating point number into the section. */ |
| 8501 | p = frag_more ((int) length); |
| 8502 | memcpy (p, temp, length); |
| 8503 | |
| 8504 | /* Switch back to the original section. */ |
| 8505 | subseg_set (seg, subseg); |
| 8506 | } |
| 8507 | } |
| 8508 | continue; |
| 8509 | |
| 8510 | case 'i': /* 16 bit unsigned immediate */ |
| 8511 | case 'j': /* 16 bit signed immediate */ |
| 8512 | *imm_reloc = BFD_RELOC_LO16; |
| 8513 | c = my_getSmallExpression (&imm_expr, s); |
| 8514 | if (c != S_EX_NONE) |
| 8515 | { |
| 8516 | if (c != S_EX_LO) |
| 8517 | { |
| 8518 | if (imm_expr.X_op == O_constant) |
| 8519 | imm_expr.X_add_number = |
| 8520 | (imm_expr.X_add_number >> 16) & 0xffff; |
| 8521 | #ifdef OBJ_ELF |
| 8522 | else if (c == S_EX_HIGHEST) |
| 8523 | *imm_reloc = BFD_RELOC_MIPS_HIGHEST; |
| 8524 | else if (c == S_EX_HIGHER) |
| 8525 | *imm_reloc = BFD_RELOC_MIPS_HIGHER; |
| 8526 | else if (c == S_EX_GP_REL) |
| 8527 | { |
| 8528 | /* This occurs in NewABI only. */ |
| 8529 | c = my_getSmallExpression (&imm_expr, s); |
| 8530 | if (c != S_EX_NEG) |
| 8531 | as_bad (_("bad composition of relocations")); |
| 8532 | else |
| 8533 | { |
| 8534 | c = my_getSmallExpression (&imm_expr, s); |
| 8535 | if (c != S_EX_LO) |
| 8536 | as_bad (_("bad composition of relocations")); |
| 8537 | else |
| 8538 | { |
| 8539 | imm_reloc[0] = BFD_RELOC_GPREL16; |
| 8540 | imm_reloc[1] = BFD_RELOC_MIPS_SUB; |
| 8541 | imm_reloc[2] = BFD_RELOC_LO16; |
| 8542 | } |
| 8543 | } |
| 8544 | } |
| 8545 | #endif |
| 8546 | else if (c == S_EX_HI) |
| 8547 | { |
| 8548 | *imm_reloc = BFD_RELOC_HI16_S; |
| 8549 | imm_unmatched_hi = true; |
| 8550 | } |
| 8551 | else |
| 8552 | *imm_reloc = BFD_RELOC_HI16; |
| 8553 | } |
| 8554 | else if (imm_expr.X_op == O_constant) |
| 8555 | imm_expr.X_add_number &= 0xffff; |
| 8556 | } |
| 8557 | if (*args == 'i') |
| 8558 | { |
| 8559 | if ((c == S_EX_NONE && imm_expr.X_op != O_constant) |
| 8560 | || ((imm_expr.X_add_number < 0 |
| 8561 | || imm_expr.X_add_number >= 0x10000) |
| 8562 | && imm_expr.X_op == O_constant)) |
| 8563 | { |
| 8564 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && |
| 8565 | !strcmp (insn->name, insn[1].name)) |
| 8566 | break; |
| 8567 | if (imm_expr.X_op == O_constant |
| 8568 | || imm_expr.X_op == O_big) |
| 8569 | as_bad (_("16 bit expression not in range 0..65535")); |
| 8570 | } |
| 8571 | } |
| 8572 | else |
| 8573 | { |
| 8574 | int more; |
| 8575 | offsetT max; |
| 8576 | |
| 8577 | /* The upper bound should be 0x8000, but |
| 8578 | unfortunately the MIPS assembler accepts numbers |
| 8579 | from 0x8000 to 0xffff and sign extends them, and |
| 8580 | we want to be compatible. We only permit this |
| 8581 | extended range for an instruction which does not |
| 8582 | provide any further alternates, since those |
| 8583 | alternates may handle other cases. People should |
| 8584 | use the numbers they mean, rather than relying on |
| 8585 | a mysterious sign extension. */ |
| 8586 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && |
| 8587 | strcmp (insn->name, insn[1].name) == 0); |
| 8588 | if (more) |
| 8589 | max = 0x8000; |
| 8590 | else |
| 8591 | max = 0x10000; |
| 8592 | if ((c == S_EX_NONE && imm_expr.X_op != O_constant) |
| 8593 | || ((imm_expr.X_add_number < -0x8000 |
| 8594 | || imm_expr.X_add_number >= max) |
| 8595 | && imm_expr.X_op == O_constant) |
| 8596 | || (more |
| 8597 | && imm_expr.X_add_number < 0 |
| 8598 | && HAVE_64BIT_GPRS |
| 8599 | && imm_expr.X_unsigned |
| 8600 | && sizeof (imm_expr.X_add_number) <= 4)) |
| 8601 | { |
| 8602 | if (more) |
| 8603 | break; |
| 8604 | if (imm_expr.X_op == O_constant |
| 8605 | || imm_expr.X_op == O_big) |
| 8606 | as_bad (_("16 bit expression not in range -32768..32767")); |
| 8607 | } |
| 8608 | } |
| 8609 | s = expr_end; |
| 8610 | continue; |
| 8611 | |
| 8612 | case 'o': /* 16 bit offset */ |
| 8613 | c = my_getSmallExpression (&offset_expr, s); |
| 8614 | |
| 8615 | /* If this value won't fit into a 16 bit offset, then go |
| 8616 | find a macro that will generate the 32 bit offset |
| 8617 | code pattern. */ |
| 8618 | if (c == S_EX_NONE |
| 8619 | && (offset_expr.X_op != O_constant |
| 8620 | || offset_expr.X_add_number >= 0x8000 |
| 8621 | || offset_expr.X_add_number < -0x8000)) |
| 8622 | break; |
| 8623 | |
| 8624 | if (c == S_EX_HI) |
| 8625 | { |
| 8626 | if (offset_expr.X_op != O_constant) |
| 8627 | break; |
| 8628 | offset_expr.X_add_number = |
| 8629 | (offset_expr.X_add_number >> 16) & 0xffff; |
| 8630 | } |
| 8631 | *offset_reloc = BFD_RELOC_LO16; |
| 8632 | s = expr_end; |
| 8633 | continue; |
| 8634 | |
| 8635 | case 'p': /* pc relative offset */ |
| 8636 | if (mips_pic == EMBEDDED_PIC) |
| 8637 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
| 8638 | else |
| 8639 | *offset_reloc = BFD_RELOC_16_PCREL; |
| 8640 | my_getExpression (&offset_expr, s); |
| 8641 | s = expr_end; |
| 8642 | continue; |
| 8643 | |
| 8644 | case 'u': /* upper 16 bits */ |
| 8645 | c = my_getSmallExpression (&imm_expr, s); |
| 8646 | *imm_reloc = BFD_RELOC_LO16; |
| 8647 | if (c != S_EX_NONE) |
| 8648 | { |
| 8649 | if (c != S_EX_LO) |
| 8650 | { |
| 8651 | if (imm_expr.X_op == O_constant) |
| 8652 | imm_expr.X_add_number = |
| 8653 | (imm_expr.X_add_number >> 16) & 0xffff; |
| 8654 | else if (c == S_EX_HI) |
| 8655 | { |
| 8656 | *imm_reloc = BFD_RELOC_HI16_S; |
| 8657 | imm_unmatched_hi = true; |
| 8658 | } |
| 8659 | #ifdef OBJ_ELF |
| 8660 | else if (c == S_EX_HIGHEST) |
| 8661 | *imm_reloc = BFD_RELOC_MIPS_HIGHEST; |
| 8662 | else if (c == S_EX_GP_REL) |
| 8663 | { |
| 8664 | /* This occurs in NewABI only. */ |
| 8665 | c = my_getSmallExpression (&imm_expr, s); |
| 8666 | if (c != S_EX_NEG) |
| 8667 | as_bad (_("bad composition of relocations")); |
| 8668 | else |
| 8669 | { |
| 8670 | c = my_getSmallExpression (&imm_expr, s); |
| 8671 | if (c != S_EX_HI) |
| 8672 | as_bad (_("bad composition of relocations")); |
| 8673 | else |
| 8674 | { |
| 8675 | imm_reloc[0] = BFD_RELOC_GPREL16; |
| 8676 | imm_reloc[1] = BFD_RELOC_MIPS_SUB; |
| 8677 | imm_reloc[2] = BFD_RELOC_HI16_S; |
| 8678 | } |
| 8679 | } |
| 8680 | } |
| 8681 | #endif |
| 8682 | else |
| 8683 | *imm_reloc = BFD_RELOC_HI16; |
| 8684 | } |
| 8685 | else if (imm_expr.X_op == O_constant) |
| 8686 | imm_expr.X_add_number &= 0xffff; |
| 8687 | } |
| 8688 | if (imm_expr.X_op == O_constant |
| 8689 | && (imm_expr.X_add_number < 0 |
| 8690 | || imm_expr.X_add_number >= 0x10000)) |
| 8691 | as_bad (_("lui expression not in range 0..65535")); |
| 8692 | s = expr_end; |
| 8693 | continue; |
| 8694 | |
| 8695 | case 'a': /* 26 bit address */ |
| 8696 | my_getExpression (&offset_expr, s); |
| 8697 | s = expr_end; |
| 8698 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
| 8699 | continue; |
| 8700 | |
| 8701 | case 'N': /* 3 bit branch condition code */ |
| 8702 | case 'M': /* 3 bit compare condition code */ |
| 8703 | if (strncmp (s, "$fcc", 4) != 0) |
| 8704 | break; |
| 8705 | s += 4; |
| 8706 | regno = 0; |
| 8707 | do |
| 8708 | { |
| 8709 | regno *= 10; |
| 8710 | regno += *s - '0'; |
| 8711 | ++s; |
| 8712 | } |
| 8713 | while (ISDIGIT (*s)); |
| 8714 | if (regno > 7) |
| 8715 | as_bad (_("invalid condition code register $fcc%d"), regno); |
| 8716 | if (*args == 'N') |
| 8717 | ip->insn_opcode |= regno << OP_SH_BCC; |
| 8718 | else |
| 8719 | ip->insn_opcode |= regno << OP_SH_CCC; |
| 8720 | continue; |
| 8721 | |
| 8722 | case 'H': |
| 8723 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) |
| 8724 | s += 2; |
| 8725 | if (ISDIGIT (*s)) |
| 8726 | { |
| 8727 | c = 0; |
| 8728 | do |
| 8729 | { |
| 8730 | c *= 10; |
| 8731 | c += *s - '0'; |
| 8732 | ++s; |
| 8733 | } |
| 8734 | while (ISDIGIT (*s)); |
| 8735 | } |
| 8736 | else |
| 8737 | c = 8; /* Invalid sel value. */ |
| 8738 | |
| 8739 | if (c > 7) |
| 8740 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); |
| 8741 | ip->insn_opcode |= c; |
| 8742 | continue; |
| 8743 | |
| 8744 | default: |
| 8745 | as_bad (_("bad char = '%c'\n"), *args); |
| 8746 | internalError (); |
| 8747 | } |
| 8748 | break; |
| 8749 | } |
| 8750 | /* Args don't match. */ |
| 8751 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && |
| 8752 | !strcmp (insn->name, insn[1].name)) |
| 8753 | { |
| 8754 | ++insn; |
| 8755 | s = argsStart; |
| 8756 | insn_error = _("illegal operands"); |
| 8757 | continue; |
| 8758 | } |
| 8759 | if (save_c) |
| 8760 | *(--s) = save_c; |
| 8761 | insn_error = _("illegal operands"); |
| 8762 | return; |
| 8763 | } |
| 8764 | } |
| 8765 | |
| 8766 | /* This routine assembles an instruction into its binary format when |
| 8767 | assembling for the mips16. As a side effect, it sets one of the |
| 8768 | global variables imm_reloc or offset_reloc to the type of |
| 8769 | relocation to do if one of the operands is an address expression. |
| 8770 | It also sets mips16_small and mips16_ext if the user explicitly |
| 8771 | requested a small or extended instruction. */ |
| 8772 | |
| 8773 | static void |
| 8774 | mips16_ip (str, ip) |
| 8775 | char *str; |
| 8776 | struct mips_cl_insn *ip; |
| 8777 | { |
| 8778 | char *s; |
| 8779 | const char *args; |
| 8780 | struct mips_opcode *insn; |
| 8781 | char *argsstart; |
| 8782 | unsigned int regno; |
| 8783 | unsigned int lastregno = 0; |
| 8784 | char *s_reset; |
| 8785 | |
| 8786 | insn_error = NULL; |
| 8787 | |
| 8788 | mips16_small = false; |
| 8789 | mips16_ext = false; |
| 8790 | |
| 8791 | for (s = str; ISLOWER (*s); ++s) |
| 8792 | ; |
| 8793 | switch (*s) |
| 8794 | { |
| 8795 | case '\0': |
| 8796 | break; |
| 8797 | |
| 8798 | case ' ': |
| 8799 | *s++ = '\0'; |
| 8800 | break; |
| 8801 | |
| 8802 | case '.': |
| 8803 | if (s[1] == 't' && s[2] == ' ') |
| 8804 | { |
| 8805 | *s = '\0'; |
| 8806 | mips16_small = true; |
| 8807 | s += 3; |
| 8808 | break; |
| 8809 | } |
| 8810 | else if (s[1] == 'e' && s[2] == ' ') |
| 8811 | { |
| 8812 | *s = '\0'; |
| 8813 | mips16_ext = true; |
| 8814 | s += 3; |
| 8815 | break; |
| 8816 | } |
| 8817 | /* Fall through. */ |
| 8818 | default: |
| 8819 | insn_error = _("unknown opcode"); |
| 8820 | return; |
| 8821 | } |
| 8822 | |
| 8823 | if (mips_opts.noautoextend && ! mips16_ext) |
| 8824 | mips16_small = true; |
| 8825 | |
| 8826 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) |
| 8827 | { |
| 8828 | insn_error = _("unrecognized opcode"); |
| 8829 | return; |
| 8830 | } |
| 8831 | |
| 8832 | argsstart = s; |
| 8833 | for (;;) |
| 8834 | { |
| 8835 | assert (strcmp (insn->name, str) == 0); |
| 8836 | |
| 8837 | ip->insn_mo = insn; |
| 8838 | ip->insn_opcode = insn->match; |
| 8839 | ip->use_extend = false; |
| 8840 | imm_expr.X_op = O_absent; |
| 8841 | imm_reloc[0] = BFD_RELOC_UNUSED; |
| 8842 | imm_reloc[1] = BFD_RELOC_UNUSED; |
| 8843 | imm_reloc[2] = BFD_RELOC_UNUSED; |
| 8844 | offset_expr.X_op = O_absent; |
| 8845 | offset_reloc[0] = BFD_RELOC_UNUSED; |
| 8846 | offset_reloc[1] = BFD_RELOC_UNUSED; |
| 8847 | offset_reloc[2] = BFD_RELOC_UNUSED; |
| 8848 | for (args = insn->args; 1; ++args) |
| 8849 | { |
| 8850 | int c; |
| 8851 | |
| 8852 | if (*s == ' ') |
| 8853 | ++s; |
| 8854 | |
| 8855 | /* In this switch statement we call break if we did not find |
| 8856 | a match, continue if we did find a match, or return if we |
| 8857 | are done. */ |
| 8858 | |
| 8859 | c = *args; |
| 8860 | switch (c) |
| 8861 | { |
| 8862 | case '\0': |
| 8863 | if (*s == '\0') |
| 8864 | { |
| 8865 | /* Stuff the immediate value in now, if we can. */ |
| 8866 | if (imm_expr.X_op == O_constant |
| 8867 | && *imm_reloc > BFD_RELOC_UNUSED |
| 8868 | && insn->pinfo != INSN_MACRO) |
| 8869 | { |
| 8870 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
| 8871 | imm_expr.X_add_number, true, mips16_small, |
| 8872 | mips16_ext, &ip->insn_opcode, |
| 8873 | &ip->use_extend, &ip->extend); |
| 8874 | imm_expr.X_op = O_absent; |
| 8875 | *imm_reloc = BFD_RELOC_UNUSED; |
| 8876 | } |
| 8877 | |
| 8878 | return; |
| 8879 | } |
| 8880 | break; |
| 8881 | |
| 8882 | case ',': |
| 8883 | if (*s++ == c) |
| 8884 | continue; |
| 8885 | s--; |
| 8886 | switch (*++args) |
| 8887 | { |
| 8888 | case 'v': |
| 8889 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; |
| 8890 | continue; |
| 8891 | case 'w': |
| 8892 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; |
| 8893 | continue; |
| 8894 | } |
| 8895 | break; |
| 8896 | |
| 8897 | case '(': |
| 8898 | case ')': |
| 8899 | if (*s++ == c) |
| 8900 | continue; |
| 8901 | break; |
| 8902 | |
| 8903 | case 'v': |
| 8904 | case 'w': |
| 8905 | if (s[0] != '$') |
| 8906 | { |
| 8907 | if (c == 'v') |
| 8908 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; |
| 8909 | else |
| 8910 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; |
| 8911 | ++args; |
| 8912 | continue; |
| 8913 | } |
| 8914 | /* Fall through. */ |
| 8915 | case 'x': |
| 8916 | case 'y': |
| 8917 | case 'z': |
| 8918 | case 'Z': |
| 8919 | case '0': |
| 8920 | case 'S': |
| 8921 | case 'R': |
| 8922 | case 'X': |
| 8923 | case 'Y': |
| 8924 | if (s[0] != '$') |
| 8925 | break; |
| 8926 | s_reset = s; |
| 8927 | if (ISDIGIT (s[1])) |
| 8928 | { |
| 8929 | ++s; |
| 8930 | regno = 0; |
| 8931 | do |
| 8932 | { |
| 8933 | regno *= 10; |
| 8934 | regno += *s - '0'; |
| 8935 | ++s; |
| 8936 | } |
| 8937 | while (ISDIGIT (*s)); |
| 8938 | if (regno > 31) |
| 8939 | { |
| 8940 | as_bad (_("invalid register number (%d)"), regno); |
| 8941 | regno = 2; |
| 8942 | } |
| 8943 | } |
| 8944 | else |
| 8945 | { |
| 8946 | if (s[1] == 'r' && s[2] == 'a') |
| 8947 | { |
| 8948 | s += 3; |
| 8949 | regno = RA; |
| 8950 | } |
| 8951 | else if (s[1] == 'f' && s[2] == 'p') |
| 8952 | { |
| 8953 | s += 3; |
| 8954 | regno = FP; |
| 8955 | } |
| 8956 | else if (s[1] == 's' && s[2] == 'p') |
| 8957 | { |
| 8958 | s += 3; |
| 8959 | regno = SP; |
| 8960 | } |
| 8961 | else if (s[1] == 'g' && s[2] == 'p') |
| 8962 | { |
| 8963 | s += 3; |
| 8964 | regno = GP; |
| 8965 | } |
| 8966 | else if (s[1] == 'a' && s[2] == 't') |
| 8967 | { |
| 8968 | s += 3; |
| 8969 | regno = AT; |
| 8970 | } |
| 8971 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') |
| 8972 | { |
| 8973 | s += 4; |
| 8974 | regno = KT0; |
| 8975 | } |
| 8976 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') |
| 8977 | { |
| 8978 | s += 4; |
| 8979 | regno = KT1; |
| 8980 | } |
| 8981 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
| 8982 | { |
| 8983 | s += 5; |
| 8984 | regno = ZERO; |
| 8985 | } |
| 8986 | else |
| 8987 | break; |
| 8988 | } |
| 8989 | |
| 8990 | if (*s == ' ') |
| 8991 | ++s; |
| 8992 | if (args[1] != *s) |
| 8993 | { |
| 8994 | if (c == 'v' || c == 'w') |
| 8995 | { |
| 8996 | regno = mips16_to_32_reg_map[lastregno]; |
| 8997 | s = s_reset; |
| 8998 | ++args; |
| 8999 | } |
| 9000 | } |
| 9001 | |
| 9002 | switch (c) |
| 9003 | { |
| 9004 | case 'x': |
| 9005 | case 'y': |
| 9006 | case 'z': |
| 9007 | case 'v': |
| 9008 | case 'w': |
| 9009 | case 'Z': |
| 9010 | regno = mips32_to_16_reg_map[regno]; |
| 9011 | break; |
| 9012 | |
| 9013 | case '0': |
| 9014 | if (regno != 0) |
| 9015 | regno = ILLEGAL_REG; |
| 9016 | break; |
| 9017 | |
| 9018 | case 'S': |
| 9019 | if (regno != SP) |
| 9020 | regno = ILLEGAL_REG; |
| 9021 | break; |
| 9022 | |
| 9023 | case 'R': |
| 9024 | if (regno != RA) |
| 9025 | regno = ILLEGAL_REG; |
| 9026 | break; |
| 9027 | |
| 9028 | case 'X': |
| 9029 | case 'Y': |
| 9030 | if (regno == AT && ! mips_opts.noat) |
| 9031 | as_warn (_("used $at without \".set noat\"")); |
| 9032 | break; |
| 9033 | |
| 9034 | default: |
| 9035 | internalError (); |
| 9036 | } |
| 9037 | |
| 9038 | if (regno == ILLEGAL_REG) |
| 9039 | break; |
| 9040 | |
| 9041 | switch (c) |
| 9042 | { |
| 9043 | case 'x': |
| 9044 | case 'v': |
| 9045 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; |
| 9046 | break; |
| 9047 | case 'y': |
| 9048 | case 'w': |
| 9049 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; |
| 9050 | break; |
| 9051 | case 'z': |
| 9052 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; |
| 9053 | break; |
| 9054 | case 'Z': |
| 9055 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; |
| 9056 | case '0': |
| 9057 | case 'S': |
| 9058 | case 'R': |
| 9059 | break; |
| 9060 | case 'X': |
| 9061 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; |
| 9062 | break; |
| 9063 | case 'Y': |
| 9064 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
| 9065 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; |
| 9066 | break; |
| 9067 | default: |
| 9068 | internalError (); |
| 9069 | } |
| 9070 | |
| 9071 | lastregno = regno; |
| 9072 | continue; |
| 9073 | |
| 9074 | case 'P': |
| 9075 | if (strncmp (s, "$pc", 3) == 0) |
| 9076 | { |
| 9077 | s += 3; |
| 9078 | continue; |
| 9079 | } |
| 9080 | break; |
| 9081 | |
| 9082 | case '<': |
| 9083 | case '>': |
| 9084 | case '[': |
| 9085 | case ']': |
| 9086 | case '4': |
| 9087 | case '5': |
| 9088 | case 'H': |
| 9089 | case 'W': |
| 9090 | case 'D': |
| 9091 | case 'j': |
| 9092 | case '8': |
| 9093 | case 'V': |
| 9094 | case 'C': |
| 9095 | case 'U': |
| 9096 | case 'k': |
| 9097 | case 'K': |
| 9098 | if (s[0] == '%' |
| 9099 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) |
| 9100 | { |
| 9101 | /* This is %gprel(SYMBOL). We need to read SYMBOL, |
| 9102 | and generate the appropriate reloc. If the text |
| 9103 | inside %gprel is not a symbol name with an |
| 9104 | optional offset, then we generate a normal reloc |
| 9105 | and will probably fail later. */ |
| 9106 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); |
| 9107 | if (imm_expr.X_op == O_symbol) |
| 9108 | { |
| 9109 | mips16_ext = true; |
| 9110 | *imm_reloc = BFD_RELOC_MIPS16_GPREL; |
| 9111 | s = expr_end; |
| 9112 | ip->use_extend = true; |
| 9113 | ip->extend = 0; |
| 9114 | continue; |
| 9115 | } |
| 9116 | } |
| 9117 | else |
| 9118 | { |
| 9119 | /* Just pick up a normal expression. */ |
| 9120 | my_getExpression (&imm_expr, s); |
| 9121 | } |
| 9122 | |
| 9123 | if (imm_expr.X_op == O_register) |
| 9124 | { |
| 9125 | /* What we thought was an expression turned out to |
| 9126 | be a register. */ |
| 9127 | |
| 9128 | if (s[0] == '(' && args[1] == '(') |
| 9129 | { |
| 9130 | /* It looks like the expression was omitted |
| 9131 | before a register indirection, which means |
| 9132 | that the expression is implicitly zero. We |
| 9133 | still set up imm_expr, so that we handle |
| 9134 | explicit extensions correctly. */ |
| 9135 | imm_expr.X_op = O_constant; |
| 9136 | imm_expr.X_add_number = 0; |
| 9137 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
| 9138 | continue; |
| 9139 | } |
| 9140 | |
| 9141 | break; |
| 9142 | } |
| 9143 | |
| 9144 | /* We need to relax this instruction. */ |
| 9145 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
| 9146 | s = expr_end; |
| 9147 | continue; |
| 9148 | |
| 9149 | case 'p': |
| 9150 | case 'q': |
| 9151 | case 'A': |
| 9152 | case 'B': |
| 9153 | case 'E': |
| 9154 | /* We use offset_reloc rather than imm_reloc for the PC |
| 9155 | relative operands. This lets macros with both |
| 9156 | immediate and address operands work correctly. */ |
| 9157 | my_getExpression (&offset_expr, s); |
| 9158 | |
| 9159 | if (offset_expr.X_op == O_register) |
| 9160 | break; |
| 9161 | |
| 9162 | /* We need to relax this instruction. */ |
| 9163 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
| 9164 | s = expr_end; |
| 9165 | continue; |
| 9166 | |
| 9167 | case '6': /* break code */ |
| 9168 | my_getExpression (&imm_expr, s); |
| 9169 | check_absolute_expr (ip, &imm_expr); |
| 9170 | if ((unsigned long) imm_expr.X_add_number > 63) |
| 9171 | { |
| 9172 | as_warn (_("Invalid value for `%s' (%lu)"), |
| 9173 | ip->insn_mo->name, |
| 9174 | (unsigned long) imm_expr.X_add_number); |
| 9175 | imm_expr.X_add_number &= 0x3f; |
| 9176 | } |
| 9177 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; |
| 9178 | imm_expr.X_op = O_absent; |
| 9179 | s = expr_end; |
| 9180 | continue; |
| 9181 | |
| 9182 | case 'a': /* 26 bit address */ |
| 9183 | my_getExpression (&offset_expr, s); |
| 9184 | s = expr_end; |
| 9185 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
| 9186 | ip->insn_opcode <<= 16; |
| 9187 | continue; |
| 9188 | |
| 9189 | case 'l': /* register list for entry macro */ |
| 9190 | case 'L': /* register list for exit macro */ |
| 9191 | { |
| 9192 | int mask; |
| 9193 | |
| 9194 | if (c == 'l') |
| 9195 | mask = 0; |
| 9196 | else |
| 9197 | mask = 7 << 3; |
| 9198 | while (*s != '\0') |
| 9199 | { |
| 9200 | int freg, reg1, reg2; |
| 9201 | |
| 9202 | while (*s == ' ' || *s == ',') |
| 9203 | ++s; |
| 9204 | if (*s != '$') |
| 9205 | { |
| 9206 | as_bad (_("can't parse register list")); |
| 9207 | break; |
| 9208 | } |
| 9209 | ++s; |
| 9210 | if (*s != 'f') |
| 9211 | freg = 0; |
| 9212 | else |
| 9213 | { |
| 9214 | freg = 1; |
| 9215 | ++s; |
| 9216 | } |
| 9217 | reg1 = 0; |
| 9218 | while (ISDIGIT (*s)) |
| 9219 | { |
| 9220 | reg1 *= 10; |
| 9221 | reg1 += *s - '0'; |
| 9222 | ++s; |
| 9223 | } |
| 9224 | if (*s == ' ') |
| 9225 | ++s; |
| 9226 | if (*s != '-') |
| 9227 | reg2 = reg1; |
| 9228 | else |
| 9229 | { |
| 9230 | ++s; |
| 9231 | if (*s != '$') |
| 9232 | break; |
| 9233 | ++s; |
| 9234 | if (freg) |
| 9235 | { |
| 9236 | if (*s == 'f') |
| 9237 | ++s; |
| 9238 | else |
| 9239 | { |
| 9240 | as_bad (_("invalid register list")); |
| 9241 | break; |
| 9242 | } |
| 9243 | } |
| 9244 | reg2 = 0; |
| 9245 | while (ISDIGIT (*s)) |
| 9246 | { |
| 9247 | reg2 *= 10; |
| 9248 | reg2 += *s - '0'; |
| 9249 | ++s; |
| 9250 | } |
| 9251 | } |
| 9252 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') |
| 9253 | { |
| 9254 | mask &= ~ (7 << 3); |
| 9255 | mask |= 5 << 3; |
| 9256 | } |
| 9257 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') |
| 9258 | { |
| 9259 | mask &= ~ (7 << 3); |
| 9260 | mask |= 6 << 3; |
| 9261 | } |
| 9262 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') |
| 9263 | mask |= (reg2 - 3) << 3; |
| 9264 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) |
| 9265 | mask |= (reg2 - 15) << 1; |
| 9266 | else if (reg1 == RA && reg2 == RA) |
| 9267 | mask |= 1; |
| 9268 | else |
| 9269 | { |
| 9270 | as_bad (_("invalid register list")); |
| 9271 | break; |
| 9272 | } |
| 9273 | } |
| 9274 | /* The mask is filled in in the opcode table for the |
| 9275 | benefit of the disassembler. We remove it before |
| 9276 | applying the actual mask. */ |
| 9277 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); |
| 9278 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; |
| 9279 | } |
| 9280 | continue; |
| 9281 | |
| 9282 | case 'e': /* extend code */ |
| 9283 | my_getExpression (&imm_expr, s); |
| 9284 | check_absolute_expr (ip, &imm_expr); |
| 9285 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) |
| 9286 | { |
| 9287 | as_warn (_("Invalid value for `%s' (%lu)"), |
| 9288 | ip->insn_mo->name, |
| 9289 | (unsigned long) imm_expr.X_add_number); |
| 9290 | imm_expr.X_add_number &= 0x7ff; |
| 9291 | } |
| 9292 | ip->insn_opcode |= imm_expr.X_add_number; |
| 9293 | imm_expr.X_op = O_absent; |
| 9294 | s = expr_end; |
| 9295 | continue; |
| 9296 | |
| 9297 | default: |
| 9298 | internalError (); |
| 9299 | } |
| 9300 | break; |
| 9301 | } |
| 9302 | |
| 9303 | /* Args don't match. */ |
| 9304 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && |
| 9305 | strcmp (insn->name, insn[1].name) == 0) |
| 9306 | { |
| 9307 | ++insn; |
| 9308 | s = argsstart; |
| 9309 | continue; |
| 9310 | } |
| 9311 | |
| 9312 | insn_error = _("illegal operands"); |
| 9313 | |
| 9314 | return; |
| 9315 | } |
| 9316 | } |
| 9317 | |
| 9318 | /* This structure holds information we know about a mips16 immediate |
| 9319 | argument type. */ |
| 9320 | |
| 9321 | struct mips16_immed_operand |
| 9322 | { |
| 9323 | /* The type code used in the argument string in the opcode table. */ |
| 9324 | int type; |
| 9325 | /* The number of bits in the short form of the opcode. */ |
| 9326 | int nbits; |
| 9327 | /* The number of bits in the extended form of the opcode. */ |
| 9328 | int extbits; |
| 9329 | /* The amount by which the short form is shifted when it is used; |
| 9330 | for example, the sw instruction has a shift count of 2. */ |
| 9331 | int shift; |
| 9332 | /* The amount by which the short form is shifted when it is stored |
| 9333 | into the instruction code. */ |
| 9334 | int op_shift; |
| 9335 | /* Non-zero if the short form is unsigned. */ |
| 9336 | int unsp; |
| 9337 | /* Non-zero if the extended form is unsigned. */ |
| 9338 | int extu; |
| 9339 | /* Non-zero if the value is PC relative. */ |
| 9340 | int pcrel; |
| 9341 | }; |
| 9342 | |
| 9343 | /* The mips16 immediate operand types. */ |
| 9344 | |
| 9345 | static const struct mips16_immed_operand mips16_immed_operands[] = |
| 9346 | { |
| 9347 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, |
| 9348 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, |
| 9349 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, |
| 9350 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, |
| 9351 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, |
| 9352 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, |
| 9353 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, |
| 9354 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, |
| 9355 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, |
| 9356 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, |
| 9357 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, |
| 9358 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, |
| 9359 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, |
| 9360 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, |
| 9361 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, |
| 9362 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, |
| 9363 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, |
| 9364 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, |
| 9365 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, |
| 9366 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, |
| 9367 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } |
| 9368 | }; |
| 9369 | |
| 9370 | #define MIPS16_NUM_IMMED \ |
| 9371 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) |
| 9372 | |
| 9373 | /* Handle a mips16 instruction with an immediate value. This or's the |
| 9374 | small immediate value into *INSN. It sets *USE_EXTEND to indicate |
| 9375 | whether an extended value is needed; if one is needed, it sets |
| 9376 | *EXTEND to the value. The argument type is TYPE. The value is VAL. |
| 9377 | If SMALL is true, an unextended opcode was explicitly requested. |
| 9378 | If EXT is true, an extended opcode was explicitly requested. If |
| 9379 | WARN is true, warn if EXT does not match reality. */ |
| 9380 | |
| 9381 | static void |
| 9382 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, |
| 9383 | extend) |
| 9384 | char *file; |
| 9385 | unsigned int line; |
| 9386 | int type; |
| 9387 | offsetT val; |
| 9388 | boolean warn; |
| 9389 | boolean small; |
| 9390 | boolean ext; |
| 9391 | unsigned long *insn; |
| 9392 | boolean *use_extend; |
| 9393 | unsigned short *extend; |
| 9394 | { |
| 9395 | register const struct mips16_immed_operand *op; |
| 9396 | int mintiny, maxtiny; |
| 9397 | boolean needext; |
| 9398 | |
| 9399 | op = mips16_immed_operands; |
| 9400 | while (op->type != type) |
| 9401 | { |
| 9402 | ++op; |
| 9403 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
| 9404 | } |
| 9405 | |
| 9406 | if (op->unsp) |
| 9407 | { |
| 9408 | if (type == '<' || type == '>' || type == '[' || type == ']') |
| 9409 | { |
| 9410 | mintiny = 1; |
| 9411 | maxtiny = 1 << op->nbits; |
| 9412 | } |
| 9413 | else |
| 9414 | { |
| 9415 | mintiny = 0; |
| 9416 | maxtiny = (1 << op->nbits) - 1; |
| 9417 | } |
| 9418 | } |
| 9419 | else |
| 9420 | { |
| 9421 | mintiny = - (1 << (op->nbits - 1)); |
| 9422 | maxtiny = (1 << (op->nbits - 1)) - 1; |
| 9423 | } |
| 9424 | |
| 9425 | /* Branch offsets have an implicit 0 in the lowest bit. */ |
| 9426 | if (type == 'p' || type == 'q') |
| 9427 | val /= 2; |
| 9428 | |
| 9429 | if ((val & ((1 << op->shift) - 1)) != 0 |
| 9430 | || val < (mintiny << op->shift) |
| 9431 | || val > (maxtiny << op->shift)) |
| 9432 | needext = true; |
| 9433 | else |
| 9434 | needext = false; |
| 9435 | |
| 9436 | if (warn && ext && ! needext) |
| 9437 | as_warn_where (file, line, |
| 9438 | _("extended operand requested but not required")); |
| 9439 | if (small && needext) |
| 9440 | as_bad_where (file, line, _("invalid unextended operand value")); |
| 9441 | |
| 9442 | if (small || (! ext && ! needext)) |
| 9443 | { |
| 9444 | int insnval; |
| 9445 | |
| 9446 | *use_extend = false; |
| 9447 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
| 9448 | insnval <<= op->op_shift; |
| 9449 | *insn |= insnval; |
| 9450 | } |
| 9451 | else |
| 9452 | { |
| 9453 | long minext, maxext; |
| 9454 | int extval; |
| 9455 | |
| 9456 | if (op->extu) |
| 9457 | { |
| 9458 | minext = 0; |
| 9459 | maxext = (1 << op->extbits) - 1; |
| 9460 | } |
| 9461 | else |
| 9462 | { |
| 9463 | minext = - (1 << (op->extbits - 1)); |
| 9464 | maxext = (1 << (op->extbits - 1)) - 1; |
| 9465 | } |
| 9466 | if (val < minext || val > maxext) |
| 9467 | as_bad_where (file, line, |
| 9468 | _("operand value out of range for instruction")); |
| 9469 | |
| 9470 | *use_extend = true; |
| 9471 | if (op->extbits == 16) |
| 9472 | { |
| 9473 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); |
| 9474 | val &= 0x1f; |
| 9475 | } |
| 9476 | else if (op->extbits == 15) |
| 9477 | { |
| 9478 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); |
| 9479 | val &= 0xf; |
| 9480 | } |
| 9481 | else |
| 9482 | { |
| 9483 | extval = ((val & 0x1f) << 6) | (val & 0x20); |
| 9484 | val = 0; |
| 9485 | } |
| 9486 | |
| 9487 | *extend = (unsigned short) extval; |
| 9488 | *insn |= val; |
| 9489 | } |
| 9490 | } |
| 9491 | \f |
| 9492 | static struct percent_op_match |
| 9493 | { |
| 9494 | const char *str; |
| 9495 | const enum small_ex_type type; |
| 9496 | } percent_op[] = |
| 9497 | { |
| 9498 | {"%lo", S_EX_LO}, |
| 9499 | #ifdef OBJ_ELF |
| 9500 | {"%call_hi", S_EX_CALL_HI}, |
| 9501 | {"%call_lo", S_EX_CALL_LO}, |
| 9502 | {"%call16", S_EX_CALL16}, |
| 9503 | {"%got_disp", S_EX_GOT_DISP}, |
| 9504 | {"%got_page", S_EX_GOT_PAGE}, |
| 9505 | {"%got_ofst", S_EX_GOT_OFST}, |
| 9506 | {"%got_hi", S_EX_GOT_HI}, |
| 9507 | {"%got_lo", S_EX_GOT_LO}, |
| 9508 | {"%got", S_EX_GOT}, |
| 9509 | {"%gp_rel", S_EX_GP_REL}, |
| 9510 | {"%half", S_EX_HALF}, |
| 9511 | {"%highest", S_EX_HIGHEST}, |
| 9512 | {"%higher", S_EX_HIGHER}, |
| 9513 | {"%neg", S_EX_NEG}, |
| 9514 | #endif |
| 9515 | {"%hi", S_EX_HI} |
| 9516 | }; |
| 9517 | |
| 9518 | /* Parse small expression input. STR gets adjusted to eat up whitespace. |
| 9519 | It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's |
| 9520 | can be nested, this is handled by blanking the innermost, parsing the |
| 9521 | rest by subsequent calls. */ |
| 9522 | |
| 9523 | static int |
| 9524 | my_getSmallParser (str, len, nestlevel) |
| 9525 | char **str; |
| 9526 | unsigned int *len; |
| 9527 | int *nestlevel; |
| 9528 | { |
| 9529 | *len = 0; |
| 9530 | *str += strspn (*str, " \t"); |
| 9531 | /* Check for expression in parentheses. */ |
| 9532 | if (**str == '(') |
| 9533 | { |
| 9534 | char *b = *str + 1 + strspn (*str + 1, " \t"); |
| 9535 | char *e; |
| 9536 | |
| 9537 | /* Check for base register. */ |
| 9538 | if (b[0] == '$') |
| 9539 | { |
| 9540 | if (strchr (b, ')') |
| 9541 | && (e = b + strcspn (b, ") \t")) |
| 9542 | && e - b > 1 && e - b < 4) |
| 9543 | { |
| 9544 | if ((e - b == 3 |
| 9545 | && ((b[1] == 'f' && b[2] == 'p') |
| 9546 | || (b[1] == 's' && b[2] == 'p') |
| 9547 | || (b[1] == 'g' && b[2] == 'p') |
| 9548 | || (b[1] == 'a' && b[2] == 't') |
| 9549 | || (ISDIGIT (b[1]) |
| 9550 | && ISDIGIT (b[2])))) |
| 9551 | || (ISDIGIT (b[1]))) |
| 9552 | { |
| 9553 | *len = strcspn (*str, ")") + 1; |
| 9554 | return S_EX_REGISTER; |
| 9555 | } |
| 9556 | } |
| 9557 | } |
| 9558 | /* Check for percent_op (in parentheses). */ |
| 9559 | else if (b[0] == '%') |
| 9560 | { |
| 9561 | *str = b; |
| 9562 | return my_getPercentOp (str, len, nestlevel); |
| 9563 | } |
| 9564 | |
| 9565 | /* Some other expression in the parentheses, which can contain |
| 9566 | parentheses itself. Attempt to find the matching one. */ |
| 9567 | { |
| 9568 | int pcnt = 1; |
| 9569 | char *s; |
| 9570 | |
| 9571 | *len = 1; |
| 9572 | for (s = *str + 1; *s && pcnt; s++, (*len)++) |
| 9573 | { |
| 9574 | if (*s == '(') |
| 9575 | ++pcnt; |
| 9576 | else if (*s == ')') |
| 9577 | --pcnt; |
| 9578 | } |
| 9579 | } |
| 9580 | } |
| 9581 | /* Check for percent_op (outside of parentheses). */ |
| 9582 | else if (*str[0] == '%') |
| 9583 | return my_getPercentOp (str, len, nestlevel); |
| 9584 | |
| 9585 | /* Any other expression. */ |
| 9586 | return S_EX_NONE; |
| 9587 | } |
| 9588 | |
| 9589 | static int |
| 9590 | my_getPercentOp (str, len, nestlevel) |
| 9591 | char **str; |
| 9592 | unsigned int *len; |
| 9593 | int *nestlevel; |
| 9594 | { |
| 9595 | char *tmp = *str + 1; |
| 9596 | unsigned int i = 0; |
| 9597 | |
| 9598 | while (ISALPHA (*tmp) || *tmp == '_') |
| 9599 | { |
| 9600 | *tmp = TOLOWER (*tmp); |
| 9601 | tmp++; |
| 9602 | } |
| 9603 | while (i < (sizeof (percent_op) / sizeof (struct percent_op_match))) |
| 9604 | { |
| 9605 | if (strncmp (*str, percent_op[i].str, strlen (percent_op[i].str))) |
| 9606 | i++; |
| 9607 | else |
| 9608 | { |
| 9609 | int type = percent_op[i].type; |
| 9610 | |
| 9611 | /* Only %hi and %lo are allowed for OldABI. */ |
| 9612 | if (! HAVE_NEWABI && type != S_EX_HI && type != S_EX_LO) |
| 9613 | return S_EX_NONE; |
| 9614 | |
| 9615 | *len = strlen (percent_op[i].str); |
| 9616 | ++(*nestlevel); |
| 9617 | return type; |
| 9618 | } |
| 9619 | } |
| 9620 | return S_EX_NONE; |
| 9621 | } |
| 9622 | |
| 9623 | static int |
| 9624 | my_getSmallExpression (ep, str) |
| 9625 | expressionS *ep; |
| 9626 | char *str; |
| 9627 | { |
| 9628 | static char *oldstr = NULL; |
| 9629 | int c = S_EX_NONE; |
| 9630 | int oldc; |
| 9631 | int nestlevel = -1; |
| 9632 | unsigned int len; |
| 9633 | |
| 9634 | /* Don't update oldstr if the last call had nested percent_op's. We need |
| 9635 | it to parse the outer ones later. */ |
| 9636 | if (! oldstr) |
| 9637 | oldstr = str; |
| 9638 | |
| 9639 | do |
| 9640 | { |
| 9641 | oldc = c; |
| 9642 | c = my_getSmallParser (&str, &len, &nestlevel); |
| 9643 | if (c != S_EX_NONE && c != S_EX_REGISTER) |
| 9644 | str += len; |
| 9645 | } |
| 9646 | while (c != S_EX_NONE && c != S_EX_REGISTER); |
| 9647 | |
| 9648 | if (nestlevel >= 0) |
| 9649 | { |
| 9650 | /* A percent_op was encountered. Don't try to get an expression if |
| 9651 | it is already blanked out. */ |
| 9652 | if (*(str + strspn (str + 1, " )")) != ')') |
| 9653 | { |
| 9654 | char save; |
| 9655 | |
| 9656 | /* Let my_getExpression() stop at the closing parenthesis. */ |
| 9657 | save = *(str + len); |
| 9658 | *(str + len) = '\0'; |
| 9659 | my_getExpression (ep, str); |
| 9660 | *(str + len) = save; |
| 9661 | } |
| 9662 | if (nestlevel > 0) |
| 9663 | { |
| 9664 | /* Blank out including the % sign and the proper matching |
| 9665 | parenthesis. */ |
| 9666 | int pcnt = 1; |
| 9667 | char *s = strrchr (oldstr, '%'); |
| 9668 | char *end; |
| 9669 | |
| 9670 | for (end = strchr (s, '(') + 1; *end && pcnt; end++) |
| 9671 | { |
| 9672 | if (*end == '(') |
| 9673 | ++pcnt; |
| 9674 | else if (*end == ')') |
| 9675 | --pcnt; |
| 9676 | } |
| 9677 | |
| 9678 | memset (s, ' ', end - s); |
| 9679 | str = oldstr; |
| 9680 | } |
| 9681 | else |
| 9682 | expr_end = str + len; |
| 9683 | |
| 9684 | c = oldc; |
| 9685 | } |
| 9686 | else if (c == S_EX_NONE) |
| 9687 | { |
| 9688 | my_getExpression (ep, str); |
| 9689 | } |
| 9690 | else if (c == S_EX_REGISTER) |
| 9691 | { |
| 9692 | ep->X_op = O_constant; |
| 9693 | expr_end = str; |
| 9694 | ep->X_add_symbol = NULL; |
| 9695 | ep->X_op_symbol = NULL; |
| 9696 | ep->X_add_number = 0; |
| 9697 | } |
| 9698 | else |
| 9699 | { |
| 9700 | as_fatal (_("internal error")); |
| 9701 | } |
| 9702 | |
| 9703 | if (nestlevel <= 0) |
| 9704 | /* All percent_op's have been handled. */ |
| 9705 | oldstr = NULL; |
| 9706 | |
| 9707 | return c; |
| 9708 | } |
| 9709 | |
| 9710 | static void |
| 9711 | my_getExpression (ep, str) |
| 9712 | expressionS *ep; |
| 9713 | char *str; |
| 9714 | { |
| 9715 | char *save_in; |
| 9716 | valueT val; |
| 9717 | |
| 9718 | save_in = input_line_pointer; |
| 9719 | input_line_pointer = str; |
| 9720 | expression (ep); |
| 9721 | expr_end = input_line_pointer; |
| 9722 | input_line_pointer = save_in; |
| 9723 | |
| 9724 | /* If we are in mips16 mode, and this is an expression based on `.', |
| 9725 | then we bump the value of the symbol by 1 since that is how other |
| 9726 | text symbols are handled. We don't bother to handle complex |
| 9727 | expressions, just `.' plus or minus a constant. */ |
| 9728 | if (mips_opts.mips16 |
| 9729 | && ep->X_op == O_symbol |
| 9730 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 |
| 9731 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg |
| 9732 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
| 9733 | && symbol_constant_p (ep->X_add_symbol) |
| 9734 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
| 9735 | S_SET_VALUE (ep->X_add_symbol, val + 1); |
| 9736 | } |
| 9737 | |
| 9738 | /* Turn a string in input_line_pointer into a floating point constant |
| 9739 | of type TYPE, and store the appropriate bytes in *LITP. The number |
| 9740 | of LITTLENUMS emitted is stored in *SIZEP. An error message is |
| 9741 | returned, or NULL on OK. */ |
| 9742 | |
| 9743 | char * |
| 9744 | md_atof (type, litP, sizeP) |
| 9745 | int type; |
| 9746 | char *litP; |
| 9747 | int *sizeP; |
| 9748 | { |
| 9749 | int prec; |
| 9750 | LITTLENUM_TYPE words[4]; |
| 9751 | char *t; |
| 9752 | int i; |
| 9753 | |
| 9754 | switch (type) |
| 9755 | { |
| 9756 | case 'f': |
| 9757 | prec = 2; |
| 9758 | break; |
| 9759 | |
| 9760 | case 'd': |
| 9761 | prec = 4; |
| 9762 | break; |
| 9763 | |
| 9764 | default: |
| 9765 | *sizeP = 0; |
| 9766 | return _("bad call to md_atof"); |
| 9767 | } |
| 9768 | |
| 9769 | t = atof_ieee (input_line_pointer, type, words); |
| 9770 | if (t) |
| 9771 | input_line_pointer = t; |
| 9772 | |
| 9773 | *sizeP = prec * 2; |
| 9774 | |
| 9775 | if (! target_big_endian) |
| 9776 | { |
| 9777 | for (i = prec - 1; i >= 0; i--) |
| 9778 | { |
| 9779 | md_number_to_chars (litP, (valueT) words[i], 2); |
| 9780 | litP += 2; |
| 9781 | } |
| 9782 | } |
| 9783 | else |
| 9784 | { |
| 9785 | for (i = 0; i < prec; i++) |
| 9786 | { |
| 9787 | md_number_to_chars (litP, (valueT) words[i], 2); |
| 9788 | litP += 2; |
| 9789 | } |
| 9790 | } |
| 9791 | |
| 9792 | return NULL; |
| 9793 | } |
| 9794 | |
| 9795 | void |
| 9796 | md_number_to_chars (buf, val, n) |
| 9797 | char *buf; |
| 9798 | valueT val; |
| 9799 | int n; |
| 9800 | { |
| 9801 | if (target_big_endian) |
| 9802 | number_to_chars_bigendian (buf, val, n); |
| 9803 | else |
| 9804 | number_to_chars_littleendian (buf, val, n); |
| 9805 | } |
| 9806 | \f |
| 9807 | #ifdef OBJ_ELF |
| 9808 | static int support_64bit_objects(void) |
| 9809 | { |
| 9810 | const char **list, **l; |
| 9811 | |
| 9812 | list = bfd_target_list (); |
| 9813 | for (l = list; *l != NULL; l++) |
| 9814 | #ifdef TE_TMIPS |
| 9815 | /* This is traditional mips */ |
| 9816 | if (strcmp (*l, "elf64-tradbigmips") == 0 |
| 9817 | || strcmp (*l, "elf64-tradlittlemips") == 0) |
| 9818 | #else |
| 9819 | if (strcmp (*l, "elf64-bigmips") == 0 |
| 9820 | || strcmp (*l, "elf64-littlemips") == 0) |
| 9821 | #endif |
| 9822 | break; |
| 9823 | free (list); |
| 9824 | return (*l != NULL); |
| 9825 | } |
| 9826 | #endif /* OBJ_ELF */ |
| 9827 | |
| 9828 | const char *md_shortopts = "nO::g::G:"; |
| 9829 | |
| 9830 | struct option md_longopts[] = |
| 9831 | { |
| 9832 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) |
| 9833 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
| 9834 | {"mips1", no_argument, NULL, OPTION_MIPS1}, |
| 9835 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) |
| 9836 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
| 9837 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) |
| 9838 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
| 9839 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) |
| 9840 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
| 9841 | #define OPTION_MIPS5 (OPTION_MD_BASE + 5) |
| 9842 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
| 9843 | #define OPTION_MIPS32 (OPTION_MD_BASE + 6) |
| 9844 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
| 9845 | #define OPTION_MIPS64 (OPTION_MD_BASE + 7) |
| 9846 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
| 9847 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8) |
| 9848 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
| 9849 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
| 9850 | {"trap", no_argument, NULL, OPTION_TRAP}, |
| 9851 | {"no-break", no_argument, NULL, OPTION_TRAP}, |
| 9852 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
| 9853 | {"break", no_argument, NULL, OPTION_BREAK}, |
| 9854 | {"no-trap", no_argument, NULL, OPTION_BREAK}, |
| 9855 | #define OPTION_EB (OPTION_MD_BASE + 11) |
| 9856 | {"EB", no_argument, NULL, OPTION_EB}, |
| 9857 | #define OPTION_EL (OPTION_MD_BASE + 12) |
| 9858 | {"EL", no_argument, NULL, OPTION_EL}, |
| 9859 | #define OPTION_MIPS16 (OPTION_MD_BASE + 13) |
| 9860 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
| 9861 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14) |
| 9862 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
| 9863 | #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15) |
| 9864 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
| 9865 | #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16) |
| 9866 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
| 9867 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
| 9868 | #define OPTION_FP32 (OPTION_MD_BASE + 17) |
| 9869 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
| 9870 | #define OPTION_GP32 (OPTION_MD_BASE + 18) |
| 9871 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
| 9872 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19) |
| 9873 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
| 9874 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20) |
| 9875 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
| 9876 | #define OPTION_MARCH (OPTION_MD_BASE + 21) |
| 9877 | {"march", required_argument, NULL, OPTION_MARCH}, |
| 9878 | #define OPTION_MTUNE (OPTION_MD_BASE + 22) |
| 9879 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
| 9880 | #define OPTION_FP64 (OPTION_MD_BASE + 23) |
| 9881 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
| 9882 | #define OPTION_M4650 (OPTION_MD_BASE + 24) |
| 9883 | {"m4650", no_argument, NULL, OPTION_M4650}, |
| 9884 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 25) |
| 9885 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
| 9886 | #define OPTION_M4010 (OPTION_MD_BASE + 26) |
| 9887 | {"m4010", no_argument, NULL, OPTION_M4010}, |
| 9888 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 27) |
| 9889 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
| 9890 | #define OPTION_M4100 (OPTION_MD_BASE + 28) |
| 9891 | {"m4100", no_argument, NULL, OPTION_M4100}, |
| 9892 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 29) |
| 9893 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
| 9894 | #define OPTION_M3900 (OPTION_MD_BASE + 30) |
| 9895 | {"m3900", no_argument, NULL, OPTION_M3900}, |
| 9896 | #define OPTION_NO_M3900 (OPTION_MD_BASE + 31) |
| 9897 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
| 9898 | #define OPTION_GP64 (OPTION_MD_BASE + 32) |
| 9899 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
| 9900 | #define OPTION_MIPS3D (OPTION_MD_BASE + 33) |
| 9901 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, |
| 9902 | #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34) |
| 9903 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, |
| 9904 | #define OPTION_MDMX (OPTION_MD_BASE + 35) |
| 9905 | {"mdmx", no_argument, NULL, OPTION_MDMX}, |
| 9906 | #define OPTION_NO_MDMX (OPTION_MD_BASE + 36) |
| 9907 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, |
| 9908 | #ifdef OBJ_ELF |
| 9909 | #define OPTION_ELF_BASE (OPTION_MD_BASE + 37) |
| 9910 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
| 9911 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
| 9912 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, |
| 9913 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
| 9914 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
| 9915 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
| 9916 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
| 9917 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
| 9918 | {"mabi", required_argument, NULL, OPTION_MABI}, |
| 9919 | #define OPTION_32 (OPTION_ELF_BASE + 4) |
| 9920 | {"32", no_argument, NULL, OPTION_32}, |
| 9921 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
| 9922 | {"n32", no_argument, NULL, OPTION_N32}, |
| 9923 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
| 9924 | {"64", no_argument, NULL, OPTION_64}, |
| 9925 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
| 9926 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, |
| 9927 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) |
| 9928 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, |
| 9929 | #endif /* OBJ_ELF */ |
| 9930 | {NULL, no_argument, NULL, 0} |
| 9931 | }; |
| 9932 | size_t md_longopts_size = sizeof (md_longopts); |
| 9933 | |
| 9934 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
| 9935 | NEW_VALUE. Warn if another value was already specified. Note: |
| 9936 | we have to defer parsing the -march and -mtune arguments in order |
| 9937 | to handle 'from-abi' correctly, since the ABI might be specified |
| 9938 | in a later argument. */ |
| 9939 | |
| 9940 | static void |
| 9941 | mips_set_option_string (string_ptr, new_value) |
| 9942 | const char **string_ptr, *new_value; |
| 9943 | { |
| 9944 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) |
| 9945 | as_warn (_("A different %s was already specified, is now %s"), |
| 9946 | string_ptr == &mips_arch_string ? "-march" : "-mtune", |
| 9947 | new_value); |
| 9948 | |
| 9949 | *string_ptr = new_value; |
| 9950 | } |
| 9951 | |
| 9952 | int |
| 9953 | md_parse_option (c, arg) |
| 9954 | int c; |
| 9955 | char *arg; |
| 9956 | { |
| 9957 | switch (c) |
| 9958 | { |
| 9959 | case OPTION_CONSTRUCT_FLOATS: |
| 9960 | mips_disable_float_construction = 0; |
| 9961 | break; |
| 9962 | |
| 9963 | case OPTION_NO_CONSTRUCT_FLOATS: |
| 9964 | mips_disable_float_construction = 1; |
| 9965 | break; |
| 9966 | |
| 9967 | case OPTION_TRAP: |
| 9968 | mips_trap = 1; |
| 9969 | break; |
| 9970 | |
| 9971 | case OPTION_BREAK: |
| 9972 | mips_trap = 0; |
| 9973 | break; |
| 9974 | |
| 9975 | case OPTION_EB: |
| 9976 | target_big_endian = 1; |
| 9977 | break; |
| 9978 | |
| 9979 | case OPTION_EL: |
| 9980 | target_big_endian = 0; |
| 9981 | break; |
| 9982 | |
| 9983 | case 'n': |
| 9984 | warn_nops = 1; |
| 9985 | break; |
| 9986 | |
| 9987 | case 'O': |
| 9988 | if (arg && arg[1] == '0') |
| 9989 | mips_optimize = 1; |
| 9990 | else |
| 9991 | mips_optimize = 2; |
| 9992 | break; |
| 9993 | |
| 9994 | case 'g': |
| 9995 | if (arg == NULL) |
| 9996 | mips_debug = 2; |
| 9997 | else |
| 9998 | mips_debug = atoi (arg); |
| 9999 | /* When the MIPS assembler sees -g or -g2, it does not do |
| 10000 | optimizations which limit full symbolic debugging. We take |
| 10001 | that to be equivalent to -O0. */ |
| 10002 | if (mips_debug == 2) |
| 10003 | mips_optimize = 1; |
| 10004 | break; |
| 10005 | |
| 10006 | case OPTION_MIPS1: |
| 10007 | file_mips_isa = ISA_MIPS1; |
| 10008 | break; |
| 10009 | |
| 10010 | case OPTION_MIPS2: |
| 10011 | file_mips_isa = ISA_MIPS2; |
| 10012 | break; |
| 10013 | |
| 10014 | case OPTION_MIPS3: |
| 10015 | file_mips_isa = ISA_MIPS3; |
| 10016 | break; |
| 10017 | |
| 10018 | case OPTION_MIPS4: |
| 10019 | file_mips_isa = ISA_MIPS4; |
| 10020 | break; |
| 10021 | |
| 10022 | case OPTION_MIPS5: |
| 10023 | file_mips_isa = ISA_MIPS5; |
| 10024 | break; |
| 10025 | |
| 10026 | case OPTION_MIPS32: |
| 10027 | file_mips_isa = ISA_MIPS32; |
| 10028 | break; |
| 10029 | |
| 10030 | case OPTION_MIPS64: |
| 10031 | file_mips_isa = ISA_MIPS64; |
| 10032 | break; |
| 10033 | |
| 10034 | case OPTION_MTUNE: |
| 10035 | mips_set_option_string (&mips_tune_string, arg); |
| 10036 | break; |
| 10037 | |
| 10038 | case OPTION_MARCH: |
| 10039 | mips_set_option_string (&mips_arch_string, arg); |
| 10040 | break; |
| 10041 | |
| 10042 | case OPTION_M4650: |
| 10043 | mips_set_option_string (&mips_arch_string, "4650"); |
| 10044 | mips_set_option_string (&mips_tune_string, "4650"); |
| 10045 | break; |
| 10046 | |
| 10047 | case OPTION_NO_M4650: |
| 10048 | break; |
| 10049 | |
| 10050 | case OPTION_M4010: |
| 10051 | mips_set_option_string (&mips_arch_string, "4010"); |
| 10052 | mips_set_option_string (&mips_tune_string, "4010"); |
| 10053 | break; |
| 10054 | |
| 10055 | case OPTION_NO_M4010: |
| 10056 | break; |
| 10057 | |
| 10058 | case OPTION_M4100: |
| 10059 | mips_set_option_string (&mips_arch_string, "4100"); |
| 10060 | mips_set_option_string (&mips_tune_string, "4100"); |
| 10061 | break; |
| 10062 | |
| 10063 | case OPTION_NO_M4100: |
| 10064 | break; |
| 10065 | |
| 10066 | case OPTION_M3900: |
| 10067 | mips_set_option_string (&mips_arch_string, "3900"); |
| 10068 | mips_set_option_string (&mips_tune_string, "3900"); |
| 10069 | break; |
| 10070 | |
| 10071 | case OPTION_NO_M3900: |
| 10072 | break; |
| 10073 | |
| 10074 | case OPTION_MDMX: |
| 10075 | mips_opts.ase_mdmx = 1; |
| 10076 | break; |
| 10077 | |
| 10078 | case OPTION_NO_MDMX: |
| 10079 | mips_opts.ase_mdmx = 0; |
| 10080 | break; |
| 10081 | |
| 10082 | case OPTION_MIPS16: |
| 10083 | mips_opts.mips16 = 1; |
| 10084 | mips_no_prev_insn (false); |
| 10085 | break; |
| 10086 | |
| 10087 | case OPTION_NO_MIPS16: |
| 10088 | mips_opts.mips16 = 0; |
| 10089 | mips_no_prev_insn (false); |
| 10090 | break; |
| 10091 | |
| 10092 | case OPTION_MIPS3D: |
| 10093 | mips_opts.ase_mips3d = 1; |
| 10094 | break; |
| 10095 | |
| 10096 | case OPTION_NO_MIPS3D: |
| 10097 | mips_opts.ase_mips3d = 0; |
| 10098 | break; |
| 10099 | |
| 10100 | case OPTION_MEMBEDDED_PIC: |
| 10101 | mips_pic = EMBEDDED_PIC; |
| 10102 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) |
| 10103 | { |
| 10104 | as_bad (_("-G may not be used with embedded PIC code")); |
| 10105 | return 0; |
| 10106 | } |
| 10107 | g_switch_value = 0x7fffffff; |
| 10108 | break; |
| 10109 | |
| 10110 | #ifdef OBJ_ELF |
| 10111 | /* When generating ELF code, we permit -KPIC and -call_shared to |
| 10112 | select SVR4_PIC, and -non_shared to select no PIC. This is |
| 10113 | intended to be compatible with Irix 5. */ |
| 10114 | case OPTION_CALL_SHARED: |
| 10115 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
| 10116 | { |
| 10117 | as_bad (_("-call_shared is supported only for ELF format")); |
| 10118 | return 0; |
| 10119 | } |
| 10120 | mips_pic = SVR4_PIC; |
| 10121 | if (g_switch_seen && g_switch_value != 0) |
| 10122 | { |
| 10123 | as_bad (_("-G may not be used with SVR4 PIC code")); |
| 10124 | return 0; |
| 10125 | } |
| 10126 | g_switch_value = 0; |
| 10127 | break; |
| 10128 | |
| 10129 | case OPTION_NON_SHARED: |
| 10130 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
| 10131 | { |
| 10132 | as_bad (_("-non_shared is supported only for ELF format")); |
| 10133 | return 0; |
| 10134 | } |
| 10135 | mips_pic = NO_PIC; |
| 10136 | break; |
| 10137 | |
| 10138 | /* The -xgot option tells the assembler to use 32 offsets when |
| 10139 | accessing the got in SVR4_PIC mode. It is for Irix |
| 10140 | compatibility. */ |
| 10141 | case OPTION_XGOT: |
| 10142 | mips_big_got = 1; |
| 10143 | break; |
| 10144 | #endif /* OBJ_ELF */ |
| 10145 | |
| 10146 | case 'G': |
| 10147 | if (! USE_GLOBAL_POINTER_OPT) |
| 10148 | { |
| 10149 | as_bad (_("-G is not supported for this configuration")); |
| 10150 | return 0; |
| 10151 | } |
| 10152 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) |
| 10153 | { |
| 10154 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); |
| 10155 | return 0; |
| 10156 | } |
| 10157 | else |
| 10158 | g_switch_value = atoi (arg); |
| 10159 | g_switch_seen = 1; |
| 10160 | break; |
| 10161 | |
| 10162 | #ifdef OBJ_ELF |
| 10163 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
| 10164 | and -mabi=64. */ |
| 10165 | case OPTION_32: |
| 10166 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
| 10167 | { |
| 10168 | as_bad (_("-32 is supported for ELF format only")); |
| 10169 | return 0; |
| 10170 | } |
| 10171 | mips_abi = O32_ABI; |
| 10172 | break; |
| 10173 | |
| 10174 | case OPTION_N32: |
| 10175 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
| 10176 | { |
| 10177 | as_bad (_("-n32 is supported for ELF format only")); |
| 10178 | return 0; |
| 10179 | } |
| 10180 | mips_abi = N32_ABI; |
| 10181 | break; |
| 10182 | |
| 10183 | case OPTION_64: |
| 10184 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
| 10185 | { |
| 10186 | as_bad (_("-64 is supported for ELF format only")); |
| 10187 | return 0; |
| 10188 | } |
| 10189 | mips_abi = N64_ABI; |
| 10190 | if (! support_64bit_objects()) |
| 10191 | as_fatal (_("No compiled in support for 64 bit object file format")); |
| 10192 | break; |
| 10193 | #endif /* OBJ_ELF */ |
| 10194 | |
| 10195 | case OPTION_GP32: |
| 10196 | file_mips_gp32 = 1; |
| 10197 | break; |
| 10198 | |
| 10199 | case OPTION_GP64: |
| 10200 | file_mips_gp32 = 0; |
| 10201 | break; |
| 10202 | |
| 10203 | case OPTION_FP32: |
| 10204 | file_mips_fp32 = 1; |
| 10205 | break; |
| 10206 | |
| 10207 | case OPTION_FP64: |
| 10208 | file_mips_fp32 = 0; |
| 10209 | break; |
| 10210 | |
| 10211 | #ifdef OBJ_ELF |
| 10212 | case OPTION_MABI: |
| 10213 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
| 10214 | { |
| 10215 | as_bad (_("-mabi is supported for ELF format only")); |
| 10216 | return 0; |
| 10217 | } |
| 10218 | if (strcmp (arg, "32") == 0) |
| 10219 | mips_abi = O32_ABI; |
| 10220 | else if (strcmp (arg, "o64") == 0) |
| 10221 | mips_abi = O64_ABI; |
| 10222 | else if (strcmp (arg, "n32") == 0) |
| 10223 | mips_abi = N32_ABI; |
| 10224 | else if (strcmp (arg, "64") == 0) |
| 10225 | { |
| 10226 | mips_abi = N64_ABI; |
| 10227 | if (! support_64bit_objects()) |
| 10228 | as_fatal (_("No compiled in support for 64 bit object file " |
| 10229 | "format")); |
| 10230 | } |
| 10231 | else if (strcmp (arg, "eabi") == 0) |
| 10232 | mips_abi = EABI_ABI; |
| 10233 | else |
| 10234 | { |
| 10235 | as_fatal (_("invalid abi -mabi=%s"), arg); |
| 10236 | return 0; |
| 10237 | } |
| 10238 | break; |
| 10239 | #endif /* OBJ_ELF */ |
| 10240 | |
| 10241 | case OPTION_M7000_HILO_FIX: |
| 10242 | mips_7000_hilo_fix = true; |
| 10243 | break; |
| 10244 | |
| 10245 | case OPTION_MNO_7000_HILO_FIX: |
| 10246 | mips_7000_hilo_fix = false; |
| 10247 | break; |
| 10248 | |
| 10249 | #ifdef OBJ_ELF |
| 10250 | case OPTION_MDEBUG: |
| 10251 | mips_flag_mdebug = true; |
| 10252 | break; |
| 10253 | |
| 10254 | case OPTION_NO_MDEBUG: |
| 10255 | mips_flag_mdebug = false; |
| 10256 | break; |
| 10257 | #endif /* OBJ_ELF */ |
| 10258 | |
| 10259 | default: |
| 10260 | return 0; |
| 10261 | } |
| 10262 | |
| 10263 | return 1; |
| 10264 | } |
| 10265 | \f |
| 10266 | /* Set up globals to generate code for the ISA or processor |
| 10267 | described by INFO. */ |
| 10268 | |
| 10269 | static void |
| 10270 | mips_set_architecture (info) |
| 10271 | const struct mips_cpu_info *info; |
| 10272 | { |
| 10273 | if (info != 0) |
| 10274 | { |
| 10275 | mips_arch_info = info; |
| 10276 | mips_arch = info->cpu; |
| 10277 | mips_opts.isa = info->isa; |
| 10278 | } |
| 10279 | } |
| 10280 | |
| 10281 | |
| 10282 | /* Likewise for tuning. */ |
| 10283 | |
| 10284 | static void |
| 10285 | mips_set_tune (info) |
| 10286 | const struct mips_cpu_info *info; |
| 10287 | { |
| 10288 | if (info != 0) |
| 10289 | { |
| 10290 | mips_tune_info = info; |
| 10291 | mips_tune = info->cpu; |
| 10292 | } |
| 10293 | } |
| 10294 | |
| 10295 | |
| 10296 | void |
| 10297 | mips_after_parse_args () |
| 10298 | { |
| 10299 | /* GP relative stuff not working for PE */ |
| 10300 | if (strncmp (TARGET_OS, "pe", 2) == 0 |
| 10301 | && g_switch_value != 0) |
| 10302 | { |
| 10303 | if (g_switch_seen) |
| 10304 | as_bad (_("-G not supported in this configuration.")); |
| 10305 | g_switch_value = 0; |
| 10306 | } |
| 10307 | |
| 10308 | /* The following code determines the architecture and register size. |
| 10309 | Similar code was added to GCC 3.3 (see override_options() in |
| 10310 | config/mips/mips.c). The GAS and GCC code should be kept in sync |
| 10311 | as much as possible. */ |
| 10312 | |
| 10313 | if (mips_arch_string != 0) |
| 10314 | mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string)); |
| 10315 | |
| 10316 | if (mips_tune_string != 0) |
| 10317 | mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string)); |
| 10318 | |
| 10319 | if (file_mips_isa != ISA_UNKNOWN) |
| 10320 | { |
| 10321 | /* Handle -mipsN. At this point, file_mips_isa contains the |
| 10322 | ISA level specified by -mipsN, while mips_opts.isa contains |
| 10323 | the -march selection (if any). */ |
| 10324 | if (mips_arch_info != 0) |
| 10325 | { |
| 10326 | /* -march takes precedence over -mipsN, since it is more descriptive. |
| 10327 | There's no harm in specifying both as long as the ISA levels |
| 10328 | are the same. */ |
| 10329 | if (file_mips_isa != mips_opts.isa) |
| 10330 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
| 10331 | mips_cpu_info_from_isa (file_mips_isa)->name, |
| 10332 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
| 10333 | } |
| 10334 | else |
| 10335 | mips_set_architecture (mips_cpu_info_from_isa (file_mips_isa)); |
| 10336 | } |
| 10337 | |
| 10338 | if (mips_arch_info == 0) |
| 10339 | mips_set_architecture (mips_parse_cpu ("default CPU", |
| 10340 | MIPS_CPU_STRING_DEFAULT)); |
| 10341 | |
| 10342 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
| 10343 | as_bad ("-march=%s is not compatible with the selected ABI", |
| 10344 | mips_arch_info->name); |
| 10345 | |
| 10346 | /* Optimize for mips_arch, unless -mtune selects a different processor. */ |
| 10347 | if (mips_tune_info == 0) |
| 10348 | mips_set_tune (mips_arch_info); |
| 10349 | |
| 10350 | if (file_mips_gp32 >= 0) |
| 10351 | { |
| 10352 | /* The user specified the size of the integer registers. Make sure |
| 10353 | it agrees with the ABI and ISA. */ |
| 10354 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
| 10355 | as_bad (_("-mgp64 used with a 32-bit processor")); |
| 10356 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) |
| 10357 | as_bad (_("-mgp32 used with a 64-bit ABI")); |
| 10358 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) |
| 10359 | as_bad (_("-mgp64 used with a 32-bit ABI")); |
| 10360 | } |
| 10361 | else |
| 10362 | { |
| 10363 | /* Infer the integer register size from the ABI and processor. |
| 10364 | Restrict ourselves to 32-bit registers if that's all the |
| 10365 | processor has, or if the ABI cannot handle 64-bit registers. */ |
| 10366 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) |
| 10367 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); |
| 10368 | } |
| 10369 | |
| 10370 | /* ??? GAS treats single-float processors as though they had 64-bit |
| 10371 | float registers (although it complains when double-precision |
| 10372 | instructions are used). As things stand, saying they have 32-bit |
| 10373 | registers would lead to spurious "register must be even" messages. |
| 10374 | So here we assume float registers are always the same size as |
| 10375 | integer ones, unless the user says otherwise. */ |
| 10376 | if (file_mips_fp32 < 0) |
| 10377 | file_mips_fp32 = file_mips_gp32; |
| 10378 | |
| 10379 | /* End of GCC-shared inference code. */ |
| 10380 | |
| 10381 | /* ??? When do we want this flag to be set? Who uses it? */ |
| 10382 | if (file_mips_gp32 == 1 |
| 10383 | && mips_abi == NO_ABI |
| 10384 | && ISA_HAS_64BIT_REGS (mips_opts.isa)) |
| 10385 | mips_32bitmode = 1; |
| 10386 | |
| 10387 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) |
| 10388 | as_bad (_("trap exception not supported at ISA 1")); |
| 10389 | |
| 10390 | /* If the selected architecture includes support for ASEs, enable |
| 10391 | generation of code for them. */ |
| 10392 | if (mips_opts.mips16 == -1) |
| 10393 | mips_opts.mips16 = (CPU_HAS_MIPS16 (mips_arch)) ? 1 : 0; |
| 10394 | if (mips_opts.ase_mips3d == -1) |
| 10395 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (mips_arch)) ? 1 : 0; |
| 10396 | if (mips_opts.ase_mdmx == -1) |
| 10397 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (mips_arch)) ? 1 : 0; |
| 10398 | |
| 10399 | file_mips_isa = mips_opts.isa; |
| 10400 | file_ase_mips16 = mips_opts.mips16; |
| 10401 | file_ase_mips3d = mips_opts.ase_mips3d; |
| 10402 | file_ase_mdmx = mips_opts.ase_mdmx; |
| 10403 | mips_opts.gp32 = file_mips_gp32; |
| 10404 | mips_opts.fp32 = file_mips_fp32; |
| 10405 | |
| 10406 | if (HAVE_NEWABI) |
| 10407 | mips_big_got = 1; |
| 10408 | |
| 10409 | if (mips_flag_mdebug < 0) |
| 10410 | { |
| 10411 | #ifdef OBJ_MAYBE_ECOFF |
| 10412 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) |
| 10413 | mips_flag_mdebug = 1; |
| 10414 | else |
| 10415 | #endif /* OBJ_MAYBE_ECOFF */ |
| 10416 | mips_flag_mdebug = 0; |
| 10417 | } |
| 10418 | } |
| 10419 | \f |
| 10420 | void |
| 10421 | mips_init_after_args () |
| 10422 | { |
| 10423 | /* initialize opcodes */ |
| 10424 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; |
| 10425 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
| 10426 | } |
| 10427 | |
| 10428 | long |
| 10429 | md_pcrel_from (fixP) |
| 10430 | fixS *fixP; |
| 10431 | { |
| 10432 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour |
| 10433 | && fixP->fx_addsy != (symbolS *) NULL |
| 10434 | && ! S_IS_DEFINED (fixP->fx_addsy)) |
| 10435 | { |
| 10436 | /* This makes a branch to an undefined symbol be a branch to the |
| 10437 | current location. */ |
| 10438 | if (mips_pic == EMBEDDED_PIC) |
| 10439 | return 4; |
| 10440 | else |
| 10441 | return 1; |
| 10442 | } |
| 10443 | |
| 10444 | /* Return the address of the delay slot. */ |
| 10445 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; |
| 10446 | } |
| 10447 | |
| 10448 | /* This is called before the symbol table is processed. In order to |
| 10449 | work with gcc when using mips-tfile, we must keep all local labels. |
| 10450 | However, in other cases, we want to discard them. If we were |
| 10451 | called with -g, but we didn't see any debugging information, it may |
| 10452 | mean that gcc is smuggling debugging information through to |
| 10453 | mips-tfile, in which case we must generate all local labels. */ |
| 10454 | |
| 10455 | void |
| 10456 | mips_frob_file_before_adjust () |
| 10457 | { |
| 10458 | #ifndef NO_ECOFF_DEBUGGING |
| 10459 | if (ECOFF_DEBUGGING |
| 10460 | && mips_debug != 0 |
| 10461 | && ! ecoff_debugging_seen) |
| 10462 | flag_keep_locals = 1; |
| 10463 | #endif |
| 10464 | } |
| 10465 | |
| 10466 | /* Sort any unmatched HI16_S relocs so that they immediately precede |
| 10467 | the corresponding LO reloc. This is called before md_apply_fix3 and |
| 10468 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by |
| 10469 | explicit use of the %hi modifier. */ |
| 10470 | |
| 10471 | void |
| 10472 | mips_frob_file () |
| 10473 | { |
| 10474 | struct mips_hi_fixup *l; |
| 10475 | |
| 10476 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) |
| 10477 | { |
| 10478 | segment_info_type *seginfo; |
| 10479 | int pass; |
| 10480 | |
| 10481 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); |
| 10482 | |
| 10483 | /* Check quickly whether the next fixup happens to be a matching |
| 10484 | %lo. */ |
| 10485 | if (l->fixp->fx_next != NULL |
| 10486 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 |
| 10487 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy |
| 10488 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) |
| 10489 | continue; |
| 10490 | |
| 10491 | /* Look through the fixups for this segment for a matching %lo. |
| 10492 | When we find one, move the %hi just in front of it. We do |
| 10493 | this in two passes. In the first pass, we try to find a |
| 10494 | unique %lo. In the second pass, we permit multiple %hi |
| 10495 | relocs for a single %lo (this is a GNU extension). */ |
| 10496 | seginfo = seg_info (l->seg); |
| 10497 | for (pass = 0; pass < 2; pass++) |
| 10498 | { |
| 10499 | fixS *f, *prev; |
| 10500 | |
| 10501 | prev = NULL; |
| 10502 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) |
| 10503 | { |
| 10504 | /* Check whether this is a %lo fixup which matches l->fixp. */ |
| 10505 | if (f->fx_r_type == BFD_RELOC_LO16 |
| 10506 | && f->fx_addsy == l->fixp->fx_addsy |
| 10507 | && f->fx_offset == l->fixp->fx_offset |
| 10508 | && (pass == 1 |
| 10509 | || prev == NULL |
| 10510 | || prev->fx_r_type != BFD_RELOC_HI16_S |
| 10511 | || prev->fx_addsy != f->fx_addsy |
| 10512 | || prev->fx_offset != f->fx_offset)) |
| 10513 | { |
| 10514 | fixS **pf; |
| 10515 | |
| 10516 | /* Move l->fixp before f. */ |
| 10517 | for (pf = &seginfo->fix_root; |
| 10518 | *pf != l->fixp; |
| 10519 | pf = &(*pf)->fx_next) |
| 10520 | assert (*pf != NULL); |
| 10521 | |
| 10522 | *pf = l->fixp->fx_next; |
| 10523 | |
| 10524 | l->fixp->fx_next = f; |
| 10525 | if (prev == NULL) |
| 10526 | seginfo->fix_root = l->fixp; |
| 10527 | else |
| 10528 | prev->fx_next = l->fixp; |
| 10529 | |
| 10530 | break; |
| 10531 | } |
| 10532 | |
| 10533 | prev = f; |
| 10534 | } |
| 10535 | |
| 10536 | if (f != NULL) |
| 10537 | break; |
| 10538 | |
| 10539 | #if 0 /* GCC code motion plus incomplete dead code elimination |
| 10540 | can leave a %hi without a %lo. */ |
| 10541 | if (pass == 1) |
| 10542 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, |
| 10543 | _("Unmatched %%hi reloc")); |
| 10544 | #endif |
| 10545 | } |
| 10546 | } |
| 10547 | } |
| 10548 | |
| 10549 | /* When generating embedded PIC code we need to use a special |
| 10550 | relocation to represent the difference of two symbols in the .text |
| 10551 | section (switch tables use a difference of this sort). See |
| 10552 | include/coff/mips.h for details. This macro checks whether this |
| 10553 | fixup requires the special reloc. */ |
| 10554 | #define SWITCH_TABLE(fixp) \ |
| 10555 | ((fixp)->fx_r_type == BFD_RELOC_32 \ |
| 10556 | && OUTPUT_FLAVOR != bfd_target_elf_flavour \ |
| 10557 | && (fixp)->fx_addsy != NULL \ |
| 10558 | && (fixp)->fx_subsy != NULL \ |
| 10559 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ |
| 10560 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) |
| 10561 | |
| 10562 | /* When generating embedded PIC code we must keep all PC relative |
| 10563 | relocations, in case the linker has to relax a call. We also need |
| 10564 | to keep relocations for switch table entries. |
| 10565 | |
| 10566 | We may have combined relocations without symbols in the N32/N64 ABI. |
| 10567 | We have to prevent gas from dropping them. */ |
| 10568 | |
| 10569 | int |
| 10570 | mips_force_relocation (fixp) |
| 10571 | fixS *fixp; |
| 10572 | { |
| 10573 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
| 10574 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
| 10575 | return 1; |
| 10576 | |
| 10577 | if (HAVE_NEWABI |
| 10578 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr |
| 10579 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB |
| 10580 | || fixp->fx_r_type == BFD_RELOC_HI16_S |
| 10581 | || fixp->fx_r_type == BFD_RELOC_LO16)) |
| 10582 | return 1; |
| 10583 | |
| 10584 | return (mips_pic == EMBEDDED_PIC |
| 10585 | && (fixp->fx_pcrel |
| 10586 | || SWITCH_TABLE (fixp) |
| 10587 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S |
| 10588 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); |
| 10589 | } |
| 10590 | |
| 10591 | #ifdef OBJ_ELF |
| 10592 | static int |
| 10593 | mips_need_elf_addend_fixup (fixP) |
| 10594 | fixS *fixP; |
| 10595 | { |
| 10596 | if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16) |
| 10597 | return 1; |
| 10598 | if (mips_pic == EMBEDDED_PIC |
| 10599 | && S_IS_WEAK (fixP->fx_addsy)) |
| 10600 | return 1; |
| 10601 | if (mips_pic != EMBEDDED_PIC |
| 10602 | && (S_IS_WEAK (fixP->fx_addsy) |
| 10603 | || S_IS_EXTERNAL (fixP->fx_addsy)) |
| 10604 | && !S_IS_COMMON (fixP->fx_addsy)) |
| 10605 | return 1; |
| 10606 | if (symbol_used_in_reloc_p (fixP->fx_addsy) |
| 10607 | && (((bfd_get_section_flags (stdoutput, |
| 10608 | S_GET_SEGMENT (fixP->fx_addsy)) |
| 10609 | & SEC_LINK_ONCE) != 0) |
| 10610 | || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)), |
| 10611 | ".gnu.linkonce", |
| 10612 | sizeof (".gnu.linkonce") - 1))) |
| 10613 | return 1; |
| 10614 | return 0; |
| 10615 | } |
| 10616 | #endif |
| 10617 | |
| 10618 | /* Apply a fixup to the object file. */ |
| 10619 | |
| 10620 | void |
| 10621 | md_apply_fix3 (fixP, valP, seg) |
| 10622 | fixS *fixP; |
| 10623 | valueT *valP; |
| 10624 | segT seg ATTRIBUTE_UNUSED; |
| 10625 | { |
| 10626 | bfd_byte *buf; |
| 10627 | long insn; |
| 10628 | valueT value; |
| 10629 | |
| 10630 | assert (fixP->fx_size == 4 |
| 10631 | || fixP->fx_r_type == BFD_RELOC_16 |
| 10632 | || fixP->fx_r_type == BFD_RELOC_32 |
| 10633 | || fixP->fx_r_type == BFD_RELOC_MIPS_JMP |
| 10634 | || fixP->fx_r_type == BFD_RELOC_HI16_S |
| 10635 | || fixP->fx_r_type == BFD_RELOC_LO16 |
| 10636 | || fixP->fx_r_type == BFD_RELOC_GPREL16 |
| 10637 | || fixP->fx_r_type == BFD_RELOC_MIPS_LITERAL |
| 10638 | || fixP->fx_r_type == BFD_RELOC_GPREL32 |
| 10639 | || fixP->fx_r_type == BFD_RELOC_64 |
| 10640 | || fixP->fx_r_type == BFD_RELOC_CTOR |
| 10641 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB |
| 10642 | || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHEST |
| 10643 | || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHER |
| 10644 | || fixP->fx_r_type == BFD_RELOC_MIPS_SCN_DISP |
| 10645 | || fixP->fx_r_type == BFD_RELOC_MIPS_REL16 |
| 10646 | || fixP->fx_r_type == BFD_RELOC_MIPS_RELGOT |
| 10647 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
| 10648 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY |
| 10649 | || fixP->fx_r_type == BFD_RELOC_MIPS_JALR); |
| 10650 | |
| 10651 | value = *valP; |
| 10652 | |
| 10653 | /* If we aren't adjusting this fixup to be against the section |
| 10654 | symbol, we need to adjust the value. */ |
| 10655 | #ifdef OBJ_ELF |
| 10656 | if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour) |
| 10657 | { |
| 10658 | if (mips_need_elf_addend_fixup (fixP)) |
| 10659 | { |
| 10660 | reloc_howto_type *howto; |
| 10661 | valueT symval = S_GET_VALUE (fixP->fx_addsy); |
| 10662 | |
| 10663 | value -= symval; |
| 10664 | |
| 10665 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); |
| 10666 | if (value != 0 && howto->partial_inplace && ! fixP->fx_pcrel) |
| 10667 | { |
| 10668 | /* In this case, the bfd_install_relocation routine will |
| 10669 | incorrectly add the symbol value back in. We just want |
| 10670 | the addend to appear in the object file. */ |
| 10671 | value -= symval; |
| 10672 | |
| 10673 | /* Make sure the addend is still non-zero. If it became zero |
| 10674 | after the last operation, set it to a spurious value and |
| 10675 | subtract the same value from the object file's contents. */ |
| 10676 | if (value == 0) |
| 10677 | { |
| 10678 | value = 8; |
| 10679 | |
| 10680 | /* The in-place addends for LO16 relocations are signed; |
| 10681 | leave the matching HI16 in-place addends as zero. */ |
| 10682 | if (fixP->fx_r_type != BFD_RELOC_HI16_S) |
| 10683 | { |
| 10684 | bfd_vma contents, mask, field; |
| 10685 | |
| 10686 | contents = bfd_get_bits (fixP->fx_frag->fr_literal |
| 10687 | + fixP->fx_where, |
| 10688 | fixP->fx_size * 8, |
| 10689 | target_big_endian); |
| 10690 | |
| 10691 | /* MASK has bits set where the relocation should go. |
| 10692 | FIELD is -value, shifted into the appropriate place |
| 10693 | for this relocation. */ |
| 10694 | mask = 1 << (howto->bitsize - 1); |
| 10695 | mask = (((mask - 1) << 1) | 1) << howto->bitpos; |
| 10696 | field = (-value >> howto->rightshift) << howto->bitpos; |
| 10697 | |
| 10698 | bfd_put_bits ((field & mask) | (contents & ~mask), |
| 10699 | fixP->fx_frag->fr_literal + fixP->fx_where, |
| 10700 | fixP->fx_size * 8, |
| 10701 | target_big_endian); |
| 10702 | } |
| 10703 | } |
| 10704 | } |
| 10705 | } |
| 10706 | |
| 10707 | /* This code was generated using trial and error and so is |
| 10708 | fragile and not trustworthy. If you change it, you should |
| 10709 | rerun the elf-rel, elf-rel2, and empic testcases and ensure |
| 10710 | they still pass. */ |
| 10711 | if (fixP->fx_pcrel || fixP->fx_subsy != NULL) |
| 10712 | { |
| 10713 | value += fixP->fx_frag->fr_address + fixP->fx_where; |
| 10714 | |
| 10715 | /* BFD's REL handling, for MIPS, is _very_ weird. |
| 10716 | This gives the right results, but it can't possibly |
| 10717 | be the way things are supposed to work. */ |
| 10718 | if ((fixP->fx_r_type != BFD_RELOC_16_PCREL |
| 10719 | && fixP->fx_r_type != BFD_RELOC_16_PCREL_S2) |
| 10720 | || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section) |
| 10721 | value += fixP->fx_frag->fr_address + fixP->fx_where; |
| 10722 | } |
| 10723 | } |
| 10724 | #endif |
| 10725 | |
| 10726 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc. */ |
| 10727 | |
| 10728 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
| 10729 | fixP->fx_done = 1; |
| 10730 | |
| 10731 | switch (fixP->fx_r_type) |
| 10732 | { |
| 10733 | case BFD_RELOC_MIPS_JMP: |
| 10734 | case BFD_RELOC_MIPS_SHIFT5: |
| 10735 | case BFD_RELOC_MIPS_SHIFT6: |
| 10736 | case BFD_RELOC_MIPS_GOT_DISP: |
| 10737 | case BFD_RELOC_MIPS_GOT_PAGE: |
| 10738 | case BFD_RELOC_MIPS_GOT_OFST: |
| 10739 | case BFD_RELOC_MIPS_SUB: |
| 10740 | case BFD_RELOC_MIPS_INSERT_A: |
| 10741 | case BFD_RELOC_MIPS_INSERT_B: |
| 10742 | case BFD_RELOC_MIPS_DELETE: |
| 10743 | case BFD_RELOC_MIPS_HIGHEST: |
| 10744 | case BFD_RELOC_MIPS_HIGHER: |
| 10745 | case BFD_RELOC_MIPS_SCN_DISP: |
| 10746 | case BFD_RELOC_MIPS_REL16: |
| 10747 | case BFD_RELOC_MIPS_RELGOT: |
| 10748 | case BFD_RELOC_MIPS_JALR: |
| 10749 | case BFD_RELOC_HI16: |
| 10750 | case BFD_RELOC_HI16_S: |
| 10751 | case BFD_RELOC_GPREL16: |
| 10752 | case BFD_RELOC_MIPS_LITERAL: |
| 10753 | case BFD_RELOC_MIPS_CALL16: |
| 10754 | case BFD_RELOC_MIPS_GOT16: |
| 10755 | case BFD_RELOC_GPREL32: |
| 10756 | case BFD_RELOC_MIPS_GOT_HI16: |
| 10757 | case BFD_RELOC_MIPS_GOT_LO16: |
| 10758 | case BFD_RELOC_MIPS_CALL_HI16: |
| 10759 | case BFD_RELOC_MIPS_CALL_LO16: |
| 10760 | case BFD_RELOC_MIPS16_GPREL: |
| 10761 | if (fixP->fx_pcrel) |
| 10762 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 10763 | _("Invalid PC relative reloc")); |
| 10764 | /* Nothing needed to do. The value comes from the reloc entry */ |
| 10765 | break; |
| 10766 | |
| 10767 | case BFD_RELOC_MIPS16_JMP: |
| 10768 | /* We currently always generate a reloc against a symbol, which |
| 10769 | means that we don't want an addend even if the symbol is |
| 10770 | defined. */ |
| 10771 | fixP->fx_addnumber = 0; |
| 10772 | break; |
| 10773 | |
| 10774 | case BFD_RELOC_PCREL_HI16_S: |
| 10775 | /* The addend for this is tricky if it is internal, so we just |
| 10776 | do everything here rather than in bfd_install_relocation. */ |
| 10777 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
| 10778 | && !fixP->fx_done |
| 10779 | && value != 0) |
| 10780 | break; |
| 10781 | if (fixP->fx_addsy |
| 10782 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) |
| 10783 | { |
| 10784 | /* For an external symbol adjust by the address to make it |
| 10785 | pcrel_offset. We use the address of the RELLO reloc |
| 10786 | which follows this one. */ |
| 10787 | value += (fixP->fx_next->fx_frag->fr_address |
| 10788 | + fixP->fx_next->fx_where); |
| 10789 | } |
| 10790 | value = ((value + 0x8000) >> 16) & 0xffff; |
| 10791 | buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where; |
| 10792 | if (target_big_endian) |
| 10793 | buf += 2; |
| 10794 | md_number_to_chars ((char *) buf, value, 2); |
| 10795 | break; |
| 10796 | |
| 10797 | case BFD_RELOC_PCREL_LO16: |
| 10798 | /* The addend for this is tricky if it is internal, so we just |
| 10799 | do everything here rather than in bfd_install_relocation. */ |
| 10800 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
| 10801 | && !fixP->fx_done |
| 10802 | && value != 0) |
| 10803 | break; |
| 10804 | if (fixP->fx_addsy |
| 10805 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) |
| 10806 | value += fixP->fx_frag->fr_address + fixP->fx_where; |
| 10807 | buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where; |
| 10808 | if (target_big_endian) |
| 10809 | buf += 2; |
| 10810 | md_number_to_chars ((char *) buf, value, 2); |
| 10811 | break; |
| 10812 | |
| 10813 | case BFD_RELOC_64: |
| 10814 | /* This is handled like BFD_RELOC_32, but we output a sign |
| 10815 | extended value if we are only 32 bits. */ |
| 10816 | if (fixP->fx_done |
| 10817 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) |
| 10818 | { |
| 10819 | if (8 <= sizeof (valueT)) |
| 10820 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
| 10821 | value, 8); |
| 10822 | else |
| 10823 | { |
| 10824 | long w1, w2; |
| 10825 | long hiv; |
| 10826 | |
| 10827 | w1 = w2 = fixP->fx_where; |
| 10828 | if (target_big_endian) |
| 10829 | w1 += 4; |
| 10830 | else |
| 10831 | w2 += 4; |
| 10832 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); |
| 10833 | if ((value & 0x80000000) != 0) |
| 10834 | hiv = 0xffffffff; |
| 10835 | else |
| 10836 | hiv = 0; |
| 10837 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); |
| 10838 | } |
| 10839 | } |
| 10840 | break; |
| 10841 | |
| 10842 | case BFD_RELOC_RVA: |
| 10843 | case BFD_RELOC_32: |
| 10844 | /* If we are deleting this reloc entry, we must fill in the |
| 10845 | value now. This can happen if we have a .word which is not |
| 10846 | resolved when it appears but is later defined. We also need |
| 10847 | to fill in the value if this is an embedded PIC switch table |
| 10848 | entry. */ |
| 10849 | if (fixP->fx_done |
| 10850 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) |
| 10851 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
| 10852 | value, 4); |
| 10853 | break; |
| 10854 | |
| 10855 | case BFD_RELOC_16: |
| 10856 | /* If we are deleting this reloc entry, we must fill in the |
| 10857 | value now. */ |
| 10858 | assert (fixP->fx_size == 2); |
| 10859 | if (fixP->fx_done) |
| 10860 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
| 10861 | value, 2); |
| 10862 | break; |
| 10863 | |
| 10864 | case BFD_RELOC_LO16: |
| 10865 | /* When handling an embedded PIC switch statement, we can wind |
| 10866 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ |
| 10867 | if (fixP->fx_done) |
| 10868 | { |
| 10869 | if (value + 0x8000 > 0xffff) |
| 10870 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 10871 | _("relocation overflow")); |
| 10872 | buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where; |
| 10873 | if (target_big_endian) |
| 10874 | buf += 2; |
| 10875 | md_number_to_chars ((char *) buf, value, 2); |
| 10876 | } |
| 10877 | break; |
| 10878 | |
| 10879 | case BFD_RELOC_16_PCREL_S2: |
| 10880 | if ((value & 0x3) != 0) |
| 10881 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 10882 | _("Branch to odd address (%lx)"), (long) value); |
| 10883 | |
| 10884 | /* Fall through. */ |
| 10885 | |
| 10886 | case BFD_RELOC_16_PCREL: |
| 10887 | /* |
| 10888 | * We need to save the bits in the instruction since fixup_segment() |
| 10889 | * might be deleting the relocation entry (i.e., a branch within |
| 10890 | * the current segment). |
| 10891 | */ |
| 10892 | if (!fixP->fx_done && value != 0) |
| 10893 | break; |
| 10894 | /* If 'value' is zero, the remaining reloc code won't actually |
| 10895 | do the store, so it must be done here. This is probably |
| 10896 | a bug somewhere. */ |
| 10897 | if (!fixP->fx_done |
| 10898 | && (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2 |
| 10899 | || fixP->fx_addsy == NULL /* ??? */ |
| 10900 | || ! S_IS_DEFINED (fixP->fx_addsy))) |
| 10901 | value -= fixP->fx_frag->fr_address + fixP->fx_where; |
| 10902 | |
| 10903 | value = (offsetT) value >> 2; |
| 10904 | |
| 10905 | /* update old instruction data */ |
| 10906 | buf = (bfd_byte *) (fixP->fx_where + fixP->fx_frag->fr_literal); |
| 10907 | if (target_big_endian) |
| 10908 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; |
| 10909 | else |
| 10910 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; |
| 10911 | |
| 10912 | if (value + 0x8000 <= 0xffff) |
| 10913 | insn |= value & 0xffff; |
| 10914 | else |
| 10915 | { |
| 10916 | /* The branch offset is too large. If this is an |
| 10917 | unconditional branch, and we are not generating PIC code, |
| 10918 | we can convert it to an absolute jump instruction. */ |
| 10919 | if (mips_pic == NO_PIC |
| 10920 | && fixP->fx_done |
| 10921 | && fixP->fx_frag->fr_address >= text_section->vma |
| 10922 | && (fixP->fx_frag->fr_address |
| 10923 | < text_section->vma + text_section->_raw_size) |
| 10924 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
| 10925 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ |
| 10926 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ |
| 10927 | { |
| 10928 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
| 10929 | insn = 0x0c000000; /* jal */ |
| 10930 | else |
| 10931 | insn = 0x08000000; /* j */ |
| 10932 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; |
| 10933 | fixP->fx_done = 0; |
| 10934 | fixP->fx_addsy = section_symbol (text_section); |
| 10935 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); |
| 10936 | } |
| 10937 | else |
| 10938 | { |
| 10939 | /* FIXME. It would be possible in principle to handle |
| 10940 | conditional branches which overflow. They could be |
| 10941 | transformed into a branch around a jump. This would |
| 10942 | require setting up variant frags for each different |
| 10943 | branch type. The native MIPS assembler attempts to |
| 10944 | handle these cases, but it appears to do it |
| 10945 | incorrectly. */ |
| 10946 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 10947 | _("Branch out of range")); |
| 10948 | } |
| 10949 | } |
| 10950 | |
| 10951 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
| 10952 | break; |
| 10953 | |
| 10954 | case BFD_RELOC_VTABLE_INHERIT: |
| 10955 | fixP->fx_done = 0; |
| 10956 | if (fixP->fx_addsy |
| 10957 | && !S_IS_DEFINED (fixP->fx_addsy) |
| 10958 | && !S_IS_WEAK (fixP->fx_addsy)) |
| 10959 | S_SET_WEAK (fixP->fx_addsy); |
| 10960 | break; |
| 10961 | |
| 10962 | case BFD_RELOC_VTABLE_ENTRY: |
| 10963 | fixP->fx_done = 0; |
| 10964 | break; |
| 10965 | |
| 10966 | default: |
| 10967 | internalError (); |
| 10968 | } |
| 10969 | } |
| 10970 | |
| 10971 | #if 0 |
| 10972 | void |
| 10973 | printInsn (oc) |
| 10974 | unsigned long oc; |
| 10975 | { |
| 10976 | const struct mips_opcode *p; |
| 10977 | int treg, sreg, dreg, shamt; |
| 10978 | short imm; |
| 10979 | const char *args; |
| 10980 | int i; |
| 10981 | |
| 10982 | for (i = 0; i < NUMOPCODES; ++i) |
| 10983 | { |
| 10984 | p = &mips_opcodes[i]; |
| 10985 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) |
| 10986 | { |
| 10987 | printf ("%08lx %s\t", oc, p->name); |
| 10988 | treg = (oc >> 16) & 0x1f; |
| 10989 | sreg = (oc >> 21) & 0x1f; |
| 10990 | dreg = (oc >> 11) & 0x1f; |
| 10991 | shamt = (oc >> 6) & 0x1f; |
| 10992 | imm = oc; |
| 10993 | for (args = p->args;; ++args) |
| 10994 | { |
| 10995 | switch (*args) |
| 10996 | { |
| 10997 | case '\0': |
| 10998 | printf ("\n"); |
| 10999 | break; |
| 11000 | |
| 11001 | case ',': |
| 11002 | case '(': |
| 11003 | case ')': |
| 11004 | printf ("%c", *args); |
| 11005 | continue; |
| 11006 | |
| 11007 | case 'r': |
| 11008 | assert (treg == sreg); |
| 11009 | printf ("$%d,$%d", treg, sreg); |
| 11010 | continue; |
| 11011 | |
| 11012 | case 'd': |
| 11013 | case 'G': |
| 11014 | printf ("$%d", dreg); |
| 11015 | continue; |
| 11016 | |
| 11017 | case 't': |
| 11018 | case 'E': |
| 11019 | printf ("$%d", treg); |
| 11020 | continue; |
| 11021 | |
| 11022 | case 'k': |
| 11023 | printf ("0x%x", treg); |
| 11024 | continue; |
| 11025 | |
| 11026 | case 'b': |
| 11027 | case 's': |
| 11028 | printf ("$%d", sreg); |
| 11029 | continue; |
| 11030 | |
| 11031 | case 'a': |
| 11032 | printf ("0x%08lx", oc & 0x1ffffff); |
| 11033 | continue; |
| 11034 | |
| 11035 | case 'i': |
| 11036 | case 'j': |
| 11037 | case 'o': |
| 11038 | case 'u': |
| 11039 | printf ("%d", imm); |
| 11040 | continue; |
| 11041 | |
| 11042 | case '<': |
| 11043 | case '>': |
| 11044 | printf ("$%d", shamt); |
| 11045 | continue; |
| 11046 | |
| 11047 | default: |
| 11048 | internalError (); |
| 11049 | } |
| 11050 | break; |
| 11051 | } |
| 11052 | return; |
| 11053 | } |
| 11054 | } |
| 11055 | printf (_("%08lx UNDEFINED\n"), oc); |
| 11056 | } |
| 11057 | #endif |
| 11058 | |
| 11059 | static symbolS * |
| 11060 | get_symbol () |
| 11061 | { |
| 11062 | int c; |
| 11063 | char *name; |
| 11064 | symbolS *p; |
| 11065 | |
| 11066 | name = input_line_pointer; |
| 11067 | c = get_symbol_end (); |
| 11068 | p = (symbolS *) symbol_find_or_make (name); |
| 11069 | *input_line_pointer = c; |
| 11070 | return p; |
| 11071 | } |
| 11072 | |
| 11073 | /* Align the current frag to a given power of two. The MIPS assembler |
| 11074 | also automatically adjusts any preceding label. */ |
| 11075 | |
| 11076 | static void |
| 11077 | mips_align (to, fill, label) |
| 11078 | int to; |
| 11079 | int fill; |
| 11080 | symbolS *label; |
| 11081 | { |
| 11082 | mips_emit_delays (false); |
| 11083 | frag_align (to, fill, 0); |
| 11084 | record_alignment (now_seg, to); |
| 11085 | if (label != NULL) |
| 11086 | { |
| 11087 | assert (S_GET_SEGMENT (label) == now_seg); |
| 11088 | symbol_set_frag (label, frag_now); |
| 11089 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
| 11090 | } |
| 11091 | } |
| 11092 | |
| 11093 | /* Align to a given power of two. .align 0 turns off the automatic |
| 11094 | alignment used by the data creating pseudo-ops. */ |
| 11095 | |
| 11096 | static void |
| 11097 | s_align (x) |
| 11098 | int x ATTRIBUTE_UNUSED; |
| 11099 | { |
| 11100 | register int temp; |
| 11101 | register long temp_fill; |
| 11102 | long max_alignment = 15; |
| 11103 | |
| 11104 | /* |
| 11105 | |
| 11106 | o Note that the assembler pulls down any immediately preceeding label |
| 11107 | to the aligned address. |
| 11108 | o It's not documented but auto alignment is reinstated by |
| 11109 | a .align pseudo instruction. |
| 11110 | o Note also that after auto alignment is turned off the mips assembler |
| 11111 | issues an error on attempt to assemble an improperly aligned data item. |
| 11112 | We don't. |
| 11113 | |
| 11114 | */ |
| 11115 | |
| 11116 | temp = get_absolute_expression (); |
| 11117 | if (temp > max_alignment) |
| 11118 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); |
| 11119 | else if (temp < 0) |
| 11120 | { |
| 11121 | as_warn (_("Alignment negative: 0 assumed.")); |
| 11122 | temp = 0; |
| 11123 | } |
| 11124 | if (*input_line_pointer == ',') |
| 11125 | { |
| 11126 | ++input_line_pointer; |
| 11127 | temp_fill = get_absolute_expression (); |
| 11128 | } |
| 11129 | else |
| 11130 | temp_fill = 0; |
| 11131 | if (temp) |
| 11132 | { |
| 11133 | auto_align = 1; |
| 11134 | mips_align (temp, (int) temp_fill, |
| 11135 | insn_labels != NULL ? insn_labels->label : NULL); |
| 11136 | } |
| 11137 | else |
| 11138 | { |
| 11139 | auto_align = 0; |
| 11140 | } |
| 11141 | |
| 11142 | demand_empty_rest_of_line (); |
| 11143 | } |
| 11144 | |
| 11145 | void |
| 11146 | mips_flush_pending_output () |
| 11147 | { |
| 11148 | mips_emit_delays (false); |
| 11149 | mips_clear_insn_labels (); |
| 11150 | } |
| 11151 | |
| 11152 | static void |
| 11153 | s_change_sec (sec) |
| 11154 | int sec; |
| 11155 | { |
| 11156 | segT seg; |
| 11157 | |
| 11158 | /* When generating embedded PIC code, we only use the .text, .lit8, |
| 11159 | .sdata and .sbss sections. We change the .data and .rdata |
| 11160 | pseudo-ops to use .sdata. */ |
| 11161 | if (mips_pic == EMBEDDED_PIC |
| 11162 | && (sec == 'd' || sec == 'r')) |
| 11163 | sec = 's'; |
| 11164 | |
| 11165 | #ifdef OBJ_ELF |
| 11166 | /* The ELF backend needs to know that we are changing sections, so |
| 11167 | that .previous works correctly. We could do something like check |
| 11168 | for an obj_section_change_hook macro, but that might be confusing |
| 11169 | as it would not be appropriate to use it in the section changing |
| 11170 | functions in read.c, since obj-elf.c intercepts those. FIXME: |
| 11171 | This should be cleaner, somehow. */ |
| 11172 | obj_elf_section_change_hook (); |
| 11173 | #endif |
| 11174 | |
| 11175 | mips_emit_delays (false); |
| 11176 | switch (sec) |
| 11177 | { |
| 11178 | case 't': |
| 11179 | s_text (0); |
| 11180 | break; |
| 11181 | case 'd': |
| 11182 | s_data (0); |
| 11183 | break; |
| 11184 | case 'b': |
| 11185 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
| 11186 | demand_empty_rest_of_line (); |
| 11187 | break; |
| 11188 | |
| 11189 | case 'r': |
| 11190 | if (USE_GLOBAL_POINTER_OPT) |
| 11191 | { |
| 11192 | seg = subseg_new (RDATA_SECTION_NAME, |
| 11193 | (subsegT) get_absolute_expression ()); |
| 11194 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
| 11195 | { |
| 11196 | bfd_set_section_flags (stdoutput, seg, |
| 11197 | (SEC_ALLOC |
| 11198 | | SEC_LOAD |
| 11199 | | SEC_READONLY |
| 11200 | | SEC_RELOC |
| 11201 | | SEC_DATA)); |
| 11202 | if (strcmp (TARGET_OS, "elf") != 0) |
| 11203 | record_alignment (seg, 4); |
| 11204 | } |
| 11205 | demand_empty_rest_of_line (); |
| 11206 | } |
| 11207 | else |
| 11208 | { |
| 11209 | as_bad (_("No read only data section in this object file format")); |
| 11210 | demand_empty_rest_of_line (); |
| 11211 | return; |
| 11212 | } |
| 11213 | break; |
| 11214 | |
| 11215 | case 's': |
| 11216 | if (USE_GLOBAL_POINTER_OPT) |
| 11217 | { |
| 11218 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
| 11219 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
| 11220 | { |
| 11221 | bfd_set_section_flags (stdoutput, seg, |
| 11222 | SEC_ALLOC | SEC_LOAD | SEC_RELOC |
| 11223 | | SEC_DATA); |
| 11224 | if (strcmp (TARGET_OS, "elf") != 0) |
| 11225 | record_alignment (seg, 4); |
| 11226 | } |
| 11227 | demand_empty_rest_of_line (); |
| 11228 | break; |
| 11229 | } |
| 11230 | else |
| 11231 | { |
| 11232 | as_bad (_("Global pointers not supported; recompile -G 0")); |
| 11233 | demand_empty_rest_of_line (); |
| 11234 | return; |
| 11235 | } |
| 11236 | } |
| 11237 | |
| 11238 | auto_align = 1; |
| 11239 | } |
| 11240 | |
| 11241 | void |
| 11242 | mips_enable_auto_align () |
| 11243 | { |
| 11244 | auto_align = 1; |
| 11245 | } |
| 11246 | |
| 11247 | static void |
| 11248 | s_cons (log_size) |
| 11249 | int log_size; |
| 11250 | { |
| 11251 | symbolS *label; |
| 11252 | |
| 11253 | label = insn_labels != NULL ? insn_labels->label : NULL; |
| 11254 | mips_emit_delays (false); |
| 11255 | if (log_size > 0 && auto_align) |
| 11256 | mips_align (log_size, 0, label); |
| 11257 | mips_clear_insn_labels (); |
| 11258 | cons (1 << log_size); |
| 11259 | } |
| 11260 | |
| 11261 | static void |
| 11262 | s_float_cons (type) |
| 11263 | int type; |
| 11264 | { |
| 11265 | symbolS *label; |
| 11266 | |
| 11267 | label = insn_labels != NULL ? insn_labels->label : NULL; |
| 11268 | |
| 11269 | mips_emit_delays (false); |
| 11270 | |
| 11271 | if (auto_align) |
| 11272 | { |
| 11273 | if (type == 'd') |
| 11274 | mips_align (3, 0, label); |
| 11275 | else |
| 11276 | mips_align (2, 0, label); |
| 11277 | } |
| 11278 | |
| 11279 | mips_clear_insn_labels (); |
| 11280 | |
| 11281 | float_cons (type); |
| 11282 | } |
| 11283 | |
| 11284 | /* Handle .globl. We need to override it because on Irix 5 you are |
| 11285 | permitted to say |
| 11286 | .globl foo .text |
| 11287 | where foo is an undefined symbol, to mean that foo should be |
| 11288 | considered to be the address of a function. */ |
| 11289 | |
| 11290 | static void |
| 11291 | s_mips_globl (x) |
| 11292 | int x ATTRIBUTE_UNUSED; |
| 11293 | { |
| 11294 | char *name; |
| 11295 | int c; |
| 11296 | symbolS *symbolP; |
| 11297 | flagword flag; |
| 11298 | |
| 11299 | name = input_line_pointer; |
| 11300 | c = get_symbol_end (); |
| 11301 | symbolP = symbol_find_or_make (name); |
| 11302 | *input_line_pointer = c; |
| 11303 | SKIP_WHITESPACE (); |
| 11304 | |
| 11305 | /* On Irix 5, every global symbol that is not explicitly labelled as |
| 11306 | being a function is apparently labelled as being an object. */ |
| 11307 | flag = BSF_OBJECT; |
| 11308 | |
| 11309 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
| 11310 | { |
| 11311 | char *secname; |
| 11312 | asection *sec; |
| 11313 | |
| 11314 | secname = input_line_pointer; |
| 11315 | c = get_symbol_end (); |
| 11316 | sec = bfd_get_section_by_name (stdoutput, secname); |
| 11317 | if (sec == NULL) |
| 11318 | as_bad (_("%s: no such section"), secname); |
| 11319 | *input_line_pointer = c; |
| 11320 | |
| 11321 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) |
| 11322 | flag = BSF_FUNCTION; |
| 11323 | } |
| 11324 | |
| 11325 | symbol_get_bfdsym (symbolP)->flags |= flag; |
| 11326 | |
| 11327 | S_SET_EXTERNAL (symbolP); |
| 11328 | demand_empty_rest_of_line (); |
| 11329 | } |
| 11330 | |
| 11331 | static void |
| 11332 | s_option (x) |
| 11333 | int x ATTRIBUTE_UNUSED; |
| 11334 | { |
| 11335 | char *opt; |
| 11336 | char c; |
| 11337 | |
| 11338 | opt = input_line_pointer; |
| 11339 | c = get_symbol_end (); |
| 11340 | |
| 11341 | if (*opt == 'O') |
| 11342 | { |
| 11343 | /* FIXME: What does this mean? */ |
| 11344 | } |
| 11345 | else if (strncmp (opt, "pic", 3) == 0) |
| 11346 | { |
| 11347 | int i; |
| 11348 | |
| 11349 | i = atoi (opt + 3); |
| 11350 | if (i == 0) |
| 11351 | mips_pic = NO_PIC; |
| 11352 | else if (i == 2) |
| 11353 | mips_pic = SVR4_PIC; |
| 11354 | else |
| 11355 | as_bad (_(".option pic%d not supported"), i); |
| 11356 | |
| 11357 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) |
| 11358 | { |
| 11359 | if (g_switch_seen && g_switch_value != 0) |
| 11360 | as_warn (_("-G may not be used with SVR4 PIC code")); |
| 11361 | g_switch_value = 0; |
| 11362 | bfd_set_gp_size (stdoutput, 0); |
| 11363 | } |
| 11364 | } |
| 11365 | else |
| 11366 | as_warn (_("Unrecognized option \"%s\""), opt); |
| 11367 | |
| 11368 | *input_line_pointer = c; |
| 11369 | demand_empty_rest_of_line (); |
| 11370 | } |
| 11371 | |
| 11372 | /* This structure is used to hold a stack of .set values. */ |
| 11373 | |
| 11374 | struct mips_option_stack |
| 11375 | { |
| 11376 | struct mips_option_stack *next; |
| 11377 | struct mips_set_options options; |
| 11378 | }; |
| 11379 | |
| 11380 | static struct mips_option_stack *mips_opts_stack; |
| 11381 | |
| 11382 | /* Handle the .set pseudo-op. */ |
| 11383 | |
| 11384 | static void |
| 11385 | s_mipsset (x) |
| 11386 | int x ATTRIBUTE_UNUSED; |
| 11387 | { |
| 11388 | char *name = input_line_pointer, ch; |
| 11389 | |
| 11390 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) |
| 11391 | ++input_line_pointer; |
| 11392 | ch = *input_line_pointer; |
| 11393 | *input_line_pointer = '\0'; |
| 11394 | |
| 11395 | if (strcmp (name, "reorder") == 0) |
| 11396 | { |
| 11397 | if (mips_opts.noreorder && prev_nop_frag != NULL) |
| 11398 | { |
| 11399 | /* If we still have pending nops, we can discard them. The |
| 11400 | usual nop handling will insert any that are still |
| 11401 | needed. */ |
| 11402 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
| 11403 | * (mips_opts.mips16 ? 2 : 4)); |
| 11404 | prev_nop_frag = NULL; |
| 11405 | } |
| 11406 | mips_opts.noreorder = 0; |
| 11407 | } |
| 11408 | else if (strcmp (name, "noreorder") == 0) |
| 11409 | { |
| 11410 | mips_emit_delays (true); |
| 11411 | mips_opts.noreorder = 1; |
| 11412 | mips_any_noreorder = 1; |
| 11413 | } |
| 11414 | else if (strcmp (name, "at") == 0) |
| 11415 | { |
| 11416 | mips_opts.noat = 0; |
| 11417 | } |
| 11418 | else if (strcmp (name, "noat") == 0) |
| 11419 | { |
| 11420 | mips_opts.noat = 1; |
| 11421 | } |
| 11422 | else if (strcmp (name, "macro") == 0) |
| 11423 | { |
| 11424 | mips_opts.warn_about_macros = 0; |
| 11425 | } |
| 11426 | else if (strcmp (name, "nomacro") == 0) |
| 11427 | { |
| 11428 | if (mips_opts.noreorder == 0) |
| 11429 | as_bad (_("`noreorder' must be set before `nomacro'")); |
| 11430 | mips_opts.warn_about_macros = 1; |
| 11431 | } |
| 11432 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) |
| 11433 | { |
| 11434 | mips_opts.nomove = 0; |
| 11435 | } |
| 11436 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) |
| 11437 | { |
| 11438 | mips_opts.nomove = 1; |
| 11439 | } |
| 11440 | else if (strcmp (name, "bopt") == 0) |
| 11441 | { |
| 11442 | mips_opts.nobopt = 0; |
| 11443 | } |
| 11444 | else if (strcmp (name, "nobopt") == 0) |
| 11445 | { |
| 11446 | mips_opts.nobopt = 1; |
| 11447 | } |
| 11448 | else if (strcmp (name, "mips16") == 0 |
| 11449 | || strcmp (name, "MIPS-16") == 0) |
| 11450 | mips_opts.mips16 = 1; |
| 11451 | else if (strcmp (name, "nomips16") == 0 |
| 11452 | || strcmp (name, "noMIPS-16") == 0) |
| 11453 | mips_opts.mips16 = 0; |
| 11454 | else if (strcmp (name, "mips3d") == 0) |
| 11455 | mips_opts.ase_mips3d = 1; |
| 11456 | else if (strcmp (name, "nomips3d") == 0) |
| 11457 | mips_opts.ase_mips3d = 0; |
| 11458 | else if (strcmp (name, "mdmx") == 0) |
| 11459 | mips_opts.ase_mdmx = 1; |
| 11460 | else if (strcmp (name, "nomdmx") == 0) |
| 11461 | mips_opts.ase_mdmx = 0; |
| 11462 | else if (strncmp (name, "mips", 4) == 0) |
| 11463 | { |
| 11464 | int isa; |
| 11465 | |
| 11466 | /* Permit the user to change the ISA on the fly. Needless to |
| 11467 | say, misuse can cause serious problems. */ |
| 11468 | isa = atoi (name + 4); |
| 11469 | switch (isa) |
| 11470 | { |
| 11471 | case 0: |
| 11472 | mips_opts.gp32 = file_mips_gp32; |
| 11473 | mips_opts.fp32 = file_mips_fp32; |
| 11474 | break; |
| 11475 | case 1: |
| 11476 | case 2: |
| 11477 | case 32: |
| 11478 | mips_opts.gp32 = 1; |
| 11479 | mips_opts.fp32 = 1; |
| 11480 | break; |
| 11481 | case 3: |
| 11482 | case 4: |
| 11483 | case 5: |
| 11484 | case 64: |
| 11485 | mips_opts.gp32 = 0; |
| 11486 | mips_opts.fp32 = 0; |
| 11487 | break; |
| 11488 | default: |
| 11489 | as_bad (_("unknown ISA level %s"), name + 4); |
| 11490 | break; |
| 11491 | } |
| 11492 | |
| 11493 | switch (isa) |
| 11494 | { |
| 11495 | case 0: mips_opts.isa = file_mips_isa; break; |
| 11496 | case 1: mips_opts.isa = ISA_MIPS1; break; |
| 11497 | case 2: mips_opts.isa = ISA_MIPS2; break; |
| 11498 | case 3: mips_opts.isa = ISA_MIPS3; break; |
| 11499 | case 4: mips_opts.isa = ISA_MIPS4; break; |
| 11500 | case 5: mips_opts.isa = ISA_MIPS5; break; |
| 11501 | case 32: mips_opts.isa = ISA_MIPS32; break; |
| 11502 | case 64: mips_opts.isa = ISA_MIPS64; break; |
| 11503 | default: as_bad (_("unknown ISA level %s"), name + 4); break; |
| 11504 | } |
| 11505 | } |
| 11506 | else if (strcmp (name, "autoextend") == 0) |
| 11507 | mips_opts.noautoextend = 0; |
| 11508 | else if (strcmp (name, "noautoextend") == 0) |
| 11509 | mips_opts.noautoextend = 1; |
| 11510 | else if (strcmp (name, "push") == 0) |
| 11511 | { |
| 11512 | struct mips_option_stack *s; |
| 11513 | |
| 11514 | s = (struct mips_option_stack *) xmalloc (sizeof *s); |
| 11515 | s->next = mips_opts_stack; |
| 11516 | s->options = mips_opts; |
| 11517 | mips_opts_stack = s; |
| 11518 | } |
| 11519 | else if (strcmp (name, "pop") == 0) |
| 11520 | { |
| 11521 | struct mips_option_stack *s; |
| 11522 | |
| 11523 | s = mips_opts_stack; |
| 11524 | if (s == NULL) |
| 11525 | as_bad (_(".set pop with no .set push")); |
| 11526 | else |
| 11527 | { |
| 11528 | /* If we're changing the reorder mode we need to handle |
| 11529 | delay slots correctly. */ |
| 11530 | if (s->options.noreorder && ! mips_opts.noreorder) |
| 11531 | mips_emit_delays (true); |
| 11532 | else if (! s->options.noreorder && mips_opts.noreorder) |
| 11533 | { |
| 11534 | if (prev_nop_frag != NULL) |
| 11535 | { |
| 11536 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
| 11537 | * (mips_opts.mips16 ? 2 : 4)); |
| 11538 | prev_nop_frag = NULL; |
| 11539 | } |
| 11540 | } |
| 11541 | |
| 11542 | mips_opts = s->options; |
| 11543 | mips_opts_stack = s->next; |
| 11544 | free (s); |
| 11545 | } |
| 11546 | } |
| 11547 | else |
| 11548 | { |
| 11549 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); |
| 11550 | } |
| 11551 | *input_line_pointer = ch; |
| 11552 | demand_empty_rest_of_line (); |
| 11553 | } |
| 11554 | |
| 11555 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
| 11556 | .option pic2. It means to generate SVR4 PIC calls. */ |
| 11557 | |
| 11558 | static void |
| 11559 | s_abicalls (ignore) |
| 11560 | int ignore ATTRIBUTE_UNUSED; |
| 11561 | { |
| 11562 | mips_pic = SVR4_PIC; |
| 11563 | if (USE_GLOBAL_POINTER_OPT) |
| 11564 | { |
| 11565 | if (g_switch_seen && g_switch_value != 0) |
| 11566 | as_warn (_("-G may not be used with SVR4 PIC code")); |
| 11567 | g_switch_value = 0; |
| 11568 | } |
| 11569 | bfd_set_gp_size (stdoutput, 0); |
| 11570 | demand_empty_rest_of_line (); |
| 11571 | } |
| 11572 | |
| 11573 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 |
| 11574 | PIC code. It sets the $gp register for the function based on the |
| 11575 | function address, which is in the register named in the argument. |
| 11576 | This uses a relocation against _gp_disp, which is handled specially |
| 11577 | by the linker. The result is: |
| 11578 | lui $gp,%hi(_gp_disp) |
| 11579 | addiu $gp,$gp,%lo(_gp_disp) |
| 11580 | addu $gp,$gp,.cpload argument |
| 11581 | The .cpload argument is normally $25 == $t9. */ |
| 11582 | |
| 11583 | static void |
| 11584 | s_cpload (ignore) |
| 11585 | int ignore ATTRIBUTE_UNUSED; |
| 11586 | { |
| 11587 | expressionS ex; |
| 11588 | int icnt = 0; |
| 11589 | |
| 11590 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
| 11591 | .cpload is ignored. */ |
| 11592 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
| 11593 | { |
| 11594 | s_ignore (0); |
| 11595 | return; |
| 11596 | } |
| 11597 | |
| 11598 | /* .cpload should be in a .set noreorder section. */ |
| 11599 | if (mips_opts.noreorder == 0) |
| 11600 | as_warn (_(".cpload not in noreorder section")); |
| 11601 | |
| 11602 | ex.X_op = O_symbol; |
| 11603 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); |
| 11604 | ex.X_op_symbol = NULL; |
| 11605 | ex.X_add_number = 0; |
| 11606 | |
| 11607 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
| 11608 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
| 11609 | |
| 11610 | macro_build_lui (NULL, &icnt, &ex, mips_gp_register); |
| 11611 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", |
| 11612 | mips_gp_register, mips_gp_register, (int) BFD_RELOC_LO16); |
| 11613 | |
| 11614 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
| 11615 | mips_gp_register, mips_gp_register, tc_get_register (0)); |
| 11616 | |
| 11617 | demand_empty_rest_of_line (); |
| 11618 | } |
| 11619 | |
| 11620 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
| 11621 | .cpsetup $reg1, offset|$reg2, label |
| 11622 | |
| 11623 | If offset is given, this results in: |
| 11624 | sd $gp, offset($sp) |
| 11625 | lui $gp, %hi(%neg(%gp_rel(label))) |
| 11626 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
| 11627 | daddu $gp, $gp, $reg1 |
| 11628 | |
| 11629 | If $reg2 is given, this results in: |
| 11630 | daddu $reg2, $gp, $0 |
| 11631 | lui $gp, %hi(%neg(%gp_rel(label))) |
| 11632 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
| 11633 | daddu $gp, $gp, $reg1 |
| 11634 | $reg1 is normally $25 == $t9. */ |
| 11635 | static void |
| 11636 | s_cpsetup (ignore) |
| 11637 | int ignore ATTRIBUTE_UNUSED; |
| 11638 | { |
| 11639 | expressionS ex_off; |
| 11640 | expressionS ex_sym; |
| 11641 | int reg1; |
| 11642 | int icnt = 0; |
| 11643 | char *sym; |
| 11644 | |
| 11645 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
| 11646 | We also need NewABI support. */ |
| 11647 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
| 11648 | { |
| 11649 | s_ignore (0); |
| 11650 | return; |
| 11651 | } |
| 11652 | |
| 11653 | reg1 = tc_get_register (0); |
| 11654 | SKIP_WHITESPACE (); |
| 11655 | if (*input_line_pointer != ',') |
| 11656 | { |
| 11657 | as_bad (_("missing argument separator ',' for .cpsetup")); |
| 11658 | return; |
| 11659 | } |
| 11660 | else |
| 11661 | ++input_line_pointer; |
| 11662 | SKIP_WHITESPACE (); |
| 11663 | if (*input_line_pointer == '$') |
| 11664 | { |
| 11665 | mips_cpreturn_register = tc_get_register (0); |
| 11666 | mips_cpreturn_offset = -1; |
| 11667 | } |
| 11668 | else |
| 11669 | { |
| 11670 | mips_cpreturn_offset = get_absolute_expression (); |
| 11671 | mips_cpreturn_register = -1; |
| 11672 | } |
| 11673 | SKIP_WHITESPACE (); |
| 11674 | if (*input_line_pointer != ',') |
| 11675 | { |
| 11676 | as_bad (_("missing argument separator ',' for .cpsetup")); |
| 11677 | return; |
| 11678 | } |
| 11679 | else |
| 11680 | ++input_line_pointer; |
| 11681 | SKIP_WHITESPACE (); |
| 11682 | sym = input_line_pointer; |
| 11683 | while (ISALNUM (*input_line_pointer)) |
| 11684 | ++input_line_pointer; |
| 11685 | *input_line_pointer = 0; |
| 11686 | |
| 11687 | ex_sym.X_op = O_symbol; |
| 11688 | ex_sym.X_add_symbol = symbol_find_or_make (sym); |
| 11689 | ex_sym.X_op_symbol = NULL; |
| 11690 | ex_sym.X_add_number = 0; |
| 11691 | |
| 11692 | if (mips_cpreturn_register == -1) |
| 11693 | { |
| 11694 | ex_off.X_op = O_constant; |
| 11695 | ex_off.X_add_symbol = NULL; |
| 11696 | ex_off.X_op_symbol = NULL; |
| 11697 | ex_off.X_add_number = mips_cpreturn_offset; |
| 11698 | |
| 11699 | macro_build ((char *) NULL, &icnt, &ex_off, "sd", "t,o(b)", |
| 11700 | mips_gp_register, (int) BFD_RELOC_LO16, SP); |
| 11701 | } |
| 11702 | else |
| 11703 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu", |
| 11704 | "d,v,t", mips_cpreturn_register, mips_gp_register, 0); |
| 11705 | |
| 11706 | macro_build ((char *) NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register, |
| 11707 | (int) BFD_RELOC_GPREL16); |
| 11708 | fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
| 11709 | fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_HI16_S); |
| 11710 | macro_build ((char *) NULL, &icnt, &ex_sym, "addiu", "t,r,j", |
| 11711 | mips_gp_register, mips_gp_register, (int) BFD_RELOC_GPREL16); |
| 11712 | fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
| 11713 | fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_LO16); |
| 11714 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 11715 | HAVE_64BIT_ADDRESSES ? "daddu" : "addu", "d,v,t", |
| 11716 | mips_gp_register, mips_gp_register, reg1); |
| 11717 | |
| 11718 | demand_empty_rest_of_line (); |
| 11719 | } |
| 11720 | |
| 11721 | static void |
| 11722 | s_cplocal (ignore) |
| 11723 | int ignore ATTRIBUTE_UNUSED; |
| 11724 | { |
| 11725 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, |
| 11726 | .cplocal is ignored. */ |
| 11727 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
| 11728 | { |
| 11729 | s_ignore (0); |
| 11730 | return; |
| 11731 | } |
| 11732 | |
| 11733 | mips_gp_register = tc_get_register (0); |
| 11734 | demand_empty_rest_of_line (); |
| 11735 | } |
| 11736 | |
| 11737 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
| 11738 | offset from $sp. The offset is remembered, and after making a PIC |
| 11739 | call $gp is restored from that location. */ |
| 11740 | |
| 11741 | static void |
| 11742 | s_cprestore (ignore) |
| 11743 | int ignore ATTRIBUTE_UNUSED; |
| 11744 | { |
| 11745 | expressionS ex; |
| 11746 | int icnt = 0; |
| 11747 | |
| 11748 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
| 11749 | .cprestore is ignored. */ |
| 11750 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
| 11751 | { |
| 11752 | s_ignore (0); |
| 11753 | return; |
| 11754 | } |
| 11755 | |
| 11756 | mips_cprestore_offset = get_absolute_expression (); |
| 11757 | mips_cprestore_valid = 1; |
| 11758 | |
| 11759 | ex.X_op = O_constant; |
| 11760 | ex.X_add_symbol = NULL; |
| 11761 | ex.X_op_symbol = NULL; |
| 11762 | ex.X_add_number = mips_cprestore_offset; |
| 11763 | |
| 11764 | macro_build ((char *) NULL, &icnt, &ex, HAVE_32BIT_ADDRESSES ? "sw" : "sd", |
| 11765 | "t,o(b)", mips_gp_register, (int) BFD_RELOC_LO16, SP); |
| 11766 | |
| 11767 | demand_empty_rest_of_line (); |
| 11768 | } |
| 11769 | |
| 11770 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
| 11771 | was given in the preceeding .gpsetup, it results in: |
| 11772 | ld $gp, offset($sp) |
| 11773 | |
| 11774 | If a register $reg2 was given there, it results in: |
| 11775 | daddiu $gp, $gp, $reg2 |
| 11776 | */ |
| 11777 | static void |
| 11778 | s_cpreturn (ignore) |
| 11779 | int ignore ATTRIBUTE_UNUSED; |
| 11780 | { |
| 11781 | expressionS ex; |
| 11782 | int icnt = 0; |
| 11783 | |
| 11784 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. |
| 11785 | We also need NewABI support. */ |
| 11786 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
| 11787 | { |
| 11788 | s_ignore (0); |
| 11789 | return; |
| 11790 | } |
| 11791 | |
| 11792 | if (mips_cpreturn_register == -1) |
| 11793 | { |
| 11794 | ex.X_op = O_constant; |
| 11795 | ex.X_add_symbol = NULL; |
| 11796 | ex.X_op_symbol = NULL; |
| 11797 | ex.X_add_number = mips_cpreturn_offset; |
| 11798 | |
| 11799 | macro_build ((char *) NULL, &icnt, &ex, "ld", "t,o(b)", |
| 11800 | mips_gp_register, (int) BFD_RELOC_LO16, SP); |
| 11801 | } |
| 11802 | else |
| 11803 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu", |
| 11804 | "d,v,t", mips_gp_register, mips_cpreturn_register, 0); |
| 11805 | |
| 11806 | demand_empty_rest_of_line (); |
| 11807 | } |
| 11808 | |
| 11809 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
| 11810 | code. It sets the offset to use in gp_rel relocations. */ |
| 11811 | |
| 11812 | static void |
| 11813 | s_gpvalue (ignore) |
| 11814 | int ignore ATTRIBUTE_UNUSED; |
| 11815 | { |
| 11816 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. |
| 11817 | We also need NewABI support. */ |
| 11818 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
| 11819 | { |
| 11820 | s_ignore (0); |
| 11821 | return; |
| 11822 | } |
| 11823 | |
| 11824 | mips_gprel_offset = get_absolute_expression (); |
| 11825 | |
| 11826 | demand_empty_rest_of_line (); |
| 11827 | } |
| 11828 | |
| 11829 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
| 11830 | code. It generates a 32 bit GP relative reloc. */ |
| 11831 | |
| 11832 | static void |
| 11833 | s_gpword (ignore) |
| 11834 | int ignore ATTRIBUTE_UNUSED; |
| 11835 | { |
| 11836 | symbolS *label; |
| 11837 | expressionS ex; |
| 11838 | char *p; |
| 11839 | |
| 11840 | /* When not generating PIC code, this is treated as .word. */ |
| 11841 | if (mips_pic != SVR4_PIC) |
| 11842 | { |
| 11843 | s_cons (2); |
| 11844 | return; |
| 11845 | } |
| 11846 | |
| 11847 | label = insn_labels != NULL ? insn_labels->label : NULL; |
| 11848 | mips_emit_delays (true); |
| 11849 | if (auto_align) |
| 11850 | mips_align (2, 0, label); |
| 11851 | mips_clear_insn_labels (); |
| 11852 | |
| 11853 | expression (&ex); |
| 11854 | |
| 11855 | if (ex.X_op != O_symbol || ex.X_add_number != 0) |
| 11856 | { |
| 11857 | as_bad (_("Unsupported use of .gpword")); |
| 11858 | ignore_rest_of_line (); |
| 11859 | } |
| 11860 | |
| 11861 | p = frag_more (4); |
| 11862 | md_number_to_chars (p, (valueT) 0, 4); |
| 11863 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, false, |
| 11864 | BFD_RELOC_GPREL32); |
| 11865 | |
| 11866 | demand_empty_rest_of_line (); |
| 11867 | } |
| 11868 | |
| 11869 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
| 11870 | tables in SVR4 PIC code. */ |
| 11871 | |
| 11872 | static void |
| 11873 | s_cpadd (ignore) |
| 11874 | int ignore ATTRIBUTE_UNUSED; |
| 11875 | { |
| 11876 | int icnt = 0; |
| 11877 | int reg; |
| 11878 | |
| 11879 | /* This is ignored when not generating SVR4 PIC code or if this is NewABI |
| 11880 | code. */ |
| 11881 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
| 11882 | { |
| 11883 | s_ignore (0); |
| 11884 | return; |
| 11885 | } |
| 11886 | |
| 11887 | /* Add $gp to the register named as an argument. */ |
| 11888 | reg = tc_get_register (0); |
| 11889 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 11890 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 11891 | "d,v,t", reg, reg, mips_gp_register); |
| 11892 | |
| 11893 | demand_empty_rest_of_line (); |
| 11894 | } |
| 11895 | |
| 11896 | /* Handle the .insn pseudo-op. This marks instruction labels in |
| 11897 | mips16 mode. This permits the linker to handle them specially, |
| 11898 | such as generating jalx instructions when needed. We also make |
| 11899 | them odd for the duration of the assembly, in order to generate the |
| 11900 | right sort of code. We will make them even in the adjust_symtab |
| 11901 | routine, while leaving them marked. This is convenient for the |
| 11902 | debugger and the disassembler. The linker knows to make them odd |
| 11903 | again. */ |
| 11904 | |
| 11905 | static void |
| 11906 | s_insn (ignore) |
| 11907 | int ignore ATTRIBUTE_UNUSED; |
| 11908 | { |
| 11909 | mips16_mark_labels (); |
| 11910 | |
| 11911 | demand_empty_rest_of_line (); |
| 11912 | } |
| 11913 | |
| 11914 | /* Handle a .stabn directive. We need these in order to mark a label |
| 11915 | as being a mips16 text label correctly. Sometimes the compiler |
| 11916 | will emit a label, followed by a .stabn, and then switch sections. |
| 11917 | If the label and .stabn are in mips16 mode, then the label is |
| 11918 | really a mips16 text label. */ |
| 11919 | |
| 11920 | static void |
| 11921 | s_mips_stab (type) |
| 11922 | int type; |
| 11923 | { |
| 11924 | if (type == 'n') |
| 11925 | mips16_mark_labels (); |
| 11926 | |
| 11927 | s_stab (type); |
| 11928 | } |
| 11929 | |
| 11930 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. |
| 11931 | */ |
| 11932 | |
| 11933 | static void |
| 11934 | s_mips_weakext (ignore) |
| 11935 | int ignore ATTRIBUTE_UNUSED; |
| 11936 | { |
| 11937 | char *name; |
| 11938 | int c; |
| 11939 | symbolS *symbolP; |
| 11940 | expressionS exp; |
| 11941 | |
| 11942 | name = input_line_pointer; |
| 11943 | c = get_symbol_end (); |
| 11944 | symbolP = symbol_find_or_make (name); |
| 11945 | S_SET_WEAK (symbolP); |
| 11946 | *input_line_pointer = c; |
| 11947 | |
| 11948 | SKIP_WHITESPACE (); |
| 11949 | |
| 11950 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
| 11951 | { |
| 11952 | if (S_IS_DEFINED (symbolP)) |
| 11953 | { |
| 11954 | as_bad ("ignoring attempt to redefine symbol %s", |
| 11955 | S_GET_NAME (symbolP)); |
| 11956 | ignore_rest_of_line (); |
| 11957 | return; |
| 11958 | } |
| 11959 | |
| 11960 | if (*input_line_pointer == ',') |
| 11961 | { |
| 11962 | ++input_line_pointer; |
| 11963 | SKIP_WHITESPACE (); |
| 11964 | } |
| 11965 | |
| 11966 | expression (&exp); |
| 11967 | if (exp.X_op != O_symbol) |
| 11968 | { |
| 11969 | as_bad ("bad .weakext directive"); |
| 11970 | ignore_rest_of_line (); |
| 11971 | return; |
| 11972 | } |
| 11973 | symbol_set_value_expression (symbolP, &exp); |
| 11974 | } |
| 11975 | |
| 11976 | demand_empty_rest_of_line (); |
| 11977 | } |
| 11978 | |
| 11979 | /* Parse a register string into a number. Called from the ECOFF code |
| 11980 | to parse .frame. The argument is non-zero if this is the frame |
| 11981 | register, so that we can record it in mips_frame_reg. */ |
| 11982 | |
| 11983 | int |
| 11984 | tc_get_register (frame) |
| 11985 | int frame; |
| 11986 | { |
| 11987 | int reg; |
| 11988 | |
| 11989 | SKIP_WHITESPACE (); |
| 11990 | if (*input_line_pointer++ != '$') |
| 11991 | { |
| 11992 | as_warn (_("expected `$'")); |
| 11993 | reg = ZERO; |
| 11994 | } |
| 11995 | else if (ISDIGIT (*input_line_pointer)) |
| 11996 | { |
| 11997 | reg = get_absolute_expression (); |
| 11998 | if (reg < 0 || reg >= 32) |
| 11999 | { |
| 12000 | as_warn (_("Bad register number")); |
| 12001 | reg = ZERO; |
| 12002 | } |
| 12003 | } |
| 12004 | else |
| 12005 | { |
| 12006 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
| 12007 | { |
| 12008 | reg = RA; |
| 12009 | input_line_pointer += 2; |
| 12010 | } |
| 12011 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
| 12012 | { |
| 12013 | reg = FP; |
| 12014 | input_line_pointer += 2; |
| 12015 | } |
| 12016 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
| 12017 | { |
| 12018 | reg = SP; |
| 12019 | input_line_pointer += 2; |
| 12020 | } |
| 12021 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
| 12022 | { |
| 12023 | reg = GP; |
| 12024 | input_line_pointer += 2; |
| 12025 | } |
| 12026 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
| 12027 | { |
| 12028 | reg = AT; |
| 12029 | input_line_pointer += 2; |
| 12030 | } |
| 12031 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) |
| 12032 | { |
| 12033 | reg = KT0; |
| 12034 | input_line_pointer += 3; |
| 12035 | } |
| 12036 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) |
| 12037 | { |
| 12038 | reg = KT1; |
| 12039 | input_line_pointer += 3; |
| 12040 | } |
| 12041 | else if (strncmp (input_line_pointer, "zero", 4) == 0) |
| 12042 | { |
| 12043 | reg = ZERO; |
| 12044 | input_line_pointer += 4; |
| 12045 | } |
| 12046 | else |
| 12047 | { |
| 12048 | as_warn (_("Unrecognized register name")); |
| 12049 | reg = ZERO; |
| 12050 | while (ISALNUM(*input_line_pointer)) |
| 12051 | input_line_pointer++; |
| 12052 | } |
| 12053 | } |
| 12054 | if (frame) |
| 12055 | { |
| 12056 | mips_frame_reg = reg != 0 ? reg : SP; |
| 12057 | mips_frame_reg_valid = 1; |
| 12058 | mips_cprestore_valid = 0; |
| 12059 | } |
| 12060 | return reg; |
| 12061 | } |
| 12062 | |
| 12063 | valueT |
| 12064 | md_section_align (seg, addr) |
| 12065 | asection *seg; |
| 12066 | valueT addr; |
| 12067 | { |
| 12068 | int align = bfd_get_section_alignment (stdoutput, seg); |
| 12069 | |
| 12070 | #ifdef OBJ_ELF |
| 12071 | /* We don't need to align ELF sections to the full alignment. |
| 12072 | However, Irix 5 may prefer that we align them at least to a 16 |
| 12073 | byte boundary. We don't bother to align the sections if we are |
| 12074 | targeted for an embedded system. */ |
| 12075 | if (strcmp (TARGET_OS, "elf") == 0) |
| 12076 | return addr; |
| 12077 | if (align > 4) |
| 12078 | align = 4; |
| 12079 | #endif |
| 12080 | |
| 12081 | return ((addr + (1 << align) - 1) & (-1 << align)); |
| 12082 | } |
| 12083 | |
| 12084 | /* Utility routine, called from above as well. If called while the |
| 12085 | input file is still being read, it's only an approximation. (For |
| 12086 | example, a symbol may later become defined which appeared to be |
| 12087 | undefined earlier.) */ |
| 12088 | |
| 12089 | static int |
| 12090 | nopic_need_relax (sym, before_relaxing) |
| 12091 | symbolS *sym; |
| 12092 | int before_relaxing; |
| 12093 | { |
| 12094 | if (sym == 0) |
| 12095 | return 0; |
| 12096 | |
| 12097 | if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0) |
| 12098 | { |
| 12099 | const char *symname; |
| 12100 | int change; |
| 12101 | |
| 12102 | /* Find out whether this symbol can be referenced off the $gp |
| 12103 | register. It can be if it is smaller than the -G size or if |
| 12104 | it is in the .sdata or .sbss section. Certain symbols can |
| 12105 | not be referenced off the $gp, although it appears as though |
| 12106 | they can. */ |
| 12107 | symname = S_GET_NAME (sym); |
| 12108 | if (symname != (const char *) NULL |
| 12109 | && (strcmp (symname, "eprol") == 0 |
| 12110 | || strcmp (symname, "etext") == 0 |
| 12111 | || strcmp (symname, "_gp") == 0 |
| 12112 | || strcmp (symname, "edata") == 0 |
| 12113 | || strcmp (symname, "_fbss") == 0 |
| 12114 | || strcmp (symname, "_fdata") == 0 |
| 12115 | || strcmp (symname, "_ftext") == 0 |
| 12116 | || strcmp (symname, "end") == 0 |
| 12117 | || strcmp (symname, "_gp_disp") == 0)) |
| 12118 | change = 1; |
| 12119 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) |
| 12120 | && (0 |
| 12121 | #ifndef NO_ECOFF_DEBUGGING |
| 12122 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
| 12123 | && (symbol_get_obj (sym)->ecoff_extern_size |
| 12124 | <= g_switch_value)) |
| 12125 | #endif |
| 12126 | /* We must defer this decision until after the whole |
| 12127 | file has been read, since there might be a .extern |
| 12128 | after the first use of this symbol. */ |
| 12129 | || (before_relaxing |
| 12130 | #ifndef NO_ECOFF_DEBUGGING |
| 12131 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
| 12132 | #endif |
| 12133 | && S_GET_VALUE (sym) == 0) |
| 12134 | || (S_GET_VALUE (sym) != 0 |
| 12135 | && S_GET_VALUE (sym) <= g_switch_value))) |
| 12136 | change = 0; |
| 12137 | else |
| 12138 | { |
| 12139 | const char *segname; |
| 12140 | |
| 12141 | segname = segment_name (S_GET_SEGMENT (sym)); |
| 12142 | assert (strcmp (segname, ".lit8") != 0 |
| 12143 | && strcmp (segname, ".lit4") != 0); |
| 12144 | change = (strcmp (segname, ".sdata") != 0 |
| 12145 | && strcmp (segname, ".sbss") != 0 |
| 12146 | && strncmp (segname, ".sdata.", 7) != 0 |
| 12147 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
| 12148 | } |
| 12149 | return change; |
| 12150 | } |
| 12151 | else |
| 12152 | /* We are not optimizing for the $gp register. */ |
| 12153 | return 1; |
| 12154 | } |
| 12155 | |
| 12156 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
| 12157 | extended opcode. SEC is the section the frag is in. */ |
| 12158 | |
| 12159 | static int |
| 12160 | mips16_extended_frag (fragp, sec, stretch) |
| 12161 | fragS *fragp; |
| 12162 | asection *sec; |
| 12163 | long stretch; |
| 12164 | { |
| 12165 | int type; |
| 12166 | register const struct mips16_immed_operand *op; |
| 12167 | offsetT val; |
| 12168 | int mintiny, maxtiny; |
| 12169 | segT symsec; |
| 12170 | fragS *sym_frag; |
| 12171 | |
| 12172 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) |
| 12173 | return 0; |
| 12174 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
| 12175 | return 1; |
| 12176 | |
| 12177 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
| 12178 | op = mips16_immed_operands; |
| 12179 | while (op->type != type) |
| 12180 | { |
| 12181 | ++op; |
| 12182 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
| 12183 | } |
| 12184 | |
| 12185 | if (op->unsp) |
| 12186 | { |
| 12187 | if (type == '<' || type == '>' || type == '[' || type == ']') |
| 12188 | { |
| 12189 | mintiny = 1; |
| 12190 | maxtiny = 1 << op->nbits; |
| 12191 | } |
| 12192 | else |
| 12193 | { |
| 12194 | mintiny = 0; |
| 12195 | maxtiny = (1 << op->nbits) - 1; |
| 12196 | } |
| 12197 | } |
| 12198 | else |
| 12199 | { |
| 12200 | mintiny = - (1 << (op->nbits - 1)); |
| 12201 | maxtiny = (1 << (op->nbits - 1)) - 1; |
| 12202 | } |
| 12203 | |
| 12204 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
| 12205 | val = S_GET_VALUE (fragp->fr_symbol); |
| 12206 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
| 12207 | |
| 12208 | if (op->pcrel) |
| 12209 | { |
| 12210 | addressT addr; |
| 12211 | |
| 12212 | /* We won't have the section when we are called from |
| 12213 | mips_relax_frag. However, we will always have been called |
| 12214 | from md_estimate_size_before_relax first. If this is a |
| 12215 | branch to a different section, we mark it as such. If SEC is |
| 12216 | NULL, and the frag is not marked, then it must be a branch to |
| 12217 | the same section. */ |
| 12218 | if (sec == NULL) |
| 12219 | { |
| 12220 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) |
| 12221 | return 1; |
| 12222 | } |
| 12223 | else |
| 12224 | { |
| 12225 | /* Must have been called from md_estimate_size_before_relax. */ |
| 12226 | if (symsec != sec) |
| 12227 | { |
| 12228 | fragp->fr_subtype = |
| 12229 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); |
| 12230 | |
| 12231 | /* FIXME: We should support this, and let the linker |
| 12232 | catch branches and loads that are out of range. */ |
| 12233 | as_bad_where (fragp->fr_file, fragp->fr_line, |
| 12234 | _("unsupported PC relative reference to different section")); |
| 12235 | |
| 12236 | return 1; |
| 12237 | } |
| 12238 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
| 12239 | /* Assume non-extended on the first relaxation pass. |
| 12240 | The address we have calculated will be bogus if this is |
| 12241 | a forward branch to another frag, as the forward frag |
| 12242 | will have fr_address == 0. */ |
| 12243 | return 0; |
| 12244 | } |
| 12245 | |
| 12246 | /* In this case, we know for sure that the symbol fragment is in |
| 12247 | the same section. If the relax_marker of the symbol fragment |
| 12248 | differs from the relax_marker of this fragment, we have not |
| 12249 | yet adjusted the symbol fragment fr_address. We want to add |
| 12250 | in STRETCH in order to get a better estimate of the address. |
| 12251 | This particularly matters because of the shift bits. */ |
| 12252 | if (stretch != 0 |
| 12253 | && sym_frag->relax_marker != fragp->relax_marker) |
| 12254 | { |
| 12255 | fragS *f; |
| 12256 | |
| 12257 | /* Adjust stretch for any alignment frag. Note that if have |
| 12258 | been expanding the earlier code, the symbol may be |
| 12259 | defined in what appears to be an earlier frag. FIXME: |
| 12260 | This doesn't handle the fr_subtype field, which specifies |
| 12261 | a maximum number of bytes to skip when doing an |
| 12262 | alignment. */ |
| 12263 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
| 12264 | { |
| 12265 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) |
| 12266 | { |
| 12267 | if (stretch < 0) |
| 12268 | stretch = - ((- stretch) |
| 12269 | & ~ ((1 << (int) f->fr_offset) - 1)); |
| 12270 | else |
| 12271 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); |
| 12272 | if (stretch == 0) |
| 12273 | break; |
| 12274 | } |
| 12275 | } |
| 12276 | if (f != NULL) |
| 12277 | val += stretch; |
| 12278 | } |
| 12279 | |
| 12280 | addr = fragp->fr_address + fragp->fr_fix; |
| 12281 | |
| 12282 | /* The base address rules are complicated. The base address of |
| 12283 | a branch is the following instruction. The base address of a |
| 12284 | PC relative load or add is the instruction itself, but if it |
| 12285 | is in a delay slot (in which case it can not be extended) use |
| 12286 | the address of the instruction whose delay slot it is in. */ |
| 12287 | if (type == 'p' || type == 'q') |
| 12288 | { |
| 12289 | addr += 2; |
| 12290 | |
| 12291 | /* If we are currently assuming that this frag should be |
| 12292 | extended, then, the current address is two bytes |
| 12293 | higher. */ |
| 12294 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
| 12295 | addr += 2; |
| 12296 | |
| 12297 | /* Ignore the low bit in the target, since it will be set |
| 12298 | for a text label. */ |
| 12299 | if ((val & 1) != 0) |
| 12300 | --val; |
| 12301 | } |
| 12302 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
| 12303 | addr -= 4; |
| 12304 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) |
| 12305 | addr -= 2; |
| 12306 | |
| 12307 | val -= addr & ~ ((1 << op->shift) - 1); |
| 12308 | |
| 12309 | /* Branch offsets have an implicit 0 in the lowest bit. */ |
| 12310 | if (type == 'p' || type == 'q') |
| 12311 | val /= 2; |
| 12312 | |
| 12313 | /* If any of the shifted bits are set, we must use an extended |
| 12314 | opcode. If the address depends on the size of this |
| 12315 | instruction, this can lead to a loop, so we arrange to always |
| 12316 | use an extended opcode. We only check this when we are in |
| 12317 | the main relaxation loop, when SEC is NULL. */ |
| 12318 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) |
| 12319 | { |
| 12320 | fragp->fr_subtype = |
| 12321 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); |
| 12322 | return 1; |
| 12323 | } |
| 12324 | |
| 12325 | /* If we are about to mark a frag as extended because the value |
| 12326 | is precisely maxtiny + 1, then there is a chance of an |
| 12327 | infinite loop as in the following code: |
| 12328 | la $4,foo |
| 12329 | .skip 1020 |
| 12330 | .align 2 |
| 12331 | foo: |
| 12332 | In this case when the la is extended, foo is 0x3fc bytes |
| 12333 | away, so the la can be shrunk, but then foo is 0x400 away, so |
| 12334 | the la must be extended. To avoid this loop, we mark the |
| 12335 | frag as extended if it was small, and is about to become |
| 12336 | extended with a value of maxtiny + 1. */ |
| 12337 | if (val == ((maxtiny + 1) << op->shift) |
| 12338 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) |
| 12339 | && sec == NULL) |
| 12340 | { |
| 12341 | fragp->fr_subtype = |
| 12342 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); |
| 12343 | return 1; |
| 12344 | } |
| 12345 | } |
| 12346 | else if (symsec != absolute_section && sec != NULL) |
| 12347 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); |
| 12348 | |
| 12349 | if ((val & ((1 << op->shift) - 1)) != 0 |
| 12350 | || val < (mintiny << op->shift) |
| 12351 | || val > (maxtiny << op->shift)) |
| 12352 | return 1; |
| 12353 | else |
| 12354 | return 0; |
| 12355 | } |
| 12356 | |
| 12357 | /* Estimate the size of a frag before relaxing. Unless this is the |
| 12358 | mips16, we are not really relaxing here, and the final size is |
| 12359 | encoded in the subtype information. For the mips16, we have to |
| 12360 | decide whether we are using an extended opcode or not. */ |
| 12361 | |
| 12362 | int |
| 12363 | md_estimate_size_before_relax (fragp, segtype) |
| 12364 | fragS *fragp; |
| 12365 | asection *segtype; |
| 12366 | { |
| 12367 | int change = 0; |
| 12368 | boolean linkonce = false; |
| 12369 | |
| 12370 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
| 12371 | /* We don't want to modify the EXTENDED bit here; it might get us |
| 12372 | into infinite loops. We change it only in mips_relax_frag(). */ |
| 12373 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); |
| 12374 | |
| 12375 | if (mips_pic == NO_PIC) |
| 12376 | { |
| 12377 | change = nopic_need_relax (fragp->fr_symbol, 0); |
| 12378 | } |
| 12379 | else if (mips_pic == SVR4_PIC) |
| 12380 | { |
| 12381 | symbolS *sym; |
| 12382 | asection *symsec; |
| 12383 | |
| 12384 | sym = fragp->fr_symbol; |
| 12385 | |
| 12386 | /* Handle the case of a symbol equated to another symbol. */ |
| 12387 | while (symbol_equated_reloc_p (sym)) |
| 12388 | { |
| 12389 | symbolS *n; |
| 12390 | |
| 12391 | /* It's possible to get a loop here in a badly written |
| 12392 | program. */ |
| 12393 | n = symbol_get_value_expression (sym)->X_add_symbol; |
| 12394 | if (n == sym) |
| 12395 | break; |
| 12396 | sym = n; |
| 12397 | } |
| 12398 | |
| 12399 | symsec = S_GET_SEGMENT (sym); |
| 12400 | |
| 12401 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ |
| 12402 | if (symsec != segtype && ! S_IS_LOCAL (sym)) |
| 12403 | { |
| 12404 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) |
| 12405 | != 0) |
| 12406 | linkonce = true; |
| 12407 | |
| 12408 | /* The GNU toolchain uses an extension for ELF: a section |
| 12409 | beginning with the magic string .gnu.linkonce is a linkonce |
| 12410 | section. */ |
| 12411 | if (strncmp (segment_name (symsec), ".gnu.linkonce", |
| 12412 | sizeof ".gnu.linkonce" - 1) == 0) |
| 12413 | linkonce = true; |
| 12414 | } |
| 12415 | |
| 12416 | /* This must duplicate the test in adjust_reloc_syms. */ |
| 12417 | change = (symsec != &bfd_und_section |
| 12418 | && symsec != &bfd_abs_section |
| 12419 | && ! bfd_is_com_section (symsec) |
| 12420 | && !linkonce |
| 12421 | #ifdef OBJ_ELF |
| 12422 | /* A global or weak symbol is treated as external. */ |
| 12423 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour |
| 12424 | || (! S_IS_WEAK (sym) |
| 12425 | && (! S_IS_EXTERNAL (sym) |
| 12426 | || mips_pic == EMBEDDED_PIC))) |
| 12427 | #endif |
| 12428 | ); |
| 12429 | } |
| 12430 | else |
| 12431 | abort (); |
| 12432 | |
| 12433 | if (change) |
| 12434 | { |
| 12435 | /* Record the offset to the first reloc in the fr_opcode field. |
| 12436 | This lets md_convert_frag and tc_gen_reloc know that the code |
| 12437 | must be expanded. */ |
| 12438 | fragp->fr_opcode = (fragp->fr_literal |
| 12439 | + fragp->fr_fix |
| 12440 | - RELAX_OLD (fragp->fr_subtype) |
| 12441 | + RELAX_RELOC1 (fragp->fr_subtype)); |
| 12442 | /* FIXME: This really needs as_warn_where. */ |
| 12443 | if (RELAX_WARN (fragp->fr_subtype)) |
| 12444 | as_warn (_("AT used after \".set noat\" or macro used after " |
| 12445 | "\".set nomacro\"")); |
| 12446 | |
| 12447 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); |
| 12448 | } |
| 12449 | |
| 12450 | return 0; |
| 12451 | } |
| 12452 | |
| 12453 | /* This is called to see whether a reloc against a defined symbol |
| 12454 | should be converted into a reloc against a section. Don't adjust |
| 12455 | MIPS16 jump relocations, so we don't have to worry about the format |
| 12456 | of the offset in the .o file. Don't adjust relocations against |
| 12457 | mips16 symbols, so that the linker can find them if it needs to set |
| 12458 | up a stub. */ |
| 12459 | |
| 12460 | int |
| 12461 | mips_fix_adjustable (fixp) |
| 12462 | fixS *fixp; |
| 12463 | { |
| 12464 | #ifdef OBJ_ELF |
| 12465 | /* Prevent all adjustments to global symbols. */ |
| 12466 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
| 12467 | && mips_pic != EMBEDDED_PIC |
| 12468 | && (S_IS_EXTERNAL (fixp->fx_addsy) || S_IS_WEAK (fixp->fx_addsy))) |
| 12469 | return 0; |
| 12470 | #endif |
| 12471 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) |
| 12472 | return 0; |
| 12473 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
| 12474 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
| 12475 | return 0; |
| 12476 | if (fixp->fx_addsy == NULL) |
| 12477 | return 1; |
| 12478 | #ifdef OBJ_ELF |
| 12479 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
| 12480 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 |
| 12481 | && fixp->fx_subsy == NULL) |
| 12482 | return 0; |
| 12483 | #endif |
| 12484 | return 1; |
| 12485 | } |
| 12486 | |
| 12487 | /* Translate internal representation of relocation info to BFD target |
| 12488 | format. */ |
| 12489 | |
| 12490 | arelent ** |
| 12491 | tc_gen_reloc (section, fixp) |
| 12492 | asection *section ATTRIBUTE_UNUSED; |
| 12493 | fixS *fixp; |
| 12494 | { |
| 12495 | static arelent *retval[4]; |
| 12496 | arelent *reloc; |
| 12497 | bfd_reloc_code_real_type code; |
| 12498 | |
| 12499 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
| 12500 | retval[1] = NULL; |
| 12501 | |
| 12502 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
| 12503 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
| 12504 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
| 12505 | |
| 12506 | if (mips_pic == EMBEDDED_PIC |
| 12507 | && SWITCH_TABLE (fixp)) |
| 12508 | { |
| 12509 | /* For a switch table entry we use a special reloc. The addend |
| 12510 | is actually the difference between the reloc address and the |
| 12511 | subtrahend. */ |
| 12512 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); |
| 12513 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) |
| 12514 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); |
| 12515 | fixp->fx_r_type = BFD_RELOC_GPREL32; |
| 12516 | } |
| 12517 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
| 12518 | { |
| 12519 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
| 12520 | reloc->addend = fixp->fx_addnumber; |
| 12521 | else |
| 12522 | { |
| 12523 | /* We use a special addend for an internal RELLO reloc. */ |
| 12524 | if (symbol_section_p (fixp->fx_addsy)) |
| 12525 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); |
| 12526 | else |
| 12527 | reloc->addend = fixp->fx_addnumber + reloc->address; |
| 12528 | } |
| 12529 | } |
| 12530 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) |
| 12531 | { |
| 12532 | assert (fixp->fx_next != NULL |
| 12533 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); |
| 12534 | |
| 12535 | /* The reloc is relative to the RELLO; adjust the addend |
| 12536 | accordingly. */ |
| 12537 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
| 12538 | reloc->addend = fixp->fx_next->fx_addnumber; |
| 12539 | else |
| 12540 | { |
| 12541 | /* We use a special addend for an internal RELHI reloc. */ |
| 12542 | if (symbol_section_p (fixp->fx_addsy)) |
| 12543 | reloc->addend = (fixp->fx_next->fx_frag->fr_address |
| 12544 | + fixp->fx_next->fx_where |
| 12545 | - S_GET_VALUE (fixp->fx_subsy)); |
| 12546 | else |
| 12547 | reloc->addend = (fixp->fx_addnumber |
| 12548 | + fixp->fx_next->fx_frag->fr_address |
| 12549 | + fixp->fx_next->fx_where); |
| 12550 | } |
| 12551 | } |
| 12552 | else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour) |
| 12553 | reloc->addend = fixp->fx_addnumber; |
| 12554 | else |
| 12555 | { |
| 12556 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
| 12557 | /* A gruesome hack which is a result of the gruesome gas reloc |
| 12558 | handling. */ |
| 12559 | reloc->addend = reloc->address; |
| 12560 | else |
| 12561 | reloc->addend = -reloc->address; |
| 12562 | } |
| 12563 | |
| 12564 | /* If this is a variant frag, we may need to adjust the existing |
| 12565 | reloc and generate a new one. */ |
| 12566 | if (fixp->fx_frag->fr_opcode != NULL |
| 12567 | && (fixp->fx_r_type == BFD_RELOC_GPREL16 |
| 12568 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 |
| 12569 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 |
| 12570 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 |
| 12571 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 |
| 12572 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 |
| 12573 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16) |
| 12574 | && ! HAVE_NEWABI) |
| 12575 | { |
| 12576 | arelent *reloc2; |
| 12577 | |
| 12578 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); |
| 12579 | |
| 12580 | /* If this is not the last reloc in this frag, then we have two |
| 12581 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a |
| 12582 | CALL_HI16/CALL_LO16, both of which are being replaced. Let |
| 12583 | the second one handle all of them. */ |
| 12584 | if (fixp->fx_next != NULL |
| 12585 | && fixp->fx_frag == fixp->fx_next->fx_frag) |
| 12586 | { |
| 12587 | assert ((fixp->fx_r_type == BFD_RELOC_GPREL16 |
| 12588 | && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16) |
| 12589 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 |
| 12590 | && (fixp->fx_next->fx_r_type |
| 12591 | == BFD_RELOC_MIPS_GOT_LO16)) |
| 12592 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 |
| 12593 | && (fixp->fx_next->fx_r_type |
| 12594 | == BFD_RELOC_MIPS_CALL_LO16))); |
| 12595 | retval[0] = NULL; |
| 12596 | return retval; |
| 12597 | } |
| 12598 | |
| 12599 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; |
| 12600 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
| 12601 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); |
| 12602 | retval[2] = NULL; |
| 12603 | reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
| 12604 | *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
| 12605 | reloc2->address = (reloc->address |
| 12606 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) |
| 12607 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); |
| 12608 | reloc2->addend = fixp->fx_addnumber; |
| 12609 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); |
| 12610 | assert (reloc2->howto != NULL); |
| 12611 | |
| 12612 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) |
| 12613 | { |
| 12614 | arelent *reloc3; |
| 12615 | |
| 12616 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); |
| 12617 | retval[3] = NULL; |
| 12618 | *reloc3 = *reloc2; |
| 12619 | reloc3->address += 4; |
| 12620 | } |
| 12621 | |
| 12622 | if (mips_pic == NO_PIC) |
| 12623 | { |
| 12624 | assert (fixp->fx_r_type == BFD_RELOC_GPREL16); |
| 12625 | fixp->fx_r_type = BFD_RELOC_HI16_S; |
| 12626 | } |
| 12627 | else if (mips_pic == SVR4_PIC) |
| 12628 | { |
| 12629 | switch (fixp->fx_r_type) |
| 12630 | { |
| 12631 | default: |
| 12632 | abort (); |
| 12633 | case BFD_RELOC_MIPS_GOT16: |
| 12634 | break; |
| 12635 | case BFD_RELOC_MIPS_CALL16: |
| 12636 | case BFD_RELOC_MIPS_GOT_LO16: |
| 12637 | case BFD_RELOC_MIPS_CALL_LO16: |
| 12638 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; |
| 12639 | break; |
| 12640 | } |
| 12641 | } |
| 12642 | else |
| 12643 | abort (); |
| 12644 | } |
| 12645 | |
| 12646 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
| 12647 | entry to be used in the relocation's section offset. */ |
| 12648 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
| 12649 | { |
| 12650 | reloc->address = reloc->addend; |
| 12651 | reloc->addend = 0; |
| 12652 | } |
| 12653 | |
| 12654 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that |
| 12655 | fixup_segment converted a non-PC relative reloc into a PC |
| 12656 | relative reloc. In such a case, we need to convert the reloc |
| 12657 | code. */ |
| 12658 | code = fixp->fx_r_type; |
| 12659 | if (fixp->fx_pcrel) |
| 12660 | { |
| 12661 | switch (code) |
| 12662 | { |
| 12663 | case BFD_RELOC_8: |
| 12664 | code = BFD_RELOC_8_PCREL; |
| 12665 | break; |
| 12666 | case BFD_RELOC_16: |
| 12667 | code = BFD_RELOC_16_PCREL; |
| 12668 | break; |
| 12669 | case BFD_RELOC_32: |
| 12670 | code = BFD_RELOC_32_PCREL; |
| 12671 | break; |
| 12672 | case BFD_RELOC_64: |
| 12673 | code = BFD_RELOC_64_PCREL; |
| 12674 | break; |
| 12675 | case BFD_RELOC_8_PCREL: |
| 12676 | case BFD_RELOC_16_PCREL: |
| 12677 | case BFD_RELOC_32_PCREL: |
| 12678 | case BFD_RELOC_64_PCREL: |
| 12679 | case BFD_RELOC_16_PCREL_S2: |
| 12680 | case BFD_RELOC_PCREL_HI16_S: |
| 12681 | case BFD_RELOC_PCREL_LO16: |
| 12682 | break; |
| 12683 | default: |
| 12684 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 12685 | _("Cannot make %s relocation PC relative"), |
| 12686 | bfd_get_reloc_code_name (code)); |
| 12687 | } |
| 12688 | } |
| 12689 | |
| 12690 | #ifdef OBJ_ELF |
| 12691 | /* md_apply_fix3 has a double-subtraction hack to get |
| 12692 | bfd_install_relocation to behave nicely. GPREL relocations are |
| 12693 | handled correctly without this hack, so undo it here. We can't |
| 12694 | stop md_apply_fix3 from subtracting twice in the first place since |
| 12695 | the fake addend is required for variant frags above. */ |
| 12696 | if (fixp->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour |
| 12697 | && code == BFD_RELOC_GPREL16 |
| 12698 | && reloc->addend != 0 |
| 12699 | && mips_need_elf_addend_fixup (fixp)) |
| 12700 | reloc->addend += S_GET_VALUE (fixp->fx_addsy); |
| 12701 | #endif |
| 12702 | |
| 12703 | /* To support a PC relative reloc when generating embedded PIC code |
| 12704 | for ECOFF, we use a Cygnus extension. We check for that here to |
| 12705 | make sure that we don't let such a reloc escape normally. */ |
| 12706 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
| 12707 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) |
| 12708 | && code == BFD_RELOC_16_PCREL_S2 |
| 12709 | && mips_pic != EMBEDDED_PIC) |
| 12710 | reloc->howto = NULL; |
| 12711 | else |
| 12712 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
| 12713 | |
| 12714 | if (reloc->howto == NULL) |
| 12715 | { |
| 12716 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 12717 | _("Can not represent %s relocation in this object file format"), |
| 12718 | bfd_get_reloc_code_name (code)); |
| 12719 | retval[0] = NULL; |
| 12720 | } |
| 12721 | |
| 12722 | return retval; |
| 12723 | } |
| 12724 | |
| 12725 | /* Relax a machine dependent frag. This returns the amount by which |
| 12726 | the current size of the frag should change. */ |
| 12727 | |
| 12728 | int |
| 12729 | mips_relax_frag (fragp, stretch) |
| 12730 | fragS *fragp; |
| 12731 | long stretch; |
| 12732 | { |
| 12733 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
| 12734 | return 0; |
| 12735 | |
| 12736 | if (mips16_extended_frag (fragp, NULL, stretch)) |
| 12737 | { |
| 12738 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
| 12739 | return 0; |
| 12740 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); |
| 12741 | return 2; |
| 12742 | } |
| 12743 | else |
| 12744 | { |
| 12745 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
| 12746 | return 0; |
| 12747 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); |
| 12748 | return -2; |
| 12749 | } |
| 12750 | |
| 12751 | return 0; |
| 12752 | } |
| 12753 | |
| 12754 | /* Convert a machine dependent frag. */ |
| 12755 | |
| 12756 | void |
| 12757 | md_convert_frag (abfd, asec, fragp) |
| 12758 | bfd *abfd ATTRIBUTE_UNUSED; |
| 12759 | segT asec; |
| 12760 | fragS *fragp; |
| 12761 | { |
| 12762 | int old, new; |
| 12763 | char *fixptr; |
| 12764 | |
| 12765 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
| 12766 | { |
| 12767 | int type; |
| 12768 | register const struct mips16_immed_operand *op; |
| 12769 | boolean small, ext; |
| 12770 | offsetT val; |
| 12771 | bfd_byte *buf; |
| 12772 | unsigned long insn; |
| 12773 | boolean use_extend; |
| 12774 | unsigned short extend; |
| 12775 | |
| 12776 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
| 12777 | op = mips16_immed_operands; |
| 12778 | while (op->type != type) |
| 12779 | ++op; |
| 12780 | |
| 12781 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
| 12782 | { |
| 12783 | small = false; |
| 12784 | ext = true; |
| 12785 | } |
| 12786 | else |
| 12787 | { |
| 12788 | small = true; |
| 12789 | ext = false; |
| 12790 | } |
| 12791 | |
| 12792 | resolve_symbol_value (fragp->fr_symbol); |
| 12793 | val = S_GET_VALUE (fragp->fr_symbol); |
| 12794 | if (op->pcrel) |
| 12795 | { |
| 12796 | addressT addr; |
| 12797 | |
| 12798 | addr = fragp->fr_address + fragp->fr_fix; |
| 12799 | |
| 12800 | /* The rules for the base address of a PC relative reloc are |
| 12801 | complicated; see mips16_extended_frag. */ |
| 12802 | if (type == 'p' || type == 'q') |
| 12803 | { |
| 12804 | addr += 2; |
| 12805 | if (ext) |
| 12806 | addr += 2; |
| 12807 | /* Ignore the low bit in the target, since it will be |
| 12808 | set for a text label. */ |
| 12809 | if ((val & 1) != 0) |
| 12810 | --val; |
| 12811 | } |
| 12812 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
| 12813 | addr -= 4; |
| 12814 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) |
| 12815 | addr -= 2; |
| 12816 | |
| 12817 | addr &= ~ (addressT) ((1 << op->shift) - 1); |
| 12818 | val -= addr; |
| 12819 | |
| 12820 | /* Make sure the section winds up with the alignment we have |
| 12821 | assumed. */ |
| 12822 | if (op->shift > 0) |
| 12823 | record_alignment (asec, op->shift); |
| 12824 | } |
| 12825 | |
| 12826 | if (ext |
| 12827 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) |
| 12828 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) |
| 12829 | as_warn_where (fragp->fr_file, fragp->fr_line, |
| 12830 | _("extended instruction in delay slot")); |
| 12831 | |
| 12832 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); |
| 12833 | |
| 12834 | if (target_big_endian) |
| 12835 | insn = bfd_getb16 (buf); |
| 12836 | else |
| 12837 | insn = bfd_getl16 (buf); |
| 12838 | |
| 12839 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, |
| 12840 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), |
| 12841 | small, ext, &insn, &use_extend, &extend); |
| 12842 | |
| 12843 | if (use_extend) |
| 12844 | { |
| 12845 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
| 12846 | fragp->fr_fix += 2; |
| 12847 | buf += 2; |
| 12848 | } |
| 12849 | |
| 12850 | md_number_to_chars ((char *) buf, insn, 2); |
| 12851 | fragp->fr_fix += 2; |
| 12852 | buf += 2; |
| 12853 | } |
| 12854 | else |
| 12855 | { |
| 12856 | if (fragp->fr_opcode == NULL) |
| 12857 | return; |
| 12858 | |
| 12859 | old = RELAX_OLD (fragp->fr_subtype); |
| 12860 | new = RELAX_NEW (fragp->fr_subtype); |
| 12861 | fixptr = fragp->fr_literal + fragp->fr_fix; |
| 12862 | |
| 12863 | if (new > 0) |
| 12864 | memcpy (fixptr - old, fixptr, new); |
| 12865 | |
| 12866 | fragp->fr_fix += new - old; |
| 12867 | } |
| 12868 | } |
| 12869 | |
| 12870 | #ifdef OBJ_ELF |
| 12871 | |
| 12872 | /* This function is called after the relocs have been generated. |
| 12873 | We've been storing mips16 text labels as odd. Here we convert them |
| 12874 | back to even for the convenience of the debugger. */ |
| 12875 | |
| 12876 | void |
| 12877 | mips_frob_file_after_relocs () |
| 12878 | { |
| 12879 | asymbol **syms; |
| 12880 | unsigned int count, i; |
| 12881 | |
| 12882 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
| 12883 | return; |
| 12884 | |
| 12885 | syms = bfd_get_outsymbols (stdoutput); |
| 12886 | count = bfd_get_symcount (stdoutput); |
| 12887 | for (i = 0; i < count; i++, syms++) |
| 12888 | { |
| 12889 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 |
| 12890 | && ((*syms)->value & 1) != 0) |
| 12891 | { |
| 12892 | (*syms)->value &= ~1; |
| 12893 | /* If the symbol has an odd size, it was probably computed |
| 12894 | incorrectly, so adjust that as well. */ |
| 12895 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) |
| 12896 | ++elf_symbol (*syms)->internal_elf_sym.st_size; |
| 12897 | } |
| 12898 | } |
| 12899 | } |
| 12900 | |
| 12901 | #endif |
| 12902 | |
| 12903 | /* This function is called whenever a label is defined. It is used |
| 12904 | when handling branch delays; if a branch has a label, we assume we |
| 12905 | can not move it. */ |
| 12906 | |
| 12907 | void |
| 12908 | mips_define_label (sym) |
| 12909 | symbolS *sym; |
| 12910 | { |
| 12911 | struct insn_label_list *l; |
| 12912 | |
| 12913 | if (free_insn_labels == NULL) |
| 12914 | l = (struct insn_label_list *) xmalloc (sizeof *l); |
| 12915 | else |
| 12916 | { |
| 12917 | l = free_insn_labels; |
| 12918 | free_insn_labels = l->next; |
| 12919 | } |
| 12920 | |
| 12921 | l->label = sym; |
| 12922 | l->next = insn_labels; |
| 12923 | insn_labels = l; |
| 12924 | } |
| 12925 | \f |
| 12926 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 12927 | |
| 12928 | /* Some special processing for a MIPS ELF file. */ |
| 12929 | |
| 12930 | void |
| 12931 | mips_elf_final_processing () |
| 12932 | { |
| 12933 | /* Write out the register information. */ |
| 12934 | if (mips_abi != N64_ABI) |
| 12935 | { |
| 12936 | Elf32_RegInfo s; |
| 12937 | |
| 12938 | s.ri_gprmask = mips_gprmask; |
| 12939 | s.ri_cprmask[0] = mips_cprmask[0]; |
| 12940 | s.ri_cprmask[1] = mips_cprmask[1]; |
| 12941 | s.ri_cprmask[2] = mips_cprmask[2]; |
| 12942 | s.ri_cprmask[3] = mips_cprmask[3]; |
| 12943 | /* The gp_value field is set by the MIPS ELF backend. */ |
| 12944 | |
| 12945 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, |
| 12946 | ((Elf32_External_RegInfo *) |
| 12947 | mips_regmask_frag)); |
| 12948 | } |
| 12949 | else |
| 12950 | { |
| 12951 | Elf64_Internal_RegInfo s; |
| 12952 | |
| 12953 | s.ri_gprmask = mips_gprmask; |
| 12954 | s.ri_pad = 0; |
| 12955 | s.ri_cprmask[0] = mips_cprmask[0]; |
| 12956 | s.ri_cprmask[1] = mips_cprmask[1]; |
| 12957 | s.ri_cprmask[2] = mips_cprmask[2]; |
| 12958 | s.ri_cprmask[3] = mips_cprmask[3]; |
| 12959 | /* The gp_value field is set by the MIPS ELF backend. */ |
| 12960 | |
| 12961 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, |
| 12962 | ((Elf64_External_RegInfo *) |
| 12963 | mips_regmask_frag)); |
| 12964 | } |
| 12965 | |
| 12966 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some |
| 12967 | sort of BFD interface for this. */ |
| 12968 | if (mips_any_noreorder) |
| 12969 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; |
| 12970 | if (mips_pic != NO_PIC) |
| 12971 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
| 12972 | |
| 12973 | /* Set MIPS ELF flags for ASEs. */ |
| 12974 | if (file_ase_mips16) |
| 12975 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; |
| 12976 | #if 0 /* XXX FIXME */ |
| 12977 | if (file_ase_mips3d) |
| 12978 | elf_elfheader (stdoutput)->e_flags |= ???; |
| 12979 | #endif |
| 12980 | if (file_ase_mdmx) |
| 12981 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; |
| 12982 | |
| 12983 | /* Set the MIPS ELF ABI flags. */ |
| 12984 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
| 12985 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
| 12986 | else if (mips_abi == O64_ABI) |
| 12987 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
| 12988 | else if (mips_abi == EABI_ABI) |
| 12989 | { |
| 12990 | if (!file_mips_gp32) |
| 12991 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
| 12992 | else |
| 12993 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; |
| 12994 | } |
| 12995 | else if (mips_abi == N32_ABI) |
| 12996 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
| 12997 | |
| 12998 | /* Nothing to do for N64_ABI. */ |
| 12999 | |
| 13000 | if (mips_32bitmode) |
| 13001 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; |
| 13002 | } |
| 13003 | |
| 13004 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |
| 13005 | \f |
| 13006 | typedef struct proc { |
| 13007 | symbolS *isym; |
| 13008 | unsigned long reg_mask; |
| 13009 | unsigned long reg_offset; |
| 13010 | unsigned long fpreg_mask; |
| 13011 | unsigned long fpreg_offset; |
| 13012 | unsigned long frame_offset; |
| 13013 | unsigned long frame_reg; |
| 13014 | unsigned long pc_reg; |
| 13015 | } procS; |
| 13016 | |
| 13017 | static procS cur_proc; |
| 13018 | static procS *cur_proc_ptr; |
| 13019 | static int numprocs; |
| 13020 | |
| 13021 | /* Fill in an rs_align_code fragment. */ |
| 13022 | |
| 13023 | void |
| 13024 | mips_handle_align (fragp) |
| 13025 | fragS *fragp; |
| 13026 | { |
| 13027 | if (fragp->fr_type != rs_align_code) |
| 13028 | return; |
| 13029 | |
| 13030 | if (mips_opts.mips16) |
| 13031 | { |
| 13032 | static const unsigned char be_nop[] = { 0x65, 0x00 }; |
| 13033 | static const unsigned char le_nop[] = { 0x00, 0x65 }; |
| 13034 | |
| 13035 | int bytes; |
| 13036 | char *p; |
| 13037 | |
| 13038 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
| 13039 | p = fragp->fr_literal + fragp->fr_fix; |
| 13040 | |
| 13041 | if (bytes & 1) |
| 13042 | { |
| 13043 | *p++ = 0; |
| 13044 | fragp->fr_fix++; |
| 13045 | } |
| 13046 | |
| 13047 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); |
| 13048 | fragp->fr_var = 2; |
| 13049 | } |
| 13050 | |
| 13051 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
| 13052 | } |
| 13053 | |
| 13054 | static void |
| 13055 | md_obj_begin () |
| 13056 | { |
| 13057 | } |
| 13058 | |
| 13059 | static void |
| 13060 | md_obj_end () |
| 13061 | { |
| 13062 | /* check for premature end, nesting errors, etc */ |
| 13063 | if (cur_proc_ptr) |
| 13064 | as_warn (_("missing .end at end of assembly")); |
| 13065 | } |
| 13066 | |
| 13067 | static long |
| 13068 | get_number () |
| 13069 | { |
| 13070 | int negative = 0; |
| 13071 | long val = 0; |
| 13072 | |
| 13073 | if (*input_line_pointer == '-') |
| 13074 | { |
| 13075 | ++input_line_pointer; |
| 13076 | negative = 1; |
| 13077 | } |
| 13078 | if (!ISDIGIT (*input_line_pointer)) |
| 13079 | as_bad (_("expected simple number")); |
| 13080 | if (input_line_pointer[0] == '0') |
| 13081 | { |
| 13082 | if (input_line_pointer[1] == 'x') |
| 13083 | { |
| 13084 | input_line_pointer += 2; |
| 13085 | while (ISXDIGIT (*input_line_pointer)) |
| 13086 | { |
| 13087 | val <<= 4; |
| 13088 | val |= hex_value (*input_line_pointer++); |
| 13089 | } |
| 13090 | return negative ? -val : val; |
| 13091 | } |
| 13092 | else |
| 13093 | { |
| 13094 | ++input_line_pointer; |
| 13095 | while (ISDIGIT (*input_line_pointer)) |
| 13096 | { |
| 13097 | val <<= 3; |
| 13098 | val |= *input_line_pointer++ - '0'; |
| 13099 | } |
| 13100 | return negative ? -val : val; |
| 13101 | } |
| 13102 | } |
| 13103 | if (!ISDIGIT (*input_line_pointer)) |
| 13104 | { |
| 13105 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), |
| 13106 | *input_line_pointer, *input_line_pointer); |
| 13107 | as_warn (_("invalid number")); |
| 13108 | return -1; |
| 13109 | } |
| 13110 | while (ISDIGIT (*input_line_pointer)) |
| 13111 | { |
| 13112 | val *= 10; |
| 13113 | val += *input_line_pointer++ - '0'; |
| 13114 | } |
| 13115 | return negative ? -val : val; |
| 13116 | } |
| 13117 | |
| 13118 | /* The .file directive; just like the usual .file directive, but there |
| 13119 | is an initial number which is the ECOFF file index. In the non-ECOFF |
| 13120 | case .file implies DWARF-2. */ |
| 13121 | |
| 13122 | static void |
| 13123 | s_mips_file (x) |
| 13124 | int x ATTRIBUTE_UNUSED; |
| 13125 | { |
| 13126 | static int first_file_directive = 0; |
| 13127 | |
| 13128 | if (ECOFF_DEBUGGING) |
| 13129 | { |
| 13130 | get_number (); |
| 13131 | s_app_file (0); |
| 13132 | } |
| 13133 | else |
| 13134 | { |
| 13135 | char *filename; |
| 13136 | |
| 13137 | filename = dwarf2_directive_file (0); |
| 13138 | |
| 13139 | /* Versions of GCC up to 3.1 start files with a ".file" |
| 13140 | directive even for stabs output. Make sure that this |
| 13141 | ".file" is handled. Note that you need a version of GCC |
| 13142 | after 3.1 in order to support DWARF-2 on MIPS. */ |
| 13143 | if (filename != NULL && ! first_file_directive) |
| 13144 | { |
| 13145 | (void) new_logical_line (filename, -1); |
| 13146 | s_app_file_string (filename); |
| 13147 | } |
| 13148 | first_file_directive = 1; |
| 13149 | } |
| 13150 | } |
| 13151 | |
| 13152 | /* The .loc directive, implying DWARF-2. */ |
| 13153 | |
| 13154 | static void |
| 13155 | s_mips_loc (x) |
| 13156 | int x ATTRIBUTE_UNUSED; |
| 13157 | { |
| 13158 | if (!ECOFF_DEBUGGING) |
| 13159 | dwarf2_directive_loc (0); |
| 13160 | } |
| 13161 | |
| 13162 | /* The .end directive. */ |
| 13163 | |
| 13164 | static void |
| 13165 | s_mips_end (x) |
| 13166 | int x ATTRIBUTE_UNUSED; |
| 13167 | { |
| 13168 | symbolS *p; |
| 13169 | int maybe_text; |
| 13170 | |
| 13171 | /* Following functions need their own .frame and .cprestore directives. */ |
| 13172 | mips_frame_reg_valid = 0; |
| 13173 | mips_cprestore_valid = 0; |
| 13174 | |
| 13175 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
| 13176 | { |
| 13177 | p = get_symbol (); |
| 13178 | demand_empty_rest_of_line (); |
| 13179 | } |
| 13180 | else |
| 13181 | p = NULL; |
| 13182 | |
| 13183 | #ifdef BFD_ASSEMBLER |
| 13184 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) |
| 13185 | maybe_text = 1; |
| 13186 | else |
| 13187 | maybe_text = 0; |
| 13188 | #else |
| 13189 | if (now_seg != data_section && now_seg != bss_section) |
| 13190 | maybe_text = 1; |
| 13191 | else |
| 13192 | maybe_text = 0; |
| 13193 | #endif |
| 13194 | |
| 13195 | if (!maybe_text) |
| 13196 | as_warn (_(".end not in text section")); |
| 13197 | |
| 13198 | if (!cur_proc_ptr) |
| 13199 | { |
| 13200 | as_warn (_(".end directive without a preceding .ent directive.")); |
| 13201 | demand_empty_rest_of_line (); |
| 13202 | return; |
| 13203 | } |
| 13204 | |
| 13205 | if (p != NULL) |
| 13206 | { |
| 13207 | assert (S_GET_NAME (p)); |
| 13208 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) |
| 13209 | as_warn (_(".end symbol does not match .ent symbol.")); |
| 13210 | |
| 13211 | if (debug_type == DEBUG_STABS) |
| 13212 | stabs_generate_asm_endfunc (S_GET_NAME (p), |
| 13213 | S_GET_NAME (p)); |
| 13214 | } |
| 13215 | else |
| 13216 | as_warn (_(".end directive missing or unknown symbol")); |
| 13217 | |
| 13218 | #ifdef OBJ_ELF |
| 13219 | /* Generate a .pdr section. */ |
| 13220 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) |
| 13221 | { |
| 13222 | segT saved_seg = now_seg; |
| 13223 | subsegT saved_subseg = now_subseg; |
| 13224 | valueT dot; |
| 13225 | expressionS exp; |
| 13226 | char *fragp; |
| 13227 | |
| 13228 | dot = frag_now_fix (); |
| 13229 | |
| 13230 | #ifdef md_flush_pending_output |
| 13231 | md_flush_pending_output (); |
| 13232 | #endif |
| 13233 | |
| 13234 | assert (pdr_seg); |
| 13235 | subseg_set (pdr_seg, 0); |
| 13236 | |
| 13237 | /* Write the symbol. */ |
| 13238 | exp.X_op = O_symbol; |
| 13239 | exp.X_add_symbol = p; |
| 13240 | exp.X_add_number = 0; |
| 13241 | emit_expr (&exp, 4); |
| 13242 | |
| 13243 | fragp = frag_more (7 * 4); |
| 13244 | |
| 13245 | md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4); |
| 13246 | md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4); |
| 13247 | md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4); |
| 13248 | md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4); |
| 13249 | md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4); |
| 13250 | md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4); |
| 13251 | md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4); |
| 13252 | |
| 13253 | subseg_set (saved_seg, saved_subseg); |
| 13254 | } |
| 13255 | #endif /* OBJ_ELF */ |
| 13256 | |
| 13257 | cur_proc_ptr = NULL; |
| 13258 | } |
| 13259 | |
| 13260 | /* The .aent and .ent directives. */ |
| 13261 | |
| 13262 | static void |
| 13263 | s_mips_ent (aent) |
| 13264 | int aent; |
| 13265 | { |
| 13266 | symbolS *symbolP; |
| 13267 | int maybe_text; |
| 13268 | |
| 13269 | symbolP = get_symbol (); |
| 13270 | if (*input_line_pointer == ',') |
| 13271 | ++input_line_pointer; |
| 13272 | SKIP_WHITESPACE (); |
| 13273 | if (ISDIGIT (*input_line_pointer) |
| 13274 | || *input_line_pointer == '-') |
| 13275 | get_number (); |
| 13276 | |
| 13277 | #ifdef BFD_ASSEMBLER |
| 13278 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) |
| 13279 | maybe_text = 1; |
| 13280 | else |
| 13281 | maybe_text = 0; |
| 13282 | #else |
| 13283 | if (now_seg != data_section && now_seg != bss_section) |
| 13284 | maybe_text = 1; |
| 13285 | else |
| 13286 | maybe_text = 0; |
| 13287 | #endif |
| 13288 | |
| 13289 | if (!maybe_text) |
| 13290 | as_warn (_(".ent or .aent not in text section.")); |
| 13291 | |
| 13292 | if (!aent && cur_proc_ptr) |
| 13293 | as_warn (_("missing .end")); |
| 13294 | |
| 13295 | if (!aent) |
| 13296 | { |
| 13297 | /* This function needs its own .frame and .cprestore directives. */ |
| 13298 | mips_frame_reg_valid = 0; |
| 13299 | mips_cprestore_valid = 0; |
| 13300 | |
| 13301 | cur_proc_ptr = &cur_proc; |
| 13302 | memset (cur_proc_ptr, '\0', sizeof (procS)); |
| 13303 | |
| 13304 | cur_proc_ptr->isym = symbolP; |
| 13305 | |
| 13306 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
| 13307 | |
| 13308 | ++numprocs; |
| 13309 | |
| 13310 | if (debug_type == DEBUG_STABS) |
| 13311 | stabs_generate_asm_func (S_GET_NAME (symbolP), |
| 13312 | S_GET_NAME (symbolP)); |
| 13313 | } |
| 13314 | |
| 13315 | demand_empty_rest_of_line (); |
| 13316 | } |
| 13317 | |
| 13318 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) |
| 13319 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
| 13320 | s_mips_frame is used so that we can set the PDR information correctly. |
| 13321 | We can't use the ecoff routines because they make reference to the ecoff |
| 13322 | symbol table (in the mdebug section). */ |
| 13323 | |
| 13324 | static void |
| 13325 | s_mips_frame (ignore) |
| 13326 | int ignore ATTRIBUTE_UNUSED; |
| 13327 | { |
| 13328 | #ifdef OBJ_ELF |
| 13329 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) |
| 13330 | { |
| 13331 | long val; |
| 13332 | |
| 13333 | if (cur_proc_ptr == (procS *) NULL) |
| 13334 | { |
| 13335 | as_warn (_(".frame outside of .ent")); |
| 13336 | demand_empty_rest_of_line (); |
| 13337 | return; |
| 13338 | } |
| 13339 | |
| 13340 | cur_proc_ptr->frame_reg = tc_get_register (1); |
| 13341 | |
| 13342 | SKIP_WHITESPACE (); |
| 13343 | if (*input_line_pointer++ != ',' |
| 13344 | || get_absolute_expression_and_terminator (&val) != ',') |
| 13345 | { |
| 13346 | as_warn (_("Bad .frame directive")); |
| 13347 | --input_line_pointer; |
| 13348 | demand_empty_rest_of_line (); |
| 13349 | return; |
| 13350 | } |
| 13351 | |
| 13352 | cur_proc_ptr->frame_offset = val; |
| 13353 | cur_proc_ptr->pc_reg = tc_get_register (0); |
| 13354 | |
| 13355 | demand_empty_rest_of_line (); |
| 13356 | } |
| 13357 | else |
| 13358 | #endif /* OBJ_ELF */ |
| 13359 | s_ignore (ignore); |
| 13360 | } |
| 13361 | |
| 13362 | /* The .fmask and .mask directives. If the mdebug section is present |
| 13363 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For |
| 13364 | embedded targets, s_mips_mask is used so that we can set the PDR |
| 13365 | information correctly. We can't use the ecoff routines because they |
| 13366 | make reference to the ecoff symbol table (in the mdebug section). */ |
| 13367 | |
| 13368 | static void |
| 13369 | s_mips_mask (reg_type) |
| 13370 | char reg_type; |
| 13371 | { |
| 13372 | #ifdef OBJ_ELF |
| 13373 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) |
| 13374 | { |
| 13375 | long mask, off; |
| 13376 | |
| 13377 | if (cur_proc_ptr == (procS *) NULL) |
| 13378 | { |
| 13379 | as_warn (_(".mask/.fmask outside of .ent")); |
| 13380 | demand_empty_rest_of_line (); |
| 13381 | return; |
| 13382 | } |
| 13383 | |
| 13384 | if (get_absolute_expression_and_terminator (&mask) != ',') |
| 13385 | { |
| 13386 | as_warn (_("Bad .mask/.fmask directive")); |
| 13387 | --input_line_pointer; |
| 13388 | demand_empty_rest_of_line (); |
| 13389 | return; |
| 13390 | } |
| 13391 | |
| 13392 | off = get_absolute_expression (); |
| 13393 | |
| 13394 | if (reg_type == 'F') |
| 13395 | { |
| 13396 | cur_proc_ptr->fpreg_mask = mask; |
| 13397 | cur_proc_ptr->fpreg_offset = off; |
| 13398 | } |
| 13399 | else |
| 13400 | { |
| 13401 | cur_proc_ptr->reg_mask = mask; |
| 13402 | cur_proc_ptr->reg_offset = off; |
| 13403 | } |
| 13404 | |
| 13405 | demand_empty_rest_of_line (); |
| 13406 | } |
| 13407 | else |
| 13408 | #endif /* OBJ_ELF */ |
| 13409 | s_ignore (reg_type); |
| 13410 | } |
| 13411 | |
| 13412 | /* The .loc directive. */ |
| 13413 | |
| 13414 | #if 0 |
| 13415 | static void |
| 13416 | s_loc (x) |
| 13417 | int x; |
| 13418 | { |
| 13419 | symbolS *symbolP; |
| 13420 | int lineno; |
| 13421 | int addroff; |
| 13422 | |
| 13423 | assert (now_seg == text_section); |
| 13424 | |
| 13425 | lineno = get_number (); |
| 13426 | addroff = frag_now_fix (); |
| 13427 | |
| 13428 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
| 13429 | S_SET_TYPE (symbolP, N_SLINE); |
| 13430 | S_SET_OTHER (symbolP, 0); |
| 13431 | S_SET_DESC (symbolP, lineno); |
| 13432 | symbolP->sy_segment = now_seg; |
| 13433 | } |
| 13434 | #endif |
| 13435 | |
| 13436 | /* A table describing all the processors gas knows about. Names are |
| 13437 | matched in the order listed. |
| 13438 | |
| 13439 | To ease comparison, please keep this table in the same order as |
| 13440 | gcc's mips_cpu_info_table[]. */ |
| 13441 | static const struct mips_cpu_info mips_cpu_info_table[] = |
| 13442 | { |
| 13443 | /* Entries for generic ISAs */ |
| 13444 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, |
| 13445 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, |
| 13446 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, |
| 13447 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, |
| 13448 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, |
| 13449 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, |
| 13450 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, |
| 13451 | |
| 13452 | /* MIPS I */ |
| 13453 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
| 13454 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, |
| 13455 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, |
| 13456 | |
| 13457 | /* MIPS II */ |
| 13458 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
| 13459 | |
| 13460 | /* MIPS III */ |
| 13461 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
| 13462 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, |
| 13463 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, |
| 13464 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, |
| 13465 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, |
| 13466 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, |
| 13467 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, |
| 13468 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, |
| 13469 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, |
| 13470 | |
| 13471 | /* MIPS IV */ |
| 13472 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
| 13473 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, |
| 13474 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, |
| 13475 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, |
| 13476 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, |
| 13477 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, |
| 13478 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, |
| 13479 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, |
| 13480 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, |
| 13481 | { "r7000", 0, ISA_MIPS4, CPU_R5000 }, |
| 13482 | |
| 13483 | /* MIPS 32 */ |
| 13484 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32, }, |
| 13485 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, |
| 13486 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, |
| 13487 | |
| 13488 | /* MIPS 64 */ |
| 13489 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
| 13490 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
| 13491 | |
| 13492 | /* Broadcom SB-1 CPU */ |
| 13493 | { "SB-1", 0, ISA_MIPS64, CPU_SB1 }, |
| 13494 | { "sb-1250", 0, ISA_MIPS64, CPU_SB1 }, |
| 13495 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
| 13496 | { "sb1250", 0, ISA_MIPS64, CPU_SB1 }, |
| 13497 | |
| 13498 | /* End marker */ |
| 13499 | { NULL, 0, 0, 0 } |
| 13500 | }; |
| 13501 | |
| 13502 | |
| 13503 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
| 13504 | with a final "000" replaced by "k". Ignore case. |
| 13505 | |
| 13506 | Note: this function is shared between GCC and GAS. */ |
| 13507 | |
| 13508 | static boolean |
| 13509 | mips_strict_matching_cpu_name_p (canonical, given) |
| 13510 | const char *canonical, *given; |
| 13511 | { |
| 13512 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) |
| 13513 | given++, canonical++; |
| 13514 | |
| 13515 | return ((*given == 0 && *canonical == 0) |
| 13516 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); |
| 13517 | } |
| 13518 | |
| 13519 | |
| 13520 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied |
| 13521 | CPU name. We've traditionally allowed a lot of variation here. |
| 13522 | |
| 13523 | Note: this function is shared between GCC and GAS. */ |
| 13524 | |
| 13525 | static boolean |
| 13526 | mips_matching_cpu_name_p (canonical, given) |
| 13527 | const char *canonical, *given; |
| 13528 | { |
| 13529 | /* First see if the name matches exactly, or with a final "000" |
| 13530 | turned into "k". */ |
| 13531 | if (mips_strict_matching_cpu_name_p (canonical, given)) |
| 13532 | return true; |
| 13533 | |
| 13534 | /* If not, try comparing based on numerical designation alone. |
| 13535 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ |
| 13536 | if (TOLOWER (*given) == 'r') |
| 13537 | given++; |
| 13538 | if (!ISDIGIT (*given)) |
| 13539 | return false; |
| 13540 | |
| 13541 | /* Skip over some well-known prefixes in the canonical name, |
| 13542 | hoping to find a number there too. */ |
| 13543 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') |
| 13544 | canonical += 2; |
| 13545 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') |
| 13546 | canonical += 2; |
| 13547 | else if (TOLOWER (canonical[0]) == 'r') |
| 13548 | canonical += 1; |
| 13549 | |
| 13550 | return mips_strict_matching_cpu_name_p (canonical, given); |
| 13551 | } |
| 13552 | |
| 13553 | |
| 13554 | /* Parse an option that takes the name of a processor as its argument. |
| 13555 | OPTION is the name of the option and CPU_STRING is the argument. |
| 13556 | Return the corresponding processor enumeration if the CPU_STRING is |
| 13557 | recognized, otherwise report an error and return null. |
| 13558 | |
| 13559 | A similar function exists in GCC. */ |
| 13560 | |
| 13561 | static const struct mips_cpu_info * |
| 13562 | mips_parse_cpu (option, cpu_string) |
| 13563 | const char *option, *cpu_string; |
| 13564 | { |
| 13565 | const struct mips_cpu_info *p; |
| 13566 | |
| 13567 | /* 'from-abi' selects the most compatible architecture for the given |
| 13568 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the |
| 13569 | EABIs, we have to decide whether we're using the 32-bit or 64-bit |
| 13570 | version. Look first at the -mgp options, if given, otherwise base |
| 13571 | the choice on MIPS_DEFAULT_64BIT. |
| 13572 | |
| 13573 | Treat NO_ABI like the EABIs. One reason to do this is that the |
| 13574 | plain 'mips' and 'mips64' configs have 'from-abi' as their default |
| 13575 | architecture. This code picks MIPS I for 'mips' and MIPS III for |
| 13576 | 'mips64', just as we did in the days before 'from-abi'. */ |
| 13577 | if (strcasecmp (cpu_string, "from-abi") == 0) |
| 13578 | { |
| 13579 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) |
| 13580 | return mips_cpu_info_from_isa (ISA_MIPS1); |
| 13581 | |
| 13582 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) |
| 13583 | return mips_cpu_info_from_isa (ISA_MIPS3); |
| 13584 | |
| 13585 | if (file_mips_gp32 >= 0) |
| 13586 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); |
| 13587 | |
| 13588 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT |
| 13589 | ? ISA_MIPS3 |
| 13590 | : ISA_MIPS1); |
| 13591 | } |
| 13592 | |
| 13593 | /* 'default' has traditionally been a no-op. Probably not very useful. */ |
| 13594 | if (strcasecmp (cpu_string, "default") == 0) |
| 13595 | return 0; |
| 13596 | |
| 13597 | for (p = mips_cpu_info_table; p->name != 0; p++) |
| 13598 | if (mips_matching_cpu_name_p (p->name, cpu_string)) |
| 13599 | return p; |
| 13600 | |
| 13601 | as_bad ("Bad value (%s) for %s", cpu_string, option); |
| 13602 | return 0; |
| 13603 | } |
| 13604 | |
| 13605 | /* Return the canonical processor information for ISA (a member of the |
| 13606 | ISA_MIPS* enumeration). */ |
| 13607 | |
| 13608 | static const struct mips_cpu_info * |
| 13609 | mips_cpu_info_from_isa (isa) |
| 13610 | int isa; |
| 13611 | { |
| 13612 | int i; |
| 13613 | |
| 13614 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) |
| 13615 | if (mips_cpu_info_table[i].is_isa |
| 13616 | && isa == mips_cpu_info_table[i].isa) |
| 13617 | return (&mips_cpu_info_table[i]); |
| 13618 | |
| 13619 | return NULL; |
| 13620 | } |
| 13621 | \f |
| 13622 | static void |
| 13623 | show (stream, string, col_p, first_p) |
| 13624 | FILE *stream; |
| 13625 | const char *string; |
| 13626 | int *col_p; |
| 13627 | int *first_p; |
| 13628 | { |
| 13629 | if (*first_p) |
| 13630 | { |
| 13631 | fprintf (stream, "%24s", ""); |
| 13632 | *col_p = 24; |
| 13633 | } |
| 13634 | else |
| 13635 | { |
| 13636 | fprintf (stream, ", "); |
| 13637 | *col_p += 2; |
| 13638 | } |
| 13639 | |
| 13640 | if (*col_p + strlen (string) > 72) |
| 13641 | { |
| 13642 | fprintf (stream, "\n%24s", ""); |
| 13643 | *col_p = 24; |
| 13644 | } |
| 13645 | |
| 13646 | fprintf (stream, "%s", string); |
| 13647 | *col_p += strlen (string); |
| 13648 | |
| 13649 | *first_p = 0; |
| 13650 | } |
| 13651 | |
| 13652 | void |
| 13653 | md_show_usage (stream) |
| 13654 | FILE *stream; |
| 13655 | { |
| 13656 | int column, first; |
| 13657 | size_t i; |
| 13658 | |
| 13659 | fprintf (stream, _("\ |
| 13660 | MIPS options:\n\ |
| 13661 | -membedded-pic generate embedded position independent code\n\ |
| 13662 | -EB generate big endian output\n\ |
| 13663 | -EL generate little endian output\n\ |
| 13664 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ |
| 13665 | -G NUM allow referencing objects up to NUM bytes\n\ |
| 13666 | implicitly with the gp register [default 8]\n")); |
| 13667 | fprintf (stream, _("\ |
| 13668 | -mips1 generate MIPS ISA I instructions\n\ |
| 13669 | -mips2 generate MIPS ISA II instructions\n\ |
| 13670 | -mips3 generate MIPS ISA III instructions\n\ |
| 13671 | -mips4 generate MIPS ISA IV instructions\n\ |
| 13672 | -mips5 generate MIPS ISA V instructions\n\ |
| 13673 | -mips32 generate MIPS32 ISA instructions\n\ |
| 13674 | -mips64 generate MIPS64 ISA instructions\n\ |
| 13675 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
| 13676 | |
| 13677 | first = 1; |
| 13678 | |
| 13679 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) |
| 13680 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
| 13681 | show (stream, "from-abi", &column, &first); |
| 13682 | fputc ('\n', stream); |
| 13683 | |
| 13684 | fprintf (stream, _("\ |
| 13685 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ |
| 13686 | -no-mCPU don't generate code specific to CPU.\n\ |
| 13687 | For -mCPU and -no-mCPU, CPU must be one of:\n")); |
| 13688 | |
| 13689 | first = 1; |
| 13690 | |
| 13691 | show (stream, "3900", &column, &first); |
| 13692 | show (stream, "4010", &column, &first); |
| 13693 | show (stream, "4100", &column, &first); |
| 13694 | show (stream, "4650", &column, &first); |
| 13695 | fputc ('\n', stream); |
| 13696 | |
| 13697 | fprintf (stream, _("\ |
| 13698 | -mips16 generate mips16 instructions\n\ |
| 13699 | -no-mips16 do not generate mips16 instructions\n")); |
| 13700 | fprintf (stream, _("\ |
| 13701 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
| 13702 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ |
| 13703 | -O0 remove unneeded NOPs, do not swap branches\n\ |
| 13704 | -O remove unneeded NOPs and swap branches\n\ |
| 13705 | -n warn about NOPs generated from macros\n\ |
| 13706 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
| 13707 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
| 13708 | --break, --no-trap break exception on div by 0 and mult overflow\n")); |
| 13709 | #ifdef OBJ_ELF |
| 13710 | fprintf (stream, _("\ |
| 13711 | -KPIC, -call_shared generate SVR4 position independent code\n\ |
| 13712 | -non_shared do not generate position independent code\n\ |
| 13713 | -xgot assume a 32 bit GOT\n\ |
| 13714 | -mabi=ABI create ABI conformant object file for:\n")); |
| 13715 | |
| 13716 | first = 1; |
| 13717 | |
| 13718 | show (stream, "32", &column, &first); |
| 13719 | show (stream, "o64", &column, &first); |
| 13720 | show (stream, "n32", &column, &first); |
| 13721 | show (stream, "64", &column, &first); |
| 13722 | show (stream, "eabi", &column, &first); |
| 13723 | |
| 13724 | fputc ('\n', stream); |
| 13725 | |
| 13726 | fprintf (stream, _("\ |
| 13727 | -32 create o32 ABI object file (default)\n\ |
| 13728 | -n32 create n32 ABI object file\n\ |
| 13729 | -64 create 64 ABI object file\n")); |
| 13730 | #endif |
| 13731 | } |