| 1 | /* tc-sparc.c -- Assemble for the SPARC |
| 2 | Copyright (C) 1989-2019 Free Software Foundation, Inc. |
| 3 | This file is part of GAS, the GNU Assembler. |
| 4 | |
| 5 | GAS is free software; you can redistribute it and/or modify |
| 6 | it under the terms of the GNU General Public License as published by |
| 7 | the Free Software Foundation; either version 3, or (at your option) |
| 8 | any later version. |
| 9 | |
| 10 | GAS is distributed in the hope that it will be useful, |
| 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | GNU General Public License for more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public |
| 16 | License along with GAS; see the file COPYING. If not, write |
| 17 | to the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
| 18 | Boston, MA 02110-1301, USA. */ |
| 19 | |
| 20 | #include "as.h" |
| 21 | #include "safe-ctype.h" |
| 22 | #include "subsegs.h" |
| 23 | |
| 24 | #include "opcode/sparc.h" |
| 25 | #include "dw2gencfi.h" |
| 26 | |
| 27 | #include "elf/sparc.h" |
| 28 | #include "dwarf2dbg.h" |
| 29 | |
| 30 | /* Some ancient Sun C compilers would not take such hex constants as |
| 31 | unsigned, and would end up sign-extending them to form an offsetT, |
| 32 | so use these constants instead. */ |
| 33 | #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1) |
| 34 | #define U0x80000000 ((((unsigned long) 1 << 16) << 15)) |
| 35 | |
| 36 | static int sparc_ip (char *, const struct sparc_opcode **); |
| 37 | static int parse_sparc_asi (char **, const sparc_asi **); |
| 38 | static int parse_keyword_arg (int (*) (const char *), char **, int *); |
| 39 | static int parse_const_expr_arg (char **, int *); |
| 40 | static int get_expression (char *); |
| 41 | |
| 42 | /* Default architecture. */ |
| 43 | /* ??? The default value should be V8, but sparclite support was added |
| 44 | by making it the default. GCC now passes -Asparclite, so maybe sometime in |
| 45 | the future we can set this to V8. */ |
| 46 | #ifndef DEFAULT_ARCH |
| 47 | #define DEFAULT_ARCH "sparclite" |
| 48 | #endif |
| 49 | static const char *default_arch = DEFAULT_ARCH; |
| 50 | |
| 51 | /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size' |
| 52 | have been set. */ |
| 53 | static int default_init_p; |
| 54 | |
| 55 | /* Current architecture. We don't bump up unless necessary. */ |
| 56 | static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6; |
| 57 | |
| 58 | /* The maximum architecture level we can bump up to. |
| 59 | In a 32 bit environment, don't allow bumping up to v9 by default. |
| 60 | The native assembler works this way. The user is required to pass |
| 61 | an explicit argument before we'll create v9 object files. However, if |
| 62 | we don't see any v9 insns, a v8plus object file is not created. */ |
| 63 | static enum sparc_opcode_arch_val max_architecture; |
| 64 | |
| 65 | /* Either 32 or 64, selects file format. */ |
| 66 | static int sparc_arch_size; |
| 67 | /* Initial (default) value, recorded separately in case a user option |
| 68 | changes the value before md_show_usage is called. */ |
| 69 | static int default_arch_size; |
| 70 | |
| 71 | /* The currently selected v9 memory model. Currently only used for |
| 72 | ELF. */ |
| 73 | static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO; |
| 74 | |
| 75 | #ifndef TE_SOLARIS |
| 76 | /* Bitmask of instruction types seen so far, used to populate the |
| 77 | GNU attributes section with hwcap information. */ |
| 78 | static bfd_uint64_t hwcap_seen; |
| 79 | #endif |
| 80 | |
| 81 | static bfd_uint64_t hwcap_allowed; |
| 82 | |
| 83 | static int architecture_requested; |
| 84 | static int warn_on_bump; |
| 85 | |
| 86 | /* If warn_on_bump and the needed architecture is higher than this |
| 87 | architecture, issue a warning. */ |
| 88 | static enum sparc_opcode_arch_val warn_after_architecture; |
| 89 | |
| 90 | /* Non-zero if the assembler should generate error if an undeclared |
| 91 | g[23] register has been used in -64. */ |
| 92 | static int no_undeclared_regs; |
| 93 | |
| 94 | /* Non-zero if the assembler should generate a warning if an |
| 95 | unpredictable DCTI (delayed control transfer instruction) couple is |
| 96 | found. */ |
| 97 | static int dcti_couples_detect; |
| 98 | |
| 99 | /* Non-zero if we should try to relax jumps and calls. */ |
| 100 | static int sparc_relax; |
| 101 | |
| 102 | /* Non-zero if we are generating PIC code. */ |
| 103 | int sparc_pic_code; |
| 104 | |
| 105 | /* Non-zero if we should give an error when misaligned data is seen. */ |
| 106 | static int enforce_aligned_data; |
| 107 | |
| 108 | extern int target_big_endian; |
| 109 | |
| 110 | static int target_little_endian_data; |
| 111 | |
| 112 | /* Symbols for global registers on v9. */ |
| 113 | static symbolS *globals[8]; |
| 114 | |
| 115 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ |
| 116 | int sparc_cie_data_alignment; |
| 117 | |
| 118 | /* V9 and 86x have big and little endian data, but instructions are always big |
| 119 | endian. The sparclet has bi-endian support but both data and insns have |
| 120 | the same endianness. Global `target_big_endian' is used for data. |
| 121 | The following macro is used for instructions. */ |
| 122 | #ifndef INSN_BIG_ENDIAN |
| 123 | #define INSN_BIG_ENDIAN (target_big_endian \ |
| 124 | || default_arch_type == sparc86x \ |
| 125 | || SPARC_OPCODE_ARCH_V9_P (max_architecture)) |
| 126 | #endif |
| 127 | |
| 128 | /* Handle of the OPCODE hash table. */ |
| 129 | static struct hash_control *op_hash; |
| 130 | |
| 131 | static void s_data1 (void); |
| 132 | static void s_seg (int); |
| 133 | static void s_proc (int); |
| 134 | static void s_reserve (int); |
| 135 | static void s_common (int); |
| 136 | static void s_empty (int); |
| 137 | static void s_uacons (int); |
| 138 | static void s_ncons (int); |
| 139 | static void s_register (int); |
| 140 | |
| 141 | const pseudo_typeS md_pseudo_table[] = |
| 142 | { |
| 143 | {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */ |
| 144 | {"common", s_common, 0}, |
| 145 | {"empty", s_empty, 0}, |
| 146 | {"global", s_globl, 0}, |
| 147 | {"half", cons, 2}, |
| 148 | {"nword", s_ncons, 0}, |
| 149 | {"optim", s_ignore, 0}, |
| 150 | {"proc", s_proc, 0}, |
| 151 | {"reserve", s_reserve, 0}, |
| 152 | {"seg", s_seg, 0}, |
| 153 | {"skip", s_space, 0}, |
| 154 | {"word", cons, 4}, |
| 155 | {"xword", cons, 8}, |
| 156 | {"uahalf", s_uacons, 2}, |
| 157 | {"uaword", s_uacons, 4}, |
| 158 | {"uaxword", s_uacons, 8}, |
| 159 | /* These are specific to sparc/svr4. */ |
| 160 | {"2byte", s_uacons, 2}, |
| 161 | {"4byte", s_uacons, 4}, |
| 162 | {"8byte", s_uacons, 8}, |
| 163 | {"register", s_register, 0}, |
| 164 | {NULL, 0, 0}, |
| 165 | }; |
| 166 | |
| 167 | /* This array holds the chars that always start a comment. If the |
| 168 | pre-processor is disabled, these aren't very useful. */ |
| 169 | const char comment_chars[] = "!"; /* JF removed '|' from |
| 170 | comment_chars. */ |
| 171 | |
| 172 | /* This array holds the chars that only start a comment at the beginning of |
| 173 | a line. If the line seems to have the form '# 123 filename' |
| 174 | .line and .file directives will appear in the pre-processed output. */ |
| 175 | /* Note that input_file.c hand checks for '#' at the beginning of the |
| 176 | first line of the input file. This is because the compiler outputs |
| 177 | #NO_APP at the beginning of its output. */ |
| 178 | /* Also note that comments started like this one will always |
| 179 | work if '/' isn't otherwise defined. */ |
| 180 | const char line_comment_chars[] = "#"; |
| 181 | |
| 182 | const char line_separator_chars[] = ";"; |
| 183 | |
| 184 | /* Chars that can be used to separate mant from exp in floating point |
| 185 | nums. */ |
| 186 | const char EXP_CHARS[] = "eE"; |
| 187 | |
| 188 | /* Chars that mean this number is a floating point constant. |
| 189 | As in 0f12.456 |
| 190 | or 0d1.2345e12 */ |
| 191 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
| 192 | |
| 193 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be |
| 194 | changed in read.c. Ideally it shouldn't have to know about it at all, |
| 195 | but nothing is ideal around here. */ |
| 196 | |
| 197 | #define isoctal(c) ((unsigned) ((c) - '0') < 8) |
| 198 | |
| 199 | struct sparc_it |
| 200 | { |
| 201 | const char *error; |
| 202 | unsigned long opcode; |
| 203 | struct nlist *nlistp; |
| 204 | expressionS exp; |
| 205 | expressionS exp2; |
| 206 | int pcrel; |
| 207 | bfd_reloc_code_real_type reloc; |
| 208 | }; |
| 209 | |
| 210 | struct sparc_it the_insn, set_insn; |
| 211 | |
| 212 | static void output_insn (const struct sparc_opcode *, struct sparc_it *); |
| 213 | \f |
| 214 | /* Table of arguments to -A. |
| 215 | The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect |
| 216 | for this use. That table is for opcodes only. This table is for opcodes |
| 217 | and file formats. */ |
| 218 | |
| 219 | enum sparc_arch_types {v6, v7, v8, leon, sparclet, sparclite, sparc86x, v8plus, |
| 220 | v8plusa, v9, v9a, v9b, v9_64}; |
| 221 | |
| 222 | static struct sparc_arch { |
| 223 | const char *name; |
| 224 | const char *opcode_arch; |
| 225 | enum sparc_arch_types arch_type; |
| 226 | /* Default word size, as specified during configuration. |
| 227 | A value of zero means can't be used to specify default architecture. */ |
| 228 | int default_arch_size; |
| 229 | /* Allowable arg to -A? */ |
| 230 | int user_option_p; |
| 231 | /* Extra hardware capabilities allowed. These are added to the |
| 232 | hardware capabilities associated with the opcode |
| 233 | architecture. */ |
| 234 | int hwcap_allowed; |
| 235 | int hwcap2_allowed; |
| 236 | } sparc_arch_table[] = { |
| 237 | { "v6", "v6", v6, 0, 1, 0, 0 }, |
| 238 | { "v7", "v7", v7, 0, 1, 0, 0 }, |
| 239 | { "v8", "v8", v8, 32, 1, 0, 0 }, |
| 240 | { "v8a", "v8", v8, 32, 1, 0, 0 }, |
| 241 | { "sparc", "v9", v9, 0, 1, HWCAP_V8PLUS, 0 }, |
| 242 | { "sparcvis", "v9a", v9, 0, 1, 0, 0 }, |
| 243 | { "sparcvis2", "v9b", v9, 0, 1, 0, 0 }, |
| 244 | { "sparcfmaf", "v9b", v9, 0, 1, HWCAP_FMAF, 0 }, |
| 245 | { "sparcima", "v9b", v9, 0, 1, HWCAP_FMAF|HWCAP_IMA, 0 }, |
| 246 | { "sparcvis3", "v9b", v9, 0, 1, HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC, 0 }, |
| 247 | { "sparcvis3r", "v9b", v9, 0, 1, HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_FJFMAU, 0 }, |
| 248 | |
| 249 | { "sparc4", "v9v", v9, 0, 1, 0, 0 }, |
| 250 | { "sparc5", "v9m", v9, 0, 1, 0, 0 }, |
| 251 | { "sparc6", "m8", v9, 0, 1, 0, 0 }, |
| 252 | |
| 253 | { "leon", "leon", leon, 32, 1, 0, 0 }, |
| 254 | { "sparclet", "sparclet", sparclet, 32, 1, 0, 0 }, |
| 255 | { "sparclite", "sparclite", sparclite, 32, 1, 0, 0 }, |
| 256 | { "sparc86x", "sparclite", sparc86x, 32, 1, 0, 0 }, |
| 257 | |
| 258 | { "v8plus", "v9", v9, 0, 1, HWCAP_V8PLUS, 0 }, |
| 259 | { "v8plusa", "v9a", v9, 0, 1, HWCAP_V8PLUS, 0 }, |
| 260 | { "v8plusb", "v9b", v9, 0, 1, HWCAP_V8PLUS, 0 }, |
| 261 | { "v8plusc", "v9c", v9, 0, 1, HWCAP_V8PLUS, 0 }, |
| 262 | { "v8plusd", "v9d", v9, 0, 1, HWCAP_V8PLUS, 0 }, |
| 263 | { "v8pluse", "v9e", v9, 0, 1, HWCAP_V8PLUS, 0 }, |
| 264 | { "v8plusv", "v9v", v9, 0, 1, HWCAP_V8PLUS, 0 }, |
| 265 | { "v8plusm", "v9m", v9, 0, 1, HWCAP_V8PLUS, 0 }, |
| 266 | { "v8plusm8", "m8", v9, 0, 1, HWCAP_V8PLUS, 0 }, |
| 267 | |
| 268 | { "v9", "v9", v9, 0, 1, 0, 0 }, |
| 269 | { "v9a", "v9a", v9, 0, 1, 0, 0 }, |
| 270 | { "v9b", "v9b", v9, 0, 1, 0, 0 }, |
| 271 | { "v9c", "v9c", v9, 0, 1, 0, 0 }, |
| 272 | { "v9d", "v9d", v9, 0, 1, 0, 0 }, |
| 273 | { "v9e", "v9e", v9, 0, 1, 0, 0 }, |
| 274 | { "v9v", "v9v", v9, 0, 1, 0, 0 }, |
| 275 | { "v9m", "v9m", v9, 0, 1, 0, 0 }, |
| 276 | { "v9m8", "m8", v9, 0, 1, 0, 0 }, |
| 277 | |
| 278 | /* This exists to allow configure.tgt to pass one |
| 279 | value to specify both the default machine and default word size. */ |
| 280 | { "v9-64", "v9", v9, 64, 0, 0, 0 }, |
| 281 | { NULL, NULL, v8, 0, 0, 0, 0 } |
| 282 | }; |
| 283 | |
| 284 | /* Variant of default_arch */ |
| 285 | static enum sparc_arch_types default_arch_type; |
| 286 | |
| 287 | static struct sparc_arch * |
| 288 | lookup_arch (const char *name) |
| 289 | { |
| 290 | struct sparc_arch *sa; |
| 291 | |
| 292 | for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++) |
| 293 | if (strcmp (sa->name, name) == 0) |
| 294 | break; |
| 295 | if (sa->name == NULL) |
| 296 | return NULL; |
| 297 | return sa; |
| 298 | } |
| 299 | |
| 300 | /* Initialize the default opcode arch and word size from the default |
| 301 | architecture name. */ |
| 302 | |
| 303 | static void |
| 304 | init_default_arch (void) |
| 305 | { |
| 306 | struct sparc_arch *sa = lookup_arch (default_arch); |
| 307 | |
| 308 | if (sa == NULL |
| 309 | || sa->default_arch_size == 0) |
| 310 | as_fatal (_("Invalid default architecture, broken assembler.")); |
| 311 | |
| 312 | max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch); |
| 313 | if (max_architecture == SPARC_OPCODE_ARCH_BAD) |
| 314 | as_fatal (_("Bad opcode table, broken assembler.")); |
| 315 | default_arch_size = sparc_arch_size = sa->default_arch_size; |
| 316 | default_init_p = 1; |
| 317 | default_arch_type = sa->arch_type; |
| 318 | } |
| 319 | |
| 320 | /* Called by TARGET_MACH. */ |
| 321 | |
| 322 | unsigned long |
| 323 | sparc_mach (void) |
| 324 | { |
| 325 | /* We don't get a chance to initialize anything before we're called, |
| 326 | so handle that now. */ |
| 327 | if (! default_init_p) |
| 328 | init_default_arch (); |
| 329 | |
| 330 | return sparc_arch_size == 64 ? bfd_mach_sparc_v9 : bfd_mach_sparc; |
| 331 | } |
| 332 | |
| 333 | /* Called by TARGET_FORMAT. */ |
| 334 | |
| 335 | const char * |
| 336 | sparc_target_format (void) |
| 337 | { |
| 338 | /* We don't get a chance to initialize anything before we're called, |
| 339 | so handle that now. */ |
| 340 | if (! default_init_p) |
| 341 | init_default_arch (); |
| 342 | |
| 343 | #ifdef TE_VXWORKS |
| 344 | return "elf32-sparc-vxworks"; |
| 345 | #endif |
| 346 | |
| 347 | return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT; |
| 348 | } |
| 349 | \f |
| 350 | /* md_parse_option |
| 351 | * Invocation line includes a switch not recognized by the base assembler. |
| 352 | * See if it's a processor-specific option. These are: |
| 353 | * |
| 354 | * -bump |
| 355 | * Warn on architecture bumps. See also -A. |
| 356 | * |
| 357 | * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet |
| 358 | * Standard 32 bit architectures. |
| 359 | * -Av9, -Av9a, -Av9b |
| 360 | * Sparc64 in either a 32 or 64 bit world (-32/-64 says which). |
| 361 | * This used to only mean 64 bits, but properly specifying it |
| 362 | * complicated gcc's ASM_SPECs, so now opcode selection is |
| 363 | * specified orthogonally to word size (except when specifying |
| 364 | * the default, but that is an internal implementation detail). |
| 365 | * -Av8plus, -Av8plusa, -Av8plusb |
| 366 | * Same as -Av9{,a,b}. |
| 367 | * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb |
| 368 | * Same as -Av8plus{,a,b} -32, for compatibility with Sun's |
| 369 | * assembler. |
| 370 | * -xarch=v9, -xarch=v9a, -xarch=v9b |
| 371 | * Same as -Av9{,a,b} -64, for compatibility with Sun's |
| 372 | * assembler. |
| 373 | * |
| 374 | * Select the architecture and possibly the file format. |
| 375 | * Instructions or features not supported by the selected |
| 376 | * architecture cause fatal errors. |
| 377 | * |
| 378 | * The default is to start at v6, and bump the architecture up |
| 379 | * whenever an instruction is seen at a higher level. In 32 bit |
| 380 | * environments, v9 is not bumped up to, the user must pass |
| 381 | * -Av8plus{,a,b}. |
| 382 | * |
| 383 | * If -bump is specified, a warning is printing when bumping to |
| 384 | * higher levels. |
| 385 | * |
| 386 | * If an architecture is specified, all instructions must match |
| 387 | * that architecture. Any higher level instructions are flagged |
| 388 | * as errors. Note that in the 32 bit environment specifying |
| 389 | * -Av8plus does not automatically create a v8plus object file, a |
| 390 | * v9 insn must be seen. |
| 391 | * |
| 392 | * If both an architecture and -bump are specified, the |
| 393 | * architecture starts at the specified level, but bumps are |
| 394 | * warnings. Note that we can't set `current_architecture' to |
| 395 | * the requested level in this case: in the 32 bit environment, |
| 396 | * we still must avoid creating v8plus object files unless v9 |
| 397 | * insns are seen. |
| 398 | * |
| 399 | * Note: |
| 400 | * Bumping between incompatible architectures is always an |
| 401 | * error. For example, from sparclite to v9. |
| 402 | */ |
| 403 | |
| 404 | const char *md_shortopts = "A:K:VQ:sq"; |
| 405 | struct option md_longopts[] = { |
| 406 | #define OPTION_BUMP (OPTION_MD_BASE) |
| 407 | {"bump", no_argument, NULL, OPTION_BUMP}, |
| 408 | #define OPTION_SPARC (OPTION_MD_BASE + 1) |
| 409 | {"sparc", no_argument, NULL, OPTION_SPARC}, |
| 410 | #define OPTION_XARCH (OPTION_MD_BASE + 2) |
| 411 | {"xarch", required_argument, NULL, OPTION_XARCH}, |
| 412 | #define OPTION_32 (OPTION_MD_BASE + 3) |
| 413 | {"32", no_argument, NULL, OPTION_32}, |
| 414 | #define OPTION_64 (OPTION_MD_BASE + 4) |
| 415 | {"64", no_argument, NULL, OPTION_64}, |
| 416 | #define OPTION_TSO (OPTION_MD_BASE + 5) |
| 417 | {"TSO", no_argument, NULL, OPTION_TSO}, |
| 418 | #define OPTION_PSO (OPTION_MD_BASE + 6) |
| 419 | {"PSO", no_argument, NULL, OPTION_PSO}, |
| 420 | #define OPTION_RMO (OPTION_MD_BASE + 7) |
| 421 | {"RMO", no_argument, NULL, OPTION_RMO}, |
| 422 | #ifdef SPARC_BIENDIAN |
| 423 | #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8) |
| 424 | {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN}, |
| 425 | #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9) |
| 426 | {"EB", no_argument, NULL, OPTION_BIG_ENDIAN}, |
| 427 | #endif |
| 428 | #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10) |
| 429 | {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA}, |
| 430 | #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11) |
| 431 | {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA}, |
| 432 | #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12) |
| 433 | {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS}, |
| 434 | #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13) |
| 435 | {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS}, |
| 436 | #define OPTION_RELAX (OPTION_MD_BASE + 14) |
| 437 | {"relax", no_argument, NULL, OPTION_RELAX}, |
| 438 | #define OPTION_NO_RELAX (OPTION_MD_BASE + 15) |
| 439 | {"no-relax", no_argument, NULL, OPTION_NO_RELAX}, |
| 440 | #define OPTION_DCTI_COUPLES_DETECT (OPTION_MD_BASE + 16) |
| 441 | {"dcti-couples-detect", no_argument, NULL, OPTION_DCTI_COUPLES_DETECT}, |
| 442 | {NULL, no_argument, NULL, 0} |
| 443 | }; |
| 444 | |
| 445 | size_t md_longopts_size = sizeof (md_longopts); |
| 446 | |
| 447 | int |
| 448 | md_parse_option (int c, const char *arg) |
| 449 | { |
| 450 | /* We don't get a chance to initialize anything before we're called, |
| 451 | so handle that now. */ |
| 452 | if (! default_init_p) |
| 453 | init_default_arch (); |
| 454 | |
| 455 | switch (c) |
| 456 | { |
| 457 | case OPTION_BUMP: |
| 458 | warn_on_bump = 1; |
| 459 | warn_after_architecture = SPARC_OPCODE_ARCH_V6; |
| 460 | break; |
| 461 | |
| 462 | case OPTION_XARCH: |
| 463 | if (!strncmp (arg, "v9", 2)) |
| 464 | md_parse_option (OPTION_64, NULL); |
| 465 | else |
| 466 | { |
| 467 | if (!strncmp (arg, "v8", 2) |
| 468 | || !strncmp (arg, "v7", 2) |
| 469 | || !strncmp (arg, "v6", 2) |
| 470 | || !strcmp (arg, "sparclet") |
| 471 | || !strcmp (arg, "sparclite") |
| 472 | || !strcmp (arg, "sparc86x")) |
| 473 | md_parse_option (OPTION_32, NULL); |
| 474 | } |
| 475 | /* Fall through. */ |
| 476 | |
| 477 | case 'A': |
| 478 | { |
| 479 | struct sparc_arch *sa; |
| 480 | enum sparc_opcode_arch_val opcode_arch; |
| 481 | |
| 482 | sa = lookup_arch (arg); |
| 483 | if (sa == NULL |
| 484 | || ! sa->user_option_p) |
| 485 | { |
| 486 | if (c == OPTION_XARCH) |
| 487 | as_bad (_("invalid architecture -xarch=%s"), arg); |
| 488 | else |
| 489 | as_bad (_("invalid architecture -A%s"), arg); |
| 490 | return 0; |
| 491 | } |
| 492 | |
| 493 | opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch); |
| 494 | if (opcode_arch == SPARC_OPCODE_ARCH_BAD) |
| 495 | as_fatal (_("Bad opcode table, broken assembler.")); |
| 496 | |
| 497 | if (!architecture_requested |
| 498 | || opcode_arch > max_architecture) |
| 499 | max_architecture = opcode_arch; |
| 500 | |
| 501 | /* The allowed hardware capabilities are the implied by the |
| 502 | opcodes arch plus any extra capabilities defined in the GAS |
| 503 | arch. */ |
| 504 | hwcap_allowed |
| 505 | = (hwcap_allowed |
| 506 | | (((bfd_uint64_t) sparc_opcode_archs[opcode_arch].hwcaps2) << 32) |
| 507 | | (((bfd_uint64_t) sa->hwcap2_allowed) << 32) |
| 508 | | sparc_opcode_archs[opcode_arch].hwcaps |
| 509 | | sa->hwcap_allowed); |
| 510 | architecture_requested = 1; |
| 511 | } |
| 512 | break; |
| 513 | |
| 514 | case OPTION_SPARC: |
| 515 | /* Ignore -sparc, used by SunOS make default .s.o rule. */ |
| 516 | break; |
| 517 | |
| 518 | case OPTION_ENFORCE_ALIGNED_DATA: |
| 519 | enforce_aligned_data = 1; |
| 520 | break; |
| 521 | |
| 522 | #ifdef SPARC_BIENDIAN |
| 523 | case OPTION_LITTLE_ENDIAN: |
| 524 | target_big_endian = 0; |
| 525 | if (default_arch_type != sparclet) |
| 526 | as_fatal ("This target does not support -EL"); |
| 527 | break; |
| 528 | case OPTION_LITTLE_ENDIAN_DATA: |
| 529 | target_little_endian_data = 1; |
| 530 | target_big_endian = 0; |
| 531 | if (default_arch_type != sparc86x |
| 532 | && default_arch_type != v9) |
| 533 | as_fatal ("This target does not support --little-endian-data"); |
| 534 | break; |
| 535 | case OPTION_BIG_ENDIAN: |
| 536 | target_big_endian = 1; |
| 537 | break; |
| 538 | #endif |
| 539 | |
| 540 | case OPTION_32: |
| 541 | case OPTION_64: |
| 542 | { |
| 543 | const char **list, **l; |
| 544 | |
| 545 | sparc_arch_size = c == OPTION_32 ? 32 : 64; |
| 546 | list = bfd_target_list (); |
| 547 | for (l = list; *l != NULL; l++) |
| 548 | { |
| 549 | if (sparc_arch_size == 32) |
| 550 | { |
| 551 | if (CONST_STRNEQ (*l, "elf32-sparc")) |
| 552 | break; |
| 553 | } |
| 554 | else |
| 555 | { |
| 556 | if (CONST_STRNEQ (*l, "elf64-sparc")) |
| 557 | break; |
| 558 | } |
| 559 | } |
| 560 | if (*l == NULL) |
| 561 | as_fatal (_("No compiled in support for %d bit object file format"), |
| 562 | sparc_arch_size); |
| 563 | free (list); |
| 564 | |
| 565 | if (sparc_arch_size == 64 |
| 566 | && max_architecture < SPARC_OPCODE_ARCH_V9) |
| 567 | max_architecture = SPARC_OPCODE_ARCH_V9; |
| 568 | } |
| 569 | break; |
| 570 | |
| 571 | case OPTION_TSO: |
| 572 | sparc_memory_model = MM_TSO; |
| 573 | break; |
| 574 | |
| 575 | case OPTION_PSO: |
| 576 | sparc_memory_model = MM_PSO; |
| 577 | break; |
| 578 | |
| 579 | case OPTION_RMO: |
| 580 | sparc_memory_model = MM_RMO; |
| 581 | break; |
| 582 | |
| 583 | case 'V': |
| 584 | print_version_id (); |
| 585 | break; |
| 586 | |
| 587 | case 'Q': |
| 588 | /* Qy - do emit .comment |
| 589 | Qn - do not emit .comment. */ |
| 590 | break; |
| 591 | |
| 592 | case 's': |
| 593 | /* Use .stab instead of .stab.excl. */ |
| 594 | break; |
| 595 | |
| 596 | case 'q': |
| 597 | /* quick -- Native assembler does fewer checks. */ |
| 598 | break; |
| 599 | |
| 600 | case 'K': |
| 601 | if (strcmp (arg, "PIC") != 0) |
| 602 | as_warn (_("Unrecognized option following -K")); |
| 603 | else |
| 604 | sparc_pic_code = 1; |
| 605 | break; |
| 606 | |
| 607 | case OPTION_NO_UNDECLARED_REGS: |
| 608 | no_undeclared_regs = 1; |
| 609 | break; |
| 610 | |
| 611 | case OPTION_UNDECLARED_REGS: |
| 612 | no_undeclared_regs = 0; |
| 613 | break; |
| 614 | |
| 615 | case OPTION_RELAX: |
| 616 | sparc_relax = 1; |
| 617 | break; |
| 618 | |
| 619 | case OPTION_NO_RELAX: |
| 620 | sparc_relax = 0; |
| 621 | break; |
| 622 | |
| 623 | case OPTION_DCTI_COUPLES_DETECT: |
| 624 | dcti_couples_detect = 1; |
| 625 | break; |
| 626 | |
| 627 | default: |
| 628 | return 0; |
| 629 | } |
| 630 | |
| 631 | return 1; |
| 632 | } |
| 633 | |
| 634 | void |
| 635 | md_show_usage (FILE *stream) |
| 636 | { |
| 637 | const struct sparc_arch *arch; |
| 638 | int column; |
| 639 | |
| 640 | /* We don't get a chance to initialize anything before we're called, |
| 641 | so handle that now. */ |
| 642 | if (! default_init_p) |
| 643 | init_default_arch (); |
| 644 | |
| 645 | fprintf (stream, _("SPARC options:\n")); |
| 646 | column = 0; |
| 647 | for (arch = &sparc_arch_table[0]; arch->name; arch++) |
| 648 | { |
| 649 | if (!arch->user_option_p) |
| 650 | continue; |
| 651 | if (arch != &sparc_arch_table[0]) |
| 652 | fprintf (stream, " | "); |
| 653 | if (column + strlen (arch->name) > 70) |
| 654 | { |
| 655 | column = 0; |
| 656 | fputc ('\n', stream); |
| 657 | } |
| 658 | column += 5 + 2 + strlen (arch->name); |
| 659 | fprintf (stream, "-A%s", arch->name); |
| 660 | } |
| 661 | for (arch = &sparc_arch_table[0]; arch->name; arch++) |
| 662 | { |
| 663 | if (!arch->user_option_p) |
| 664 | continue; |
| 665 | fprintf (stream, " | "); |
| 666 | if (column + strlen (arch->name) > 65) |
| 667 | { |
| 668 | column = 0; |
| 669 | fputc ('\n', stream); |
| 670 | } |
| 671 | column += 5 + 7 + strlen (arch->name); |
| 672 | fprintf (stream, "-xarch=%s", arch->name); |
| 673 | } |
| 674 | fprintf (stream, _("\n\ |
| 675 | specify variant of SPARC architecture\n\ |
| 676 | -bump warn when assembler switches architectures\n\ |
| 677 | -sparc ignored\n\ |
| 678 | --enforce-aligned-data force .long, etc., to be aligned correctly\n\ |
| 679 | -relax relax jumps and branches (default)\n\ |
| 680 | -no-relax avoid changing any jumps and branches\n")); |
| 681 | fprintf (stream, _("\ |
| 682 | -32 create 32 bit object file\n\ |
| 683 | -64 create 64 bit object file\n")); |
| 684 | fprintf (stream, _("\ |
| 685 | [default is %d]\n"), default_arch_size); |
| 686 | fprintf (stream, _("\ |
| 687 | -TSO use Total Store Ordering\n\ |
| 688 | -PSO use Partial Store Ordering\n\ |
| 689 | -RMO use Relaxed Memory Ordering\n")); |
| 690 | fprintf (stream, _("\ |
| 691 | [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO"); |
| 692 | fprintf (stream, _("\ |
| 693 | -KPIC generate PIC\n\ |
| 694 | -V print assembler version number\n\ |
| 695 | -undeclared-regs ignore application global register usage without\n\ |
| 696 | appropriate .register directive (default)\n\ |
| 697 | -no-undeclared-regs force error on application global register usage\n\ |
| 698 | without appropriate .register directive\n\ |
| 699 | --dcti-couples-detect warn when an unpredictable DCTI couple is found\n\ |
| 700 | -q ignored\n\ |
| 701 | -Qy, -Qn ignored\n\ |
| 702 | -s ignored\n")); |
| 703 | #ifdef SPARC_BIENDIAN |
| 704 | fprintf (stream, _("\ |
| 705 | -EL generate code for a little endian machine\n\ |
| 706 | -EB generate code for a big endian machine\n\ |
| 707 | --little-endian-data generate code for a machine having big endian\n\ |
| 708 | instructions and little endian data.\n")); |
| 709 | #endif |
| 710 | } |
| 711 | \f |
| 712 | /* Native operand size opcode translation. */ |
| 713 | static struct |
| 714 | { |
| 715 | const char *name; |
| 716 | const char *name32; |
| 717 | const char *name64; |
| 718 | } native_op_table[] = |
| 719 | { |
| 720 | {"ldn", "ld", "ldx"}, |
| 721 | {"ldna", "lda", "ldxa"}, |
| 722 | {"stn", "st", "stx"}, |
| 723 | {"stna", "sta", "stxa"}, |
| 724 | {"slln", "sll", "sllx"}, |
| 725 | {"srln", "srl", "srlx"}, |
| 726 | {"sran", "sra", "srax"}, |
| 727 | {"casn", "cas", "casx"}, |
| 728 | {"casna", "casa", "casxa"}, |
| 729 | {"clrn", "clr", "clrx"}, |
| 730 | {NULL, NULL, NULL}, |
| 731 | }; |
| 732 | \f |
| 733 | /* sparc64 privileged and hyperprivileged registers. */ |
| 734 | |
| 735 | struct priv_reg_entry |
| 736 | { |
| 737 | const char *name; |
| 738 | int regnum; |
| 739 | }; |
| 740 | |
| 741 | struct priv_reg_entry priv_reg_table[] = |
| 742 | { |
| 743 | {"tpc", 0}, |
| 744 | {"tnpc", 1}, |
| 745 | {"tstate", 2}, |
| 746 | {"tt", 3}, |
| 747 | {"tick", 4}, |
| 748 | {"tba", 5}, |
| 749 | {"pstate", 6}, |
| 750 | {"tl", 7}, |
| 751 | {"pil", 8}, |
| 752 | {"cwp", 9}, |
| 753 | {"cansave", 10}, |
| 754 | {"canrestore", 11}, |
| 755 | {"cleanwin", 12}, |
| 756 | {"otherwin", 13}, |
| 757 | {"wstate", 14}, |
| 758 | {"fq", 15}, |
| 759 | {"gl", 16}, |
| 760 | {"pmcdper", 23}, |
| 761 | {"ver", 31}, |
| 762 | {NULL, -1}, /* End marker. */ |
| 763 | }; |
| 764 | |
| 765 | struct priv_reg_entry hpriv_reg_table[] = |
| 766 | { |
| 767 | {"hpstate", 0}, |
| 768 | {"htstate", 1}, |
| 769 | {"hintp", 3}, |
| 770 | {"htba", 5}, |
| 771 | {"hver", 6}, |
| 772 | {"hmcdper", 23}, |
| 773 | {"hmcddfr", 24}, |
| 774 | {"hva_mask_nz", 27}, |
| 775 | {"hstick_offset", 28}, |
| 776 | {"hstick_enable", 29}, |
| 777 | {"hstick_cmpr", 31}, |
| 778 | {NULL, -1}, /* End marker. */ |
| 779 | }; |
| 780 | |
| 781 | /* v9a or later specific ancillary state registers. */ |
| 782 | |
| 783 | struct priv_reg_entry v9a_asr_table[] = |
| 784 | { |
| 785 | {"tick_cmpr", 23}, |
| 786 | {"sys_tick_cmpr", 25}, |
| 787 | {"sys_tick", 24}, |
| 788 | {"stick_cmpr", 25}, |
| 789 | {"stick", 24}, |
| 790 | {"softint_clear", 21}, |
| 791 | {"softint_set", 20}, |
| 792 | {"softint", 22}, |
| 793 | {"set_softint", 20}, |
| 794 | {"pause", 27}, |
| 795 | {"pic", 17}, |
| 796 | {"pcr", 16}, |
| 797 | {"mwait", 28}, |
| 798 | {"gsr", 19}, |
| 799 | {"dcr", 18}, |
| 800 | {"cfr", 26}, |
| 801 | {"clear_softint", 21}, |
| 802 | {NULL, -1}, /* End marker. */ |
| 803 | }; |
| 804 | |
| 805 | static int |
| 806 | cmp_reg_entry (const void *parg, const void *qarg) |
| 807 | { |
| 808 | const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg; |
| 809 | const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg; |
| 810 | |
| 811 | if (p->name == q->name) |
| 812 | return 0; |
| 813 | else if (p->name == NULL) |
| 814 | return 1; |
| 815 | else if (q->name == NULL) |
| 816 | return -1; |
| 817 | else |
| 818 | return strcmp (q->name, p->name); |
| 819 | } |
| 820 | \f |
| 821 | /* sparc %-pseudo-operations. */ |
| 822 | |
| 823 | |
| 824 | #define F_POP_V9 0x1 /* The pseudo-op is for v9 only. */ |
| 825 | #define F_POP_PCREL 0x2 /* The pseudo-op can be used in pc-relative |
| 826 | contexts. */ |
| 827 | #define F_POP_TLS_CALL 0x4 /* The pseudo-op marks a tls call. */ |
| 828 | #define F_POP_POSTFIX 0x8 /* The pseudo-op should appear after the |
| 829 | last operand of an |
| 830 | instruction. (Generally they can appear |
| 831 | anywhere an immediate operand is |
| 832 | expected. */ |
| 833 | struct pop_entry |
| 834 | { |
| 835 | /* The name as it appears in assembler. */ |
| 836 | const char *name; |
| 837 | /* The reloc this pseudo-op translates to. */ |
| 838 | bfd_reloc_code_real_type reloc; |
| 839 | /* Flags. See F_POP_* above. */ |
| 840 | int flags; |
| 841 | }; |
| 842 | |
| 843 | struct pop_entry pop_table[] = |
| 844 | { |
| 845 | { "hix", BFD_RELOC_SPARC_HIX22, F_POP_V9 }, |
| 846 | { "lox", BFD_RELOC_SPARC_LOX10, F_POP_V9 }, |
| 847 | { "hi", BFD_RELOC_HI22, F_POP_PCREL }, |
| 848 | { "lo", BFD_RELOC_LO10, F_POP_PCREL }, |
| 849 | { "pc22", BFD_RELOC_SPARC_PC22, F_POP_PCREL }, |
| 850 | { "pc10", BFD_RELOC_SPARC_PC10, F_POP_PCREL }, |
| 851 | { "hh", BFD_RELOC_SPARC_HH22, F_POP_V9|F_POP_PCREL }, |
| 852 | { "hm", BFD_RELOC_SPARC_HM10, F_POP_V9|F_POP_PCREL }, |
| 853 | { "lm", BFD_RELOC_SPARC_LM22, F_POP_V9|F_POP_PCREL }, |
| 854 | { "h34", BFD_RELOC_SPARC_H34, F_POP_V9 }, |
| 855 | { "l34", BFD_RELOC_SPARC_L44, F_POP_V9 }, |
| 856 | { "h44", BFD_RELOC_SPARC_H44, F_POP_V9 }, |
| 857 | { "m44", BFD_RELOC_SPARC_M44, F_POP_V9 }, |
| 858 | { "l44", BFD_RELOC_SPARC_L44, F_POP_V9 }, |
| 859 | { "uhi", BFD_RELOC_SPARC_HH22, F_POP_V9 }, |
| 860 | { "ulo", BFD_RELOC_SPARC_HM10, F_POP_V9 }, |
| 861 | { "tgd_hi22", BFD_RELOC_SPARC_TLS_GD_HI22, 0 }, |
| 862 | { "tgd_lo10", BFD_RELOC_SPARC_TLS_GD_LO10, 0 }, |
| 863 | { "tldm_hi22", BFD_RELOC_SPARC_TLS_LDM_HI22, 0 }, |
| 864 | { "tldm_lo10", BFD_RELOC_SPARC_TLS_LDM_LO10, 0 }, |
| 865 | { "tldo_hix22", BFD_RELOC_SPARC_TLS_LDO_HIX22, 0 }, |
| 866 | { "tldo_lox10", BFD_RELOC_SPARC_TLS_LDO_LOX10, 0 }, |
| 867 | { "tie_hi22", BFD_RELOC_SPARC_TLS_IE_HI22, 0 }, |
| 868 | { "tie_lo10", BFD_RELOC_SPARC_TLS_IE_LO10, 0 }, |
| 869 | { "tle_hix22", BFD_RELOC_SPARC_TLS_LE_HIX22, 0 }, |
| 870 | { "tle_lox10", BFD_RELOC_SPARC_TLS_LE_LOX10, 0 }, |
| 871 | { "gdop_hix22", BFD_RELOC_SPARC_GOTDATA_OP_HIX22, 0 }, |
| 872 | { "gdop_lox10", BFD_RELOC_SPARC_GOTDATA_OP_LOX10, 0 }, |
| 873 | { "tgd_add", BFD_RELOC_SPARC_TLS_GD_ADD, F_POP_POSTFIX }, |
| 874 | { "tgd_call", BFD_RELOC_SPARC_TLS_GD_CALL, F_POP_POSTFIX|F_POP_TLS_CALL }, |
| 875 | { "tldm_add", BFD_RELOC_SPARC_TLS_LDM_ADD, F_POP_POSTFIX }, |
| 876 | { "tldm_call", BFD_RELOC_SPARC_TLS_LDM_CALL, F_POP_POSTFIX|F_POP_TLS_CALL }, |
| 877 | { "tldo_add", BFD_RELOC_SPARC_TLS_LDO_ADD, F_POP_POSTFIX }, |
| 878 | { "tie_ldx", BFD_RELOC_SPARC_TLS_IE_LDX, F_POP_POSTFIX }, |
| 879 | { "tie_ld", BFD_RELOC_SPARC_TLS_IE_LD, F_POP_POSTFIX }, |
| 880 | { "tie_add", BFD_RELOC_SPARC_TLS_IE_ADD, F_POP_POSTFIX }, |
| 881 | { "gdop", BFD_RELOC_SPARC_GOTDATA_OP, F_POP_POSTFIX } |
| 882 | }; |
| 883 | \f |
| 884 | /* Table of %-names that can appear in a sparc assembly program. This |
| 885 | table is initialized in md_begin and contains entries for each |
| 886 | privileged/hyperprivileged/alternate register and %-pseudo-op. */ |
| 887 | |
| 888 | enum perc_entry_type |
| 889 | { |
| 890 | perc_entry_none = 0, |
| 891 | perc_entry_reg, |
| 892 | perc_entry_post_pop, |
| 893 | perc_entry_imm_pop |
| 894 | }; |
| 895 | |
| 896 | struct perc_entry |
| 897 | { |
| 898 | /* Entry type. */ |
| 899 | enum perc_entry_type type; |
| 900 | /* Name of the %-entity. */ |
| 901 | const char *name; |
| 902 | /* strlen (name). */ |
| 903 | int len; |
| 904 | /* Value. Either a pop or a reg depending on type.*/ |
| 905 | union |
| 906 | { |
| 907 | struct pop_entry *pop; |
| 908 | struct priv_reg_entry *reg; |
| 909 | }; |
| 910 | }; |
| 911 | |
| 912 | #define NUM_PERC_ENTRIES \ |
| 913 | (((sizeof (priv_reg_table) / sizeof (priv_reg_table[0])) - 1) \ |
| 914 | + ((sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0])) - 1) \ |
| 915 | + ((sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0])) - 1) \ |
| 916 | + ARRAY_SIZE (pop_table) \ |
| 917 | + 1) |
| 918 | |
| 919 | struct perc_entry perc_table[NUM_PERC_ENTRIES]; |
| 920 | |
| 921 | static int |
| 922 | cmp_perc_entry (const void *parg, const void *qarg) |
| 923 | { |
| 924 | const struct perc_entry *p = (const struct perc_entry *) parg; |
| 925 | const struct perc_entry *q = (const struct perc_entry *) qarg; |
| 926 | |
| 927 | if (p->name == q->name) |
| 928 | return 0; |
| 929 | else if (p->name == NULL) |
| 930 | return 1; |
| 931 | else if (q->name == NULL) |
| 932 | return -1; |
| 933 | else |
| 934 | return strcmp (q->name, p->name); |
| 935 | } |
| 936 | \f |
| 937 | /* This function is called once, at assembler startup time. It should |
| 938 | set up all the tables, etc. that the MD part of the assembler will |
| 939 | need. */ |
| 940 | |
| 941 | void |
| 942 | md_begin (void) |
| 943 | { |
| 944 | const char *retval = NULL; |
| 945 | int lose = 0; |
| 946 | unsigned int i = 0; |
| 947 | |
| 948 | /* We don't get a chance to initialize anything before md_parse_option |
| 949 | is called, and it may not be called, so handle default initialization |
| 950 | now if not already done. */ |
| 951 | if (! default_init_p) |
| 952 | init_default_arch (); |
| 953 | |
| 954 | sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4; |
| 955 | op_hash = hash_new (); |
| 956 | |
| 957 | while (i < (unsigned int) sparc_num_opcodes) |
| 958 | { |
| 959 | const char *name = sparc_opcodes[i].name; |
| 960 | retval = hash_insert (op_hash, name, (void *) &sparc_opcodes[i]); |
| 961 | if (retval != NULL) |
| 962 | { |
| 963 | as_bad (_("Internal error: can't hash `%s': %s\n"), |
| 964 | sparc_opcodes[i].name, retval); |
| 965 | lose = 1; |
| 966 | } |
| 967 | do |
| 968 | { |
| 969 | if (sparc_opcodes[i].match & sparc_opcodes[i].lose) |
| 970 | { |
| 971 | as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"), |
| 972 | sparc_opcodes[i].name, sparc_opcodes[i].args); |
| 973 | lose = 1; |
| 974 | } |
| 975 | ++i; |
| 976 | } |
| 977 | while (i < (unsigned int) sparc_num_opcodes |
| 978 | && !strcmp (sparc_opcodes[i].name, name)); |
| 979 | } |
| 980 | |
| 981 | for (i = 0; native_op_table[i].name; i++) |
| 982 | { |
| 983 | const struct sparc_opcode *insn; |
| 984 | const char *name = ((sparc_arch_size == 32) |
| 985 | ? native_op_table[i].name32 |
| 986 | : native_op_table[i].name64); |
| 987 | insn = (struct sparc_opcode *) hash_find (op_hash, name); |
| 988 | if (insn == NULL) |
| 989 | { |
| 990 | as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"), |
| 991 | name, native_op_table[i].name); |
| 992 | lose = 1; |
| 993 | } |
| 994 | else |
| 995 | { |
| 996 | retval = hash_insert (op_hash, native_op_table[i].name, |
| 997 | (void *) insn); |
| 998 | if (retval != NULL) |
| 999 | { |
| 1000 | as_bad (_("Internal error: can't hash `%s': %s\n"), |
| 1001 | sparc_opcodes[i].name, retval); |
| 1002 | lose = 1; |
| 1003 | } |
| 1004 | } |
| 1005 | } |
| 1006 | |
| 1007 | if (lose) |
| 1008 | as_fatal (_("Broken assembler. No assembly attempted.")); |
| 1009 | |
| 1010 | qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]), |
| 1011 | sizeof (priv_reg_table[0]), cmp_reg_entry); |
| 1012 | qsort (hpriv_reg_table, sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0]), |
| 1013 | sizeof (hpriv_reg_table[0]), cmp_reg_entry); |
| 1014 | qsort (v9a_asr_table, sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0]), |
| 1015 | sizeof (v9a_asr_table[0]), cmp_reg_entry); |
| 1016 | |
| 1017 | /* If -bump, record the architecture level at which we start issuing |
| 1018 | warnings. The behaviour is different depending upon whether an |
| 1019 | architecture was explicitly specified. If it wasn't, we issue warnings |
| 1020 | for all upwards bumps. If it was, we don't start issuing warnings until |
| 1021 | we need to bump beyond the requested architecture or when we bump between |
| 1022 | conflicting architectures. */ |
| 1023 | |
| 1024 | if (warn_on_bump |
| 1025 | && architecture_requested) |
| 1026 | { |
| 1027 | /* `max_architecture' records the requested architecture. |
| 1028 | Issue warnings if we go above it. */ |
| 1029 | warn_after_architecture = max_architecture; |
| 1030 | } |
| 1031 | |
| 1032 | /* Find the highest architecture level that doesn't conflict with |
| 1033 | the requested one. */ |
| 1034 | |
| 1035 | if (warn_on_bump |
| 1036 | || !architecture_requested) |
| 1037 | { |
| 1038 | enum sparc_opcode_arch_val current_max_architecture |
| 1039 | = max_architecture; |
| 1040 | |
| 1041 | for (max_architecture = SPARC_OPCODE_ARCH_MAX; |
| 1042 | max_architecture > warn_after_architecture; |
| 1043 | --max_architecture) |
| 1044 | if (! SPARC_OPCODE_CONFLICT_P (max_architecture, |
| 1045 | current_max_architecture)) |
| 1046 | break; |
| 1047 | } |
| 1048 | |
| 1049 | /* Prepare the tables of %-pseudo-ops. */ |
| 1050 | { |
| 1051 | struct priv_reg_entry *reg_tables[] |
| 1052 | = {priv_reg_table, hpriv_reg_table, v9a_asr_table, NULL}; |
| 1053 | struct priv_reg_entry **reg_table; |
| 1054 | int entry = 0; |
| 1055 | |
| 1056 | /* Add registers. */ |
| 1057 | for (reg_table = reg_tables; reg_table[0]; reg_table++) |
| 1058 | { |
| 1059 | struct priv_reg_entry *reg; |
| 1060 | for (reg = *reg_table; reg->name; reg++) |
| 1061 | { |
| 1062 | struct perc_entry *p = &perc_table[entry++]; |
| 1063 | p->type = perc_entry_reg; |
| 1064 | p->name = reg->name; |
| 1065 | p->len = strlen (reg->name); |
| 1066 | p->reg = reg; |
| 1067 | } |
| 1068 | } |
| 1069 | |
| 1070 | /* Add %-pseudo-ops. */ |
| 1071 | for (i = 0; i < ARRAY_SIZE (pop_table); i++) |
| 1072 | { |
| 1073 | struct perc_entry *p = &perc_table[entry++]; |
| 1074 | p->type = (pop_table[i].flags & F_POP_POSTFIX |
| 1075 | ? perc_entry_post_pop : perc_entry_imm_pop); |
| 1076 | p->name = pop_table[i].name; |
| 1077 | p->len = strlen (pop_table[i].name); |
| 1078 | p->pop = &pop_table[i]; |
| 1079 | } |
| 1080 | |
| 1081 | /* Last entry is the sentinel. */ |
| 1082 | perc_table[entry].type = perc_entry_none; |
| 1083 | |
| 1084 | qsort (perc_table, sizeof (perc_table) / sizeof (perc_table[0]), |
| 1085 | sizeof (perc_table[0]), cmp_perc_entry); |
| 1086 | |
| 1087 | } |
| 1088 | } |
| 1089 | |
| 1090 | /* Called after all assembly has been done. */ |
| 1091 | |
| 1092 | void |
| 1093 | sparc_md_end (void) |
| 1094 | { |
| 1095 | unsigned long mach; |
| 1096 | #ifndef TE_SOLARIS |
| 1097 | int hwcaps, hwcaps2; |
| 1098 | #endif |
| 1099 | |
| 1100 | if (sparc_arch_size == 64) |
| 1101 | switch (current_architecture) |
| 1102 | { |
| 1103 | case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break; |
| 1104 | case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break; |
| 1105 | case SPARC_OPCODE_ARCH_V9C: mach = bfd_mach_sparc_v9c; break; |
| 1106 | case SPARC_OPCODE_ARCH_V9D: mach = bfd_mach_sparc_v9d; break; |
| 1107 | case SPARC_OPCODE_ARCH_V9E: mach = bfd_mach_sparc_v9e; break; |
| 1108 | case SPARC_OPCODE_ARCH_V9V: mach = bfd_mach_sparc_v9v; break; |
| 1109 | case SPARC_OPCODE_ARCH_V9M: mach = bfd_mach_sparc_v9m; break; |
| 1110 | case SPARC_OPCODE_ARCH_M8: mach = bfd_mach_sparc_v9m8; break; |
| 1111 | default: mach = bfd_mach_sparc_v9; break; |
| 1112 | } |
| 1113 | else |
| 1114 | switch (current_architecture) |
| 1115 | { |
| 1116 | case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break; |
| 1117 | case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break; |
| 1118 | case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break; |
| 1119 | case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break; |
| 1120 | case SPARC_OPCODE_ARCH_V9C: mach = bfd_mach_sparc_v8plusc; break; |
| 1121 | case SPARC_OPCODE_ARCH_V9D: mach = bfd_mach_sparc_v8plusd; break; |
| 1122 | case SPARC_OPCODE_ARCH_V9E: mach = bfd_mach_sparc_v8pluse; break; |
| 1123 | case SPARC_OPCODE_ARCH_V9V: mach = bfd_mach_sparc_v8plusv; break; |
| 1124 | case SPARC_OPCODE_ARCH_V9M: mach = bfd_mach_sparc_v8plusm; break; |
| 1125 | case SPARC_OPCODE_ARCH_M8: mach = bfd_mach_sparc_v8plusm8; break; |
| 1126 | /* The sparclite is treated like a normal sparc. Perhaps it shouldn't |
| 1127 | be but for now it is (since that's the way it's always been |
| 1128 | treated). */ |
| 1129 | default: mach = bfd_mach_sparc; break; |
| 1130 | } |
| 1131 | bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach); |
| 1132 | |
| 1133 | #ifndef TE_SOLARIS |
| 1134 | hwcaps = hwcap_seen & U0xffffffff; |
| 1135 | hwcaps2 = hwcap_seen >> 32; |
| 1136 | |
| 1137 | if (hwcaps) |
| 1138 | bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, hwcaps); |
| 1139 | if (hwcaps2) |
| 1140 | bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS2, hwcaps2); |
| 1141 | #endif |
| 1142 | } |
| 1143 | \f |
| 1144 | /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */ |
| 1145 | |
| 1146 | static inline int |
| 1147 | in_signed_range (bfd_signed_vma val, bfd_signed_vma max) |
| 1148 | { |
| 1149 | if (max <= 0) |
| 1150 | abort (); |
| 1151 | /* Sign-extend the value from the architecture word size, so that |
| 1152 | 0xffffffff is always considered -1 on sparc32. */ |
| 1153 | if (sparc_arch_size == 32) |
| 1154 | { |
| 1155 | bfd_signed_vma sign = (bfd_signed_vma) 1 << 31; |
| 1156 | val = ((val & U0xffffffff) ^ sign) - sign; |
| 1157 | } |
| 1158 | if (val > max) |
| 1159 | return 0; |
| 1160 | if (val < ~max) |
| 1161 | return 0; |
| 1162 | return 1; |
| 1163 | } |
| 1164 | |
| 1165 | /* Return non-zero if VAL is in the range 0 to MAX. */ |
| 1166 | |
| 1167 | static inline int |
| 1168 | in_unsigned_range (bfd_vma val, bfd_vma max) |
| 1169 | { |
| 1170 | if (val > max) |
| 1171 | return 0; |
| 1172 | return 1; |
| 1173 | } |
| 1174 | |
| 1175 | /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX. |
| 1176 | (e.g. -15 to +31). */ |
| 1177 | |
| 1178 | static inline int |
| 1179 | in_bitfield_range (bfd_signed_vma val, bfd_signed_vma max) |
| 1180 | { |
| 1181 | if (max <= 0) |
| 1182 | abort (); |
| 1183 | if (val > max) |
| 1184 | return 0; |
| 1185 | if (val < ~(max >> 1)) |
| 1186 | return 0; |
| 1187 | return 1; |
| 1188 | } |
| 1189 | |
| 1190 | static int |
| 1191 | sparc_ffs (unsigned int mask) |
| 1192 | { |
| 1193 | int i; |
| 1194 | |
| 1195 | if (mask == 0) |
| 1196 | return -1; |
| 1197 | |
| 1198 | for (i = 0; (mask & 1) == 0; ++i) |
| 1199 | mask >>= 1; |
| 1200 | return i; |
| 1201 | } |
| 1202 | |
| 1203 | /* Implement big shift right. */ |
| 1204 | static bfd_vma |
| 1205 | BSR (bfd_vma val, int amount) |
| 1206 | { |
| 1207 | if (sizeof (bfd_vma) <= 4 && amount >= 32) |
| 1208 | as_fatal (_("Support for 64-bit arithmetic not compiled in.")); |
| 1209 | return val >> amount; |
| 1210 | } |
| 1211 | \f |
| 1212 | /* For communication between sparc_ip and get_expression. */ |
| 1213 | static char *expr_end; |
| 1214 | |
| 1215 | /* Values for `special_case'. |
| 1216 | Instructions that require weird handling because they're longer than |
| 1217 | 4 bytes. */ |
| 1218 | #define SPECIAL_CASE_NONE 0 |
| 1219 | #define SPECIAL_CASE_SET 1 |
| 1220 | #define SPECIAL_CASE_SETSW 2 |
| 1221 | #define SPECIAL_CASE_SETX 3 |
| 1222 | /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */ |
| 1223 | #define SPECIAL_CASE_FDIV 4 |
| 1224 | |
| 1225 | /* Bit masks of various insns. */ |
| 1226 | #define NOP_INSN 0x01000000 |
| 1227 | #define OR_INSN 0x80100000 |
| 1228 | #define XOR_INSN 0x80180000 |
| 1229 | #define FMOVS_INSN 0x81A00020 |
| 1230 | #define SETHI_INSN 0x01000000 |
| 1231 | #define SLLX_INSN 0x81281000 |
| 1232 | #define SRA_INSN 0x81380000 |
| 1233 | |
| 1234 | /* The last instruction to be assembled. */ |
| 1235 | static const struct sparc_opcode *last_insn; |
| 1236 | /* The assembled opcode of `last_insn'. */ |
| 1237 | static unsigned long last_opcode; |
| 1238 | \f |
| 1239 | /* Handle the set and setuw synthetic instructions. */ |
| 1240 | |
| 1241 | static void |
| 1242 | synthetize_setuw (const struct sparc_opcode *insn) |
| 1243 | { |
| 1244 | int need_hi22_p = 0; |
| 1245 | int rd = (the_insn.opcode & RD (~0)) >> 25; |
| 1246 | |
| 1247 | if (the_insn.exp.X_op == O_constant) |
| 1248 | { |
| 1249 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) |
| 1250 | { |
| 1251 | if (sizeof (offsetT) > 4 |
| 1252 | && (the_insn.exp.X_add_number < 0 |
| 1253 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) |
| 1254 | as_warn (_("set: number not in 0..4294967295 range")); |
| 1255 | } |
| 1256 | else |
| 1257 | { |
| 1258 | if (sizeof (offsetT) > 4 |
| 1259 | && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 |
| 1260 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) |
| 1261 | as_warn (_("set: number not in -2147483648..4294967295 range")); |
| 1262 | the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number; |
| 1263 | } |
| 1264 | } |
| 1265 | |
| 1266 | /* See if operand is absolute and small; skip sethi if so. */ |
| 1267 | if (the_insn.exp.X_op != O_constant |
| 1268 | || the_insn.exp.X_add_number >= (1 << 12) |
| 1269 | || the_insn.exp.X_add_number < -(1 << 12)) |
| 1270 | { |
| 1271 | the_insn.opcode = (SETHI_INSN | RD (rd) |
| 1272 | | ((the_insn.exp.X_add_number >> 10) |
| 1273 | & (the_insn.exp.X_op == O_constant |
| 1274 | ? 0x3fffff : 0))); |
| 1275 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
| 1276 | ? BFD_RELOC_HI22 : BFD_RELOC_NONE); |
| 1277 | output_insn (insn, &the_insn); |
| 1278 | need_hi22_p = 1; |
| 1279 | } |
| 1280 | |
| 1281 | /* See if operand has no low-order bits; skip OR if so. */ |
| 1282 | if (the_insn.exp.X_op != O_constant |
| 1283 | || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0) |
| 1284 | || ! need_hi22_p) |
| 1285 | { |
| 1286 | the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0) |
| 1287 | | RD (rd) | IMMED |
| 1288 | | (the_insn.exp.X_add_number |
| 1289 | & (the_insn.exp.X_op != O_constant |
| 1290 | ? 0 : need_hi22_p ? 0x3ff : 0x1fff))); |
| 1291 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
| 1292 | ? BFD_RELOC_LO10 : BFD_RELOC_NONE); |
| 1293 | output_insn (insn, &the_insn); |
| 1294 | } |
| 1295 | } |
| 1296 | |
| 1297 | /* Handle the setsw synthetic instruction. */ |
| 1298 | |
| 1299 | static void |
| 1300 | synthetize_setsw (const struct sparc_opcode *insn) |
| 1301 | { |
| 1302 | int low32, rd, opc; |
| 1303 | |
| 1304 | rd = (the_insn.opcode & RD (~0)) >> 25; |
| 1305 | |
| 1306 | if (the_insn.exp.X_op != O_constant) |
| 1307 | { |
| 1308 | synthetize_setuw (insn); |
| 1309 | |
| 1310 | /* Need to sign extend it. */ |
| 1311 | the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd)); |
| 1312 | the_insn.reloc = BFD_RELOC_NONE; |
| 1313 | output_insn (insn, &the_insn); |
| 1314 | return; |
| 1315 | } |
| 1316 | |
| 1317 | if (sizeof (offsetT) > 4 |
| 1318 | && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 |
| 1319 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) |
| 1320 | as_warn (_("setsw: number not in -2147483648..4294967295 range")); |
| 1321 | |
| 1322 | low32 = the_insn.exp.X_add_number; |
| 1323 | |
| 1324 | if (low32 >= 0) |
| 1325 | { |
| 1326 | synthetize_setuw (insn); |
| 1327 | return; |
| 1328 | } |
| 1329 | |
| 1330 | opc = OR_INSN; |
| 1331 | |
| 1332 | the_insn.reloc = BFD_RELOC_NONE; |
| 1333 | /* See if operand is absolute and small; skip sethi if so. */ |
| 1334 | if (low32 < -(1 << 12)) |
| 1335 | { |
| 1336 | the_insn.opcode = (SETHI_INSN | RD (rd) |
| 1337 | | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff)); |
| 1338 | output_insn (insn, &the_insn); |
| 1339 | low32 = 0x1c00 | (low32 & 0x3ff); |
| 1340 | opc = RS1 (rd) | XOR_INSN; |
| 1341 | } |
| 1342 | |
| 1343 | the_insn.opcode = (opc | RD (rd) | IMMED |
| 1344 | | (low32 & 0x1fff)); |
| 1345 | output_insn (insn, &the_insn); |
| 1346 | } |
| 1347 | |
| 1348 | /* Handle the setx synthetic instruction. */ |
| 1349 | |
| 1350 | static void |
| 1351 | synthetize_setx (const struct sparc_opcode *insn) |
| 1352 | { |
| 1353 | int upper32, lower32; |
| 1354 | int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14; |
| 1355 | int dstreg = (the_insn.opcode & RD (~0)) >> 25; |
| 1356 | int upper_dstreg; |
| 1357 | int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0; |
| 1358 | int need_xor10_p = 0; |
| 1359 | |
| 1360 | #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000) |
| 1361 | lower32 = SIGNEXT32 (the_insn.exp.X_add_number); |
| 1362 | upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32)); |
| 1363 | #undef SIGNEXT32 |
| 1364 | |
| 1365 | upper_dstreg = tmpreg; |
| 1366 | /* The tmp reg should not be the dst reg. */ |
| 1367 | if (tmpreg == dstreg) |
| 1368 | as_warn (_("setx: temporary register same as destination register")); |
| 1369 | |
| 1370 | /* ??? Obviously there are other optimizations we can do |
| 1371 | (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be |
| 1372 | doing some of these. Later. If you do change things, try to |
| 1373 | change all of this to be table driven as well. */ |
| 1374 | /* What to output depends on the number if it's constant. |
| 1375 | Compute that first, then output what we've decided upon. */ |
| 1376 | if (the_insn.exp.X_op != O_constant) |
| 1377 | { |
| 1378 | if (sparc_arch_size == 32) |
| 1379 | { |
| 1380 | /* When arch size is 32, we want setx to be equivalent |
| 1381 | to setuw for anything but constants. */ |
| 1382 | the_insn.exp.X_add_number &= 0xffffffff; |
| 1383 | synthetize_setuw (insn); |
| 1384 | return; |
| 1385 | } |
| 1386 | need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1; |
| 1387 | lower32 = 0; |
| 1388 | upper32 = 0; |
| 1389 | } |
| 1390 | else |
| 1391 | { |
| 1392 | /* Reset X_add_number, we've extracted it as upper32/lower32. |
| 1393 | Otherwise fixup_segment will complain about not being able to |
| 1394 | write an 8 byte number in a 4 byte field. */ |
| 1395 | the_insn.exp.X_add_number = 0; |
| 1396 | |
| 1397 | /* Only need hh22 if `or' insn can't handle constant. */ |
| 1398 | if (upper32 < -(1 << 12) || upper32 >= (1 << 12)) |
| 1399 | need_hh22_p = 1; |
| 1400 | |
| 1401 | /* Does bottom part (after sethi) have bits? */ |
| 1402 | if ((need_hh22_p && (upper32 & 0x3ff) != 0) |
| 1403 | /* No hh22, but does upper32 still have bits we can't set |
| 1404 | from lower32? */ |
| 1405 | || (! need_hh22_p && upper32 != 0 && upper32 != -1)) |
| 1406 | need_hm10_p = 1; |
| 1407 | |
| 1408 | /* If the lower half is all zero, we build the upper half directly |
| 1409 | into the dst reg. */ |
| 1410 | if (lower32 != 0 |
| 1411 | /* Need lower half if number is zero or 0xffffffff00000000. */ |
| 1412 | || (! need_hh22_p && ! need_hm10_p)) |
| 1413 | { |
| 1414 | /* No need for sethi if `or' insn can handle constant. */ |
| 1415 | if (lower32 < -(1 << 12) || lower32 >= (1 << 12) |
| 1416 | /* Note that we can't use a negative constant in the `or' |
| 1417 | insn unless the upper 32 bits are all ones. */ |
| 1418 | || (lower32 < 0 && upper32 != -1) |
| 1419 | || (lower32 >= 0 && upper32 == -1)) |
| 1420 | need_hi22_p = 1; |
| 1421 | |
| 1422 | if (need_hi22_p && upper32 == -1) |
| 1423 | need_xor10_p = 1; |
| 1424 | |
| 1425 | /* Does bottom part (after sethi) have bits? */ |
| 1426 | else if ((need_hi22_p && (lower32 & 0x3ff) != 0) |
| 1427 | /* No sethi. */ |
| 1428 | || (! need_hi22_p && (lower32 & 0x1fff) != 0) |
| 1429 | /* Need `or' if we didn't set anything else. */ |
| 1430 | || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p)) |
| 1431 | need_lo10_p = 1; |
| 1432 | } |
| 1433 | else |
| 1434 | /* Output directly to dst reg if lower 32 bits are all zero. */ |
| 1435 | upper_dstreg = dstreg; |
| 1436 | } |
| 1437 | |
| 1438 | if (!upper_dstreg && dstreg) |
| 1439 | as_warn (_("setx: illegal temporary register g0")); |
| 1440 | |
| 1441 | if (need_hh22_p) |
| 1442 | { |
| 1443 | the_insn.opcode = (SETHI_INSN | RD (upper_dstreg) |
| 1444 | | ((upper32 >> 10) & 0x3fffff)); |
| 1445 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
| 1446 | ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE); |
| 1447 | output_insn (insn, &the_insn); |
| 1448 | } |
| 1449 | |
| 1450 | if (need_hi22_p) |
| 1451 | { |
| 1452 | the_insn.opcode = (SETHI_INSN | RD (dstreg) |
| 1453 | | (((need_xor10_p ? ~lower32 : lower32) |
| 1454 | >> 10) & 0x3fffff)); |
| 1455 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
| 1456 | ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE); |
| 1457 | output_insn (insn, &the_insn); |
| 1458 | } |
| 1459 | |
| 1460 | if (need_hm10_p) |
| 1461 | { |
| 1462 | the_insn.opcode = (OR_INSN |
| 1463 | | (need_hh22_p ? RS1 (upper_dstreg) : 0) |
| 1464 | | RD (upper_dstreg) |
| 1465 | | IMMED |
| 1466 | | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff))); |
| 1467 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
| 1468 | ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE); |
| 1469 | output_insn (insn, &the_insn); |
| 1470 | } |
| 1471 | |
| 1472 | if (need_lo10_p) |
| 1473 | { |
| 1474 | /* FIXME: One nice optimization to do here is to OR the low part |
| 1475 | with the highpart if hi22 isn't needed and the low part is |
| 1476 | positive. */ |
| 1477 | the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0) |
| 1478 | | RD (dstreg) |
| 1479 | | IMMED |
| 1480 | | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff))); |
| 1481 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
| 1482 | ? BFD_RELOC_LO10 : BFD_RELOC_NONE); |
| 1483 | output_insn (insn, &the_insn); |
| 1484 | } |
| 1485 | |
| 1486 | /* If we needed to build the upper part, shift it into place. */ |
| 1487 | if (need_hh22_p || need_hm10_p) |
| 1488 | { |
| 1489 | the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg) |
| 1490 | | IMMED | 32); |
| 1491 | the_insn.reloc = BFD_RELOC_NONE; |
| 1492 | output_insn (insn, &the_insn); |
| 1493 | } |
| 1494 | |
| 1495 | /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */ |
| 1496 | if (need_xor10_p) |
| 1497 | { |
| 1498 | the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED |
| 1499 | | 0x1c00 | (lower32 & 0x3ff)); |
| 1500 | the_insn.reloc = BFD_RELOC_NONE; |
| 1501 | output_insn (insn, &the_insn); |
| 1502 | } |
| 1503 | |
| 1504 | /* If we needed to build both upper and lower parts, OR them together. */ |
| 1505 | else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p)) |
| 1506 | { |
| 1507 | the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg) |
| 1508 | | RD (dstreg)); |
| 1509 | the_insn.reloc = BFD_RELOC_NONE; |
| 1510 | output_insn (insn, &the_insn); |
| 1511 | } |
| 1512 | } |
| 1513 | \f |
| 1514 | /* Main entry point to assemble one instruction. */ |
| 1515 | |
| 1516 | void |
| 1517 | md_assemble (char *str) |
| 1518 | { |
| 1519 | const struct sparc_opcode *insn; |
| 1520 | int special_case; |
| 1521 | |
| 1522 | know (str); |
| 1523 | special_case = sparc_ip (str, &insn); |
| 1524 | if (insn == NULL) |
| 1525 | return; |
| 1526 | |
| 1527 | /* Certain instructions may not appear on delay slots. Check for |
| 1528 | these situations. */ |
| 1529 | if (last_insn != NULL |
| 1530 | && (last_insn->flags & F_DELAYED) != 0) |
| 1531 | { |
| 1532 | /* Before SPARC V9 the effect of having a delayed branch |
| 1533 | instruction in the delay slot of a conditional delayed branch |
| 1534 | was undefined. |
| 1535 | |
| 1536 | In SPARC V9 DCTI couples are well defined. |
| 1537 | |
| 1538 | However, starting with the UltraSPARC Architecture 2005, DCTI |
| 1539 | couples (of all kind) are deprecated and should not be used, |
| 1540 | as they may be slow or behave differently to what the |
| 1541 | programmer expects. */ |
| 1542 | if (dcti_couples_detect |
| 1543 | && (insn->flags & F_DELAYED) != 0 |
| 1544 | && ((max_architecture < SPARC_OPCODE_ARCH_V9 |
| 1545 | && (last_insn->flags & F_CONDBR) != 0) |
| 1546 | || max_architecture >= SPARC_OPCODE_ARCH_V9C)) |
| 1547 | as_warn (_("unpredictable DCTI couple")); |
| 1548 | |
| 1549 | |
| 1550 | /* We warn about attempts to put a floating point branch in a |
| 1551 | delay slot, unless the delay slot has been annulled. */ |
| 1552 | if ((insn->flags & F_FBR) != 0 |
| 1553 | /* ??? This test isn't completely accurate. We assume anything with |
| 1554 | F_{UNBR,CONDBR,FBR} set is annullable. */ |
| 1555 | && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0 |
| 1556 | || (last_opcode & ANNUL) == 0)) |
| 1557 | as_warn (_("FP branch in delay slot")); |
| 1558 | } |
| 1559 | |
| 1560 | /* SPARC before v9 does not allow a floating point compare |
| 1561 | directly before a floating point branch. Insert a nop |
| 1562 | instruction if needed, with a warning. */ |
| 1563 | if (max_architecture < SPARC_OPCODE_ARCH_V9 |
| 1564 | && last_insn != NULL |
| 1565 | && (insn->flags & F_FBR) != 0 |
| 1566 | && (last_insn->flags & F_FLOAT) != 0 |
| 1567 | && (last_insn->match & OP3 (0x35)) == OP3 (0x35)) |
| 1568 | { |
| 1569 | struct sparc_it nop_insn; |
| 1570 | |
| 1571 | nop_insn.opcode = NOP_INSN; |
| 1572 | nop_insn.reloc = BFD_RELOC_NONE; |
| 1573 | output_insn (insn, &nop_insn); |
| 1574 | as_warn (_("FP branch preceded by FP compare; NOP inserted")); |
| 1575 | } |
| 1576 | |
| 1577 | switch (special_case) |
| 1578 | { |
| 1579 | case SPECIAL_CASE_NONE: |
| 1580 | /* Normal insn. */ |
| 1581 | output_insn (insn, &the_insn); |
| 1582 | break; |
| 1583 | |
| 1584 | case SPECIAL_CASE_SETSW: |
| 1585 | synthetize_setsw (insn); |
| 1586 | break; |
| 1587 | |
| 1588 | case SPECIAL_CASE_SET: |
| 1589 | synthetize_setuw (insn); |
| 1590 | break; |
| 1591 | |
| 1592 | case SPECIAL_CASE_SETX: |
| 1593 | synthetize_setx (insn); |
| 1594 | break; |
| 1595 | |
| 1596 | case SPECIAL_CASE_FDIV: |
| 1597 | { |
| 1598 | int rd = (the_insn.opcode >> 25) & 0x1f; |
| 1599 | |
| 1600 | output_insn (insn, &the_insn); |
| 1601 | |
| 1602 | /* According to information leaked from Sun, the "fdiv" instructions |
| 1603 | on early SPARC machines would produce incorrect results sometimes. |
| 1604 | The workaround is to add an fmovs of the destination register to |
| 1605 | itself just after the instruction. This was true on machines |
| 1606 | with Weitek 1165 float chips, such as the Sun-4/260 and /280. */ |
| 1607 | gas_assert (the_insn.reloc == BFD_RELOC_NONE); |
| 1608 | the_insn.opcode = FMOVS_INSN | rd | RD (rd); |
| 1609 | output_insn (insn, &the_insn); |
| 1610 | return; |
| 1611 | } |
| 1612 | |
| 1613 | default: |
| 1614 | as_fatal (_("failed special case insn sanity check")); |
| 1615 | } |
| 1616 | } |
| 1617 | |
| 1618 | static const char * |
| 1619 | get_hwcap_name (bfd_uint64_t mask) |
| 1620 | { |
| 1621 | if (mask & HWCAP_MUL32) |
| 1622 | return "mul32"; |
| 1623 | if (mask & HWCAP_DIV32) |
| 1624 | return "div32"; |
| 1625 | if (mask & HWCAP_FSMULD) |
| 1626 | return "fsmuld"; |
| 1627 | if (mask & HWCAP_V8PLUS) |
| 1628 | return "v8plus"; |
| 1629 | if (mask & HWCAP_POPC) |
| 1630 | return "popc"; |
| 1631 | if (mask & HWCAP_VIS) |
| 1632 | return "vis"; |
| 1633 | if (mask & HWCAP_VIS2) |
| 1634 | return "vis2"; |
| 1635 | if (mask & HWCAP_ASI_BLK_INIT) |
| 1636 | return "ASIBlkInit"; |
| 1637 | if (mask & HWCAP_FMAF) |
| 1638 | return "fmaf"; |
| 1639 | if (mask & HWCAP_VIS3) |
| 1640 | return "vis3"; |
| 1641 | if (mask & HWCAP_HPC) |
| 1642 | return "hpc"; |
| 1643 | if (mask & HWCAP_RANDOM) |
| 1644 | return "random"; |
| 1645 | if (mask & HWCAP_TRANS) |
| 1646 | return "trans"; |
| 1647 | if (mask & HWCAP_FJFMAU) |
| 1648 | return "fjfmau"; |
| 1649 | if (mask & HWCAP_IMA) |
| 1650 | return "ima"; |
| 1651 | if (mask & HWCAP_ASI_CACHE_SPARING) |
| 1652 | return "cspare"; |
| 1653 | if (mask & HWCAP_AES) |
| 1654 | return "aes"; |
| 1655 | if (mask & HWCAP_DES) |
| 1656 | return "des"; |
| 1657 | if (mask & HWCAP_KASUMI) |
| 1658 | return "kasumi"; |
| 1659 | if (mask & HWCAP_CAMELLIA) |
| 1660 | return "camellia"; |
| 1661 | if (mask & HWCAP_MD5) |
| 1662 | return "md5"; |
| 1663 | if (mask & HWCAP_SHA1) |
| 1664 | return "sha1"; |
| 1665 | if (mask & HWCAP_SHA256) |
| 1666 | return "sha256"; |
| 1667 | if (mask & HWCAP_SHA512) |
| 1668 | return "sha512"; |
| 1669 | if (mask & HWCAP_MPMUL) |
| 1670 | return "mpmul"; |
| 1671 | if (mask & HWCAP_MONT) |
| 1672 | return "mont"; |
| 1673 | if (mask & HWCAP_PAUSE) |
| 1674 | return "pause"; |
| 1675 | if (mask & HWCAP_CBCOND) |
| 1676 | return "cbcond"; |
| 1677 | if (mask & HWCAP_CRC32C) |
| 1678 | return "crc32c"; |
| 1679 | |
| 1680 | mask = mask >> 32; |
| 1681 | if (mask & HWCAP2_FJATHPLUS) |
| 1682 | return "fjathplus"; |
| 1683 | if (mask & HWCAP2_VIS3B) |
| 1684 | return "vis3b"; |
| 1685 | if (mask & HWCAP2_ADP) |
| 1686 | return "adp"; |
| 1687 | if (mask & HWCAP2_SPARC5) |
| 1688 | return "sparc5"; |
| 1689 | if (mask & HWCAP2_MWAIT) |
| 1690 | return "mwait"; |
| 1691 | if (mask & HWCAP2_XMPMUL) |
| 1692 | return "xmpmul"; |
| 1693 | if (mask & HWCAP2_XMONT) |
| 1694 | return "xmont"; |
| 1695 | if (mask & HWCAP2_NSEC) |
| 1696 | return "nsec"; |
| 1697 | if (mask & HWCAP2_SPARC6) |
| 1698 | return "sparc6"; |
| 1699 | if (mask & HWCAP2_ONADDSUB) |
| 1700 | return "onaddsub"; |
| 1701 | if (mask & HWCAP2_ONMUL) |
| 1702 | return "onmul"; |
| 1703 | if (mask & HWCAP2_ONDIV) |
| 1704 | return "ondiv"; |
| 1705 | if (mask & HWCAP2_DICTUNP) |
| 1706 | return "dictunp"; |
| 1707 | if (mask & HWCAP2_FPCMPSHL) |
| 1708 | return "fpcmpshl"; |
| 1709 | if (mask & HWCAP2_RLE) |
| 1710 | return "rle"; |
| 1711 | if (mask & HWCAP2_SHA3) |
| 1712 | return "sha3"; |
| 1713 | |
| 1714 | return "UNKNOWN"; |
| 1715 | } |
| 1716 | |
| 1717 | /* Subroutine of md_assemble to do the actual parsing. */ |
| 1718 | |
| 1719 | static int |
| 1720 | sparc_ip (char *str, const struct sparc_opcode **pinsn) |
| 1721 | { |
| 1722 | const char *error_message = ""; |
| 1723 | char *s; |
| 1724 | const char *args; |
| 1725 | char c; |
| 1726 | const struct sparc_opcode *insn; |
| 1727 | char *argsStart; |
| 1728 | unsigned long opcode; |
| 1729 | unsigned int mask = 0; |
| 1730 | int match = 0; |
| 1731 | int comma = 0; |
| 1732 | int v9_arg_p; |
| 1733 | int special_case = SPECIAL_CASE_NONE; |
| 1734 | const sparc_asi *sasi = NULL; |
| 1735 | |
| 1736 | s = str; |
| 1737 | if (ISLOWER (*s)) |
| 1738 | { |
| 1739 | do |
| 1740 | ++s; |
| 1741 | while (ISLOWER (*s) || ISDIGIT (*s) || *s == '_'); |
| 1742 | } |
| 1743 | |
| 1744 | switch (*s) |
| 1745 | { |
| 1746 | case '\0': |
| 1747 | break; |
| 1748 | |
| 1749 | case ',': |
| 1750 | comma = 1; |
| 1751 | /* Fall through. */ |
| 1752 | |
| 1753 | case ' ': |
| 1754 | *s++ = '\0'; |
| 1755 | break; |
| 1756 | |
| 1757 | default: |
| 1758 | as_bad (_("Unknown opcode: `%s'"), str); |
| 1759 | *pinsn = NULL; |
| 1760 | return special_case; |
| 1761 | } |
| 1762 | insn = (struct sparc_opcode *) hash_find (op_hash, str); |
| 1763 | *pinsn = insn; |
| 1764 | if (insn == NULL) |
| 1765 | { |
| 1766 | as_bad (_("Unknown opcode: `%s'"), str); |
| 1767 | return special_case; |
| 1768 | } |
| 1769 | if (comma) |
| 1770 | { |
| 1771 | *--s = ','; |
| 1772 | } |
| 1773 | |
| 1774 | argsStart = s; |
| 1775 | for (;;) |
| 1776 | { |
| 1777 | opcode = insn->match; |
| 1778 | memset (&the_insn, '\0', sizeof (the_insn)); |
| 1779 | the_insn.reloc = BFD_RELOC_NONE; |
| 1780 | v9_arg_p = 0; |
| 1781 | |
| 1782 | /* Build the opcode, checking as we go to make sure that the |
| 1783 | operands match. */ |
| 1784 | for (args = insn->args;; ++args) |
| 1785 | { |
| 1786 | switch (*args) |
| 1787 | { |
| 1788 | case 'K': |
| 1789 | { |
| 1790 | int kmask = 0; |
| 1791 | |
| 1792 | /* Parse a series of masks. */ |
| 1793 | if (*s == '#') |
| 1794 | { |
| 1795 | while (*s == '#') |
| 1796 | { |
| 1797 | int jmask; |
| 1798 | |
| 1799 | if (! parse_keyword_arg (sparc_encode_membar, &s, |
| 1800 | &jmask)) |
| 1801 | { |
| 1802 | error_message = _(": invalid membar mask name"); |
| 1803 | goto error; |
| 1804 | } |
| 1805 | kmask |= jmask; |
| 1806 | while (*s == ' ') |
| 1807 | ++s; |
| 1808 | if (*s == '|' || *s == '+') |
| 1809 | ++s; |
| 1810 | while (*s == ' ') |
| 1811 | ++s; |
| 1812 | } |
| 1813 | } |
| 1814 | else |
| 1815 | { |
| 1816 | if (! parse_const_expr_arg (&s, &kmask)) |
| 1817 | { |
| 1818 | error_message = _(": invalid membar mask expression"); |
| 1819 | goto error; |
| 1820 | } |
| 1821 | if (kmask < 0 || kmask > 127) |
| 1822 | { |
| 1823 | error_message = _(": invalid membar mask number"); |
| 1824 | goto error; |
| 1825 | } |
| 1826 | } |
| 1827 | |
| 1828 | opcode |= MEMBAR (kmask); |
| 1829 | continue; |
| 1830 | } |
| 1831 | |
| 1832 | case '3': |
| 1833 | { |
| 1834 | int smask = 0; |
| 1835 | |
| 1836 | if (! parse_const_expr_arg (&s, &smask)) |
| 1837 | { |
| 1838 | error_message = _(": invalid siam mode expression"); |
| 1839 | goto error; |
| 1840 | } |
| 1841 | if (smask < 0 || smask > 7) |
| 1842 | { |
| 1843 | error_message = _(": invalid siam mode number"); |
| 1844 | goto error; |
| 1845 | } |
| 1846 | opcode |= smask; |
| 1847 | continue; |
| 1848 | } |
| 1849 | |
| 1850 | case '*': |
| 1851 | { |
| 1852 | int fcn = 0; |
| 1853 | |
| 1854 | /* Parse a prefetch function. */ |
| 1855 | if (*s == '#') |
| 1856 | { |
| 1857 | if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn)) |
| 1858 | { |
| 1859 | error_message = _(": invalid prefetch function name"); |
| 1860 | goto error; |
| 1861 | } |
| 1862 | } |
| 1863 | else |
| 1864 | { |
| 1865 | if (! parse_const_expr_arg (&s, &fcn)) |
| 1866 | { |
| 1867 | error_message = _(": invalid prefetch function expression"); |
| 1868 | goto error; |
| 1869 | } |
| 1870 | if (fcn < 0 || fcn > 31) |
| 1871 | { |
| 1872 | error_message = _(": invalid prefetch function number"); |
| 1873 | goto error; |
| 1874 | } |
| 1875 | } |
| 1876 | opcode |= RD (fcn); |
| 1877 | continue; |
| 1878 | } |
| 1879 | |
| 1880 | case '!': |
| 1881 | case '?': |
| 1882 | /* Parse a sparc64 privileged register. */ |
| 1883 | if (*s == '%') |
| 1884 | { |
| 1885 | struct priv_reg_entry *p; |
| 1886 | unsigned int len = 9999999; /* Init to make gcc happy. */ |
| 1887 | |
| 1888 | s += 1; |
| 1889 | for (p = priv_reg_table; p->name; p++) |
| 1890 | if (p->name[0] == s[0]) |
| 1891 | { |
| 1892 | len = strlen (p->name); |
| 1893 | if (strncmp (p->name, s, len) == 0) |
| 1894 | break; |
| 1895 | } |
| 1896 | |
| 1897 | if (!p->name) |
| 1898 | { |
| 1899 | error_message = _(": unrecognizable privileged register"); |
| 1900 | goto error; |
| 1901 | } |
| 1902 | |
| 1903 | if (((opcode >> (*args == '?' ? 14 : 25)) & 0x1f) != (unsigned) p->regnum) |
| 1904 | { |
| 1905 | error_message = _(": unrecognizable privileged register"); |
| 1906 | goto error; |
| 1907 | } |
| 1908 | |
| 1909 | s += len; |
| 1910 | continue; |
| 1911 | } |
| 1912 | else |
| 1913 | { |
| 1914 | error_message = _(": unrecognizable privileged register"); |
| 1915 | goto error; |
| 1916 | } |
| 1917 | |
| 1918 | case '$': |
| 1919 | case '%': |
| 1920 | /* Parse a sparc64 hyperprivileged register. */ |
| 1921 | if (*s == '%') |
| 1922 | { |
| 1923 | struct priv_reg_entry *p; |
| 1924 | unsigned int len = 9999999; /* Init to make gcc happy. */ |
| 1925 | |
| 1926 | s += 1; |
| 1927 | for (p = hpriv_reg_table; p->name; p++) |
| 1928 | if (p->name[0] == s[0]) |
| 1929 | { |
| 1930 | len = strlen (p->name); |
| 1931 | if (strncmp (p->name, s, len) == 0) |
| 1932 | break; |
| 1933 | } |
| 1934 | |
| 1935 | if (!p->name) |
| 1936 | { |
| 1937 | error_message = _(": unrecognizable hyperprivileged register"); |
| 1938 | goto error; |
| 1939 | } |
| 1940 | |
| 1941 | if (((opcode >> (*args == '$' ? 14 : 25)) & 0x1f) != (unsigned) p->regnum) |
| 1942 | { |
| 1943 | error_message = _(": unrecognizable hyperprivileged register"); |
| 1944 | goto error; |
| 1945 | } |
| 1946 | |
| 1947 | s += len; |
| 1948 | continue; |
| 1949 | } |
| 1950 | else |
| 1951 | { |
| 1952 | error_message = _(": unrecognizable hyperprivileged register"); |
| 1953 | goto error; |
| 1954 | } |
| 1955 | |
| 1956 | case '_': |
| 1957 | case '/': |
| 1958 | /* Parse a v9a or later ancillary state register. */ |
| 1959 | if (*s == '%') |
| 1960 | { |
| 1961 | struct priv_reg_entry *p; |
| 1962 | unsigned int len = 9999999; /* Init to make gcc happy. */ |
| 1963 | |
| 1964 | s += 1; |
| 1965 | for (p = v9a_asr_table; p->name; p++) |
| 1966 | if (p->name[0] == s[0]) |
| 1967 | { |
| 1968 | len = strlen (p->name); |
| 1969 | if (strncmp (p->name, s, len) == 0) |
| 1970 | break; |
| 1971 | } |
| 1972 | |
| 1973 | if (!p->name) |
| 1974 | { |
| 1975 | error_message = _(": unrecognizable ancillary state register"); |
| 1976 | goto error; |
| 1977 | } |
| 1978 | |
| 1979 | if (((opcode >> (*args == '/' ? 14 : 25)) & 0x1f) != (unsigned) p->regnum) |
| 1980 | { |
| 1981 | error_message = _(": unrecognizable ancillary state register"); |
| 1982 | goto error; |
| 1983 | } |
| 1984 | |
| 1985 | s += len; |
| 1986 | continue; |
| 1987 | } |
| 1988 | else |
| 1989 | { |
| 1990 | error_message = _(": unrecognizable ancillary state register"); |
| 1991 | goto error; |
| 1992 | } |
| 1993 | |
| 1994 | case 'M': |
| 1995 | case 'm': |
| 1996 | if (strncmp (s, "%asr", 4) == 0) |
| 1997 | { |
| 1998 | s += 4; |
| 1999 | |
| 2000 | if (ISDIGIT (*s)) |
| 2001 | { |
| 2002 | long num = 0; |
| 2003 | |
| 2004 | while (ISDIGIT (*s)) |
| 2005 | { |
| 2006 | num = num * 10 + *s - '0'; |
| 2007 | ++s; |
| 2008 | } |
| 2009 | |
| 2010 | /* We used to check here for the asr number to |
| 2011 | be between 16 and 31 in V9 and later, as |
| 2012 | mandated by the section C.1.1 "Register |
| 2013 | Names" in the SPARC spec. However, we |
| 2014 | decided to remove this restriction as a) it |
| 2015 | introduces problems when new V9 asr registers |
| 2016 | are introduced, b) the Solaris assembler |
| 2017 | doesn't implement this restriction and c) the |
| 2018 | restriction will go away in future revisions |
| 2019 | of the Oracle SPARC Architecture. */ |
| 2020 | |
| 2021 | if (num < 0 || 31 < num) |
| 2022 | { |
| 2023 | error_message = _(": asr number must be between 0 and 31"); |
| 2024 | goto error; |
| 2025 | } |
| 2026 | |
| 2027 | opcode |= (*args == 'M' ? RS1 (num) : RD (num)); |
| 2028 | continue; |
| 2029 | } |
| 2030 | else |
| 2031 | { |
| 2032 | error_message = _(": expecting %asrN"); |
| 2033 | goto error; |
| 2034 | } |
| 2035 | } /* if %asr */ |
| 2036 | break; |
| 2037 | |
| 2038 | case 'I': |
| 2039 | the_insn.reloc = BFD_RELOC_SPARC_11; |
| 2040 | goto immediate; |
| 2041 | |
| 2042 | case 'j': |
| 2043 | the_insn.reloc = BFD_RELOC_SPARC_10; |
| 2044 | goto immediate; |
| 2045 | |
| 2046 | case ')': |
| 2047 | if (*s == ' ') |
| 2048 | s++; |
| 2049 | if ((s[0] == '0' && s[1] == 'x' && ISXDIGIT (s[2])) |
| 2050 | || ISDIGIT (*s)) |
| 2051 | { |
| 2052 | long num = 0; |
| 2053 | |
| 2054 | if (s[0] == '0' && s[1] == 'x') |
| 2055 | { |
| 2056 | s += 2; |
| 2057 | while (ISXDIGIT (*s)) |
| 2058 | { |
| 2059 | num <<= 4; |
| 2060 | num |= hex_value (*s); |
| 2061 | ++s; |
| 2062 | } |
| 2063 | } |
| 2064 | else |
| 2065 | { |
| 2066 | while (ISDIGIT (*s)) |
| 2067 | { |
| 2068 | num = num * 10 + *s - '0'; |
| 2069 | ++s; |
| 2070 | } |
| 2071 | } |
| 2072 | if (num < 0 || num > 31) |
| 2073 | { |
| 2074 | error_message = _(": crypto immediate must be between 0 and 31"); |
| 2075 | goto error; |
| 2076 | } |
| 2077 | |
| 2078 | opcode |= RS3 (num); |
| 2079 | continue; |
| 2080 | } |
| 2081 | else |
| 2082 | { |
| 2083 | error_message = _(": expecting crypto immediate"); |
| 2084 | goto error; |
| 2085 | } |
| 2086 | |
| 2087 | case 'X': |
| 2088 | /* V8 systems don't understand BFD_RELOC_SPARC_5. */ |
| 2089 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) |
| 2090 | the_insn.reloc = BFD_RELOC_SPARC_5; |
| 2091 | else |
| 2092 | the_insn.reloc = BFD_RELOC_SPARC13; |
| 2093 | /* These fields are unsigned, but for upward compatibility, |
| 2094 | allow negative values as well. */ |
| 2095 | goto immediate; |
| 2096 | |
| 2097 | case 'Y': |
| 2098 | /* V8 systems don't understand BFD_RELOC_SPARC_6. */ |
| 2099 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) |
| 2100 | the_insn.reloc = BFD_RELOC_SPARC_6; |
| 2101 | else |
| 2102 | the_insn.reloc = BFD_RELOC_SPARC13; |
| 2103 | /* These fields are unsigned, but for upward compatibility, |
| 2104 | allow negative values as well. */ |
| 2105 | goto immediate; |
| 2106 | |
| 2107 | case 'k': |
| 2108 | the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16; |
| 2109 | the_insn.pcrel = 1; |
| 2110 | goto immediate; |
| 2111 | |
| 2112 | case '=': |
| 2113 | the_insn.reloc = /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10; |
| 2114 | the_insn.pcrel = 1; |
| 2115 | goto immediate; |
| 2116 | |
| 2117 | case 'G': |
| 2118 | the_insn.reloc = BFD_RELOC_SPARC_WDISP19; |
| 2119 | the_insn.pcrel = 1; |
| 2120 | goto immediate; |
| 2121 | |
| 2122 | case 'N': |
| 2123 | if (*s == 'p' && s[1] == 'n') |
| 2124 | { |
| 2125 | s += 2; |
| 2126 | continue; |
| 2127 | } |
| 2128 | break; |
| 2129 | |
| 2130 | case 'T': |
| 2131 | if (*s == 'p' && s[1] == 't') |
| 2132 | { |
| 2133 | s += 2; |
| 2134 | continue; |
| 2135 | } |
| 2136 | break; |
| 2137 | |
| 2138 | case 'z': |
| 2139 | if (*s == ' ') |
| 2140 | { |
| 2141 | ++s; |
| 2142 | } |
| 2143 | if ((strncmp (s, "%icc", 4) == 0) |
| 2144 | || (sparc_arch_size == 32 && strncmp (s, "%ncc", 4) == 0)) |
| 2145 | { |
| 2146 | s += 4; |
| 2147 | continue; |
| 2148 | } |
| 2149 | break; |
| 2150 | |
| 2151 | case 'Z': |
| 2152 | if (*s == ' ') |
| 2153 | { |
| 2154 | ++s; |
| 2155 | } |
| 2156 | if ((strncmp (s, "%xcc", 4) == 0) |
| 2157 | || (sparc_arch_size == 64 && strncmp (s, "%ncc", 4) == 0)) |
| 2158 | { |
| 2159 | s += 4; |
| 2160 | continue; |
| 2161 | } |
| 2162 | break; |
| 2163 | |
| 2164 | case '6': |
| 2165 | if (*s == ' ') |
| 2166 | { |
| 2167 | ++s; |
| 2168 | } |
| 2169 | if (strncmp (s, "%fcc0", 5) == 0) |
| 2170 | { |
| 2171 | s += 5; |
| 2172 | continue; |
| 2173 | } |
| 2174 | break; |
| 2175 | |
| 2176 | case '7': |
| 2177 | if (*s == ' ') |
| 2178 | { |
| 2179 | ++s; |
| 2180 | } |
| 2181 | if (strncmp (s, "%fcc1", 5) == 0) |
| 2182 | { |
| 2183 | s += 5; |
| 2184 | continue; |
| 2185 | } |
| 2186 | break; |
| 2187 | |
| 2188 | case '8': |
| 2189 | if (*s == ' ') |
| 2190 | { |
| 2191 | ++s; |
| 2192 | } |
| 2193 | if (strncmp (s, "%fcc2", 5) == 0) |
| 2194 | { |
| 2195 | s += 5; |
| 2196 | continue; |
| 2197 | } |
| 2198 | break; |
| 2199 | |
| 2200 | case '9': |
| 2201 | if (*s == ' ') |
| 2202 | { |
| 2203 | ++s; |
| 2204 | } |
| 2205 | if (strncmp (s, "%fcc3", 5) == 0) |
| 2206 | { |
| 2207 | s += 5; |
| 2208 | continue; |
| 2209 | } |
| 2210 | break; |
| 2211 | |
| 2212 | case 'P': |
| 2213 | if (strncmp (s, "%pc", 3) == 0) |
| 2214 | { |
| 2215 | s += 3; |
| 2216 | continue; |
| 2217 | } |
| 2218 | break; |
| 2219 | |
| 2220 | case 'W': |
| 2221 | if (strncmp (s, "%tick", 5) == 0) |
| 2222 | { |
| 2223 | s += 5; |
| 2224 | continue; |
| 2225 | } |
| 2226 | break; |
| 2227 | |
| 2228 | case '\0': /* End of args. */ |
| 2229 | if (s[0] == ',' && s[1] == '%') |
| 2230 | { |
| 2231 | char *s1; |
| 2232 | int npar = 0; |
| 2233 | const struct perc_entry *p; |
| 2234 | |
| 2235 | for (p = perc_table; p->type != perc_entry_none; p++) |
| 2236 | if ((p->type == perc_entry_post_pop || p->type == perc_entry_reg) |
| 2237 | && strncmp (s + 2, p->name, p->len) == 0) |
| 2238 | break; |
| 2239 | if (p->type == perc_entry_none || p->type == perc_entry_reg) |
| 2240 | break; |
| 2241 | |
| 2242 | if (s[p->len + 2] != '(') |
| 2243 | { |
| 2244 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), p->name); |
| 2245 | return special_case; |
| 2246 | } |
| 2247 | |
| 2248 | if (! (p->pop->flags & F_POP_TLS_CALL) |
| 2249 | && the_insn.reloc != BFD_RELOC_NONE) |
| 2250 | { |
| 2251 | as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"), |
| 2252 | p->name); |
| 2253 | return special_case; |
| 2254 | } |
| 2255 | |
| 2256 | if ((p->pop->flags & F_POP_TLS_CALL) |
| 2257 | && (the_insn.reloc != BFD_RELOC_32_PCREL_S2 |
| 2258 | || the_insn.exp.X_add_number != 0 |
| 2259 | || the_insn.exp.X_add_symbol |
| 2260 | != symbol_find_or_make ("__tls_get_addr"))) |
| 2261 | { |
| 2262 | as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"), |
| 2263 | p->name); |
| 2264 | return special_case; |
| 2265 | } |
| 2266 | |
| 2267 | the_insn.reloc = p->pop->reloc; |
| 2268 | memset (&the_insn.exp, 0, sizeof (the_insn.exp)); |
| 2269 | s += p->len + 3; |
| 2270 | |
| 2271 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) |
| 2272 | if (*s1 == '(') |
| 2273 | npar++; |
| 2274 | else if (*s1 == ')') |
| 2275 | { |
| 2276 | if (!npar) |
| 2277 | break; |
| 2278 | npar--; |
| 2279 | } |
| 2280 | |
| 2281 | if (*s1 != ')') |
| 2282 | { |
| 2283 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), p->name); |
| 2284 | return special_case; |
| 2285 | } |
| 2286 | |
| 2287 | *s1 = '\0'; |
| 2288 | (void) get_expression (s); |
| 2289 | *s1 = ')'; |
| 2290 | s = s1 + 1; |
| 2291 | } |
| 2292 | if (*s == '\0') |
| 2293 | match = 1; |
| 2294 | break; |
| 2295 | |
| 2296 | case '+': |
| 2297 | if (*s == '+') |
| 2298 | { |
| 2299 | ++s; |
| 2300 | continue; |
| 2301 | } |
| 2302 | if (*s == '-') |
| 2303 | { |
| 2304 | continue; |
| 2305 | } |
| 2306 | break; |
| 2307 | |
| 2308 | case '[': /* These must match exactly. */ |
| 2309 | case ']': |
| 2310 | case ',': |
| 2311 | case ' ': |
| 2312 | if (*s++ == *args) |
| 2313 | continue; |
| 2314 | break; |
| 2315 | |
| 2316 | case '#': /* Must be at least one digit. */ |
| 2317 | if (ISDIGIT (*s++)) |
| 2318 | { |
| 2319 | while (ISDIGIT (*s)) |
| 2320 | { |
| 2321 | ++s; |
| 2322 | } |
| 2323 | continue; |
| 2324 | } |
| 2325 | break; |
| 2326 | |
| 2327 | case 'C': /* Coprocessor state register. */ |
| 2328 | if (strncmp (s, "%csr", 4) == 0) |
| 2329 | { |
| 2330 | s += 4; |
| 2331 | continue; |
| 2332 | } |
| 2333 | break; |
| 2334 | |
| 2335 | case 'b': /* Next operand is a coprocessor register. */ |
| 2336 | case 'c': |
| 2337 | case 'D': |
| 2338 | if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s)) |
| 2339 | { |
| 2340 | mask = *s++; |
| 2341 | if (ISDIGIT (*s)) |
| 2342 | { |
| 2343 | mask = 10 * (mask - '0') + (*s++ - '0'); |
| 2344 | if (mask >= 32) |
| 2345 | { |
| 2346 | break; |
| 2347 | } |
| 2348 | } |
| 2349 | else |
| 2350 | { |
| 2351 | mask -= '0'; |
| 2352 | } |
| 2353 | switch (*args) |
| 2354 | { |
| 2355 | |
| 2356 | case 'b': |
| 2357 | opcode |= mask << 14; |
| 2358 | continue; |
| 2359 | |
| 2360 | case 'c': |
| 2361 | opcode |= mask; |
| 2362 | continue; |
| 2363 | |
| 2364 | case 'D': |
| 2365 | opcode |= mask << 25; |
| 2366 | continue; |
| 2367 | } |
| 2368 | } |
| 2369 | break; |
| 2370 | |
| 2371 | case 'r': /* next operand must be a register */ |
| 2372 | case 'O': |
| 2373 | case '1': |
| 2374 | case '2': |
| 2375 | case 'd': |
| 2376 | if (*s++ == '%') |
| 2377 | { |
| 2378 | switch (c = *s++) |
| 2379 | { |
| 2380 | |
| 2381 | case 'f': /* frame pointer */ |
| 2382 | if (*s++ == 'p') |
| 2383 | { |
| 2384 | mask = 0x1e; |
| 2385 | break; |
| 2386 | } |
| 2387 | goto error; |
| 2388 | |
| 2389 | case 'g': /* global register */ |
| 2390 | c = *s++; |
| 2391 | if (isoctal (c)) |
| 2392 | { |
| 2393 | mask = c - '0'; |
| 2394 | break; |
| 2395 | } |
| 2396 | goto error; |
| 2397 | |
| 2398 | case 'i': /* in register */ |
| 2399 | c = *s++; |
| 2400 | if (isoctal (c)) |
| 2401 | { |
| 2402 | mask = c - '0' + 24; |
| 2403 | break; |
| 2404 | } |
| 2405 | goto error; |
| 2406 | |
| 2407 | case 'l': /* local register */ |
| 2408 | c = *s++; |
| 2409 | if (isoctal (c)) |
| 2410 | { |
| 2411 | mask = (c - '0' + 16); |
| 2412 | break; |
| 2413 | } |
| 2414 | goto error; |
| 2415 | |
| 2416 | case 'o': /* out register */ |
| 2417 | c = *s++; |
| 2418 | if (isoctal (c)) |
| 2419 | { |
| 2420 | mask = (c - '0' + 8); |
| 2421 | break; |
| 2422 | } |
| 2423 | goto error; |
| 2424 | |
| 2425 | case 's': /* stack pointer */ |
| 2426 | if (*s++ == 'p') |
| 2427 | { |
| 2428 | mask = 0xe; |
| 2429 | break; |
| 2430 | } |
| 2431 | goto error; |
| 2432 | |
| 2433 | case 'r': /* any register */ |
| 2434 | if (!ISDIGIT ((c = *s++))) |
| 2435 | { |
| 2436 | goto error; |
| 2437 | } |
| 2438 | /* FALLTHROUGH */ |
| 2439 | case '0': |
| 2440 | case '1': |
| 2441 | case '2': |
| 2442 | case '3': |
| 2443 | case '4': |
| 2444 | case '5': |
| 2445 | case '6': |
| 2446 | case '7': |
| 2447 | case '8': |
| 2448 | case '9': |
| 2449 | if (ISDIGIT (*s)) |
| 2450 | { |
| 2451 | if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) |
| 2452 | { |
| 2453 | goto error; |
| 2454 | } |
| 2455 | } |
| 2456 | else |
| 2457 | { |
| 2458 | c -= '0'; |
| 2459 | } |
| 2460 | mask = c; |
| 2461 | break; |
| 2462 | |
| 2463 | default: |
| 2464 | goto error; |
| 2465 | } |
| 2466 | |
| 2467 | if ((mask & ~1) == 2 && sparc_arch_size == 64 |
| 2468 | && no_undeclared_regs && ! globals[mask]) |
| 2469 | as_bad (_("detected global register use not covered by .register pseudo-op")); |
| 2470 | |
| 2471 | /* Got the register, now figure out where |
| 2472 | it goes in the opcode. */ |
| 2473 | switch (*args) |
| 2474 | { |
| 2475 | case '1': |
| 2476 | opcode |= mask << 14; |
| 2477 | continue; |
| 2478 | |
| 2479 | case '2': |
| 2480 | opcode |= mask; |
| 2481 | continue; |
| 2482 | |
| 2483 | case 'd': |
| 2484 | opcode |= mask << 25; |
| 2485 | continue; |
| 2486 | |
| 2487 | case 'r': |
| 2488 | opcode |= (mask << 25) | (mask << 14); |
| 2489 | continue; |
| 2490 | |
| 2491 | case 'O': |
| 2492 | opcode |= (mask << 25) | (mask << 0); |
| 2493 | continue; |
| 2494 | } |
| 2495 | } |
| 2496 | break; |
| 2497 | |
| 2498 | case 'e': /* next operand is a floating point register */ |
| 2499 | case 'v': |
| 2500 | case 'V': |
| 2501 | case ';': |
| 2502 | |
| 2503 | case 'f': |
| 2504 | case 'B': |
| 2505 | case 'R': |
| 2506 | case ':': |
| 2507 | case '\'': |
| 2508 | |
| 2509 | case '4': |
| 2510 | case '5': |
| 2511 | |
| 2512 | case 'g': |
| 2513 | case 'H': |
| 2514 | case 'J': |
| 2515 | case '}': |
| 2516 | case '^': |
| 2517 | { |
| 2518 | char format; |
| 2519 | |
| 2520 | if (*s++ == '%' |
| 2521 | && ((format = *s) == 'f' |
| 2522 | || format == 'd' |
| 2523 | || format == 'q') |
| 2524 | && ISDIGIT (*++s)) |
| 2525 | { |
| 2526 | for (mask = 0; ISDIGIT (*s); ++s) |
| 2527 | { |
| 2528 | mask = 10 * mask + (*s - '0'); |
| 2529 | } /* read the number */ |
| 2530 | |
| 2531 | if ((*args == 'v' |
| 2532 | || *args == 'B' |
| 2533 | || *args == '5' |
| 2534 | || *args == 'H' |
| 2535 | || *args == '\'' |
| 2536 | || format == 'd') |
| 2537 | && (mask & 1)) |
| 2538 | { |
| 2539 | /* register must be even numbered */ |
| 2540 | break; |
| 2541 | } |
| 2542 | |
| 2543 | if ((*args == 'V' |
| 2544 | || *args == 'R' |
| 2545 | || *args == 'J' |
| 2546 | || format == 'q') |
| 2547 | && (mask & 3)) |
| 2548 | { |
| 2549 | /* register must be multiple of 4 */ |
| 2550 | break; |
| 2551 | } |
| 2552 | |
| 2553 | if ((*args == ':' |
| 2554 | || *args == ';' |
| 2555 | || *args == '^') |
| 2556 | && (mask & 7)) |
| 2557 | { |
| 2558 | /* register must be multiple of 8 */ |
| 2559 | break; |
| 2560 | } |
| 2561 | |
| 2562 | if (*args == '\'' && mask < 48) |
| 2563 | { |
| 2564 | /* register must be higher or equal than %f48 */ |
| 2565 | break; |
| 2566 | } |
| 2567 | |
| 2568 | if (mask >= 64) |
| 2569 | { |
| 2570 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) |
| 2571 | error_message = _(": There are only 64 f registers; [0-63]"); |
| 2572 | else |
| 2573 | error_message = _(": There are only 32 f registers; [0-31]"); |
| 2574 | goto error; |
| 2575 | } /* on error */ |
| 2576 | else if (mask >= 32) |
| 2577 | { |
| 2578 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) |
| 2579 | { |
| 2580 | if (*args == 'e' || *args == 'f' || *args == 'g') |
| 2581 | { |
| 2582 | error_message |
| 2583 | = _(": There are only 32 single precision f registers; [0-31]"); |
| 2584 | goto error; |
| 2585 | } |
| 2586 | v9_arg_p = 1; |
| 2587 | mask -= 31; /* wrap high bit */ |
| 2588 | } |
| 2589 | else |
| 2590 | { |
| 2591 | error_message = _(": There are only 32 f registers; [0-31]"); |
| 2592 | goto error; |
| 2593 | } |
| 2594 | } |
| 2595 | } |
| 2596 | else |
| 2597 | { |
| 2598 | break; |
| 2599 | } /* if not an 'f' register. */ |
| 2600 | |
| 2601 | if (*args == '}' && mask != RS2 (opcode)) |
| 2602 | { |
| 2603 | error_message |
| 2604 | = _(": Instruction requires frs2 and frsd must be the same register"); |
| 2605 | goto error; |
| 2606 | } |
| 2607 | |
| 2608 | switch (*args) |
| 2609 | { |
| 2610 | case 'v': |
| 2611 | case 'V': |
| 2612 | case 'e': |
| 2613 | case ';': |
| 2614 | opcode |= RS1 (mask); |
| 2615 | continue; |
| 2616 | |
| 2617 | case 'f': |
| 2618 | case 'B': |
| 2619 | case 'R': |
| 2620 | case ':': |
| 2621 | opcode |= RS2 (mask); |
| 2622 | continue; |
| 2623 | |
| 2624 | case '\'': |
| 2625 | opcode |= RS2 (mask & 0xe); |
| 2626 | continue; |
| 2627 | |
| 2628 | case '4': |
| 2629 | case '5': |
| 2630 | opcode |= RS3 (mask); |
| 2631 | continue; |
| 2632 | |
| 2633 | case 'g': |
| 2634 | case 'H': |
| 2635 | case 'J': |
| 2636 | case '}': |
| 2637 | case '^': |
| 2638 | opcode |= RD (mask); |
| 2639 | continue; |
| 2640 | } /* Pack it in. */ |
| 2641 | |
| 2642 | know (0); |
| 2643 | break; |
| 2644 | } /* float arg */ |
| 2645 | |
| 2646 | case 'F': |
| 2647 | if (strncmp (s, "%fsr", 4) == 0) |
| 2648 | { |
| 2649 | s += 4; |
| 2650 | continue; |
| 2651 | } |
| 2652 | break; |
| 2653 | |
| 2654 | case '(': |
| 2655 | if (strncmp (s, "%efsr", 5) == 0) |
| 2656 | { |
| 2657 | s += 5; |
| 2658 | continue; |
| 2659 | } |
| 2660 | break; |
| 2661 | |
| 2662 | case '0': /* 64 bit immediate (set, setsw, setx insn) */ |
| 2663 | the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ |
| 2664 | goto immediate; |
| 2665 | |
| 2666 | case 'l': /* 22 bit PC relative immediate */ |
| 2667 | the_insn.reloc = BFD_RELOC_SPARC_WDISP22; |
| 2668 | the_insn.pcrel = 1; |
| 2669 | goto immediate; |
| 2670 | |
| 2671 | case 'L': /* 30 bit immediate */ |
| 2672 | the_insn.reloc = BFD_RELOC_32_PCREL_S2; |
| 2673 | the_insn.pcrel = 1; |
| 2674 | goto immediate; |
| 2675 | |
| 2676 | case 'h': |
| 2677 | case 'n': /* 22 bit immediate */ |
| 2678 | the_insn.reloc = BFD_RELOC_SPARC22; |
| 2679 | goto immediate; |
| 2680 | |
| 2681 | case 'i': /* 13 bit immediate */ |
| 2682 | the_insn.reloc = BFD_RELOC_SPARC13; |
| 2683 | |
| 2684 | /* fallthrough */ |
| 2685 | |
| 2686 | immediate: |
| 2687 | if (*s == ' ') |
| 2688 | s++; |
| 2689 | |
| 2690 | { |
| 2691 | char *s1; |
| 2692 | const char *op_arg = NULL; |
| 2693 | static expressionS op_exp; |
| 2694 | bfd_reloc_code_real_type old_reloc = the_insn.reloc; |
| 2695 | |
| 2696 | /* Check for %hi, etc. */ |
| 2697 | if (*s == '%') |
| 2698 | { |
| 2699 | const struct perc_entry *p; |
| 2700 | |
| 2701 | for (p = perc_table; p->type != perc_entry_none; p++) |
| 2702 | if ((p->type == perc_entry_imm_pop || p->type == perc_entry_reg) |
| 2703 | && strncmp (s + 1, p->name, p->len) == 0) |
| 2704 | break; |
| 2705 | if (p->type == perc_entry_none || p->type == perc_entry_reg) |
| 2706 | break; |
| 2707 | |
| 2708 | if (s[p->len + 1] != '(') |
| 2709 | { |
| 2710 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), p->name); |
| 2711 | return special_case; |
| 2712 | } |
| 2713 | |
| 2714 | op_arg = p->name; |
| 2715 | the_insn.reloc = p->pop->reloc; |
| 2716 | s += p->len + 2; |
| 2717 | v9_arg_p = p->pop->flags & F_POP_V9; |
| 2718 | } |
| 2719 | |
| 2720 | /* Note that if the get_expression() fails, we will still |
| 2721 | have created U entries in the symbol table for the |
| 2722 | 'symbols' in the input string. Try not to create U |
| 2723 | symbols for registers, etc. */ |
| 2724 | |
| 2725 | /* This stuff checks to see if the expression ends in |
| 2726 | +%reg. If it does, it removes the register from |
| 2727 | the expression, and re-sets 's' to point to the |
| 2728 | right place. */ |
| 2729 | |
| 2730 | if (op_arg) |
| 2731 | { |
| 2732 | int npar = 0; |
| 2733 | |
| 2734 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) |
| 2735 | if (*s1 == '(') |
| 2736 | npar++; |
| 2737 | else if (*s1 == ')') |
| 2738 | { |
| 2739 | if (!npar) |
| 2740 | break; |
| 2741 | npar--; |
| 2742 | } |
| 2743 | |
| 2744 | if (*s1 != ')') |
| 2745 | { |
| 2746 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg); |
| 2747 | return special_case; |
| 2748 | } |
| 2749 | |
| 2750 | *s1 = '\0'; |
| 2751 | (void) get_expression (s); |
| 2752 | *s1 = ')'; |
| 2753 | if (expr_end != s1) |
| 2754 | { |
| 2755 | as_bad (_("Expression inside %%%s could not be parsed"), op_arg); |
| 2756 | return special_case; |
| 2757 | } |
| 2758 | s = s1 + 1; |
| 2759 | if (*s == ',' || *s == ']' || !*s) |
| 2760 | continue; |
| 2761 | if (*s != '+' && *s != '-') |
| 2762 | { |
| 2763 | as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg); |
| 2764 | return special_case; |
| 2765 | } |
| 2766 | *s1 = '0'; |
| 2767 | s = s1; |
| 2768 | op_exp = the_insn.exp; |
| 2769 | memset (&the_insn.exp, 0, sizeof (the_insn.exp)); |
| 2770 | } |
| 2771 | |
| 2772 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) |
| 2773 | ; |
| 2774 | |
| 2775 | if (s1 != s && ISDIGIT (s1[-1])) |
| 2776 | { |
| 2777 | if (s1[-2] == '%' && s1[-3] == '+') |
| 2778 | s1 -= 3; |
| 2779 | else if (strchr ("golir0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+') |
| 2780 | s1 -= 4; |
| 2781 | else if (s1[-3] == 'r' && s1[-4] == '%' && s1[-5] == '+') |
| 2782 | s1 -= 5; |
| 2783 | else |
| 2784 | s1 = NULL; |
| 2785 | if (s1) |
| 2786 | { |
| 2787 | *s1 = '\0'; |
| 2788 | if (op_arg && s1 == s + 1) |
| 2789 | the_insn.exp.X_op = O_absent; |
| 2790 | else |
| 2791 | (void) get_expression (s); |
| 2792 | *s1 = '+'; |
| 2793 | if (op_arg) |
| 2794 | *s = ')'; |
| 2795 | s = s1; |
| 2796 | } |
| 2797 | } |
| 2798 | else |
| 2799 | s1 = NULL; |
| 2800 | |
| 2801 | if (!s1) |
| 2802 | { |
| 2803 | (void) get_expression (s); |
| 2804 | if (op_arg) |
| 2805 | *s = ')'; |
| 2806 | s = expr_end; |
| 2807 | } |
| 2808 | |
| 2809 | if (op_arg) |
| 2810 | { |
| 2811 | the_insn.exp2 = the_insn.exp; |
| 2812 | the_insn.exp = op_exp; |
| 2813 | if (the_insn.exp2.X_op == O_absent) |
| 2814 | the_insn.exp2.X_op = O_illegal; |
| 2815 | else if (the_insn.exp.X_op == O_absent) |
| 2816 | { |
| 2817 | the_insn.exp = the_insn.exp2; |
| 2818 | the_insn.exp2.X_op = O_illegal; |
| 2819 | } |
| 2820 | else if (the_insn.exp.X_op == O_constant) |
| 2821 | { |
| 2822 | valueT val = the_insn.exp.X_add_number; |
| 2823 | switch (the_insn.reloc) |
| 2824 | { |
| 2825 | default: |
| 2826 | break; |
| 2827 | |
| 2828 | case BFD_RELOC_SPARC_HH22: |
| 2829 | val = BSR (val, 32); |
| 2830 | /* Fall through. */ |
| 2831 | |
| 2832 | case BFD_RELOC_SPARC_LM22: |
| 2833 | case BFD_RELOC_HI22: |
| 2834 | val = (val >> 10) & 0x3fffff; |
| 2835 | break; |
| 2836 | |
| 2837 | case BFD_RELOC_SPARC_HM10: |
| 2838 | val = BSR (val, 32); |
| 2839 | /* Fall through. */ |
| 2840 | |
| 2841 | case BFD_RELOC_LO10: |
| 2842 | val &= 0x3ff; |
| 2843 | break; |
| 2844 | |
| 2845 | case BFD_RELOC_SPARC_H34: |
| 2846 | val >>= 12; |
| 2847 | val &= 0x3fffff; |
| 2848 | break; |
| 2849 | |
| 2850 | case BFD_RELOC_SPARC_H44: |
| 2851 | val >>= 22; |
| 2852 | val &= 0x3fffff; |
| 2853 | break; |
| 2854 | |
| 2855 | case BFD_RELOC_SPARC_M44: |
| 2856 | val >>= 12; |
| 2857 | val &= 0x3ff; |
| 2858 | break; |
| 2859 | |
| 2860 | case BFD_RELOC_SPARC_L44: |
| 2861 | val &= 0xfff; |
| 2862 | break; |
| 2863 | |
| 2864 | case BFD_RELOC_SPARC_HIX22: |
| 2865 | val = ~val; |
| 2866 | val = (val >> 10) & 0x3fffff; |
| 2867 | break; |
| 2868 | |
| 2869 | case BFD_RELOC_SPARC_LOX10: |
| 2870 | val = (val & 0x3ff) | 0x1c00; |
| 2871 | break; |
| 2872 | } |
| 2873 | the_insn.exp = the_insn.exp2; |
| 2874 | the_insn.exp.X_add_number += val; |
| 2875 | the_insn.exp2.X_op = O_illegal; |
| 2876 | the_insn.reloc = old_reloc; |
| 2877 | } |
| 2878 | else if (the_insn.exp2.X_op != O_constant) |
| 2879 | { |
| 2880 | as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg); |
| 2881 | return special_case; |
| 2882 | } |
| 2883 | else |
| 2884 | { |
| 2885 | if (old_reloc != BFD_RELOC_SPARC13 |
| 2886 | || the_insn.reloc != BFD_RELOC_LO10 |
| 2887 | || sparc_arch_size != 64 |
| 2888 | || sparc_pic_code) |
| 2889 | { |
| 2890 | as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg); |
| 2891 | return special_case; |
| 2892 | } |
| 2893 | the_insn.reloc = BFD_RELOC_SPARC_OLO10; |
| 2894 | } |
| 2895 | } |
| 2896 | } |
| 2897 | /* Check for constants that don't require emitting a reloc. */ |
| 2898 | if (the_insn.exp.X_op == O_constant |
| 2899 | && the_insn.exp.X_add_symbol == 0 |
| 2900 | && the_insn.exp.X_op_symbol == 0) |
| 2901 | { |
| 2902 | /* For pc-relative call instructions, we reject |
| 2903 | constants to get better code. */ |
| 2904 | if (the_insn.pcrel |
| 2905 | && the_insn.reloc == BFD_RELOC_32_PCREL_S2 |
| 2906 | && in_signed_range (the_insn.exp.X_add_number, 0x3fff)) |
| 2907 | { |
| 2908 | error_message = _(": PC-relative operand can't be a constant"); |
| 2909 | goto error; |
| 2910 | } |
| 2911 | |
| 2912 | if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22 |
| 2913 | && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64) |
| 2914 | { |
| 2915 | error_message = _(": TLS operand can't be a constant"); |
| 2916 | goto error; |
| 2917 | } |
| 2918 | |
| 2919 | /* Constants that won't fit are checked in md_apply_fix |
| 2920 | and bfd_install_relocation. |
| 2921 | ??? It would be preferable to install the constants |
| 2922 | into the insn here and save having to create a fixS |
| 2923 | for each one. There already exists code to handle |
| 2924 | all the various cases (e.g. in md_apply_fix and |
| 2925 | bfd_install_relocation) so duplicating all that code |
| 2926 | here isn't right. */ |
| 2927 | |
| 2928 | /* This is a special case to handle cbcond instructions |
| 2929 | properly, which can need two relocations. The first |
| 2930 | one is for the 5-bit immediate field and the latter |
| 2931 | is going to be for the WDISP10 branch part. We |
| 2932 | handle the R_SPARC_5 immediate directly here so that |
| 2933 | we don't need to add support for multiple relocations |
| 2934 | in one instruction just yet. */ |
| 2935 | if (the_insn.reloc == BFD_RELOC_SPARC_5 |
| 2936 | && ((insn->match & OP(0x3)) == 0)) |
| 2937 | { |
| 2938 | valueT val = the_insn.exp.X_add_number; |
| 2939 | |
| 2940 | the_insn.reloc = BFD_RELOC_NONE; |
| 2941 | if (! in_bitfield_range (val, 0x1f)) |
| 2942 | { |
| 2943 | error_message = _(": Immediate value in cbcond is out of range."); |
| 2944 | goto error; |
| 2945 | } |
| 2946 | opcode |= val & 0x1f; |
| 2947 | } |
| 2948 | } |
| 2949 | |
| 2950 | continue; |
| 2951 | |
| 2952 | case 'a': |
| 2953 | if (*s++ == 'a') |
| 2954 | { |
| 2955 | opcode |= ANNUL; |
| 2956 | continue; |
| 2957 | } |
| 2958 | break; |
| 2959 | |
| 2960 | case 'A': |
| 2961 | { |
| 2962 | int asi = 0; |
| 2963 | |
| 2964 | /* Parse an asi. */ |
| 2965 | if (*s == '#') |
| 2966 | { |
| 2967 | if (! parse_sparc_asi (&s, &sasi)) |
| 2968 | { |
| 2969 | error_message = _(": invalid ASI name"); |
| 2970 | goto error; |
| 2971 | } |
| 2972 | asi = sasi->value; |
| 2973 | } |
| 2974 | else |
| 2975 | { |
| 2976 | if (! parse_const_expr_arg (&s, &asi)) |
| 2977 | { |
| 2978 | error_message = _(": invalid ASI expression"); |
| 2979 | goto error; |
| 2980 | } |
| 2981 | if (asi < 0 || asi > 255) |
| 2982 | { |
| 2983 | error_message = _(": invalid ASI number"); |
| 2984 | goto error; |
| 2985 | } |
| 2986 | } |
| 2987 | opcode |= ASI (asi); |
| 2988 | continue; |
| 2989 | } /* Alternate space. */ |
| 2990 | |
| 2991 | case 'p': |
| 2992 | if (strncmp (s, "%psr", 4) == 0) |
| 2993 | { |
| 2994 | s += 4; |
| 2995 | continue; |
| 2996 | } |
| 2997 | break; |
| 2998 | |
| 2999 | case 'q': /* Floating point queue. */ |
| 3000 | if (strncmp (s, "%fq", 3) == 0) |
| 3001 | { |
| 3002 | s += 3; |
| 3003 | continue; |
| 3004 | } |
| 3005 | break; |
| 3006 | |
| 3007 | case 'Q': /* Coprocessor queue. */ |
| 3008 | if (strncmp (s, "%cq", 3) == 0) |
| 3009 | { |
| 3010 | s += 3; |
| 3011 | continue; |
| 3012 | } |
| 3013 | break; |
| 3014 | |
| 3015 | case 'S': |
| 3016 | if (strcmp (str, "set") == 0 |
| 3017 | || strcmp (str, "setuw") == 0) |
| 3018 | { |
| 3019 | special_case = SPECIAL_CASE_SET; |
| 3020 | continue; |
| 3021 | } |
| 3022 | else if (strcmp (str, "setsw") == 0) |
| 3023 | { |
| 3024 | special_case = SPECIAL_CASE_SETSW; |
| 3025 | continue; |
| 3026 | } |
| 3027 | else if (strcmp (str, "setx") == 0) |
| 3028 | { |
| 3029 | special_case = SPECIAL_CASE_SETX; |
| 3030 | continue; |
| 3031 | } |
| 3032 | else if (strncmp (str, "fdiv", 4) == 0) |
| 3033 | { |
| 3034 | special_case = SPECIAL_CASE_FDIV; |
| 3035 | continue; |
| 3036 | } |
| 3037 | break; |
| 3038 | |
| 3039 | case 'o': |
| 3040 | if (strncmp (s, "%asi", 4) != 0) |
| 3041 | break; |
| 3042 | s += 4; |
| 3043 | continue; |
| 3044 | |
| 3045 | case 's': |
| 3046 | if (strncmp (s, "%fprs", 5) != 0) |
| 3047 | break; |
| 3048 | s += 5; |
| 3049 | continue; |
| 3050 | |
| 3051 | case '{': |
| 3052 | if (strncmp (s, "%mcdper",7) != 0) |
| 3053 | break; |
| 3054 | s += 7; |
| 3055 | continue; |
| 3056 | |
| 3057 | case '&': |
| 3058 | if (strncmp (s, "%entropy", 8) != 0) |
| 3059 | break; |
| 3060 | s += 8; |
| 3061 | continue; |
| 3062 | |
| 3063 | case 'E': |
| 3064 | if (strncmp (s, "%ccr", 4) != 0) |
| 3065 | break; |
| 3066 | s += 4; |
| 3067 | continue; |
| 3068 | |
| 3069 | case 't': |
| 3070 | if (strncmp (s, "%tbr", 4) != 0) |
| 3071 | break; |
| 3072 | s += 4; |
| 3073 | continue; |
| 3074 | |
| 3075 | case 'w': |
| 3076 | if (strncmp (s, "%wim", 4) != 0) |
| 3077 | break; |
| 3078 | s += 4; |
| 3079 | continue; |
| 3080 | |
| 3081 | case '|': |
| 3082 | { |
| 3083 | int imm2 = 0; |
| 3084 | |
| 3085 | /* Parse a 2-bit immediate. */ |
| 3086 | if (! parse_const_expr_arg (&s, &imm2)) |
| 3087 | { |
| 3088 | error_message = _(": non-immdiate imm2 operand"); |
| 3089 | goto error; |
| 3090 | } |
| 3091 | if ((imm2 & ~0x3) != 0) |
| 3092 | { |
| 3093 | error_message = _(": imm2 immediate operand out of range (0-3)"); |
| 3094 | goto error; |
| 3095 | } |
| 3096 | |
| 3097 | opcode |= ((imm2 & 0x2) << 3) | (imm2 & 0x1); |
| 3098 | continue; |
| 3099 | } |
| 3100 | |
| 3101 | case 'x': |
| 3102 | { |
| 3103 | char *push = input_line_pointer; |
| 3104 | expressionS e; |
| 3105 | |
| 3106 | input_line_pointer = s; |
| 3107 | expression (&e); |
| 3108 | if (e.X_op == O_constant) |
| 3109 | { |
| 3110 | int n = e.X_add_number; |
| 3111 | if (n != e.X_add_number || (n & ~0x1ff) != 0) |
| 3112 | as_bad (_("OPF immediate operand out of range (0-0x1ff)")); |
| 3113 | else |
| 3114 | opcode |= e.X_add_number << 5; |
| 3115 | } |
| 3116 | else |
| 3117 | as_bad (_("non-immediate OPF operand, ignored")); |
| 3118 | s = input_line_pointer; |
| 3119 | input_line_pointer = push; |
| 3120 | continue; |
| 3121 | } |
| 3122 | |
| 3123 | case 'y': |
| 3124 | if (strncmp (s, "%y", 2) != 0) |
| 3125 | break; |
| 3126 | s += 2; |
| 3127 | continue; |
| 3128 | |
| 3129 | case 'u': |
| 3130 | case 'U': |
| 3131 | { |
| 3132 | /* Parse a sparclet cpreg. */ |
| 3133 | int cpreg; |
| 3134 | if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg)) |
| 3135 | { |
| 3136 | error_message = _(": invalid cpreg name"); |
| 3137 | goto error; |
| 3138 | } |
| 3139 | opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg)); |
| 3140 | continue; |
| 3141 | } |
| 3142 | |
| 3143 | default: |
| 3144 | as_fatal (_("failed sanity check.")); |
| 3145 | } /* switch on arg code. */ |
| 3146 | |
| 3147 | /* Break out of for() loop. */ |
| 3148 | break; |
| 3149 | } /* For each arg that we expect. */ |
| 3150 | |
| 3151 | error: |
| 3152 | if (match == 0) |
| 3153 | { |
| 3154 | /* Args don't match. */ |
| 3155 | if (&insn[1] - sparc_opcodes < sparc_num_opcodes |
| 3156 | && (insn->name == insn[1].name |
| 3157 | || !strcmp (insn->name, insn[1].name))) |
| 3158 | { |
| 3159 | ++insn; |
| 3160 | s = argsStart; |
| 3161 | continue; |
| 3162 | } |
| 3163 | else |
| 3164 | { |
| 3165 | as_bad (_("Illegal operands%s"), error_message); |
| 3166 | return special_case; |
| 3167 | } |
| 3168 | } |
| 3169 | else |
| 3170 | { |
| 3171 | /* We have a match. Now see if the architecture is OK. */ |
| 3172 | /* String to use in case of architecture warning. */ |
| 3173 | const char *msg_str = str; |
| 3174 | int needed_arch_mask = insn->architecture; |
| 3175 | |
| 3176 | /* Include the ASI architecture needed as well */ |
| 3177 | if (sasi && needed_arch_mask > sasi->architecture) |
| 3178 | { |
| 3179 | needed_arch_mask = sasi->architecture; |
| 3180 | msg_str = sasi->name; |
| 3181 | } |
| 3182 | |
| 3183 | bfd_uint64_t hwcaps |
| 3184 | = (((bfd_uint64_t) insn->hwcaps2) << 32) | insn->hwcaps; |
| 3185 | |
| 3186 | #ifndef TE_SOLARIS |
| 3187 | if (hwcaps) |
| 3188 | hwcap_seen |= hwcaps; |
| 3189 | #endif |
| 3190 | if (v9_arg_p) |
| 3191 | { |
| 3192 | needed_arch_mask &= |
| 3193 | ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1); |
| 3194 | if (! needed_arch_mask) |
| 3195 | needed_arch_mask = |
| 3196 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); |
| 3197 | } |
| 3198 | |
| 3199 | if (needed_arch_mask |
| 3200 | & SPARC_OPCODE_SUPPORTED (current_architecture)) |
| 3201 | /* OK. */ |
| 3202 | ; |
| 3203 | /* Can we bump up the architecture? */ |
| 3204 | else if (needed_arch_mask |
| 3205 | & SPARC_OPCODE_SUPPORTED (max_architecture)) |
| 3206 | { |
| 3207 | enum sparc_opcode_arch_val needed_architecture = |
| 3208 | sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture) |
| 3209 | & needed_arch_mask); |
| 3210 | |
| 3211 | gas_assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX); |
| 3212 | if (warn_on_bump |
| 3213 | && needed_architecture > warn_after_architecture) |
| 3214 | { |
| 3215 | as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""), |
| 3216 | sparc_opcode_archs[current_architecture].name, |
| 3217 | sparc_opcode_archs[needed_architecture].name, |
| 3218 | msg_str); |
| 3219 | warn_after_architecture = needed_architecture; |
| 3220 | } |
| 3221 | current_architecture = needed_architecture; |
| 3222 | hwcap_allowed |
| 3223 | = (hwcap_allowed |
| 3224 | | hwcaps |
| 3225 | | (((bfd_uint64_t) sparc_opcode_archs[current_architecture].hwcaps2) << 32) |
| 3226 | | sparc_opcode_archs[current_architecture].hwcaps); |
| 3227 | } |
| 3228 | /* Conflict. */ |
| 3229 | /* ??? This seems to be a bit fragile. What if the next entry in |
| 3230 | the opcode table is the one we want and it is supported? |
| 3231 | It is possible to arrange the table today so that this can't |
| 3232 | happen but what about tomorrow? */ |
| 3233 | else |
| 3234 | { |
| 3235 | int arch, printed_one_p = 0; |
| 3236 | char *p; |
| 3237 | char required_archs[SPARC_OPCODE_ARCH_MAX * 16]; |
| 3238 | |
| 3239 | /* Create a list of the architectures that support the insn. */ |
| 3240 | needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture); |
| 3241 | p = required_archs; |
| 3242 | arch = sparc_ffs (needed_arch_mask); |
| 3243 | while ((1 << arch) <= needed_arch_mask) |
| 3244 | { |
| 3245 | if ((1 << arch) & needed_arch_mask) |
| 3246 | { |
| 3247 | if (printed_one_p) |
| 3248 | *p++ = '|'; |
| 3249 | strcpy (p, sparc_opcode_archs[arch].name); |
| 3250 | p += strlen (p); |
| 3251 | printed_one_p = 1; |
| 3252 | } |
| 3253 | ++arch; |
| 3254 | } |
| 3255 | |
| 3256 | as_bad (_("Architecture mismatch on \"%s %s\"."), str, argsStart); |
| 3257 | as_tsktsk (_("(Requires %s; requested architecture is %s.)"), |
| 3258 | required_archs, |
| 3259 | sparc_opcode_archs[max_architecture].name); |
| 3260 | return special_case; |
| 3261 | } |
| 3262 | |
| 3263 | /* Make sure the hwcaps used by the instruction are |
| 3264 | currently enabled. */ |
| 3265 | if (hwcaps & ~hwcap_allowed) |
| 3266 | { |
| 3267 | const char *hwcap_name = get_hwcap_name(hwcaps & ~hwcap_allowed); |
| 3268 | |
| 3269 | as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."), |
| 3270 | hwcap_name, str); |
| 3271 | return special_case; |
| 3272 | } |
| 3273 | } /* If no match. */ |
| 3274 | |
| 3275 | break; |
| 3276 | } /* Forever looking for a match. */ |
| 3277 | |
| 3278 | the_insn.opcode = opcode; |
| 3279 | return special_case; |
| 3280 | } |
| 3281 | |
| 3282 | static char * |
| 3283 | skip_over_keyword (char *q) |
| 3284 | { |
| 3285 | for (q = q + (*q == '#' || *q == '%'); |
| 3286 | ISALNUM (*q) || *q == '_'; |
| 3287 | ++q) |
| 3288 | continue; |
| 3289 | return q; |
| 3290 | } |
| 3291 | |
| 3292 | static int |
| 3293 | parse_sparc_asi (char **input_pointer_p, const sparc_asi **value_p) |
| 3294 | { |
| 3295 | const sparc_asi *value; |
| 3296 | char c, *p, *q; |
| 3297 | |
| 3298 | p = *input_pointer_p; |
| 3299 | q = skip_over_keyword(p); |
| 3300 | c = *q; |
| 3301 | *q = 0; |
| 3302 | value = sparc_encode_asi (p); |
| 3303 | *q = c; |
| 3304 | if (value == NULL) |
| 3305 | return 0; |
| 3306 | *value_p = value; |
| 3307 | *input_pointer_p = q; |
| 3308 | return 1; |
| 3309 | } |
| 3310 | |
| 3311 | /* Parse an argument that can be expressed as a keyword. |
| 3312 | (eg: #StoreStore or %ccfr). |
| 3313 | The result is a boolean indicating success. |
| 3314 | If successful, INPUT_POINTER is updated. */ |
| 3315 | |
| 3316 | static int |
| 3317 | parse_keyword_arg (int (*lookup_fn) (const char *), |
| 3318 | char **input_pointerP, |
| 3319 | int *valueP) |
| 3320 | { |
| 3321 | int value; |
| 3322 | char c, *p, *q; |
| 3323 | |
| 3324 | p = *input_pointerP; |
| 3325 | q = skip_over_keyword(p); |
| 3326 | c = *q; |
| 3327 | *q = 0; |
| 3328 | value = (*lookup_fn) (p); |
| 3329 | *q = c; |
| 3330 | if (value == -1) |
| 3331 | return 0; |
| 3332 | *valueP = value; |
| 3333 | *input_pointerP = q; |
| 3334 | return 1; |
| 3335 | } |
| 3336 | |
| 3337 | /* Parse an argument that is a constant expression. |
| 3338 | The result is a boolean indicating success. */ |
| 3339 | |
| 3340 | static int |
| 3341 | parse_const_expr_arg (char **input_pointerP, int *valueP) |
| 3342 | { |
| 3343 | char *save = input_line_pointer; |
| 3344 | expressionS exp; |
| 3345 | |
| 3346 | input_line_pointer = *input_pointerP; |
| 3347 | /* The next expression may be something other than a constant |
| 3348 | (say if we're not processing the right variant of the insn). |
| 3349 | Don't call expression unless we're sure it will succeed as it will |
| 3350 | signal an error (which we want to defer until later). */ |
| 3351 | /* FIXME: It might be better to define md_operand and have it recognize |
| 3352 | things like %asi, etc. but continuing that route through to the end |
| 3353 | is a lot of work. */ |
| 3354 | if (*input_line_pointer == '%') |
| 3355 | { |
| 3356 | input_line_pointer = save; |
| 3357 | return 0; |
| 3358 | } |
| 3359 | expression (&exp); |
| 3360 | *input_pointerP = input_line_pointer; |
| 3361 | input_line_pointer = save; |
| 3362 | if (exp.X_op != O_constant) |
| 3363 | return 0; |
| 3364 | *valueP = exp.X_add_number; |
| 3365 | return 1; |
| 3366 | } |
| 3367 | |
| 3368 | /* Subroutine of sparc_ip to parse an expression. */ |
| 3369 | |
| 3370 | static int |
| 3371 | get_expression (char *str) |
| 3372 | { |
| 3373 | char *save_in; |
| 3374 | segT seg; |
| 3375 | |
| 3376 | save_in = input_line_pointer; |
| 3377 | input_line_pointer = str; |
| 3378 | seg = expression (&the_insn.exp); |
| 3379 | if (seg != absolute_section |
| 3380 | && seg != text_section |
| 3381 | && seg != data_section |
| 3382 | && seg != bss_section |
| 3383 | && seg != undefined_section) |
| 3384 | { |
| 3385 | the_insn.error = _("bad segment"); |
| 3386 | expr_end = input_line_pointer; |
| 3387 | input_line_pointer = save_in; |
| 3388 | return 1; |
| 3389 | } |
| 3390 | expr_end = input_line_pointer; |
| 3391 | input_line_pointer = save_in; |
| 3392 | return 0; |
| 3393 | } |
| 3394 | |
| 3395 | /* Subroutine of md_assemble to output one insn. */ |
| 3396 | |
| 3397 | static void |
| 3398 | output_insn (const struct sparc_opcode *insn, struct sparc_it *theinsn) |
| 3399 | { |
| 3400 | char *toP = frag_more (4); |
| 3401 | |
| 3402 | /* Put out the opcode. */ |
| 3403 | if (INSN_BIG_ENDIAN) |
| 3404 | number_to_chars_bigendian (toP, (valueT) theinsn->opcode, 4); |
| 3405 | else |
| 3406 | number_to_chars_littleendian (toP, (valueT) theinsn->opcode, 4); |
| 3407 | |
| 3408 | /* Put out the symbol-dependent stuff. */ |
| 3409 | if (theinsn->reloc != BFD_RELOC_NONE) |
| 3410 | { |
| 3411 | fixS *fixP = fix_new_exp (frag_now, /* Which frag. */ |
| 3412 | (toP - frag_now->fr_literal), /* Where. */ |
| 3413 | 4, /* Size. */ |
| 3414 | &theinsn->exp, |
| 3415 | theinsn->pcrel, |
| 3416 | theinsn->reloc); |
| 3417 | /* Turn off overflow checking in fixup_segment. We'll do our |
| 3418 | own overflow checking in md_apply_fix. This is necessary because |
| 3419 | the insn size is 4 and fixup_segment will signal an overflow for |
| 3420 | large 8 byte quantities. */ |
| 3421 | fixP->fx_no_overflow = 1; |
| 3422 | if (theinsn->reloc == BFD_RELOC_SPARC_OLO10) |
| 3423 | fixP->tc_fix_data = theinsn->exp2.X_add_number; |
| 3424 | } |
| 3425 | |
| 3426 | last_insn = insn; |
| 3427 | last_opcode = theinsn->opcode; |
| 3428 | |
| 3429 | dwarf2_emit_insn (4); |
| 3430 | } |
| 3431 | \f |
| 3432 | const char * |
| 3433 | md_atof (int type, char *litP, int *sizeP) |
| 3434 | { |
| 3435 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
| 3436 | } |
| 3437 | |
| 3438 | /* Write a value out to the object file, using the appropriate |
| 3439 | endianness. */ |
| 3440 | |
| 3441 | void |
| 3442 | md_number_to_chars (char *buf, valueT val, int n) |
| 3443 | { |
| 3444 | if (target_big_endian) |
| 3445 | number_to_chars_bigendian (buf, val, n); |
| 3446 | else if (target_little_endian_data |
| 3447 | && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC)) |
| 3448 | /* Output debug words, which are not in allocated sections, as big |
| 3449 | endian. */ |
| 3450 | number_to_chars_bigendian (buf, val, n); |
| 3451 | else if (target_little_endian_data || ! target_big_endian) |
| 3452 | number_to_chars_littleendian (buf, val, n); |
| 3453 | } |
| 3454 | \f |
| 3455 | /* Apply a fixS to the frags, now that we know the value it ought to |
| 3456 | hold. */ |
| 3457 | |
| 3458 | void |
| 3459 | md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED) |
| 3460 | { |
| 3461 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; |
| 3462 | offsetT val = * (offsetT *) valP; |
| 3463 | long insn; |
| 3464 | |
| 3465 | gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED); |
| 3466 | |
| 3467 | fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ |
| 3468 | |
| 3469 | /* SPARC ELF relocations don't use an addend in the data field. */ |
| 3470 | if (fixP->fx_addsy != NULL) |
| 3471 | { |
| 3472 | switch (fixP->fx_r_type) |
| 3473 | { |
| 3474 | case BFD_RELOC_SPARC_TLS_GD_HI22: |
| 3475 | case BFD_RELOC_SPARC_TLS_GD_LO10: |
| 3476 | case BFD_RELOC_SPARC_TLS_GD_ADD: |
| 3477 | case BFD_RELOC_SPARC_TLS_GD_CALL: |
| 3478 | case BFD_RELOC_SPARC_TLS_LDM_HI22: |
| 3479 | case BFD_RELOC_SPARC_TLS_LDM_LO10: |
| 3480 | case BFD_RELOC_SPARC_TLS_LDM_ADD: |
| 3481 | case BFD_RELOC_SPARC_TLS_LDM_CALL: |
| 3482 | case BFD_RELOC_SPARC_TLS_LDO_HIX22: |
| 3483 | case BFD_RELOC_SPARC_TLS_LDO_LOX10: |
| 3484 | case BFD_RELOC_SPARC_TLS_LDO_ADD: |
| 3485 | case BFD_RELOC_SPARC_TLS_IE_HI22: |
| 3486 | case BFD_RELOC_SPARC_TLS_IE_LO10: |
| 3487 | case BFD_RELOC_SPARC_TLS_IE_LD: |
| 3488 | case BFD_RELOC_SPARC_TLS_IE_LDX: |
| 3489 | case BFD_RELOC_SPARC_TLS_IE_ADD: |
| 3490 | case BFD_RELOC_SPARC_TLS_LE_HIX22: |
| 3491 | case BFD_RELOC_SPARC_TLS_LE_LOX10: |
| 3492 | case BFD_RELOC_SPARC_TLS_DTPMOD32: |
| 3493 | case BFD_RELOC_SPARC_TLS_DTPMOD64: |
| 3494 | case BFD_RELOC_SPARC_TLS_DTPOFF32: |
| 3495 | case BFD_RELOC_SPARC_TLS_DTPOFF64: |
| 3496 | case BFD_RELOC_SPARC_TLS_TPOFF32: |
| 3497 | case BFD_RELOC_SPARC_TLS_TPOFF64: |
| 3498 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
| 3499 | |
| 3500 | default: |
| 3501 | break; |
| 3502 | } |
| 3503 | |
| 3504 | return; |
| 3505 | } |
| 3506 | |
| 3507 | /* This is a hack. There should be a better way to |
| 3508 | handle this. Probably in terms of howto fields, once |
| 3509 | we can look at these fixups in terms of howtos. */ |
| 3510 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy) |
| 3511 | val += fixP->fx_where + fixP->fx_frag->fr_address; |
| 3512 | |
| 3513 | /* If this is a data relocation, just output VAL. */ |
| 3514 | |
| 3515 | if (fixP->fx_r_type == BFD_RELOC_8) |
| 3516 | { |
| 3517 | md_number_to_chars (buf, val, 1); |
| 3518 | } |
| 3519 | else if (fixP->fx_r_type == BFD_RELOC_16 |
| 3520 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA16) |
| 3521 | { |
| 3522 | md_number_to_chars (buf, val, 2); |
| 3523 | } |
| 3524 | else if (fixP->fx_r_type == BFD_RELOC_32 |
| 3525 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA32 |
| 3526 | || fixP->fx_r_type == BFD_RELOC_SPARC_REV32) |
| 3527 | { |
| 3528 | md_number_to_chars (buf, val, 4); |
| 3529 | } |
| 3530 | else if (fixP->fx_r_type == BFD_RELOC_64 |
| 3531 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA64) |
| 3532 | { |
| 3533 | md_number_to_chars (buf, val, 8); |
| 3534 | } |
| 3535 | else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
| 3536 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
| 3537 | { |
| 3538 | fixP->fx_done = 0; |
| 3539 | return; |
| 3540 | } |
| 3541 | else |
| 3542 | { |
| 3543 | /* It's a relocation against an instruction. */ |
| 3544 | |
| 3545 | if (INSN_BIG_ENDIAN) |
| 3546 | insn = bfd_getb32 ((unsigned char *) buf); |
| 3547 | else |
| 3548 | insn = bfd_getl32 ((unsigned char *) buf); |
| 3549 | |
| 3550 | switch (fixP->fx_r_type) |
| 3551 | { |
| 3552 | case BFD_RELOC_32_PCREL_S2: |
| 3553 | val = val >> 2; |
| 3554 | /* FIXME: This increment-by-one deserves a comment of why it's |
| 3555 | being done! */ |
| 3556 | if (! sparc_pic_code |
| 3557 | || fixP->fx_addsy == NULL |
| 3558 | || symbol_section_p (fixP->fx_addsy)) |
| 3559 | ++val; |
| 3560 | |
| 3561 | insn |= val & 0x3fffffff; |
| 3562 | |
| 3563 | /* See if we have a delay slot. In that case we attempt to |
| 3564 | optimize several cases transforming CALL instructions |
| 3565 | into branches. But we can only do that if the relocation |
| 3566 | can be completely resolved here, i.e. if no undefined |
| 3567 | symbol is associated with it. */ |
| 3568 | if (sparc_relax && fixP->fx_addsy == NULL |
| 3569 | && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix) |
| 3570 | { |
| 3571 | #define G0 0 |
| 3572 | #define O7 15 |
| 3573 | #define XCC (2 << 20) |
| 3574 | #define COND(x) (((x)&0xf)<<25) |
| 3575 | #define CONDA COND(0x8) |
| 3576 | #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC) |
| 3577 | #define INSN_BA (F2(0,2) | CONDA) |
| 3578 | #define INSN_OR F3(2, 0x2, 0) |
| 3579 | #define INSN_NOP F2(0,4) |
| 3580 | |
| 3581 | long delay; |
| 3582 | |
| 3583 | /* If the instruction is a call with either: |
| 3584 | restore |
| 3585 | arithmetic instruction with rd == %o7 |
| 3586 | where rs1 != %o7 and rs2 if it is register != %o7 |
| 3587 | then we can optimize if the call destination is near |
| 3588 | by changing the call into a branch always. */ |
| 3589 | if (INSN_BIG_ENDIAN) |
| 3590 | delay = bfd_getb32 ((unsigned char *) buf + 4); |
| 3591 | else |
| 3592 | delay = bfd_getl32 ((unsigned char *) buf + 4); |
| 3593 | if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2)) |
| 3594 | break; |
| 3595 | if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */ |
| 3596 | && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */ |
| 3597 | || ((delay & RD (~0)) != RD (O7)))) |
| 3598 | break; |
| 3599 | if ((delay & RS1 (~0)) == RS1 (O7) |
| 3600 | || ((delay & F3I (~0)) == 0 |
| 3601 | && (delay & RS2 (~0)) == RS2 (O7))) |
| 3602 | break; |
| 3603 | /* Ensure the branch will fit into simm22. */ |
| 3604 | if ((val & 0x3fe00000) |
| 3605 | && (val & 0x3fe00000) != 0x3fe00000) |
| 3606 | break; |
| 3607 | /* Check if the arch is v9 and branch will fit |
| 3608 | into simm19. */ |
| 3609 | if (((val & 0x3c0000) == 0 |
| 3610 | || (val & 0x3c0000) == 0x3c0000) |
| 3611 | && (sparc_arch_size == 64 |
| 3612 | || current_architecture >= SPARC_OPCODE_ARCH_V9)) |
| 3613 | /* ba,pt %xcc */ |
| 3614 | insn = INSN_BPA | (val & 0x7ffff); |
| 3615 | else |
| 3616 | /* ba */ |
| 3617 | insn = INSN_BA | (val & 0x3fffff); |
| 3618 | if (fixP->fx_where >= 4 |
| 3619 | && ((delay & (0xffffffff ^ RS1 (~0))) |
| 3620 | == (INSN_OR | RD (O7) | RS2 (G0)))) |
| 3621 | { |
| 3622 | long setter; |
| 3623 | int reg; |
| 3624 | |
| 3625 | if (INSN_BIG_ENDIAN) |
| 3626 | setter = bfd_getb32 ((unsigned char *) buf - 4); |
| 3627 | else |
| 3628 | setter = bfd_getl32 ((unsigned char *) buf - 4); |
| 3629 | if ((setter & (0xffffffff ^ RD (~0))) |
| 3630 | != (INSN_OR | RS1 (O7) | RS2 (G0))) |
| 3631 | break; |
| 3632 | /* The sequence was |
| 3633 | or %o7, %g0, %rN |
| 3634 | call foo |
| 3635 | or %rN, %g0, %o7 |
| 3636 | |
| 3637 | If call foo was replaced with ba, replace |
| 3638 | or %rN, %g0, %o7 with nop. */ |
| 3639 | reg = (delay & RS1 (~0)) >> 14; |
| 3640 | if (reg != ((setter & RD (~0)) >> 25) |
| 3641 | || reg == G0 || reg == O7) |
| 3642 | break; |
| 3643 | |
| 3644 | if (INSN_BIG_ENDIAN) |
| 3645 | bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4); |
| 3646 | else |
| 3647 | bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4); |
| 3648 | } |
| 3649 | } |
| 3650 | break; |
| 3651 | |
| 3652 | case BFD_RELOC_SPARC_11: |
| 3653 | if (! in_signed_range (val, 0x7ff)) |
| 3654 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 3655 | _("relocation overflow")); |
| 3656 | insn |= val & 0x7ff; |
| 3657 | break; |
| 3658 | |
| 3659 | case BFD_RELOC_SPARC_10: |
| 3660 | if (! in_signed_range (val, 0x3ff)) |
| 3661 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 3662 | _("relocation overflow")); |
| 3663 | insn |= val & 0x3ff; |
| 3664 | break; |
| 3665 | |
| 3666 | case BFD_RELOC_SPARC_7: |
| 3667 | if (! in_bitfield_range (val, 0x7f)) |
| 3668 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 3669 | _("relocation overflow")); |
| 3670 | insn |= val & 0x7f; |
| 3671 | break; |
| 3672 | |
| 3673 | case BFD_RELOC_SPARC_6: |
| 3674 | if (! in_bitfield_range (val, 0x3f)) |
| 3675 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 3676 | _("relocation overflow")); |
| 3677 | insn |= val & 0x3f; |
| 3678 | break; |
| 3679 | |
| 3680 | case BFD_RELOC_SPARC_5: |
| 3681 | if (! in_bitfield_range (val, 0x1f)) |
| 3682 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 3683 | _("relocation overflow")); |
| 3684 | insn |= val & 0x1f; |
| 3685 | break; |
| 3686 | |
| 3687 | case BFD_RELOC_SPARC_WDISP10: |
| 3688 | if ((val & 3) |
| 3689 | || val >= 0x007fc |
| 3690 | || val <= -(offsetT) 0x808) |
| 3691 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 3692 | _("relocation overflow")); |
| 3693 | /* FIXME: The +1 deserves a comment. */ |
| 3694 | val = (val >> 2) + 1; |
| 3695 | insn |= ((val & 0x300) << 11) |
| 3696 | | ((val & 0xff) << 5); |
| 3697 | break; |
| 3698 | |
| 3699 | case BFD_RELOC_SPARC_WDISP16: |
| 3700 | if ((val & 3) |
| 3701 | || val >= 0x1fffc |
| 3702 | || val <= -(offsetT) 0x20008) |
| 3703 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 3704 | _("relocation overflow")); |
| 3705 | /* FIXME: The +1 deserves a comment. */ |
| 3706 | val = (val >> 2) + 1; |
| 3707 | insn |= ((val & 0xc000) << 6) | (val & 0x3fff); |
| 3708 | break; |
| 3709 | |
| 3710 | case BFD_RELOC_SPARC_WDISP19: |
| 3711 | if ((val & 3) |
| 3712 | || val >= 0xffffc |
| 3713 | || val <= -(offsetT) 0x100008) |
| 3714 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 3715 | _("relocation overflow")); |
| 3716 | /* FIXME: The +1 deserves a comment. */ |
| 3717 | val = (val >> 2) + 1; |
| 3718 | insn |= val & 0x7ffff; |
| 3719 | break; |
| 3720 | |
| 3721 | case BFD_RELOC_SPARC_HH22: |
| 3722 | val = BSR (val, 32); |
| 3723 | /* Fall through. */ |
| 3724 | |
| 3725 | case BFD_RELOC_SPARC_LM22: |
| 3726 | case BFD_RELOC_HI22: |
| 3727 | if (!fixP->fx_addsy) |
| 3728 | insn |= (val >> 10) & 0x3fffff; |
| 3729 | else |
| 3730 | /* FIXME: Need comment explaining why we do this. */ |
| 3731 | insn &= ~0xffff; |
| 3732 | break; |
| 3733 | |
| 3734 | case BFD_RELOC_SPARC22: |
| 3735 | if (val & ~0x003fffff) |
| 3736 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 3737 | _("relocation overflow")); |
| 3738 | insn |= (val & 0x3fffff); |
| 3739 | break; |
| 3740 | |
| 3741 | case BFD_RELOC_SPARC_HM10: |
| 3742 | val = BSR (val, 32); |
| 3743 | /* Fall through. */ |
| 3744 | |
| 3745 | case BFD_RELOC_LO10: |
| 3746 | if (!fixP->fx_addsy) |
| 3747 | insn |= val & 0x3ff; |
| 3748 | else |
| 3749 | /* FIXME: Need comment explaining why we do this. */ |
| 3750 | insn &= ~0xff; |
| 3751 | break; |
| 3752 | |
| 3753 | case BFD_RELOC_SPARC_OLO10: |
| 3754 | val &= 0x3ff; |
| 3755 | val += fixP->tc_fix_data; |
| 3756 | /* Fall through. */ |
| 3757 | |
| 3758 | case BFD_RELOC_SPARC13: |
| 3759 | if (! in_signed_range (val, 0x1fff)) |
| 3760 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 3761 | _("relocation overflow")); |
| 3762 | insn |= val & 0x1fff; |
| 3763 | break; |
| 3764 | |
| 3765 | case BFD_RELOC_SPARC_WDISP22: |
| 3766 | val = (val >> 2) + 1; |
| 3767 | /* Fall through. */ |
| 3768 | case BFD_RELOC_SPARC_BASE22: |
| 3769 | insn |= val & 0x3fffff; |
| 3770 | break; |
| 3771 | |
| 3772 | case BFD_RELOC_SPARC_H34: |
| 3773 | if (!fixP->fx_addsy) |
| 3774 | { |
| 3775 | bfd_vma tval = val; |
| 3776 | tval >>= 12; |
| 3777 | insn |= tval & 0x3fffff; |
| 3778 | } |
| 3779 | break; |
| 3780 | |
| 3781 | case BFD_RELOC_SPARC_H44: |
| 3782 | if (!fixP->fx_addsy) |
| 3783 | { |
| 3784 | bfd_vma tval = val; |
| 3785 | tval >>= 22; |
| 3786 | insn |= tval & 0x3fffff; |
| 3787 | } |
| 3788 | break; |
| 3789 | |
| 3790 | case BFD_RELOC_SPARC_M44: |
| 3791 | if (!fixP->fx_addsy) |
| 3792 | insn |= (val >> 12) & 0x3ff; |
| 3793 | break; |
| 3794 | |
| 3795 | case BFD_RELOC_SPARC_L44: |
| 3796 | if (!fixP->fx_addsy) |
| 3797 | insn |= val & 0xfff; |
| 3798 | break; |
| 3799 | |
| 3800 | case BFD_RELOC_SPARC_HIX22: |
| 3801 | if (!fixP->fx_addsy) |
| 3802 | { |
| 3803 | val ^= ~(offsetT) 0; |
| 3804 | insn |= (val >> 10) & 0x3fffff; |
| 3805 | } |
| 3806 | break; |
| 3807 | |
| 3808 | case BFD_RELOC_SPARC_LOX10: |
| 3809 | if (!fixP->fx_addsy) |
| 3810 | insn |= 0x1c00 | (val & 0x3ff); |
| 3811 | break; |
| 3812 | |
| 3813 | case BFD_RELOC_NONE: |
| 3814 | default: |
| 3815 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 3816 | _("bad or unhandled relocation type: 0x%02x"), |
| 3817 | fixP->fx_r_type); |
| 3818 | break; |
| 3819 | } |
| 3820 | |
| 3821 | if (INSN_BIG_ENDIAN) |
| 3822 | bfd_putb32 (insn, (unsigned char *) buf); |
| 3823 | else |
| 3824 | bfd_putl32 (insn, (unsigned char *) buf); |
| 3825 | } |
| 3826 | |
| 3827 | /* Are we finished with this relocation now? */ |
| 3828 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) |
| 3829 | fixP->fx_done = 1; |
| 3830 | } |
| 3831 | |
| 3832 | /* Translate internal representation of relocation info to BFD target |
| 3833 | format. */ |
| 3834 | |
| 3835 | arelent ** |
| 3836 | tc_gen_reloc (asection *section, fixS *fixp) |
| 3837 | { |
| 3838 | static arelent *relocs[3]; |
| 3839 | arelent *reloc; |
| 3840 | bfd_reloc_code_real_type code; |
| 3841 | |
| 3842 | relocs[0] = reloc = XNEW (arelent); |
| 3843 | relocs[1] = NULL; |
| 3844 | |
| 3845 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
| 3846 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
| 3847 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
| 3848 | |
| 3849 | switch (fixp->fx_r_type) |
| 3850 | { |
| 3851 | case BFD_RELOC_8: |
| 3852 | case BFD_RELOC_16: |
| 3853 | case BFD_RELOC_32: |
| 3854 | case BFD_RELOC_64: |
| 3855 | if (fixp->fx_pcrel) |
| 3856 | { |
| 3857 | switch (fixp->fx_size) |
| 3858 | { |
| 3859 | default: |
| 3860 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 3861 | _("can not do %d byte pc-relative relocation"), |
| 3862 | fixp->fx_size); |
| 3863 | code = fixp->fx_r_type; |
| 3864 | fixp->fx_pcrel = 0; |
| 3865 | break; |
| 3866 | case 1: code = BFD_RELOC_8_PCREL; break; |
| 3867 | case 2: code = BFD_RELOC_16_PCREL; break; |
| 3868 | case 4: code = BFD_RELOC_32_PCREL; break; |
| 3869 | #ifdef BFD64 |
| 3870 | case 8: code = BFD_RELOC_64_PCREL; break; |
| 3871 | #endif |
| 3872 | } |
| 3873 | if (fixp->fx_pcrel) |
| 3874 | fixp->fx_addnumber = fixp->fx_offset; |
| 3875 | break; |
| 3876 | } |
| 3877 | /* Fall through. */ |
| 3878 | case BFD_RELOC_HI22: |
| 3879 | case BFD_RELOC_LO10: |
| 3880 | case BFD_RELOC_32_PCREL_S2: |
| 3881 | case BFD_RELOC_SPARC13: |
| 3882 | case BFD_RELOC_SPARC22: |
| 3883 | case BFD_RELOC_SPARC_PC22: |
| 3884 | case BFD_RELOC_SPARC_PC10: |
| 3885 | case BFD_RELOC_SPARC_BASE13: |
| 3886 | case BFD_RELOC_SPARC_WDISP10: |
| 3887 | case BFD_RELOC_SPARC_WDISP16: |
| 3888 | case BFD_RELOC_SPARC_WDISP19: |
| 3889 | case BFD_RELOC_SPARC_WDISP22: |
| 3890 | case BFD_RELOC_SPARC_5: |
| 3891 | case BFD_RELOC_SPARC_6: |
| 3892 | case BFD_RELOC_SPARC_7: |
| 3893 | case BFD_RELOC_SPARC_10: |
| 3894 | case BFD_RELOC_SPARC_11: |
| 3895 | case BFD_RELOC_SPARC_HH22: |
| 3896 | case BFD_RELOC_SPARC_HM10: |
| 3897 | case BFD_RELOC_SPARC_LM22: |
| 3898 | case BFD_RELOC_SPARC_PC_HH22: |
| 3899 | case BFD_RELOC_SPARC_PC_HM10: |
| 3900 | case BFD_RELOC_SPARC_PC_LM22: |
| 3901 | case BFD_RELOC_SPARC_H34: |
| 3902 | case BFD_RELOC_SPARC_H44: |
| 3903 | case BFD_RELOC_SPARC_M44: |
| 3904 | case BFD_RELOC_SPARC_L44: |
| 3905 | case BFD_RELOC_SPARC_HIX22: |
| 3906 | case BFD_RELOC_SPARC_LOX10: |
| 3907 | case BFD_RELOC_SPARC_REV32: |
| 3908 | case BFD_RELOC_SPARC_OLO10: |
| 3909 | case BFD_RELOC_SPARC_UA16: |
| 3910 | case BFD_RELOC_SPARC_UA32: |
| 3911 | case BFD_RELOC_SPARC_UA64: |
| 3912 | case BFD_RELOC_8_PCREL: |
| 3913 | case BFD_RELOC_16_PCREL: |
| 3914 | case BFD_RELOC_32_PCREL: |
| 3915 | case BFD_RELOC_64_PCREL: |
| 3916 | case BFD_RELOC_SPARC_PLT32: |
| 3917 | case BFD_RELOC_SPARC_PLT64: |
| 3918 | case BFD_RELOC_VTABLE_ENTRY: |
| 3919 | case BFD_RELOC_VTABLE_INHERIT: |
| 3920 | case BFD_RELOC_SPARC_TLS_GD_HI22: |
| 3921 | case BFD_RELOC_SPARC_TLS_GD_LO10: |
| 3922 | case BFD_RELOC_SPARC_TLS_GD_ADD: |
| 3923 | case BFD_RELOC_SPARC_TLS_GD_CALL: |
| 3924 | case BFD_RELOC_SPARC_TLS_LDM_HI22: |
| 3925 | case BFD_RELOC_SPARC_TLS_LDM_LO10: |
| 3926 | case BFD_RELOC_SPARC_TLS_LDM_ADD: |
| 3927 | case BFD_RELOC_SPARC_TLS_LDM_CALL: |
| 3928 | case BFD_RELOC_SPARC_TLS_LDO_HIX22: |
| 3929 | case BFD_RELOC_SPARC_TLS_LDO_LOX10: |
| 3930 | case BFD_RELOC_SPARC_TLS_LDO_ADD: |
| 3931 | case BFD_RELOC_SPARC_TLS_IE_HI22: |
| 3932 | case BFD_RELOC_SPARC_TLS_IE_LO10: |
| 3933 | case BFD_RELOC_SPARC_TLS_IE_LD: |
| 3934 | case BFD_RELOC_SPARC_TLS_IE_LDX: |
| 3935 | case BFD_RELOC_SPARC_TLS_IE_ADD: |
| 3936 | case BFD_RELOC_SPARC_TLS_LE_HIX22: |
| 3937 | case BFD_RELOC_SPARC_TLS_LE_LOX10: |
| 3938 | case BFD_RELOC_SPARC_TLS_DTPOFF32: |
| 3939 | case BFD_RELOC_SPARC_TLS_DTPOFF64: |
| 3940 | case BFD_RELOC_SPARC_GOTDATA_OP_HIX22: |
| 3941 | case BFD_RELOC_SPARC_GOTDATA_OP_LOX10: |
| 3942 | case BFD_RELOC_SPARC_GOTDATA_OP: |
| 3943 | code = fixp->fx_r_type; |
| 3944 | break; |
| 3945 | default: |
| 3946 | abort (); |
| 3947 | return NULL; |
| 3948 | } |
| 3949 | |
| 3950 | /* If we are generating PIC code, we need to generate a different |
| 3951 | set of relocs. */ |
| 3952 | |
| 3953 | #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" |
| 3954 | #ifdef TE_VXWORKS |
| 3955 | #define GOTT_BASE "__GOTT_BASE__" |
| 3956 | #define GOTT_INDEX "__GOTT_INDEX__" |
| 3957 | #endif |
| 3958 | |
| 3959 | /* This code must be parallel to tc_fix_adjustable. */ |
| 3960 | |
| 3961 | if (sparc_pic_code) |
| 3962 | { |
| 3963 | switch (code) |
| 3964 | { |
| 3965 | case BFD_RELOC_32_PCREL_S2: |
| 3966 | if (generic_force_reloc (fixp)) |
| 3967 | code = BFD_RELOC_SPARC_WPLT30; |
| 3968 | break; |
| 3969 | case BFD_RELOC_HI22: |
| 3970 | code = BFD_RELOC_SPARC_GOT22; |
| 3971 | if (fixp->fx_addsy != NULL) |
| 3972 | { |
| 3973 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) |
| 3974 | code = BFD_RELOC_SPARC_PC22; |
| 3975 | #ifdef TE_VXWORKS |
| 3976 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 |
| 3977 | || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) |
| 3978 | code = BFD_RELOC_HI22; /* Unchanged. */ |
| 3979 | #endif |
| 3980 | } |
| 3981 | break; |
| 3982 | case BFD_RELOC_LO10: |
| 3983 | code = BFD_RELOC_SPARC_GOT10; |
| 3984 | if (fixp->fx_addsy != NULL) |
| 3985 | { |
| 3986 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) |
| 3987 | code = BFD_RELOC_SPARC_PC10; |
| 3988 | #ifdef TE_VXWORKS |
| 3989 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 |
| 3990 | || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) |
| 3991 | code = BFD_RELOC_LO10; /* Unchanged. */ |
| 3992 | #endif |
| 3993 | } |
| 3994 | break; |
| 3995 | case BFD_RELOC_SPARC13: |
| 3996 | code = BFD_RELOC_SPARC_GOT13; |
| 3997 | break; |
| 3998 | default: |
| 3999 | break; |
| 4000 | } |
| 4001 | } |
| 4002 | |
| 4003 | /* Nothing is aligned in DWARF debugging sections. */ |
| 4004 | if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING) |
| 4005 | switch (code) |
| 4006 | { |
| 4007 | case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break; |
| 4008 | case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break; |
| 4009 | case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break; |
| 4010 | default: break; |
| 4011 | } |
| 4012 | |
| 4013 | if (code == BFD_RELOC_SPARC_OLO10) |
| 4014 | reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10); |
| 4015 | else |
| 4016 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
| 4017 | if (reloc->howto == 0) |
| 4018 | { |
| 4019 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 4020 | _("internal error: can't export reloc type %d (`%s')"), |
| 4021 | fixp->fx_r_type, bfd_get_reloc_code_name (code)); |
| 4022 | xfree (reloc); |
| 4023 | relocs[0] = NULL; |
| 4024 | return relocs; |
| 4025 | } |
| 4026 | |
| 4027 | /* @@ Why fx_addnumber sometimes and fx_offset other times? */ |
| 4028 | if (code != BFD_RELOC_32_PCREL_S2 |
| 4029 | && code != BFD_RELOC_SPARC_WDISP22 |
| 4030 | && code != BFD_RELOC_SPARC_WDISP16 |
| 4031 | && code != BFD_RELOC_SPARC_WDISP19 |
| 4032 | && code != BFD_RELOC_SPARC_WDISP10 |
| 4033 | && code != BFD_RELOC_SPARC_WPLT30 |
| 4034 | && code != BFD_RELOC_SPARC_TLS_GD_CALL |
| 4035 | && code != BFD_RELOC_SPARC_TLS_LDM_CALL) |
| 4036 | reloc->addend = fixp->fx_addnumber; |
| 4037 | else if (symbol_section_p (fixp->fx_addsy)) |
| 4038 | reloc->addend = (section->vma |
| 4039 | + fixp->fx_addnumber |
| 4040 | + md_pcrel_from (fixp)); |
| 4041 | else |
| 4042 | reloc->addend = fixp->fx_offset; |
| 4043 | |
| 4044 | /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13 |
| 4045 | on the same location. */ |
| 4046 | if (code == BFD_RELOC_SPARC_OLO10) |
| 4047 | { |
| 4048 | relocs[1] = reloc = XNEW (arelent); |
| 4049 | relocs[2] = NULL; |
| 4050 | |
| 4051 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
| 4052 | *reloc->sym_ptr_ptr |
| 4053 | = symbol_get_bfdsym (section_symbol (absolute_section)); |
| 4054 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
| 4055 | reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13); |
| 4056 | reloc->addend = fixp->tc_fix_data; |
| 4057 | } |
| 4058 | |
| 4059 | return relocs; |
| 4060 | } |
| 4061 | \f |
| 4062 | /* We have no need to default values of symbols. */ |
| 4063 | |
| 4064 | symbolS * |
| 4065 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
| 4066 | { |
| 4067 | return 0; |
| 4068 | } |
| 4069 | |
| 4070 | /* Round up a section size to the appropriate boundary. */ |
| 4071 | |
| 4072 | valueT |
| 4073 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
| 4074 | { |
| 4075 | return size; |
| 4076 | } |
| 4077 | |
| 4078 | /* Exactly what point is a PC-relative offset relative TO? |
| 4079 | On the sparc, they're relative to the address of the offset, plus |
| 4080 | its size. This gets us to the following instruction. |
| 4081 | (??? Is this right? FIXME-SOON) */ |
| 4082 | long |
| 4083 | md_pcrel_from (fixS *fixP) |
| 4084 | { |
| 4085 | long ret; |
| 4086 | |
| 4087 | ret = fixP->fx_where + fixP->fx_frag->fr_address; |
| 4088 | if (! sparc_pic_code |
| 4089 | || fixP->fx_addsy == NULL |
| 4090 | || symbol_section_p (fixP->fx_addsy)) |
| 4091 | ret += fixP->fx_size; |
| 4092 | return ret; |
| 4093 | } |
| 4094 | \f |
| 4095 | /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power |
| 4096 | of two. */ |
| 4097 | |
| 4098 | static int |
| 4099 | mylog2 (int value) |
| 4100 | { |
| 4101 | int shift; |
| 4102 | |
| 4103 | if (value <= 0) |
| 4104 | return -1; |
| 4105 | |
| 4106 | for (shift = 0; (value & 1) == 0; value >>= 1) |
| 4107 | ++shift; |
| 4108 | |
| 4109 | return (value == 1) ? shift : -1; |
| 4110 | } |
| 4111 | |
| 4112 | /* Sort of like s_lcomm. */ |
| 4113 | |
| 4114 | static void |
| 4115 | s_reserve (int ignore ATTRIBUTE_UNUSED) |
| 4116 | { |
| 4117 | char *name; |
| 4118 | char *p; |
| 4119 | char c; |
| 4120 | int align; |
| 4121 | int size; |
| 4122 | int temp; |
| 4123 | symbolS *symbolP; |
| 4124 | |
| 4125 | c = get_symbol_name (&name); |
| 4126 | p = input_line_pointer; |
| 4127 | *p = c; |
| 4128 | SKIP_WHITESPACE_AFTER_NAME (); |
| 4129 | |
| 4130 | if (*input_line_pointer != ',') |
| 4131 | { |
| 4132 | as_bad (_("Expected comma after name")); |
| 4133 | ignore_rest_of_line (); |
| 4134 | return; |
| 4135 | } |
| 4136 | |
| 4137 | ++input_line_pointer; |
| 4138 | |
| 4139 | if ((size = get_absolute_expression ()) < 0) |
| 4140 | { |
| 4141 | as_bad (_("BSS length (%d.) <0! Ignored."), size); |
| 4142 | ignore_rest_of_line (); |
| 4143 | return; |
| 4144 | } /* Bad length. */ |
| 4145 | |
| 4146 | *p = 0; |
| 4147 | symbolP = symbol_find_or_make (name); |
| 4148 | *p = c; |
| 4149 | |
| 4150 | if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0 |
| 4151 | && strncmp (input_line_pointer, ",\".bss\"", 7) != 0) |
| 4152 | { |
| 4153 | as_bad (_("bad .reserve segment -- expected BSS segment")); |
| 4154 | return; |
| 4155 | } |
| 4156 | |
| 4157 | if (input_line_pointer[2] == '.') |
| 4158 | input_line_pointer += 7; |
| 4159 | else |
| 4160 | input_line_pointer += 6; |
| 4161 | SKIP_WHITESPACE (); |
| 4162 | |
| 4163 | if (*input_line_pointer == ',') |
| 4164 | { |
| 4165 | ++input_line_pointer; |
| 4166 | |
| 4167 | SKIP_WHITESPACE (); |
| 4168 | if (*input_line_pointer == '\n') |
| 4169 | { |
| 4170 | as_bad (_("missing alignment")); |
| 4171 | ignore_rest_of_line (); |
| 4172 | return; |
| 4173 | } |
| 4174 | |
| 4175 | align = (int) get_absolute_expression (); |
| 4176 | |
| 4177 | if (align < 0) |
| 4178 | { |
| 4179 | as_bad (_("negative alignment")); |
| 4180 | ignore_rest_of_line (); |
| 4181 | return; |
| 4182 | } |
| 4183 | |
| 4184 | if (align != 0) |
| 4185 | { |
| 4186 | temp = mylog2 (align); |
| 4187 | if (temp < 0) |
| 4188 | { |
| 4189 | as_bad (_("alignment not a power of 2")); |
| 4190 | ignore_rest_of_line (); |
| 4191 | return; |
| 4192 | } |
| 4193 | |
| 4194 | align = temp; |
| 4195 | } |
| 4196 | |
| 4197 | record_alignment (bss_section, align); |
| 4198 | } |
| 4199 | else |
| 4200 | align = 0; |
| 4201 | |
| 4202 | if (!S_IS_DEFINED (symbolP)) |
| 4203 | { |
| 4204 | if (! need_pass_2) |
| 4205 | { |
| 4206 | char *pfrag; |
| 4207 | segT current_seg = now_seg; |
| 4208 | subsegT current_subseg = now_subseg; |
| 4209 | |
| 4210 | /* Switch to bss. */ |
| 4211 | subseg_set (bss_section, 1); |
| 4212 | |
| 4213 | if (align) |
| 4214 | /* Do alignment. */ |
| 4215 | frag_align (align, 0, 0); |
| 4216 | |
| 4217 | /* Detach from old frag. */ |
| 4218 | if (S_GET_SEGMENT (symbolP) == bss_section) |
| 4219 | symbol_get_frag (symbolP)->fr_symbol = NULL; |
| 4220 | |
| 4221 | symbol_set_frag (symbolP, frag_now); |
| 4222 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, |
| 4223 | (offsetT) size, (char *) 0); |
| 4224 | *pfrag = 0; |
| 4225 | |
| 4226 | S_SET_SEGMENT (symbolP, bss_section); |
| 4227 | |
| 4228 | subseg_set (current_seg, current_subseg); |
| 4229 | |
| 4230 | S_SET_SIZE (symbolP, size); |
| 4231 | } |
| 4232 | } |
| 4233 | else |
| 4234 | { |
| 4235 | as_warn (_("Ignoring attempt to re-define symbol %s"), |
| 4236 | S_GET_NAME (symbolP)); |
| 4237 | } |
| 4238 | |
| 4239 | demand_empty_rest_of_line (); |
| 4240 | } |
| 4241 | |
| 4242 | static void |
| 4243 | s_common (int ignore ATTRIBUTE_UNUSED) |
| 4244 | { |
| 4245 | char *name; |
| 4246 | char c; |
| 4247 | char *p; |
| 4248 | offsetT temp, size; |
| 4249 | symbolS *symbolP; |
| 4250 | |
| 4251 | c = get_symbol_name (&name); |
| 4252 | /* Just after name is now '\0'. */ |
| 4253 | p = input_line_pointer; |
| 4254 | *p = c; |
| 4255 | SKIP_WHITESPACE_AFTER_NAME (); |
| 4256 | if (*input_line_pointer != ',') |
| 4257 | { |
| 4258 | as_bad (_("Expected comma after symbol-name")); |
| 4259 | ignore_rest_of_line (); |
| 4260 | return; |
| 4261 | } |
| 4262 | |
| 4263 | /* Skip ','. */ |
| 4264 | input_line_pointer++; |
| 4265 | |
| 4266 | if ((temp = get_absolute_expression ()) < 0) |
| 4267 | { |
| 4268 | as_bad (_(".COMMon length (%lu) out of range ignored"), |
| 4269 | (unsigned long) temp); |
| 4270 | ignore_rest_of_line (); |
| 4271 | return; |
| 4272 | } |
| 4273 | size = temp; |
| 4274 | *p = 0; |
| 4275 | symbolP = symbol_find_or_make (name); |
| 4276 | *p = c; |
| 4277 | if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) |
| 4278 | { |
| 4279 | as_bad (_("Ignoring attempt to re-define symbol")); |
| 4280 | ignore_rest_of_line (); |
| 4281 | return; |
| 4282 | } |
| 4283 | if (S_GET_VALUE (symbolP) != 0) |
| 4284 | { |
| 4285 | if (S_GET_VALUE (symbolP) != (valueT) size) |
| 4286 | { |
| 4287 | as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."), |
| 4288 | S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size); |
| 4289 | } |
| 4290 | } |
| 4291 | know (symbol_get_frag (symbolP) == &zero_address_frag); |
| 4292 | if (*input_line_pointer != ',') |
| 4293 | { |
| 4294 | as_bad (_("Expected comma after common length")); |
| 4295 | ignore_rest_of_line (); |
| 4296 | return; |
| 4297 | } |
| 4298 | input_line_pointer++; |
| 4299 | SKIP_WHITESPACE (); |
| 4300 | if (*input_line_pointer != '"') |
| 4301 | { |
| 4302 | temp = get_absolute_expression (); |
| 4303 | |
| 4304 | if (temp < 0) |
| 4305 | { |
| 4306 | as_bad (_("negative alignment")); |
| 4307 | ignore_rest_of_line (); |
| 4308 | return; |
| 4309 | } |
| 4310 | |
| 4311 | if (symbol_get_obj (symbolP)->local) |
| 4312 | { |
| 4313 | segT old_sec; |
| 4314 | int old_subsec; |
| 4315 | int align; |
| 4316 | |
| 4317 | old_sec = now_seg; |
| 4318 | old_subsec = now_subseg; |
| 4319 | |
| 4320 | if (temp == 0) |
| 4321 | align = 0; |
| 4322 | else |
| 4323 | align = mylog2 (temp); |
| 4324 | |
| 4325 | if (align < 0) |
| 4326 | { |
| 4327 | as_bad (_("alignment not a power of 2")); |
| 4328 | ignore_rest_of_line (); |
| 4329 | return; |
| 4330 | } |
| 4331 | |
| 4332 | record_alignment (bss_section, align); |
| 4333 | subseg_set (bss_section, 0); |
| 4334 | if (align) |
| 4335 | frag_align (align, 0, 0); |
| 4336 | if (S_GET_SEGMENT (symbolP) == bss_section) |
| 4337 | symbol_get_frag (symbolP)->fr_symbol = 0; |
| 4338 | symbol_set_frag (symbolP, frag_now); |
| 4339 | p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, |
| 4340 | (offsetT) size, (char *) 0); |
| 4341 | *p = 0; |
| 4342 | S_SET_SEGMENT (symbolP, bss_section); |
| 4343 | S_CLEAR_EXTERNAL (symbolP); |
| 4344 | S_SET_SIZE (symbolP, size); |
| 4345 | subseg_set (old_sec, old_subsec); |
| 4346 | } |
| 4347 | else |
| 4348 | { |
| 4349 | allocate_common: |
| 4350 | S_SET_VALUE (symbolP, (valueT) size); |
| 4351 | S_SET_ALIGN (symbolP, temp); |
| 4352 | S_SET_SIZE (symbolP, size); |
| 4353 | S_SET_EXTERNAL (symbolP); |
| 4354 | S_SET_SEGMENT (symbolP, bfd_com_section_ptr); |
| 4355 | } |
| 4356 | } |
| 4357 | else |
| 4358 | { |
| 4359 | input_line_pointer++; |
| 4360 | /* @@ Some use the dot, some don't. Can we get some consistency?? */ |
| 4361 | if (*input_line_pointer == '.') |
| 4362 | input_line_pointer++; |
| 4363 | /* @@ Some say data, some say bss. */ |
| 4364 | if (strncmp (input_line_pointer, "bss\"", 4) |
| 4365 | && strncmp (input_line_pointer, "data\"", 5)) |
| 4366 | { |
| 4367 | while (*--input_line_pointer != '"') |
| 4368 | ; |
| 4369 | input_line_pointer--; |
| 4370 | goto bad_common_segment; |
| 4371 | } |
| 4372 | while (*input_line_pointer++ != '"') |
| 4373 | ; |
| 4374 | goto allocate_common; |
| 4375 | } |
| 4376 | |
| 4377 | symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; |
| 4378 | |
| 4379 | demand_empty_rest_of_line (); |
| 4380 | return; |
| 4381 | |
| 4382 | { |
| 4383 | bad_common_segment: |
| 4384 | p = input_line_pointer; |
| 4385 | while (*p && *p != '\n') |
| 4386 | p++; |
| 4387 | c = *p; |
| 4388 | *p = '\0'; |
| 4389 | as_bad (_("bad .common segment %s"), input_line_pointer + 1); |
| 4390 | *p = c; |
| 4391 | input_line_pointer = p; |
| 4392 | ignore_rest_of_line (); |
| 4393 | return; |
| 4394 | } |
| 4395 | } |
| 4396 | |
| 4397 | /* Handle the .empty pseudo-op. This suppresses the warnings about |
| 4398 | invalid delay slot usage. */ |
| 4399 | |
| 4400 | static void |
| 4401 | s_empty (int ignore ATTRIBUTE_UNUSED) |
| 4402 | { |
| 4403 | /* The easy way to implement is to just forget about the last |
| 4404 | instruction. */ |
| 4405 | last_insn = NULL; |
| 4406 | } |
| 4407 | |
| 4408 | static void |
| 4409 | s_seg (int ignore ATTRIBUTE_UNUSED) |
| 4410 | { |
| 4411 | |
| 4412 | if (strncmp (input_line_pointer, "\"text\"", 6) == 0) |
| 4413 | { |
| 4414 | input_line_pointer += 6; |
| 4415 | s_text (0); |
| 4416 | return; |
| 4417 | } |
| 4418 | if (strncmp (input_line_pointer, "\"data\"", 6) == 0) |
| 4419 | { |
| 4420 | input_line_pointer += 6; |
| 4421 | s_data (0); |
| 4422 | return; |
| 4423 | } |
| 4424 | if (strncmp (input_line_pointer, "\"data1\"", 7) == 0) |
| 4425 | { |
| 4426 | input_line_pointer += 7; |
| 4427 | s_data1 (); |
| 4428 | return; |
| 4429 | } |
| 4430 | if (strncmp (input_line_pointer, "\"bss\"", 5) == 0) |
| 4431 | { |
| 4432 | input_line_pointer += 5; |
| 4433 | /* We only support 2 segments -- text and data -- for now, so |
| 4434 | things in the "bss segment" will have to go into data for now. |
| 4435 | You can still allocate SEG_BSS stuff with .lcomm or .reserve. */ |
| 4436 | subseg_set (data_section, 255); /* FIXME-SOMEDAY. */ |
| 4437 | return; |
| 4438 | } |
| 4439 | as_bad (_("Unknown segment type")); |
| 4440 | demand_empty_rest_of_line (); |
| 4441 | } |
| 4442 | |
| 4443 | static void |
| 4444 | s_data1 (void) |
| 4445 | { |
| 4446 | subseg_set (data_section, 1); |
| 4447 | demand_empty_rest_of_line (); |
| 4448 | } |
| 4449 | |
| 4450 | static void |
| 4451 | s_proc (int ignore ATTRIBUTE_UNUSED) |
| 4452 | { |
| 4453 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) |
| 4454 | { |
| 4455 | ++input_line_pointer; |
| 4456 | } |
| 4457 | ++input_line_pointer; |
| 4458 | } |
| 4459 | |
| 4460 | /* This static variable is set by s_uacons to tell sparc_cons_align |
| 4461 | that the expression does not need to be aligned. */ |
| 4462 | |
| 4463 | static int sparc_no_align_cons = 0; |
| 4464 | |
| 4465 | /* This handles the unaligned space allocation pseudo-ops, such as |
| 4466 | .uaword. .uaword is just like .word, but the value does not need |
| 4467 | to be aligned. */ |
| 4468 | |
| 4469 | static void |
| 4470 | s_uacons (int bytes) |
| 4471 | { |
| 4472 | /* Tell sparc_cons_align not to align this value. */ |
| 4473 | sparc_no_align_cons = 1; |
| 4474 | cons (bytes); |
| 4475 | sparc_no_align_cons = 0; |
| 4476 | } |
| 4477 | |
| 4478 | /* This handles the native word allocation pseudo-op .nword. |
| 4479 | For sparc_arch_size 32 it is equivalent to .word, for |
| 4480 | sparc_arch_size 64 it is equivalent to .xword. */ |
| 4481 | |
| 4482 | static void |
| 4483 | s_ncons (int bytes ATTRIBUTE_UNUSED) |
| 4484 | { |
| 4485 | cons (sparc_arch_size == 32 ? 4 : 8); |
| 4486 | } |
| 4487 | |
| 4488 | /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a |
| 4489 | global register. |
| 4490 | The syntax is: |
| 4491 | |
| 4492 | .register %g[2367],{#scratch|symbolname|#ignore} |
| 4493 | */ |
| 4494 | |
| 4495 | static void |
| 4496 | s_register (int ignore ATTRIBUTE_UNUSED) |
| 4497 | { |
| 4498 | char c; |
| 4499 | int reg; |
| 4500 | int flags; |
| 4501 | char *regname; |
| 4502 | |
| 4503 | if (input_line_pointer[0] != '%' |
| 4504 | || input_line_pointer[1] != 'g' |
| 4505 | || ((input_line_pointer[2] & ~1) != '2' |
| 4506 | && (input_line_pointer[2] & ~1) != '6') |
| 4507 | || input_line_pointer[3] != ',') |
| 4508 | as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); |
| 4509 | reg = input_line_pointer[2] - '0'; |
| 4510 | input_line_pointer += 4; |
| 4511 | |
| 4512 | if (*input_line_pointer == '#') |
| 4513 | { |
| 4514 | ++input_line_pointer; |
| 4515 | c = get_symbol_name (®name); |
| 4516 | if (strcmp (regname, "scratch") && strcmp (regname, "ignore")) |
| 4517 | as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); |
| 4518 | if (regname[0] == 'i') |
| 4519 | regname = NULL; |
| 4520 | else |
| 4521 | regname = (char *) ""; |
| 4522 | } |
| 4523 | else |
| 4524 | { |
| 4525 | c = get_symbol_name (®name); |
| 4526 | } |
| 4527 | |
| 4528 | if (sparc_arch_size == 64) |
| 4529 | { |
| 4530 | if (globals[reg]) |
| 4531 | { |
| 4532 | if ((regname && globals[reg] != (symbolS *) 1 |
| 4533 | && strcmp (S_GET_NAME (globals[reg]), regname)) |
| 4534 | || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1))) |
| 4535 | as_bad (_("redefinition of global register")); |
| 4536 | } |
| 4537 | else |
| 4538 | { |
| 4539 | if (regname == NULL) |
| 4540 | globals[reg] = (symbolS *) 1; |
| 4541 | else |
| 4542 | { |
| 4543 | if (*regname) |
| 4544 | { |
| 4545 | if (symbol_find (regname)) |
| 4546 | as_bad (_("Register symbol %s already defined."), |
| 4547 | regname); |
| 4548 | } |
| 4549 | globals[reg] = symbol_make (regname); |
| 4550 | flags = symbol_get_bfdsym (globals[reg])->flags; |
| 4551 | if (! *regname) |
| 4552 | flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK); |
| 4553 | if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK))) |
| 4554 | flags |= BSF_GLOBAL; |
| 4555 | symbol_get_bfdsym (globals[reg])->flags = flags; |
| 4556 | S_SET_VALUE (globals[reg], (valueT) reg); |
| 4557 | S_SET_ALIGN (globals[reg], reg); |
| 4558 | S_SET_SIZE (globals[reg], 0); |
| 4559 | /* Although we actually want undefined_section here, |
| 4560 | we have to use absolute_section, because otherwise |
| 4561 | generic as code will make it a COM section. |
| 4562 | We fix this up in sparc_adjust_symtab. */ |
| 4563 | S_SET_SEGMENT (globals[reg], absolute_section); |
| 4564 | S_SET_OTHER (globals[reg], 0); |
| 4565 | elf_symbol (symbol_get_bfdsym (globals[reg])) |
| 4566 | ->internal_elf_sym.st_info = |
| 4567 | ELF_ST_INFO(STB_GLOBAL, STT_REGISTER); |
| 4568 | elf_symbol (symbol_get_bfdsym (globals[reg])) |
| 4569 | ->internal_elf_sym.st_shndx = SHN_UNDEF; |
| 4570 | } |
| 4571 | } |
| 4572 | } |
| 4573 | |
| 4574 | (void) restore_line_pointer (c); |
| 4575 | |
| 4576 | demand_empty_rest_of_line (); |
| 4577 | } |
| 4578 | |
| 4579 | /* Adjust the symbol table. We set undefined sections for STT_REGISTER |
| 4580 | symbols which need it. */ |
| 4581 | |
| 4582 | void |
| 4583 | sparc_adjust_symtab (void) |
| 4584 | { |
| 4585 | symbolS *sym; |
| 4586 | |
| 4587 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
| 4588 | { |
| 4589 | if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) |
| 4590 | ->internal_elf_sym.st_info) != STT_REGISTER) |
| 4591 | continue; |
| 4592 | |
| 4593 | if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) |
| 4594 | ->internal_elf_sym.st_shndx != SHN_UNDEF)) |
| 4595 | continue; |
| 4596 | |
| 4597 | S_SET_SEGMENT (sym, undefined_section); |
| 4598 | } |
| 4599 | } |
| 4600 | |
| 4601 | /* If the --enforce-aligned-data option is used, we require .word, |
| 4602 | et. al., to be aligned correctly. We do it by setting up an |
| 4603 | rs_align_code frag, and checking in HANDLE_ALIGN to make sure that |
| 4604 | no unexpected alignment was introduced. |
| 4605 | |
| 4606 | The SunOS and Solaris native assemblers enforce aligned data by |
| 4607 | default. We don't want to do that, because gcc can deliberately |
| 4608 | generate misaligned data if the packed attribute is used. Instead, |
| 4609 | we permit misaligned data by default, and permit the user to set an |
| 4610 | option to check for it. */ |
| 4611 | |
| 4612 | void |
| 4613 | sparc_cons_align (int nbytes) |
| 4614 | { |
| 4615 | int nalign; |
| 4616 | |
| 4617 | /* Only do this if we are enforcing aligned data. */ |
| 4618 | if (! enforce_aligned_data) |
| 4619 | return; |
| 4620 | |
| 4621 | /* Don't align if this is an unaligned pseudo-op. */ |
| 4622 | if (sparc_no_align_cons) |
| 4623 | return; |
| 4624 | |
| 4625 | nalign = mylog2 (nbytes); |
| 4626 | if (nalign == 0) |
| 4627 | return; |
| 4628 | |
| 4629 | gas_assert (nalign > 0); |
| 4630 | |
| 4631 | if (now_seg == absolute_section) |
| 4632 | { |
| 4633 | if ((abs_section_offset & ((1 << nalign) - 1)) != 0) |
| 4634 | as_bad (_("misaligned data")); |
| 4635 | return; |
| 4636 | } |
| 4637 | |
| 4638 | frag_var (rs_align_test, 1, 1, (relax_substateT) 0, |
| 4639 | (symbolS *) NULL, (offsetT) nalign, (char *) NULL); |
| 4640 | |
| 4641 | record_alignment (now_seg, nalign); |
| 4642 | } |
| 4643 | |
| 4644 | /* This is called from HANDLE_ALIGN in tc-sparc.h. */ |
| 4645 | |
| 4646 | void |
| 4647 | sparc_handle_align (fragS *fragp) |
| 4648 | { |
| 4649 | int count, fix; |
| 4650 | char *p; |
| 4651 | |
| 4652 | count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
| 4653 | |
| 4654 | switch (fragp->fr_type) |
| 4655 | { |
| 4656 | case rs_align_test: |
| 4657 | if (count != 0) |
| 4658 | as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data")); |
| 4659 | break; |
| 4660 | |
| 4661 | case rs_align_code: |
| 4662 | p = fragp->fr_literal + fragp->fr_fix; |
| 4663 | fix = 0; |
| 4664 | |
| 4665 | if (count & 3) |
| 4666 | { |
| 4667 | fix = count & 3; |
| 4668 | memset (p, 0, fix); |
| 4669 | p += fix; |
| 4670 | count -= fix; |
| 4671 | } |
| 4672 | |
| 4673 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8) |
| 4674 | { |
| 4675 | unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */ |
| 4676 | if (INSN_BIG_ENDIAN) |
| 4677 | number_to_chars_bigendian (p, wval, 4); |
| 4678 | else |
| 4679 | number_to_chars_littleendian (p, wval, 4); |
| 4680 | p += 4; |
| 4681 | count -= 4; |
| 4682 | fix += 4; |
| 4683 | } |
| 4684 | |
| 4685 | if (INSN_BIG_ENDIAN) |
| 4686 | number_to_chars_bigendian (p, 0x01000000, 4); |
| 4687 | else |
| 4688 | number_to_chars_littleendian (p, 0x01000000, 4); |
| 4689 | |
| 4690 | fragp->fr_fix += fix; |
| 4691 | fragp->fr_var = 4; |
| 4692 | break; |
| 4693 | |
| 4694 | default: |
| 4695 | break; |
| 4696 | } |
| 4697 | } |
| 4698 | |
| 4699 | /* Some special processing for a Sparc ELF file. */ |
| 4700 | |
| 4701 | void |
| 4702 | sparc_elf_final_processing (void) |
| 4703 | { |
| 4704 | /* Set the Sparc ELF flag bits. FIXME: There should probably be some |
| 4705 | sort of BFD interface for this. */ |
| 4706 | if (sparc_arch_size == 64) |
| 4707 | { |
| 4708 | switch (sparc_memory_model) |
| 4709 | { |
| 4710 | case MM_RMO: |
| 4711 | elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO; |
| 4712 | break; |
| 4713 | case MM_PSO: |
| 4714 | elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO; |
| 4715 | break; |
| 4716 | default: |
| 4717 | break; |
| 4718 | } |
| 4719 | } |
| 4720 | else if (current_architecture >= SPARC_OPCODE_ARCH_V9) |
| 4721 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS; |
| 4722 | if (current_architecture == SPARC_OPCODE_ARCH_V9A) |
| 4723 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1; |
| 4724 | else if (current_architecture == SPARC_OPCODE_ARCH_V9B) |
| 4725 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3; |
| 4726 | } |
| 4727 | |
| 4728 | const char * |
| 4729 | sparc_cons (expressionS *exp, int size) |
| 4730 | { |
| 4731 | char *save; |
| 4732 | const char *sparc_cons_special_reloc = NULL; |
| 4733 | |
| 4734 | SKIP_WHITESPACE (); |
| 4735 | save = input_line_pointer; |
| 4736 | if (input_line_pointer[0] == '%' |
| 4737 | && input_line_pointer[1] == 'r' |
| 4738 | && input_line_pointer[2] == '_') |
| 4739 | { |
| 4740 | if (strncmp (input_line_pointer + 3, "disp", 4) == 0) |
| 4741 | { |
| 4742 | input_line_pointer += 7; |
| 4743 | sparc_cons_special_reloc = "disp"; |
| 4744 | } |
| 4745 | else if (strncmp (input_line_pointer + 3, "plt", 3) == 0) |
| 4746 | { |
| 4747 | if (size != 4 && size != 8) |
| 4748 | as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size); |
| 4749 | else |
| 4750 | { |
| 4751 | input_line_pointer += 6; |
| 4752 | sparc_cons_special_reloc = "plt"; |
| 4753 | } |
| 4754 | } |
| 4755 | else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0) |
| 4756 | { |
| 4757 | if (size != 4 && size != 8) |
| 4758 | as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size); |
| 4759 | else |
| 4760 | { |
| 4761 | input_line_pointer += 13; |
| 4762 | sparc_cons_special_reloc = "tls_dtpoff"; |
| 4763 | } |
| 4764 | } |
| 4765 | if (sparc_cons_special_reloc) |
| 4766 | { |
| 4767 | int bad = 0; |
| 4768 | |
| 4769 | switch (size) |
| 4770 | { |
| 4771 | case 1: |
| 4772 | if (*input_line_pointer != '8') |
| 4773 | bad = 1; |
| 4774 | input_line_pointer--; |
| 4775 | break; |
| 4776 | case 2: |
| 4777 | if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6') |
| 4778 | bad = 1; |
| 4779 | break; |
| 4780 | case 4: |
| 4781 | if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2') |
| 4782 | bad = 1; |
| 4783 | break; |
| 4784 | case 8: |
| 4785 | if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4') |
| 4786 | bad = 1; |
| 4787 | break; |
| 4788 | default: |
| 4789 | bad = 1; |
| 4790 | break; |
| 4791 | } |
| 4792 | |
| 4793 | if (bad) |
| 4794 | { |
| 4795 | as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"), |
| 4796 | sparc_cons_special_reloc, size * 8, size); |
| 4797 | } |
| 4798 | else |
| 4799 | { |
| 4800 | input_line_pointer += 2; |
| 4801 | if (*input_line_pointer != '(') |
| 4802 | { |
| 4803 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), |
| 4804 | sparc_cons_special_reloc, size * 8); |
| 4805 | bad = 1; |
| 4806 | } |
| 4807 | } |
| 4808 | |
| 4809 | if (bad) |
| 4810 | { |
| 4811 | input_line_pointer = save; |
| 4812 | sparc_cons_special_reloc = NULL; |
| 4813 | } |
| 4814 | else |
| 4815 | { |
| 4816 | int c; |
| 4817 | char *end = ++input_line_pointer; |
| 4818 | int npar = 0; |
| 4819 | |
| 4820 | while (! is_end_of_line[(c = *end)]) |
| 4821 | { |
| 4822 | if (c == '(') |
| 4823 | npar++; |
| 4824 | else if (c == ')') |
| 4825 | { |
| 4826 | if (!npar) |
| 4827 | break; |
| 4828 | npar--; |
| 4829 | } |
| 4830 | end++; |
| 4831 | } |
| 4832 | |
| 4833 | if (c != ')') |
| 4834 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), |
| 4835 | sparc_cons_special_reloc, size * 8); |
| 4836 | else |
| 4837 | { |
| 4838 | *end = '\0'; |
| 4839 | expression (exp); |
| 4840 | *end = c; |
| 4841 | if (input_line_pointer != end) |
| 4842 | { |
| 4843 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), |
| 4844 | sparc_cons_special_reloc, size * 8); |
| 4845 | } |
| 4846 | else |
| 4847 | { |
| 4848 | input_line_pointer++; |
| 4849 | SKIP_WHITESPACE (); |
| 4850 | c = *input_line_pointer; |
| 4851 | if (! is_end_of_line[c] && c != ',') |
| 4852 | as_bad (_("Illegal operands: garbage after %%r_%s%d()"), |
| 4853 | sparc_cons_special_reloc, size * 8); |
| 4854 | } |
| 4855 | } |
| 4856 | } |
| 4857 | } |
| 4858 | } |
| 4859 | if (sparc_cons_special_reloc == NULL) |
| 4860 | expression (exp); |
| 4861 | return sparc_cons_special_reloc; |
| 4862 | } |
| 4863 | |
| 4864 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a |
| 4865 | reloc for a cons. We could use the definition there, except that |
| 4866 | we want to handle little endian relocs specially. */ |
| 4867 | |
| 4868 | void |
| 4869 | cons_fix_new_sparc (fragS *frag, |
| 4870 | int where, |
| 4871 | unsigned int nbytes, |
| 4872 | expressionS *exp, |
| 4873 | const char *sparc_cons_special_reloc) |
| 4874 | { |
| 4875 | bfd_reloc_code_real_type r; |
| 4876 | |
| 4877 | r = (nbytes == 1 ? BFD_RELOC_8 : |
| 4878 | (nbytes == 2 ? BFD_RELOC_16 : |
| 4879 | (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); |
| 4880 | |
| 4881 | if (target_little_endian_data |
| 4882 | && nbytes == 4 |
| 4883 | && now_seg->flags & SEC_ALLOC) |
| 4884 | r = BFD_RELOC_SPARC_REV32; |
| 4885 | |
| 4886 | #ifdef TE_SOLARIS |
| 4887 | /* The Solaris linker does not allow R_SPARC_UA64 |
| 4888 | relocations for 32-bit executables. */ |
| 4889 | if (!target_little_endian_data |
| 4890 | && sparc_arch_size != 64 |
| 4891 | && r == BFD_RELOC_64) |
| 4892 | r = BFD_RELOC_32; |
| 4893 | #endif |
| 4894 | |
| 4895 | if (sparc_cons_special_reloc) |
| 4896 | { |
| 4897 | if (*sparc_cons_special_reloc == 'd') |
| 4898 | switch (nbytes) |
| 4899 | { |
| 4900 | case 1: r = BFD_RELOC_8_PCREL; break; |
| 4901 | case 2: r = BFD_RELOC_16_PCREL; break; |
| 4902 | case 4: r = BFD_RELOC_32_PCREL; break; |
| 4903 | case 8: r = BFD_RELOC_64_PCREL; break; |
| 4904 | default: abort (); |
| 4905 | } |
| 4906 | else if (*sparc_cons_special_reloc == 'p') |
| 4907 | switch (nbytes) |
| 4908 | { |
| 4909 | case 4: r = BFD_RELOC_SPARC_PLT32; break; |
| 4910 | case 8: r = BFD_RELOC_SPARC_PLT64; break; |
| 4911 | } |
| 4912 | else |
| 4913 | switch (nbytes) |
| 4914 | { |
| 4915 | case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break; |
| 4916 | case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break; |
| 4917 | } |
| 4918 | } |
| 4919 | else if (sparc_no_align_cons |
| 4920 | || /* PR 20803 - relocs in the .eh_frame section |
| 4921 | need to support unaligned access. */ |
| 4922 | strcmp (now_seg->name, ".eh_frame") == 0) |
| 4923 | { |
| 4924 | switch (nbytes) |
| 4925 | { |
| 4926 | case 2: r = BFD_RELOC_SPARC_UA16; break; |
| 4927 | case 4: r = BFD_RELOC_SPARC_UA32; break; |
| 4928 | #ifdef TE_SOLARIS |
| 4929 | /* The Solaris linker does not allow R_SPARC_UA64 |
| 4930 | relocations for 32-bit executables. */ |
| 4931 | case 8: r = sparc_arch_size == 64 ? |
| 4932 | BFD_RELOC_SPARC_UA64 : BFD_RELOC_SPARC_UA32; break; |
| 4933 | #else |
| 4934 | case 8: r = BFD_RELOC_SPARC_UA64; break; |
| 4935 | #endif |
| 4936 | default: abort (); |
| 4937 | } |
| 4938 | } |
| 4939 | |
| 4940 | fix_new_exp (frag, where, (int) nbytes, exp, 0, r); |
| 4941 | } |
| 4942 | |
| 4943 | void |
| 4944 | sparc_cfi_frame_initial_instructions (void) |
| 4945 | { |
| 4946 | cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0); |
| 4947 | } |
| 4948 | |
| 4949 | int |
| 4950 | sparc_regname_to_dw2regnum (char *regname) |
| 4951 | { |
| 4952 | char *q; |
| 4953 | int i; |
| 4954 | |
| 4955 | if (!regname[0]) |
| 4956 | return -1; |
| 4957 | |
| 4958 | switch (regname[0]) |
| 4959 | { |
| 4960 | case 'g': i = 0; break; |
| 4961 | case 'o': i = 1; break; |
| 4962 | case 'l': i = 2; break; |
| 4963 | case 'i': i = 3; break; |
| 4964 | default: i = -1; break; |
| 4965 | } |
| 4966 | if (i != -1) |
| 4967 | { |
| 4968 | if (regname[1] < '0' || regname[1] > '8' || regname[2]) |
| 4969 | return -1; |
| 4970 | return i * 8 + regname[1] - '0'; |
| 4971 | } |
| 4972 | if (regname[0] == 's' && regname[1] == 'p' && !regname[2]) |
| 4973 | return 14; |
| 4974 | if (regname[0] == 'f' && regname[1] == 'p' && !regname[2]) |
| 4975 | return 30; |
| 4976 | if (regname[0] == 'f' || regname[0] == 'r') |
| 4977 | { |
| 4978 | unsigned int regnum; |
| 4979 | |
| 4980 | regnum = strtoul (regname + 1, &q, 10); |
| 4981 | if (q == NULL || *q) |
| 4982 | return -1; |
| 4983 | if (regnum >= ((regname[0] == 'f' |
| 4984 | && SPARC_OPCODE_ARCH_V9_P (max_architecture)) |
| 4985 | ? 64 : 32)) |
| 4986 | return -1; |
| 4987 | if (regname[0] == 'f') |
| 4988 | { |
| 4989 | regnum += 32; |
| 4990 | if (regnum >= 64 && (regnum & 1)) |
| 4991 | return -1; |
| 4992 | } |
| 4993 | return regnum; |
| 4994 | } |
| 4995 | return -1; |
| 4996 | } |
| 4997 | |
| 4998 | void |
| 4999 | sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes) |
| 5000 | { |
| 5001 | sparc_no_align_cons = 1; |
| 5002 | emit_expr_with_reloc (exp, nbytes, "disp"); |
| 5003 | sparc_no_align_cons = 0; |
| 5004 | } |