| 1 | @c Copyright (C) 1996-2019 Free Software Foundation, Inc. |
| 2 | @c This is part of the GAS manual. |
| 3 | @c For copying conditions, see the file as.texinfo. |
| 4 | |
| 5 | @ifset GENERIC |
| 6 | @page |
| 7 | @node ARM-Dependent |
| 8 | @chapter ARM Dependent Features |
| 9 | @end ifset |
| 10 | |
| 11 | @ifclear GENERIC |
| 12 | @node Machine Dependencies |
| 13 | @chapter ARM Dependent Features |
| 14 | @end ifclear |
| 15 | |
| 16 | @cindex ARM support |
| 17 | @cindex Thumb support |
| 18 | @menu |
| 19 | * ARM Options:: Options |
| 20 | * ARM Syntax:: Syntax |
| 21 | * ARM Floating Point:: Floating Point |
| 22 | * ARM Directives:: ARM Machine Directives |
| 23 | * ARM Opcodes:: Opcodes |
| 24 | * ARM Mapping Symbols:: Mapping Symbols |
| 25 | * ARM Unwinding Tutorial:: Unwinding |
| 26 | @end menu |
| 27 | |
| 28 | @node ARM Options |
| 29 | @section Options |
| 30 | @cindex ARM options (none) |
| 31 | @cindex options for ARM (none) |
| 32 | |
| 33 | @table @code |
| 34 | |
| 35 | @cindex @code{-mcpu=} command-line option, ARM |
| 36 | @item -mcpu=@var{processor}[+@var{extension}@dots{}] |
| 37 | This option specifies the target processor. The assembler will issue an |
| 38 | error message if an attempt is made to assemble an instruction which |
| 39 | will not execute on the target processor. The following processor names are |
| 40 | recognized: |
| 41 | @code{arm1}, |
| 42 | @code{arm2}, |
| 43 | @code{arm250}, |
| 44 | @code{arm3}, |
| 45 | @code{arm6}, |
| 46 | @code{arm60}, |
| 47 | @code{arm600}, |
| 48 | @code{arm610}, |
| 49 | @code{arm620}, |
| 50 | @code{arm7}, |
| 51 | @code{arm7m}, |
| 52 | @code{arm7d}, |
| 53 | @code{arm7dm}, |
| 54 | @code{arm7di}, |
| 55 | @code{arm7dmi}, |
| 56 | @code{arm70}, |
| 57 | @code{arm700}, |
| 58 | @code{arm700i}, |
| 59 | @code{arm710}, |
| 60 | @code{arm710t}, |
| 61 | @code{arm720}, |
| 62 | @code{arm720t}, |
| 63 | @code{arm740t}, |
| 64 | @code{arm710c}, |
| 65 | @code{arm7100}, |
| 66 | @code{arm7500}, |
| 67 | @code{arm7500fe}, |
| 68 | @code{arm7t}, |
| 69 | @code{arm7tdmi}, |
| 70 | @code{arm7tdmi-s}, |
| 71 | @code{arm8}, |
| 72 | @code{arm810}, |
| 73 | @code{strongarm}, |
| 74 | @code{strongarm1}, |
| 75 | @code{strongarm110}, |
| 76 | @code{strongarm1100}, |
| 77 | @code{strongarm1110}, |
| 78 | @code{arm9}, |
| 79 | @code{arm920}, |
| 80 | @code{arm920t}, |
| 81 | @code{arm922t}, |
| 82 | @code{arm940t}, |
| 83 | @code{arm9tdmi}, |
| 84 | @code{fa526} (Faraday FA526 processor), |
| 85 | @code{fa626} (Faraday FA626 processor), |
| 86 | @code{arm9e}, |
| 87 | @code{arm926e}, |
| 88 | @code{arm926ej-s}, |
| 89 | @code{arm946e-r0}, |
| 90 | @code{arm946e}, |
| 91 | @code{arm946e-s}, |
| 92 | @code{arm966e-r0}, |
| 93 | @code{arm966e}, |
| 94 | @code{arm966e-s}, |
| 95 | @code{arm968e-s}, |
| 96 | @code{arm10t}, |
| 97 | @code{arm10tdmi}, |
| 98 | @code{arm10e}, |
| 99 | @code{arm1020}, |
| 100 | @code{arm1020t}, |
| 101 | @code{arm1020e}, |
| 102 | @code{arm1022e}, |
| 103 | @code{arm1026ej-s}, |
| 104 | @code{fa606te} (Faraday FA606TE processor), |
| 105 | @code{fa616te} (Faraday FA616TE processor), |
| 106 | @code{fa626te} (Faraday FA626TE processor), |
| 107 | @code{fmp626} (Faraday FMP626 processor), |
| 108 | @code{fa726te} (Faraday FA726TE processor), |
| 109 | @code{arm1136j-s}, |
| 110 | @code{arm1136jf-s}, |
| 111 | @code{arm1156t2-s}, |
| 112 | @code{arm1156t2f-s}, |
| 113 | @code{arm1176jz-s}, |
| 114 | @code{arm1176jzf-s}, |
| 115 | @code{mpcore}, |
| 116 | @code{mpcorenovfp}, |
| 117 | @code{cortex-a5}, |
| 118 | @code{cortex-a7}, |
| 119 | @code{cortex-a8}, |
| 120 | @code{cortex-a9}, |
| 121 | @code{cortex-a15}, |
| 122 | @code{cortex-a17}, |
| 123 | @code{cortex-a32}, |
| 124 | @code{cortex-a35}, |
| 125 | @code{cortex-a53}, |
| 126 | @code{cortex-a55}, |
| 127 | @code{cortex-a57}, |
| 128 | @code{cortex-a72}, |
| 129 | @code{cortex-a73}, |
| 130 | @code{cortex-a75}, |
| 131 | @code{cortex-a76}, |
| 132 | @code{cortex-a76ae}, |
| 133 | @code{cortex-a77}, |
| 134 | @code{ares}, |
| 135 | @code{cortex-r4}, |
| 136 | @code{cortex-r4f}, |
| 137 | @code{cortex-r5}, |
| 138 | @code{cortex-r7}, |
| 139 | @code{cortex-r8}, |
| 140 | @code{cortex-r52}, |
| 141 | @code{cortex-m35p}, |
| 142 | @code{cortex-m33}, |
| 143 | @code{cortex-m23}, |
| 144 | @code{cortex-m7}, |
| 145 | @code{cortex-m4}, |
| 146 | @code{cortex-m3}, |
| 147 | @code{cortex-m1}, |
| 148 | @code{cortex-m0}, |
| 149 | @code{cortex-m0plus}, |
| 150 | @code{exynos-m1}, |
| 151 | @code{marvell-pj4}, |
| 152 | @code{marvell-whitney}, |
| 153 | @code{neoverse-n1}, |
| 154 | @code{xgene1}, |
| 155 | @code{xgene2}, |
| 156 | @code{ep9312} (ARM920 with Cirrus Maverick coprocessor), |
| 157 | @code{i80200} (Intel XScale processor) |
| 158 | @code{iwmmxt} (Intel XScale processor with Wireless MMX technology coprocessor) |
| 159 | and |
| 160 | @code{xscale}. |
| 161 | The special name @code{all} may be used to allow the |
| 162 | assembler to accept instructions valid for any ARM processor. |
| 163 | |
| 164 | In addition to the basic instruction set, the assembler can be told to |
| 165 | accept various extension mnemonics that extend the processor using the |
| 166 | co-processor instruction space. For example, @code{-mcpu=arm920+maverick} |
| 167 | is equivalent to specifying @code{-mcpu=ep9312}. |
| 168 | |
| 169 | Multiple extensions may be specified, separated by a @code{+}. The |
| 170 | extensions should be specified in ascending alphabetical order. |
| 171 | |
| 172 | Some extensions may be restricted to particular architectures; this is |
| 173 | documented in the list of extensions below. |
| 174 | |
| 175 | Extension mnemonics may also be removed from those the assembler accepts. |
| 176 | This is done be prepending @code{no} to the option that adds the extension. |
| 177 | Extensions that are removed should be listed after all extensions which have |
| 178 | been added, again in ascending alphabetical order. For example, |
| 179 | @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}. |
| 180 | |
| 181 | |
| 182 | The following extensions are currently supported: |
| 183 | @code{bf16} (BFloat16 extensions for v8.6-A architecture), |
| 184 | @code{i8mm} (Int8 Matrix Multiply extensions for v8.6-A architecture), |
| 185 | @code{crc} |
| 186 | @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}), |
| 187 | @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}), |
| 188 | @code{fp} (Floating Point Extensions for v8-A architecture), |
| 189 | @code{fp16} (FP16 Extensions for v8.2-A architecture, implies @code{fp}), |
| 190 | @code{fp16fml} (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, implies @code{fp16}), |
| 191 | @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures), |
| 192 | @code{iwmmxt}, |
| 193 | @code{iwmmxt2}, |
| 194 | @code{xscale}, |
| 195 | @code{maverick}, |
| 196 | @code{mp} (Multiprocessing Extensions for v7-A and v7-R |
| 197 | architectures), |
| 198 | @code{os} (Operating System for v6M architecture), |
| 199 | @code{predres} (Execution and Data Prediction Restriction Instruction for |
| 200 | v8-A architectures, added by default from v8.5-A), |
| 201 | @code{sb} (Speculation Barrier Instruction for v8-A architectures, added by |
| 202 | default from v8.5-A), |
| 203 | @code{sec} (Security Extensions for v6K and v7-A architectures), |
| 204 | @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}), |
| 205 | @code{virt} (Virtualization Extensions for v7-A architecture, implies |
| 206 | @code{idiv}), |
| 207 | @code{pan} (Privileged Access Never Extensions for v8-A architecture), |
| 208 | @code{ras} (Reliability, Availability and Serviceability extensions |
| 209 | for v8-A architecture), |
| 210 | @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies |
| 211 | @code{simd}) |
| 212 | and |
| 213 | @code{xscale}. |
| 214 | |
| 215 | @cindex @code{-march=} command-line option, ARM |
| 216 | @item -march=@var{architecture}[+@var{extension}@dots{}] |
| 217 | This option specifies the target architecture. The assembler will issue |
| 218 | an error message if an attempt is made to assemble an instruction which |
| 219 | will not execute on the target architecture. The following architecture |
| 220 | names are recognized: |
| 221 | @code{armv1}, |
| 222 | @code{armv2}, |
| 223 | @code{armv2a}, |
| 224 | @code{armv2s}, |
| 225 | @code{armv3}, |
| 226 | @code{armv3m}, |
| 227 | @code{armv4}, |
| 228 | @code{armv4xm}, |
| 229 | @code{armv4t}, |
| 230 | @code{armv4txm}, |
| 231 | @code{armv5}, |
| 232 | @code{armv5t}, |
| 233 | @code{armv5txm}, |
| 234 | @code{armv5te}, |
| 235 | @code{armv5texp}, |
| 236 | @code{armv6}, |
| 237 | @code{armv6j}, |
| 238 | @code{armv6k}, |
| 239 | @code{armv6z}, |
| 240 | @code{armv6kz}, |
| 241 | @code{armv6-m}, |
| 242 | @code{armv6s-m}, |
| 243 | @code{armv7}, |
| 244 | @code{armv7-a}, |
| 245 | @code{armv7ve}, |
| 246 | @code{armv7-r}, |
| 247 | @code{armv7-m}, |
| 248 | @code{armv7e-m}, |
| 249 | @code{armv8-a}, |
| 250 | @code{armv8.1-a}, |
| 251 | @code{armv8.2-a}, |
| 252 | @code{armv8.3-a}, |
| 253 | @code{armv8-r}, |
| 254 | @code{armv8.4-a}, |
| 255 | @code{armv8.5-a}, |
| 256 | @code{armv8-m.base}, |
| 257 | @code{armv8-m.main}, |
| 258 | @code{armv8.1-m.main}, |
| 259 | @code{armv8.6-a}, |
| 260 | @code{iwmmxt}, |
| 261 | @code{iwmmxt2} |
| 262 | and |
| 263 | @code{xscale}. |
| 264 | If both @code{-mcpu} and |
| 265 | @code{-march} are specified, the assembler will use |
| 266 | the setting for @code{-mcpu}. |
| 267 | |
| 268 | The architecture option can be extended with a set extension options. These |
| 269 | extensions are context sensitive, i.e. the same extension may mean different |
| 270 | things when used with different architectures. When used together with a |
| 271 | @code{-mfpu} option, the union of both feature enablement is taken. |
| 272 | See their availability and meaning below: |
| 273 | |
| 274 | For @code{armv5te}, @code{armv5texp}, @code{armv5tej}, @code{armv6}, @code{armv6j}, @code{armv6k}, @code{armv6z}, @code{armv6kz}, @code{armv6zk}, @code{armv6t2}, @code{armv6kt2} and @code{armv6zt2}: |
| 275 | |
| 276 | @code{+fp}: Enables VFPv2 instructions. |
| 277 | @code{+nofp}: Disables all FPU instrunctions. |
| 278 | |
| 279 | For @code{armv7}: |
| 280 | |
| 281 | @code{+fp}: Enables VFPv3 instructions with 16 double-word registers. |
| 282 | @code{+nofp}: Disables all FPU instructions. |
| 283 | |
| 284 | For @code{armv7-a}: |
| 285 | |
| 286 | @code{+fp}: Enables VFPv3 instructions with 16 double-word registers. |
| 287 | @code{+vfpv3-d16}: Alias for @code{+fp}. |
| 288 | @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers. |
| 289 | @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point |
| 290 | conversion instructions and 16 double-word registers. |
| 291 | @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion |
| 292 | instructions and 32 double-word registers. |
| 293 | @code{+vfpv4-d16}: Enables VFPv4 instructions with 16 double-word registers. |
| 294 | @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers. |
| 295 | @code{+simd}: Enables VFPv3 and NEONv1 instructions with 32 double-word |
| 296 | registers. |
| 297 | @code{+neon}: Alias for @code{+simd}. |
| 298 | @code{+neon-vfpv3}: Alias for @code{+simd}. |
| 299 | @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and |
| 300 | NEONv1 instructions with 32 double-word registers. |
| 301 | @code{+neon-vfpv4}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32 |
| 302 | double-word registers. |
| 303 | @code{+mp}: Enables Multiprocessing Extensions. |
| 304 | @code{+sec}: Enables Security Extensions. |
| 305 | @code{+nofp}: Disables all FPU and NEON instructions. |
| 306 | @code{+nosimd}: Disables all NEON instructions. |
| 307 | |
| 308 | For @code{armv7ve}: |
| 309 | |
| 310 | @code{+fp}: Enables VFPv4 instructions with 16 double-word registers. |
| 311 | @code{+vfpv4-d16}: Alias for @code{+fp}. |
| 312 | @code{+vfpv3-d16}: Enables VFPv3 instructions with 16 double-word registers. |
| 313 | @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers. |
| 314 | @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point |
| 315 | conversion instructions and 16 double-word registers. |
| 316 | @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion |
| 317 | instructions and 32 double-word registers. |
| 318 | @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers. |
| 319 | @code{+simd}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32 |
| 320 | double-word registers. |
| 321 | @code{+neon-vfpv4}: Alias for @code{+simd}. |
| 322 | @code{+neon}: Enables VFPv3 and NEONv1 instructions with 32 double-word |
| 323 | registers. |
| 324 | @code{+neon-vfpv3}: Alias for @code{+neon}. |
| 325 | @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and |
| 326 | NEONv1 instructions with 32 double-word registers. |
| 327 | double-word registers. |
| 328 | @code{+nofp}: Disables all FPU and NEON instructions. |
| 329 | @code{+nosimd}: Disables all NEON instructions. |
| 330 | |
| 331 | For @code{armv7-r}: |
| 332 | |
| 333 | @code{+fp.sp}: Enables single-precision only VFPv3 instructions with 16 |
| 334 | double-word registers. |
| 335 | @code{+vfpv3xd}: Alias for @code{+fp.sp}. |
| 336 | @code{+fp}: Enables VFPv3 instructions with 16 double-word registers. |
| 337 | @code{+vfpv3-d16}: Alias for @code{+fp}. |
| 338 | @code{+vfpv3xd-fp16}: Enables single-precision only VFPv3 and half |
| 339 | floating-point conversion instructions with 16 double-word registers. |
| 340 | @code{+vfpv3-d16-fp16}: Enables VFPv3 and half precision floating-point |
| 341 | conversion instructions with 16 double-word registers. |
| 342 | @code{+idiv}: Enables integer division instructions in ARM mode. |
| 343 | @code{+nofp}: Disables all FPU instructions. |
| 344 | |
| 345 | For @code{armv7e-m}: |
| 346 | |
| 347 | @code{+fp}: Enables single-precision only VFPv4 instructions with 16 |
| 348 | double-word registers. |
| 349 | @code{+vfpvf4-sp-d16}: Alias for @code{+fp}. |
| 350 | @code{+fpv5}: Enables single-precision only VFPv5 instructions with 16 |
| 351 | double-word registers. |
| 352 | @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers. |
| 353 | @code{+fpv5-d16"}: Alias for @code{+fp.dp}. |
| 354 | @code{+nofp}: Disables all FPU instructions. |
| 355 | |
| 356 | For @code{armv8-m.main}: |
| 357 | |
| 358 | @code{+dsp}: Enables DSP Extension. |
| 359 | @code{+fp}: Enables single-precision only VFPv5 instructions with 16 |
| 360 | double-word registers. |
| 361 | @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers. |
| 362 | @code{+nofp}: Disables all FPU instructions. |
| 363 | @code{+nodsp}: Disables DSP Extension. |
| 364 | |
| 365 | For @code{armv8.1-m.main}: |
| 366 | |
| 367 | @code{+dsp}: Enables DSP Extension. |
| 368 | @code{+fp}: Enables single and half precision scalar Floating Point Extensions |
| 369 | for Armv8.1-M Mainline with 16 double-word registers. |
| 370 | @code{+fp.dp}: Enables double precision scalar Floating Point Extensions for |
| 371 | Armv8.1-M Mainline, implies @code{+fp}. |
| 372 | @code{+mve}: Enables integer only M-profile Vector Extension for |
| 373 | Armv8.1-M Mainline, implies @code{+dsp}. |
| 374 | @code{+mve.fp}: Enables Floating Point M-profile Vector Extension for |
| 375 | Armv8.1-M Mainline, implies @code{+mve} and @code{+fp}. |
| 376 | @code{+nofp}: Disables all FPU instructions. |
| 377 | @code{+nodsp}: Disables DSP Extension. |
| 378 | @code{+nomve}: Disables all M-profile Vector Extensions. |
| 379 | |
| 380 | For @code{armv8-a}: |
| 381 | |
| 382 | @code{+crc}: Enables CRC32 Extension. |
| 383 | @code{+simd}: Enables VFP and NEON for Armv8-A. |
| 384 | @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies |
| 385 | @code{+simd}. |
| 386 | @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. |
| 387 | @code{+predres}: Enables Execution and Data Prediction Restriction Instruction |
| 388 | for Armv8-A. |
| 389 | @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions. |
| 390 | @code{+nocrypto}: Disables Cryptography Extensions. |
| 391 | |
| 392 | For @code{armv8.1-a}: |
| 393 | |
| 394 | @code{+simd}: Enables VFP and NEON for Armv8.1-A. |
| 395 | @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies |
| 396 | @code{+simd}. |
| 397 | @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. |
| 398 | @code{+predres}: Enables Execution and Data Prediction Restriction Instruction |
| 399 | for Armv8-A. |
| 400 | @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions. |
| 401 | @code{+nocrypto}: Disables Cryptography Extensions. |
| 402 | |
| 403 | For @code{armv8.2-a} and @code{armv8.3-a}: |
| 404 | |
| 405 | @code{+simd}: Enables VFP and NEON for Armv8.1-A. |
| 406 | @code{+fp16}: Enables FP16 Extension for Armv8.2-A, implies @code{+simd}. |
| 407 | @code{+fp16fml}: Enables FP16 Floating Point Multiplication Variant Extensions |
| 408 | for Armv8.2-A, implies @code{+fp16}. |
| 409 | @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies |
| 410 | @code{+simd}. |
| 411 | @code{+dotprod}: Enables Dot Product Extensions for Armv8.2-A, implies |
| 412 | @code{+simd}. |
| 413 | @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. |
| 414 | @code{+predres}: Enables Execution and Data Prediction Restriction Instruction |
| 415 | for Armv8-A. |
| 416 | @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions. |
| 417 | @code{+nocrypto}: Disables Cryptography Extensions. |
| 418 | |
| 419 | For @code{armv8.4-a}: |
| 420 | |
| 421 | @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for |
| 422 | Armv8.2-A. |
| 423 | @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication |
| 424 | Variant Extensions for Armv8.2-A, implies @code{+simd}. |
| 425 | @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies |
| 426 | @code{+simd}. |
| 427 | @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. |
| 428 | @code{+predres}: Enables Execution and Data Prediction Restriction Instruction |
| 429 | for Armv8-A. |
| 430 | @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions. |
| 431 | @code{+nocryptp}: Disables Cryptography Extensions. |
| 432 | |
| 433 | For @code{armv8.5-a}: |
| 434 | |
| 435 | @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for |
| 436 | Armv8.2-A. |
| 437 | @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication |
| 438 | Variant Extensions for Armv8.2-A, implies @code{+simd}. |
| 439 | @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies |
| 440 | @code{+simd}. |
| 441 | @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions. |
| 442 | @code{+nocryptp}: Disables Cryptography Extensions. |
| 443 | |
| 444 | |
| 445 | @cindex @code{-mfpu=} command-line option, ARM |
| 446 | @item -mfpu=@var{floating-point-format} |
| 447 | |
| 448 | This option specifies the floating point format to assemble for. The |
| 449 | assembler will issue an error message if an attempt is made to assemble |
| 450 | an instruction which will not execute on the target floating point unit. |
| 451 | The following format options are recognized: |
| 452 | @code{softfpa}, |
| 453 | @code{fpe}, |
| 454 | @code{fpe2}, |
| 455 | @code{fpe3}, |
| 456 | @code{fpa}, |
| 457 | @code{fpa10}, |
| 458 | @code{fpa11}, |
| 459 | @code{arm7500fe}, |
| 460 | @code{softvfp}, |
| 461 | @code{softvfp+vfp}, |
| 462 | @code{vfp}, |
| 463 | @code{vfp10}, |
| 464 | @code{vfp10-r0}, |
| 465 | @code{vfp9}, |
| 466 | @code{vfpxd}, |
| 467 | @code{vfpv2}, |
| 468 | @code{vfpv3}, |
| 469 | @code{vfpv3-fp16}, |
| 470 | @code{vfpv3-d16}, |
| 471 | @code{vfpv3-d16-fp16}, |
| 472 | @code{vfpv3xd}, |
| 473 | @code{vfpv3xd-d16}, |
| 474 | @code{vfpv4}, |
| 475 | @code{vfpv4-d16}, |
| 476 | @code{fpv4-sp-d16}, |
| 477 | @code{fpv5-sp-d16}, |
| 478 | @code{fpv5-d16}, |
| 479 | @code{fp-armv8}, |
| 480 | @code{arm1020t}, |
| 481 | @code{arm1020e}, |
| 482 | @code{arm1136jf-s}, |
| 483 | @code{maverick}, |
| 484 | @code{neon}, |
| 485 | @code{neon-vfpv3}, |
| 486 | @code{neon-fp16}, |
| 487 | @code{neon-vfpv4}, |
| 488 | @code{neon-fp-armv8}, |
| 489 | @code{crypto-neon-fp-armv8}, |
| 490 | @code{neon-fp-armv8.1} |
| 491 | and |
| 492 | @code{crypto-neon-fp-armv8.1}. |
| 493 | |
| 494 | In addition to determining which instructions are assembled, this option |
| 495 | also affects the way in which the @code{.double} assembler directive behaves |
| 496 | when assembling little-endian code. |
| 497 | |
| 498 | The default is dependent on the processor selected. For Architecture 5 or |
| 499 | later, the default is to assemble for VFP instructions; for earlier |
| 500 | architectures the default is to assemble for FPA instructions. |
| 501 | |
| 502 | @cindex @code{-mfp16-format=} command-line option |
| 503 | @item -mfp16-format=@var{format} |
| 504 | This option specifies the half-precision floating point format to use |
| 505 | when assembling floating point numbers emitted by the @code{.float16} |
| 506 | directive. |
| 507 | The following format options are recognized: |
| 508 | @code{ieee}, |
| 509 | @code{alternative}. |
| 510 | If @code{ieee} is specified then the IEEE 754-2008 half-precision floating |
| 511 | point format is used, if @code{alternative} is specified then the Arm |
| 512 | alternative half-precision format is used. If this option is set on the |
| 513 | command line then the format is fixed and cannot be changed with |
| 514 | the @code{float16_format} directive. If this value is not set then |
| 515 | the IEEE 754-2008 format is used until the format is explicitly set with |
| 516 | the @code{float16_format} directive. |
| 517 | |
| 518 | @cindex @code{-mthumb} command-line option, ARM |
| 519 | @item -mthumb |
| 520 | This option specifies that the assembler should start assembling Thumb |
| 521 | instructions; that is, it should behave as though the file starts with a |
| 522 | @code{.code 16} directive. |
| 523 | |
| 524 | @cindex @code{-mthumb-interwork} command-line option, ARM |
| 525 | @item -mthumb-interwork |
| 526 | This option specifies that the output generated by the assembler should |
| 527 | be marked as supporting interworking. It also affects the behaviour |
| 528 | of the @code{ADR} and @code{ADRL} pseudo opcodes. |
| 529 | |
| 530 | @cindex @code{-mimplicit-it} command-line option, ARM |
| 531 | @item -mimplicit-it=never |
| 532 | @itemx -mimplicit-it=always |
| 533 | @itemx -mimplicit-it=arm |
| 534 | @itemx -mimplicit-it=thumb |
| 535 | The @code{-mimplicit-it} option controls the behavior of the assembler when |
| 536 | conditional instructions are not enclosed in IT blocks. |
| 537 | There are four possible behaviors. |
| 538 | If @code{never} is specified, such constructs cause a warning in ARM |
| 539 | code and an error in Thumb-2 code. |
| 540 | If @code{always} is specified, such constructs are accepted in both |
| 541 | ARM and Thumb-2 code, where the IT instruction is added implicitly. |
| 542 | If @code{arm} is specified, such constructs are accepted in ARM code |
| 543 | and cause an error in Thumb-2 code. |
| 544 | If @code{thumb} is specified, such constructs cause a warning in ARM |
| 545 | code and are accepted in Thumb-2 code. If you omit this option, the |
| 546 | behavior is equivalent to @code{-mimplicit-it=arm}. |
| 547 | |
| 548 | @cindex @code{-mapcs-26} command-line option, ARM |
| 549 | @cindex @code{-mapcs-32} command-line option, ARM |
| 550 | @item -mapcs-26 |
| 551 | @itemx -mapcs-32 |
| 552 | These options specify that the output generated by the assembler should |
| 553 | be marked as supporting the indicated version of the Arm Procedure. |
| 554 | Calling Standard. |
| 555 | |
| 556 | @cindex @code{-matpcs} command-line option, ARM |
| 557 | @item -matpcs |
| 558 | This option specifies that the output generated by the assembler should |
| 559 | be marked as supporting the Arm/Thumb Procedure Calling Standard. If |
| 560 | enabled this option will cause the assembler to create an empty |
| 561 | debugging section in the object file called .arm.atpcs. Debuggers can |
| 562 | use this to determine the ABI being used by. |
| 563 | |
| 564 | @cindex @code{-mapcs-float} command-line option, ARM |
| 565 | @item -mapcs-float |
| 566 | This indicates the floating point variant of the APCS should be |
| 567 | used. In this variant floating point arguments are passed in FP |
| 568 | registers rather than integer registers. |
| 569 | |
| 570 | @cindex @code{-mapcs-reentrant} command-line option, ARM |
| 571 | @item -mapcs-reentrant |
| 572 | This indicates that the reentrant variant of the APCS should be used. |
| 573 | This variant supports position independent code. |
| 574 | |
| 575 | @cindex @code{-mfloat-abi=} command-line option, ARM |
| 576 | @item -mfloat-abi=@var{abi} |
| 577 | This option specifies that the output generated by the assembler should be |
| 578 | marked as using specified floating point ABI. |
| 579 | The following values are recognized: |
| 580 | @code{soft}, |
| 581 | @code{softfp} |
| 582 | and |
| 583 | @code{hard}. |
| 584 | |
| 585 | @cindex @code{-eabi=} command-line option, ARM |
| 586 | @item -meabi=@var{ver} |
| 587 | This option specifies which EABI version the produced object files should |
| 588 | conform to. |
| 589 | The following values are recognized: |
| 590 | @code{gnu}, |
| 591 | @code{4} |
| 592 | and |
| 593 | @code{5}. |
| 594 | |
| 595 | @cindex @code{-EB} command-line option, ARM |
| 596 | @item -EB |
| 597 | This option specifies that the output generated by the assembler should |
| 598 | be marked as being encoded for a big-endian processor. |
| 599 | |
| 600 | Note: If a program is being built for a system with big-endian data |
| 601 | and little-endian instructions then it should be assembled with the |
| 602 | @option{-EB} option, (all of it, code and data) and then linked with |
| 603 | the @option{--be8} option. This will reverse the endianness of the |
| 604 | instructions back to little-endian, but leave the data as big-endian. |
| 605 | |
| 606 | @cindex @code{-EL} command-line option, ARM |
| 607 | @item -EL |
| 608 | This option specifies that the output generated by the assembler should |
| 609 | be marked as being encoded for a little-endian processor. |
| 610 | |
| 611 | @cindex @code{-k} command-line option, ARM |
| 612 | @cindex PIC code generation for ARM |
| 613 | @item -k |
| 614 | This option specifies that the output of the assembler should be marked |
| 615 | as position-independent code (PIC). |
| 616 | |
| 617 | @cindex @code{--fix-v4bx} command-line option, ARM |
| 618 | @item --fix-v4bx |
| 619 | Allow @code{BX} instructions in ARMv4 code. This is intended for use with |
| 620 | the linker option of the same name. |
| 621 | |
| 622 | @cindex @code{-mwarn-deprecated} command-line option, ARM |
| 623 | @item -mwarn-deprecated |
| 624 | @itemx -mno-warn-deprecated |
| 625 | Enable or disable warnings about using deprecated options or |
| 626 | features. The default is to warn. |
| 627 | |
| 628 | @cindex @code{-mccs} command-line option, ARM |
| 629 | @item -mccs |
| 630 | Turns on CodeComposer Studio assembly syntax compatibility mode. |
| 631 | |
| 632 | @cindex @code{-mwarn-syms} command-line option, ARM |
| 633 | @item -mwarn-syms |
| 634 | @itemx -mno-warn-syms |
| 635 | Enable or disable warnings about symbols that match the names of ARM |
| 636 | instructions. The default is to warn. |
| 637 | |
| 638 | @end table |
| 639 | |
| 640 | |
| 641 | @node ARM Syntax |
| 642 | @section Syntax |
| 643 | @menu |
| 644 | * ARM-Instruction-Set:: Instruction Set |
| 645 | * ARM-Chars:: Special Characters |
| 646 | * ARM-Regs:: Register Names |
| 647 | * ARM-Relocations:: Relocations |
| 648 | * ARM-Neon-Alignment:: NEON Alignment Specifiers |
| 649 | @end menu |
| 650 | |
| 651 | @node ARM-Instruction-Set |
| 652 | @subsection Instruction Set Syntax |
| 653 | Two slightly different syntaxes are support for ARM and THUMB |
| 654 | instructions. The default, @code{divided}, uses the old style where |
| 655 | ARM and THUMB instructions had their own, separate syntaxes. The new, |
| 656 | @code{unified} syntax, which can be selected via the @code{.syntax} |
| 657 | directive, and has the following main features: |
| 658 | |
| 659 | @itemize @bullet |
| 660 | @item |
| 661 | Immediate operands do not require a @code{#} prefix. |
| 662 | |
| 663 | @item |
| 664 | The @code{IT} instruction may appear, and if it does it is validated |
| 665 | against subsequent conditional affixes. In ARM mode it does not |
| 666 | generate machine code, in THUMB mode it does. |
| 667 | |
| 668 | @item |
| 669 | For ARM instructions the conditional affixes always appear at the end |
| 670 | of the instruction. For THUMB instructions conditional affixes can be |
| 671 | used, but only inside the scope of an @code{IT} instruction. |
| 672 | |
| 673 | @item |
| 674 | All of the instructions new to the V6T2 architecture (and later) are |
| 675 | available. (Only a few such instructions can be written in the |
| 676 | @code{divided} syntax). |
| 677 | |
| 678 | @item |
| 679 | The @code{.N} and @code{.W} suffixes are recognized and honored. |
| 680 | |
| 681 | @item |
| 682 | All instructions set the flags if and only if they have an @code{s} |
| 683 | affix. |
| 684 | @end itemize |
| 685 | |
| 686 | @node ARM-Chars |
| 687 | @subsection Special Characters |
| 688 | |
| 689 | @cindex line comment character, ARM |
| 690 | @cindex ARM line comment character |
| 691 | The presence of a @samp{@@} anywhere on a line indicates the start of |
| 692 | a comment that extends to the end of that line. |
| 693 | |
| 694 | If a @samp{#} appears as the first character of a line then the whole |
| 695 | line is treated as a comment, but in this case the line could also be |
| 696 | a logical line number directive (@pxref{Comments}) or a preprocessor |
| 697 | control command (@pxref{Preprocessing}). |
| 698 | |
| 699 | @cindex line separator, ARM |
| 700 | @cindex statement separator, ARM |
| 701 | @cindex ARM line separator |
| 702 | The @samp{;} character can be used instead of a newline to separate |
| 703 | statements. |
| 704 | |
| 705 | @cindex immediate character, ARM |
| 706 | @cindex ARM immediate character |
| 707 | Either @samp{#} or @samp{$} can be used to indicate immediate operands. |
| 708 | |
| 709 | @cindex identifiers, ARM |
| 710 | @cindex ARM identifiers |
| 711 | *TODO* Explain about /data modifier on symbols. |
| 712 | |
| 713 | @node ARM-Regs |
| 714 | @subsection Register Names |
| 715 | |
| 716 | @cindex ARM register names |
| 717 | @cindex register names, ARM |
| 718 | *TODO* Explain about ARM register naming, and the predefined names. |
| 719 | |
| 720 | @node ARM-Relocations |
| 721 | @subsection ARM relocation generation |
| 722 | |
| 723 | @cindex data relocations, ARM |
| 724 | @cindex ARM data relocations |
| 725 | Specific data relocations can be generated by putting the relocation name |
| 726 | in parentheses after the symbol name. For example: |
| 727 | |
| 728 | @smallexample |
| 729 | .word foo(TARGET1) |
| 730 | @end smallexample |
| 731 | |
| 732 | This will generate an @samp{R_ARM_TARGET1} relocation against the symbol |
| 733 | @var{foo}. |
| 734 | The following relocations are supported: |
| 735 | @code{GOT}, |
| 736 | @code{GOTOFF}, |
| 737 | @code{TARGET1}, |
| 738 | @code{TARGET2}, |
| 739 | @code{SBREL}, |
| 740 | @code{TLSGD}, |
| 741 | @code{TLSLDM}, |
| 742 | @code{TLSLDO}, |
| 743 | @code{TLSDESC}, |
| 744 | @code{TLSCALL}, |
| 745 | @code{GOTTPOFF}, |
| 746 | @code{GOT_PREL} |
| 747 | and |
| 748 | @code{TPOFF}. |
| 749 | |
| 750 | For compatibility with older toolchains the assembler also accepts |
| 751 | @code{(PLT)} after branch targets. On legacy targets this will |
| 752 | generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI |
| 753 | targets it will encode either the @samp{R_ARM_CALL} or |
| 754 | @samp{R_ARM_JUMP24} relocation, as appropriate. |
| 755 | |
| 756 | @cindex MOVW and MOVT relocations, ARM |
| 757 | Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated |
| 758 | by prefixing the value with @samp{#:lower16:} and @samp{#:upper16} |
| 759 | respectively. For example to load the 32-bit address of foo into r0: |
| 760 | |
| 761 | @smallexample |
| 762 | MOVW r0, #:lower16:foo |
| 763 | MOVT r0, #:upper16:foo |
| 764 | @end smallexample |
| 765 | |
| 766 | Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC}, |
| 767 | @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be |
| 768 | generated by prefixing the value with @samp{#:lower0_7:#}, |
| 769 | @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#} |
| 770 | respectively. For example to load the 32-bit address of foo into r0: |
| 771 | |
| 772 | @smallexample |
| 773 | MOVS r0, #:upper8_15:#foo |
| 774 | LSLS r0, r0, #8 |
| 775 | ADDS r0, #:upper0_7:#foo |
| 776 | LSLS r0, r0, #8 |
| 777 | ADDS r0, #:lower8_15:#foo |
| 778 | LSLS r0, r0, #8 |
| 779 | ADDS r0, #:lower0_7:#foo |
| 780 | @end smallexample |
| 781 | |
| 782 | @node ARM-Neon-Alignment |
| 783 | @subsection NEON Alignment Specifiers |
| 784 | |
| 785 | @cindex alignment for NEON instructions |
| 786 | Some NEON load/store instructions allow an optional address |
| 787 | alignment qualifier. |
| 788 | The ARM documentation specifies that this is indicated by |
| 789 | @samp{@@ @var{align}}. However GAS already interprets |
| 790 | the @samp{@@} character as a "line comment" start, |
| 791 | so @samp{: @var{align}} is used instead. For example: |
| 792 | |
| 793 | @smallexample |
| 794 | vld1.8 @{q0@}, [r0, :128] |
| 795 | @end smallexample |
| 796 | |
| 797 | @node ARM Floating Point |
| 798 | @section Floating Point |
| 799 | |
| 800 | @cindex floating point, ARM (@sc{ieee}) |
| 801 | @cindex ARM floating point (@sc{ieee}) |
| 802 | The ARM family uses @sc{ieee} floating-point numbers. |
| 803 | |
| 804 | @node ARM Directives |
| 805 | @section ARM Machine Directives |
| 806 | |
| 807 | @cindex machine directives, ARM |
| 808 | @cindex ARM machine directives |
| 809 | @table @code |
| 810 | |
| 811 | @c AAAAAAAAAAAAAAAAAAAAAAAAA |
| 812 | |
| 813 | @ifclear ELF |
| 814 | @cindex @code{.2byte} directive, ARM |
| 815 | @cindex @code{.4byte} directive, ARM |
| 816 | @cindex @code{.8byte} directive, ARM |
| 817 | @item .2byte @var{expression} [, @var{expression}]* |
| 818 | @itemx .4byte @var{expression} [, @var{expression}]* |
| 819 | @itemx .8byte @var{expression} [, @var{expression}]* |
| 820 | These directives write 2, 4 or 8 byte values to the output section. |
| 821 | @end ifclear |
| 822 | |
| 823 | @cindex @code{.align} directive, ARM |
| 824 | @item .align @var{expression} [, @var{expression}] |
| 825 | This is the generic @var{.align} directive. For the ARM however if the |
| 826 | first argument is zero (ie no alignment is needed) the assembler will |
| 827 | behave as if the argument had been 2 (ie pad to the next four byte |
| 828 | boundary). This is for compatibility with ARM's own assembler. |
| 829 | |
| 830 | @cindex @code{.arch} directive, ARM |
| 831 | @item .arch @var{name} |
| 832 | Select the target architecture. Valid values for @var{name} are the same as |
| 833 | for the @option{-march} command-line option without the instruction set |
| 834 | extension. |
| 835 | |
| 836 | Specifying @code{.arch} clears any previously selected architecture |
| 837 | extensions. |
| 838 | |
| 839 | @cindex @code{.arch_extension} directive, ARM |
| 840 | @item .arch_extension @var{name} |
| 841 | Add or remove an architecture extension to the target architecture. Valid |
| 842 | values for @var{name} are the same as those accepted as architectural |
| 843 | extensions by the @option{-mcpu} and @option{-march} command-line options. |
| 844 | |
| 845 | @code{.arch_extension} may be used multiple times to add or remove extensions |
| 846 | incrementally to the architecture being compiled for. |
| 847 | |
| 848 | @cindex @code{.arm} directive, ARM |
| 849 | @item .arm |
| 850 | This performs the same action as @var{.code 32}. |
| 851 | |
| 852 | @c BBBBBBBBBBBBBBBBBBBBBBBBBB |
| 853 | |
| 854 | @cindex @code{.bss} directive, ARM |
| 855 | @item .bss |
| 856 | This directive switches to the @code{.bss} section. |
| 857 | |
| 858 | @c CCCCCCCCCCCCCCCCCCCCCCCCCC |
| 859 | |
| 860 | @cindex @code{.cantunwind} directive, ARM |
| 861 | @item .cantunwind |
| 862 | Prevents unwinding through the current function. No personality routine |
| 863 | or exception table data is required or permitted. |
| 864 | |
| 865 | @cindex @code{.code} directive, ARM |
| 866 | @item .code @code{[16|32]} |
| 867 | This directive selects the instruction set being generated. The value 16 |
| 868 | selects Thumb, with the value 32 selecting ARM. |
| 869 | |
| 870 | @cindex @code{.cpu} directive, ARM |
| 871 | @item .cpu @var{name} |
| 872 | Select the target processor. Valid values for @var{name} are the same as |
| 873 | for the @option{-mcpu} command-line option without the instruction set |
| 874 | extension. |
| 875 | |
| 876 | Specifying @code{.cpu} clears any previously selected architecture |
| 877 | extensions. |
| 878 | |
| 879 | @c DDDDDDDDDDDDDDDDDDDDDDDDDD |
| 880 | |
| 881 | @cindex @code{.dn} and @code{.qn} directives, ARM |
| 882 | @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]] |
| 883 | @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]] |
| 884 | |
| 885 | The @code{dn} and @code{qn} directives are used to create typed |
| 886 | and/or indexed register aliases for use in Advanced SIMD Extension |
| 887 | (Neon) instructions. The former should be used to create aliases |
| 888 | of double-precision registers, and the latter to create aliases of |
| 889 | quad-precision registers. |
| 890 | |
| 891 | If these directives are used to create typed aliases, those aliases can |
| 892 | be used in Neon instructions instead of writing types after the mnemonic |
| 893 | or after each operand. For example: |
| 894 | |
| 895 | @smallexample |
| 896 | x .dn d2.f32 |
| 897 | y .dn d3.f32 |
| 898 | z .dn d4.f32[1] |
| 899 | vmul x,y,z |
| 900 | @end smallexample |
| 901 | |
| 902 | This is equivalent to writing the following: |
| 903 | |
| 904 | @smallexample |
| 905 | vmul.f32 d2,d3,d4[1] |
| 906 | @end smallexample |
| 907 | |
| 908 | Aliases created using @code{dn} or @code{qn} can be destroyed using |
| 909 | @code{unreq}. |
| 910 | |
| 911 | @c EEEEEEEEEEEEEEEEEEEEEEEEEE |
| 912 | |
| 913 | @cindex @code{.eabi_attribute} directive, ARM |
| 914 | @item .eabi_attribute @var{tag}, @var{value} |
| 915 | Set the EABI object attribute @var{tag} to @var{value}. |
| 916 | |
| 917 | The @var{tag} is either an attribute number, or one of the following: |
| 918 | @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch}, |
| 919 | @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use}, |
| 920 | @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch}, |
| 921 | @code{Tag_Advanced_SIMD_arch}, @code{Tag_MVE_arch}, @code{Tag_PCS_config}, |
| 922 | @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data}, |
| 923 | @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use}, |
| 924 | @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding}, |
| 925 | @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions}, |
| 926 | @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model}, |
| 927 | @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved}, |
| 928 | @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use}, |
| 929 | @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args}, |
| 930 | @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals}, |
| 931 | @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access}, |
| 932 | @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format}, |
| 933 | @code{Tag_MPextension_use}, @code{Tag_DIV_use}, |
| 934 | @code{Tag_nodefaults}, @code{Tag_also_compatible_with}, |
| 935 | @code{Tag_conformance}, @code{Tag_T2EE_use}, |
| 936 | @code{Tag_Virtualization_use} |
| 937 | |
| 938 | The @var{value} is either a @code{number}, @code{"string"}, or |
| 939 | @code{number, "string"} depending on the tag. |
| 940 | |
| 941 | Note - the following legacy values are also accepted by @var{tag}: |
| 942 | @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed}, |
| 943 | @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension}, |
| 944 | |
| 945 | @cindex @code{.even} directive, ARM |
| 946 | @item .even |
| 947 | This directive aligns to an even-numbered address. |
| 948 | |
| 949 | @cindex @code{.extend} directive, ARM |
| 950 | @cindex @code{.ldouble} directive, ARM |
| 951 | @item .extend @var{expression} [, @var{expression}]* |
| 952 | @itemx .ldouble @var{expression} [, @var{expression}]* |
| 953 | These directives write 12byte long double floating-point values to the |
| 954 | output section. These are not compatible with current ARM processors |
| 955 | or ABIs. |
| 956 | |
| 957 | @c FFFFFFFFFFFFFFFFFFFFFFFFFF |
| 958 | |
| 959 | @cindex @code{.float16} directive, ARM |
| 960 | @item .float16 @var{value [,...,value_n]} |
| 961 | Place the half precision floating point representation of one or more |
| 962 | floating-point values into the current section. The exact format of the |
| 963 | encoding is specified by @code{.float16_format}. If the format has not |
| 964 | been explicitly set yet (either via the @code{.float16_format} directive or |
| 965 | the command line option) then the IEEE 754-2008 format is used. |
| 966 | |
| 967 | @cindex @code{.float16_format} directive, ARM |
| 968 | @item .float16_format @var{format} |
| 969 | Set the format to use when encoding float16 values emitted by |
| 970 | the @code{.float16} directive. |
| 971 | Once the format has been set it cannot be changed. |
| 972 | @code{format} should be one of the following: @code{ieee} (encode in |
| 973 | the IEEE 754-2008 half precision format) or @code{alternative} (encode in |
| 974 | the Arm alternative half precision format). |
| 975 | |
| 976 | @anchor{arm_fnend} |
| 977 | @cindex @code{.fnend} directive, ARM |
| 978 | @item .fnend |
| 979 | Marks the end of a function with an unwind table entry. The unwind index |
| 980 | table entry is created when this directive is processed. |
| 981 | |
| 982 | If no personality routine has been specified then standard personality |
| 983 | routine 0 or 1 will be used, depending on the number of unwind opcodes |
| 984 | required. |
| 985 | |
| 986 | @anchor{arm_fnstart} |
| 987 | @cindex @code{.fnstart} directive, ARM |
| 988 | @item .fnstart |
| 989 | Marks the start of a function with an unwind table entry. |
| 990 | |
| 991 | @cindex @code{.force_thumb} directive, ARM |
| 992 | @item .force_thumb |
| 993 | This directive forces the selection of Thumb instructions, even if the |
| 994 | target processor does not support those instructions |
| 995 | |
| 996 | @cindex @code{.fpu} directive, ARM |
| 997 | @item .fpu @var{name} |
| 998 | Select the floating-point unit to assemble for. Valid values for @var{name} |
| 999 | are the same as for the @option{-mfpu} command-line option. |
| 1000 | |
| 1001 | @c GGGGGGGGGGGGGGGGGGGGGGGGGG |
| 1002 | @c HHHHHHHHHHHHHHHHHHHHHHHHHH |
| 1003 | |
| 1004 | @cindex @code{.handlerdata} directive, ARM |
| 1005 | @item .handlerdata |
| 1006 | Marks the end of the current function, and the start of the exception table |
| 1007 | entry for that function. Anything between this directive and the |
| 1008 | @code{.fnend} directive will be added to the exception table entry. |
| 1009 | |
| 1010 | Must be preceded by a @code{.personality} or @code{.personalityindex} |
| 1011 | directive. |
| 1012 | |
| 1013 | @c IIIIIIIIIIIIIIIIIIIIIIIIII |
| 1014 | |
| 1015 | @cindex @code{.inst} directive, ARM |
| 1016 | @item .inst @var{opcode} [ , @dots{} ] |
| 1017 | @itemx .inst.n @var{opcode} [ , @dots{} ] |
| 1018 | @itemx .inst.w @var{opcode} [ , @dots{} ] |
| 1019 | Generates the instruction corresponding to the numerical value @var{opcode}. |
| 1020 | @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be |
| 1021 | specified explicitly, overriding the normal encoding rules. |
| 1022 | |
| 1023 | @c JJJJJJJJJJJJJJJJJJJJJJJJJJ |
| 1024 | @c KKKKKKKKKKKKKKKKKKKKKKKKKK |
| 1025 | @c LLLLLLLLLLLLLLLLLLLLLLLLLL |
| 1026 | |
| 1027 | @item .ldouble @var{expression} [, @var{expression}]* |
| 1028 | See @code{.extend}. |
| 1029 | |
| 1030 | @cindex @code{.ltorg} directive, ARM |
| 1031 | @item .ltorg |
| 1032 | This directive causes the current contents of the literal pool to be |
| 1033 | dumped into the current section (which is assumed to be the .text |
| 1034 | section) at the current location (aligned to a word boundary). |
| 1035 | @code{GAS} maintains a separate literal pool for each section and each |
| 1036 | sub-section. The @code{.ltorg} directive will only affect the literal |
| 1037 | pool of the current section and sub-section. At the end of assembly |
| 1038 | all remaining, un-empty literal pools will automatically be dumped. |
| 1039 | |
| 1040 | Note - older versions of @code{GAS} would dump the current literal |
| 1041 | pool any time a section change occurred. This is no longer done, since |
| 1042 | it prevents accurate control of the placement of literal pools. |
| 1043 | |
| 1044 | @c MMMMMMMMMMMMMMMMMMMMMMMMMM |
| 1045 | |
| 1046 | @cindex @code{.movsp} directive, ARM |
| 1047 | @item .movsp @var{reg} [, #@var{offset}] |
| 1048 | Tell the unwinder that @var{reg} contains an offset from the current |
| 1049 | stack pointer. If @var{offset} is not specified then it is assumed to be |
| 1050 | zero. |
| 1051 | |
| 1052 | @c NNNNNNNNNNNNNNNNNNNNNNNNNN |
| 1053 | @c OOOOOOOOOOOOOOOOOOOOOOOOOO |
| 1054 | |
| 1055 | @cindex @code{.object_arch} directive, ARM |
| 1056 | @item .object_arch @var{name} |
| 1057 | Override the architecture recorded in the EABI object attribute section. |
| 1058 | Valid values for @var{name} are the same as for the @code{.arch} directive. |
| 1059 | Typically this is useful when code uses runtime detection of CPU features. |
| 1060 | |
| 1061 | @c PPPPPPPPPPPPPPPPPPPPPPPPPP |
| 1062 | |
| 1063 | @cindex @code{.packed} directive, ARM |
| 1064 | @item .packed @var{expression} [, @var{expression}]* |
| 1065 | This directive writes 12-byte packed floating-point values to the |
| 1066 | output section. These are not compatible with current ARM processors |
| 1067 | or ABIs. |
| 1068 | |
| 1069 | @anchor{arm_pad} |
| 1070 | @cindex @code{.pad} directive, ARM |
| 1071 | @item .pad #@var{count} |
| 1072 | Generate unwinder annotations for a stack adjustment of @var{count} bytes. |
| 1073 | A positive value indicates the function prologue allocated stack space by |
| 1074 | decrementing the stack pointer. |
| 1075 | |
| 1076 | @cindex @code{.personality} directive, ARM |
| 1077 | @item .personality @var{name} |
| 1078 | Sets the personality routine for the current function to @var{name}. |
| 1079 | |
| 1080 | @cindex @code{.personalityindex} directive, ARM |
| 1081 | @item .personalityindex @var{index} |
| 1082 | Sets the personality routine for the current function to the EABI standard |
| 1083 | routine number @var{index} |
| 1084 | |
| 1085 | @cindex @code{.pool} directive, ARM |
| 1086 | @item .pool |
| 1087 | This is a synonym for .ltorg. |
| 1088 | |
| 1089 | @c QQQQQQQQQQQQQQQQQQQQQQQQQQ |
| 1090 | @c RRRRRRRRRRRRRRRRRRRRRRRRRR |
| 1091 | |
| 1092 | @cindex @code{.req} directive, ARM |
| 1093 | @item @var{name} .req @var{register name} |
| 1094 | This creates an alias for @var{register name} called @var{name}. For |
| 1095 | example: |
| 1096 | |
| 1097 | @smallexample |
| 1098 | foo .req r0 |
| 1099 | @end smallexample |
| 1100 | |
| 1101 | @c SSSSSSSSSSSSSSSSSSSSSSSSSS |
| 1102 | |
| 1103 | @anchor{arm_save} |
| 1104 | @cindex @code{.save} directive, ARM |
| 1105 | @item .save @var{reglist} |
| 1106 | Generate unwinder annotations to restore the registers in @var{reglist}. |
| 1107 | The format of @var{reglist} is the same as the corresponding store-multiple |
| 1108 | instruction. |
| 1109 | |
| 1110 | @smallexample |
| 1111 | @exdent @emph{core registers} |
| 1112 | .save @{r4, r5, r6, lr@} |
| 1113 | stmfd sp!, @{r4, r5, r6, lr@} |
| 1114 | @exdent @emph{FPA registers} |
| 1115 | .save f4, 2 |
| 1116 | sfmfd f4, 2, [sp]! |
| 1117 | @exdent @emph{VFP registers} |
| 1118 | .save @{d8, d9, d10@} |
| 1119 | fstmdx sp!, @{d8, d9, d10@} |
| 1120 | @exdent @emph{iWMMXt registers} |
| 1121 | .save @{wr10, wr11@} |
| 1122 | wstrd wr11, [sp, #-8]! |
| 1123 | wstrd wr10, [sp, #-8]! |
| 1124 | or |
| 1125 | .save wr11 |
| 1126 | wstrd wr11, [sp, #-8]! |
| 1127 | .save wr10 |
| 1128 | wstrd wr10, [sp, #-8]! |
| 1129 | @end smallexample |
| 1130 | |
| 1131 | @anchor{arm_setfp} |
| 1132 | @cindex @code{.setfp} directive, ARM |
| 1133 | @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}] |
| 1134 | Make all unwinder annotations relative to a frame pointer. Without this |
| 1135 | the unwinder will use offsets from the stack pointer. |
| 1136 | |
| 1137 | The syntax of this directive is the same as the @code{add} or @code{mov} |
| 1138 | instruction used to set the frame pointer. @var{spreg} must be either |
| 1139 | @code{sp} or mentioned in a previous @code{.movsp} directive. |
| 1140 | |
| 1141 | @smallexample |
| 1142 | .movsp ip |
| 1143 | mov ip, sp |
| 1144 | @dots{} |
| 1145 | .setfp fp, ip, #4 |
| 1146 | add fp, ip, #4 |
| 1147 | @end smallexample |
| 1148 | |
| 1149 | @cindex @code{.secrel32} directive, ARM |
| 1150 | @item .secrel32 @var{expression} [, @var{expression}]* |
| 1151 | This directive emits relocations that evaluate to the section-relative |
| 1152 | offset of each expression's symbol. This directive is only supported |
| 1153 | for PE targets. |
| 1154 | |
| 1155 | @cindex @code{.syntax} directive, ARM |
| 1156 | @item .syntax [@code{unified} | @code{divided}] |
| 1157 | This directive sets the Instruction Set Syntax as described in the |
| 1158 | @ref{ARM-Instruction-Set} section. |
| 1159 | |
| 1160 | @c TTTTTTTTTTTTTTTTTTTTTTTTTT |
| 1161 | |
| 1162 | @cindex @code{.thumb} directive, ARM |
| 1163 | @item .thumb |
| 1164 | This performs the same action as @var{.code 16}. |
| 1165 | |
| 1166 | @cindex @code{.thumb_func} directive, ARM |
| 1167 | @item .thumb_func |
| 1168 | This directive specifies that the following symbol is the name of a |
| 1169 | Thumb encoded function. This information is necessary in order to allow |
| 1170 | the assembler and linker to generate correct code for interworking |
| 1171 | between Arm and Thumb instructions and should be used even if |
| 1172 | interworking is not going to be performed. The presence of this |
| 1173 | directive also implies @code{.thumb} |
| 1174 | |
| 1175 | This directive is not necessary when generating EABI objects. On these |
| 1176 | targets the encoding is implicit when generating Thumb code. |
| 1177 | |
| 1178 | @cindex @code{.thumb_set} directive, ARM |
| 1179 | @item .thumb_set |
| 1180 | This performs the equivalent of a @code{.set} directive in that it |
| 1181 | creates a symbol which is an alias for another symbol (possibly not yet |
| 1182 | defined). This directive also has the added property in that it marks |
| 1183 | the aliased symbol as being a thumb function entry point, in the same |
| 1184 | way that the @code{.thumb_func} directive does. |
| 1185 | |
| 1186 | @cindex @code{.tlsdescseq} directive, ARM |
| 1187 | @item .tlsdescseq @var{tls-variable} |
| 1188 | This directive is used to annotate parts of an inlined TLS descriptor |
| 1189 | trampoline. Normally the trampoline is provided by the linker, and |
| 1190 | this directive is not needed. |
| 1191 | |
| 1192 | @c UUUUUUUUUUUUUUUUUUUUUUUUUU |
| 1193 | |
| 1194 | @cindex @code{.unreq} directive, ARM |
| 1195 | @item .unreq @var{alias-name} |
| 1196 | This undefines a register alias which was previously defined using the |
| 1197 | @code{req}, @code{dn} or @code{qn} directives. For example: |
| 1198 | |
| 1199 | @smallexample |
| 1200 | foo .req r0 |
| 1201 | .unreq foo |
| 1202 | @end smallexample |
| 1203 | |
| 1204 | An error occurs if the name is undefined. Note - this pseudo op can |
| 1205 | be used to delete builtin in register name aliases (eg 'r0'). This |
| 1206 | should only be done if it is really necessary. |
| 1207 | |
| 1208 | @cindex @code{.unwind_raw} directive, ARM |
| 1209 | @item .unwind_raw @var{offset}, @var{byte1}, @dots{} |
| 1210 | Insert one of more arbitrary unwind opcode bytes, which are known to adjust |
| 1211 | the stack pointer by @var{offset} bytes. |
| 1212 | |
| 1213 | For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to |
| 1214 | @code{.save @{r0@}} |
| 1215 | |
| 1216 | @c VVVVVVVVVVVVVVVVVVVVVVVVVV |
| 1217 | |
| 1218 | @cindex @code{.vsave} directive, ARM |
| 1219 | @item .vsave @var{vfp-reglist} |
| 1220 | Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist} |
| 1221 | using FLDMD. Also works for VFPv3 registers |
| 1222 | that are to be restored using VLDM. |
| 1223 | The format of @var{vfp-reglist} is the same as the corresponding store-multiple |
| 1224 | instruction. |
| 1225 | |
| 1226 | @smallexample |
| 1227 | @exdent @emph{VFP registers} |
| 1228 | .vsave @{d8, d9, d10@} |
| 1229 | fstmdd sp!, @{d8, d9, d10@} |
| 1230 | @exdent @emph{VFPv3 registers} |
| 1231 | .vsave @{d15, d16, d17@} |
| 1232 | vstm sp!, @{d15, d16, d17@} |
| 1233 | @end smallexample |
| 1234 | |
| 1235 | Since FLDMX and FSTMX are now deprecated, this directive should be |
| 1236 | used in favour of @code{.save} for saving VFP registers for ARMv6 and above. |
| 1237 | |
| 1238 | @c WWWWWWWWWWWWWWWWWWWWWWWWWW |
| 1239 | @c XXXXXXXXXXXXXXXXXXXXXXXXXX |
| 1240 | @c YYYYYYYYYYYYYYYYYYYYYYYYYY |
| 1241 | @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ |
| 1242 | |
| 1243 | @end table |
| 1244 | |
| 1245 | @node ARM Opcodes |
| 1246 | @section Opcodes |
| 1247 | |
| 1248 | @cindex ARM opcodes |
| 1249 | @cindex opcodes for ARM |
| 1250 | @code{@value{AS}} implements all the standard ARM opcodes. It also |
| 1251 | implements several pseudo opcodes, including several synthetic load |
| 1252 | instructions. |
| 1253 | |
| 1254 | @table @code |
| 1255 | |
| 1256 | @cindex @code{NOP} pseudo op, ARM |
| 1257 | @item NOP |
| 1258 | @smallexample |
| 1259 | nop |
| 1260 | @end smallexample |
| 1261 | |
| 1262 | This pseudo op will always evaluate to a legal ARM instruction that does |
| 1263 | nothing. Currently it will evaluate to MOV r0, r0. |
| 1264 | |
| 1265 | @cindex @code{LDR reg,=<label>} pseudo op, ARM |
| 1266 | @item LDR |
| 1267 | @smallexample |
| 1268 | ldr <register> , = <expression> |
| 1269 | @end smallexample |
| 1270 | |
| 1271 | If expression evaluates to a numeric constant then a MOV or MVN |
| 1272 | instruction will be used in place of the LDR instruction, if the |
| 1273 | constant can be generated by either of these instructions. Otherwise |
| 1274 | the constant will be placed into the nearest literal pool (if it not |
| 1275 | already there) and a PC relative LDR instruction will be generated. |
| 1276 | |
| 1277 | @cindex @code{ADR reg,<label>} pseudo op, ARM |
| 1278 | @item ADR |
| 1279 | @smallexample |
| 1280 | adr <register> <label> |
| 1281 | @end smallexample |
| 1282 | |
| 1283 | This instruction will load the address of @var{label} into the indicated |
| 1284 | register. The instruction will evaluate to a PC relative ADD or SUB |
| 1285 | instruction depending upon where the label is located. If the label is |
| 1286 | out of range, or if it is not defined in the same file (and section) as |
| 1287 | the ADR instruction, then an error will be generated. This instruction |
| 1288 | will not make use of the literal pool. |
| 1289 | |
| 1290 | If @var{label} is a thumb function symbol, and thumb interworking has |
| 1291 | been enabled via the @option{-mthumb-interwork} option then the bottom |
| 1292 | bit of the value stored into @var{register} will be set. This allows |
| 1293 | the following sequence to work as expected: |
| 1294 | |
| 1295 | @smallexample |
| 1296 | adr r0, thumb_function |
| 1297 | blx r0 |
| 1298 | @end smallexample |
| 1299 | |
| 1300 | @cindex @code{ADRL reg,<label>} pseudo op, ARM |
| 1301 | @item ADRL |
| 1302 | @smallexample |
| 1303 | adrl <register> <label> |
| 1304 | @end smallexample |
| 1305 | |
| 1306 | This instruction will load the address of @var{label} into the indicated |
| 1307 | register. The instruction will evaluate to one or two PC relative ADD |
| 1308 | or SUB instructions depending upon where the label is located. If a |
| 1309 | second instruction is not needed a NOP instruction will be generated in |
| 1310 | its place, so that this instruction is always 8 bytes long. |
| 1311 | |
| 1312 | If the label is out of range, or if it is not defined in the same file |
| 1313 | (and section) as the ADRL instruction, then an error will be generated. |
| 1314 | This instruction will not make use of the literal pool. |
| 1315 | |
| 1316 | If @var{label} is a thumb function symbol, and thumb interworking has |
| 1317 | been enabled via the @option{-mthumb-interwork} option then the bottom |
| 1318 | bit of the value stored into @var{register} will be set. |
| 1319 | |
| 1320 | @end table |
| 1321 | |
| 1322 | For information on the ARM or Thumb instruction sets, see @cite{ARM |
| 1323 | Software Development Toolkit Reference Manual}, Advanced RISC Machines |
| 1324 | Ltd. |
| 1325 | |
| 1326 | @node ARM Mapping Symbols |
| 1327 | @section Mapping Symbols |
| 1328 | |
| 1329 | The ARM ELF specification requires that special symbols be inserted |
| 1330 | into object files to mark certain features: |
| 1331 | |
| 1332 | @table @code |
| 1333 | |
| 1334 | @cindex @code{$a} |
| 1335 | @item $a |
| 1336 | At the start of a region of code containing ARM instructions. |
| 1337 | |
| 1338 | @cindex @code{$t} |
| 1339 | @item $t |
| 1340 | At the start of a region of code containing THUMB instructions. |
| 1341 | |
| 1342 | @cindex @code{$d} |
| 1343 | @item $d |
| 1344 | At the start of a region of data. |
| 1345 | |
| 1346 | @end table |
| 1347 | |
| 1348 | The assembler will automatically insert these symbols for you - there |
| 1349 | is no need to code them yourself. Support for tagging symbols ($b, |
| 1350 | $f, $p and $m) which is also mentioned in the current ARM ELF |
| 1351 | specification is not implemented. This is because they have been |
| 1352 | dropped from the new EABI and so tools cannot rely upon their |
| 1353 | presence. |
| 1354 | |
| 1355 | @node ARM Unwinding Tutorial |
| 1356 | @section Unwinding |
| 1357 | |
| 1358 | The ABI for the ARM Architecture specifies a standard format for |
| 1359 | exception unwind information. This information is used when an |
| 1360 | exception is thrown to determine where control should be transferred. |
| 1361 | In particular, the unwind information is used to determine which |
| 1362 | function called the function that threw the exception, and which |
| 1363 | function called that one, and so forth. This information is also used |
| 1364 | to restore the values of callee-saved registers in the function |
| 1365 | catching the exception. |
| 1366 | |
| 1367 | If you are writing functions in assembly code, and those functions |
| 1368 | call other functions that throw exceptions, you must use assembly |
| 1369 | pseudo ops to ensure that appropriate exception unwind information is |
| 1370 | generated. Otherwise, if one of the functions called by your assembly |
| 1371 | code throws an exception, the run-time library will be unable to |
| 1372 | unwind the stack through your assembly code and your program will not |
| 1373 | behave correctly. |
| 1374 | |
| 1375 | To illustrate the use of these pseudo ops, we will examine the code |
| 1376 | that G++ generates for the following C++ input: |
| 1377 | |
| 1378 | @verbatim |
| 1379 | void callee (int *); |
| 1380 | |
| 1381 | int |
| 1382 | caller () |
| 1383 | { |
| 1384 | int i; |
| 1385 | callee (&i); |
| 1386 | return i; |
| 1387 | } |
| 1388 | @end verbatim |
| 1389 | |
| 1390 | This example does not show how to throw or catch an exception from |
| 1391 | assembly code. That is a much more complex operation and should |
| 1392 | always be done in a high-level language, such as C++, that directly |
| 1393 | supports exceptions. |
| 1394 | |
| 1395 | The code generated by one particular version of G++ when compiling the |
| 1396 | example above is: |
| 1397 | |
| 1398 | @verbatim |
| 1399 | _Z6callerv: |
| 1400 | .fnstart |
| 1401 | .LFB2: |
| 1402 | @ Function supports interworking. |
| 1403 | @ args = 0, pretend = 0, frame = 8 |
| 1404 | @ frame_needed = 1, uses_anonymous_args = 0 |
| 1405 | stmfd sp!, {fp, lr} |
| 1406 | .save {fp, lr} |
| 1407 | .LCFI0: |
| 1408 | .setfp fp, sp, #4 |
| 1409 | add fp, sp, #4 |
| 1410 | .LCFI1: |
| 1411 | .pad #8 |
| 1412 | sub sp, sp, #8 |
| 1413 | .LCFI2: |
| 1414 | sub r3, fp, #8 |
| 1415 | mov r0, r3 |
| 1416 | bl _Z6calleePi |
| 1417 | ldr r3, [fp, #-8] |
| 1418 | mov r0, r3 |
| 1419 | sub sp, fp, #4 |
| 1420 | ldmfd sp!, {fp, lr} |
| 1421 | bx lr |
| 1422 | .LFE2: |
| 1423 | .fnend |
| 1424 | @end verbatim |
| 1425 | |
| 1426 | Of course, the sequence of instructions varies based on the options |
| 1427 | you pass to GCC and on the version of GCC in use. The exact |
| 1428 | instructions are not important since we are focusing on the pseudo ops |
| 1429 | that are used to generate unwind information. |
| 1430 | |
| 1431 | An important assumption made by the unwinder is that the stack frame |
| 1432 | does not change during the body of the function. In particular, since |
| 1433 | we assume that the assembly code does not itself throw an exception, |
| 1434 | the only point where an exception can be thrown is from a call, such |
| 1435 | as the @code{bl} instruction above. At each call site, the same saved |
| 1436 | registers (including @code{lr}, which indicates the return address) |
| 1437 | must be located in the same locations relative to the frame pointer. |
| 1438 | |
| 1439 | The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo |
| 1440 | op appears immediately before the first instruction of the function |
| 1441 | while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo |
| 1442 | op appears immediately after the last instruction of the function. |
| 1443 | These pseudo ops specify the range of the function. |
| 1444 | |
| 1445 | Only the order of the other pseudos ops (e.g., @code{.setfp} or |
| 1446 | @code{.pad}) matters; their exact locations are irrelevant. In the |
| 1447 | example above, the compiler emits the pseudo ops with particular |
| 1448 | instructions. That makes it easier to understand the code, but it is |
| 1449 | not required for correctness. It would work just as well to emit all |
| 1450 | of the pseudo ops other than @code{.fnend} in the same order, but |
| 1451 | immediately after @code{.fnstart}. |
| 1452 | |
| 1453 | The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op |
| 1454 | indicates registers that have been saved to the stack so that they can |
| 1455 | be restored before the function returns. The argument to the |
| 1456 | @code{.save} pseudo op is a list of registers to save. If a register |
| 1457 | is ``callee-saved'' (as specified by the ABI) and is modified by the |
| 1458 | function you are writing, then your code must save the value before it |
| 1459 | is modified and restore the original value before the function |
| 1460 | returns. If an exception is thrown, the run-time library restores the |
| 1461 | values of these registers from their locations on the stack before |
| 1462 | returning control to the exception handler. (Of course, if an |
| 1463 | exception is not thrown, the function that contains the @code{.save} |
| 1464 | pseudo op restores these registers in the function epilogue, as is |
| 1465 | done with the @code{ldmfd} instruction above.) |
| 1466 | |
| 1467 | You do not have to save callee-saved registers at the very beginning |
| 1468 | of the function and you do not need to use the @code{.save} pseudo op |
| 1469 | immediately following the point at which the registers are saved. |
| 1470 | However, if you modify a callee-saved register, you must save it on |
| 1471 | the stack before modifying it and before calling any functions which |
| 1472 | might throw an exception. And, you must use the @code{.save} pseudo |
| 1473 | op to indicate that you have done so. |
| 1474 | |
| 1475 | The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a |
| 1476 | modification of the stack pointer that does not save any registers. |
| 1477 | The argument is the number of bytes (in decimal) that are subtracted |
| 1478 | from the stack pointer. (On ARM CPUs, the stack grows downwards, so |
| 1479 | subtracting from the stack pointer increases the size of the stack.) |
| 1480 | |
| 1481 | The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op |
| 1482 | indicates the register that contains the frame pointer. The first |
| 1483 | argument is the register that is set, which is typically @code{fp}. |
| 1484 | The second argument indicates the register from which the frame |
| 1485 | pointer takes its value. The third argument, if present, is the value |
| 1486 | (in decimal) added to the register specified by the second argument to |
| 1487 | compute the value of the frame pointer. You should not modify the |
| 1488 | frame pointer in the body of the function. |
| 1489 | |
| 1490 | If you do not use a frame pointer, then you should not use the |
| 1491 | @code{.setfp} pseudo op. If you do not use a frame pointer, then you |
| 1492 | should avoid modifying the stack pointer outside of the function |
| 1493 | prologue. Otherwise, the run-time library will be unable to find |
| 1494 | saved registers when it is unwinding the stack. |
| 1495 | |
| 1496 | The pseudo ops described above are sufficient for writing assembly |
| 1497 | code that calls functions which may throw exceptions. If you need to |
| 1498 | know more about the object-file format used to represent unwind |
| 1499 | information, you may consult the @cite{Exception Handling ABI for the |
| 1500 | ARM Architecture} available from @uref{http://infocenter.arm.com}. |
| 1501 | |