| 1 | @c Copyright (C) 1991-2019 Free Software Foundation, Inc. |
| 2 | @c This is part of the GAS manual. |
| 3 | @c For copying conditions, see the file as.texinfo. |
| 4 | @ifset GENERIC |
| 5 | @page |
| 6 | @node MIPS-Dependent |
| 7 | @chapter MIPS Dependent Features |
| 8 | @end ifset |
| 9 | @ifclear GENERIC |
| 10 | @node Machine Dependencies |
| 11 | @chapter MIPS Dependent Features |
| 12 | @end ifclear |
| 13 | |
| 14 | @cindex MIPS processor |
| 15 | @sc{gnu} @code{@value{AS}} for MIPS architectures supports several |
| 16 | different MIPS processors, and MIPS ISA levels I through V, MIPS32, |
| 17 | and MIPS64. For information about the MIPS instruction set, see |
| 18 | @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall). |
| 19 | For an overview of MIPS assembly conventions, see ``Appendix D: |
| 20 | Assembly Language Programming'' in the same work. |
| 21 | |
| 22 | @menu |
| 23 | * MIPS Options:: Assembler options |
| 24 | * MIPS Macros:: High-level assembly macros |
| 25 | * MIPS Symbol Sizes:: Directives to override the size of symbols |
| 26 | * MIPS Small Data:: Controlling the use of small data accesses |
| 27 | * MIPS ISA:: Directives to override the ISA level |
| 28 | * MIPS assembly options:: Directives to control code generation |
| 29 | * MIPS autoextend:: Directives for extending MIPS 16 bit instructions |
| 30 | * MIPS insn:: Directive to mark data as an instruction |
| 31 | * MIPS FP ABIs:: Marking which FP ABI is in use |
| 32 | * MIPS NaN Encodings:: Directives to record which NaN encoding is being used |
| 33 | * MIPS Option Stack:: Directives to save and restore options |
| 34 | * MIPS ASE Instruction Generation Overrides:: Directives to control |
| 35 | generation of MIPS ASE instructions |
| 36 | * MIPS Floating-Point:: Directives to override floating-point options |
| 37 | * MIPS Syntax:: MIPS specific syntactical considerations |
| 38 | @end menu |
| 39 | |
| 40 | @node MIPS Options |
| 41 | @section Assembler options |
| 42 | |
| 43 | The MIPS configurations of @sc{gnu} @code{@value{AS}} support these |
| 44 | special options: |
| 45 | |
| 46 | @table @code |
| 47 | @cindex @code{-G} option (MIPS) |
| 48 | @item -G @var{num} |
| 49 | Set the ``small data'' limit to @var{n} bytes. The default limit is 8 bytes. |
| 50 | @xref{MIPS Small Data,, Controlling the use of small data accesses}. |
| 51 | |
| 52 | @cindex @code{-EB} option (MIPS) |
| 53 | @cindex @code{-EL} option (MIPS) |
| 54 | @cindex MIPS big-endian output |
| 55 | @cindex MIPS little-endian output |
| 56 | @cindex big-endian output, MIPS |
| 57 | @cindex little-endian output, MIPS |
| 58 | @item -EB |
| 59 | @itemx -EL |
| 60 | Any MIPS configuration of @code{@value{AS}} can select big-endian or |
| 61 | little-endian output at run time (unlike the other @sc{gnu} development |
| 62 | tools, which must be configured for one or the other). Use @samp{-EB} |
| 63 | to select big-endian output, and @samp{-EL} for little-endian. |
| 64 | |
| 65 | @item -KPIC |
| 66 | @cindex PIC selection, MIPS |
| 67 | @cindex @option{-KPIC} option, MIPS |
| 68 | Generate SVR4-style PIC. This option tells the assembler to generate |
| 69 | SVR4-style position-independent macro expansions. It also tells the |
| 70 | assembler to mark the output file as PIC. |
| 71 | |
| 72 | @item -mvxworks-pic |
| 73 | @cindex @option{-mvxworks-pic} option, MIPS |
| 74 | Generate VxWorks PIC. This option tells the assembler to generate |
| 75 | VxWorks-style position-independent macro expansions. |
| 76 | |
| 77 | @cindex MIPS architecture options |
| 78 | @item -mips1 |
| 79 | @itemx -mips2 |
| 80 | @itemx -mips3 |
| 81 | @itemx -mips4 |
| 82 | @itemx -mips5 |
| 83 | @itemx -mips32 |
| 84 | @itemx -mips32r2 |
| 85 | @itemx -mips32r3 |
| 86 | @itemx -mips32r5 |
| 87 | @itemx -mips32r6 |
| 88 | @itemx -mips64 |
| 89 | @itemx -mips64r2 |
| 90 | @itemx -mips64r3 |
| 91 | @itemx -mips64r5 |
| 92 | @itemx -mips64r6 |
| 93 | Generate code for a particular MIPS Instruction Set Architecture level. |
| 94 | @samp{-mips1} corresponds to the R2000 and R3000 processors, |
| 95 | @samp{-mips2} to the R6000 processor, @samp{-mips3} to the |
| 96 | R4000 processor, and @samp{-mips4} to the R8000 and R10000 processors. |
| 97 | @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3}, |
| 98 | @samp{-mips32r5}, @samp{-mips32r6}, @samp{-mips64}, @samp{-mips64r2}, |
| 99 | @samp{-mips64r3}, @samp{-mips64r5}, and @samp{-mips64r6} correspond to |
| 100 | generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 |
| 101 | Release 5, MIPS32 Release 6, MIPS64, and MIPS64 Release 2, MIPS64 |
| 102 | Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, |
| 103 | respectively. You can also switch instruction sets during the assembly; |
| 104 | see @ref{MIPS ISA, Directives to override the ISA level}. |
| 105 | |
| 106 | @item -mgp32 |
| 107 | @itemx -mfp32 |
| 108 | Some macros have different expansions for 32-bit and 64-bit registers. |
| 109 | The register sizes are normally inferred from the ISA and ABI, but these |
| 110 | flags force a certain group of registers to be treated as 32 bits wide at |
| 111 | all times. @samp{-mgp32} controls the size of general-purpose registers |
| 112 | and @samp{-mfp32} controls the size of floating-point registers. |
| 113 | |
| 114 | The @code{.set gp=32} and @code{.set fp=32} directives allow the size |
| 115 | of registers to be changed for parts of an object. The default value is |
| 116 | restored by @code{.set gp=default} and @code{.set fp=default}. |
| 117 | |
| 118 | On some MIPS variants there is a 32-bit mode flag; when this flag is |
| 119 | set, 64-bit instructions generate a trap. Also, some 32-bit OSes only |
| 120 | save the 32-bit registers on a context switch, so it is essential never |
| 121 | to use the 64-bit registers. |
| 122 | |
| 123 | @item -mgp64 |
| 124 | @itemx -mfp64 |
| 125 | Assume that 64-bit registers are available. This is provided in the |
| 126 | interests of symmetry with @samp{-mgp32} and @samp{-mfp32}. |
| 127 | |
| 128 | The @code{.set gp=64} and @code{.set fp=64} directives allow the size |
| 129 | of registers to be changed for parts of an object. The default value is |
| 130 | restored by @code{.set gp=default} and @code{.set fp=default}. |
| 131 | |
| 132 | @item -mfpxx |
| 133 | Make no assumptions about whether 32-bit or 64-bit floating-point |
| 134 | registers are available. This is provided to support having modules |
| 135 | compatible with either @samp{-mfp32} or @samp{-mfp64}. This option can |
| 136 | only be used with MIPS II and above. |
| 137 | |
| 138 | The @code{.set fp=xx} directive allows a part of an object to be marked |
| 139 | as not making assumptions about 32-bit or 64-bit FP registers. The |
| 140 | default value is restored by @code{.set fp=default}. |
| 141 | |
| 142 | @item -modd-spreg |
| 143 | @itemx -mno-odd-spreg |
| 144 | Enable use of floating-point operations on odd-numbered single-precision |
| 145 | registers when supported by the ISA. @samp{-mfpxx} implies |
| 146 | @samp{-mno-odd-spreg}, otherwise the default is @samp{-modd-spreg} |
| 147 | |
| 148 | @item -mips16 |
| 149 | @itemx -no-mips16 |
| 150 | Generate code for the MIPS 16 processor. This is equivalent to putting |
| 151 | @code{.module mips16} at the start of the assembly file. @samp{-no-mips16} |
| 152 | turns off this option. |
| 153 | |
| 154 | @item -mmips16e2 |
| 155 | @itemx -mno-mips16e2 |
| 156 | Enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent |
| 157 | to putting @code{.module mips16e2} at the start of the assembly file. |
| 158 | @samp{-mno-mips16e2} turns off this option. |
| 159 | |
| 160 | @item -mmicromips |
| 161 | @itemx -mno-micromips |
| 162 | Generate code for the microMIPS processor. This is equivalent to putting |
| 163 | @code{.module micromips} at the start of the assembly file. |
| 164 | @samp{-mno-micromips} turns off this option. This is equivalent to putting |
| 165 | @code{.module nomicromips} at the start of the assembly file. |
| 166 | |
| 167 | @item -msmartmips |
| 168 | @itemx -mno-smartmips |
| 169 | Enables the SmartMIPS extensions to the MIPS32 instruction set, which |
| 170 | provides a number of new instructions which target smartcard and |
| 171 | cryptographic applications. This is equivalent to putting |
| 172 | @code{.module smartmips} at the start of the assembly file. |
| 173 | @samp{-mno-smartmips} turns off this option. |
| 174 | |
| 175 | @item -mips3d |
| 176 | @itemx -no-mips3d |
| 177 | Generate code for the MIPS-3D Application Specific Extension. |
| 178 | This tells the assembler to accept MIPS-3D instructions. |
| 179 | @samp{-no-mips3d} turns off this option. |
| 180 | |
| 181 | @item -mdmx |
| 182 | @itemx -no-mdmx |
| 183 | Generate code for the MDMX Application Specific Extension. |
| 184 | This tells the assembler to accept MDMX instructions. |
| 185 | @samp{-no-mdmx} turns off this option. |
| 186 | |
| 187 | @item -mdsp |
| 188 | @itemx -mno-dsp |
| 189 | Generate code for the DSP Release 1 Application Specific Extension. |
| 190 | This tells the assembler to accept DSP Release 1 instructions. |
| 191 | @samp{-mno-dsp} turns off this option. |
| 192 | |
| 193 | @item -mdspr2 |
| 194 | @itemx -mno-dspr2 |
| 195 | Generate code for the DSP Release 2 Application Specific Extension. |
| 196 | This option implies @samp{-mdsp}. |
| 197 | This tells the assembler to accept DSP Release 2 instructions. |
| 198 | @samp{-mno-dspr2} turns off this option. |
| 199 | |
| 200 | @item -mdspr3 |
| 201 | @itemx -mno-dspr3 |
| 202 | Generate code for the DSP Release 3 Application Specific Extension. |
| 203 | This option implies @samp{-mdsp} and @samp{-mdspr2}. |
| 204 | This tells the assembler to accept DSP Release 3 instructions. |
| 205 | @samp{-mno-dspr3} turns off this option. |
| 206 | |
| 207 | @item -mmt |
| 208 | @itemx -mno-mt |
| 209 | Generate code for the MT Application Specific Extension. |
| 210 | This tells the assembler to accept MT instructions. |
| 211 | @samp{-mno-mt} turns off this option. |
| 212 | |
| 213 | @item -mmcu |
| 214 | @itemx -mno-mcu |
| 215 | Generate code for the MCU Application Specific Extension. |
| 216 | This tells the assembler to accept MCU instructions. |
| 217 | @samp{-mno-mcu} turns off this option. |
| 218 | |
| 219 | @item -mmsa |
| 220 | @itemx -mno-msa |
| 221 | Generate code for the MIPS SIMD Architecture Extension. |
| 222 | This tells the assembler to accept MSA instructions. |
| 223 | @samp{-mno-msa} turns off this option. |
| 224 | |
| 225 | @item -mxpa |
| 226 | @itemx -mno-xpa |
| 227 | Generate code for the MIPS eXtended Physical Address (XPA) Extension. |
| 228 | This tells the assembler to accept XPA instructions. |
| 229 | @samp{-mno-xpa} turns off this option. |
| 230 | |
| 231 | @item -mvirt |
| 232 | @itemx -mno-virt |
| 233 | Generate code for the Virtualization Application Specific Extension. |
| 234 | This tells the assembler to accept Virtualization instructions. |
| 235 | @samp{-mno-virt} turns off this option. |
| 236 | |
| 237 | @item -mcrc |
| 238 | @itemx -mno-crc |
| 239 | Generate code for the cyclic redundancy check (CRC) Application Specific |
| 240 | Extension. This tells the assembler to accept CRC instructions. |
| 241 | @samp{-mno-crc} turns off this option. |
| 242 | |
| 243 | @item -mginv |
| 244 | @itemx -mno-ginv |
| 245 | Generate code for the Global INValidate (GINV) Application Specific |
| 246 | Extension. This tells the assembler to accept GINV instructions. |
| 247 | @samp{-mno-ginv} turns off this option. |
| 248 | |
| 249 | @item -mloongson-mmi |
| 250 | @itemx -mno-loongson-mmi |
| 251 | Generate code for the Loongson MultiMedia extensions Instructions (MMI) |
| 252 | Application Specific Extension. This tells the assembler to accept MMI |
| 253 | instructions. |
| 254 | @samp{-mno-loongson-mmi} turns off this option. |
| 255 | |
| 256 | @item -mloongson-cam |
| 257 | @itemx -mno-loongson-cam |
| 258 | Generate code for the Loongson Content Address Memory (CAM) |
| 259 | Application Specific Extension. This tells the assembler to accept CAM |
| 260 | instructions. |
| 261 | @samp{-mno-loongson-cam} turns off this option. |
| 262 | |
| 263 | @item -mloongson-ext |
| 264 | @itemx -mno-loongson-ext |
| 265 | Generate code for the Loongson EXTensions (EXT) instructions |
| 266 | Application Specific Extension. This tells the assembler to accept EXT |
| 267 | instructions. |
| 268 | @samp{-mno-loongson-ext} turns off this option. |
| 269 | |
| 270 | @item -mloongson-ext2 |
| 271 | @itemx -mno-loongson-ext2 |
| 272 | Generate code for the Loongson EXTensions R2 (EXT2) instructions |
| 273 | Application Specific Extension. This tells the assembler to accept EXT2 |
| 274 | instructions. |
| 275 | @samp{-mno-loongson-ext2} turns off this option. |
| 276 | |
| 277 | @item -minsn32 |
| 278 | @itemx -mno-insn32 |
| 279 | Only use 32-bit instruction encodings when generating code for the |
| 280 | microMIPS processor. This option inhibits the use of any 16-bit |
| 281 | instructions. This is equivalent to putting @code{.set insn32} at |
| 282 | the start of the assembly file. @samp{-mno-insn32} turns off this |
| 283 | option. This is equivalent to putting @code{.set noinsn32} at the |
| 284 | start of the assembly file. By default @samp{-mno-insn32} is |
| 285 | selected, allowing all instructions to be used. |
| 286 | |
| 287 | @item -mfix7000 |
| 288 | @itemx -mno-fix7000 |
| 289 | Cause nops to be inserted if the read of the destination register |
| 290 | of an mfhi or mflo instruction occurs in the following two instructions. |
| 291 | |
| 292 | @item -mfix-rm7000 |
| 293 | @itemx -mno-fix-rm7000 |
| 294 | Cause nops to be inserted if a dmult or dmultu instruction is |
| 295 | followed by a load instruction. |
| 296 | |
| 297 | @item -mfix-loongson2f-jump |
| 298 | @itemx -mno-fix-loongson2f-jump |
| 299 | Eliminate instruction fetch from outside 256M region to work around the |
| 300 | Loongson2F @samp{jump} instructions. Without it, under extreme cases, |
| 301 | the kernel may crash. The issue has been solved in latest processor |
| 302 | batches, but this fix has no side effect to them. |
| 303 | |
| 304 | @item -mfix-loongson2f-nop |
| 305 | @itemx -mno-fix-loongson2f-nop |
| 306 | Replace nops by @code{or at,at,zero} to work around the Loongson2F |
| 307 | @samp{nop} errata. Without it, under extreme cases, the CPU might |
| 308 | deadlock. The issue has been solved in later Loongson2F batches, but |
| 309 | this fix has no side effect to them. |
| 310 | |
| 311 | @item -mfix-loongson3-llsc |
| 312 | @itemx -mno-fix-loongson3-llsc |
| 313 | Insert @samp{sync} before @samp{ll} and @samp{lld} to work around |
| 314 | Loongson3 LLSC errata. Without it, under extrame cases, the CPU might |
| 315 | deadlock. The default can be controlled by the |
| 316 | @option{--enable-mips-fix-loongson3-llsc=[yes|no]} configure option. |
| 317 | |
| 318 | @item -mfix-vr4120 |
| 319 | @itemx -mno-fix-vr4120 |
| 320 | Insert nops to work around certain VR4120 errata. This option is |
| 321 | intended to be used on GCC-generated code: it is not designed to catch |
| 322 | all problems in hand-written assembler code. |
| 323 | |
| 324 | @item -mfix-vr4130 |
| 325 | @itemx -mno-fix-vr4130 |
| 326 | Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata. |
| 327 | |
| 328 | @item -mfix-24k |
| 329 | @itemx -mno-fix-24k |
| 330 | Insert nops to work around the 24K @samp{eret}/@samp{deret} errata. |
| 331 | |
| 332 | @item -mfix-cn63xxp1 |
| 333 | @itemx -mno-fix-cn63xxp1 |
| 334 | Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around |
| 335 | certain CN63XXP1 errata. |
| 336 | |
| 337 | @item -mfix-r5900 |
| 338 | @itemx -mno-fix-r5900 |
| 339 | Do not attempt to schedule the preceding instruction into the delay slot |
| 340 | of a branch instruction placed at the end of a short loop of six |
| 341 | instructions or fewer and always schedule a @code{nop} instruction there |
| 342 | instead. The short loop bug under certain conditions causes loops to |
| 343 | execute only once or twice, due to a hardware bug in the R5900 chip. |
| 344 | |
| 345 | @item -m4010 |
| 346 | @itemx -no-m4010 |
| 347 | Generate code for the LSI R4010 chip. This tells the assembler to |
| 348 | accept the R4010-specific instructions (@samp{addciu}, @samp{ffc}, |
| 349 | etc.), and to not schedule @samp{nop} instructions around accesses to |
| 350 | the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this |
| 351 | option. |
| 352 | |
| 353 | @item -m4650 |
| 354 | @itemx -no-m4650 |
| 355 | Generate code for the MIPS R4650 chip. This tells the assembler to accept |
| 356 | the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop} |
| 357 | instructions around accesses to the @samp{HI} and @samp{LO} registers. |
| 358 | @samp{-no-m4650} turns off this option. |
| 359 | |
| 360 | @item -m3900 |
| 361 | @itemx -no-m3900 |
| 362 | @itemx -m4100 |
| 363 | @itemx -no-m4100 |
| 364 | For each option @samp{-m@var{nnnn}}, generate code for the MIPS |
| 365 | R@var{nnnn} chip. This tells the assembler to accept instructions |
| 366 | specific to that chip, and to schedule for that chip's hazards. |
| 367 | |
| 368 | @item -march=@var{cpu} |
| 369 | Generate code for a particular MIPS CPU. It is exactly equivalent to |
| 370 | @samp{-m@var{cpu}}, except that there are more value of @var{cpu} |
| 371 | understood. Valid @var{cpu} value are: |
| 372 | |
| 373 | @quotation |
| 374 | 2000, |
| 375 | 3000, |
| 376 | 3900, |
| 377 | 4000, |
| 378 | 4010, |
| 379 | 4100, |
| 380 | 4111, |
| 381 | vr4120, |
| 382 | vr4130, |
| 383 | vr4181, |
| 384 | 4300, |
| 385 | 4400, |
| 386 | 4600, |
| 387 | 4650, |
| 388 | 5000, |
| 389 | rm5200, |
| 390 | rm5230, |
| 391 | rm5231, |
| 392 | rm5261, |
| 393 | rm5721, |
| 394 | vr5400, |
| 395 | vr5500, |
| 396 | 6000, |
| 397 | rm7000, |
| 398 | 8000, |
| 399 | rm9000, |
| 400 | 10000, |
| 401 | 12000, |
| 402 | 14000, |
| 403 | 16000, |
| 404 | 4kc, |
| 405 | 4km, |
| 406 | 4kp, |
| 407 | 4ksc, |
| 408 | 4kec, |
| 409 | 4kem, |
| 410 | 4kep, |
| 411 | 4ksd, |
| 412 | m4k, |
| 413 | m4kp, |
| 414 | m14k, |
| 415 | m14kc, |
| 416 | m14ke, |
| 417 | m14kec, |
| 418 | 24kc, |
| 419 | 24kf2_1, |
| 420 | 24kf, |
| 421 | 24kf1_1, |
| 422 | 24kec, |
| 423 | 24kef2_1, |
| 424 | 24kef, |
| 425 | 24kef1_1, |
| 426 | 34kc, |
| 427 | 34kf2_1, |
| 428 | 34kf, |
| 429 | 34kf1_1, |
| 430 | 34kn, |
| 431 | 74kc, |
| 432 | 74kf2_1, |
| 433 | 74kf, |
| 434 | 74kf1_1, |
| 435 | 74kf3_2, |
| 436 | 1004kc, |
| 437 | 1004kf2_1, |
| 438 | 1004kf, |
| 439 | 1004kf1_1, |
| 440 | interaptiv, |
| 441 | interaptiv-mr2, |
| 442 | m5100, |
| 443 | m5101, |
| 444 | p5600, |
| 445 | 5kc, |
| 446 | 5kf, |
| 447 | 20kc, |
| 448 | 25kf, |
| 449 | sb1, |
| 450 | sb1a, |
| 451 | i6400, |
| 452 | i6500, |
| 453 | p6600, |
| 454 | loongson2e, |
| 455 | loongson2f, |
| 456 | gs464, |
| 457 | gs464e, |
| 458 | gs264e, |
| 459 | octeon, |
| 460 | octeon+, |
| 461 | octeon2, |
| 462 | octeon3, |
| 463 | xlr, |
| 464 | xlp |
| 465 | @end quotation |
| 466 | |
| 467 | For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are |
| 468 | accepted as synonyms for @samp{@var{n}f1_1}. These values are |
| 469 | deprecated. |
| 470 | |
| 471 | @item -mtune=@var{cpu} |
| 472 | Schedule and tune for a particular MIPS CPU. Valid @var{cpu} values are |
| 473 | identical to @samp{-march=@var{cpu}}. |
| 474 | |
| 475 | @item -mabi=@var{abi} |
| 476 | Record which ABI the source code uses. The recognized arguments |
| 477 | are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}. |
| 478 | |
| 479 | @item -msym32 |
| 480 | @itemx -mno-sym32 |
| 481 | @cindex -msym32 |
| 482 | @cindex -mno-sym32 |
| 483 | Equivalent to adding @code{.set sym32} or @code{.set nosym32} to |
| 484 | the beginning of the assembler input. @xref{MIPS Symbol Sizes}. |
| 485 | |
| 486 | @cindex @code{-nocpp} ignored (MIPS) |
| 487 | @item -nocpp |
| 488 | This option is ignored. It is accepted for command-line compatibility with |
| 489 | other assemblers, which use it to turn off C style preprocessing. With |
| 490 | @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the |
| 491 | @sc{gnu} assembler itself never runs the C preprocessor. |
| 492 | |
| 493 | @item -msoft-float |
| 494 | @itemx -mhard-float |
| 495 | Disable or enable floating-point instructions. Note that by default |
| 496 | floating-point instructions are always allowed even with CPU targets |
| 497 | that don't have support for these instructions. |
| 498 | |
| 499 | @item -msingle-float |
| 500 | @itemx -mdouble-float |
| 501 | Disable or enable double-precision floating-point operations. Note |
| 502 | that by default double-precision floating-point operations are always |
| 503 | allowed even with CPU targets that don't have support for these |
| 504 | operations. |
| 505 | |
| 506 | @item --construct-floats |
| 507 | @itemx --no-construct-floats |
| 508 | The @code{--no-construct-floats} option disables the construction of |
| 509 | double width floating point constants by loading the two halves of the |
| 510 | value into the two single width floating point registers that make up |
| 511 | the double width register. This feature is useful if the processor |
| 512 | support the FR bit in its status register, and this bit is known (by |
| 513 | the programmer) to be set. This bit prevents the aliasing of the double |
| 514 | width register by the single width registers. |
| 515 | |
| 516 | By default @code{--construct-floats} is selected, allowing construction |
| 517 | of these floating point constants. |
| 518 | |
| 519 | @item --relax-branch |
| 520 | @itemx --no-relax-branch |
| 521 | The @samp{--relax-branch} option enables the relaxation of out-of-range |
| 522 | branches. Any branches whose target cannot be reached directly are |
| 523 | converted to a small instruction sequence including an inverse-condition |
| 524 | branch to the physically next instruction, and a jump to the original |
| 525 | target is inserted between the two instructions. In PIC code the jump |
| 526 | will involve further instructions for address calculation. |
| 527 | |
| 528 | The @code{BC1ANY2F}, @code{BC1ANY2T}, @code{BC1ANY4F}, @code{BC1ANY4T}, |
| 529 | @code{BPOSGE32} and @code{BPOSGE64} instructions are excluded from |
| 530 | relaxation, because they have no complementing counterparts. They could |
| 531 | be relaxed with the use of a longer sequence involving another branch, |
| 532 | however this has not been implemented and if their target turns out of |
| 533 | reach, they produce an error even if branch relaxation is enabled. |
| 534 | |
| 535 | Also no MIPS16 branches are ever relaxed. |
| 536 | |
| 537 | By default @samp{--no-relax-branch} is selected, causing any out-of-range |
| 538 | branches to produce an error. |
| 539 | |
| 540 | @item -mignore-branch-isa |
| 541 | @itemx -mno-ignore-branch-isa |
| 542 | Ignore branch checks for invalid transitions between ISA modes. |
| 543 | |
| 544 | The semantics of branches does not provide for an ISA mode switch, so in |
| 545 | most cases the ISA mode a branch has been encoded for has to be the same |
| 546 | as the ISA mode of the branch's target label. If the ISA modes do not |
| 547 | match, then such a branch, if taken, will cause the ISA mode to remain |
| 548 | unchanged and instructions that follow will be executed in the wrong ISA |
| 549 | mode causing the program to misbehave or crash. |
| 550 | |
| 551 | In the case of the @code{BAL} instruction it may be possible to relax |
| 552 | it to an equivalent @code{JALX} instruction so that the ISA mode is |
| 553 | switched at the run time as required. For other branches no relaxation |
| 554 | is possible and therefore GAS has checks implemented that verify in |
| 555 | branch assembly that the two ISA modes match, and report an error |
| 556 | otherwise so that the problem with code can be diagnosed at the assembly |
| 557 | time rather than at the run time. |
| 558 | |
| 559 | However some assembly code, including generated code produced by some |
| 560 | versions of GCC, may incorrectly include branches to data labels, which |
| 561 | appear to require a mode switch but are either dead or immediately |
| 562 | followed by valid instructions encoded for the same ISA the branch has |
| 563 | been encoded for. While not strictly correct at the source level such |
| 564 | code will execute as intended, so to help with these cases |
| 565 | @samp{-mignore-branch-isa} is supported which disables ISA mode checks |
| 566 | for branches. |
| 567 | |
| 568 | By default @samp{-mno-ignore-branch-isa} is selected, causing any invalid |
| 569 | branch requiring a transition between ISA modes to produce an error. |
| 570 | |
| 571 | @cindex @option{-mnan=} command-line option, MIPS |
| 572 | @item -mnan=@var{encoding} |
| 573 | This option indicates whether the source code uses the IEEE 2008 |
| 574 | NaN encoding (@option{-mnan=2008}) or the original MIPS encoding |
| 575 | (@option{-mnan=legacy}). It is equivalent to adding a @code{.nan} |
| 576 | directive to the beginning of the source file. @xref{MIPS NaN Encodings}. |
| 577 | |
| 578 | @option{-mnan=legacy} is the default if no @option{-mnan} option or |
| 579 | @code{.nan} directive is used. |
| 580 | |
| 581 | @item --trap |
| 582 | @itemx --no-break |
| 583 | @c FIXME! (1) reflect these options (next item too) in option summaries; |
| 584 | @c (2) stop teasing, say _which_ instructions expanded _how_. |
| 585 | @code{@value{AS}} automatically macro expands certain division and |
| 586 | multiplication instructions to check for overflow and division by zero. This |
| 587 | option causes @code{@value{AS}} to generate code to take a trap exception |
| 588 | rather than a break exception when an error is detected. The trap instructions |
| 589 | are only supported at Instruction Set Architecture level 2 and higher. |
| 590 | |
| 591 | @item --break |
| 592 | @itemx --no-trap |
| 593 | Generate code to take a break exception rather than a trap exception when an |
| 594 | error is detected. This is the default. |
| 595 | |
| 596 | @item -mpdr |
| 597 | @itemx -mno-pdr |
| 598 | Control generation of @code{.pdr} sections. Off by default on IRIX, on |
| 599 | elsewhere. |
| 600 | |
| 601 | @item -mshared |
| 602 | @itemx -mno-shared |
| 603 | When generating code using the Unix calling conventions (selected by |
| 604 | @samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code |
| 605 | which can go into a shared library. The @samp{-mno-shared} option |
| 606 | tells gas to generate code which uses the calling convention, but can |
| 607 | not go into a shared library. The resulting code is slightly more |
| 608 | efficient. This option only affects the handling of the |
| 609 | @samp{.cpload} and @samp{.cpsetup} pseudo-ops. |
| 610 | @end table |
| 611 | |
| 612 | @node MIPS Macros |
| 613 | @section High-level assembly macros |
| 614 | |
| 615 | MIPS assemblers have traditionally provided a wider range of |
| 616 | instructions than the MIPS architecture itself. These extra |
| 617 | instructions are usually referred to as ``macro'' instructions |
| 618 | @footnote{The term ``macro'' is somewhat overloaded here, since |
| 619 | these macros have no relation to those defined by @code{.macro}, |
| 620 | @pxref{Macro,, @code{.macro}}.}. |
| 621 | |
| 622 | Some MIPS macro instructions extend an underlying architectural instruction |
| 623 | while others are entirely new. An example of the former type is @code{and}, |
| 624 | which allows the third operand to be either a register or an arbitrary |
| 625 | immediate value. Examples of the latter type include @code{bgt}, which |
| 626 | branches to the third operand when the first operand is greater than |
| 627 | the second operand, and @code{ulh}, which implements an unaligned |
| 628 | 2-byte load. |
| 629 | |
| 630 | One of the most common extensions provided by macros is to expand |
| 631 | memory offsets to the full address range (32 or 64 bits) and to allow |
| 632 | symbolic offsets such as @samp{my_data + 4} to be used in place of |
| 633 | integer constants. For example, the architectural instruction |
| 634 | @code{lbu} allows only a signed 16-bit offset, whereas the macro |
| 635 | @code{lbu} allows code such as @samp{lbu $4,array+32769($5)}. |
| 636 | The implementation of these symbolic offsets depends on several factors, |
| 637 | such as whether the assembler is generating SVR4-style PIC (selected by |
| 638 | @option{-KPIC}, @pxref{MIPS Options,, Assembler options}), the size of symbols |
| 639 | (@pxref{MIPS Symbol Sizes,, Directives to override the size of symbols}), |
| 640 | and the small data limit (@pxref{MIPS Small Data,, Controlling the use |
| 641 | of small data accesses}). |
| 642 | |
| 643 | @kindex @code{.set macro} |
| 644 | @kindex @code{.set nomacro} |
| 645 | Sometimes it is undesirable to have one assembly instruction expand |
| 646 | to several machine instructions. The directive @code{.set nomacro} |
| 647 | tells the assembler to warn when this happens. @code{.set macro} |
| 648 | restores the default behavior. |
| 649 | |
| 650 | @cindex @code{at} register, MIPS |
| 651 | @kindex @code{.set at=@var{reg}} |
| 652 | Some macro instructions need a temporary register to store intermediate |
| 653 | results. This register is usually @code{$1}, also known as @code{$at}, |
| 654 | but it can be changed to any core register @var{reg} using |
| 655 | @code{.set at=@var{reg}}. Note that @code{$at} always refers |
| 656 | to @code{$1} regardless of which register is being used as the |
| 657 | temporary register. |
| 658 | |
| 659 | @kindex @code{.set at} |
| 660 | @kindex @code{.set noat} |
| 661 | Implicit uses of the temporary register in macros could interfere with |
| 662 | explicit uses in the assembly code. The assembler therefore warns |
| 663 | whenever it sees an explicit use of the temporary register. The directive |
| 664 | @code{.set noat} silences this warning while @code{.set at} restores |
| 665 | the default behavior. It is safe to use @code{.set noat} while |
| 666 | @code{.set nomacro} is in effect since single-instruction macros |
| 667 | never need a temporary register. |
| 668 | |
| 669 | Note that while the @sc{gnu} assembler provides these macros for compatibility, |
| 670 | it does not make any attempt to optimize them with the surrounding code. |
| 671 | |
| 672 | @node MIPS Symbol Sizes |
| 673 | @section Directives to override the size of symbols |
| 674 | |
| 675 | @kindex @code{.set sym32} |
| 676 | @kindex @code{.set nosym32} |
| 677 | The n64 ABI allows symbols to have any 64-bit value. Although this |
| 678 | provides a great deal of flexibility, it means that some macros have |
| 679 | much longer expansions than their 32-bit counterparts. For example, |
| 680 | the non-PIC expansion of @samp{dla $4,sym} is usually: |
| 681 | |
| 682 | @smallexample |
| 683 | lui $4,%highest(sym) |
| 684 | lui $1,%hi(sym) |
| 685 | daddiu $4,$4,%higher(sym) |
| 686 | daddiu $1,$1,%lo(sym) |
| 687 | dsll32 $4,$4,0 |
| 688 | daddu $4,$4,$1 |
| 689 | @end smallexample |
| 690 | |
| 691 | whereas the 32-bit expansion is simply: |
| 692 | |
| 693 | @smallexample |
| 694 | lui $4,%hi(sym) |
| 695 | daddiu $4,$4,%lo(sym) |
| 696 | @end smallexample |
| 697 | |
| 698 | n64 code is sometimes constructed in such a way that all symbolic |
| 699 | constants are known to have 32-bit values, and in such cases, it's |
| 700 | preferable to use the 32-bit expansion instead of the 64-bit |
| 701 | expansion. |
| 702 | |
| 703 | You can use the @code{.set sym32} directive to tell the assembler |
| 704 | that, from this point on, all expressions of the form |
| 705 | @samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}} |
| 706 | have 32-bit values. For example: |
| 707 | |
| 708 | @smallexample |
| 709 | .set sym32 |
| 710 | dla $4,sym |
| 711 | lw $4,sym+16 |
| 712 | sw $4,sym+0x8000($4) |
| 713 | @end smallexample |
| 714 | |
| 715 | will cause the assembler to treat @samp{sym}, @code{sym+16} and |
| 716 | @code{sym+0x8000} as 32-bit values. The handling of non-symbolic |
| 717 | addresses is not affected. |
| 718 | |
| 719 | The directive @code{.set nosym32} ends a @code{.set sym32} block and |
| 720 | reverts to the normal behavior. It is also possible to change the |
| 721 | symbol size using the command-line options @option{-msym32} and |
| 722 | @option{-mno-sym32}. |
| 723 | |
| 724 | These options and directives are always accepted, but at present, |
| 725 | they have no effect for anything other than n64. |
| 726 | |
| 727 | @node MIPS Small Data |
| 728 | @section Controlling the use of small data accesses |
| 729 | |
| 730 | @c This section deliberately glosses over the possibility of using -G |
| 731 | @c in SVR4-style PIC, as could be done on IRIX. We don't support that. |
| 732 | @cindex small data, MIPS |
| 733 | @cindex @code{gp} register, MIPS |
| 734 | It often takes several instructions to load the address of a symbol. |
| 735 | For example, when @samp{addr} is a 32-bit symbol, the non-PIC expansion |
| 736 | of @samp{dla $4,addr} is usually: |
| 737 | |
| 738 | @smallexample |
| 739 | lui $4,%hi(addr) |
| 740 | daddiu $4,$4,%lo(addr) |
| 741 | @end smallexample |
| 742 | |
| 743 | The sequence is much longer when @samp{addr} is a 64-bit symbol. |
| 744 | @xref{MIPS Symbol Sizes,, Directives to override the size of symbols}. |
| 745 | |
| 746 | In order to cut down on this overhead, most embedded MIPS systems |
| 747 | set aside a 64-kilobyte ``small data'' area and guarantee that all |
| 748 | data of size @var{n} and smaller will be placed in that area. |
| 749 | The limit @var{n} is passed to both the assembler and the linker |
| 750 | using the command-line option @option{-G @var{n}}, @pxref{MIPS Options,, |
| 751 | Assembler options}. Note that the same value of @var{n} must be used |
| 752 | when linking and when assembling all input files to the link; any |
| 753 | inconsistency could cause a relocation overflow error. |
| 754 | |
| 755 | The size of an object in the @code{.bss} section is set by the |
| 756 | @code{.comm} or @code{.lcomm} directive that defines it. The size of |
| 757 | an external object may be set with the @code{.extern} directive. For |
| 758 | example, @samp{.extern sym,4} declares that the object at @code{sym} |
| 759 | is 4 bytes in length, while leaving @code{sym} otherwise undefined. |
| 760 | |
| 761 | When no @option{-G} option is given, the default limit is 8 bytes. |
| 762 | The option @option{-G 0} prevents any data from being automatically |
| 763 | classified as small. |
| 764 | |
| 765 | It is also possible to mark specific objects as small by putting them |
| 766 | in the special sections @code{.sdata} and @code{.sbss}, which are |
| 767 | ``small'' counterparts of @code{.data} and @code{.bss} respectively. |
| 768 | The toolchain will treat such data as small regardless of the |
| 769 | @option{-G} setting. |
| 770 | |
| 771 | On startup, systems that support a small data area are expected to |
| 772 | initialize register @code{$28}, also known as @code{$gp}, in such a |
| 773 | way that small data can be accessed using a 16-bit offset from that |
| 774 | register. For example, when @samp{addr} is small data, |
| 775 | the @samp{dla $4,addr} instruction above is equivalent to: |
| 776 | |
| 777 | @smallexample |
| 778 | daddiu $4,$28,%gp_rel(addr) |
| 779 | @end smallexample |
| 780 | |
| 781 | Small data is not supported for SVR4-style PIC. |
| 782 | |
| 783 | @node MIPS ISA |
| 784 | @section Directives to override the ISA level |
| 785 | |
| 786 | @cindex MIPS ISA override |
| 787 | @kindex @code{.set mips@var{n}} |
| 788 | @sc{gnu} @code{@value{AS}} supports an additional directive to change |
| 789 | the MIPS Instruction Set Architecture level on the fly: @code{.set |
| 790 | mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 32r3, |
| 791 | 32r5, 32r6, 64, 64r2, 64r3, 64r5 or 64r6. |
| 792 | The values other than 0 make the assembler accept instructions |
| 793 | for the corresponding ISA level, from that point on in the |
| 794 | assembly. @code{.set mips@var{n}} affects not only which instructions |
| 795 | are permitted, but also how certain macros are expanded. @code{.set |
| 796 | mips0} restores the ISA level to its original level: either the |
| 797 | level you selected with command-line options, or the default for your |
| 798 | configuration. You can use this feature to permit specific MIPS III |
| 799 | instructions while assembling in 32 bit mode. Use this directive with |
| 800 | care! |
| 801 | |
| 802 | @cindex MIPS CPU override |
| 803 | @kindex @code{.set arch=@var{cpu}} |
| 804 | The @code{.set arch=@var{cpu}} directive provides even finer control. |
| 805 | It changes the effective CPU target and allows the assembler to use |
| 806 | instructions specific to a particular CPU. All CPUs supported by the |
| 807 | @samp{-march} command-line option are also selectable by this directive. |
| 808 | The original value is restored by @code{.set arch=default}. |
| 809 | |
| 810 | The directive @code{.set mips16} puts the assembler into MIPS 16 mode, |
| 811 | in which it will assemble instructions for the MIPS 16 processor. Use |
| 812 | @code{.set nomips16} to return to normal 32 bit mode. |
| 813 | |
| 814 | Traditional MIPS assemblers do not support this directive. |
| 815 | |
| 816 | The directive @code{.set micromips} puts the assembler into microMIPS mode, |
| 817 | in which it will assemble instructions for the microMIPS processor. Use |
| 818 | @code{.set nomicromips} to return to normal 32 bit mode. |
| 819 | |
| 820 | Traditional MIPS assemblers do not support this directive. |
| 821 | |
| 822 | @node MIPS assembly options |
| 823 | @section Directives to control code generation |
| 824 | |
| 825 | @cindex MIPS directives to override command-line options |
| 826 | @kindex @code{.module} |
| 827 | The @code{.module} directive allows command-line options to be set directly |
| 828 | from assembly. The format of the directive matches the @code{.set} |
| 829 | directive but only those options which are relevant to a whole module are |
| 830 | supported. The effect of a @code{.module} directive is the same as the |
| 831 | corresponding command-line option. Where @code{.set} directives support |
| 832 | returning to a default then the @code{.module} directives do not as they |
| 833 | define the defaults. |
| 834 | |
| 835 | These module-level directives must appear first in assembly. |
| 836 | |
| 837 | Traditional MIPS assemblers do not support this directive. |
| 838 | |
| 839 | @cindex MIPS 32-bit microMIPS instruction generation override |
| 840 | @kindex @code{.set insn32} |
| 841 | @kindex @code{.set noinsn32} |
| 842 | The directive @code{.set insn32} makes the assembler only use 32-bit |
| 843 | instruction encodings when generating code for the microMIPS processor. |
| 844 | This directive inhibits the use of any 16-bit instructions from that |
| 845 | point on in the assembly. The @code{.set noinsn32} directive allows |
| 846 | 16-bit instructions to be accepted. |
| 847 | |
| 848 | Traditional MIPS assemblers do not support this directive. |
| 849 | |
| 850 | @node MIPS autoextend |
| 851 | @section Directives for extending MIPS 16 bit instructions |
| 852 | |
| 853 | @kindex @code{.set autoextend} |
| 854 | @kindex @code{.set noautoextend} |
| 855 | By default, MIPS 16 instructions are automatically extended to 32 bits |
| 856 | when necessary. The directive @code{.set noautoextend} will turn this |
| 857 | off. When @code{.set noautoextend} is in effect, any 32 bit instruction |
| 858 | must be explicitly extended with the @code{.e} modifier (e.g., |
| 859 | @code{li.e $4,1000}). The directive @code{.set autoextend} may be used |
| 860 | to once again automatically extend instructions when necessary. |
| 861 | |
| 862 | This directive is only meaningful when in MIPS 16 mode. Traditional |
| 863 | MIPS assemblers do not support this directive. |
| 864 | |
| 865 | @node MIPS insn |
| 866 | @section Directive to mark data as an instruction |
| 867 | |
| 868 | @kindex @code{.insn} |
| 869 | The @code{.insn} directive tells @code{@value{AS}} that the following |
| 870 | data is actually instructions. This makes a difference in MIPS 16 and |
| 871 | microMIPS modes: when loading the address of a label which precedes |
| 872 | instructions, @code{@value{AS}} automatically adds 1 to the value, so |
| 873 | that jumping to the loaded address will do the right thing. |
| 874 | |
| 875 | @kindex @code{.global} |
| 876 | The @code{.global} and @code{.globl} directives supported by |
| 877 | @code{@value{AS}} will by default mark the symbol as pointing to a |
| 878 | region of data not code. This means that, for example, any |
| 879 | instructions following such a symbol will not be disassembled by |
| 880 | @code{objdump} as it will regard them as data. To change this |
| 881 | behavior an optional section name can be placed after the symbol name |
| 882 | in the @code{.global} directive. If this section exists and is known |
| 883 | to be a code section, then the symbol will be marked as pointing at |
| 884 | code not data. Ie the syntax for the directive is: |
| 885 | |
| 886 | @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...}, |
| 887 | |
| 888 | Here is a short example: |
| 889 | |
| 890 | @example |
| 891 | .global foo .text, bar, baz .data |
| 892 | foo: |
| 893 | nop |
| 894 | bar: |
| 895 | .word 0x0 |
| 896 | baz: |
| 897 | .word 0x1 |
| 898 | |
| 899 | @end example |
| 900 | |
| 901 | @node MIPS FP ABIs |
| 902 | @section Directives to control the FP ABI |
| 903 | @menu |
| 904 | * MIPS FP ABI History:: History of FP ABIs |
| 905 | * MIPS FP ABI Variants:: Supported FP ABIs |
| 906 | * MIPS FP ABI Selection:: Automatic selection of FP ABI |
| 907 | * MIPS FP ABI Compatibility:: Linking different FP ABI variants |
| 908 | @end menu |
| 909 | |
| 910 | @node MIPS FP ABI History |
| 911 | @subsection History of FP ABIs |
| 912 | @cindex @code{.gnu_attribute 4, @var{n}} directive, MIPS |
| 913 | @cindex @code{.gnu_attribute Tag_GNU_MIPS_ABI_FP, @var{n}} directive, MIPS |
| 914 | The MIPS ABIs support a variety of different floating-point extensions |
| 915 | where calling-convention and register sizes vary for floating-point data. |
| 916 | The extensions exist to support a wide variety of optional architecture |
| 917 | features. The resulting ABI variants are generally incompatible with each |
| 918 | other and must be tracked carefully. |
| 919 | |
| 920 | Traditionally the use of an explicit @code{.gnu_attribute 4, @var{n}} |
| 921 | directive is used to indicate which ABI is in use by a specific module. |
| 922 | It was then left to the user to ensure that command-line options and the |
| 923 | selected ABI were compatible with some potential for inconsistencies. |
| 924 | |
| 925 | @node MIPS FP ABI Variants |
| 926 | @subsection Supported FP ABIs |
| 927 | The supported floating-point ABI variants are: |
| 928 | |
| 929 | @table @code |
| 930 | @item 0 - No floating-point |
| 931 | This variant is used to indicate that floating-point is not used within |
| 932 | the module at all and therefore has no impact on the ABI. This is the |
| 933 | default. |
| 934 | |
| 935 | @item 1 - Double-precision |
| 936 | This variant indicates that double-precision support is used. For 64-bit |
| 937 | ABIs this means that 64-bit wide floating-point registers are required. |
| 938 | For 32-bit ABIs this means that 32-bit wide floating-point registers are |
| 939 | required and double-precision operations use pairs of registers. |
| 940 | |
| 941 | @item 2 - Single-precision |
| 942 | This variant indicates that single-precision support is used. Double |
| 943 | precision operations will be supported via soft-float routines. |
| 944 | |
| 945 | @item 3 - Soft-float |
| 946 | This variant indicates that although floating-point support is used all |
| 947 | operations are emulated in software. This means the ABI is modified to |
| 948 | pass all floating-point data in general-purpose registers. |
| 949 | |
| 950 | @item 4 - Deprecated |
| 951 | This variant existed as an initial attempt at supporting 64-bit wide |
| 952 | floating-point registers for O32 ABI on a MIPS32r2 CPU. This has been |
| 953 | superseded by 5, 6 and 7. |
| 954 | |
| 955 | @item 5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU |
| 956 | This variant is used by 32-bit ABIs to indicate that the floating-point |
| 957 | code in the module has been designed to operate correctly with either |
| 958 | 32-bit wide or 64-bit wide floating-point registers. Double-precision |
| 959 | support is used. Only O32 currently supports this variant and requires |
| 960 | a minimum architecture of MIPS II. |
| 961 | |
| 962 | @item 6 - Double-precision 32-bit FPU, 64-bit FPU |
| 963 | This variant is used by 32-bit ABIs to indicate that the floating-point |
| 964 | code in the module requires 64-bit wide floating-point registers. |
| 965 | Double-precision support is used. Only O32 currently supports this |
| 966 | variant and requires a minimum architecture of MIPS32r2. |
| 967 | |
| 968 | @item 7 - Double-precision compat 32-bit FPU, 64-bit FPU |
| 969 | This variant is used by 32-bit ABIs to indicate that the floating-point |
| 970 | code in the module requires 64-bit wide floating-point registers. |
| 971 | Double-precision support is used. This differs from the previous ABI |
| 972 | as it restricts use of odd-numbered single-precision registers. Only |
| 973 | O32 currently supports this variant and requires a minimum architecture |
| 974 | of MIPS32r2. |
| 975 | @end table |
| 976 | |
| 977 | @node MIPS FP ABI Selection |
| 978 | @subsection Automatic selection of FP ABI |
| 979 | @cindex @code{.module fp=@var{nn}} directive, MIPS |
| 980 | In order to simplify and add safety to the process of selecting the |
| 981 | correct floating-point ABI, the assembler will automatically infer the |
| 982 | correct @code{.gnu_attribute 4, @var{n}} directive based on command-line |
| 983 | options and @code{.module} overrides. Where an explicit |
| 984 | @code{.gnu_attribute 4, @var{n}} directive has been seen then a warning |
| 985 | will be raised if it does not match an inferred setting. |
| 986 | |
| 987 | The floating-point ABI is inferred as follows. If @samp{-msoft-float} |
| 988 | has been used the module will be marked as soft-float. If |
| 989 | @samp{-msingle-float} has been used then the module will be marked as |
| 990 | single-precision. The remaining ABIs are then selected based |
| 991 | on the FP register width. Double-precision is selected if the width |
| 992 | of GP and FP registers match and the special double-precision variants |
| 993 | for 32-bit ABIs are then selected depending on @samp{-mfpxx}, |
| 994 | @samp{-mfp64} and @samp{-mno-odd-spreg}. |
| 995 | |
| 996 | @node MIPS FP ABI Compatibility |
| 997 | @subsection Linking different FP ABI variants |
| 998 | Modules using the default FP ABI (no floating-point) can be linked with |
| 999 | any other (singular) FP ABI variant. |
| 1000 | |
| 1001 | Special compatibility support exists for O32 with the four |
| 1002 | double-precision FP ABI variants. The @samp{-mfpxx} FP ABI is specifically |
| 1003 | designed to be compatible with the standard double-precision ABI and the |
| 1004 | @samp{-mfp64} FP ABIs. This makes it desirable for O32 modules to be |
| 1005 | built as @samp{-mfpxx} to ensure the maximum compatibility with other |
| 1006 | modules produced for more specific needs. The only FP ABIs which cannot |
| 1007 | be linked together are the standard double-precision ABI and the full |
| 1008 | @samp{-mfp64} ABI with @samp{-modd-spreg}. |
| 1009 | |
| 1010 | @node MIPS NaN Encodings |
| 1011 | @section Directives to record which NaN encoding is being used |
| 1012 | |
| 1013 | @cindex MIPS IEEE 754 NaN data encoding selection |
| 1014 | @cindex @code{.nan} directive, MIPS |
| 1015 | The IEEE 754 floating-point standard defines two types of not-a-number |
| 1016 | (NaN) data: ``signalling'' NaNs and ``quiet'' NaNs. The original version |
| 1017 | of the standard did not specify how these two types should be |
| 1018 | distinguished. Most implementations followed the i387 model, in which |
| 1019 | the first bit of the significand is set for quiet NaNs and clear for |
| 1020 | signalling NaNs. However, the original MIPS implementation assigned the |
| 1021 | opposite meaning to the bit, so that it was set for signalling NaNs and |
| 1022 | clear for quiet NaNs. |
| 1023 | |
| 1024 | The 2008 revision of the standard formally suggested the i387 choice |
| 1025 | and as from Sep 2012 the current release of the MIPS architecture |
| 1026 | therefore optionally supports that form. Code that uses one NaN encoding |
| 1027 | would usually be incompatible with code that uses the other NaN encoding, |
| 1028 | so MIPS ELF objects have a flag (@code{EF_MIPS_NAN2008}) to record which |
| 1029 | encoding is being used. |
| 1030 | |
| 1031 | Assembly files can use the @code{.nan} directive to select between the |
| 1032 | two encodings. @samp{.nan 2008} says that the assembly file uses the |
| 1033 | IEEE 754-2008 encoding while @samp{.nan legacy} says that the file uses |
| 1034 | the original MIPS encoding. If several @code{.nan} directives are given, |
| 1035 | the final setting is the one that is used. |
| 1036 | |
| 1037 | The command-line options @option{-mnan=legacy} and @option{-mnan=2008} |
| 1038 | can be used instead of @samp{.nan legacy} and @samp{.nan 2008} |
| 1039 | respectively. However, any @code{.nan} directive overrides the |
| 1040 | command-line setting. |
| 1041 | |
| 1042 | @samp{.nan legacy} is the default if no @code{.nan} directive or |
| 1043 | @option{-mnan} option is given. |
| 1044 | |
| 1045 | Note that @sc{gnu} @code{@value{AS}} does not produce NaNs itself and |
| 1046 | therefore these directives do not affect code generation. They simply |
| 1047 | control the setting of the @code{EF_MIPS_NAN2008} flag. |
| 1048 | |
| 1049 | Traditional MIPS assemblers do not support these directives. |
| 1050 | |
| 1051 | @node MIPS Option Stack |
| 1052 | @section Directives to save and restore options |
| 1053 | |
| 1054 | @cindex MIPS option stack |
| 1055 | @kindex @code{.set push} |
| 1056 | @kindex @code{.set pop} |
| 1057 | The directives @code{.set push} and @code{.set pop} may be used to save |
| 1058 | and restore the current settings for all the options which are |
| 1059 | controlled by @code{.set}. The @code{.set push} directive saves the |
| 1060 | current settings on a stack. The @code{.set pop} directive pops the |
| 1061 | stack and restores the settings. |
| 1062 | |
| 1063 | These directives can be useful inside an macro which must change an |
| 1064 | option such as the ISA level or instruction reordering but does not want |
| 1065 | to change the state of the code which invoked the macro. |
| 1066 | |
| 1067 | Traditional MIPS assemblers do not support these directives. |
| 1068 | |
| 1069 | @node MIPS ASE Instruction Generation Overrides |
| 1070 | @section Directives to control generation of MIPS ASE instructions |
| 1071 | |
| 1072 | @cindex MIPS MIPS-3D instruction generation override |
| 1073 | @kindex @code{.set mips3d} |
| 1074 | @kindex @code{.set nomips3d} |
| 1075 | The directive @code{.set mips3d} makes the assembler accept instructions |
| 1076 | from the MIPS-3D Application Specific Extension from that point on |
| 1077 | in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D |
| 1078 | instructions from being accepted. |
| 1079 | |
| 1080 | @cindex SmartMIPS instruction generation override |
| 1081 | @kindex @code{.set smartmips} |
| 1082 | @kindex @code{.set nosmartmips} |
| 1083 | The directive @code{.set smartmips} makes the assembler accept |
| 1084 | instructions from the SmartMIPS Application Specific Extension to the |
| 1085 | MIPS32 ISA from that point on in the assembly. The |
| 1086 | @code{.set nosmartmips} directive prevents SmartMIPS instructions from |
| 1087 | being accepted. |
| 1088 | |
| 1089 | @cindex MIPS MDMX instruction generation override |
| 1090 | @kindex @code{.set mdmx} |
| 1091 | @kindex @code{.set nomdmx} |
| 1092 | The directive @code{.set mdmx} makes the assembler accept instructions |
| 1093 | from the MDMX Application Specific Extension from that point on |
| 1094 | in the assembly. The @code{.set nomdmx} directive prevents MDMX |
| 1095 | instructions from being accepted. |
| 1096 | |
| 1097 | @cindex MIPS DSP Release 1 instruction generation override |
| 1098 | @kindex @code{.set dsp} |
| 1099 | @kindex @code{.set nodsp} |
| 1100 | The directive @code{.set dsp} makes the assembler accept instructions |
| 1101 | from the DSP Release 1 Application Specific Extension from that point |
| 1102 | on in the assembly. The @code{.set nodsp} directive prevents DSP |
| 1103 | Release 1 instructions from being accepted. |
| 1104 | |
| 1105 | @cindex MIPS DSP Release 2 instruction generation override |
| 1106 | @kindex @code{.set dspr2} |
| 1107 | @kindex @code{.set nodspr2} |
| 1108 | The directive @code{.set dspr2} makes the assembler accept instructions |
| 1109 | from the DSP Release 2 Application Specific Extension from that point |
| 1110 | on in the assembly. This directive implies @code{.set dsp}. The |
| 1111 | @code{.set nodspr2} directive prevents DSP Release 2 instructions from |
| 1112 | being accepted. |
| 1113 | |
| 1114 | @cindex MIPS DSP Release 3 instruction generation override |
| 1115 | @kindex @code{.set dspr3} |
| 1116 | @kindex @code{.set nodspr3} |
| 1117 | The directive @code{.set dspr3} makes the assembler accept instructions |
| 1118 | from the DSP Release 3 Application Specific Extension from that point |
| 1119 | on in the assembly. This directive implies @code{.set dsp} and |
| 1120 | @code{.set dspr2}. The @code{.set nodspr3} directive prevents DSP |
| 1121 | Release 3 instructions from being accepted. |
| 1122 | |
| 1123 | @cindex MIPS MT instruction generation override |
| 1124 | @kindex @code{.set mt} |
| 1125 | @kindex @code{.set nomt} |
| 1126 | The directive @code{.set mt} makes the assembler accept instructions |
| 1127 | from the MT Application Specific Extension from that point on |
| 1128 | in the assembly. The @code{.set nomt} directive prevents MT |
| 1129 | instructions from being accepted. |
| 1130 | |
| 1131 | @cindex MIPS MCU instruction generation override |
| 1132 | @kindex @code{.set mcu} |
| 1133 | @kindex @code{.set nomcu} |
| 1134 | The directive @code{.set mcu} makes the assembler accept instructions |
| 1135 | from the MCU Application Specific Extension from that point on |
| 1136 | in the assembly. The @code{.set nomcu} directive prevents MCU |
| 1137 | instructions from being accepted. |
| 1138 | |
| 1139 | @cindex MIPS SIMD Architecture instruction generation override |
| 1140 | @kindex @code{.set msa} |
| 1141 | @kindex @code{.set nomsa} |
| 1142 | The directive @code{.set msa} makes the assembler accept instructions |
| 1143 | from the MIPS SIMD Architecture Extension from that point on |
| 1144 | in the assembly. The @code{.set nomsa} directive prevents MSA |
| 1145 | instructions from being accepted. |
| 1146 | |
| 1147 | @cindex Virtualization instruction generation override |
| 1148 | @kindex @code{.set virt} |
| 1149 | @kindex @code{.set novirt} |
| 1150 | The directive @code{.set virt} makes the assembler accept instructions |
| 1151 | from the Virtualization Application Specific Extension from that point |
| 1152 | on in the assembly. The @code{.set novirt} directive prevents Virtualization |
| 1153 | instructions from being accepted. |
| 1154 | |
| 1155 | @cindex MIPS eXtended Physical Address (XPA) instruction generation override |
| 1156 | @kindex @code{.set xpa} |
| 1157 | @kindex @code{.set noxpa} |
| 1158 | The directive @code{.set xpa} makes the assembler accept instructions |
| 1159 | from the XPA Extension from that point on in the assembly. The |
| 1160 | @code{.set noxpa} directive prevents XPA instructions from being accepted. |
| 1161 | |
| 1162 | @cindex MIPS16e2 instruction generation override |
| 1163 | @kindex @code{.set mips16e2} |
| 1164 | @kindex @code{.set nomips16e2} |
| 1165 | The directive @code{.set mips16e2} makes the assembler accept instructions |
| 1166 | from the MIPS16e2 Application Specific Extension from that point on in the |
| 1167 | assembly, whenever in MIPS16 mode. The @code{.set nomips16e2} directive |
| 1168 | prevents MIPS16e2 instructions from being accepted, in MIPS16 mode. Neither |
| 1169 | directive affects the state of MIPS16 mode being active itself which has |
| 1170 | separate controls. |
| 1171 | |
| 1172 | @cindex MIPS cyclic redundancy check (CRC) instruction generation override |
| 1173 | @kindex @code{.set crc} |
| 1174 | @kindex @code{.set nocrc} |
| 1175 | The directive @code{.set crc} makes the assembler accept instructions |
| 1176 | from the CRC Extension from that point on in the assembly. The |
| 1177 | @code{.set nocrc} directive prevents CRC instructions from being accepted. |
| 1178 | |
| 1179 | @cindex MIPS Global INValidate (GINV) instruction generation override |
| 1180 | @kindex @code{.set ginv} |
| 1181 | @kindex @code{.set noginv} |
| 1182 | The directive @code{.set ginv} makes the assembler accept instructions |
| 1183 | from the GINV Extension from that point on in the assembly. The |
| 1184 | @code{.set noginv} directive prevents GINV instructions from being accepted. |
| 1185 | |
| 1186 | @cindex Loongson MultiMedia extensions Instructions (MMI) generation override |
| 1187 | @kindex @code{.set loongson-mmi} |
| 1188 | @kindex @code{.set noloongson-mmi} |
| 1189 | The directive @code{.set loongson-mmi} makes the assembler accept |
| 1190 | instructions from the MMI Extension from that point on in the assembly. |
| 1191 | The @code{.set noloongson-mmi} directive prevents MMI instructions from |
| 1192 | being accepted. |
| 1193 | |
| 1194 | @cindex Loongson Content Address Memory (CAM) generation override |
| 1195 | @kindex @code{.set loongson-cam} |
| 1196 | @kindex @code{.set noloongson-cam} |
| 1197 | The directive @code{.set loongson-cam} makes the assembler accept |
| 1198 | instructions from the Loongson CAM from that point on in the assembly. |
| 1199 | The @code{.set noloongson-cam} directive prevents Loongson CAM instructions |
| 1200 | from being accepted. |
| 1201 | |
| 1202 | @cindex Loongson EXTensions (EXT) instructions generation override |
| 1203 | @kindex @code{.set loongson-ext} |
| 1204 | @kindex @code{.set noloongson-ext} |
| 1205 | The directive @code{.set loongson-ext} makes the assembler accept |
| 1206 | instructions from the Loongson EXT from that point on in the assembly. |
| 1207 | The @code{.set noloongson-ext} directive prevents Loongson EXT instructions |
| 1208 | from being accepted. |
| 1209 | |
| 1210 | @cindex Loongson EXTensions R2 (EXT2) instructions generation override |
| 1211 | @kindex @code{.set loongson-ext2} |
| 1212 | @kindex @code{.set noloongson-ext2} |
| 1213 | The directive @code{.set loongson-ext2} makes the assembler accept |
| 1214 | instructions from the Loongson EXT2 from that point on in the assembly. |
| 1215 | This directive implies @code{.set loognson-ext}. |
| 1216 | The @code{.set noloongson-ext2} directive prevents Loongson EXT2 instructions |
| 1217 | from being accepted. |
| 1218 | |
| 1219 | Traditional MIPS assemblers do not support these directives. |
| 1220 | |
| 1221 | @node MIPS Floating-Point |
| 1222 | @section Directives to override floating-point options |
| 1223 | |
| 1224 | @cindex Disable floating-point instructions |
| 1225 | @kindex @code{.set softfloat} |
| 1226 | @kindex @code{.set hardfloat} |
| 1227 | The directives @code{.set softfloat} and @code{.set hardfloat} provide |
| 1228 | finer control of disabling and enabling float-point instructions. |
| 1229 | These directives always override the default (that hard-float |
| 1230 | instructions are accepted) or the command-line options |
| 1231 | (@samp{-msoft-float} and @samp{-mhard-float}). |
| 1232 | |
| 1233 | @cindex Disable single-precision floating-point operations |
| 1234 | @kindex @code{.set singlefloat} |
| 1235 | @kindex @code{.set doublefloat} |
| 1236 | The directives @code{.set singlefloat} and @code{.set doublefloat} |
| 1237 | provide finer control of disabling and enabling double-precision |
| 1238 | float-point operations. These directives always override the default |
| 1239 | (that double-precision operations are accepted) or the command-line |
| 1240 | options (@samp{-msingle-float} and @samp{-mdouble-float}). |
| 1241 | |
| 1242 | Traditional MIPS assemblers do not support these directives. |
| 1243 | |
| 1244 | @node MIPS Syntax |
| 1245 | @section Syntactical considerations for the MIPS assembler |
| 1246 | @menu |
| 1247 | * MIPS-Chars:: Special Characters |
| 1248 | @end menu |
| 1249 | |
| 1250 | @node MIPS-Chars |
| 1251 | @subsection Special Characters |
| 1252 | |
| 1253 | @cindex line comment character, MIPS |
| 1254 | @cindex MIPS line comment character |
| 1255 | The presence of a @samp{#} on a line indicates the start of a comment |
| 1256 | that extends to the end of the current line. |
| 1257 | |
| 1258 | If a @samp{#} appears as the first character of a line, the whole line |
| 1259 | is treated as a comment, but in this case the line can also be a |
| 1260 | logical line number directive (@pxref{Comments}) or a |
| 1261 | preprocessor control command (@pxref{Preprocessing}). |
| 1262 | |
| 1263 | @cindex line separator, MIPS |
| 1264 | @cindex statement separator, MIPS |
| 1265 | @cindex MIPS line separator |
| 1266 | The @samp{;} character can be used to separate statements on the same |
| 1267 | line. |