| 1 | @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001, |
| 2 | @c 2002, 2003, 2004 |
| 3 | @c Free Software Foundation, Inc. |
| 4 | @c This is part of the GAS manual. |
| 5 | @c For copying conditions, see the file as.texinfo. |
| 6 | @ifset GENERIC |
| 7 | @page |
| 8 | @node MIPS-Dependent |
| 9 | @chapter MIPS Dependent Features |
| 10 | @end ifset |
| 11 | @ifclear GENERIC |
| 12 | @node Machine Dependencies |
| 13 | @chapter MIPS Dependent Features |
| 14 | @end ifclear |
| 15 | |
| 16 | @cindex MIPS processor |
| 17 | @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several |
| 18 | different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32, |
| 19 | and MIPS64. For information about the @sc{mips} instruction set, see |
| 20 | @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall). |
| 21 | For an overview of @sc{mips} assembly conventions, see ``Appendix D: |
| 22 | Assembly Language Programming'' in the same work. |
| 23 | |
| 24 | @menu |
| 25 | * MIPS Opts:: Assembler options |
| 26 | * MIPS Object:: ECOFF object code |
| 27 | * MIPS Stabs:: Directives for debugging information |
| 28 | * MIPS ISA:: Directives to override the ISA level |
| 29 | * MIPS symbol sizes:: Directives to override the size of symbols |
| 30 | * MIPS autoextend:: Directives for extending MIPS 16 bit instructions |
| 31 | * MIPS insn:: Directive to mark data as an instruction |
| 32 | * MIPS option stack:: Directives to save and restore options |
| 33 | * MIPS ASE instruction generation overrides:: Directives to control |
| 34 | generation of MIPS ASE instructions |
| 35 | @end menu |
| 36 | |
| 37 | @node MIPS Opts |
| 38 | @section Assembler options |
| 39 | |
| 40 | The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these |
| 41 | special options: |
| 42 | |
| 43 | @table @code |
| 44 | @cindex @code{-G} option (MIPS) |
| 45 | @item -G @var{num} |
| 46 | This option sets the largest size of an object that can be referenced |
| 47 | implicitly with the @code{gp} register. It is only accepted for targets |
| 48 | that use @sc{ecoff} format. The default value is 8. |
| 49 | |
| 50 | @cindex @code{-EB} option (MIPS) |
| 51 | @cindex @code{-EL} option (MIPS) |
| 52 | @cindex MIPS big-endian output |
| 53 | @cindex MIPS little-endian output |
| 54 | @cindex big-endian output, MIPS |
| 55 | @cindex little-endian output, MIPS |
| 56 | @item -EB |
| 57 | @itemx -EL |
| 58 | Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or |
| 59 | little-endian output at run time (unlike the other @sc{gnu} development |
| 60 | tools, which must be configured for one or the other). Use @samp{-EB} |
| 61 | to select big-endian output, and @samp{-EL} for little-endian. |
| 62 | |
| 63 | @cindex MIPS architecture options |
| 64 | @item -mips1 |
| 65 | @itemx -mips2 |
| 66 | @itemx -mips3 |
| 67 | @itemx -mips4 |
| 68 | @itemx -mips5 |
| 69 | @itemx -mips32 |
| 70 | @itemx -mips32r2 |
| 71 | @itemx -mips64 |
| 72 | @itemx -mips64r2 |
| 73 | Generate code for a particular MIPS Instruction Set Architecture level. |
| 74 | @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors, |
| 75 | @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the |
| 76 | @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and |
| 77 | @sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, |
| 78 | @samp{-mips64}, and @samp{-mips64r2} |
| 79 | correspond to generic |
| 80 | @sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64}, |
| 81 | and @sc{MIPS64 Release 2} |
| 82 | ISA processors, respectively. You can also switch |
| 83 | instruction sets during the assembly; see @ref{MIPS ISA, Directives to |
| 84 | override the ISA level}. |
| 85 | |
| 86 | @item -mgp32 |
| 87 | @itemx -mfp32 |
| 88 | Some macros have different expansions for 32-bit and 64-bit registers. |
| 89 | The register sizes are normally inferred from the ISA and ABI, but these |
| 90 | flags force a certain group of registers to be treated as 32 bits wide at |
| 91 | all times. @samp{-mgp32} controls the size of general-purpose registers |
| 92 | and @samp{-mfp32} controls the size of floating-point registers. |
| 93 | |
| 94 | On some MIPS variants there is a 32-bit mode flag; when this flag is |
| 95 | set, 64-bit instructions generate a trap. Also, some 32-bit OSes only |
| 96 | save the 32-bit registers on a context switch, so it is essential never |
| 97 | to use the 64-bit registers. |
| 98 | |
| 99 | @item -mgp64 |
| 100 | Assume that 64-bit general purpose registers are available. This is |
| 101 | provided in the interests of symmetry with -gp32. |
| 102 | |
| 103 | @item -mips16 |
| 104 | @itemx -no-mips16 |
| 105 | Generate code for the MIPS 16 processor. This is equivalent to putting |
| 106 | @samp{.set mips16} at the start of the assembly file. @samp{-no-mips16} |
| 107 | turns off this option. |
| 108 | |
| 109 | @item -msmartmips |
| 110 | @itemx -mno-smartmips |
| 111 | Enables the SmartMIPS extensions to the MIPS32 instruction set, which |
| 112 | provides a number of new instructions which target smartcard and |
| 113 | cryptographic applications. This is equivalent to putting |
| 114 | @samp{.set smartmips} at the start of the assembly file. |
| 115 | @samp{-mno-smartmips} turns off this option. |
| 116 | |
| 117 | @item -mips3d |
| 118 | @itemx -no-mips3d |
| 119 | Generate code for the MIPS-3D Application Specific Extension. |
| 120 | This tells the assembler to accept MIPS-3D instructions. |
| 121 | @samp{-no-mips3d} turns off this option. |
| 122 | |
| 123 | @item -mdmx |
| 124 | @itemx -no-mdmx |
| 125 | Generate code for the MDMX Application Specific Extension. |
| 126 | This tells the assembler to accept MDMX instructions. |
| 127 | @samp{-no-mdmx} turns off this option. |
| 128 | |
| 129 | @item -mdsp |
| 130 | @itemx -mno-dsp |
| 131 | Generate code for the DSP Application Specific Extension. |
| 132 | This tells the assembler to accept DSP instructions. |
| 133 | @samp{-mno-dsp} turns off this option. |
| 134 | |
| 135 | @item -mmt |
| 136 | @itemx -mno-mt |
| 137 | Generate code for the MT Application Specific Extension. |
| 138 | This tells the assembler to accept MT instructions. |
| 139 | @samp{-mno-mt} turns off this option. |
| 140 | |
| 141 | @item -mfix7000 |
| 142 | @itemx -mno-fix7000 |
| 143 | Cause nops to be inserted if the read of the destination register |
| 144 | of an mfhi or mflo instruction occurs in the following two instructions. |
| 145 | |
| 146 | @item -mfix-vr4120 |
| 147 | @itemx -no-mfix-vr4120 |
| 148 | Insert nops to work around certain VR4120 errata. This option is |
| 149 | intended to be used on GCC-generated code: it is not designed to catch |
| 150 | all problems in hand-written assembler code. |
| 151 | |
| 152 | @item -mfix-vr4130 |
| 153 | @itemx -no-mfix-vr4130 |
| 154 | Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata. |
| 155 | |
| 156 | @item -m4010 |
| 157 | @itemx -no-m4010 |
| 158 | Generate code for the LSI @sc{r4010} chip. This tells the assembler to |
| 159 | accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc}, |
| 160 | etc.), and to not schedule @samp{nop} instructions around accesses to |
| 161 | the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this |
| 162 | option. |
| 163 | |
| 164 | @item -m4650 |
| 165 | @itemx -no-m4650 |
| 166 | Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept |
| 167 | the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop} |
| 168 | instructions around accesses to the @samp{HI} and @samp{LO} registers. |
| 169 | @samp{-no-m4650} turns off this option. |
| 170 | |
| 171 | @itemx -m3900 |
| 172 | @itemx -no-m3900 |
| 173 | @itemx -m4100 |
| 174 | @itemx -no-m4100 |
| 175 | For each option @samp{-m@var{nnnn}}, generate code for the MIPS |
| 176 | @sc{r@var{nnnn}} chip. This tells the assembler to accept instructions |
| 177 | specific to that chip, and to schedule for that chip's hazards. |
| 178 | |
| 179 | @item -march=@var{cpu} |
| 180 | Generate code for a particular MIPS cpu. It is exactly equivalent to |
| 181 | @samp{-m@var{cpu}}, except that there are more value of @var{cpu} |
| 182 | understood. Valid @var{cpu} value are: |
| 183 | |
| 184 | @quotation |
| 185 | 2000, |
| 186 | 3000, |
| 187 | 3900, |
| 188 | 4000, |
| 189 | 4010, |
| 190 | 4100, |
| 191 | 4111, |
| 192 | vr4120, |
| 193 | vr4130, |
| 194 | vr4181, |
| 195 | 4300, |
| 196 | 4400, |
| 197 | 4600, |
| 198 | 4650, |
| 199 | 5000, |
| 200 | rm5200, |
| 201 | rm5230, |
| 202 | rm5231, |
| 203 | rm5261, |
| 204 | rm5721, |
| 205 | vr5400, |
| 206 | vr5500, |
| 207 | 6000, |
| 208 | rm7000, |
| 209 | 8000, |
| 210 | rm9000, |
| 211 | 10000, |
| 212 | 12000, |
| 213 | mips32-4k, |
| 214 | sb1 |
| 215 | @end quotation |
| 216 | |
| 217 | @item -mtune=@var{cpu} |
| 218 | Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are |
| 219 | identical to @samp{-march=@var{cpu}}. |
| 220 | |
| 221 | @item -mabi=@var{abi} |
| 222 | Record which ABI the source code uses. The recognized arguments |
| 223 | are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}. |
| 224 | |
| 225 | @item -msym32 |
| 226 | @itemx -mno-sym32 |
| 227 | @cindex -msym32 |
| 228 | @cindex -mno-sym32 |
| 229 | Equivalent to adding @code{.set sym32} or @code{.set nosym32} to |
| 230 | the beginning of the assembler input. @xref{MIPS symbol sizes}. |
| 231 | |
| 232 | @cindex @code{-nocpp} ignored (MIPS) |
| 233 | @item -nocpp |
| 234 | This option is ignored. It is accepted for command-line compatibility with |
| 235 | other assemblers, which use it to turn off C style preprocessing. With |
| 236 | @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the |
| 237 | @sc{gnu} assembler itself never runs the C preprocessor. |
| 238 | |
| 239 | @item --construct-floats |
| 240 | @itemx --no-construct-floats |
| 241 | @cindex --construct-floats |
| 242 | @cindex --no-construct-floats |
| 243 | The @code{--no-construct-floats} option disables the construction of |
| 244 | double width floating point constants by loading the two halves of the |
| 245 | value into the two single width floating point registers that make up |
| 246 | the double width register. This feature is useful if the processor |
| 247 | support the FR bit in its status register, and this bit is known (by |
| 248 | the programmer) to be set. This bit prevents the aliasing of the double |
| 249 | width register by the single width registers. |
| 250 | |
| 251 | By default @code{--construct-floats} is selected, allowing construction |
| 252 | of these floating point constants. |
| 253 | |
| 254 | @item --trap |
| 255 | @itemx --no-break |
| 256 | @c FIXME! (1) reflect these options (next item too) in option summaries; |
| 257 | @c (2) stop teasing, say _which_ instructions expanded _how_. |
| 258 | @code{@value{AS}} automatically macro expands certain division and |
| 259 | multiplication instructions to check for overflow and division by zero. This |
| 260 | option causes @code{@value{AS}} to generate code to take a trap exception |
| 261 | rather than a break exception when an error is detected. The trap instructions |
| 262 | are only supported at Instruction Set Architecture level 2 and higher. |
| 263 | |
| 264 | @item --break |
| 265 | @itemx --no-trap |
| 266 | Generate code to take a break exception rather than a trap exception when an |
| 267 | error is detected. This is the default. |
| 268 | |
| 269 | @item -mpdr |
| 270 | @itemx -mno-pdr |
| 271 | Control generation of @code{.pdr} sections. Off by default on IRIX, on |
| 272 | elsewhere. |
| 273 | |
| 274 | @item -mshared |
| 275 | @itemx -mno-shared |
| 276 | When generating code using the Unix calling conventions (selected by |
| 277 | @samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code |
| 278 | which can go into a shared library. The @samp{-mno-shared} option |
| 279 | tells gas to generate code which uses the calling convention, but can |
| 280 | not go into a shared library. The resulting code is slightly more |
| 281 | efficient. This option only affects the handling of the |
| 282 | @samp{.cpload} and @samp{.cpsetup} pseudo-ops. |
| 283 | @end table |
| 284 | |
| 285 | @node MIPS Object |
| 286 | @section MIPS ECOFF object code |
| 287 | |
| 288 | @cindex ECOFF sections |
| 289 | @cindex MIPS ECOFF sections |
| 290 | Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections |
| 291 | besides the usual @code{.text}, @code{.data} and @code{.bss}. The |
| 292 | additional sections are @code{.rdata}, used for read-only data, |
| 293 | @code{.sdata}, used for small data, and @code{.sbss}, used for small |
| 294 | common objects. |
| 295 | |
| 296 | @cindex small objects, MIPS ECOFF |
| 297 | @cindex @code{gp} register, MIPS |
| 298 | When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28}) |
| 299 | register to form the address of a ``small object''. Any object in the |
| 300 | @code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense. |
| 301 | For external objects, or for objects in the @code{.bss} section, you can use |
| 302 | the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via |
| 303 | @code{$gp}; the default value is 8, meaning that a reference to any object |
| 304 | eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to |
| 305 | @code{@value{AS}} prevents it from using the @code{$gp} register on the basis |
| 306 | of object size (but the assembler uses @code{$gp} for objects in @code{.sdata} |
| 307 | or @code{sbss} in any case). The size of an object in the @code{.bss} section |
| 308 | is set by the @code{.comm} or @code{.lcomm} directive that defines it. The |
| 309 | size of an external object may be set with the @code{.extern} directive. For |
| 310 | example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes |
| 311 | in length, whie leaving @code{sym} otherwise undefined. |
| 312 | |
| 313 | Using small @sc{ecoff} objects requires linker support, and assumes that the |
| 314 | @code{$gp} register is correctly initialized (normally done automatically by |
| 315 | the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the |
| 316 | @code{$gp} register. |
| 317 | |
| 318 | @node MIPS Stabs |
| 319 | @section Directives for debugging information |
| 320 | |
| 321 | @cindex MIPS debugging directives |
| 322 | @sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for |
| 323 | generating debugging information which are not support by traditional @sc{mips} |
| 324 | assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file}, |
| 325 | @code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val}, |
| 326 | @code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information |
| 327 | generated by the three @code{.stab} directives can only be read by @sc{gdb}, |
| 328 | not by traditional @sc{mips} debuggers (this enhancement is required to fully |
| 329 | support C++ debugging). These directives are primarily used by compilers, not |
| 330 | assembly language programmers! |
| 331 | |
| 332 | @node MIPS symbol sizes |
| 333 | @section Directives to override the size of symbols |
| 334 | |
| 335 | @cindex @code{.set sym32} |
| 336 | @cindex @code{.set nosym32} |
| 337 | The n64 ABI allows symbols to have any 64-bit value. Although this |
| 338 | provides a great deal of flexibility, it means that some macros have |
| 339 | much longer expansions than their 32-bit counterparts. For example, |
| 340 | the non-PIC expansion of @samp{dla $4,sym} is usually: |
| 341 | |
| 342 | @smallexample |
| 343 | lui $4,%highest(sym) |
| 344 | lui $1,%hi(sym) |
| 345 | daddiu $4,$4,%higher(sym) |
| 346 | daddiu $1,$1,%lo(sym) |
| 347 | dsll32 $4,$4,0 |
| 348 | daddu $4,$4,$1 |
| 349 | @end smallexample |
| 350 | |
| 351 | whereas the 32-bit expansion is simply: |
| 352 | |
| 353 | @smallexample |
| 354 | lui $4,%hi(sym) |
| 355 | daddiu $4,$4,%lo(sym) |
| 356 | @end smallexample |
| 357 | |
| 358 | n64 code is sometimes constructed in such a way that all symbolic |
| 359 | constants are known to have 32-bit values, and in such cases, it's |
| 360 | preferable to use the 32-bit expansion instead of the 64-bit |
| 361 | expansion. |
| 362 | |
| 363 | You can use the @code{.set sym32} directive to tell the assembler |
| 364 | that, from this point on, all expressions of the form |
| 365 | @samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}} |
| 366 | have 32-bit values. For example: |
| 367 | |
| 368 | @smallexample |
| 369 | .set sym32 |
| 370 | dla $4,sym |
| 371 | lw $4,sym+16 |
| 372 | sw $4,sym+0x8000($4) |
| 373 | @end smallexample |
| 374 | |
| 375 | will cause the assembler to treat @samp{sym}, @code{sym+16} and |
| 376 | @code{sym+0x8000} as 32-bit values. The handling of non-symbolic |
| 377 | addresses is not affected. |
| 378 | |
| 379 | The directive @code{.set nosym32} ends a @code{.set sym32} block and |
| 380 | reverts to the normal behavior. It is also possible to change the |
| 381 | symbol size using the command-line options @option{-msym32} and |
| 382 | @option{-mno-sym32}. |
| 383 | |
| 384 | These options and directives are always accepted, but at present, |
| 385 | they have no effect for anything other than n64. |
| 386 | |
| 387 | @node MIPS ISA |
| 388 | @section Directives to override the ISA level |
| 389 | |
| 390 | @cindex MIPS ISA override |
| 391 | @kindex @code{.set mips@var{n}} |
| 392 | @sc{gnu} @code{@value{AS}} supports an additional directive to change |
| 393 | the @sc{mips} Instruction Set Architecture level on the fly: @code{.set |
| 394 | mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64 |
| 395 | or 64r2. |
| 396 | The values other than 0 make the assembler accept instructions |
| 397 | for the corresponding @sc{isa} level, from that point on in the |
| 398 | assembly. @code{.set mips@var{n}} affects not only which instructions |
| 399 | are permitted, but also how certain macros are expanded. @code{.set |
| 400 | mips0} restores the @sc{isa} level to its original level: either the |
| 401 | level you selected with command line options, or the default for your |
| 402 | configuration. You can use this feature to permit specific @sc{r4000} |
| 403 | instructions while assembling in 32 bit mode. Use this directive with |
| 404 | care! |
| 405 | |
| 406 | The directive @samp{.set mips16} puts the assembler into MIPS 16 mode, |
| 407 | in which it will assemble instructions for the MIPS 16 processor. Use |
| 408 | @samp{.set nomips16} to return to normal 32 bit mode. |
| 409 | |
| 410 | The @samp{.set smartmips} directive enables use of the SmartMIPS |
| 411 | extensions to the MIPS32 @sc{isa}; the @samp{.set nosmartmips} directive |
| 412 | reverses that. |
| 413 | |
| 414 | Traditional @sc{mips} assemblers do not support this directive. |
| 415 | |
| 416 | @node MIPS autoextend |
| 417 | @section Directives for extending MIPS 16 bit instructions |
| 418 | |
| 419 | @kindex @code{.set autoextend} |
| 420 | @kindex @code{.set noautoextend} |
| 421 | By default, MIPS 16 instructions are automatically extended to 32 bits |
| 422 | when necessary. The directive @samp{.set noautoextend} will turn this |
| 423 | off. When @samp{.set noautoextend} is in effect, any 32 bit instruction |
| 424 | must be explicitly extended with the @samp{.e} modifier (e.g., |
| 425 | @samp{li.e $4,1000}). The directive @samp{.set autoextend} may be used |
| 426 | to once again automatically extend instructions when necessary. |
| 427 | |
| 428 | This directive is only meaningful when in MIPS 16 mode. Traditional |
| 429 | @sc{mips} assemblers do not support this directive. |
| 430 | |
| 431 | @node MIPS insn |
| 432 | @section Directive to mark data as an instruction |
| 433 | |
| 434 | @kindex @code{.insn} |
| 435 | The @code{.insn} directive tells @code{@value{AS}} that the following |
| 436 | data is actually instructions. This makes a difference in MIPS 16 mode: |
| 437 | when loading the address of a label which precedes instructions, |
| 438 | @code{@value{AS}} automatically adds 1 to the value, so that jumping to |
| 439 | the loaded address will do the right thing. |
| 440 | |
| 441 | @node MIPS option stack |
| 442 | @section Directives to save and restore options |
| 443 | |
| 444 | @cindex MIPS option stack |
| 445 | @kindex @code{.set push} |
| 446 | @kindex @code{.set pop} |
| 447 | The directives @code{.set push} and @code{.set pop} may be used to save |
| 448 | and restore the current settings for all the options which are |
| 449 | controlled by @code{.set}. The @code{.set push} directive saves the |
| 450 | current settings on a stack. The @code{.set pop} directive pops the |
| 451 | stack and restores the settings. |
| 452 | |
| 453 | These directives can be useful inside an macro which must change an |
| 454 | option such as the ISA level or instruction reordering but does not want |
| 455 | to change the state of the code which invoked the macro. |
| 456 | |
| 457 | Traditional @sc{mips} assemblers do not support these directives. |
| 458 | |
| 459 | @node MIPS ASE instruction generation overrides |
| 460 | @section Directives to control generation of MIPS ASE instructions |
| 461 | |
| 462 | @cindex MIPS MIPS-3D instruction generation override |
| 463 | @kindex @code{.set mips3d} |
| 464 | @kindex @code{.set nomips3d} |
| 465 | The directive @code{.set mips3d} makes the assembler accept instructions |
| 466 | from the MIPS-3D Application Specific Extension from that point on |
| 467 | in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D |
| 468 | instructions from being accepted. |
| 469 | |
| 470 | @cindex MIPS MDMX instruction generation override |
| 471 | @kindex @code{.set mdmx} |
| 472 | @kindex @code{.set nomdmx} |
| 473 | The directive @code{.set mdmx} makes the assembler accept instructions |
| 474 | from the MDMX Application Specific Extension from that point on |
| 475 | in the assembly. The @code{.set nomdmx} directive prevents MDMX |
| 476 | instructions from being accepted. |
| 477 | |
| 478 | @cindex MIPS DSP instruction generation override |
| 479 | @kindex @code{.set dsp} |
| 480 | @kindex @code{.set nodsp} |
| 481 | The directive @code{.set dsp} makes the assembler accept instructions |
| 482 | from the DSP Application Specific Extension from that point on |
| 483 | in the assembly. The @code{.set nodsp} directive prevents DSP |
| 484 | instructions from being accepted. |
| 485 | |
| 486 | @cindex MIPS MT instruction generation override |
| 487 | @kindex @code{.set mt} |
| 488 | @kindex @code{.set nomt} |
| 489 | The directive @code{.set mt} makes the assembler accept instructions |
| 490 | from the MT Application Specific Extension from that point on |
| 491 | in the assembly. The @code{.set nomt} directive prevents MT |
| 492 | instructions from being accepted. |
| 493 | |
| 494 | Traditional @sc{mips} assemblers do not support these directives. |