| 1 | @c Copyright (C) 2013-2021 Free Software Foundation, Inc. |
| 2 | @c This is part of the GAS manual. |
| 3 | @c For copying conditions, see the file as.texinfo. |
| 4 | @c man end |
| 5 | |
| 6 | @ifset GENERIC |
| 7 | @page |
| 8 | @node NDS32-Dependent |
| 9 | @chapter NDS32 Dependent Features |
| 10 | @end ifset |
| 11 | @ifclear GENERIC |
| 12 | @node Machine Dependencies |
| 13 | @chapter NDS32 Dependent Features |
| 14 | @end ifclear |
| 15 | |
| 16 | @cindex NDS32 processor |
| 17 | The NDS32 processors family includes high-performance and low-power 32-bit |
| 18 | processors for high-end to low-end. @sc{gnu} @code{@value{AS}} for NDS32 |
| 19 | architectures supports NDS32 ISA version 3. For detail about NDS32 |
| 20 | instruction set, please see the AndeStar ISA User Manual which is available |
| 21 | at http://www.andestech.com/en/index/index.htm |
| 22 | |
| 23 | @menu |
| 24 | * NDS32 Options:: Assembler options |
| 25 | * NDS32 Syntax:: High-level assembly macros |
| 26 | @end menu |
| 27 | |
| 28 | @node NDS32 Options |
| 29 | @section NDS32 Options |
| 30 | |
| 31 | @cindex NDS32 options |
| 32 | @cindex options for NDS32 |
| 33 | The NDS32 configurations of @sc{gnu} @code{@value{AS}} support these |
| 34 | special options: |
| 35 | |
| 36 | @c man begin OPTIONS |
| 37 | @table @code |
| 38 | |
| 39 | @item -O1 |
| 40 | Optimize for performance. |
| 41 | |
| 42 | @item -Os |
| 43 | Optimize for space. |
| 44 | |
| 45 | @item -EL |
| 46 | Produce little endian data output. |
| 47 | |
| 48 | @item -EB |
| 49 | Produce little endian data output. |
| 50 | |
| 51 | @item -mpic |
| 52 | Generate PIC. |
| 53 | |
| 54 | @item -mno-fp-as-gp-relax |
| 55 | Suppress fp-as-gp relaxation for this file. |
| 56 | |
| 57 | @item -mb2bb-relax |
| 58 | Back-to-back branch optimization. |
| 59 | |
| 60 | @item -mno-all-relax |
| 61 | Suppress all relaxation for this file. |
| 62 | |
| 63 | @item -march=<arch name> |
| 64 | Assemble for architecture <arch name> which could be v3, v3j, v3m, v3f, |
| 65 | v3s, v2, v2j, v2f, v2s. |
| 66 | |
| 67 | @item -mbaseline=<baseline> |
| 68 | Assemble for baseline <baseline> which could be v2, v3, v3m. |
| 69 | |
| 70 | @item -mfpu-freg=@var{FREG} |
| 71 | Specify a FPU configuration. |
| 72 | @table @code |
| 73 | @item 0 8 SP / 4 DP registers |
| 74 | @item 1 16 SP / 8 DP registers |
| 75 | @item 2 32 SP / 16 DP registers |
| 76 | @item 3 32 SP / 32 DP registers |
| 77 | @end table |
| 78 | |
| 79 | @item -mabi=@var{abi} |
| 80 | Specify a abi version <abi> could be v1, v2, v2fp, v2fpp. |
| 81 | |
| 82 | @item -m[no-]mac |
| 83 | Enable/Disable Multiply instructions support. |
| 84 | |
| 85 | @item -m[no-]div |
| 86 | Enable/Disable Divide instructions support. |
| 87 | |
| 88 | @item -m[no-]16bit-ext |
| 89 | Enable/Disable 16-bit extension |
| 90 | |
| 91 | @item -m[no-]dx-regs |
| 92 | Enable/Disable d0/d1 registers |
| 93 | |
| 94 | @item -m[no-]perf-ext |
| 95 | Enable/Disable Performance extension |
| 96 | |
| 97 | @item -m[no-]perf2-ext |
| 98 | Enable/Disable Performance extension 2 |
| 99 | |
| 100 | @item -m[no-]string-ext |
| 101 | Enable/Disable String extension |
| 102 | |
| 103 | @item -m[no-]reduced-regs |
| 104 | Enable/Disable Reduced Register configuration (GPR16) option |
| 105 | |
| 106 | @item -m[no-]audio-isa-ext |
| 107 | Enable/Disable AUDIO ISA extension |
| 108 | |
| 109 | @item -m[no-]fpu-sp-ext |
| 110 | Enable/Disable FPU SP extension |
| 111 | |
| 112 | @item -m[no-]fpu-dp-ext |
| 113 | Enable/Disable FPU DP extension |
| 114 | |
| 115 | @item -m[no-]fpu-fma |
| 116 | Enable/Disable FPU fused-multiply-add instructions |
| 117 | |
| 118 | @item -mall-ext |
| 119 | Turn on all extensions and instructions support |
| 120 | @end table |
| 121 | @c man end |
| 122 | |
| 123 | @node NDS32 Syntax |
| 124 | @section Syntax |
| 125 | |
| 126 | @menu |
| 127 | * NDS32-Chars:: Special Characters |
| 128 | * NDS32-Regs:: Register Names |
| 129 | * NDS32-Ops:: Pseudo Instructions |
| 130 | @end menu |
| 131 | |
| 132 | @node NDS32-Chars |
| 133 | @subsection Special Characters |
| 134 | |
| 135 | Use @samp{#} at column 1 and @samp{!} anywhere in the line except inside |
| 136 | quotes. |
| 137 | |
| 138 | Multiple instructions in a line are allowed though not recommended and |
| 139 | should be separated by @samp{;}. |
| 140 | |
| 141 | Assembler is not case-sensitive in general except user defined label. |
| 142 | For example, @samp{jral F1} is different from @samp{jral f1} while it is |
| 143 | the same as @samp{JRAL F1}. |
| 144 | |
| 145 | @node NDS32-Regs |
| 146 | @subsection Register Names |
| 147 | @table @code |
| 148 | @item General purpose registers (GPR) |
| 149 | There are 32 32-bit general purpose registers $r0 to $r31. |
| 150 | |
| 151 | @item Accumulators d0 and d1 |
| 152 | 64-bit accumulators: $d0.hi, $d0.lo, $d1.hi, and $d1.lo. |
| 153 | |
| 154 | @item Assembler reserved register $ta |
| 155 | Register $ta ($r15) is reserved for assembler using. |
| 156 | |
| 157 | @item Operating system reserved registers $p0 and $p1 |
| 158 | Registers $p0 ($r26) and $p1 ($r27) are used by operating system as scratch |
| 159 | registers. |
| 160 | |
| 161 | @item Frame pointer $fp |
| 162 | Register $r28 is regarded as the frame pointer. |
| 163 | |
| 164 | @item Global pointer |
| 165 | Register $r29 is regarded as the global pointer. |
| 166 | |
| 167 | @item Link pointer |
| 168 | Register $r30 is regarded as the link pointer. |
| 169 | |
| 170 | @item Stack pointer |
| 171 | Register $r31 is regarded as the stack pointer. |
| 172 | @end table |
| 173 | |
| 174 | @node NDS32-Ops |
| 175 | @subsection Pseudo Instructions |
| 176 | @table @code |
| 177 | @item li rt5,imm32 |
| 178 | load 32-bit integer into register rt5. @samp{sethi rt5,hi20(imm32)} and then |
| 179 | @samp{ori rt5,reg,lo12(imm32)}. |
| 180 | |
| 181 | @item la rt5,var |
| 182 | Load 32-bit address of var into register rt5. @samp{sethi rt5,hi20(var)} and |
| 183 | then @samp{ori reg,rt5,lo12(var)} |
| 184 | |
| 185 | @item l.[bhw] rt5,var |
| 186 | Load value of var into register rt5. @samp{sethi $ta,hi20(var)} and then |
| 187 | @samp{l[bhw]i rt5,[$ta+lo12(var)]} |
| 188 | |
| 189 | @item l.[bh]s rt5,var |
| 190 | Load value of var into register rt5. @samp{sethi $ta,hi20(var)} and then |
| 191 | @samp{l[bh]si rt5,[$ta+lo12(var)]} |
| 192 | |
| 193 | @item l.[bhw]p rt5,var,inc |
| 194 | Load value of var into register rt5 and increment $ta by amount inc. |
| 195 | @samp{la $ta,var} and then @samp{l[bhw]i.bi rt5,[$ta],inc} |
| 196 | |
| 197 | @item l.[bhw]pc rt5,inc |
| 198 | Continue loading value of var into register rt5 and increment $ta by amount inc. |
| 199 | @samp{l[bhw]i.bi rt5,[$ta],inc.} |
| 200 | |
| 201 | @item l.[bh]sp rt5,var,inc |
| 202 | Load value of var into register rt5 and increment $ta by amount inc. |
| 203 | @samp{la $ta,var} and then @samp{l[bh]si.bi rt5,[$ta],inc} |
| 204 | |
| 205 | @item l.[bh]spc rt5,inc |
| 206 | Continue loading value of var into register rt5 and increment $ta by amount inc. |
| 207 | @samp{l[bh]si.bi rt5,[$ta],inc.} |
| 208 | |
| 209 | @item s.[bhw] rt5,var |
| 210 | Store register rt5 to var. |
| 211 | @samp{sethi $ta,hi20(var)} and then @samp{s[bhw]i rt5,[$ta+lo12(var)]} |
| 212 | |
| 213 | @item s.[bhw]p rt5,var,inc |
| 214 | Store register rt5 to var and increment $ta by amount inc. |
| 215 | @samp{la $ta,var} and then @samp{s[bhw]i.bi rt5,[$ta],inc} |
| 216 | |
| 217 | @item s.[bhw]pc rt5,inc |
| 218 | Continue storing register rt5 to var and increment $ta by amount inc. |
| 219 | @samp{s[bhw]i.bi rt5,[$ta],inc.} |
| 220 | |
| 221 | @item not rt5,ra5 |
| 222 | Alias of @samp{nor rt5,ra5,ra5}. |
| 223 | |
| 224 | @item neg rt5,ra5 |
| 225 | Alias of @samp{subri rt5,ra5,0}. |
| 226 | |
| 227 | @item br rb5 |
| 228 | Depending on how it is assembled, it is translated into @samp{r5 rb5} |
| 229 | or @samp{jr rb5}. |
| 230 | |
| 231 | @item b label |
| 232 | Branch to label depending on how it is assembled, it is translated into |
| 233 | @samp{j8 label}, @samp{j label}, or "@samp{la $ta,label} @samp{br $ta}". |
| 234 | |
| 235 | @item bral rb5 |
| 236 | Alias of jral br5 depending on how it is assembled, it is translated |
| 237 | into @samp{jral5 rb5} or @samp{jral rb5}. |
| 238 | |
| 239 | @item bal fname |
| 240 | Alias of jal fname depending on how it is assembled, it is translated into |
| 241 | @samp{jal fname} or "@samp{la $ta,fname} @samp{bral $ta}". |
| 242 | |
| 243 | @item call fname |
| 244 | Call function fname same as @samp{jal fname}. |
| 245 | |
| 246 | @item move rt5,ra5 |
| 247 | For 16-bit, this is @samp{mov55 rt5,ra5}. |
| 248 | For no 16-bit, this is @samp{ori rt5,ra5,0}. |
| 249 | |
| 250 | @item move rt5,var |
| 251 | This is the same as @samp{l.w rt5,var}. |
| 252 | |
| 253 | @item move rt5,imm32 |
| 254 | This is the same as @samp{li rt5,imm32}. |
| 255 | |
| 256 | @item pushm ra5,rb5 |
| 257 | Push contents of registers from ra5 to rb5 into stack. |
| 258 | |
| 259 | @item push ra5 |
| 260 | Push content of register ra5 into stack. (same @samp{pushm ra5,ra5}). |
| 261 | |
| 262 | @item push.d var |
| 263 | Push value of double-word variable var into stack. |
| 264 | |
| 265 | @item push.w var |
| 266 | Push value of word variable var into stack. |
| 267 | |
| 268 | @item push.h var |
| 269 | Push value of half-word variable var into stack. |
| 270 | |
| 271 | @item push.b var |
| 272 | Push value of byte variable var into stack. |
| 273 | |
| 274 | @item pusha var |
| 275 | Push 32-bit address of variable var into stack. |
| 276 | |
| 277 | @item pushi imm32 |
| 278 | Push 32-bit immediate value into stack. |
| 279 | |
| 280 | @item popm ra5,rb5 |
| 281 | Pop top of stack values into registers ra5 to rb5. |
| 282 | |
| 283 | @item pop rt5 |
| 284 | Pop top of stack value into register. (same as @samp{popm rt5,rt5}.) |
| 285 | |
| 286 | @item pop.d var,ra5 |
| 287 | Pop value of double-word variable var from stack using register ra5 |
| 288 | as 2nd scratch register. (1st is $ta) |
| 289 | |
| 290 | @item pop.w var,ra5 |
| 291 | Pop value of word variable var from stack using register ra5. |
| 292 | |
| 293 | @item pop.h var,ra5 |
| 294 | Pop value of half-word variable var from stack using register ra5. |
| 295 | |
| 296 | @item pop.b var,ra5 |
| 297 | Pop value of byte variable var from stack using register ra5. |
| 298 | |
| 299 | @end table |