| 1 | /* fp_cvt_ins.s Test file for AArch64 floating-point<->fixed-point |
| 2 | conversion and floating-point<->integer conversion instructions. |
| 3 | |
| 4 | Copyright (C) 2011-2018 Free Software Foundation, Inc. |
| 5 | Contributed by ARM Ltd. |
| 6 | |
| 7 | This file is part of GAS. |
| 8 | |
| 9 | GAS is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 3 of the license, or |
| 12 | (at your option) any later version. |
| 13 | |
| 14 | GAS is distributed in the hope that it will be useful, |
| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License |
| 20 | along with this program; see the file COPYING3. If not, |
| 21 | see <http://www.gnu.org/licenses/>. */ |
| 22 | |
| 23 | // SCVTF & UCVTF |
| 24 | .macro do_cvtf fbits, reg |
| 25 | .ifc \fbits, 0 |
| 26 | // Floating-point<->integer conversions |
| 27 | SCVTF \reg\()7, W7 |
| 28 | SCVTF \reg\()7, X7 |
| 29 | UCVTF \reg\()7, W7 |
| 30 | UCVTF \reg\()7, X7 |
| 31 | .else |
| 32 | // Floating-point<->fixed-point conversions |
| 33 | .ifle \fbits-32 |
| 34 | SCVTF \reg\()7, W7, #\fbits |
| 35 | .endif |
| 36 | SCVTF \reg\()7, X7, #\fbits |
| 37 | .ifle \fbits-32 |
| 38 | UCVTF \reg\()7, W7, #\fbits |
| 39 | .endif |
| 40 | UCVTF \reg\()7, X7, #\fbits |
| 41 | .endif |
| 42 | .endm |
| 43 | |
| 44 | // FMOV |
| 45 | .macro do_fmov type |
| 46 | .ifc \type, S |
| 47 | // 32-bit |
| 48 | FMOV W7, S7 |
| 49 | FMOV S7, W7 |
| 50 | .elseif \type == D |
| 51 | // 64-bit |
| 52 | FMOV X7, D7 |
| 53 | FMOV D7, X7 |
| 54 | .else |
| 55 | // 64-bit with V reg element |
| 56 | FMOV X7, V7.D[1] |
| 57 | FMOV V7.D[1], X7 |
| 58 | .endif |
| 59 | .endm |
| 60 | |
| 61 | .macro do_fcvt suffix, fbits, reg |
| 62 | .ifc \fbits, 0 |
| 63 | // Floating-point<->integer conversions |
| 64 | FCVT\suffix W7, \reg\()7 |
| 65 | FCVT\suffix X7, \reg\()7 |
| 66 | .else |
| 67 | // Floating-point<->fixed-point conversions |
| 68 | .ifle \fbits-32 |
| 69 | FCVT\suffix W7, \reg\()7, #\fbits |
| 70 | .endif |
| 71 | FCVT\suffix X7, \reg\()7, #\fbits |
| 72 | .endif |
| 73 | .endm |
| 74 | |
| 75 | .macro fcvts_with_fbits fbits |
| 76 | .ifc \fbits, 0 |
| 77 | // fp <-> integer |
| 78 | .irp reg, S, D |
| 79 | // single-precision and double precision |
| 80 | do_fcvt NS, \fbits, \reg |
| 81 | do_fcvt NU, \fbits, \reg |
| 82 | do_fcvt PS, \fbits, \reg |
| 83 | do_fcvt PU, \fbits, \reg |
| 84 | do_fcvt MS, \fbits, \reg |
| 85 | do_fcvt MU, \fbits, \reg |
| 86 | do_fcvt ZS, \fbits, \reg |
| 87 | do_fcvt ZU, \fbits, \reg |
| 88 | do_cvtf \fbits, \reg |
| 89 | do_fcvt AS, \fbits, \reg |
| 90 | do_fcvt AU, \fbits, \reg |
| 91 | do_fmov S |
| 92 | .endr |
| 93 | .else |
| 94 | // fp <-> fixed-point |
| 95 | // After ISA 2.06, only FCVTZ[US] and [US]CVTF are available |
| 96 | .irp reg, S, D |
| 97 | // single-precision and double precision |
| 98 | do_fcvt ZS, \fbits, \reg |
| 99 | do_fcvt ZU, \fbits, \reg |
| 100 | do_cvtf \fbits, \reg |
| 101 | .endr |
| 102 | .endif |
| 103 | .endm |
| 104 | |
| 105 | .macro fcvts_with_fbits_wrapper from=0, to=64 |
| 106 | fcvts_with_fbits \from |
| 107 | .if \to-\from |
| 108 | fcvts_with_fbits_wrapper "(\from+1)", \to |
| 109 | .endif |
| 110 | .endm |
| 111 | |
| 112 | func: |
| 113 | // Generate fcvt instructions without fbits and |
| 114 | // with fbits from 1 to 64, also generate [us]cvtf |
| 115 | // and fmov. |
| 116 | fcvts_with_fbits_wrapper from=0, to=64 |
| 117 | do_fmov V |