| 1 | #objdump: -dr --prefix-addresses --show-raw-insn |
| 2 | #name: MIPS relaxed macro with branch swapping |
| 3 | #as: -32 |
| 4 | #source: relax-swap3.s |
| 5 | |
| 6 | .*: +file format .*mips.* |
| 7 | |
| 8 | Disassembly of section \.text: |
| 9 | [0-9a-f]+ <[^>]*> f000 6a00 li v0,0 |
| 10 | [ ]*[0-9a-f]+: R_MIPS16_HI16 bar |
| 11 | [0-9a-f]+ <[^>]*> f400 3240 sll v0,16 |
| 12 | [0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0 |
| 13 | [ ]*[0-9a-f]+: R_MIPS16_LO16 bar |
| 14 | [0-9a-f]+ <[^>]*> eb80 jrc v1 |
| 15 | [0-9a-f]+ <[^>]*> f000 6a00 li v0,0 |
| 16 | [ ]*[0-9a-f]+: R_MIPS16_HI16 bar |
| 17 | [0-9a-f]+ <[^>]*> f400 3240 sll v0,16 |
| 18 | [0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0 |
| 19 | [ ]*[0-9a-f]+: R_MIPS16_LO16 bar |
| 20 | [0-9a-f]+ <[^>]*> 2300 beqz v1,[0-9a-f]+ <[^>]*> |
| 21 | \.\.\. |