| 1 | /* Native-dependent code for GNU/Linux AArch64. |
| 2 | |
| 3 | Copyright (C) 2011-2019 Free Software Foundation, Inc. |
| 4 | Contributed by ARM Ltd. |
| 5 | |
| 6 | This file is part of GDB. |
| 7 | |
| 8 | This program is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU General Public License as published by |
| 10 | the Free Software Foundation; either version 3 of the License, or |
| 11 | (at your option) any later version. |
| 12 | |
| 13 | This program is distributed in the hope that it will be useful, |
| 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | GNU General Public License for more details. |
| 17 | |
| 18 | You should have received a copy of the GNU General Public License |
| 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 20 | |
| 21 | #include "defs.h" |
| 22 | |
| 23 | #include "inferior.h" |
| 24 | #include "gdbcore.h" |
| 25 | #include "regcache.h" |
| 26 | #include "linux-nat.h" |
| 27 | #include "target-descriptions.h" |
| 28 | #include "auxv.h" |
| 29 | #include "gdbcmd.h" |
| 30 | #include "aarch64-tdep.h" |
| 31 | #include "aarch64-linux-tdep.h" |
| 32 | #include "aarch32-linux-nat.h" |
| 33 | #include "aarch32-tdep.h" |
| 34 | #include "arch/arm.h" |
| 35 | #include "nat/aarch64-linux.h" |
| 36 | #include "nat/aarch64-linux-hw-point.h" |
| 37 | #include "nat/aarch64-sve-linux-ptrace.h" |
| 38 | |
| 39 | #include "elf/external.h" |
| 40 | #include "elf/common.h" |
| 41 | |
| 42 | #include "nat/gdb_ptrace.h" |
| 43 | #include <sys/utsname.h> |
| 44 | #include <asm/ptrace.h> |
| 45 | |
| 46 | #include "gregset.h" |
| 47 | #include "linux-tdep.h" |
| 48 | |
| 49 | /* Defines ps_err_e, struct ps_prochandle. */ |
| 50 | #include "gdb_proc_service.h" |
| 51 | #include "arch-utils.h" |
| 52 | |
| 53 | #ifndef TRAP_HWBKPT |
| 54 | #define TRAP_HWBKPT 0x0004 |
| 55 | #endif |
| 56 | |
| 57 | class aarch64_linux_nat_target final : public linux_nat_target |
| 58 | { |
| 59 | public: |
| 60 | /* Add our register access methods. */ |
| 61 | void fetch_registers (struct regcache *, int) override; |
| 62 | void store_registers (struct regcache *, int) override; |
| 63 | |
| 64 | const struct target_desc *read_description () override; |
| 65 | |
| 66 | /* Add our hardware breakpoint and watchpoint implementation. */ |
| 67 | int can_use_hw_breakpoint (enum bptype, int, int) override; |
| 68 | int insert_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; |
| 69 | int remove_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; |
| 70 | int region_ok_for_hw_watchpoint (CORE_ADDR, int) override; |
| 71 | int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, |
| 72 | struct expression *) override; |
| 73 | int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, |
| 74 | struct expression *) override; |
| 75 | bool stopped_by_watchpoint () override; |
| 76 | bool stopped_data_address (CORE_ADDR *) override; |
| 77 | bool watchpoint_addr_within_range (CORE_ADDR, CORE_ADDR, int) override; |
| 78 | |
| 79 | int can_do_single_step () override; |
| 80 | |
| 81 | /* Override the GNU/Linux inferior startup hook. */ |
| 82 | void post_startup_inferior (ptid_t) override; |
| 83 | |
| 84 | /* Override the GNU/Linux post attach hook. */ |
| 85 | void post_attach (int pid) override; |
| 86 | |
| 87 | /* These three defer to common nat/ code. */ |
| 88 | void low_new_thread (struct lwp_info *lp) override |
| 89 | { aarch64_linux_new_thread (lp); } |
| 90 | void low_delete_thread (struct arch_lwp_info *lp) override |
| 91 | { aarch64_linux_delete_thread (lp); } |
| 92 | void low_prepare_to_resume (struct lwp_info *lp) override |
| 93 | { aarch64_linux_prepare_to_resume (lp); } |
| 94 | |
| 95 | void low_new_fork (struct lwp_info *parent, pid_t child_pid) override; |
| 96 | void low_forget_process (pid_t pid) override; |
| 97 | |
| 98 | /* Add our siginfo layout converter. */ |
| 99 | bool low_siginfo_fixup (siginfo_t *ptrace, gdb_byte *inf, int direction) |
| 100 | override; |
| 101 | |
| 102 | struct gdbarch *thread_architecture (ptid_t) override; |
| 103 | }; |
| 104 | |
| 105 | static aarch64_linux_nat_target the_aarch64_linux_nat_target; |
| 106 | |
| 107 | /* Per-process data. We don't bind this to a per-inferior registry |
| 108 | because of targets like x86 GNU/Linux that need to keep track of |
| 109 | processes that aren't bound to any inferior (e.g., fork children, |
| 110 | checkpoints). */ |
| 111 | |
| 112 | struct aarch64_process_info |
| 113 | { |
| 114 | /* Linked list. */ |
| 115 | struct aarch64_process_info *next; |
| 116 | |
| 117 | /* The process identifier. */ |
| 118 | pid_t pid; |
| 119 | |
| 120 | /* Copy of aarch64 hardware debug registers. */ |
| 121 | struct aarch64_debug_reg_state state; |
| 122 | }; |
| 123 | |
| 124 | static struct aarch64_process_info *aarch64_process_list = NULL; |
| 125 | |
| 126 | /* Find process data for process PID. */ |
| 127 | |
| 128 | static struct aarch64_process_info * |
| 129 | aarch64_find_process_pid (pid_t pid) |
| 130 | { |
| 131 | struct aarch64_process_info *proc; |
| 132 | |
| 133 | for (proc = aarch64_process_list; proc; proc = proc->next) |
| 134 | if (proc->pid == pid) |
| 135 | return proc; |
| 136 | |
| 137 | return NULL; |
| 138 | } |
| 139 | |
| 140 | /* Add process data for process PID. Returns newly allocated info |
| 141 | object. */ |
| 142 | |
| 143 | static struct aarch64_process_info * |
| 144 | aarch64_add_process (pid_t pid) |
| 145 | { |
| 146 | struct aarch64_process_info *proc; |
| 147 | |
| 148 | proc = XCNEW (struct aarch64_process_info); |
| 149 | proc->pid = pid; |
| 150 | |
| 151 | proc->next = aarch64_process_list; |
| 152 | aarch64_process_list = proc; |
| 153 | |
| 154 | return proc; |
| 155 | } |
| 156 | |
| 157 | /* Get data specific info for process PID, creating it if necessary. |
| 158 | Never returns NULL. */ |
| 159 | |
| 160 | static struct aarch64_process_info * |
| 161 | aarch64_process_info_get (pid_t pid) |
| 162 | { |
| 163 | struct aarch64_process_info *proc; |
| 164 | |
| 165 | proc = aarch64_find_process_pid (pid); |
| 166 | if (proc == NULL) |
| 167 | proc = aarch64_add_process (pid); |
| 168 | |
| 169 | return proc; |
| 170 | } |
| 171 | |
| 172 | /* Called whenever GDB is no longer debugging process PID. It deletes |
| 173 | data structures that keep track of debug register state. */ |
| 174 | |
| 175 | void |
| 176 | aarch64_linux_nat_target::low_forget_process (pid_t pid) |
| 177 | { |
| 178 | struct aarch64_process_info *proc, **proc_link; |
| 179 | |
| 180 | proc = aarch64_process_list; |
| 181 | proc_link = &aarch64_process_list; |
| 182 | |
| 183 | while (proc != NULL) |
| 184 | { |
| 185 | if (proc->pid == pid) |
| 186 | { |
| 187 | *proc_link = proc->next; |
| 188 | |
| 189 | xfree (proc); |
| 190 | return; |
| 191 | } |
| 192 | |
| 193 | proc_link = &proc->next; |
| 194 | proc = *proc_link; |
| 195 | } |
| 196 | } |
| 197 | |
| 198 | /* Get debug registers state for process PID. */ |
| 199 | |
| 200 | struct aarch64_debug_reg_state * |
| 201 | aarch64_get_debug_reg_state (pid_t pid) |
| 202 | { |
| 203 | return &aarch64_process_info_get (pid)->state; |
| 204 | } |
| 205 | |
| 206 | /* Fill GDB's register array with the general-purpose register values |
| 207 | from the current thread. */ |
| 208 | |
| 209 | static void |
| 210 | fetch_gregs_from_thread (struct regcache *regcache) |
| 211 | { |
| 212 | int ret, tid; |
| 213 | struct gdbarch *gdbarch = regcache->arch (); |
| 214 | elf_gregset_t regs; |
| 215 | struct iovec iovec; |
| 216 | |
| 217 | /* Make sure REGS can hold all registers contents on both aarch64 |
| 218 | and arm. */ |
| 219 | gdb_static_assert (sizeof (regs) >= 18 * 4); |
| 220 | |
| 221 | tid = regcache->ptid ().lwp (); |
| 222 | |
| 223 | iovec.iov_base = ®s; |
| 224 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
| 225 | iovec.iov_len = 18 * 4; |
| 226 | else |
| 227 | iovec.iov_len = sizeof (regs); |
| 228 | |
| 229 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec); |
| 230 | if (ret < 0) |
| 231 | perror_with_name (_("Unable to fetch general registers.")); |
| 232 | |
| 233 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
| 234 | aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, 1); |
| 235 | else |
| 236 | { |
| 237 | int regno; |
| 238 | |
| 239 | for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++) |
| 240 | regcache->raw_supply (regno, ®s[regno - AARCH64_X0_REGNUM]); |
| 241 | } |
| 242 | } |
| 243 | |
| 244 | /* Store to the current thread the valid general-purpose register |
| 245 | values in the GDB's register array. */ |
| 246 | |
| 247 | static void |
| 248 | store_gregs_to_thread (const struct regcache *regcache) |
| 249 | { |
| 250 | int ret, tid; |
| 251 | elf_gregset_t regs; |
| 252 | struct iovec iovec; |
| 253 | struct gdbarch *gdbarch = regcache->arch (); |
| 254 | |
| 255 | /* Make sure REGS can hold all registers contents on both aarch64 |
| 256 | and arm. */ |
| 257 | gdb_static_assert (sizeof (regs) >= 18 * 4); |
| 258 | tid = regcache->ptid ().lwp (); |
| 259 | |
| 260 | iovec.iov_base = ®s; |
| 261 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
| 262 | iovec.iov_len = 18 * 4; |
| 263 | else |
| 264 | iovec.iov_len = sizeof (regs); |
| 265 | |
| 266 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec); |
| 267 | if (ret < 0) |
| 268 | perror_with_name (_("Unable to fetch general registers.")); |
| 269 | |
| 270 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
| 271 | aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, 1); |
| 272 | else |
| 273 | { |
| 274 | int regno; |
| 275 | |
| 276 | for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++) |
| 277 | if (REG_VALID == regcache->get_register_status (regno)) |
| 278 | regcache->raw_collect (regno, ®s[regno - AARCH64_X0_REGNUM]); |
| 279 | } |
| 280 | |
| 281 | ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iovec); |
| 282 | if (ret < 0) |
| 283 | perror_with_name (_("Unable to store general registers.")); |
| 284 | } |
| 285 | |
| 286 | /* Fill GDB's register array with the fp/simd register values |
| 287 | from the current thread. */ |
| 288 | |
| 289 | static void |
| 290 | fetch_fpregs_from_thread (struct regcache *regcache) |
| 291 | { |
| 292 | int ret, tid; |
| 293 | elf_fpregset_t regs; |
| 294 | struct iovec iovec; |
| 295 | struct gdbarch *gdbarch = regcache->arch (); |
| 296 | |
| 297 | /* Make sure REGS can hold all VFP registers contents on both aarch64 |
| 298 | and arm. */ |
| 299 | gdb_static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE); |
| 300 | |
| 301 | tid = regcache->ptid ().lwp (); |
| 302 | |
| 303 | iovec.iov_base = ®s; |
| 304 | |
| 305 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
| 306 | { |
| 307 | iovec.iov_len = ARM_VFP3_REGS_SIZE; |
| 308 | |
| 309 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec); |
| 310 | if (ret < 0) |
| 311 | perror_with_name (_("Unable to fetch VFP registers.")); |
| 312 | |
| 313 | aarch32_vfp_regcache_supply (regcache, (gdb_byte *) ®s, 32); |
| 314 | } |
| 315 | else |
| 316 | { |
| 317 | int regno; |
| 318 | |
| 319 | iovec.iov_len = sizeof (regs); |
| 320 | |
| 321 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec); |
| 322 | if (ret < 0) |
| 323 | perror_with_name (_("Unable to fetch vFP/SIMD registers.")); |
| 324 | |
| 325 | for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++) |
| 326 | regcache->raw_supply (regno, ®s.vregs[regno - AARCH64_V0_REGNUM]); |
| 327 | |
| 328 | regcache->raw_supply (AARCH64_FPSR_REGNUM, ®s.fpsr); |
| 329 | regcache->raw_supply (AARCH64_FPCR_REGNUM, ®s.fpcr); |
| 330 | } |
| 331 | } |
| 332 | |
| 333 | /* Store to the current thread the valid fp/simd register |
| 334 | values in the GDB's register array. */ |
| 335 | |
| 336 | static void |
| 337 | store_fpregs_to_thread (const struct regcache *regcache) |
| 338 | { |
| 339 | int ret, tid; |
| 340 | elf_fpregset_t regs; |
| 341 | struct iovec iovec; |
| 342 | struct gdbarch *gdbarch = regcache->arch (); |
| 343 | |
| 344 | /* Make sure REGS can hold all VFP registers contents on both aarch64 |
| 345 | and arm. */ |
| 346 | gdb_static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE); |
| 347 | tid = regcache->ptid ().lwp (); |
| 348 | |
| 349 | iovec.iov_base = ®s; |
| 350 | |
| 351 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
| 352 | { |
| 353 | iovec.iov_len = ARM_VFP3_REGS_SIZE; |
| 354 | |
| 355 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec); |
| 356 | if (ret < 0) |
| 357 | perror_with_name (_("Unable to fetch VFP registers.")); |
| 358 | |
| 359 | aarch32_vfp_regcache_collect (regcache, (gdb_byte *) ®s, 32); |
| 360 | } |
| 361 | else |
| 362 | { |
| 363 | int regno; |
| 364 | |
| 365 | iovec.iov_len = sizeof (regs); |
| 366 | |
| 367 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec); |
| 368 | if (ret < 0) |
| 369 | perror_with_name (_("Unable to fetch FP/SIMD registers.")); |
| 370 | |
| 371 | for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++) |
| 372 | if (REG_VALID == regcache->get_register_status (regno)) |
| 373 | regcache->raw_collect |
| 374 | (regno, (char *) ®s.vregs[regno - AARCH64_V0_REGNUM]); |
| 375 | |
| 376 | if (REG_VALID == regcache->get_register_status (AARCH64_FPSR_REGNUM)) |
| 377 | regcache->raw_collect (AARCH64_FPSR_REGNUM, (char *) ®s.fpsr); |
| 378 | if (REG_VALID == regcache->get_register_status (AARCH64_FPCR_REGNUM)) |
| 379 | regcache->raw_collect (AARCH64_FPCR_REGNUM, (char *) ®s.fpcr); |
| 380 | } |
| 381 | |
| 382 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
| 383 | { |
| 384 | ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iovec); |
| 385 | if (ret < 0) |
| 386 | perror_with_name (_("Unable to store VFP registers.")); |
| 387 | } |
| 388 | else |
| 389 | { |
| 390 | ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iovec); |
| 391 | if (ret < 0) |
| 392 | perror_with_name (_("Unable to store FP/SIMD registers.")); |
| 393 | } |
| 394 | } |
| 395 | |
| 396 | /* Fill GDB's register array with the sve register values |
| 397 | from the current thread. */ |
| 398 | |
| 399 | static void |
| 400 | fetch_sveregs_from_thread (struct regcache *regcache) |
| 401 | { |
| 402 | std::unique_ptr<gdb_byte[]> base |
| 403 | = aarch64_sve_get_sveregs (regcache->ptid ().lwp ()); |
| 404 | aarch64_sve_regs_copy_to_reg_buf (regcache, base.get ()); |
| 405 | } |
| 406 | |
| 407 | /* Store to the current thread the valid sve register |
| 408 | values in the GDB's register array. */ |
| 409 | |
| 410 | static void |
| 411 | store_sveregs_to_thread (struct regcache *regcache) |
| 412 | { |
| 413 | int ret; |
| 414 | struct iovec iovec; |
| 415 | int tid = regcache->ptid ().lwp (); |
| 416 | |
| 417 | /* First store vector length to the thread. This is done first to ensure the |
| 418 | ptrace buffers read from the kernel are the correct size. */ |
| 419 | if (!aarch64_sve_set_vq (tid, regcache)) |
| 420 | perror_with_name (_("Unable to set VG register.")); |
| 421 | |
| 422 | /* Obtain a dump of SVE registers from ptrace. */ |
| 423 | std::unique_ptr<gdb_byte[]> base = aarch64_sve_get_sveregs (tid); |
| 424 | |
| 425 | /* Overwrite with regcache state. */ |
| 426 | aarch64_sve_regs_copy_from_reg_buf (regcache, base.get ()); |
| 427 | |
| 428 | /* Write back to the kernel. */ |
| 429 | iovec.iov_base = base.get (); |
| 430 | iovec.iov_len = ((struct user_sve_header *) base.get ())->size; |
| 431 | ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_SVE, &iovec); |
| 432 | |
| 433 | if (ret < 0) |
| 434 | perror_with_name (_("Unable to store sve registers")); |
| 435 | } |
| 436 | |
| 437 | /* Fill GDB's register array with the pointer authentication mask values from |
| 438 | the current thread. */ |
| 439 | |
| 440 | static void |
| 441 | fetch_pauth_masks_from_thread (struct regcache *regcache) |
| 442 | { |
| 443 | struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); |
| 444 | int ret; |
| 445 | struct iovec iovec; |
| 446 | uint64_t pauth_regset[2] = {0, 0}; |
| 447 | int tid = regcache->ptid ().lwp (); |
| 448 | |
| 449 | iovec.iov_base = &pauth_regset; |
| 450 | iovec.iov_len = sizeof (pauth_regset); |
| 451 | |
| 452 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_PAC_MASK, &iovec); |
| 453 | if (ret != 0) |
| 454 | perror_with_name (_("unable to fetch pauth registers.")); |
| 455 | |
| 456 | regcache->raw_supply (AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base), |
| 457 | &pauth_regset[0]); |
| 458 | regcache->raw_supply (AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base), |
| 459 | &pauth_regset[1]); |
| 460 | } |
| 461 | |
| 462 | /* Implement the "fetch_registers" target_ops method. */ |
| 463 | |
| 464 | void |
| 465 | aarch64_linux_nat_target::fetch_registers (struct regcache *regcache, |
| 466 | int regno) |
| 467 | { |
| 468 | struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); |
| 469 | |
| 470 | if (regno == -1) |
| 471 | { |
| 472 | fetch_gregs_from_thread (regcache); |
| 473 | if (tdep->has_sve ()) |
| 474 | fetch_sveregs_from_thread (regcache); |
| 475 | else |
| 476 | fetch_fpregs_from_thread (regcache); |
| 477 | |
| 478 | if (tdep->has_pauth ()) |
| 479 | fetch_pauth_masks_from_thread (regcache); |
| 480 | } |
| 481 | else if (regno < AARCH64_V0_REGNUM) |
| 482 | fetch_gregs_from_thread (regcache); |
| 483 | else if (tdep->has_sve ()) |
| 484 | fetch_sveregs_from_thread (regcache); |
| 485 | else |
| 486 | fetch_fpregs_from_thread (regcache); |
| 487 | |
| 488 | if (tdep->has_pauth ()) |
| 489 | { |
| 490 | if (regno == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base) |
| 491 | || regno == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base)) |
| 492 | fetch_pauth_masks_from_thread (regcache); |
| 493 | } |
| 494 | } |
| 495 | |
| 496 | /* Implement the "store_registers" target_ops method. */ |
| 497 | |
| 498 | void |
| 499 | aarch64_linux_nat_target::store_registers (struct regcache *regcache, |
| 500 | int regno) |
| 501 | { |
| 502 | struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); |
| 503 | |
| 504 | if (regno == -1) |
| 505 | { |
| 506 | store_gregs_to_thread (regcache); |
| 507 | if (tdep->has_sve ()) |
| 508 | store_sveregs_to_thread (regcache); |
| 509 | else |
| 510 | store_fpregs_to_thread (regcache); |
| 511 | } |
| 512 | else if (regno < AARCH64_V0_REGNUM) |
| 513 | store_gregs_to_thread (regcache); |
| 514 | else if (tdep->has_sve ()) |
| 515 | store_sveregs_to_thread (regcache); |
| 516 | else |
| 517 | store_fpregs_to_thread (regcache); |
| 518 | } |
| 519 | |
| 520 | /* Fill register REGNO (if it is a general-purpose register) in |
| 521 | *GREGSETPS with the value in GDB's register array. If REGNO is -1, |
| 522 | do this for all registers. */ |
| 523 | |
| 524 | void |
| 525 | fill_gregset (const struct regcache *regcache, |
| 526 | gdb_gregset_t *gregsetp, int regno) |
| 527 | { |
| 528 | regcache_collect_regset (&aarch64_linux_gregset, regcache, |
| 529 | regno, (gdb_byte *) gregsetp, |
| 530 | AARCH64_LINUX_SIZEOF_GREGSET); |
| 531 | } |
| 532 | |
| 533 | /* Fill GDB's register array with the general-purpose register values |
| 534 | in *GREGSETP. */ |
| 535 | |
| 536 | void |
| 537 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
| 538 | { |
| 539 | regcache_supply_regset (&aarch64_linux_gregset, regcache, -1, |
| 540 | (const gdb_byte *) gregsetp, |
| 541 | AARCH64_LINUX_SIZEOF_GREGSET); |
| 542 | } |
| 543 | |
| 544 | /* Fill register REGNO (if it is a floating-point register) in |
| 545 | *FPREGSETP with the value in GDB's register array. If REGNO is -1, |
| 546 | do this for all registers. */ |
| 547 | |
| 548 | void |
| 549 | fill_fpregset (const struct regcache *regcache, |
| 550 | gdb_fpregset_t *fpregsetp, int regno) |
| 551 | { |
| 552 | regcache_collect_regset (&aarch64_linux_fpregset, regcache, |
| 553 | regno, (gdb_byte *) fpregsetp, |
| 554 | AARCH64_LINUX_SIZEOF_FPREGSET); |
| 555 | } |
| 556 | |
| 557 | /* Fill GDB's register array with the floating-point register values |
| 558 | in *FPREGSETP. */ |
| 559 | |
| 560 | void |
| 561 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
| 562 | { |
| 563 | regcache_supply_regset (&aarch64_linux_fpregset, regcache, -1, |
| 564 | (const gdb_byte *) fpregsetp, |
| 565 | AARCH64_LINUX_SIZEOF_FPREGSET); |
| 566 | } |
| 567 | |
| 568 | /* linux_nat_new_fork hook. */ |
| 569 | |
| 570 | void |
| 571 | aarch64_linux_nat_target::low_new_fork (struct lwp_info *parent, |
| 572 | pid_t child_pid) |
| 573 | { |
| 574 | pid_t parent_pid; |
| 575 | struct aarch64_debug_reg_state *parent_state; |
| 576 | struct aarch64_debug_reg_state *child_state; |
| 577 | |
| 578 | /* NULL means no watchpoint has ever been set in the parent. In |
| 579 | that case, there's nothing to do. */ |
| 580 | if (parent->arch_private == NULL) |
| 581 | return; |
| 582 | |
| 583 | /* GDB core assumes the child inherits the watchpoints/hw |
| 584 | breakpoints of the parent, and will remove them all from the |
| 585 | forked off process. Copy the debug registers mirrors into the |
| 586 | new process so that all breakpoints and watchpoints can be |
| 587 | removed together. */ |
| 588 | |
| 589 | parent_pid = parent->ptid.pid (); |
| 590 | parent_state = aarch64_get_debug_reg_state (parent_pid); |
| 591 | child_state = aarch64_get_debug_reg_state (child_pid); |
| 592 | *child_state = *parent_state; |
| 593 | } |
| 594 | \f |
| 595 | |
| 596 | /* Called by libthread_db. Returns a pointer to the thread local |
| 597 | storage (or its descriptor). */ |
| 598 | |
| 599 | ps_err_e |
| 600 | ps_get_thread_area (struct ps_prochandle *ph, |
| 601 | lwpid_t lwpid, int idx, void **base) |
| 602 | { |
| 603 | int is_64bit_p |
| 604 | = (gdbarch_bfd_arch_info (target_gdbarch ())->bits_per_word == 64); |
| 605 | |
| 606 | return aarch64_ps_get_thread_area (ph, lwpid, idx, base, is_64bit_p); |
| 607 | } |
| 608 | \f |
| 609 | |
| 610 | /* Implement the "post_startup_inferior" target_ops method. */ |
| 611 | |
| 612 | void |
| 613 | aarch64_linux_nat_target::post_startup_inferior (ptid_t ptid) |
| 614 | { |
| 615 | low_forget_process (ptid.pid ()); |
| 616 | aarch64_linux_get_debug_reg_capacity (ptid.pid ()); |
| 617 | linux_nat_target::post_startup_inferior (ptid); |
| 618 | } |
| 619 | |
| 620 | /* Implement the "post_attach" target_ops method. */ |
| 621 | |
| 622 | void |
| 623 | aarch64_linux_nat_target::post_attach (int pid) |
| 624 | { |
| 625 | low_forget_process (pid); |
| 626 | /* Set the hardware debug register capacity. If |
| 627 | aarch64_linux_get_debug_reg_capacity is not called |
| 628 | (as it is in aarch64_linux_child_post_startup_inferior) then |
| 629 | software watchpoints will be used instead of hardware |
| 630 | watchpoints when attaching to a target. */ |
| 631 | aarch64_linux_get_debug_reg_capacity (pid); |
| 632 | linux_nat_target::post_attach (pid); |
| 633 | } |
| 634 | |
| 635 | /* Implement the "read_description" target_ops method. */ |
| 636 | |
| 637 | const struct target_desc * |
| 638 | aarch64_linux_nat_target::read_description () |
| 639 | { |
| 640 | int ret, tid; |
| 641 | gdb_byte regbuf[ARM_VFP3_REGS_SIZE]; |
| 642 | struct iovec iovec; |
| 643 | |
| 644 | tid = inferior_ptid.lwp (); |
| 645 | |
| 646 | iovec.iov_base = regbuf; |
| 647 | iovec.iov_len = ARM_VFP3_REGS_SIZE; |
| 648 | |
| 649 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec); |
| 650 | if (ret == 0) |
| 651 | return aarch32_read_description (); |
| 652 | |
| 653 | CORE_ADDR hwcap = linux_get_hwcap (this); |
| 654 | |
| 655 | return aarch64_read_description (aarch64_sve_get_vq (tid), |
| 656 | hwcap & AARCH64_HWCAP_PACA); |
| 657 | } |
| 658 | |
| 659 | /* Convert a native/host siginfo object, into/from the siginfo in the |
| 660 | layout of the inferiors' architecture. Returns true if any |
| 661 | conversion was done; false otherwise. If DIRECTION is 1, then copy |
| 662 | from INF to NATIVE. If DIRECTION is 0, copy from NATIVE to |
| 663 | INF. */ |
| 664 | |
| 665 | bool |
| 666 | aarch64_linux_nat_target::low_siginfo_fixup (siginfo_t *native, gdb_byte *inf, |
| 667 | int direction) |
| 668 | { |
| 669 | struct gdbarch *gdbarch = get_frame_arch (get_current_frame ()); |
| 670 | |
| 671 | /* Is the inferior 32-bit? If so, then do fixup the siginfo |
| 672 | object. */ |
| 673 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
| 674 | { |
| 675 | if (direction == 0) |
| 676 | aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo *) inf, |
| 677 | native); |
| 678 | else |
| 679 | aarch64_siginfo_from_compat_siginfo (native, |
| 680 | (struct compat_siginfo *) inf); |
| 681 | |
| 682 | return true; |
| 683 | } |
| 684 | |
| 685 | return false; |
| 686 | } |
| 687 | |
| 688 | /* Returns the number of hardware watchpoints of type TYPE that we can |
| 689 | set. Value is positive if we can set CNT watchpoints, zero if |
| 690 | setting watchpoints of type TYPE is not supported, and negative if |
| 691 | CNT is more than the maximum number of watchpoints of type TYPE |
| 692 | that we can support. TYPE is one of bp_hardware_watchpoint, |
| 693 | bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint. |
| 694 | CNT is the number of such watchpoints used so far (including this |
| 695 | one). OTHERTYPE is non-zero if other types of watchpoints are |
| 696 | currently enabled. */ |
| 697 | |
| 698 | int |
| 699 | aarch64_linux_nat_target::can_use_hw_breakpoint (enum bptype type, |
| 700 | int cnt, int othertype) |
| 701 | { |
| 702 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint |
| 703 | || type == bp_access_watchpoint || type == bp_watchpoint) |
| 704 | { |
| 705 | if (aarch64_num_wp_regs == 0) |
| 706 | return 0; |
| 707 | } |
| 708 | else if (type == bp_hardware_breakpoint) |
| 709 | { |
| 710 | if (aarch64_num_bp_regs == 0) |
| 711 | return 0; |
| 712 | } |
| 713 | else |
| 714 | gdb_assert_not_reached ("unexpected breakpoint type"); |
| 715 | |
| 716 | /* We always return 1 here because we don't have enough information |
| 717 | about possible overlap of addresses that they want to watch. As an |
| 718 | extreme example, consider the case where all the watchpoints watch |
| 719 | the same address and the same region length: then we can handle a |
| 720 | virtually unlimited number of watchpoints, due to debug register |
| 721 | sharing implemented via reference counts. */ |
| 722 | return 1; |
| 723 | } |
| 724 | |
| 725 | /* Insert a hardware-assisted breakpoint at BP_TGT->reqstd_address. |
| 726 | Return 0 on success, -1 on failure. */ |
| 727 | |
| 728 | int |
| 729 | aarch64_linux_nat_target::insert_hw_breakpoint (struct gdbarch *gdbarch, |
| 730 | struct bp_target_info *bp_tgt) |
| 731 | { |
| 732 | int ret; |
| 733 | CORE_ADDR addr = bp_tgt->placed_address = bp_tgt->reqstd_address; |
| 734 | int len; |
| 735 | const enum target_hw_bp_type type = hw_execute; |
| 736 | struct aarch64_debug_reg_state *state |
| 737 | = aarch64_get_debug_reg_state (inferior_ptid.pid ()); |
| 738 | |
| 739 | gdbarch_breakpoint_from_pc (gdbarch, &addr, &len); |
| 740 | |
| 741 | if (show_debug_regs) |
| 742 | fprintf_unfiltered |
| 743 | (gdb_stdlog, |
| 744 | "insert_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n", |
| 745 | (unsigned long) addr, len); |
| 746 | |
| 747 | ret = aarch64_handle_breakpoint (type, addr, len, 1 /* is_insert */, state); |
| 748 | |
| 749 | if (show_debug_regs) |
| 750 | { |
| 751 | aarch64_show_debug_reg_state (state, |
| 752 | "insert_hw_breakpoint", addr, len, type); |
| 753 | } |
| 754 | |
| 755 | return ret; |
| 756 | } |
| 757 | |
| 758 | /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address. |
| 759 | Return 0 on success, -1 on failure. */ |
| 760 | |
| 761 | int |
| 762 | aarch64_linux_nat_target::remove_hw_breakpoint (struct gdbarch *gdbarch, |
| 763 | struct bp_target_info *bp_tgt) |
| 764 | { |
| 765 | int ret; |
| 766 | CORE_ADDR addr = bp_tgt->placed_address; |
| 767 | int len = 4; |
| 768 | const enum target_hw_bp_type type = hw_execute; |
| 769 | struct aarch64_debug_reg_state *state |
| 770 | = aarch64_get_debug_reg_state (inferior_ptid.pid ()); |
| 771 | |
| 772 | gdbarch_breakpoint_from_pc (gdbarch, &addr, &len); |
| 773 | |
| 774 | if (show_debug_regs) |
| 775 | fprintf_unfiltered |
| 776 | (gdb_stdlog, "remove_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n", |
| 777 | (unsigned long) addr, len); |
| 778 | |
| 779 | ret = aarch64_handle_breakpoint (type, addr, len, 0 /* is_insert */, state); |
| 780 | |
| 781 | if (show_debug_regs) |
| 782 | { |
| 783 | aarch64_show_debug_reg_state (state, |
| 784 | "remove_hw_watchpoint", addr, len, type); |
| 785 | } |
| 786 | |
| 787 | return ret; |
| 788 | } |
| 789 | |
| 790 | /* Implement the "insert_watchpoint" target_ops method. |
| 791 | |
| 792 | Insert a watchpoint to watch a memory region which starts at |
| 793 | address ADDR and whose length is LEN bytes. Watch memory accesses |
| 794 | of the type TYPE. Return 0 on success, -1 on failure. */ |
| 795 | |
| 796 | int |
| 797 | aarch64_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, |
| 798 | enum target_hw_bp_type type, |
| 799 | struct expression *cond) |
| 800 | { |
| 801 | int ret; |
| 802 | struct aarch64_debug_reg_state *state |
| 803 | = aarch64_get_debug_reg_state (inferior_ptid.pid ()); |
| 804 | |
| 805 | if (show_debug_regs) |
| 806 | fprintf_unfiltered (gdb_stdlog, |
| 807 | "insert_watchpoint on entry (addr=0x%08lx, len=%d)\n", |
| 808 | (unsigned long) addr, len); |
| 809 | |
| 810 | gdb_assert (type != hw_execute); |
| 811 | |
| 812 | ret = aarch64_handle_watchpoint (type, addr, len, 1 /* is_insert */, state); |
| 813 | |
| 814 | if (show_debug_regs) |
| 815 | { |
| 816 | aarch64_show_debug_reg_state (state, |
| 817 | "insert_watchpoint", addr, len, type); |
| 818 | } |
| 819 | |
| 820 | return ret; |
| 821 | } |
| 822 | |
| 823 | /* Implement the "remove_watchpoint" target_ops method. |
| 824 | Remove a watchpoint that watched the memory region which starts at |
| 825 | address ADDR, whose length is LEN bytes, and for accesses of the |
| 826 | type TYPE. Return 0 on success, -1 on failure. */ |
| 827 | |
| 828 | int |
| 829 | aarch64_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len, |
| 830 | enum target_hw_bp_type type, |
| 831 | struct expression *cond) |
| 832 | { |
| 833 | int ret; |
| 834 | struct aarch64_debug_reg_state *state |
| 835 | = aarch64_get_debug_reg_state (inferior_ptid.pid ()); |
| 836 | |
| 837 | if (show_debug_regs) |
| 838 | fprintf_unfiltered (gdb_stdlog, |
| 839 | "remove_watchpoint on entry (addr=0x%08lx, len=%d)\n", |
| 840 | (unsigned long) addr, len); |
| 841 | |
| 842 | gdb_assert (type != hw_execute); |
| 843 | |
| 844 | ret = aarch64_handle_watchpoint (type, addr, len, 0 /* is_insert */, state); |
| 845 | |
| 846 | if (show_debug_regs) |
| 847 | { |
| 848 | aarch64_show_debug_reg_state (state, |
| 849 | "remove_watchpoint", addr, len, type); |
| 850 | } |
| 851 | |
| 852 | return ret; |
| 853 | } |
| 854 | |
| 855 | /* Implement the "region_ok_for_hw_watchpoint" target_ops method. */ |
| 856 | |
| 857 | int |
| 858 | aarch64_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) |
| 859 | { |
| 860 | return aarch64_linux_region_ok_for_watchpoint (addr, len); |
| 861 | } |
| 862 | |
| 863 | /* Implement the "stopped_data_address" target_ops method. */ |
| 864 | |
| 865 | bool |
| 866 | aarch64_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p) |
| 867 | { |
| 868 | siginfo_t siginfo; |
| 869 | int i; |
| 870 | struct aarch64_debug_reg_state *state; |
| 871 | |
| 872 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) |
| 873 | return false; |
| 874 | |
| 875 | /* This must be a hardware breakpoint. */ |
| 876 | if (siginfo.si_signo != SIGTRAP |
| 877 | || (siginfo.si_code & 0xffff) != TRAP_HWBKPT) |
| 878 | return false; |
| 879 | |
| 880 | /* Check if the address matches any watched address. */ |
| 881 | state = aarch64_get_debug_reg_state (inferior_ptid.pid ()); |
| 882 | for (i = aarch64_num_wp_regs - 1; i >= 0; --i) |
| 883 | { |
| 884 | const unsigned int offset |
| 885 | = aarch64_watchpoint_offset (state->dr_ctrl_wp[i]); |
| 886 | const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]); |
| 887 | const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr; |
| 888 | const CORE_ADDR addr_watch = state->dr_addr_wp[i] + offset; |
| 889 | const CORE_ADDR addr_watch_aligned = align_down (state->dr_addr_wp[i], 8); |
| 890 | const CORE_ADDR addr_orig = state->dr_addr_orig_wp[i]; |
| 891 | |
| 892 | if (state->dr_ref_count_wp[i] |
| 893 | && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i]) |
| 894 | && addr_trap >= addr_watch_aligned |
| 895 | && addr_trap < addr_watch + len) |
| 896 | { |
| 897 | /* ADDR_TRAP reports the first address of the memory range |
| 898 | accessed by the CPU, regardless of what was the memory |
| 899 | range watched. Thus, a large CPU access that straddles |
| 900 | the ADDR_WATCH..ADDR_WATCH+LEN range may result in an |
| 901 | ADDR_TRAP that is lower than the |
| 902 | ADDR_WATCH..ADDR_WATCH+LEN range. E.g.: |
| 903 | |
| 904 | addr: | 4 | 5 | 6 | 7 | 8 | |
| 905 | |---- range watched ----| |
| 906 | |----------- range accessed ------------| |
| 907 | |
| 908 | In this case, ADDR_TRAP will be 4. |
| 909 | |
| 910 | To match a watchpoint known to GDB core, we must never |
| 911 | report *ADDR_P outside of any ADDR_WATCH..ADDR_WATCH+LEN |
| 912 | range. ADDR_WATCH <= ADDR_TRAP < ADDR_ORIG is a false |
| 913 | positive on kernels older than 4.10. See PR |
| 914 | external/20207. */ |
| 915 | *addr_p = addr_orig; |
| 916 | return true; |
| 917 | } |
| 918 | } |
| 919 | |
| 920 | return false; |
| 921 | } |
| 922 | |
| 923 | /* Implement the "stopped_by_watchpoint" target_ops method. */ |
| 924 | |
| 925 | bool |
| 926 | aarch64_linux_nat_target::stopped_by_watchpoint () |
| 927 | { |
| 928 | CORE_ADDR addr; |
| 929 | |
| 930 | return stopped_data_address (&addr); |
| 931 | } |
| 932 | |
| 933 | /* Implement the "watchpoint_addr_within_range" target_ops method. */ |
| 934 | |
| 935 | bool |
| 936 | aarch64_linux_nat_target::watchpoint_addr_within_range (CORE_ADDR addr, |
| 937 | CORE_ADDR start, int length) |
| 938 | { |
| 939 | return start <= addr && start + length - 1 >= addr; |
| 940 | } |
| 941 | |
| 942 | /* Implement the "can_do_single_step" target_ops method. */ |
| 943 | |
| 944 | int |
| 945 | aarch64_linux_nat_target::can_do_single_step () |
| 946 | { |
| 947 | return 1; |
| 948 | } |
| 949 | |
| 950 | /* Implement the "thread_architecture" target_ops method. */ |
| 951 | |
| 952 | struct gdbarch * |
| 953 | aarch64_linux_nat_target::thread_architecture (ptid_t ptid) |
| 954 | { |
| 955 | /* Return the gdbarch for the current thread. If the vector length has |
| 956 | changed since the last time this was called, then do a further lookup. */ |
| 957 | |
| 958 | uint64_t vq = aarch64_sve_get_vq (ptid.lwp ()); |
| 959 | |
| 960 | /* Find the current gdbarch the same way as process_stratum_target. Only |
| 961 | return it if the current vector length matches the one in the tdep. */ |
| 962 | inferior *inf = find_inferior_ptid (ptid); |
| 963 | gdb_assert (inf != NULL); |
| 964 | if (vq == gdbarch_tdep (inf->gdbarch)->vq) |
| 965 | return inf->gdbarch; |
| 966 | |
| 967 | /* We reach here if the vector length for the thread is different from its |
| 968 | value at process start. Lookup gdbarch via info (potentially creating a |
| 969 | new one), stashing the vector length inside id. Use -1 for when SVE |
| 970 | unavailable, to distinguish from an unset value of 0. */ |
| 971 | struct gdbarch_info info; |
| 972 | gdbarch_info_init (&info); |
| 973 | info.bfd_arch_info = bfd_lookup_arch (bfd_arch_spu, bfd_mach_spu); |
| 974 | info.id = (int *) (vq == 0 ? -1 : vq); |
| 975 | return gdbarch_find_by_info (info); |
| 976 | } |
| 977 | |
| 978 | /* Define AArch64 maintenance commands. */ |
| 979 | |
| 980 | static void |
| 981 | add_show_debug_regs_command (void) |
| 982 | { |
| 983 | /* A maintenance command to enable printing the internal DRi mirror |
| 984 | variables. */ |
| 985 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, |
| 986 | &show_debug_regs, _("\ |
| 987 | Set whether to show variables that mirror the AArch64 debug registers."), _("\ |
| 988 | Show whether to show variables that mirror the AArch64 debug registers."), _("\ |
| 989 | Use \"on\" to enable, \"off\" to disable.\n\ |
| 990 | If enabled, the debug registers values are shown when GDB inserts\n\ |
| 991 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ |
| 992 | triggers a breakpoint or watchpoint."), |
| 993 | NULL, |
| 994 | NULL, |
| 995 | &maintenance_set_cmdlist, |
| 996 | &maintenance_show_cmdlist); |
| 997 | } |
| 998 | |
| 999 | void |
| 1000 | _initialize_aarch64_linux_nat (void) |
| 1001 | { |
| 1002 | add_show_debug_regs_command (); |
| 1003 | |
| 1004 | /* Register the target. */ |
| 1005 | linux_target = &the_aarch64_linux_nat_target; |
| 1006 | add_inf_child_target (&the_aarch64_linux_nat_target); |
| 1007 | } |