| 1 | /* Common target dependent code for GDB on AArch64 systems. |
| 2 | |
| 3 | Copyright (C) 2009-2018 Free Software Foundation, Inc. |
| 4 | Contributed by ARM Ltd. |
| 5 | |
| 6 | This file is part of GDB. |
| 7 | |
| 8 | This program is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU General Public License as published by |
| 10 | the Free Software Foundation; either version 3 of the License, or |
| 11 | (at your option) any later version. |
| 12 | |
| 13 | This program is distributed in the hope that it will be useful, |
| 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | GNU General Public License for more details. |
| 17 | |
| 18 | You should have received a copy of the GNU General Public License |
| 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 20 | |
| 21 | |
| 22 | #ifndef AARCH64_TDEP_H |
| 23 | #define AARCH64_TDEP_H |
| 24 | |
| 25 | #include "arch/aarch64.h" |
| 26 | |
| 27 | /* Forward declarations. */ |
| 28 | struct gdbarch; |
| 29 | struct regset; |
| 30 | |
| 31 | /* AArch64 Dwarf register numbering. */ |
| 32 | #define AARCH64_DWARF_X0 0 |
| 33 | #define AARCH64_DWARF_SP 31 |
| 34 | #define AARCH64_DWARF_V0 64 |
| 35 | #define AARCH64_DWARF_SVE_VG 46 |
| 36 | #define AARCH64_DWARF_SVE_FFR 47 |
| 37 | #define AARCH64_DWARF_SVE_P0 48 |
| 38 | #define AARCH64_DWARF_SVE_Z0 96 |
| 39 | |
| 40 | /* Size of integer registers. */ |
| 41 | #define X_REGISTER_SIZE 8 |
| 42 | #define B_REGISTER_SIZE 1 |
| 43 | #define H_REGISTER_SIZE 2 |
| 44 | #define S_REGISTER_SIZE 4 |
| 45 | #define D_REGISTER_SIZE 8 |
| 46 | #define V_REGISTER_SIZE 16 |
| 47 | #define Q_REGISTER_SIZE 16 |
| 48 | |
| 49 | /* Total number of general (X) registers. */ |
| 50 | #define AARCH64_X_REGISTER_COUNT 32 |
| 51 | /* Total number of D registers. */ |
| 52 | #define AARCH64_D_REGISTER_COUNT 32 |
| 53 | |
| 54 | /* The maximum number of modified instructions generated for one |
| 55 | single-stepped instruction. */ |
| 56 | #define DISPLACED_MODIFIED_INSNS 1 |
| 57 | |
| 58 | /* Target-dependent structure in gdbarch. */ |
| 59 | struct gdbarch_tdep |
| 60 | { |
| 61 | /* Lowest address at which instructions will appear. */ |
| 62 | CORE_ADDR lowest_pc; |
| 63 | |
| 64 | /* Offset to PC value in jump buffer. If this is negative, longjmp |
| 65 | support will be disabled. */ |
| 66 | int jb_pc; |
| 67 | |
| 68 | /* And the size of each entry in the buf. */ |
| 69 | size_t jb_elt_size; |
| 70 | |
| 71 | /* Types for AdvSISD registers. */ |
| 72 | struct type *vnq_type; |
| 73 | struct type *vnd_type; |
| 74 | struct type *vns_type; |
| 75 | struct type *vnh_type; |
| 76 | struct type *vnb_type; |
| 77 | struct type *vnv_type; |
| 78 | |
| 79 | /* syscall record. */ |
| 80 | int (*aarch64_syscall_record) (struct regcache *regcache, unsigned long svc_number); |
| 81 | |
| 82 | /* The VQ value for SVE targets, or zero if SVE is not supported. */ |
| 83 | uint64_t vq; |
| 84 | |
| 85 | /* Returns true if the target supports SVE. */ |
| 86 | bool has_sve () const |
| 87 | { |
| 88 | return vq != 0; |
| 89 | } |
| 90 | }; |
| 91 | |
| 92 | const target_desc *aarch64_read_description (uint64_t vq); |
| 93 | |
| 94 | extern int aarch64_process_record (struct gdbarch *gdbarch, |
| 95 | struct regcache *regcache, CORE_ADDR addr); |
| 96 | |
| 97 | struct displaced_step_closure * |
| 98 | aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch, |
| 99 | CORE_ADDR from, CORE_ADDR to, |
| 100 | struct regcache *regs); |
| 101 | |
| 102 | void aarch64_displaced_step_fixup (struct gdbarch *gdbarch, |
| 103 | struct displaced_step_closure *dsc, |
| 104 | CORE_ADDR from, CORE_ADDR to, |
| 105 | struct regcache *regs); |
| 106 | |
| 107 | int aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch, |
| 108 | struct displaced_step_closure *closure); |
| 109 | |
| 110 | #endif /* aarch64-tdep.h */ |