| 1 | /* GNU/Linux on ARM native support. |
| 2 | Copyright (C) 1999-2019 Free Software Foundation, Inc. |
| 3 | |
| 4 | This file is part of GDB. |
| 5 | |
| 6 | This program is free software; you can redistribute it and/or modify |
| 7 | it under the terms of the GNU General Public License as published by |
| 8 | the Free Software Foundation; either version 3 of the License, or |
| 9 | (at your option) any later version. |
| 10 | |
| 11 | This program is distributed in the hope that it will be useful, |
| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | GNU General Public License for more details. |
| 15 | |
| 16 | You should have received a copy of the GNU General Public License |
| 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 18 | |
| 19 | #include "defs.h" |
| 20 | #include "inferior.h" |
| 21 | #include "gdbcore.h" |
| 22 | #include "regcache.h" |
| 23 | #include "target.h" |
| 24 | #include "linux-nat.h" |
| 25 | #include "target-descriptions.h" |
| 26 | #include "auxv.h" |
| 27 | #include "observable.h" |
| 28 | #include "gdbthread.h" |
| 29 | |
| 30 | #include "arm-tdep.h" |
| 31 | #include "arm-linux-tdep.h" |
| 32 | #include "aarch32-linux-nat.h" |
| 33 | |
| 34 | #include <elf/common.h> |
| 35 | #include <sys/user.h> |
| 36 | #include "nat/gdb_ptrace.h" |
| 37 | #include <sys/utsname.h> |
| 38 | #include <sys/procfs.h> |
| 39 | |
| 40 | #include "nat/linux-ptrace.h" |
| 41 | #include "linux-tdep.h" |
| 42 | |
| 43 | /* Prototypes for supply_gregset etc. */ |
| 44 | #include "gregset.h" |
| 45 | |
| 46 | /* Defines ps_err_e, struct ps_prochandle. */ |
| 47 | #include "gdb_proc_service.h" |
| 48 | |
| 49 | #ifndef PTRACE_GET_THREAD_AREA |
| 50 | #define PTRACE_GET_THREAD_AREA 22 |
| 51 | #endif |
| 52 | |
| 53 | #ifndef PTRACE_GETWMMXREGS |
| 54 | #define PTRACE_GETWMMXREGS 18 |
| 55 | #define PTRACE_SETWMMXREGS 19 |
| 56 | #endif |
| 57 | |
| 58 | #ifndef PTRACE_GETVFPREGS |
| 59 | #define PTRACE_GETVFPREGS 27 |
| 60 | #define PTRACE_SETVFPREGS 28 |
| 61 | #endif |
| 62 | |
| 63 | #ifndef PTRACE_GETHBPREGS |
| 64 | #define PTRACE_GETHBPREGS 29 |
| 65 | #define PTRACE_SETHBPREGS 30 |
| 66 | #endif |
| 67 | |
| 68 | extern int arm_apcs_32; |
| 69 | |
| 70 | class arm_linux_nat_target final : public linux_nat_target |
| 71 | { |
| 72 | public: |
| 73 | /* Add our register access methods. */ |
| 74 | void fetch_registers (struct regcache *, int) override; |
| 75 | void store_registers (struct regcache *, int) override; |
| 76 | |
| 77 | /* Add our hardware breakpoint and watchpoint implementation. */ |
| 78 | int can_use_hw_breakpoint (enum bptype, int, int) override; |
| 79 | |
| 80 | int insert_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; |
| 81 | |
| 82 | int remove_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; |
| 83 | |
| 84 | int region_ok_for_hw_watchpoint (CORE_ADDR, int) override; |
| 85 | |
| 86 | int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, |
| 87 | struct expression *) override; |
| 88 | |
| 89 | int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, |
| 90 | struct expression *) override; |
| 91 | bool stopped_by_watchpoint () override; |
| 92 | |
| 93 | bool stopped_data_address (CORE_ADDR *) override; |
| 94 | |
| 95 | bool watchpoint_addr_within_range (CORE_ADDR, CORE_ADDR, int) override; |
| 96 | |
| 97 | const struct target_desc *read_description () override; |
| 98 | |
| 99 | /* Override linux_nat_target low methods. */ |
| 100 | |
| 101 | /* Handle thread creation and exit. */ |
| 102 | void low_new_thread (struct lwp_info *lp) override; |
| 103 | void low_delete_thread (struct arch_lwp_info *lp) override; |
| 104 | void low_prepare_to_resume (struct lwp_info *lp) override; |
| 105 | |
| 106 | /* Handle process creation and exit. */ |
| 107 | void low_new_fork (struct lwp_info *parent, pid_t child_pid) override; |
| 108 | void low_forget_process (pid_t pid) override; |
| 109 | }; |
| 110 | |
| 111 | static arm_linux_nat_target the_arm_linux_nat_target; |
| 112 | |
| 113 | /* Get the whole floating point state of the process and store it |
| 114 | into regcache. */ |
| 115 | |
| 116 | static void |
| 117 | fetch_fpregs (struct regcache *regcache) |
| 118 | { |
| 119 | int ret, regno, tid; |
| 120 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
| 121 | |
| 122 | /* Get the thread id for the ptrace call. */ |
| 123 | tid = regcache->ptid ().lwp (); |
| 124 | |
| 125 | /* Read the floating point state. */ |
| 126 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
| 127 | { |
| 128 | struct iovec iov; |
| 129 | |
| 130 | iov.iov_base = &fp; |
| 131 | iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; |
| 132 | |
| 133 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); |
| 134 | } |
| 135 | else |
| 136 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); |
| 137 | |
| 138 | if (ret < 0) |
| 139 | perror_with_name (_("Unable to fetch the floating point registers.")); |
| 140 | |
| 141 | /* Fetch fpsr. */ |
| 142 | regcache->raw_supply (ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET); |
| 143 | |
| 144 | /* Fetch the floating point registers. */ |
| 145 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
| 146 | supply_nwfpe_register (regcache, regno, fp); |
| 147 | } |
| 148 | |
| 149 | /* Save the whole floating point state of the process using |
| 150 | the contents from regcache. */ |
| 151 | |
| 152 | static void |
| 153 | store_fpregs (const struct regcache *regcache) |
| 154 | { |
| 155 | int ret, regno, tid; |
| 156 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
| 157 | |
| 158 | /* Get the thread id for the ptrace call. */ |
| 159 | tid = regcache->ptid ().lwp (); |
| 160 | |
| 161 | /* Read the floating point state. */ |
| 162 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
| 163 | { |
| 164 | elf_fpregset_t fpregs; |
| 165 | struct iovec iov; |
| 166 | |
| 167 | iov.iov_base = &fpregs; |
| 168 | iov.iov_len = sizeof (fpregs); |
| 169 | |
| 170 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); |
| 171 | } |
| 172 | else |
| 173 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); |
| 174 | |
| 175 | if (ret < 0) |
| 176 | perror_with_name (_("Unable to fetch the floating point registers.")); |
| 177 | |
| 178 | /* Store fpsr. */ |
| 179 | if (REG_VALID == regcache->get_register_status (ARM_FPS_REGNUM)) |
| 180 | regcache->raw_collect (ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET); |
| 181 | |
| 182 | /* Store the floating point registers. */ |
| 183 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
| 184 | if (REG_VALID == regcache->get_register_status (regno)) |
| 185 | collect_nwfpe_register (regcache, regno, fp); |
| 186 | |
| 187 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
| 188 | { |
| 189 | struct iovec iov; |
| 190 | |
| 191 | iov.iov_base = &fp; |
| 192 | iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; |
| 193 | |
| 194 | ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iov); |
| 195 | } |
| 196 | else |
| 197 | ret = ptrace (PTRACE_SETFPREGS, tid, 0, fp); |
| 198 | |
| 199 | if (ret < 0) |
| 200 | perror_with_name (_("Unable to store floating point registers.")); |
| 201 | } |
| 202 | |
| 203 | /* Fetch all general registers of the process and store into |
| 204 | regcache. */ |
| 205 | |
| 206 | static void |
| 207 | fetch_regs (struct regcache *regcache) |
| 208 | { |
| 209 | int ret, tid; |
| 210 | elf_gregset_t regs; |
| 211 | |
| 212 | /* Get the thread id for the ptrace call. */ |
| 213 | tid = regcache->ptid ().lwp (); |
| 214 | |
| 215 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
| 216 | { |
| 217 | struct iovec iov; |
| 218 | |
| 219 | iov.iov_base = ®s; |
| 220 | iov.iov_len = sizeof (regs); |
| 221 | |
| 222 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); |
| 223 | } |
| 224 | else |
| 225 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); |
| 226 | |
| 227 | if (ret < 0) |
| 228 | perror_with_name (_("Unable to fetch general registers.")); |
| 229 | |
| 230 | aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, arm_apcs_32); |
| 231 | } |
| 232 | |
| 233 | static void |
| 234 | store_regs (const struct regcache *regcache) |
| 235 | { |
| 236 | int ret, tid; |
| 237 | elf_gregset_t regs; |
| 238 | |
| 239 | /* Get the thread id for the ptrace call. */ |
| 240 | tid = regcache->ptid ().lwp (); |
| 241 | |
| 242 | /* Fetch the general registers. */ |
| 243 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
| 244 | { |
| 245 | struct iovec iov; |
| 246 | |
| 247 | iov.iov_base = ®s; |
| 248 | iov.iov_len = sizeof (regs); |
| 249 | |
| 250 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); |
| 251 | } |
| 252 | else |
| 253 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); |
| 254 | |
| 255 | if (ret < 0) |
| 256 | perror_with_name (_("Unable to fetch general registers.")); |
| 257 | |
| 258 | aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, arm_apcs_32); |
| 259 | |
| 260 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
| 261 | { |
| 262 | struct iovec iov; |
| 263 | |
| 264 | iov.iov_base = ®s; |
| 265 | iov.iov_len = sizeof (regs); |
| 266 | |
| 267 | ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iov); |
| 268 | } |
| 269 | else |
| 270 | ret = ptrace (PTRACE_SETREGS, tid, 0, ®s); |
| 271 | |
| 272 | if (ret < 0) |
| 273 | perror_with_name (_("Unable to store general registers.")); |
| 274 | } |
| 275 | |
| 276 | /* Fetch all WMMX registers of the process and store into |
| 277 | regcache. */ |
| 278 | |
| 279 | #define IWMMXT_REGS_SIZE (16 * 8 + 6 * 4) |
| 280 | |
| 281 | static void |
| 282 | fetch_wmmx_regs (struct regcache *regcache) |
| 283 | { |
| 284 | char regbuf[IWMMXT_REGS_SIZE]; |
| 285 | int ret, regno, tid; |
| 286 | |
| 287 | /* Get the thread id for the ptrace call. */ |
| 288 | tid = regcache->ptid ().lwp (); |
| 289 | |
| 290 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); |
| 291 | if (ret < 0) |
| 292 | perror_with_name (_("Unable to fetch WMMX registers.")); |
| 293 | |
| 294 | for (regno = 0; regno < 16; regno++) |
| 295 | regcache->raw_supply (regno + ARM_WR0_REGNUM, ®buf[regno * 8]); |
| 296 | |
| 297 | for (regno = 0; regno < 2; regno++) |
| 298 | regcache->raw_supply (regno + ARM_WCSSF_REGNUM, |
| 299 | ®buf[16 * 8 + regno * 4]); |
| 300 | |
| 301 | for (regno = 0; regno < 4; regno++) |
| 302 | regcache->raw_supply (regno + ARM_WCGR0_REGNUM, |
| 303 | ®buf[16 * 8 + 2 * 4 + regno * 4]); |
| 304 | } |
| 305 | |
| 306 | static void |
| 307 | store_wmmx_regs (const struct regcache *regcache) |
| 308 | { |
| 309 | char regbuf[IWMMXT_REGS_SIZE]; |
| 310 | int ret, regno, tid; |
| 311 | |
| 312 | /* Get the thread id for the ptrace call. */ |
| 313 | tid = regcache->ptid ().lwp (); |
| 314 | |
| 315 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); |
| 316 | if (ret < 0) |
| 317 | perror_with_name (_("Unable to fetch WMMX registers.")); |
| 318 | |
| 319 | for (regno = 0; regno < 16; regno++) |
| 320 | if (REG_VALID == regcache->get_register_status (regno + ARM_WR0_REGNUM)) |
| 321 | regcache->raw_collect (regno + ARM_WR0_REGNUM, ®buf[regno * 8]); |
| 322 | |
| 323 | for (regno = 0; regno < 2; regno++) |
| 324 | if (REG_VALID == regcache->get_register_status (regno + ARM_WCSSF_REGNUM)) |
| 325 | regcache->raw_collect (regno + ARM_WCSSF_REGNUM, |
| 326 | ®buf[16 * 8 + regno * 4]); |
| 327 | |
| 328 | for (regno = 0; regno < 4; regno++) |
| 329 | if (REG_VALID == regcache->get_register_status (regno + ARM_WCGR0_REGNUM)) |
| 330 | regcache->raw_collect (regno + ARM_WCGR0_REGNUM, |
| 331 | ®buf[16 * 8 + 2 * 4 + regno * 4]); |
| 332 | |
| 333 | ret = ptrace (PTRACE_SETWMMXREGS, tid, 0, regbuf); |
| 334 | |
| 335 | if (ret < 0) |
| 336 | perror_with_name (_("Unable to store WMMX registers.")); |
| 337 | } |
| 338 | |
| 339 | static void |
| 340 | fetch_vfp_regs (struct regcache *regcache) |
| 341 | { |
| 342 | gdb_byte regbuf[VFP_REGS_SIZE]; |
| 343 | int ret, tid; |
| 344 | struct gdbarch *gdbarch = regcache->arch (); |
| 345 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 346 | |
| 347 | /* Get the thread id for the ptrace call. */ |
| 348 | tid = regcache->ptid ().lwp (); |
| 349 | |
| 350 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
| 351 | { |
| 352 | struct iovec iov; |
| 353 | |
| 354 | iov.iov_base = regbuf; |
| 355 | iov.iov_len = VFP_REGS_SIZE; |
| 356 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); |
| 357 | } |
| 358 | else |
| 359 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); |
| 360 | |
| 361 | if (ret < 0) |
| 362 | perror_with_name (_("Unable to fetch VFP registers.")); |
| 363 | |
| 364 | aarch32_vfp_regcache_supply (regcache, regbuf, |
| 365 | tdep->vfp_register_count); |
| 366 | } |
| 367 | |
| 368 | static void |
| 369 | store_vfp_regs (const struct regcache *regcache) |
| 370 | { |
| 371 | gdb_byte regbuf[VFP_REGS_SIZE]; |
| 372 | int ret, tid; |
| 373 | struct gdbarch *gdbarch = regcache->arch (); |
| 374 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 375 | |
| 376 | /* Get the thread id for the ptrace call. */ |
| 377 | tid = regcache->ptid ().lwp (); |
| 378 | |
| 379 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
| 380 | { |
| 381 | struct iovec iov; |
| 382 | |
| 383 | iov.iov_base = regbuf; |
| 384 | iov.iov_len = VFP_REGS_SIZE; |
| 385 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); |
| 386 | } |
| 387 | else |
| 388 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); |
| 389 | |
| 390 | if (ret < 0) |
| 391 | perror_with_name (_("Unable to fetch VFP registers (for update).")); |
| 392 | |
| 393 | aarch32_vfp_regcache_collect (regcache, regbuf, |
| 394 | tdep->vfp_register_count); |
| 395 | |
| 396 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
| 397 | { |
| 398 | struct iovec iov; |
| 399 | |
| 400 | iov.iov_base = regbuf; |
| 401 | iov.iov_len = VFP_REGS_SIZE; |
| 402 | ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iov); |
| 403 | } |
| 404 | else |
| 405 | ret = ptrace (PTRACE_SETVFPREGS, tid, 0, regbuf); |
| 406 | |
| 407 | if (ret < 0) |
| 408 | perror_with_name (_("Unable to store VFP registers.")); |
| 409 | } |
| 410 | |
| 411 | /* Fetch registers from the child process. Fetch all registers if |
| 412 | regno == -1, otherwise fetch all general registers or all floating |
| 413 | point registers depending upon the value of regno. */ |
| 414 | |
| 415 | void |
| 416 | arm_linux_nat_target::fetch_registers (struct regcache *regcache, int regno) |
| 417 | { |
| 418 | struct gdbarch *gdbarch = regcache->arch (); |
| 419 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 420 | |
| 421 | if (-1 == regno) |
| 422 | { |
| 423 | fetch_regs (regcache); |
| 424 | if (tdep->have_wmmx_registers) |
| 425 | fetch_wmmx_regs (regcache); |
| 426 | if (tdep->vfp_register_count > 0) |
| 427 | fetch_vfp_regs (regcache); |
| 428 | if (tdep->have_fpa_registers) |
| 429 | fetch_fpregs (regcache); |
| 430 | } |
| 431 | else |
| 432 | { |
| 433 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
| 434 | fetch_regs (regcache); |
| 435 | else if (regno >= ARM_F0_REGNUM && regno <= ARM_FPS_REGNUM) |
| 436 | fetch_fpregs (regcache); |
| 437 | else if (tdep->have_wmmx_registers |
| 438 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
| 439 | fetch_wmmx_regs (regcache); |
| 440 | else if (tdep->vfp_register_count > 0 |
| 441 | && regno >= ARM_D0_REGNUM |
| 442 | && (regno < ARM_D0_REGNUM + tdep->vfp_register_count |
| 443 | || regno == ARM_FPSCR_REGNUM)) |
| 444 | fetch_vfp_regs (regcache); |
| 445 | } |
| 446 | } |
| 447 | |
| 448 | /* Store registers back into the inferior. Store all registers if |
| 449 | regno == -1, otherwise store all general registers or all floating |
| 450 | point registers depending upon the value of regno. */ |
| 451 | |
| 452 | void |
| 453 | arm_linux_nat_target::store_registers (struct regcache *regcache, int regno) |
| 454 | { |
| 455 | struct gdbarch *gdbarch = regcache->arch (); |
| 456 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 457 | |
| 458 | if (-1 == regno) |
| 459 | { |
| 460 | store_regs (regcache); |
| 461 | if (tdep->have_wmmx_registers) |
| 462 | store_wmmx_regs (regcache); |
| 463 | if (tdep->vfp_register_count > 0) |
| 464 | store_vfp_regs (regcache); |
| 465 | if (tdep->have_fpa_registers) |
| 466 | store_fpregs (regcache); |
| 467 | } |
| 468 | else |
| 469 | { |
| 470 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
| 471 | store_regs (regcache); |
| 472 | else if ((regno >= ARM_F0_REGNUM) && (regno <= ARM_FPS_REGNUM)) |
| 473 | store_fpregs (regcache); |
| 474 | else if (tdep->have_wmmx_registers |
| 475 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
| 476 | store_wmmx_regs (regcache); |
| 477 | else if (tdep->vfp_register_count > 0 |
| 478 | && regno >= ARM_D0_REGNUM |
| 479 | && (regno < ARM_D0_REGNUM + tdep->vfp_register_count |
| 480 | || regno == ARM_FPSCR_REGNUM)) |
| 481 | store_vfp_regs (regcache); |
| 482 | } |
| 483 | } |
| 484 | |
| 485 | /* Wrapper functions for the standard regset handling, used by |
| 486 | thread debugging. */ |
| 487 | |
| 488 | void |
| 489 | fill_gregset (const struct regcache *regcache, |
| 490 | gdb_gregset_t *gregsetp, int regno) |
| 491 | { |
| 492 | arm_linux_collect_gregset (NULL, regcache, regno, gregsetp, 0); |
| 493 | } |
| 494 | |
| 495 | void |
| 496 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
| 497 | { |
| 498 | arm_linux_supply_gregset (NULL, regcache, -1, gregsetp, 0); |
| 499 | } |
| 500 | |
| 501 | void |
| 502 | fill_fpregset (const struct regcache *regcache, |
| 503 | gdb_fpregset_t *fpregsetp, int regno) |
| 504 | { |
| 505 | arm_linux_collect_nwfpe (NULL, regcache, regno, fpregsetp, 0); |
| 506 | } |
| 507 | |
| 508 | /* Fill GDB's register array with the floating-point register values |
| 509 | in *fpregsetp. */ |
| 510 | |
| 511 | void |
| 512 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
| 513 | { |
| 514 | arm_linux_supply_nwfpe (NULL, regcache, -1, fpregsetp, 0); |
| 515 | } |
| 516 | |
| 517 | /* Fetch the thread-local storage pointer for libthread_db. */ |
| 518 | |
| 519 | ps_err_e |
| 520 | ps_get_thread_area (struct ps_prochandle *ph, |
| 521 | lwpid_t lwpid, int idx, void **base) |
| 522 | { |
| 523 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) |
| 524 | return PS_ERR; |
| 525 | |
| 526 | /* IDX is the bias from the thread pointer to the beginning of the |
| 527 | thread descriptor. It has to be subtracted due to implementation |
| 528 | quirks in libthread_db. */ |
| 529 | *base = (void *) ((char *)*base - idx); |
| 530 | |
| 531 | return PS_OK; |
| 532 | } |
| 533 | |
| 534 | const struct target_desc * |
| 535 | arm_linux_nat_target::read_description () |
| 536 | { |
| 537 | CORE_ADDR arm_hwcap = linux_get_hwcap (this); |
| 538 | |
| 539 | if (have_ptrace_getregset == TRIBOOL_UNKNOWN) |
| 540 | { |
| 541 | elf_gregset_t gpregs; |
| 542 | struct iovec iov; |
| 543 | int tid = inferior_ptid.lwp (); |
| 544 | |
| 545 | iov.iov_base = &gpregs; |
| 546 | iov.iov_len = sizeof (gpregs); |
| 547 | |
| 548 | /* Check if PTRACE_GETREGSET works. */ |
| 549 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) < 0) |
| 550 | have_ptrace_getregset = TRIBOOL_FALSE; |
| 551 | else |
| 552 | have_ptrace_getregset = TRIBOOL_TRUE; |
| 553 | } |
| 554 | |
| 555 | if (arm_hwcap & HWCAP_IWMMXT) |
| 556 | return tdesc_arm_with_iwmmxt; |
| 557 | |
| 558 | if (arm_hwcap & HWCAP_VFP) |
| 559 | { |
| 560 | int pid; |
| 561 | char *buf; |
| 562 | const struct target_desc * result = NULL; |
| 563 | |
| 564 | /* NEON implies VFPv3-D32 or no-VFP unit. Say that we only support |
| 565 | Neon with VFPv3-D32. */ |
| 566 | if (arm_hwcap & HWCAP_NEON) |
| 567 | result = tdesc_arm_with_neon; |
| 568 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) |
| 569 | result = tdesc_arm_with_vfpv3; |
| 570 | else |
| 571 | result = tdesc_arm_with_vfpv2; |
| 572 | |
| 573 | /* Now make sure that the kernel supports reading these |
| 574 | registers. Support was added in 2.6.30. */ |
| 575 | pid = inferior_ptid.lwp (); |
| 576 | errno = 0; |
| 577 | buf = (char *) alloca (VFP_REGS_SIZE); |
| 578 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 |
| 579 | && errno == EIO) |
| 580 | result = NULL; |
| 581 | |
| 582 | return result; |
| 583 | } |
| 584 | |
| 585 | return this->beneath ()->read_description (); |
| 586 | } |
| 587 | |
| 588 | /* Information describing the hardware breakpoint capabilities. */ |
| 589 | struct arm_linux_hwbp_cap |
| 590 | { |
| 591 | gdb_byte arch; |
| 592 | gdb_byte max_wp_length; |
| 593 | gdb_byte wp_count; |
| 594 | gdb_byte bp_count; |
| 595 | }; |
| 596 | |
| 597 | /* Since we cannot dynamically allocate subfields of arm_linux_process_info, |
| 598 | assume a maximum number of supported break-/watchpoints. */ |
| 599 | #define MAX_BPTS 16 |
| 600 | #define MAX_WPTS 16 |
| 601 | |
| 602 | /* Get hold of the Hardware Breakpoint information for the target we are |
| 603 | attached to. Returns NULL if the kernel doesn't support Hardware |
| 604 | breakpoints at all, or a pointer to the information structure. */ |
| 605 | static const struct arm_linux_hwbp_cap * |
| 606 | arm_linux_get_hwbp_cap (void) |
| 607 | { |
| 608 | /* The info structure we return. */ |
| 609 | static struct arm_linux_hwbp_cap info; |
| 610 | |
| 611 | /* Is INFO in a good state? -1 means that no attempt has been made to |
| 612 | initialize INFO; 0 means an attempt has been made, but it failed; 1 |
| 613 | means INFO is in an initialized state. */ |
| 614 | static int available = -1; |
| 615 | |
| 616 | if (available == -1) |
| 617 | { |
| 618 | int tid; |
| 619 | unsigned int val; |
| 620 | |
| 621 | tid = inferior_ptid.lwp (); |
| 622 | if (ptrace (PTRACE_GETHBPREGS, tid, 0, &val) < 0) |
| 623 | available = 0; |
| 624 | else |
| 625 | { |
| 626 | info.arch = (gdb_byte)((val >> 24) & 0xff); |
| 627 | info.max_wp_length = (gdb_byte)((val >> 16) & 0xff); |
| 628 | info.wp_count = (gdb_byte)((val >> 8) & 0xff); |
| 629 | info.bp_count = (gdb_byte)(val & 0xff); |
| 630 | |
| 631 | if (info.wp_count > MAX_WPTS) |
| 632 | { |
| 633 | warning (_("arm-linux-gdb supports %d hardware watchpoints but target \ |
| 634 | supports %d"), MAX_WPTS, info.wp_count); |
| 635 | info.wp_count = MAX_WPTS; |
| 636 | } |
| 637 | |
| 638 | if (info.bp_count > MAX_BPTS) |
| 639 | { |
| 640 | warning (_("arm-linux-gdb supports %d hardware breakpoints but target \ |
| 641 | supports %d"), MAX_BPTS, info.bp_count); |
| 642 | info.bp_count = MAX_BPTS; |
| 643 | } |
| 644 | available = (info.arch != 0); |
| 645 | } |
| 646 | } |
| 647 | |
| 648 | return available == 1 ? &info : NULL; |
| 649 | } |
| 650 | |
| 651 | /* How many hardware breakpoints are available? */ |
| 652 | static int |
| 653 | arm_linux_get_hw_breakpoint_count (void) |
| 654 | { |
| 655 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); |
| 656 | return cap != NULL ? cap->bp_count : 0; |
| 657 | } |
| 658 | |
| 659 | /* How many hardware watchpoints are available? */ |
| 660 | static int |
| 661 | arm_linux_get_hw_watchpoint_count (void) |
| 662 | { |
| 663 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); |
| 664 | return cap != NULL ? cap->wp_count : 0; |
| 665 | } |
| 666 | |
| 667 | /* Have we got a free break-/watch-point available for use? Returns -1 if |
| 668 | there is not an appropriate resource available, otherwise returns 1. */ |
| 669 | int |
| 670 | arm_linux_nat_target::can_use_hw_breakpoint (enum bptype type, |
| 671 | int cnt, int ot) |
| 672 | { |
| 673 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint |
| 674 | || type == bp_access_watchpoint || type == bp_watchpoint) |
| 675 | { |
| 676 | int count = arm_linux_get_hw_watchpoint_count (); |
| 677 | |
| 678 | if (count == 0) |
| 679 | return 0; |
| 680 | else if (cnt + ot > count) |
| 681 | return -1; |
| 682 | } |
| 683 | else if (type == bp_hardware_breakpoint) |
| 684 | { |
| 685 | int count = arm_linux_get_hw_breakpoint_count (); |
| 686 | |
| 687 | if (count == 0) |
| 688 | return 0; |
| 689 | else if (cnt > count) |
| 690 | return -1; |
| 691 | } |
| 692 | else |
| 693 | gdb_assert_not_reached ("unknown breakpoint type"); |
| 694 | |
| 695 | return 1; |
| 696 | } |
| 697 | |
| 698 | /* Enum describing the different types of ARM hardware break-/watch-points. */ |
| 699 | typedef enum |
| 700 | { |
| 701 | arm_hwbp_break = 0, |
| 702 | arm_hwbp_load = 1, |
| 703 | arm_hwbp_store = 2, |
| 704 | arm_hwbp_access = 3 |
| 705 | } arm_hwbp_type; |
| 706 | |
| 707 | /* Type describing an ARM Hardware Breakpoint Control register value. */ |
| 708 | typedef unsigned int arm_hwbp_control_t; |
| 709 | |
| 710 | /* Structure used to keep track of hardware break-/watch-points. */ |
| 711 | struct arm_linux_hw_breakpoint |
| 712 | { |
| 713 | /* Address to break on, or being watched. */ |
| 714 | unsigned int address; |
| 715 | /* Control register for break-/watch- point. */ |
| 716 | arm_hwbp_control_t control; |
| 717 | }; |
| 718 | |
| 719 | /* Structure containing arrays of per process hardware break-/watchpoints |
| 720 | for caching address and control information. |
| 721 | |
| 722 | The Linux ptrace interface to hardware break-/watch-points presents the |
| 723 | values in a vector centred around 0 (which is used fo generic information). |
| 724 | Positive indicies refer to breakpoint addresses/control registers, negative |
| 725 | indices to watchpoint addresses/control registers. |
| 726 | |
| 727 | The Linux vector is indexed as follows: |
| 728 | -((i << 1) + 2): Control register for watchpoint i. |
| 729 | -((i << 1) + 1): Address register for watchpoint i. |
| 730 | 0: Information register. |
| 731 | ((i << 1) + 1): Address register for breakpoint i. |
| 732 | ((i << 1) + 2): Control register for breakpoint i. |
| 733 | |
| 734 | This structure is used as a per-thread cache of the state stored by the |
| 735 | kernel, so that we don't need to keep calling into the kernel to find a |
| 736 | free breakpoint. |
| 737 | |
| 738 | We treat break-/watch-points with their enable bit clear as being deleted. |
| 739 | */ |
| 740 | struct arm_linux_debug_reg_state |
| 741 | { |
| 742 | /* Hardware breakpoints for this process. */ |
| 743 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; |
| 744 | /* Hardware watchpoints for this process. */ |
| 745 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; |
| 746 | }; |
| 747 | |
| 748 | /* Per-process arch-specific data we want to keep. */ |
| 749 | struct arm_linux_process_info |
| 750 | { |
| 751 | /* Linked list. */ |
| 752 | struct arm_linux_process_info *next; |
| 753 | /* The process identifier. */ |
| 754 | pid_t pid; |
| 755 | /* Hardware break-/watchpoints state information. */ |
| 756 | struct arm_linux_debug_reg_state state; |
| 757 | |
| 758 | }; |
| 759 | |
| 760 | /* Per-thread arch-specific data we want to keep. */ |
| 761 | struct arch_lwp_info |
| 762 | { |
| 763 | /* Non-zero if our copy differs from what's recorded in the thread. */ |
| 764 | char bpts_changed[MAX_BPTS]; |
| 765 | char wpts_changed[MAX_WPTS]; |
| 766 | }; |
| 767 | |
| 768 | static struct arm_linux_process_info *arm_linux_process_list = NULL; |
| 769 | |
| 770 | /* Find process data for process PID. */ |
| 771 | |
| 772 | static struct arm_linux_process_info * |
| 773 | arm_linux_find_process_pid (pid_t pid) |
| 774 | { |
| 775 | struct arm_linux_process_info *proc; |
| 776 | |
| 777 | for (proc = arm_linux_process_list; proc; proc = proc->next) |
| 778 | if (proc->pid == pid) |
| 779 | return proc; |
| 780 | |
| 781 | return NULL; |
| 782 | } |
| 783 | |
| 784 | /* Add process data for process PID. Returns newly allocated info |
| 785 | object. */ |
| 786 | |
| 787 | static struct arm_linux_process_info * |
| 788 | arm_linux_add_process (pid_t pid) |
| 789 | { |
| 790 | struct arm_linux_process_info *proc; |
| 791 | |
| 792 | proc = XCNEW (struct arm_linux_process_info); |
| 793 | proc->pid = pid; |
| 794 | |
| 795 | proc->next = arm_linux_process_list; |
| 796 | arm_linux_process_list = proc; |
| 797 | |
| 798 | return proc; |
| 799 | } |
| 800 | |
| 801 | /* Get data specific info for process PID, creating it if necessary. |
| 802 | Never returns NULL. */ |
| 803 | |
| 804 | static struct arm_linux_process_info * |
| 805 | arm_linux_process_info_get (pid_t pid) |
| 806 | { |
| 807 | struct arm_linux_process_info *proc; |
| 808 | |
| 809 | proc = arm_linux_find_process_pid (pid); |
| 810 | if (proc == NULL) |
| 811 | proc = arm_linux_add_process (pid); |
| 812 | |
| 813 | return proc; |
| 814 | } |
| 815 | |
| 816 | /* Called whenever GDB is no longer debugging process PID. It deletes |
| 817 | data structures that keep track of debug register state. */ |
| 818 | |
| 819 | void |
| 820 | arm_linux_nat_target::low_forget_process (pid_t pid) |
| 821 | { |
| 822 | struct arm_linux_process_info *proc, **proc_link; |
| 823 | |
| 824 | proc = arm_linux_process_list; |
| 825 | proc_link = &arm_linux_process_list; |
| 826 | |
| 827 | while (proc != NULL) |
| 828 | { |
| 829 | if (proc->pid == pid) |
| 830 | { |
| 831 | *proc_link = proc->next; |
| 832 | |
| 833 | xfree (proc); |
| 834 | return; |
| 835 | } |
| 836 | |
| 837 | proc_link = &proc->next; |
| 838 | proc = *proc_link; |
| 839 | } |
| 840 | } |
| 841 | |
| 842 | /* Get hardware break-/watchpoint state for process PID. */ |
| 843 | |
| 844 | static struct arm_linux_debug_reg_state * |
| 845 | arm_linux_get_debug_reg_state (pid_t pid) |
| 846 | { |
| 847 | return &arm_linux_process_info_get (pid)->state; |
| 848 | } |
| 849 | |
| 850 | /* Initialize an ARM hardware break-/watch-point control register value. |
| 851 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the |
| 852 | type of break-/watch-point; ENABLE indicates whether the point is enabled. |
| 853 | */ |
| 854 | static arm_hwbp_control_t |
| 855 | arm_hwbp_control_initialize (unsigned byte_address_select, |
| 856 | arm_hwbp_type hwbp_type, |
| 857 | int enable) |
| 858 | { |
| 859 | gdb_assert ((byte_address_select & ~0xffU) == 0); |
| 860 | gdb_assert (hwbp_type != arm_hwbp_break |
| 861 | || ((byte_address_select & 0xfU) != 0)); |
| 862 | |
| 863 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; |
| 864 | } |
| 865 | |
| 866 | /* Does the breakpoint control value CONTROL have the enable bit set? */ |
| 867 | static int |
| 868 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) |
| 869 | { |
| 870 | return control & 0x1; |
| 871 | } |
| 872 | |
| 873 | /* Change a breakpoint control word so that it is in the disabled state. */ |
| 874 | static arm_hwbp_control_t |
| 875 | arm_hwbp_control_disable (arm_hwbp_control_t control) |
| 876 | { |
| 877 | return control & ~0x1; |
| 878 | } |
| 879 | |
| 880 | /* Initialise the hardware breakpoint structure P. The breakpoint will be |
| 881 | enabled, and will point to the placed address of BP_TGT. */ |
| 882 | static void |
| 883 | arm_linux_hw_breakpoint_initialize (struct gdbarch *gdbarch, |
| 884 | struct bp_target_info *bp_tgt, |
| 885 | struct arm_linux_hw_breakpoint *p) |
| 886 | { |
| 887 | unsigned mask; |
| 888 | CORE_ADDR address = bp_tgt->placed_address = bp_tgt->reqstd_address; |
| 889 | |
| 890 | /* We have to create a mask for the control register which says which bits |
| 891 | of the word pointed to by address to break on. */ |
| 892 | if (arm_pc_is_thumb (gdbarch, address)) |
| 893 | { |
| 894 | mask = 0x3; |
| 895 | address &= ~1; |
| 896 | } |
| 897 | else |
| 898 | { |
| 899 | mask = 0xf; |
| 900 | address &= ~3; |
| 901 | } |
| 902 | |
| 903 | p->address = (unsigned int) address; |
| 904 | p->control = arm_hwbp_control_initialize (mask, arm_hwbp_break, 1); |
| 905 | } |
| 906 | |
| 907 | /* Get the ARM hardware breakpoint type from the TYPE value we're |
| 908 | given when asked to set a watchpoint. */ |
| 909 | static arm_hwbp_type |
| 910 | arm_linux_get_hwbp_type (enum target_hw_bp_type type) |
| 911 | { |
| 912 | if (type == hw_read) |
| 913 | return arm_hwbp_load; |
| 914 | else if (type == hw_write) |
| 915 | return arm_hwbp_store; |
| 916 | else |
| 917 | return arm_hwbp_access; |
| 918 | } |
| 919 | |
| 920 | /* Initialize the hardware breakpoint structure P for a watchpoint at ADDR |
| 921 | to LEN. The type of watchpoint is given in RW. */ |
| 922 | static void |
| 923 | arm_linux_hw_watchpoint_initialize (CORE_ADDR addr, int len, |
| 924 | enum target_hw_bp_type type, |
| 925 | struct arm_linux_hw_breakpoint *p) |
| 926 | { |
| 927 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); |
| 928 | unsigned mask; |
| 929 | |
| 930 | gdb_assert (cap != NULL); |
| 931 | gdb_assert (cap->max_wp_length != 0); |
| 932 | |
| 933 | mask = (1 << len) - 1; |
| 934 | |
| 935 | p->address = (unsigned int) addr; |
| 936 | p->control = arm_hwbp_control_initialize (mask, |
| 937 | arm_linux_get_hwbp_type (type), 1); |
| 938 | } |
| 939 | |
| 940 | /* Are two break-/watch-points equal? */ |
| 941 | static int |
| 942 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, |
| 943 | const struct arm_linux_hw_breakpoint *p2) |
| 944 | { |
| 945 | return p1->address == p2->address && p1->control == p2->control; |
| 946 | } |
| 947 | |
| 948 | /* Callback to mark a watch-/breakpoint to be updated in all threads of |
| 949 | the current process. */ |
| 950 | |
| 951 | static int |
| 952 | update_registers_callback (struct lwp_info *lwp, int watch, int index) |
| 953 | { |
| 954 | if (lwp->arch_private == NULL) |
| 955 | lwp->arch_private = XCNEW (struct arch_lwp_info); |
| 956 | |
| 957 | /* The actual update is done later just before resuming the lwp, |
| 958 | we just mark that the registers need updating. */ |
| 959 | if (watch) |
| 960 | lwp->arch_private->wpts_changed[index] = 1; |
| 961 | else |
| 962 | lwp->arch_private->bpts_changed[index] = 1; |
| 963 | |
| 964 | /* If the lwp isn't stopped, force it to momentarily pause, so |
| 965 | we can update its breakpoint registers. */ |
| 966 | if (!lwp->stopped) |
| 967 | linux_stop_lwp (lwp); |
| 968 | |
| 969 | return 0; |
| 970 | } |
| 971 | |
| 972 | /* Insert the hardware breakpoint (WATCHPOINT = 0) or watchpoint (WATCHPOINT |
| 973 | =1) BPT for thread TID. */ |
| 974 | static void |
| 975 | arm_linux_insert_hw_breakpoint1 (const struct arm_linux_hw_breakpoint* bpt, |
| 976 | int watchpoint) |
| 977 | { |
| 978 | int pid; |
| 979 | ptid_t pid_ptid; |
| 980 | gdb_byte count, i; |
| 981 | struct arm_linux_hw_breakpoint* bpts; |
| 982 | |
| 983 | pid = inferior_ptid.pid (); |
| 984 | pid_ptid = ptid_t (pid); |
| 985 | |
| 986 | if (watchpoint) |
| 987 | { |
| 988 | count = arm_linux_get_hw_watchpoint_count (); |
| 989 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
| 990 | } |
| 991 | else |
| 992 | { |
| 993 | count = arm_linux_get_hw_breakpoint_count (); |
| 994 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
| 995 | } |
| 996 | |
| 997 | for (i = 0; i < count; ++i) |
| 998 | if (!arm_hwbp_control_is_enabled (bpts[i].control)) |
| 999 | { |
| 1000 | bpts[i] = *bpt; |
| 1001 | iterate_over_lwps (pid_ptid, |
| 1002 | [=] (struct lwp_info *info) |
| 1003 | { |
| 1004 | return update_registers_callback (info, watchpoint, |
| 1005 | i); |
| 1006 | }); |
| 1007 | break; |
| 1008 | } |
| 1009 | |
| 1010 | gdb_assert (i != count); |
| 1011 | } |
| 1012 | |
| 1013 | /* Remove the hardware breakpoint (WATCHPOINT = 0) or watchpoint |
| 1014 | (WATCHPOINT = 1) BPT for thread TID. */ |
| 1015 | static void |
| 1016 | arm_linux_remove_hw_breakpoint1 (const struct arm_linux_hw_breakpoint *bpt, |
| 1017 | int watchpoint) |
| 1018 | { |
| 1019 | int pid; |
| 1020 | gdb_byte count, i; |
| 1021 | ptid_t pid_ptid; |
| 1022 | struct arm_linux_hw_breakpoint* bpts; |
| 1023 | |
| 1024 | pid = inferior_ptid.pid (); |
| 1025 | pid_ptid = ptid_t (pid); |
| 1026 | |
| 1027 | if (watchpoint) |
| 1028 | { |
| 1029 | count = arm_linux_get_hw_watchpoint_count (); |
| 1030 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
| 1031 | } |
| 1032 | else |
| 1033 | { |
| 1034 | count = arm_linux_get_hw_breakpoint_count (); |
| 1035 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
| 1036 | } |
| 1037 | |
| 1038 | for (i = 0; i < count; ++i) |
| 1039 | if (arm_linux_hw_breakpoint_equal (bpt, bpts + i)) |
| 1040 | { |
| 1041 | bpts[i].control = arm_hwbp_control_disable (bpts[i].control); |
| 1042 | iterate_over_lwps (pid_ptid, |
| 1043 | [=] (struct lwp_info *info) |
| 1044 | { |
| 1045 | return update_registers_callback (info, watchpoint, |
| 1046 | i); |
| 1047 | }); |
| 1048 | break; |
| 1049 | } |
| 1050 | |
| 1051 | gdb_assert (i != count); |
| 1052 | } |
| 1053 | |
| 1054 | /* Insert a Hardware breakpoint. */ |
| 1055 | int |
| 1056 | arm_linux_nat_target::insert_hw_breakpoint (struct gdbarch *gdbarch, |
| 1057 | struct bp_target_info *bp_tgt) |
| 1058 | { |
| 1059 | struct arm_linux_hw_breakpoint p; |
| 1060 | |
| 1061 | if (arm_linux_get_hw_breakpoint_count () == 0) |
| 1062 | return -1; |
| 1063 | |
| 1064 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); |
| 1065 | |
| 1066 | arm_linux_insert_hw_breakpoint1 (&p, 0); |
| 1067 | |
| 1068 | return 0; |
| 1069 | } |
| 1070 | |
| 1071 | /* Remove a hardware breakpoint. */ |
| 1072 | int |
| 1073 | arm_linux_nat_target::remove_hw_breakpoint (struct gdbarch *gdbarch, |
| 1074 | struct bp_target_info *bp_tgt) |
| 1075 | { |
| 1076 | struct arm_linux_hw_breakpoint p; |
| 1077 | |
| 1078 | if (arm_linux_get_hw_breakpoint_count () == 0) |
| 1079 | return -1; |
| 1080 | |
| 1081 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); |
| 1082 | |
| 1083 | arm_linux_remove_hw_breakpoint1 (&p, 0); |
| 1084 | |
| 1085 | return 0; |
| 1086 | } |
| 1087 | |
| 1088 | /* Are we able to use a hardware watchpoint for the LEN bytes starting at |
| 1089 | ADDR? */ |
| 1090 | int |
| 1091 | arm_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) |
| 1092 | { |
| 1093 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); |
| 1094 | CORE_ADDR max_wp_length, aligned_addr; |
| 1095 | |
| 1096 | /* Can not set watchpoints for zero or negative lengths. */ |
| 1097 | if (len <= 0) |
| 1098 | return 0; |
| 1099 | |
| 1100 | /* Need to be able to use the ptrace interface. */ |
| 1101 | if (cap == NULL || cap->wp_count == 0) |
| 1102 | return 0; |
| 1103 | |
| 1104 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address |
| 1105 | range covered by a watchpoint. */ |
| 1106 | max_wp_length = (CORE_ADDR)cap->max_wp_length; |
| 1107 | aligned_addr = addr & ~(max_wp_length - 1); |
| 1108 | |
| 1109 | if (aligned_addr + max_wp_length < addr + len) |
| 1110 | return 0; |
| 1111 | |
| 1112 | /* The current ptrace interface can only handle watchpoints that are a |
| 1113 | power of 2. */ |
| 1114 | if ((len & (len - 1)) != 0) |
| 1115 | return 0; |
| 1116 | |
| 1117 | /* All tests passed so we must be able to set a watchpoint. */ |
| 1118 | return 1; |
| 1119 | } |
| 1120 | |
| 1121 | /* Insert a Hardware breakpoint. */ |
| 1122 | int |
| 1123 | arm_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, |
| 1124 | enum target_hw_bp_type rw, |
| 1125 | struct expression *cond) |
| 1126 | { |
| 1127 | struct arm_linux_hw_breakpoint p; |
| 1128 | |
| 1129 | if (arm_linux_get_hw_watchpoint_count () == 0) |
| 1130 | return -1; |
| 1131 | |
| 1132 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); |
| 1133 | |
| 1134 | arm_linux_insert_hw_breakpoint1 (&p, 1); |
| 1135 | |
| 1136 | return 0; |
| 1137 | } |
| 1138 | |
| 1139 | /* Remove a hardware breakpoint. */ |
| 1140 | int |
| 1141 | arm_linux_nat_target::remove_watchpoint (CORE_ADDR addr, |
| 1142 | int len, enum target_hw_bp_type rw, |
| 1143 | struct expression *cond) |
| 1144 | { |
| 1145 | struct arm_linux_hw_breakpoint p; |
| 1146 | |
| 1147 | if (arm_linux_get_hw_watchpoint_count () == 0) |
| 1148 | return -1; |
| 1149 | |
| 1150 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); |
| 1151 | |
| 1152 | arm_linux_remove_hw_breakpoint1 (&p, 1); |
| 1153 | |
| 1154 | return 0; |
| 1155 | } |
| 1156 | |
| 1157 | /* What was the data address the target was stopped on accessing. */ |
| 1158 | bool |
| 1159 | arm_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p) |
| 1160 | { |
| 1161 | siginfo_t siginfo; |
| 1162 | int slot; |
| 1163 | |
| 1164 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) |
| 1165 | return false; |
| 1166 | |
| 1167 | /* This must be a hardware breakpoint. */ |
| 1168 | if (siginfo.si_signo != SIGTRAP |
| 1169 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) |
| 1170 | return false; |
| 1171 | |
| 1172 | /* We must be able to set hardware watchpoints. */ |
| 1173 | if (arm_linux_get_hw_watchpoint_count () == 0) |
| 1174 | return 0; |
| 1175 | |
| 1176 | slot = siginfo.si_errno; |
| 1177 | |
| 1178 | /* If we are in a positive slot then we're looking at a breakpoint and not |
| 1179 | a watchpoint. */ |
| 1180 | if (slot >= 0) |
| 1181 | return false; |
| 1182 | |
| 1183 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; |
| 1184 | return true; |
| 1185 | } |
| 1186 | |
| 1187 | /* Has the target been stopped by hitting a watchpoint? */ |
| 1188 | bool |
| 1189 | arm_linux_nat_target::stopped_by_watchpoint () |
| 1190 | { |
| 1191 | CORE_ADDR addr; |
| 1192 | return stopped_data_address (&addr); |
| 1193 | } |
| 1194 | |
| 1195 | bool |
| 1196 | arm_linux_nat_target::watchpoint_addr_within_range (CORE_ADDR addr, |
| 1197 | CORE_ADDR start, |
| 1198 | int length) |
| 1199 | { |
| 1200 | return start <= addr && start + length - 1 >= addr; |
| 1201 | } |
| 1202 | |
| 1203 | /* Handle thread creation. We need to copy the breakpoints and watchpoints |
| 1204 | in the parent thread to the child thread. */ |
| 1205 | void |
| 1206 | arm_linux_nat_target::low_new_thread (struct lwp_info *lp) |
| 1207 | { |
| 1208 | int i; |
| 1209 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); |
| 1210 | |
| 1211 | /* Mark that all the hardware breakpoint/watchpoint register pairs |
| 1212 | for this thread need to be initialized. */ |
| 1213 | |
| 1214 | for (i = 0; i < MAX_BPTS; i++) |
| 1215 | { |
| 1216 | info->bpts_changed[i] = 1; |
| 1217 | info->wpts_changed[i] = 1; |
| 1218 | } |
| 1219 | |
| 1220 | lp->arch_private = info; |
| 1221 | } |
| 1222 | |
| 1223 | /* Function to call when a thread is being deleted. */ |
| 1224 | |
| 1225 | void |
| 1226 | arm_linux_nat_target::low_delete_thread (struct arch_lwp_info *arch_lwp) |
| 1227 | { |
| 1228 | xfree (arch_lwp); |
| 1229 | } |
| 1230 | |
| 1231 | /* Called when resuming a thread. |
| 1232 | The hardware debug registers are updated when there is any change. */ |
| 1233 | |
| 1234 | void |
| 1235 | arm_linux_nat_target::low_prepare_to_resume (struct lwp_info *lwp) |
| 1236 | { |
| 1237 | int pid, i; |
| 1238 | struct arm_linux_hw_breakpoint *bpts, *wpts; |
| 1239 | struct arch_lwp_info *arm_lwp_info = lwp->arch_private; |
| 1240 | |
| 1241 | pid = lwp->ptid.lwp (); |
| 1242 | bpts = arm_linux_get_debug_reg_state (lwp->ptid.pid ())->bpts; |
| 1243 | wpts = arm_linux_get_debug_reg_state (lwp->ptid.pid ())->wpts; |
| 1244 | |
| 1245 | /* NULL means this is the main thread still going through the shell, |
| 1246 | or, no watchpoint has been set yet. In that case, there's |
| 1247 | nothing to do. */ |
| 1248 | if (arm_lwp_info == NULL) |
| 1249 | return; |
| 1250 | |
| 1251 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) |
| 1252 | if (arm_lwp_info->bpts_changed[i]) |
| 1253 | { |
| 1254 | errno = 0; |
| 1255 | if (arm_hwbp_control_is_enabled (bpts[i].control)) |
| 1256 | if (ptrace (PTRACE_SETHBPREGS, pid, |
| 1257 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), &bpts[i].address) < 0) |
| 1258 | perror_with_name (_("Unexpected error setting breakpoint")); |
| 1259 | |
| 1260 | if (bpts[i].control != 0) |
| 1261 | if (ptrace (PTRACE_SETHBPREGS, pid, |
| 1262 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), &bpts[i].control) < 0) |
| 1263 | perror_with_name (_("Unexpected error setting breakpoint")); |
| 1264 | |
| 1265 | arm_lwp_info->bpts_changed[i] = 0; |
| 1266 | } |
| 1267 | |
| 1268 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) |
| 1269 | if (arm_lwp_info->wpts_changed[i]) |
| 1270 | { |
| 1271 | errno = 0; |
| 1272 | if (arm_hwbp_control_is_enabled (wpts[i].control)) |
| 1273 | if (ptrace (PTRACE_SETHBPREGS, pid, |
| 1274 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), &wpts[i].address) < 0) |
| 1275 | perror_with_name (_("Unexpected error setting watchpoint")); |
| 1276 | |
| 1277 | if (wpts[i].control != 0) |
| 1278 | if (ptrace (PTRACE_SETHBPREGS, pid, |
| 1279 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), &wpts[i].control) < 0) |
| 1280 | perror_with_name (_("Unexpected error setting watchpoint")); |
| 1281 | |
| 1282 | arm_lwp_info->wpts_changed[i] = 0; |
| 1283 | } |
| 1284 | } |
| 1285 | |
| 1286 | /* linux_nat_new_fork hook. */ |
| 1287 | |
| 1288 | void |
| 1289 | arm_linux_nat_target::low_new_fork (struct lwp_info *parent, pid_t child_pid) |
| 1290 | { |
| 1291 | pid_t parent_pid; |
| 1292 | struct arm_linux_debug_reg_state *parent_state; |
| 1293 | struct arm_linux_debug_reg_state *child_state; |
| 1294 | |
| 1295 | /* NULL means no watchpoint has ever been set in the parent. In |
| 1296 | that case, there's nothing to do. */ |
| 1297 | if (parent->arch_private == NULL) |
| 1298 | return; |
| 1299 | |
| 1300 | /* GDB core assumes the child inherits the watchpoints/hw |
| 1301 | breakpoints of the parent, and will remove them all from the |
| 1302 | forked off process. Copy the debug registers mirrors into the |
| 1303 | new process so that all breakpoints and watchpoints can be |
| 1304 | removed together. */ |
| 1305 | |
| 1306 | parent_pid = parent->ptid.pid (); |
| 1307 | parent_state = arm_linux_get_debug_reg_state (parent_pid); |
| 1308 | child_state = arm_linux_get_debug_reg_state (child_pid); |
| 1309 | *child_state = *parent_state; |
| 1310 | } |
| 1311 | |
| 1312 | void |
| 1313 | _initialize_arm_linux_nat (void) |
| 1314 | { |
| 1315 | /* Register the target. */ |
| 1316 | linux_target = &the_arm_linux_nat_target; |
| 1317 | add_inf_child_target (&the_arm_linux_nat_target); |
| 1318 | } |