| 1 | /* Common target dependent code for GDB on ARM systems. |
| 2 | Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000, |
| 3 | 2001, 2002, 2003 Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 2 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program; if not, write to the Free Software |
| 19 | Foundation, Inc., 59 Temple Place - Suite 330, |
| 20 | Boston, MA 02111-1307, USA. */ |
| 21 | |
| 22 | #include <ctype.h> /* XXX for isupper () */ |
| 23 | |
| 24 | #include "defs.h" |
| 25 | #include "frame.h" |
| 26 | #include "inferior.h" |
| 27 | #include "gdbcmd.h" |
| 28 | #include "gdbcore.h" |
| 29 | #include "symfile.h" |
| 30 | #include "gdb_string.h" |
| 31 | #include "dis-asm.h" /* For register styles. */ |
| 32 | #include "regcache.h" |
| 33 | #include "doublest.h" |
| 34 | #include "value.h" |
| 35 | #include "arch-utils.h" |
| 36 | #include "solib-svr4.h" |
| 37 | #include "osabi.h" |
| 38 | |
| 39 | #include "arm-tdep.h" |
| 40 | #include "gdb/sim-arm.h" |
| 41 | |
| 42 | #include "elf-bfd.h" |
| 43 | #include "coff/internal.h" |
| 44 | #include "elf/arm.h" |
| 45 | |
| 46 | #include "gdb_assert.h" |
| 47 | |
| 48 | static int arm_debug; |
| 49 | |
| 50 | /* Each OS has a different mechanism for accessing the various |
| 51 | registers stored in the sigcontext structure. |
| 52 | |
| 53 | SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or |
| 54 | function pointer) which may be used to determine the addresses |
| 55 | of the various saved registers in the sigcontext structure. |
| 56 | |
| 57 | For the ARM target, there are three parameters to this function. |
| 58 | The first is the pc value of the frame under consideration, the |
| 59 | second the stack pointer of this frame, and the last is the |
| 60 | register number to fetch. |
| 61 | |
| 62 | If the tm.h file does not define this macro, then it's assumed that |
| 63 | no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to |
| 64 | be 0. |
| 65 | |
| 66 | When it comes time to multi-arching this code, see the identically |
| 67 | named machinery in ia64-tdep.c for an example of how it could be |
| 68 | done. It should not be necessary to modify the code below where |
| 69 | this macro is used. */ |
| 70 | |
| 71 | #ifdef SIGCONTEXT_REGISTER_ADDRESS |
| 72 | #ifndef SIGCONTEXT_REGISTER_ADDRESS_P |
| 73 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 1 |
| 74 | #endif |
| 75 | #else |
| 76 | #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0 |
| 77 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 0 |
| 78 | #endif |
| 79 | |
| 80 | /* Macros for setting and testing a bit in a minimal symbol that marks |
| 81 | it as Thumb function. The MSB of the minimal symbol's "info" field |
| 82 | is used for this purpose. This field is already being used to store |
| 83 | the symbol size, so the assumption is that the symbol size cannot |
| 84 | exceed 2^31. |
| 85 | |
| 86 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. |
| 87 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. |
| 88 | MSYMBOL_SIZE Returns the size of the minimal symbol, |
| 89 | i.e. the "info" field with the "special" bit |
| 90 | masked out. */ |
| 91 | |
| 92 | #define MSYMBOL_SET_SPECIAL(msym) \ |
| 93 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ |
| 94 | | 0x80000000) |
| 95 | |
| 96 | #define MSYMBOL_IS_SPECIAL(msym) \ |
| 97 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) |
| 98 | |
| 99 | #define MSYMBOL_SIZE(msym) \ |
| 100 | ((long) MSYMBOL_INFO (msym) & 0x7fffffff) |
| 101 | |
| 102 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
| 103 | static struct cmd_list_element *setarmcmdlist = NULL; |
| 104 | static struct cmd_list_element *showarmcmdlist = NULL; |
| 105 | |
| 106 | /* The type of floating-point to use. Keep this in sync with enum |
| 107 | arm_float_model, and the help string in _initialize_arm_tdep. */ |
| 108 | static const char *fp_model_strings[] = |
| 109 | { |
| 110 | "auto", |
| 111 | "softfpa", |
| 112 | "fpa", |
| 113 | "softvfp", |
| 114 | "vfp" |
| 115 | }; |
| 116 | |
| 117 | /* A variable that can be configured by the user. */ |
| 118 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; |
| 119 | static const char *current_fp_model = "auto"; |
| 120 | |
| 121 | /* Number of different reg name sets (options). */ |
| 122 | static int num_disassembly_options; |
| 123 | |
| 124 | /* We have more registers than the disassembler as gdb can print the value |
| 125 | of special registers as well. |
| 126 | The general register names are overwritten by whatever is being used by |
| 127 | the disassembler at the moment. We also adjust the case of cpsr and fps. */ |
| 128 | |
| 129 | /* Initial value: Register names used in ARM's ISA documentation. */ |
| 130 | static char * arm_register_name_strings[] = |
| 131 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
| 132 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ |
| 133 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ |
| 134 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ |
| 135 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ |
| 136 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ |
| 137 | "fps", "cpsr" }; /* 24 25 */ |
| 138 | static char **arm_register_names = arm_register_name_strings; |
| 139 | |
| 140 | /* Valid register name styles. */ |
| 141 | static const char **valid_disassembly_styles; |
| 142 | |
| 143 | /* Disassembly style to use. Default to "std" register names. */ |
| 144 | static const char *disassembly_style; |
| 145 | /* Index to that option in the opcodes table. */ |
| 146 | static int current_option; |
| 147 | |
| 148 | /* This is used to keep the bfd arch_info in sync with the disassembly |
| 149 | style. */ |
| 150 | static void set_disassembly_style_sfunc(char *, int, |
| 151 | struct cmd_list_element *); |
| 152 | static void set_disassembly_style (void); |
| 153 | |
| 154 | static void convert_from_extended (const struct floatformat *, const void *, |
| 155 | void *); |
| 156 | static void convert_to_extended (const struct floatformat *, void *, |
| 157 | const void *); |
| 158 | |
| 159 | /* Define other aspects of the stack frame. We keep the offsets of |
| 160 | all saved registers, 'cause we need 'em a lot! We also keep the |
| 161 | current size of the stack frame, and the offset of the frame |
| 162 | pointer from the stack pointer (for frameless functions, and when |
| 163 | we're still in the prologue of a function with a frame). */ |
| 164 | |
| 165 | struct frame_extra_info |
| 166 | { |
| 167 | int framesize; |
| 168 | int frameoffset; |
| 169 | int framereg; |
| 170 | }; |
| 171 | |
| 172 | /* Addresses for calling Thumb functions have the bit 0 set. |
| 173 | Here are some macros to test, set, or clear bit 0 of addresses. */ |
| 174 | #define IS_THUMB_ADDR(addr) ((addr) & 1) |
| 175 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) |
| 176 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) |
| 177 | |
| 178 | static int |
| 179 | arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe) |
| 180 | { |
| 181 | return (DEPRECATED_FRAME_SAVED_PC (thisframe) >= LOWEST_PC); |
| 182 | } |
| 183 | |
| 184 | /* Set to true if the 32-bit mode is in use. */ |
| 185 | |
| 186 | int arm_apcs_32 = 1; |
| 187 | |
| 188 | /* Flag set by arm_fix_call_dummy that tells whether the target |
| 189 | function is a Thumb function. This flag is checked by |
| 190 | arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and |
| 191 | its use in valops.c) to pass the function address as an additional |
| 192 | parameter. */ |
| 193 | |
| 194 | static int target_is_thumb; |
| 195 | |
| 196 | /* Flag set by arm_fix_call_dummy that tells whether the calling |
| 197 | function is a Thumb function. This flag is checked by |
| 198 | arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */ |
| 199 | |
| 200 | static int caller_is_thumb; |
| 201 | |
| 202 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
| 203 | function. */ |
| 204 | |
| 205 | int |
| 206 | arm_pc_is_thumb (CORE_ADDR memaddr) |
| 207 | { |
| 208 | struct minimal_symbol *sym; |
| 209 | |
| 210 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
| 211 | if (IS_THUMB_ADDR (memaddr)) |
| 212 | return 1; |
| 213 | |
| 214 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
| 215 | sym = lookup_minimal_symbol_by_pc (memaddr); |
| 216 | if (sym) |
| 217 | { |
| 218 | return (MSYMBOL_IS_SPECIAL (sym)); |
| 219 | } |
| 220 | else |
| 221 | { |
| 222 | return 0; |
| 223 | } |
| 224 | } |
| 225 | |
| 226 | /* Determine if the program counter specified in MEMADDR is in a call |
| 227 | dummy being called from a Thumb function. */ |
| 228 | |
| 229 | int |
| 230 | arm_pc_is_thumb_dummy (CORE_ADDR memaddr) |
| 231 | { |
| 232 | CORE_ADDR sp = read_sp (); |
| 233 | |
| 234 | /* FIXME: Until we switch for the new call dummy macros, this heuristic |
| 235 | is the best we can do. We are trying to determine if the pc is on |
| 236 | the stack, which (hopefully) will only happen in a call dummy. |
| 237 | We hope the current stack pointer is not so far alway from the dummy |
| 238 | frame location (true if we have not pushed large data structures or |
| 239 | gone too many levels deep) and that our 1024 is not enough to consider |
| 240 | code regions as part of the stack (true for most practical purposes). */ |
| 241 | if (DEPRECATED_PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024)) |
| 242 | return caller_is_thumb; |
| 243 | else |
| 244 | return 0; |
| 245 | } |
| 246 | |
| 247 | /* Remove useless bits from addresses in a running program. */ |
| 248 | static CORE_ADDR |
| 249 | arm_addr_bits_remove (CORE_ADDR val) |
| 250 | { |
| 251 | if (arm_apcs_32) |
| 252 | return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc)); |
| 253 | else |
| 254 | return (val & 0x03fffffc); |
| 255 | } |
| 256 | |
| 257 | /* When reading symbols, we need to zap the low bit of the address, |
| 258 | which may be set to 1 for Thumb functions. */ |
| 259 | static CORE_ADDR |
| 260 | arm_smash_text_address (CORE_ADDR val) |
| 261 | { |
| 262 | return val & ~1; |
| 263 | } |
| 264 | |
| 265 | /* Immediately after a function call, return the saved pc. Can't |
| 266 | always go through the frames for this because on some machines the |
| 267 | new frame is not set up until the new function executes some |
| 268 | instructions. */ |
| 269 | |
| 270 | static CORE_ADDR |
| 271 | arm_saved_pc_after_call (struct frame_info *frame) |
| 272 | { |
| 273 | return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM)); |
| 274 | } |
| 275 | |
| 276 | /* Determine whether the function invocation represented by FI has a |
| 277 | frame on the stack associated with it. If it does return zero, |
| 278 | otherwise return 1. */ |
| 279 | |
| 280 | static int |
| 281 | arm_frameless_function_invocation (struct frame_info *fi) |
| 282 | { |
| 283 | CORE_ADDR func_start, after_prologue; |
| 284 | int frameless; |
| 285 | |
| 286 | /* Sometimes we have functions that do a little setup (like saving the |
| 287 | vN registers with the stmdb instruction, but DO NOT set up a frame. |
| 288 | The symbol table will report this as a prologue. However, it is |
| 289 | important not to try to parse these partial frames as frames, or we |
| 290 | will get really confused. |
| 291 | |
| 292 | So I will demand 3 instructions between the start & end of the |
| 293 | prologue before I call it a real prologue, i.e. at least |
| 294 | mov ip, sp, |
| 295 | stmdb sp!, {} |
| 296 | sub sp, ip, #4. */ |
| 297 | |
| 298 | func_start = (get_pc_function_start (get_frame_pc (fi)) + FUNCTION_START_OFFSET); |
| 299 | after_prologue = SKIP_PROLOGUE (func_start); |
| 300 | |
| 301 | /* There are some frameless functions whose first two instructions |
| 302 | follow the standard APCS form, in which case after_prologue will |
| 303 | be func_start + 8. */ |
| 304 | |
| 305 | frameless = (after_prologue < func_start + 12); |
| 306 | return frameless; |
| 307 | } |
| 308 | |
| 309 | /* The address of the arguments in the frame. */ |
| 310 | static CORE_ADDR |
| 311 | arm_frame_args_address (struct frame_info *fi) |
| 312 | { |
| 313 | return get_frame_base (fi); |
| 314 | } |
| 315 | |
| 316 | /* The address of the local variables in the frame. */ |
| 317 | static CORE_ADDR |
| 318 | arm_frame_locals_address (struct frame_info *fi) |
| 319 | { |
| 320 | return get_frame_base (fi); |
| 321 | } |
| 322 | |
| 323 | /* The number of arguments being passed in the frame. */ |
| 324 | static int |
| 325 | arm_frame_num_args (struct frame_info *fi) |
| 326 | { |
| 327 | /* We have no way of knowing. */ |
| 328 | return -1; |
| 329 | } |
| 330 | |
| 331 | /* A typical Thumb prologue looks like this: |
| 332 | push {r7, lr} |
| 333 | add sp, sp, #-28 |
| 334 | add r7, sp, #12 |
| 335 | Sometimes the latter instruction may be replaced by: |
| 336 | mov r7, sp |
| 337 | |
| 338 | or like this: |
| 339 | push {r7, lr} |
| 340 | mov r7, sp |
| 341 | sub sp, #12 |
| 342 | |
| 343 | or, on tpcs, like this: |
| 344 | sub sp,#16 |
| 345 | push {r7, lr} |
| 346 | (many instructions) |
| 347 | mov r7, sp |
| 348 | sub sp, #12 |
| 349 | |
| 350 | There is always one instruction of three classes: |
| 351 | 1 - push |
| 352 | 2 - setting of r7 |
| 353 | 3 - adjusting of sp |
| 354 | |
| 355 | When we have found at least one of each class we are done with the prolog. |
| 356 | Note that the "sub sp, #NN" before the push does not count. |
| 357 | */ |
| 358 | |
| 359 | static CORE_ADDR |
| 360 | thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end) |
| 361 | { |
| 362 | CORE_ADDR current_pc; |
| 363 | /* findmask: |
| 364 | bit 0 - push { rlist } |
| 365 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) |
| 366 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) |
| 367 | */ |
| 368 | int findmask = 0; |
| 369 | |
| 370 | for (current_pc = pc; |
| 371 | current_pc + 2 < func_end && current_pc < pc + 40; |
| 372 | current_pc += 2) |
| 373 | { |
| 374 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); |
| 375 | |
| 376 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
| 377 | { |
| 378 | findmask |= 1; /* push found */ |
| 379 | } |
| 380 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
| 381 | sub sp, #simm */ |
| 382 | { |
| 383 | if ((findmask & 1) == 0) /* before push ? */ |
| 384 | continue; |
| 385 | else |
| 386 | findmask |= 4; /* add/sub sp found */ |
| 387 | } |
| 388 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ |
| 389 | { |
| 390 | findmask |= 2; /* setting of r7 found */ |
| 391 | } |
| 392 | else if (insn == 0x466f) /* mov r7, sp */ |
| 393 | { |
| 394 | findmask |= 2; /* setting of r7 found */ |
| 395 | } |
| 396 | else if (findmask == (4+2+1)) |
| 397 | { |
| 398 | /* We have found one of each type of prologue instruction */ |
| 399 | break; |
| 400 | } |
| 401 | else |
| 402 | /* Something in the prolog that we don't care about or some |
| 403 | instruction from outside the prolog scheduled here for |
| 404 | optimization. */ |
| 405 | continue; |
| 406 | } |
| 407 | |
| 408 | return current_pc; |
| 409 | } |
| 410 | |
| 411 | /* Advance the PC across any function entry prologue instructions to |
| 412 | reach some "real" code. |
| 413 | |
| 414 | The APCS (ARM Procedure Call Standard) defines the following |
| 415 | prologue: |
| 416 | |
| 417 | mov ip, sp |
| 418 | [stmfd sp!, {a1,a2,a3,a4}] |
| 419 | stmfd sp!, {...,fp,ip,lr,pc} |
| 420 | [stfe f7, [sp, #-12]!] |
| 421 | [stfe f6, [sp, #-12]!] |
| 422 | [stfe f5, [sp, #-12]!] |
| 423 | [stfe f4, [sp, #-12]!] |
| 424 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ |
| 425 | |
| 426 | static CORE_ADDR |
| 427 | arm_skip_prologue (CORE_ADDR pc) |
| 428 | { |
| 429 | unsigned long inst; |
| 430 | CORE_ADDR skip_pc; |
| 431 | CORE_ADDR func_addr, func_end = 0; |
| 432 | char *func_name; |
| 433 | struct symtab_and_line sal; |
| 434 | |
| 435 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
| 436 | if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0)) |
| 437 | return pc; |
| 438 | |
| 439 | /* See what the symbol table says. */ |
| 440 | |
| 441 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) |
| 442 | { |
| 443 | struct symbol *sym; |
| 444 | |
| 445 | /* Found a function. */ |
| 446 | sym = lookup_symbol (func_name, NULL, VAR_NAMESPACE, NULL, NULL); |
| 447 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) |
| 448 | { |
| 449 | /* Don't use this trick for assembly source files. */ |
| 450 | sal = find_pc_line (func_addr, 0); |
| 451 | if ((sal.line != 0) && (sal.end < func_end)) |
| 452 | return sal.end; |
| 453 | } |
| 454 | } |
| 455 | |
| 456 | /* Check if this is Thumb code. */ |
| 457 | if (arm_pc_is_thumb (pc)) |
| 458 | return thumb_skip_prologue (pc, func_end); |
| 459 | |
| 460 | /* Can't find the prologue end in the symbol table, try it the hard way |
| 461 | by disassembling the instructions. */ |
| 462 | |
| 463 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
| 464 | if (func_end == 0 || func_end > pc + 64) |
| 465 | func_end = pc + 64; |
| 466 | |
| 467 | for (skip_pc = pc; skip_pc < func_end; skip_pc += 4) |
| 468 | { |
| 469 | inst = read_memory_integer (skip_pc, 4); |
| 470 | |
| 471 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
| 472 | if (inst == 0xe1a0c00d) /* mov ip, sp */ |
| 473 | continue; |
| 474 | |
| 475 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
| 476 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ |
| 477 | continue; |
| 478 | |
| 479 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
| 480 | continue; |
| 481 | |
| 482 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
| 483 | continue; |
| 484 | |
| 485 | /* Any insns after this point may float into the code, if it makes |
| 486 | for better instruction scheduling, so we skip them only if we |
| 487 | find them, but still consider the function to be frame-ful. */ |
| 488 | |
| 489 | /* We may have either one sfmfd instruction here, or several stfe |
| 490 | insns, depending on the version of floating point code we |
| 491 | support. */ |
| 492 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ |
| 493 | continue; |
| 494 | |
| 495 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ |
| 496 | continue; |
| 497 | |
| 498 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ |
| 499 | continue; |
| 500 | |
| 501 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ |
| 502 | continue; |
| 503 | |
| 504 | if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */ |
| 505 | (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */ |
| 506 | (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ |
| 507 | continue; |
| 508 | |
| 509 | if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */ |
| 510 | (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */ |
| 511 | (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ |
| 512 | continue; |
| 513 | |
| 514 | /* Un-recognized instruction; stop scanning. */ |
| 515 | break; |
| 516 | } |
| 517 | |
| 518 | return skip_pc; /* End of prologue */ |
| 519 | } |
| 520 | |
| 521 | /* *INDENT-OFF* */ |
| 522 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
| 523 | This function decodes a Thumb function prologue to determine: |
| 524 | 1) the size of the stack frame |
| 525 | 2) which registers are saved on it |
| 526 | 3) the offsets of saved regs |
| 527 | 4) the offset from the stack pointer to the frame pointer |
| 528 | This information is stored in the "extra" fields of the frame_info. |
| 529 | |
| 530 | A typical Thumb function prologue would create this stack frame |
| 531 | (offsets relative to FP) |
| 532 | old SP -> 24 stack parameters |
| 533 | 20 LR |
| 534 | 16 R7 |
| 535 | R7 -> 0 local variables (16 bytes) |
| 536 | SP -> -12 additional stack space (12 bytes) |
| 537 | The frame size would thus be 36 bytes, and the frame offset would be |
| 538 | 12 bytes. The frame register is R7. |
| 539 | |
| 540 | The comments for thumb_skip_prolog() describe the algorithm we use |
| 541 | to detect the end of the prolog. */ |
| 542 | /* *INDENT-ON* */ |
| 543 | |
| 544 | static void |
| 545 | thumb_scan_prologue (struct frame_info *fi) |
| 546 | { |
| 547 | CORE_ADDR prologue_start; |
| 548 | CORE_ADDR prologue_end; |
| 549 | CORE_ADDR current_pc; |
| 550 | /* Which register has been copied to register n? */ |
| 551 | int saved_reg[16]; |
| 552 | /* findmask: |
| 553 | bit 0 - push { rlist } |
| 554 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) |
| 555 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) |
| 556 | */ |
| 557 | int findmask = 0; |
| 558 | int i; |
| 559 | |
| 560 | /* Don't try to scan dummy frames. */ |
| 561 | if (fi != NULL |
| 562 | && DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0)) |
| 563 | return; |
| 564 | |
| 565 | if (find_pc_partial_function (get_frame_pc (fi), NULL, &prologue_start, &prologue_end)) |
| 566 | { |
| 567 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); |
| 568 | |
| 569 | if (sal.line == 0) /* no line info, use current PC */ |
| 570 | prologue_end = get_frame_pc (fi); |
| 571 | else if (sal.end < prologue_end) /* next line begins after fn end */ |
| 572 | prologue_end = sal.end; /* (probably means no prologue) */ |
| 573 | } |
| 574 | else |
| 575 | /* We're in the boondocks: allow for |
| 576 | 16 pushes, an add, and "mv fp,sp". */ |
| 577 | prologue_end = prologue_start + 40; |
| 578 | |
| 579 | prologue_end = min (prologue_end, get_frame_pc (fi)); |
| 580 | |
| 581 | /* Initialize the saved register map. When register H is copied to |
| 582 | register L, we will put H in saved_reg[L]. */ |
| 583 | for (i = 0; i < 16; i++) |
| 584 | saved_reg[i] = i; |
| 585 | |
| 586 | /* Search the prologue looking for instructions that set up the |
| 587 | frame pointer, adjust the stack pointer, and save registers. |
| 588 | Do this until all basic prolog instructions are found. */ |
| 589 | |
| 590 | get_frame_extra_info (fi)->framesize = 0; |
| 591 | for (current_pc = prologue_start; |
| 592 | (current_pc < prologue_end) && ((findmask & 7) != 7); |
| 593 | current_pc += 2) |
| 594 | { |
| 595 | unsigned short insn; |
| 596 | int regno; |
| 597 | int offset; |
| 598 | |
| 599 | insn = read_memory_unsigned_integer (current_pc, 2); |
| 600 | |
| 601 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
| 602 | { |
| 603 | int mask; |
| 604 | findmask |= 1; /* push found */ |
| 605 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says |
| 606 | whether to save LR (R14). */ |
| 607 | mask = (insn & 0xff) | ((insn & 0x100) << 6); |
| 608 | |
| 609 | /* Calculate offsets of saved R0-R7 and LR. */ |
| 610 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) |
| 611 | if (mask & (1 << regno)) |
| 612 | { |
| 613 | get_frame_extra_info (fi)->framesize += 4; |
| 614 | get_frame_saved_regs (fi)[saved_reg[regno]] = |
| 615 | -(get_frame_extra_info (fi)->framesize); |
| 616 | /* Reset saved register map. */ |
| 617 | saved_reg[regno] = regno; |
| 618 | } |
| 619 | } |
| 620 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
| 621 | sub sp, #simm */ |
| 622 | { |
| 623 | if ((findmask & 1) == 0) /* before push? */ |
| 624 | continue; |
| 625 | else |
| 626 | findmask |= 4; /* add/sub sp found */ |
| 627 | |
| 628 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
| 629 | if (insn & 0x80) /* is it signed? (==subtracting) */ |
| 630 | { |
| 631 | get_frame_extra_info (fi)->frameoffset += offset; |
| 632 | offset = -offset; |
| 633 | } |
| 634 | get_frame_extra_info (fi)->framesize -= offset; |
| 635 | } |
| 636 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ |
| 637 | { |
| 638 | findmask |= 2; /* setting of r7 found */ |
| 639 | get_frame_extra_info (fi)->framereg = THUMB_FP_REGNUM; |
| 640 | /* get scaled offset */ |
| 641 | get_frame_extra_info (fi)->frameoffset = (insn & 0xff) << 2; |
| 642 | } |
| 643 | else if (insn == 0x466f) /* mov r7, sp */ |
| 644 | { |
| 645 | findmask |= 2; /* setting of r7 found */ |
| 646 | get_frame_extra_info (fi)->framereg = THUMB_FP_REGNUM; |
| 647 | get_frame_extra_info (fi)->frameoffset = 0; |
| 648 | saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM; |
| 649 | } |
| 650 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ |
| 651 | { |
| 652 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ |
| 653 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ |
| 654 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ |
| 655 | } |
| 656 | else |
| 657 | /* Something in the prolog that we don't care about or some |
| 658 | instruction from outside the prolog scheduled here for |
| 659 | optimization. */ |
| 660 | continue; |
| 661 | } |
| 662 | } |
| 663 | |
| 664 | /* This function decodes an ARM function prologue to determine: |
| 665 | 1) the size of the stack frame |
| 666 | 2) which registers are saved on it |
| 667 | 3) the offsets of saved regs |
| 668 | 4) the offset from the stack pointer to the frame pointer |
| 669 | This information is stored in the "extra" fields of the frame_info. |
| 670 | |
| 671 | There are two basic forms for the ARM prologue. The fixed argument |
| 672 | function call will look like: |
| 673 | |
| 674 | mov ip, sp |
| 675 | stmfd sp!, {fp, ip, lr, pc} |
| 676 | sub fp, ip, #4 |
| 677 | [sub sp, sp, #4] |
| 678 | |
| 679 | Which would create this stack frame (offsets relative to FP): |
| 680 | IP -> 4 (caller's stack) |
| 681 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) |
| 682 | -4 LR (return address in caller) |
| 683 | -8 IP (copy of caller's SP) |
| 684 | -12 FP (caller's FP) |
| 685 | SP -> -28 Local variables |
| 686 | |
| 687 | The frame size would thus be 32 bytes, and the frame offset would be |
| 688 | 28 bytes. The stmfd call can also save any of the vN registers it |
| 689 | plans to use, which increases the frame size accordingly. |
| 690 | |
| 691 | Note: The stored PC is 8 off of the STMFD instruction that stored it |
| 692 | because the ARM Store instructions always store PC + 8 when you read |
| 693 | the PC register. |
| 694 | |
| 695 | A variable argument function call will look like: |
| 696 | |
| 697 | mov ip, sp |
| 698 | stmfd sp!, {a1, a2, a3, a4} |
| 699 | stmfd sp!, {fp, ip, lr, pc} |
| 700 | sub fp, ip, #20 |
| 701 | |
| 702 | Which would create this stack frame (offsets relative to FP): |
| 703 | IP -> 20 (caller's stack) |
| 704 | 16 A4 |
| 705 | 12 A3 |
| 706 | 8 A2 |
| 707 | 4 A1 |
| 708 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) |
| 709 | -4 LR (return address in caller) |
| 710 | -8 IP (copy of caller's SP) |
| 711 | -12 FP (caller's FP) |
| 712 | SP -> -28 Local variables |
| 713 | |
| 714 | The frame size would thus be 48 bytes, and the frame offset would be |
| 715 | 28 bytes. |
| 716 | |
| 717 | There is another potential complication, which is that the optimizer |
| 718 | will try to separate the store of fp in the "stmfd" instruction from |
| 719 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so |
| 720 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... |
| 721 | |
| 722 | Also, note, the original version of the ARM toolchain claimed that there |
| 723 | should be an |
| 724 | |
| 725 | instruction at the end of the prologue. I have never seen GCC produce |
| 726 | this, and the ARM docs don't mention it. We still test for it below in |
| 727 | case it happens... |
| 728 | |
| 729 | */ |
| 730 | |
| 731 | static void |
| 732 | arm_scan_prologue (struct frame_info *fi) |
| 733 | { |
| 734 | int regno, sp_offset, fp_offset; |
| 735 | LONGEST return_value; |
| 736 | CORE_ADDR prologue_start, prologue_end, current_pc; |
| 737 | |
| 738 | /* Assume there is no frame until proven otherwise. */ |
| 739 | get_frame_extra_info (fi)->framereg = ARM_SP_REGNUM; |
| 740 | get_frame_extra_info (fi)->framesize = 0; |
| 741 | get_frame_extra_info (fi)->frameoffset = 0; |
| 742 | |
| 743 | /* Check for Thumb prologue. */ |
| 744 | if (arm_pc_is_thumb (get_frame_pc (fi))) |
| 745 | { |
| 746 | thumb_scan_prologue (fi); |
| 747 | return; |
| 748 | } |
| 749 | |
| 750 | /* Find the function prologue. If we can't find the function in |
| 751 | the symbol table, peek in the stack frame to find the PC. */ |
| 752 | if (find_pc_partial_function (get_frame_pc (fi), NULL, &prologue_start, &prologue_end)) |
| 753 | { |
| 754 | /* One way to find the end of the prologue (which works well |
| 755 | for unoptimized code) is to do the following: |
| 756 | |
| 757 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); |
| 758 | |
| 759 | if (sal.line == 0) |
| 760 | prologue_end = get_frame_pc (fi); |
| 761 | else if (sal.end < prologue_end) |
| 762 | prologue_end = sal.end; |
| 763 | |
| 764 | This mechanism is very accurate so long as the optimizer |
| 765 | doesn't move any instructions from the function body into the |
| 766 | prologue. If this happens, sal.end will be the last |
| 767 | instruction in the first hunk of prologue code just before |
| 768 | the first instruction that the scheduler has moved from |
| 769 | the body to the prologue. |
| 770 | |
| 771 | In order to make sure that we scan all of the prologue |
| 772 | instructions, we use a slightly less accurate mechanism which |
| 773 | may scan more than necessary. To help compensate for this |
| 774 | lack of accuracy, the prologue scanning loop below contains |
| 775 | several clauses which'll cause the loop to terminate early if |
| 776 | an implausible prologue instruction is encountered. |
| 777 | |
| 778 | The expression |
| 779 | |
| 780 | prologue_start + 64 |
| 781 | |
| 782 | is a suitable endpoint since it accounts for the largest |
| 783 | possible prologue plus up to five instructions inserted by |
| 784 | the scheduler. */ |
| 785 | |
| 786 | if (prologue_end > prologue_start + 64) |
| 787 | { |
| 788 | prologue_end = prologue_start + 64; /* See above. */ |
| 789 | } |
| 790 | } |
| 791 | else |
| 792 | { |
| 793 | /* Get address of the stmfd in the prologue of the callee; |
| 794 | the saved PC is the address of the stmfd + 8. */ |
| 795 | if (!safe_read_memory_integer (get_frame_base (fi), 4, &return_value)) |
| 796 | return; |
| 797 | else |
| 798 | { |
| 799 | prologue_start = ADDR_BITS_REMOVE (return_value) - 8; |
| 800 | prologue_end = prologue_start + 64; /* See above. */ |
| 801 | } |
| 802 | } |
| 803 | |
| 804 | /* Now search the prologue looking for instructions that set up the |
| 805 | frame pointer, adjust the stack pointer, and save registers. |
| 806 | |
| 807 | Be careful, however, and if it doesn't look like a prologue, |
| 808 | don't try to scan it. If, for instance, a frameless function |
| 809 | begins with stmfd sp!, then we will tell ourselves there is |
| 810 | a frame, which will confuse stack traceback, as well as "finish" |
| 811 | and other operations that rely on a knowledge of the stack |
| 812 | traceback. |
| 813 | |
| 814 | In the APCS, the prologue should start with "mov ip, sp" so |
| 815 | if we don't see this as the first insn, we will stop. |
| 816 | |
| 817 | [Note: This doesn't seem to be true any longer, so it's now an |
| 818 | optional part of the prologue. - Kevin Buettner, 2001-11-20] |
| 819 | |
| 820 | [Note further: The "mov ip,sp" only seems to be missing in |
| 821 | frameless functions at optimization level "-O2" or above, |
| 822 | in which case it is often (but not always) replaced by |
| 823 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
| 824 | |
| 825 | sp_offset = fp_offset = 0; |
| 826 | |
| 827 | for (current_pc = prologue_start; |
| 828 | current_pc < prologue_end; |
| 829 | current_pc += 4) |
| 830 | { |
| 831 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
| 832 | |
| 833 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
| 834 | { |
| 835 | continue; |
| 836 | } |
| 837 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
| 838 | { |
| 839 | /* Function is frameless: extra_info defaults OK? */ |
| 840 | continue; |
| 841 | } |
| 842 | else if ((insn & 0xffff0000) == 0xe92d0000) |
| 843 | /* stmfd sp!, {..., fp, ip, lr, pc} |
| 844 | or |
| 845 | stmfd sp!, {a1, a2, a3, a4} */ |
| 846 | { |
| 847 | int mask = insn & 0xffff; |
| 848 | |
| 849 | /* Calculate offsets of saved registers. */ |
| 850 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
| 851 | if (mask & (1 << regno)) |
| 852 | { |
| 853 | sp_offset -= 4; |
| 854 | get_frame_saved_regs (fi)[regno] = sp_offset; |
| 855 | } |
| 856 | } |
| 857 | else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */ |
| 858 | (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */ |
| 859 | (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ |
| 860 | { |
| 861 | /* No need to add this to saved_regs -- it's just an arg reg. */ |
| 862 | continue; |
| 863 | } |
| 864 | else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */ |
| 865 | (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */ |
| 866 | (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ |
| 867 | { |
| 868 | /* No need to add this to saved_regs -- it's just an arg reg. */ |
| 869 | continue; |
| 870 | } |
| 871 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
| 872 | { |
| 873 | unsigned imm = insn & 0xff; /* immediate value */ |
| 874 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ |
| 875 | imm = (imm >> rot) | (imm << (32 - rot)); |
| 876 | fp_offset = -imm; |
| 877 | get_frame_extra_info (fi)->framereg = ARM_FP_REGNUM; |
| 878 | } |
| 879 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ |
| 880 | { |
| 881 | unsigned imm = insn & 0xff; /* immediate value */ |
| 882 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ |
| 883 | imm = (imm >> rot) | (imm << (32 - rot)); |
| 884 | sp_offset -= imm; |
| 885 | } |
| 886 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ |
| 887 | { |
| 888 | sp_offset -= 12; |
| 889 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
| 890 | get_frame_saved_regs (fi)[regno] = sp_offset; |
| 891 | } |
| 892 | else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ |
| 893 | { |
| 894 | int n_saved_fp_regs; |
| 895 | unsigned int fp_start_reg, fp_bound_reg; |
| 896 | |
| 897 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
| 898 | { |
| 899 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
| 900 | n_saved_fp_regs = 3; |
| 901 | else |
| 902 | n_saved_fp_regs = 1; |
| 903 | } |
| 904 | else |
| 905 | { |
| 906 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
| 907 | n_saved_fp_regs = 2; |
| 908 | else |
| 909 | n_saved_fp_regs = 4; |
| 910 | } |
| 911 | |
| 912 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
| 913 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
| 914 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) |
| 915 | { |
| 916 | sp_offset -= 12; |
| 917 | get_frame_saved_regs (fi)[fp_start_reg++] = sp_offset; |
| 918 | } |
| 919 | } |
| 920 | else if ((insn & 0xf0000000) != 0xe0000000) |
| 921 | break; /* Condition not true, exit early */ |
| 922 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
| 923 | break; /* Don't scan past a block load */ |
| 924 | else |
| 925 | /* The optimizer might shove anything into the prologue, |
| 926 | so we just skip what we don't recognize. */ |
| 927 | continue; |
| 928 | } |
| 929 | |
| 930 | /* The frame size is just the negative of the offset (from the |
| 931 | original SP) of the last thing thing we pushed on the stack. |
| 932 | The frame offset is [new FP] - [new SP]. */ |
| 933 | get_frame_extra_info (fi)->framesize = -sp_offset; |
| 934 | if (get_frame_extra_info (fi)->framereg == ARM_FP_REGNUM) |
| 935 | get_frame_extra_info (fi)->frameoffset = fp_offset - sp_offset; |
| 936 | else |
| 937 | get_frame_extra_info (fi)->frameoffset = 0; |
| 938 | } |
| 939 | |
| 940 | /* Find REGNUM on the stack. Otherwise, it's in an active register. |
| 941 | One thing we might want to do here is to check REGNUM against the |
| 942 | clobber mask, and somehow flag it as invalid if it isn't saved on |
| 943 | the stack somewhere. This would provide a graceful failure mode |
| 944 | when trying to get the value of caller-saves registers for an inner |
| 945 | frame. */ |
| 946 | |
| 947 | static CORE_ADDR |
| 948 | arm_find_callers_reg (struct frame_info *fi, int regnum) |
| 949 | { |
| 950 | /* NOTE: cagney/2002-05-03: This function really shouldn't be |
| 951 | needed. Instead the (still being written) register unwind |
| 952 | function could be called directly. */ |
| 953 | for (; fi; fi = get_next_frame (fi)) |
| 954 | { |
| 955 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0)) |
| 956 | { |
| 957 | return deprecated_read_register_dummy (get_frame_pc (fi), |
| 958 | get_frame_base (fi), regnum); |
| 959 | } |
| 960 | else if (get_frame_saved_regs (fi)[regnum] != 0) |
| 961 | { |
| 962 | /* NOTE: cagney/2002-05-03: This would normally need to |
| 963 | handle ARM_SP_REGNUM as a special case as, according to |
| 964 | the frame.h comments, saved_regs[SP_REGNUM] contains the |
| 965 | SP value not its address. It appears that the ARM isn't |
| 966 | doing this though. */ |
| 967 | return read_memory_integer (get_frame_saved_regs (fi)[regnum], |
| 968 | REGISTER_RAW_SIZE (regnum)); |
| 969 | } |
| 970 | } |
| 971 | return read_register (regnum); |
| 972 | } |
| 973 | /* Function: frame_chain Given a GDB frame, determine the address of |
| 974 | the calling function's frame. This will be used to create a new |
| 975 | GDB frame struct, and then DEPRECATED_INIT_EXTRA_FRAME_INFO and |
| 976 | DEPRECATED_INIT_FRAME_PC will be called for the new frame. For |
| 977 | ARM, we save the frame size when we initialize the frame_info. */ |
| 978 | |
| 979 | static CORE_ADDR |
| 980 | arm_frame_chain (struct frame_info *fi) |
| 981 | { |
| 982 | CORE_ADDR caller_pc; |
| 983 | int framereg = get_frame_extra_info (fi)->framereg; |
| 984 | |
| 985 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0)) |
| 986 | /* A generic call dummy's frame is the same as caller's. */ |
| 987 | return get_frame_base (fi); |
| 988 | |
| 989 | if (get_frame_pc (fi) < LOWEST_PC) |
| 990 | return 0; |
| 991 | |
| 992 | /* If the caller is the startup code, we're at the end of the chain. */ |
| 993 | caller_pc = DEPRECATED_FRAME_SAVED_PC (fi); |
| 994 | |
| 995 | /* If the caller is Thumb and the caller is ARM, or vice versa, |
| 996 | the frame register of the caller is different from ours. |
| 997 | So we must scan the prologue of the caller to determine its |
| 998 | frame register number. */ |
| 999 | /* XXX Fixme, we should try to do this without creating a temporary |
| 1000 | caller_fi. */ |
| 1001 | if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (get_frame_pc (fi))) |
| 1002 | { |
| 1003 | struct cleanup *old_chain = make_cleanup (null_cleanup, NULL); |
| 1004 | struct frame_info *caller_fi = |
| 1005 | deprecated_frame_xmalloc_with_cleanup (SIZEOF_FRAME_SAVED_REGS, |
| 1006 | sizeof (struct frame_extra_info)); |
| 1007 | |
| 1008 | /* Now, scan the prologue and obtain the frame register. */ |
| 1009 | deprecated_update_frame_pc_hack (caller_fi, caller_pc); |
| 1010 | arm_scan_prologue (caller_fi); |
| 1011 | framereg = get_frame_extra_info (caller_fi)->framereg; |
| 1012 | |
| 1013 | /* Deallocate the storage associated with the temporary frame |
| 1014 | created above. */ |
| 1015 | do_cleanups (old_chain); |
| 1016 | } |
| 1017 | |
| 1018 | /* If the caller used a frame register, return its value. |
| 1019 | Otherwise, return the caller's stack pointer. */ |
| 1020 | if (framereg == ARM_FP_REGNUM || framereg == THUMB_FP_REGNUM) |
| 1021 | return arm_find_callers_reg (fi, framereg); |
| 1022 | else |
| 1023 | return get_frame_base (fi) + get_frame_extra_info (fi)->framesize; |
| 1024 | } |
| 1025 | |
| 1026 | /* This function actually figures out the frame address for a given pc |
| 1027 | and sp. This is tricky because we sometimes don't use an explicit |
| 1028 | frame pointer, and the previous stack pointer isn't necessarily |
| 1029 | recorded on the stack. The only reliable way to get this info is |
| 1030 | to examine the prologue. FROMLEAF is a little confusing, it means |
| 1031 | this is the next frame up the chain AFTER a frameless function. If |
| 1032 | this is true, then the frame value for this frame is still in the |
| 1033 | fp register. */ |
| 1034 | |
| 1035 | static void |
| 1036 | arm_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
| 1037 | { |
| 1038 | int reg; |
| 1039 | CORE_ADDR sp; |
| 1040 | |
| 1041 | if (get_frame_saved_regs (fi) == NULL) |
| 1042 | frame_saved_regs_zalloc (fi); |
| 1043 | |
| 1044 | frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info)); |
| 1045 | |
| 1046 | get_frame_extra_info (fi)->framesize = 0; |
| 1047 | get_frame_extra_info (fi)->frameoffset = 0; |
| 1048 | get_frame_extra_info (fi)->framereg = 0; |
| 1049 | |
| 1050 | if (get_next_frame (fi)) |
| 1051 | deprecated_update_frame_pc_hack (fi, DEPRECATED_FRAME_SAVED_PC (get_next_frame (fi))); |
| 1052 | |
| 1053 | memset (get_frame_saved_regs (fi), '\000', sizeof get_frame_saved_regs (fi)); |
| 1054 | |
| 1055 | /* Compute stack pointer for this frame. We use this value for both |
| 1056 | the sigtramp and call dummy cases. */ |
| 1057 | if (!get_next_frame (fi)) |
| 1058 | sp = read_sp(); |
| 1059 | else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (get_next_frame (fi)), 0, 0)) |
| 1060 | /* For generic dummy frames, pull the value direct from the frame. |
| 1061 | Having an unwind function to do this would be nice. */ |
| 1062 | sp = deprecated_read_register_dummy (get_frame_pc (get_next_frame (fi)), |
| 1063 | get_frame_base (get_next_frame (fi)), |
| 1064 | ARM_SP_REGNUM); |
| 1065 | else |
| 1066 | sp = (get_frame_base (get_next_frame (fi)) |
| 1067 | - get_frame_extra_info (get_next_frame (fi))->frameoffset |
| 1068 | + get_frame_extra_info (get_next_frame (fi))->framesize); |
| 1069 | |
| 1070 | /* Determine whether or not we're in a sigtramp frame. |
| 1071 | Unfortunately, it isn't sufficient to test (get_frame_type (fi) |
| 1072 | == SIGTRAMP_FRAME) because this value is sometimes set after |
| 1073 | invoking DEPRECATED_INIT_EXTRA_FRAME_INFO. So we test *both* |
| 1074 | (get_frame_type (fi) == SIGTRAMP_FRAME) and PC_IN_SIGTRAMP to |
| 1075 | determine if we need to use the sigcontext addresses for the |
| 1076 | saved registers. |
| 1077 | |
| 1078 | Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare |
| 1079 | against the name of the function, the code below will have to be |
| 1080 | changed to first fetch the name of the function and then pass |
| 1081 | this name to PC_IN_SIGTRAMP. */ |
| 1082 | |
| 1083 | /* FIXME: cagney/2002-11-18: This problem will go away once |
| 1084 | frame.c:get_prev_frame() is modified to set the frame's type |
| 1085 | before calling functions like this. */ |
| 1086 | |
| 1087 | if (SIGCONTEXT_REGISTER_ADDRESS_P () |
| 1088 | && ((get_frame_type (fi) == SIGTRAMP_FRAME) || PC_IN_SIGTRAMP (get_frame_pc (fi), (char *)0))) |
| 1089 | { |
| 1090 | for (reg = 0; reg < NUM_REGS; reg++) |
| 1091 | get_frame_saved_regs (fi)[reg] = SIGCONTEXT_REGISTER_ADDRESS (sp, get_frame_pc (fi), reg); |
| 1092 | |
| 1093 | /* FIXME: What about thumb mode? */ |
| 1094 | get_frame_extra_info (fi)->framereg = ARM_SP_REGNUM; |
| 1095 | deprecated_update_frame_base_hack (fi, read_memory_integer (get_frame_saved_regs (fi)[get_frame_extra_info (fi)->framereg], REGISTER_RAW_SIZE (get_frame_extra_info (fi)->framereg))); |
| 1096 | get_frame_extra_info (fi)->framesize = 0; |
| 1097 | get_frame_extra_info (fi)->frameoffset = 0; |
| 1098 | |
| 1099 | } |
| 1100 | else |
| 1101 | { |
| 1102 | arm_scan_prologue (fi); |
| 1103 | |
| 1104 | if (!get_next_frame (fi)) |
| 1105 | /* This is the innermost frame? */ |
| 1106 | deprecated_update_frame_base_hack (fi, read_register (get_frame_extra_info (fi)->framereg)); |
| 1107 | else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (get_next_frame (fi)), 0, 0)) |
| 1108 | /* Next inner most frame is a dummy, just grab its frame. |
| 1109 | Dummy frames always have the same FP as their caller. */ |
| 1110 | deprecated_update_frame_base_hack (fi, get_frame_base (get_next_frame (fi))); |
| 1111 | else if (get_frame_extra_info (fi)->framereg == ARM_FP_REGNUM |
| 1112 | || get_frame_extra_info (fi)->framereg == THUMB_FP_REGNUM) |
| 1113 | { |
| 1114 | /* not the innermost frame */ |
| 1115 | /* If we have an FP, the callee saved it. */ |
| 1116 | if (get_frame_saved_regs (get_next_frame (fi))[get_frame_extra_info (fi)->framereg] != 0) |
| 1117 | deprecated_update_frame_base_hack (fi, read_memory_integer (get_frame_saved_regs (get_next_frame (fi))[get_frame_extra_info (fi)->framereg], 4)); |
| 1118 | else if (fromleaf) |
| 1119 | /* If we were called by a frameless fn. then our frame is |
| 1120 | still in the frame pointer register on the board... */ |
| 1121 | deprecated_update_frame_base_hack (fi, read_fp ()); |
| 1122 | } |
| 1123 | |
| 1124 | /* Calculate actual addresses of saved registers using offsets |
| 1125 | determined by arm_scan_prologue. */ |
| 1126 | for (reg = 0; reg < NUM_REGS; reg++) |
| 1127 | if (get_frame_saved_regs (fi)[reg] != 0) |
| 1128 | get_frame_saved_regs (fi)[reg] |
| 1129 | += (get_frame_base (fi) |
| 1130 | + get_frame_extra_info (fi)->framesize |
| 1131 | - get_frame_extra_info (fi)->frameoffset); |
| 1132 | } |
| 1133 | } |
| 1134 | |
| 1135 | |
| 1136 | /* Find the caller of this frame. We do this by seeing if ARM_LR_REGNUM |
| 1137 | is saved in the stack anywhere, otherwise we get it from the |
| 1138 | registers. |
| 1139 | |
| 1140 | The old definition of this function was a macro: |
| 1141 | #define FRAME_SAVED_PC(FRAME) \ |
| 1142 | ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */ |
| 1143 | |
| 1144 | static CORE_ADDR |
| 1145 | arm_frame_saved_pc (struct frame_info *fi) |
| 1146 | { |
| 1147 | /* If a dummy frame, pull the PC out of the frame's register buffer. */ |
| 1148 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0)) |
| 1149 | return deprecated_read_register_dummy (get_frame_pc (fi), |
| 1150 | get_frame_base (fi), ARM_PC_REGNUM); |
| 1151 | |
| 1152 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), |
| 1153 | (get_frame_base (fi) |
| 1154 | - get_frame_extra_info (fi)->frameoffset), |
| 1155 | get_frame_base (fi))) |
| 1156 | { |
| 1157 | return read_memory_integer (get_frame_saved_regs (fi)[ARM_PC_REGNUM], |
| 1158 | REGISTER_RAW_SIZE (ARM_PC_REGNUM)); |
| 1159 | } |
| 1160 | else |
| 1161 | { |
| 1162 | CORE_ADDR pc = arm_find_callers_reg (fi, ARM_LR_REGNUM); |
| 1163 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; |
| 1164 | } |
| 1165 | } |
| 1166 | |
| 1167 | /* Return the frame address. On ARM, it is R11; on Thumb it is R7. |
| 1168 | Examine the Program Status Register to decide which state we're in. */ |
| 1169 | |
| 1170 | static CORE_ADDR |
| 1171 | arm_read_fp (void) |
| 1172 | { |
| 1173 | if (read_register (ARM_PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */ |
| 1174 | return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */ |
| 1175 | else |
| 1176 | return read_register (ARM_FP_REGNUM); /* R11 if ARM */ |
| 1177 | } |
| 1178 | |
| 1179 | /* Store into a struct frame_saved_regs the addresses of the saved |
| 1180 | registers of frame described by FRAME_INFO. This includes special |
| 1181 | registers such as PC and FP saved in special ways in the stack |
| 1182 | frame. SP is even more special: the address we return for it IS |
| 1183 | the sp for the next frame. */ |
| 1184 | |
| 1185 | static void |
| 1186 | arm_frame_init_saved_regs (struct frame_info *fip) |
| 1187 | { |
| 1188 | |
| 1189 | if (get_frame_saved_regs (fip)) |
| 1190 | return; |
| 1191 | |
| 1192 | arm_init_extra_frame_info (0, fip); |
| 1193 | } |
| 1194 | |
| 1195 | /* Set the return address for a generic dummy frame. ARM uses the |
| 1196 | entry point. */ |
| 1197 | |
| 1198 | static CORE_ADDR |
| 1199 | arm_push_return_address (CORE_ADDR pc, CORE_ADDR sp) |
| 1200 | { |
| 1201 | write_register (ARM_LR_REGNUM, CALL_DUMMY_ADDRESS ()); |
| 1202 | return sp; |
| 1203 | } |
| 1204 | |
| 1205 | /* Push an empty stack frame, to record the current PC, etc. */ |
| 1206 | |
| 1207 | static void |
| 1208 | arm_push_dummy_frame (void) |
| 1209 | { |
| 1210 | CORE_ADDR old_sp = read_register (ARM_SP_REGNUM); |
| 1211 | CORE_ADDR sp = old_sp; |
| 1212 | CORE_ADDR fp, prologue_start; |
| 1213 | int regnum; |
| 1214 | |
| 1215 | /* Push the two dummy prologue instructions in reverse order, |
| 1216 | so that they'll be in the correct low-to-high order in memory. */ |
| 1217 | /* sub fp, ip, #4 */ |
| 1218 | sp = push_word (sp, 0xe24cb004); |
| 1219 | /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */ |
| 1220 | prologue_start = sp = push_word (sp, 0xe92ddfff); |
| 1221 | |
| 1222 | /* Push a pointer to the dummy prologue + 12, because when stm |
| 1223 | instruction stores the PC, it stores the address of the stm |
| 1224 | instruction itself plus 12. */ |
| 1225 | fp = sp = push_word (sp, prologue_start + 12); |
| 1226 | |
| 1227 | /* Push the processor status. */ |
| 1228 | sp = push_word (sp, read_register (ARM_PS_REGNUM)); |
| 1229 | |
| 1230 | /* Push all 16 registers starting with r15. */ |
| 1231 | for (regnum = ARM_PC_REGNUM; regnum >= 0; regnum--) |
| 1232 | sp = push_word (sp, read_register (regnum)); |
| 1233 | |
| 1234 | /* Update fp (for both Thumb and ARM) and sp. */ |
| 1235 | write_register (ARM_FP_REGNUM, fp); |
| 1236 | write_register (THUMB_FP_REGNUM, fp); |
| 1237 | write_register (ARM_SP_REGNUM, sp); |
| 1238 | } |
| 1239 | |
| 1240 | /* CALL_DUMMY_WORDS: |
| 1241 | This sequence of words is the instructions |
| 1242 | |
| 1243 | mov lr,pc |
| 1244 | mov pc,r4 |
| 1245 | illegal |
| 1246 | |
| 1247 | Note this is 12 bytes. */ |
| 1248 | |
| 1249 | static LONGEST arm_call_dummy_words[] = |
| 1250 | { |
| 1251 | 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe |
| 1252 | }; |
| 1253 | |
| 1254 | /* Adjust the call_dummy_breakpoint_offset for the bp_call_dummy |
| 1255 | breakpoint to the proper address in the call dummy, so that |
| 1256 | `finish' after a stop in a call dummy works. |
| 1257 | |
| 1258 | FIXME rearnsha 2002-02018: Tweeking current_gdbarch is not an |
| 1259 | optimal solution, but the call to arm_fix_call_dummy is immediately |
| 1260 | followed by a call to run_stack_dummy, which is the only function |
| 1261 | where call_dummy_breakpoint_offset is actually used. */ |
| 1262 | |
| 1263 | |
| 1264 | static void |
| 1265 | arm_set_call_dummy_breakpoint_offset (void) |
| 1266 | { |
| 1267 | if (caller_is_thumb) |
| 1268 | set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 4); |
| 1269 | else |
| 1270 | set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 8); |
| 1271 | } |
| 1272 | |
| 1273 | /* Fix up the call dummy, based on whether the processor is currently |
| 1274 | in Thumb or ARM mode, and whether the target function is Thumb or |
| 1275 | ARM. There are three different situations requiring three |
| 1276 | different dummies: |
| 1277 | |
| 1278 | * ARM calling ARM: uses the call dummy in tm-arm.h, which has already |
| 1279 | been copied into the dummy parameter to this function. |
| 1280 | * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the |
| 1281 | "mov pc,r4" instruction patched to be a "bx r4" instead. |
| 1282 | * Thumb calling anything: uses the Thumb dummy defined below, which |
| 1283 | works for calling both ARM and Thumb functions. |
| 1284 | |
| 1285 | All three call dummies expect to receive the target function |
| 1286 | address in R4, with the low bit set if it's a Thumb function. */ |
| 1287 | |
| 1288 | static void |
| 1289 | arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs, |
| 1290 | struct value **args, struct type *type, int gcc_p) |
| 1291 | { |
| 1292 | static short thumb_dummy[4] = |
| 1293 | { |
| 1294 | 0xf000, 0xf801, /* bl label */ |
| 1295 | 0xdf18, /* swi 24 */ |
| 1296 | 0x4720, /* label: bx r4 */ |
| 1297 | }; |
| 1298 | static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */ |
| 1299 | |
| 1300 | /* Set flag indicating whether the current PC is in a Thumb function. */ |
| 1301 | caller_is_thumb = arm_pc_is_thumb (read_pc ()); |
| 1302 | arm_set_call_dummy_breakpoint_offset (); |
| 1303 | |
| 1304 | /* If the target function is Thumb, set the low bit of the function |
| 1305 | address. And if the CPU is currently in ARM mode, patch the |
| 1306 | second instruction of call dummy to use a BX instruction to |
| 1307 | switch to Thumb mode. */ |
| 1308 | target_is_thumb = arm_pc_is_thumb (fun); |
| 1309 | if (target_is_thumb) |
| 1310 | { |
| 1311 | fun |= 1; |
| 1312 | if (!caller_is_thumb) |
| 1313 | store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4); |
| 1314 | } |
| 1315 | |
| 1316 | /* If the CPU is currently in Thumb mode, use the Thumb call dummy |
| 1317 | instead of the ARM one that's already been copied. This will |
| 1318 | work for both Thumb and ARM target functions. */ |
| 1319 | if (caller_is_thumb) |
| 1320 | { |
| 1321 | int i; |
| 1322 | char *p = dummy; |
| 1323 | int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]); |
| 1324 | |
| 1325 | for (i = 0; i < len; i++) |
| 1326 | { |
| 1327 | store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]); |
| 1328 | p += sizeof (thumb_dummy[0]); |
| 1329 | } |
| 1330 | } |
| 1331 | |
| 1332 | /* Put the target address in r4; the call dummy will copy this to |
| 1333 | the PC. */ |
| 1334 | write_register (4, fun); |
| 1335 | } |
| 1336 | |
| 1337 | /* Note: ScottB |
| 1338 | |
| 1339 | This function does not support passing parameters using the FPA |
| 1340 | variant of the APCS. It passes any floating point arguments in the |
| 1341 | general registers and/or on the stack. */ |
| 1342 | |
| 1343 | static CORE_ADDR |
| 1344 | arm_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
| 1345 | int struct_return, CORE_ADDR struct_addr) |
| 1346 | { |
| 1347 | CORE_ADDR fp; |
| 1348 | int argnum; |
| 1349 | int argreg; |
| 1350 | int nstack; |
| 1351 | int simd_argreg; |
| 1352 | int second_pass; |
| 1353 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 1354 | |
| 1355 | /* Walk through the list of args and determine how large a temporary |
| 1356 | stack is required. Need to take care here as structs may be |
| 1357 | passed on the stack, and we have to to push them. On the second |
| 1358 | pass, do the store. */ |
| 1359 | nstack = 0; |
| 1360 | fp = sp; |
| 1361 | for (second_pass = 0; second_pass < 2; second_pass++) |
| 1362 | { |
| 1363 | /* Compute the FP using the information computed during the |
| 1364 | first pass. */ |
| 1365 | if (second_pass) |
| 1366 | fp = sp - nstack; |
| 1367 | |
| 1368 | simd_argreg = 0; |
| 1369 | argreg = ARM_A1_REGNUM; |
| 1370 | nstack = 0; |
| 1371 | |
| 1372 | /* The struct_return pointer occupies the first parameter |
| 1373 | passing register. */ |
| 1374 | if (struct_return) |
| 1375 | { |
| 1376 | if (second_pass) |
| 1377 | { |
| 1378 | if (arm_debug) |
| 1379 | fprintf_unfiltered (gdb_stdlog, |
| 1380 | "struct return in %s = 0x%s\n", |
| 1381 | REGISTER_NAME (argreg), |
| 1382 | paddr (struct_addr)); |
| 1383 | write_register (argreg, struct_addr); |
| 1384 | } |
| 1385 | argreg++; |
| 1386 | } |
| 1387 | |
| 1388 | for (argnum = 0; argnum < nargs; argnum++) |
| 1389 | { |
| 1390 | int len; |
| 1391 | struct type *arg_type; |
| 1392 | struct type *target_type; |
| 1393 | enum type_code typecode; |
| 1394 | char *val; |
| 1395 | |
| 1396 | arg_type = check_typedef (VALUE_TYPE (args[argnum])); |
| 1397 | len = TYPE_LENGTH (arg_type); |
| 1398 | target_type = TYPE_TARGET_TYPE (arg_type); |
| 1399 | typecode = TYPE_CODE (arg_type); |
| 1400 | val = VALUE_CONTENTS (args[argnum]); |
| 1401 | |
| 1402 | /* If the argument is a pointer to a function, and it is a |
| 1403 | Thumb function, create a LOCAL copy of the value and set |
| 1404 | the THUMB bit in it. */ |
| 1405 | if (second_pass |
| 1406 | && TYPE_CODE_PTR == typecode |
| 1407 | && target_type != NULL |
| 1408 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) |
| 1409 | { |
| 1410 | CORE_ADDR regval = extract_address (val, len); |
| 1411 | if (arm_pc_is_thumb (regval)) |
| 1412 | { |
| 1413 | val = alloca (len); |
| 1414 | store_address (val, len, MAKE_THUMB_ADDR (regval)); |
| 1415 | } |
| 1416 | } |
| 1417 | |
| 1418 | /* Copy the argument to general registers or the stack in |
| 1419 | register-sized pieces. Large arguments are split between |
| 1420 | registers and stack. */ |
| 1421 | while (len > 0) |
| 1422 | { |
| 1423 | int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE; |
| 1424 | |
| 1425 | if (argreg <= ARM_LAST_ARG_REGNUM) |
| 1426 | { |
| 1427 | /* The argument is being passed in a general purpose |
| 1428 | register. */ |
| 1429 | if (second_pass) |
| 1430 | { |
| 1431 | CORE_ADDR regval = extract_address (val, |
| 1432 | partial_len); |
| 1433 | if (arm_debug) |
| 1434 | fprintf_unfiltered (gdb_stdlog, |
| 1435 | "arg %d in %s = 0x%s\n", |
| 1436 | argnum, |
| 1437 | REGISTER_NAME (argreg), |
| 1438 | phex (regval, REGISTER_SIZE)); |
| 1439 | write_register (argreg, regval); |
| 1440 | } |
| 1441 | argreg++; |
| 1442 | } |
| 1443 | else |
| 1444 | { |
| 1445 | if (second_pass) |
| 1446 | { |
| 1447 | /* Push the arguments onto the stack. */ |
| 1448 | if (arm_debug) |
| 1449 | fprintf_unfiltered (gdb_stdlog, |
| 1450 | "arg %d @ 0x%s + %d\n", |
| 1451 | argnum, paddr (fp), nstack); |
| 1452 | write_memory (fp + nstack, val, REGISTER_SIZE); |
| 1453 | } |
| 1454 | nstack += REGISTER_SIZE; |
| 1455 | } |
| 1456 | |
| 1457 | len -= partial_len; |
| 1458 | val += partial_len; |
| 1459 | } |
| 1460 | |
| 1461 | } |
| 1462 | } |
| 1463 | |
| 1464 | /* Return the bottom of the argument list (pointed to by fp). */ |
| 1465 | return fp; |
| 1466 | } |
| 1467 | |
| 1468 | /* Pop the current frame. So long as the frame info has been |
| 1469 | initialized properly (see arm_init_extra_frame_info), this code |
| 1470 | works for dummy frames as well as regular frames. I.e, there's no |
| 1471 | need to have a special case for dummy frames. */ |
| 1472 | static void |
| 1473 | arm_pop_frame (void) |
| 1474 | { |
| 1475 | int regnum; |
| 1476 | struct frame_info *frame = get_current_frame (); |
| 1477 | CORE_ADDR old_SP = (get_frame_base (frame) |
| 1478 | - get_frame_extra_info (frame)->frameoffset |
| 1479 | + get_frame_extra_info (frame)->framesize); |
| 1480 | |
| 1481 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), |
| 1482 | get_frame_base (frame), |
| 1483 | get_frame_base (frame))) |
| 1484 | { |
| 1485 | generic_pop_dummy_frame (); |
| 1486 | flush_cached_frames (); |
| 1487 | return; |
| 1488 | } |
| 1489 | |
| 1490 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
| 1491 | if (get_frame_saved_regs (frame)[regnum] != 0) |
| 1492 | write_register (regnum, |
| 1493 | read_memory_integer (get_frame_saved_regs (frame)[regnum], |
| 1494 | REGISTER_RAW_SIZE (regnum))); |
| 1495 | |
| 1496 | write_register (ARM_PC_REGNUM, DEPRECATED_FRAME_SAVED_PC (frame)); |
| 1497 | write_register (ARM_SP_REGNUM, old_SP); |
| 1498 | |
| 1499 | flush_cached_frames (); |
| 1500 | } |
| 1501 | |
| 1502 | static void |
| 1503 | print_fpu_flags (int flags) |
| 1504 | { |
| 1505 | if (flags & (1 << 0)) |
| 1506 | fputs ("IVO ", stdout); |
| 1507 | if (flags & (1 << 1)) |
| 1508 | fputs ("DVZ ", stdout); |
| 1509 | if (flags & (1 << 2)) |
| 1510 | fputs ("OFL ", stdout); |
| 1511 | if (flags & (1 << 3)) |
| 1512 | fputs ("UFL ", stdout); |
| 1513 | if (flags & (1 << 4)) |
| 1514 | fputs ("INX ", stdout); |
| 1515 | putchar ('\n'); |
| 1516 | } |
| 1517 | |
| 1518 | /* Print interesting information about the floating point processor |
| 1519 | (if present) or emulator. */ |
| 1520 | static void |
| 1521 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
| 1522 | struct frame_info *frame, const char *args) |
| 1523 | { |
| 1524 | register unsigned long status = read_register (ARM_FPS_REGNUM); |
| 1525 | int type; |
| 1526 | |
| 1527 | type = (status >> 24) & 127; |
| 1528 | printf ("%s FPU type %d\n", |
| 1529 | (status & (1 << 31)) ? "Hardware" : "Software", |
| 1530 | type); |
| 1531 | fputs ("mask: ", stdout); |
| 1532 | print_fpu_flags (status >> 16); |
| 1533 | fputs ("flags: ", stdout); |
| 1534 | print_fpu_flags (status); |
| 1535 | } |
| 1536 | |
| 1537 | /* Return the GDB type object for the "standard" data type of data in |
| 1538 | register N. */ |
| 1539 | |
| 1540 | static struct type * |
| 1541 | arm_register_type (int regnum) |
| 1542 | { |
| 1543 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
| 1544 | { |
| 1545 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
| 1546 | return builtin_type_arm_ext_big; |
| 1547 | else |
| 1548 | return builtin_type_arm_ext_littlebyte_bigword; |
| 1549 | } |
| 1550 | else |
| 1551 | return builtin_type_int32; |
| 1552 | } |
| 1553 | |
| 1554 | /* Index within `registers' of the first byte of the space for |
| 1555 | register N. */ |
| 1556 | |
| 1557 | static int |
| 1558 | arm_register_byte (int regnum) |
| 1559 | { |
| 1560 | if (regnum < ARM_F0_REGNUM) |
| 1561 | return regnum * INT_REGISTER_RAW_SIZE; |
| 1562 | else if (regnum < ARM_PS_REGNUM) |
| 1563 | return (NUM_GREGS * INT_REGISTER_RAW_SIZE |
| 1564 | + (regnum - ARM_F0_REGNUM) * FP_REGISTER_RAW_SIZE); |
| 1565 | else |
| 1566 | return (NUM_GREGS * INT_REGISTER_RAW_SIZE |
| 1567 | + NUM_FREGS * FP_REGISTER_RAW_SIZE |
| 1568 | + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE); |
| 1569 | } |
| 1570 | |
| 1571 | /* Number of bytes of storage in the actual machine representation for |
| 1572 | register N. All registers are 4 bytes, except fp0 - fp7, which are |
| 1573 | 12 bytes in length. */ |
| 1574 | |
| 1575 | static int |
| 1576 | arm_register_raw_size (int regnum) |
| 1577 | { |
| 1578 | if (regnum < ARM_F0_REGNUM) |
| 1579 | return INT_REGISTER_RAW_SIZE; |
| 1580 | else if (regnum < ARM_FPS_REGNUM) |
| 1581 | return FP_REGISTER_RAW_SIZE; |
| 1582 | else |
| 1583 | return STATUS_REGISTER_SIZE; |
| 1584 | } |
| 1585 | |
| 1586 | /* Number of bytes of storage in a program's representation |
| 1587 | for register N. */ |
| 1588 | static int |
| 1589 | arm_register_virtual_size (int regnum) |
| 1590 | { |
| 1591 | if (regnum < ARM_F0_REGNUM) |
| 1592 | return INT_REGISTER_VIRTUAL_SIZE; |
| 1593 | else if (regnum < ARM_FPS_REGNUM) |
| 1594 | return FP_REGISTER_VIRTUAL_SIZE; |
| 1595 | else |
| 1596 | return STATUS_REGISTER_SIZE; |
| 1597 | } |
| 1598 | |
| 1599 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
| 1600 | static int |
| 1601 | arm_register_sim_regno (int regnum) |
| 1602 | { |
| 1603 | int reg = regnum; |
| 1604 | gdb_assert (reg >= 0 && reg < NUM_REGS); |
| 1605 | |
| 1606 | if (reg < NUM_GREGS) |
| 1607 | return SIM_ARM_R0_REGNUM + reg; |
| 1608 | reg -= NUM_GREGS; |
| 1609 | |
| 1610 | if (reg < NUM_FREGS) |
| 1611 | return SIM_ARM_FP0_REGNUM + reg; |
| 1612 | reg -= NUM_FREGS; |
| 1613 | |
| 1614 | if (reg < NUM_SREGS) |
| 1615 | return SIM_ARM_FPS_REGNUM + reg; |
| 1616 | reg -= NUM_SREGS; |
| 1617 | |
| 1618 | internal_error (__FILE__, __LINE__, "Bad REGNUM %d", regnum); |
| 1619 | } |
| 1620 | |
| 1621 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
| 1622 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. |
| 1623 | It is thought that this is is the floating-point register format on |
| 1624 | little-endian systems. */ |
| 1625 | |
| 1626 | static void |
| 1627 | convert_from_extended (const struct floatformat *fmt, const void *ptr, |
| 1628 | void *dbl) |
| 1629 | { |
| 1630 | DOUBLEST d; |
| 1631 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
| 1632 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
| 1633 | else |
| 1634 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, |
| 1635 | ptr, &d); |
| 1636 | floatformat_from_doublest (fmt, &d, dbl); |
| 1637 | } |
| 1638 | |
| 1639 | static void |
| 1640 | convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr) |
| 1641 | { |
| 1642 | DOUBLEST d; |
| 1643 | floatformat_to_doublest (fmt, ptr, &d); |
| 1644 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
| 1645 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
| 1646 | else |
| 1647 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, |
| 1648 | &d, dbl); |
| 1649 | } |
| 1650 | |
| 1651 | static int |
| 1652 | condition_true (unsigned long cond, unsigned long status_reg) |
| 1653 | { |
| 1654 | if (cond == INST_AL || cond == INST_NV) |
| 1655 | return 1; |
| 1656 | |
| 1657 | switch (cond) |
| 1658 | { |
| 1659 | case INST_EQ: |
| 1660 | return ((status_reg & FLAG_Z) != 0); |
| 1661 | case INST_NE: |
| 1662 | return ((status_reg & FLAG_Z) == 0); |
| 1663 | case INST_CS: |
| 1664 | return ((status_reg & FLAG_C) != 0); |
| 1665 | case INST_CC: |
| 1666 | return ((status_reg & FLAG_C) == 0); |
| 1667 | case INST_MI: |
| 1668 | return ((status_reg & FLAG_N) != 0); |
| 1669 | case INST_PL: |
| 1670 | return ((status_reg & FLAG_N) == 0); |
| 1671 | case INST_VS: |
| 1672 | return ((status_reg & FLAG_V) != 0); |
| 1673 | case INST_VC: |
| 1674 | return ((status_reg & FLAG_V) == 0); |
| 1675 | case INST_HI: |
| 1676 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); |
| 1677 | case INST_LS: |
| 1678 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); |
| 1679 | case INST_GE: |
| 1680 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); |
| 1681 | case INST_LT: |
| 1682 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); |
| 1683 | case INST_GT: |
| 1684 | return (((status_reg & FLAG_Z) == 0) && |
| 1685 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
| 1686 | case INST_LE: |
| 1687 | return (((status_reg & FLAG_Z) != 0) || |
| 1688 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
| 1689 | } |
| 1690 | return 1; |
| 1691 | } |
| 1692 | |
| 1693 | /* Support routines for single stepping. Calculate the next PC value. */ |
| 1694 | #define submask(x) ((1L << ((x) + 1)) - 1) |
| 1695 | #define bit(obj,st) (((obj) >> (st)) & 1) |
| 1696 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) |
| 1697 | #define sbits(obj,st,fn) \ |
| 1698 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) |
| 1699 | #define BranchDest(addr,instr) \ |
| 1700 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) |
| 1701 | #define ARM_PC_32 1 |
| 1702 | |
| 1703 | static unsigned long |
| 1704 | shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, |
| 1705 | unsigned long status_reg) |
| 1706 | { |
| 1707 | unsigned long res, shift; |
| 1708 | int rm = bits (inst, 0, 3); |
| 1709 | unsigned long shifttype = bits (inst, 5, 6); |
| 1710 | |
| 1711 | if (bit (inst, 4)) |
| 1712 | { |
| 1713 | int rs = bits (inst, 8, 11); |
| 1714 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; |
| 1715 | } |
| 1716 | else |
| 1717 | shift = bits (inst, 7, 11); |
| 1718 | |
| 1719 | res = (rm == 15 |
| 1720 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
| 1721 | + (bit (inst, 4) ? 12 : 8)) |
| 1722 | : read_register (rm)); |
| 1723 | |
| 1724 | switch (shifttype) |
| 1725 | { |
| 1726 | case 0: /* LSL */ |
| 1727 | res = shift >= 32 ? 0 : res << shift; |
| 1728 | break; |
| 1729 | |
| 1730 | case 1: /* LSR */ |
| 1731 | res = shift >= 32 ? 0 : res >> shift; |
| 1732 | break; |
| 1733 | |
| 1734 | case 2: /* ASR */ |
| 1735 | if (shift >= 32) |
| 1736 | shift = 31; |
| 1737 | res = ((res & 0x80000000L) |
| 1738 | ? ~((~res) >> shift) : res >> shift); |
| 1739 | break; |
| 1740 | |
| 1741 | case 3: /* ROR/RRX */ |
| 1742 | shift &= 31; |
| 1743 | if (shift == 0) |
| 1744 | res = (res >> 1) | (carry ? 0x80000000L : 0); |
| 1745 | else |
| 1746 | res = (res >> shift) | (res << (32 - shift)); |
| 1747 | break; |
| 1748 | } |
| 1749 | |
| 1750 | return res & 0xffffffff; |
| 1751 | } |
| 1752 | |
| 1753 | /* Return number of 1-bits in VAL. */ |
| 1754 | |
| 1755 | static int |
| 1756 | bitcount (unsigned long val) |
| 1757 | { |
| 1758 | int nbits; |
| 1759 | for (nbits = 0; val != 0; nbits++) |
| 1760 | val &= val - 1; /* delete rightmost 1-bit in val */ |
| 1761 | return nbits; |
| 1762 | } |
| 1763 | |
| 1764 | CORE_ADDR |
| 1765 | thumb_get_next_pc (CORE_ADDR pc) |
| 1766 | { |
| 1767 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
| 1768 | unsigned short inst1 = read_memory_integer (pc, 2); |
| 1769 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
| 1770 | unsigned long offset; |
| 1771 | |
| 1772 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ |
| 1773 | { |
| 1774 | CORE_ADDR sp; |
| 1775 | |
| 1776 | /* Fetch the saved PC from the stack. It's stored above |
| 1777 | all of the other registers. */ |
| 1778 | offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE; |
| 1779 | sp = read_register (ARM_SP_REGNUM); |
| 1780 | nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4); |
| 1781 | nextpc = ADDR_BITS_REMOVE (nextpc); |
| 1782 | if (nextpc == pc) |
| 1783 | error ("Infinite loop detected"); |
| 1784 | } |
| 1785 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ |
| 1786 | { |
| 1787 | unsigned long status = read_register (ARM_PS_REGNUM); |
| 1788 | unsigned long cond = bits (inst1, 8, 11); |
| 1789 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
| 1790 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
| 1791 | } |
| 1792 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ |
| 1793 | { |
| 1794 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); |
| 1795 | } |
| 1796 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */ |
| 1797 | { |
| 1798 | unsigned short inst2 = read_memory_integer (pc + 2, 2); |
| 1799 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
| 1800 | nextpc = pc_val + offset; |
| 1801 | } |
| 1802 | |
| 1803 | return nextpc; |
| 1804 | } |
| 1805 | |
| 1806 | CORE_ADDR |
| 1807 | arm_get_next_pc (CORE_ADDR pc) |
| 1808 | { |
| 1809 | unsigned long pc_val; |
| 1810 | unsigned long this_instr; |
| 1811 | unsigned long status; |
| 1812 | CORE_ADDR nextpc; |
| 1813 | |
| 1814 | if (arm_pc_is_thumb (pc)) |
| 1815 | return thumb_get_next_pc (pc); |
| 1816 | |
| 1817 | pc_val = (unsigned long) pc; |
| 1818 | this_instr = read_memory_integer (pc, 4); |
| 1819 | status = read_register (ARM_PS_REGNUM); |
| 1820 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
| 1821 | |
| 1822 | if (condition_true (bits (this_instr, 28, 31), status)) |
| 1823 | { |
| 1824 | switch (bits (this_instr, 24, 27)) |
| 1825 | { |
| 1826 | case 0x0: |
| 1827 | case 0x1: /* data processing */ |
| 1828 | case 0x2: |
| 1829 | case 0x3: |
| 1830 | { |
| 1831 | unsigned long operand1, operand2, result = 0; |
| 1832 | unsigned long rn; |
| 1833 | int c; |
| 1834 | |
| 1835 | if (bits (this_instr, 12, 15) != 15) |
| 1836 | break; |
| 1837 | |
| 1838 | if (bits (this_instr, 22, 25) == 0 |
| 1839 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
| 1840 | error ("Illegal update to pc in instruction"); |
| 1841 | |
| 1842 | /* Multiply into PC */ |
| 1843 | c = (status & FLAG_C) ? 1 : 0; |
| 1844 | rn = bits (this_instr, 16, 19); |
| 1845 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); |
| 1846 | |
| 1847 | if (bit (this_instr, 25)) |
| 1848 | { |
| 1849 | unsigned long immval = bits (this_instr, 0, 7); |
| 1850 | unsigned long rotate = 2 * bits (this_instr, 8, 11); |
| 1851 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
| 1852 | & 0xffffffff; |
| 1853 | } |
| 1854 | else /* operand 2 is a shifted register */ |
| 1855 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
| 1856 | |
| 1857 | switch (bits (this_instr, 21, 24)) |
| 1858 | { |
| 1859 | case 0x0: /*and */ |
| 1860 | result = operand1 & operand2; |
| 1861 | break; |
| 1862 | |
| 1863 | case 0x1: /*eor */ |
| 1864 | result = operand1 ^ operand2; |
| 1865 | break; |
| 1866 | |
| 1867 | case 0x2: /*sub */ |
| 1868 | result = operand1 - operand2; |
| 1869 | break; |
| 1870 | |
| 1871 | case 0x3: /*rsb */ |
| 1872 | result = operand2 - operand1; |
| 1873 | break; |
| 1874 | |
| 1875 | case 0x4: /*add */ |
| 1876 | result = operand1 + operand2; |
| 1877 | break; |
| 1878 | |
| 1879 | case 0x5: /*adc */ |
| 1880 | result = operand1 + operand2 + c; |
| 1881 | break; |
| 1882 | |
| 1883 | case 0x6: /*sbc */ |
| 1884 | result = operand1 - operand2 + c; |
| 1885 | break; |
| 1886 | |
| 1887 | case 0x7: /*rsc */ |
| 1888 | result = operand2 - operand1 + c; |
| 1889 | break; |
| 1890 | |
| 1891 | case 0x8: |
| 1892 | case 0x9: |
| 1893 | case 0xa: |
| 1894 | case 0xb: /* tst, teq, cmp, cmn */ |
| 1895 | result = (unsigned long) nextpc; |
| 1896 | break; |
| 1897 | |
| 1898 | case 0xc: /*orr */ |
| 1899 | result = operand1 | operand2; |
| 1900 | break; |
| 1901 | |
| 1902 | case 0xd: /*mov */ |
| 1903 | /* Always step into a function. */ |
| 1904 | result = operand2; |
| 1905 | break; |
| 1906 | |
| 1907 | case 0xe: /*bic */ |
| 1908 | result = operand1 & ~operand2; |
| 1909 | break; |
| 1910 | |
| 1911 | case 0xf: /*mvn */ |
| 1912 | result = ~operand2; |
| 1913 | break; |
| 1914 | } |
| 1915 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); |
| 1916 | |
| 1917 | if (nextpc == pc) |
| 1918 | error ("Infinite loop detected"); |
| 1919 | break; |
| 1920 | } |
| 1921 | |
| 1922 | case 0x4: |
| 1923 | case 0x5: /* data transfer */ |
| 1924 | case 0x6: |
| 1925 | case 0x7: |
| 1926 | if (bit (this_instr, 20)) |
| 1927 | { |
| 1928 | /* load */ |
| 1929 | if (bits (this_instr, 12, 15) == 15) |
| 1930 | { |
| 1931 | /* rd == pc */ |
| 1932 | unsigned long rn; |
| 1933 | unsigned long base; |
| 1934 | |
| 1935 | if (bit (this_instr, 22)) |
| 1936 | error ("Illegal update to pc in instruction"); |
| 1937 | |
| 1938 | /* byte write to PC */ |
| 1939 | rn = bits (this_instr, 16, 19); |
| 1940 | base = (rn == 15) ? pc_val + 8 : read_register (rn); |
| 1941 | if (bit (this_instr, 24)) |
| 1942 | { |
| 1943 | /* pre-indexed */ |
| 1944 | int c = (status & FLAG_C) ? 1 : 0; |
| 1945 | unsigned long offset = |
| 1946 | (bit (this_instr, 25) |
| 1947 | ? shifted_reg_val (this_instr, c, pc_val, status) |
| 1948 | : bits (this_instr, 0, 11)); |
| 1949 | |
| 1950 | if (bit (this_instr, 23)) |
| 1951 | base += offset; |
| 1952 | else |
| 1953 | base -= offset; |
| 1954 | } |
| 1955 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
| 1956 | 4); |
| 1957 | |
| 1958 | nextpc = ADDR_BITS_REMOVE (nextpc); |
| 1959 | |
| 1960 | if (nextpc == pc) |
| 1961 | error ("Infinite loop detected"); |
| 1962 | } |
| 1963 | } |
| 1964 | break; |
| 1965 | |
| 1966 | case 0x8: |
| 1967 | case 0x9: /* block transfer */ |
| 1968 | if (bit (this_instr, 20)) |
| 1969 | { |
| 1970 | /* LDM */ |
| 1971 | if (bit (this_instr, 15)) |
| 1972 | { |
| 1973 | /* loading pc */ |
| 1974 | int offset = 0; |
| 1975 | |
| 1976 | if (bit (this_instr, 23)) |
| 1977 | { |
| 1978 | /* up */ |
| 1979 | unsigned long reglist = bits (this_instr, 0, 14); |
| 1980 | offset = bitcount (reglist) * 4; |
| 1981 | if (bit (this_instr, 24)) /* pre */ |
| 1982 | offset += 4; |
| 1983 | } |
| 1984 | else if (bit (this_instr, 24)) |
| 1985 | offset = -4; |
| 1986 | |
| 1987 | { |
| 1988 | unsigned long rn_val = |
| 1989 | read_register (bits (this_instr, 16, 19)); |
| 1990 | nextpc = |
| 1991 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val |
| 1992 | + offset), |
| 1993 | 4); |
| 1994 | } |
| 1995 | nextpc = ADDR_BITS_REMOVE (nextpc); |
| 1996 | if (nextpc == pc) |
| 1997 | error ("Infinite loop detected"); |
| 1998 | } |
| 1999 | } |
| 2000 | break; |
| 2001 | |
| 2002 | case 0xb: /* branch & link */ |
| 2003 | case 0xa: /* branch */ |
| 2004 | { |
| 2005 | nextpc = BranchDest (pc, this_instr); |
| 2006 | |
| 2007 | nextpc = ADDR_BITS_REMOVE (nextpc); |
| 2008 | if (nextpc == pc) |
| 2009 | error ("Infinite loop detected"); |
| 2010 | break; |
| 2011 | } |
| 2012 | |
| 2013 | case 0xc: |
| 2014 | case 0xd: |
| 2015 | case 0xe: /* coproc ops */ |
| 2016 | case 0xf: /* SWI */ |
| 2017 | break; |
| 2018 | |
| 2019 | default: |
| 2020 | fprintf_filtered (gdb_stderr, "Bad bit-field extraction\n"); |
| 2021 | return (pc); |
| 2022 | } |
| 2023 | } |
| 2024 | |
| 2025 | return nextpc; |
| 2026 | } |
| 2027 | |
| 2028 | /* single_step() is called just before we want to resume the inferior, |
| 2029 | if we want to single-step it but there is no hardware or kernel |
| 2030 | single-step support. We find the target of the coming instruction |
| 2031 | and breakpoint it. |
| 2032 | |
| 2033 | single_step() is also called just after the inferior stops. If we |
| 2034 | had set up a simulated single-step, we undo our damage. */ |
| 2035 | |
| 2036 | static void |
| 2037 | arm_software_single_step (enum target_signal sig, int insert_bpt) |
| 2038 | { |
| 2039 | static int next_pc; /* State between setting and unsetting. */ |
| 2040 | static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */ |
| 2041 | |
| 2042 | if (insert_bpt) |
| 2043 | { |
| 2044 | next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM)); |
| 2045 | target_insert_breakpoint (next_pc, break_mem); |
| 2046 | } |
| 2047 | else |
| 2048 | target_remove_breakpoint (next_pc, break_mem); |
| 2049 | } |
| 2050 | |
| 2051 | #include "bfd-in2.h" |
| 2052 | #include "libcoff.h" |
| 2053 | |
| 2054 | static int |
| 2055 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
| 2056 | { |
| 2057 | if (arm_pc_is_thumb (memaddr)) |
| 2058 | { |
| 2059 | static asymbol *asym; |
| 2060 | static combined_entry_type ce; |
| 2061 | static struct coff_symbol_struct csym; |
| 2062 | static struct bfd fake_bfd; |
| 2063 | static bfd_target fake_target; |
| 2064 | |
| 2065 | if (csym.native == NULL) |
| 2066 | { |
| 2067 | /* Create a fake symbol vector containing a Thumb symbol. |
| 2068 | This is solely so that the code in print_insn_little_arm() |
| 2069 | and print_insn_big_arm() in opcodes/arm-dis.c will detect |
| 2070 | the presence of a Thumb symbol and switch to decoding |
| 2071 | Thumb instructions. */ |
| 2072 | |
| 2073 | fake_target.flavour = bfd_target_coff_flavour; |
| 2074 | fake_bfd.xvec = &fake_target; |
| 2075 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
| 2076 | csym.native = &ce; |
| 2077 | csym.symbol.the_bfd = &fake_bfd; |
| 2078 | csym.symbol.name = "fake"; |
| 2079 | asym = (asymbol *) & csym; |
| 2080 | } |
| 2081 | |
| 2082 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
| 2083 | info->symbols = &asym; |
| 2084 | } |
| 2085 | else |
| 2086 | info->symbols = NULL; |
| 2087 | |
| 2088 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
| 2089 | return print_insn_big_arm (memaddr, info); |
| 2090 | else |
| 2091 | return print_insn_little_arm (memaddr, info); |
| 2092 | } |
| 2093 | |
| 2094 | /* The following define instruction sequences that will cause ARM |
| 2095 | cpu's to take an undefined instruction trap. These are used to |
| 2096 | signal a breakpoint to GDB. |
| 2097 | |
| 2098 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb |
| 2099 | modes. A different instruction is required for each mode. The ARM |
| 2100 | cpu's can also be big or little endian. Thus four different |
| 2101 | instructions are needed to support all cases. |
| 2102 | |
| 2103 | Note: ARMv4 defines several new instructions that will take the |
| 2104 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does |
| 2105 | not in fact add the new instructions. The new undefined |
| 2106 | instructions in ARMv4 are all instructions that had no defined |
| 2107 | behaviour in earlier chips. There is no guarantee that they will |
| 2108 | raise an exception, but may be treated as NOP's. In practice, it |
| 2109 | may only safe to rely on instructions matching: |
| 2110 | |
| 2111 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 |
| 2112 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 |
| 2113 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x |
| 2114 | |
| 2115 | Even this may only true if the condition predicate is true. The |
| 2116 | following use a condition predicate of ALWAYS so it is always TRUE. |
| 2117 | |
| 2118 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, |
| 2119 | and NetBSD all use a software interrupt rather than an undefined |
| 2120 | instruction to force a trap. This can be handled by by the |
| 2121 | abi-specific code during establishment of the gdbarch vector. */ |
| 2122 | |
| 2123 | |
| 2124 | /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to |
| 2125 | override these definitions. */ |
| 2126 | #ifndef ARM_LE_BREAKPOINT |
| 2127 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} |
| 2128 | #endif |
| 2129 | #ifndef ARM_BE_BREAKPOINT |
| 2130 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} |
| 2131 | #endif |
| 2132 | #ifndef THUMB_LE_BREAKPOINT |
| 2133 | #define THUMB_LE_BREAKPOINT {0xfe,0xdf} |
| 2134 | #endif |
| 2135 | #ifndef THUMB_BE_BREAKPOINT |
| 2136 | #define THUMB_BE_BREAKPOINT {0xdf,0xfe} |
| 2137 | #endif |
| 2138 | |
| 2139 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; |
| 2140 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; |
| 2141 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; |
| 2142 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; |
| 2143 | |
| 2144 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
| 2145 | the program counter value to determine whether a 16-bit or 32-bit |
| 2146 | breakpoint should be used. It returns a pointer to a string of |
| 2147 | bytes that encode a breakpoint instruction, stores the length of |
| 2148 | the string to *lenptr, and adjusts the program counter (if |
| 2149 | necessary) to point to the actual memory location where the |
| 2150 | breakpoint should be inserted. */ |
| 2151 | |
| 2152 | /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting |
| 2153 | breakpoints and storing their handles instread of what was in |
| 2154 | memory. It is nice that this is the same size as a handle - |
| 2155 | otherwise remote-rdp will have to change. */ |
| 2156 | |
| 2157 | static const unsigned char * |
| 2158 | arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
| 2159 | { |
| 2160 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 2161 | |
| 2162 | if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr)) |
| 2163 | { |
| 2164 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
| 2165 | *lenptr = tdep->thumb_breakpoint_size; |
| 2166 | return tdep->thumb_breakpoint; |
| 2167 | } |
| 2168 | else |
| 2169 | { |
| 2170 | *lenptr = tdep->arm_breakpoint_size; |
| 2171 | return tdep->arm_breakpoint; |
| 2172 | } |
| 2173 | } |
| 2174 | |
| 2175 | /* Extract from an array REGBUF containing the (raw) register state a |
| 2176 | function return value of type TYPE, and copy that, in virtual |
| 2177 | format, into VALBUF. */ |
| 2178 | |
| 2179 | static void |
| 2180 | arm_extract_return_value (struct type *type, |
| 2181 | struct regcache *regs, |
| 2182 | void *dst) |
| 2183 | { |
| 2184 | bfd_byte *valbuf = dst; |
| 2185 | |
| 2186 | if (TYPE_CODE_FLT == TYPE_CODE (type)) |
| 2187 | { |
| 2188 | switch (arm_get_fp_model (current_gdbarch)) |
| 2189 | { |
| 2190 | case ARM_FLOAT_FPA: |
| 2191 | { |
| 2192 | /* The value is in register F0 in internal format. We need to |
| 2193 | extract the raw value and then convert it to the desired |
| 2194 | internal type. */ |
| 2195 | bfd_byte tmpbuf[FP_REGISTER_RAW_SIZE]; |
| 2196 | |
| 2197 | regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); |
| 2198 | convert_from_extended (floatformat_from_type (type), tmpbuf, |
| 2199 | valbuf); |
| 2200 | } |
| 2201 | break; |
| 2202 | |
| 2203 | case ARM_FLOAT_SOFT_FPA: |
| 2204 | case ARM_FLOAT_SOFT_VFP: |
| 2205 | regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); |
| 2206 | if (TYPE_LENGTH (type) > 4) |
| 2207 | regcache_cooked_read (regs, ARM_A1_REGNUM + 1, |
| 2208 | valbuf + INT_REGISTER_RAW_SIZE); |
| 2209 | break; |
| 2210 | |
| 2211 | default: |
| 2212 | internal_error |
| 2213 | (__FILE__, __LINE__, |
| 2214 | "arm_extract_return_value: Floating point model not supported"); |
| 2215 | break; |
| 2216 | } |
| 2217 | } |
| 2218 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
| 2219 | || TYPE_CODE (type) == TYPE_CODE_CHAR |
| 2220 | || TYPE_CODE (type) == TYPE_CODE_BOOL |
| 2221 | || TYPE_CODE (type) == TYPE_CODE_PTR |
| 2222 | || TYPE_CODE (type) == TYPE_CODE_REF |
| 2223 | || TYPE_CODE (type) == TYPE_CODE_ENUM) |
| 2224 | { |
| 2225 | /* If the the type is a plain integer, then the access is |
| 2226 | straight-forward. Otherwise we have to play around a bit more. */ |
| 2227 | int len = TYPE_LENGTH (type); |
| 2228 | int regno = ARM_A1_REGNUM; |
| 2229 | ULONGEST tmp; |
| 2230 | |
| 2231 | while (len > 0) |
| 2232 | { |
| 2233 | /* By using store_unsigned_integer we avoid having to do |
| 2234 | anything special for small big-endian values. */ |
| 2235 | regcache_cooked_read_unsigned (regs, regno++, &tmp); |
| 2236 | store_unsigned_integer (valbuf, |
| 2237 | (len > INT_REGISTER_RAW_SIZE |
| 2238 | ? INT_REGISTER_RAW_SIZE : len), |
| 2239 | tmp); |
| 2240 | len -= INT_REGISTER_RAW_SIZE; |
| 2241 | valbuf += INT_REGISTER_RAW_SIZE; |
| 2242 | } |
| 2243 | } |
| 2244 | else |
| 2245 | { |
| 2246 | /* For a structure or union the behaviour is as if the value had |
| 2247 | been stored to word-aligned memory and then loaded into |
| 2248 | registers with 32-bit load instruction(s). */ |
| 2249 | int len = TYPE_LENGTH (type); |
| 2250 | int regno = ARM_A1_REGNUM; |
| 2251 | bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE]; |
| 2252 | |
| 2253 | while (len > 0) |
| 2254 | { |
| 2255 | regcache_cooked_read (regs, regno++, tmpbuf); |
| 2256 | memcpy (valbuf, tmpbuf, |
| 2257 | len > INT_REGISTER_RAW_SIZE ? INT_REGISTER_RAW_SIZE : len); |
| 2258 | len -= INT_REGISTER_RAW_SIZE; |
| 2259 | valbuf += INT_REGISTER_RAW_SIZE; |
| 2260 | } |
| 2261 | } |
| 2262 | } |
| 2263 | |
| 2264 | /* Extract from an array REGBUF containing the (raw) register state |
| 2265 | the address in which a function should return its structure value. */ |
| 2266 | |
| 2267 | static CORE_ADDR |
| 2268 | arm_extract_struct_value_address (struct regcache *regcache) |
| 2269 | { |
| 2270 | ULONGEST ret; |
| 2271 | |
| 2272 | regcache_cooked_read_unsigned (regcache, ARM_A1_REGNUM, &ret); |
| 2273 | return ret; |
| 2274 | } |
| 2275 | |
| 2276 | /* Will a function return an aggregate type in memory or in a |
| 2277 | register? Return 0 if an aggregate type can be returned in a |
| 2278 | register, 1 if it must be returned in memory. */ |
| 2279 | |
| 2280 | static int |
| 2281 | arm_use_struct_convention (int gcc_p, struct type *type) |
| 2282 | { |
| 2283 | int nRc; |
| 2284 | register enum type_code code; |
| 2285 | |
| 2286 | /* In the ARM ABI, "integer" like aggregate types are returned in |
| 2287 | registers. For an aggregate type to be integer like, its size |
| 2288 | must be less than or equal to REGISTER_SIZE and the offset of |
| 2289 | each addressable subfield must be zero. Note that bit fields are |
| 2290 | not addressable, and all addressable subfields of unions always |
| 2291 | start at offset zero. |
| 2292 | |
| 2293 | This function is based on the behaviour of GCC 2.95.1. |
| 2294 | See: gcc/arm.c: arm_return_in_memory() for details. |
| 2295 | |
| 2296 | Note: All versions of GCC before GCC 2.95.2 do not set up the |
| 2297 | parameters correctly for a function returning the following |
| 2298 | structure: struct { float f;}; This should be returned in memory, |
| 2299 | not a register. Richard Earnshaw sent me a patch, but I do not |
| 2300 | know of any way to detect if a function like the above has been |
| 2301 | compiled with the correct calling convention. */ |
| 2302 | |
| 2303 | /* All aggregate types that won't fit in a register must be returned |
| 2304 | in memory. */ |
| 2305 | if (TYPE_LENGTH (type) > REGISTER_SIZE) |
| 2306 | { |
| 2307 | return 1; |
| 2308 | } |
| 2309 | |
| 2310 | /* The only aggregate types that can be returned in a register are |
| 2311 | structs and unions. Arrays must be returned in memory. */ |
| 2312 | code = TYPE_CODE (type); |
| 2313 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) |
| 2314 | { |
| 2315 | return 1; |
| 2316 | } |
| 2317 | |
| 2318 | /* Assume all other aggregate types can be returned in a register. |
| 2319 | Run a check for structures, unions and arrays. */ |
| 2320 | nRc = 0; |
| 2321 | |
| 2322 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) |
| 2323 | { |
| 2324 | int i; |
| 2325 | /* Need to check if this struct/union is "integer" like. For |
| 2326 | this to be true, its size must be less than or equal to |
| 2327 | REGISTER_SIZE and the offset of each addressable subfield |
| 2328 | must be zero. Note that bit fields are not addressable, and |
| 2329 | unions always start at offset zero. If any of the subfields |
| 2330 | is a floating point type, the struct/union cannot be an |
| 2331 | integer type. */ |
| 2332 | |
| 2333 | /* For each field in the object, check: |
| 2334 | 1) Is it FP? --> yes, nRc = 1; |
| 2335 | 2) Is it addressable (bitpos != 0) and |
| 2336 | not packed (bitsize == 0)? |
| 2337 | --> yes, nRc = 1 |
| 2338 | */ |
| 2339 | |
| 2340 | for (i = 0; i < TYPE_NFIELDS (type); i++) |
| 2341 | { |
| 2342 | enum type_code field_type_code; |
| 2343 | field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i)); |
| 2344 | |
| 2345 | /* Is it a floating point type field? */ |
| 2346 | if (field_type_code == TYPE_CODE_FLT) |
| 2347 | { |
| 2348 | nRc = 1; |
| 2349 | break; |
| 2350 | } |
| 2351 | |
| 2352 | /* If bitpos != 0, then we have to care about it. */ |
| 2353 | if (TYPE_FIELD_BITPOS (type, i) != 0) |
| 2354 | { |
| 2355 | /* Bitfields are not addressable. If the field bitsize is |
| 2356 | zero, then the field is not packed. Hence it cannot be |
| 2357 | a bitfield or any other packed type. */ |
| 2358 | if (TYPE_FIELD_BITSIZE (type, i) == 0) |
| 2359 | { |
| 2360 | nRc = 1; |
| 2361 | break; |
| 2362 | } |
| 2363 | } |
| 2364 | } |
| 2365 | } |
| 2366 | |
| 2367 | return nRc; |
| 2368 | } |
| 2369 | |
| 2370 | /* Write into appropriate registers a function return value of type |
| 2371 | TYPE, given in virtual format. */ |
| 2372 | |
| 2373 | static void |
| 2374 | arm_store_return_value (struct type *type, struct regcache *regs, |
| 2375 | const void *src) |
| 2376 | { |
| 2377 | const bfd_byte *valbuf = src; |
| 2378 | |
| 2379 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
| 2380 | { |
| 2381 | char buf[ARM_MAX_REGISTER_RAW_SIZE]; |
| 2382 | |
| 2383 | switch (arm_get_fp_model (current_gdbarch)) |
| 2384 | { |
| 2385 | case ARM_FLOAT_FPA: |
| 2386 | |
| 2387 | convert_to_extended (floatformat_from_type (type), buf, valbuf); |
| 2388 | regcache_cooked_write (regs, ARM_F0_REGNUM, buf); |
| 2389 | break; |
| 2390 | |
| 2391 | case ARM_FLOAT_SOFT_FPA: |
| 2392 | case ARM_FLOAT_SOFT_VFP: |
| 2393 | regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); |
| 2394 | if (TYPE_LENGTH (type) > 4) |
| 2395 | regcache_cooked_write (regs, ARM_A1_REGNUM + 1, |
| 2396 | valbuf + INT_REGISTER_RAW_SIZE); |
| 2397 | break; |
| 2398 | |
| 2399 | default: |
| 2400 | internal_error |
| 2401 | (__FILE__, __LINE__, |
| 2402 | "arm_store_return_value: Floating point model not supported"); |
| 2403 | break; |
| 2404 | } |
| 2405 | } |
| 2406 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
| 2407 | || TYPE_CODE (type) == TYPE_CODE_CHAR |
| 2408 | || TYPE_CODE (type) == TYPE_CODE_BOOL |
| 2409 | || TYPE_CODE (type) == TYPE_CODE_PTR |
| 2410 | || TYPE_CODE (type) == TYPE_CODE_REF |
| 2411 | || TYPE_CODE (type) == TYPE_CODE_ENUM) |
| 2412 | { |
| 2413 | if (TYPE_LENGTH (type) <= 4) |
| 2414 | { |
| 2415 | /* Values of one word or less are zero/sign-extended and |
| 2416 | returned in r0. */ |
| 2417 | bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE]; |
| 2418 | LONGEST val = unpack_long (type, valbuf); |
| 2419 | |
| 2420 | store_signed_integer (tmpbuf, INT_REGISTER_RAW_SIZE, val); |
| 2421 | regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); |
| 2422 | } |
| 2423 | else |
| 2424 | { |
| 2425 | /* Integral values greater than one word are stored in consecutive |
| 2426 | registers starting with r0. This will always be a multiple of |
| 2427 | the regiser size. */ |
| 2428 | int len = TYPE_LENGTH (type); |
| 2429 | int regno = ARM_A1_REGNUM; |
| 2430 | |
| 2431 | while (len > 0) |
| 2432 | { |
| 2433 | regcache_cooked_write (regs, regno++, valbuf); |
| 2434 | len -= INT_REGISTER_RAW_SIZE; |
| 2435 | valbuf += INT_REGISTER_RAW_SIZE; |
| 2436 | } |
| 2437 | } |
| 2438 | } |
| 2439 | else |
| 2440 | { |
| 2441 | /* For a structure or union the behaviour is as if the value had |
| 2442 | been stored to word-aligned memory and then loaded into |
| 2443 | registers with 32-bit load instruction(s). */ |
| 2444 | int len = TYPE_LENGTH (type); |
| 2445 | int regno = ARM_A1_REGNUM; |
| 2446 | bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE]; |
| 2447 | |
| 2448 | while (len > 0) |
| 2449 | { |
| 2450 | memcpy (tmpbuf, valbuf, |
| 2451 | len > INT_REGISTER_RAW_SIZE ? INT_REGISTER_RAW_SIZE : len); |
| 2452 | regcache_cooked_write (regs, regno++, tmpbuf); |
| 2453 | len -= INT_REGISTER_RAW_SIZE; |
| 2454 | valbuf += INT_REGISTER_RAW_SIZE; |
| 2455 | } |
| 2456 | } |
| 2457 | } |
| 2458 | |
| 2459 | /* Store the address of the place in which to copy the structure the |
| 2460 | subroutine will return. This is called from call_function. */ |
| 2461 | |
| 2462 | static void |
| 2463 | arm_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) |
| 2464 | { |
| 2465 | write_register (ARM_A1_REGNUM, addr); |
| 2466 | } |
| 2467 | |
| 2468 | static int |
| 2469 | arm_get_longjmp_target (CORE_ADDR *pc) |
| 2470 | { |
| 2471 | CORE_ADDR jb_addr; |
| 2472 | char buf[INT_REGISTER_RAW_SIZE]; |
| 2473 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 2474 | |
| 2475 | jb_addr = read_register (ARM_A1_REGNUM); |
| 2476 | |
| 2477 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, |
| 2478 | INT_REGISTER_RAW_SIZE)) |
| 2479 | return 0; |
| 2480 | |
| 2481 | *pc = extract_address (buf, INT_REGISTER_RAW_SIZE); |
| 2482 | return 1; |
| 2483 | } |
| 2484 | |
| 2485 | /* Return non-zero if the PC is inside a thumb call thunk. */ |
| 2486 | |
| 2487 | int |
| 2488 | arm_in_call_stub (CORE_ADDR pc, char *name) |
| 2489 | { |
| 2490 | CORE_ADDR start_addr; |
| 2491 | |
| 2492 | /* Find the starting address of the function containing the PC. If |
| 2493 | the caller didn't give us a name, look it up at the same time. */ |
| 2494 | if (0 == find_pc_partial_function (pc, name ? NULL : &name, |
| 2495 | &start_addr, NULL)) |
| 2496 | return 0; |
| 2497 | |
| 2498 | return strncmp (name, "_call_via_r", 11) == 0; |
| 2499 | } |
| 2500 | |
| 2501 | /* If PC is in a Thumb call or return stub, return the address of the |
| 2502 | target PC, which is in a register. The thunk functions are called |
| 2503 | _called_via_xx, where x is the register name. The possible names |
| 2504 | are r0-r9, sl, fp, ip, sp, and lr. */ |
| 2505 | |
| 2506 | CORE_ADDR |
| 2507 | arm_skip_stub (CORE_ADDR pc) |
| 2508 | { |
| 2509 | char *name; |
| 2510 | CORE_ADDR start_addr; |
| 2511 | |
| 2512 | /* Find the starting address and name of the function containing the PC. */ |
| 2513 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) |
| 2514 | return 0; |
| 2515 | |
| 2516 | /* Call thunks always start with "_call_via_". */ |
| 2517 | if (strncmp (name, "_call_via_", 10) == 0) |
| 2518 | { |
| 2519 | /* Use the name suffix to determine which register contains the |
| 2520 | target PC. */ |
| 2521 | static char *table[15] = |
| 2522 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
| 2523 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" |
| 2524 | }; |
| 2525 | int regno; |
| 2526 | |
| 2527 | for (regno = 0; regno <= 14; regno++) |
| 2528 | if (strcmp (&name[10], table[regno]) == 0) |
| 2529 | return read_register (regno); |
| 2530 | } |
| 2531 | |
| 2532 | return 0; /* not a stub */ |
| 2533 | } |
| 2534 | |
| 2535 | static void |
| 2536 | set_arm_command (char *args, int from_tty) |
| 2537 | { |
| 2538 | printf_unfiltered ("\"set arm\" must be followed by an apporpriate subcommand.\n"); |
| 2539 | help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout); |
| 2540 | } |
| 2541 | |
| 2542 | static void |
| 2543 | show_arm_command (char *args, int from_tty) |
| 2544 | { |
| 2545 | cmd_show_list (showarmcmdlist, from_tty, ""); |
| 2546 | } |
| 2547 | |
| 2548 | enum arm_float_model |
| 2549 | arm_get_fp_model (struct gdbarch *gdbarch) |
| 2550 | { |
| 2551 | if (arm_fp_model == ARM_FLOAT_AUTO) |
| 2552 | return gdbarch_tdep (gdbarch)->fp_model; |
| 2553 | |
| 2554 | return arm_fp_model; |
| 2555 | } |
| 2556 | |
| 2557 | static void |
| 2558 | arm_set_fp (struct gdbarch *gdbarch) |
| 2559 | { |
| 2560 | enum arm_float_model fp_model = arm_get_fp_model (gdbarch); |
| 2561 | |
| 2562 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE |
| 2563 | && (fp_model == ARM_FLOAT_SOFT_FPA || fp_model == ARM_FLOAT_FPA)) |
| 2564 | { |
| 2565 | set_gdbarch_double_format (gdbarch, |
| 2566 | &floatformat_ieee_double_littlebyte_bigword); |
| 2567 | set_gdbarch_long_double_format |
| 2568 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); |
| 2569 | } |
| 2570 | else |
| 2571 | { |
| 2572 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little); |
| 2573 | set_gdbarch_long_double_format (gdbarch, |
| 2574 | &floatformat_ieee_double_little); |
| 2575 | } |
| 2576 | } |
| 2577 | |
| 2578 | static void |
| 2579 | set_fp_model_sfunc (char *args, int from_tty, |
| 2580 | struct cmd_list_element *c) |
| 2581 | { |
| 2582 | enum arm_float_model fp_model; |
| 2583 | |
| 2584 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) |
| 2585 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) |
| 2586 | { |
| 2587 | arm_fp_model = fp_model; |
| 2588 | break; |
| 2589 | } |
| 2590 | |
| 2591 | if (fp_model == ARM_FLOAT_LAST) |
| 2592 | internal_error (__FILE__, __LINE__, "Invalid fp model accepted: %s.", |
| 2593 | current_fp_model); |
| 2594 | |
| 2595 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) |
| 2596 | arm_set_fp (current_gdbarch); |
| 2597 | } |
| 2598 | |
| 2599 | static void |
| 2600 | show_fp_model (char *args, int from_tty, |
| 2601 | struct cmd_list_element *c) |
| 2602 | { |
| 2603 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 2604 | |
| 2605 | if (arm_fp_model == ARM_FLOAT_AUTO |
| 2606 | && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) |
| 2607 | printf_filtered (" - the default for the current ABI is \"%s\".\n", |
| 2608 | fp_model_strings[tdep->fp_model]); |
| 2609 | } |
| 2610 | |
| 2611 | /* If the user changes the register disassembly style used for info |
| 2612 | register and other commands, we have to also switch the style used |
| 2613 | in opcodes for disassembly output. This function is run in the "set |
| 2614 | arm disassembly" command, and does that. */ |
| 2615 | |
| 2616 | static void |
| 2617 | set_disassembly_style_sfunc (char *args, int from_tty, |
| 2618 | struct cmd_list_element *c) |
| 2619 | { |
| 2620 | set_disassembly_style (); |
| 2621 | } |
| 2622 | \f |
| 2623 | /* Return the ARM register name corresponding to register I. */ |
| 2624 | static const char * |
| 2625 | arm_register_name (int i) |
| 2626 | { |
| 2627 | return arm_register_names[i]; |
| 2628 | } |
| 2629 | |
| 2630 | static void |
| 2631 | set_disassembly_style (void) |
| 2632 | { |
| 2633 | const char *setname, *setdesc, **regnames; |
| 2634 | int numregs, j; |
| 2635 | |
| 2636 | /* Find the style that the user wants in the opcodes table. */ |
| 2637 | int current = 0; |
| 2638 | numregs = get_arm_regnames (current, &setname, &setdesc, ®names); |
| 2639 | while ((disassembly_style != setname) |
| 2640 | && (current < num_disassembly_options)) |
| 2641 | get_arm_regnames (++current, &setname, &setdesc, ®names); |
| 2642 | current_option = current; |
| 2643 | |
| 2644 | /* Fill our copy. */ |
| 2645 | for (j = 0; j < numregs; j++) |
| 2646 | arm_register_names[j] = (char *) regnames[j]; |
| 2647 | |
| 2648 | /* Adjust case. */ |
| 2649 | if (isupper (*regnames[ARM_PC_REGNUM])) |
| 2650 | { |
| 2651 | arm_register_names[ARM_FPS_REGNUM] = "FPS"; |
| 2652 | arm_register_names[ARM_PS_REGNUM] = "CPSR"; |
| 2653 | } |
| 2654 | else |
| 2655 | { |
| 2656 | arm_register_names[ARM_FPS_REGNUM] = "fps"; |
| 2657 | arm_register_names[ARM_PS_REGNUM] = "cpsr"; |
| 2658 | } |
| 2659 | |
| 2660 | /* Synchronize the disassembler. */ |
| 2661 | set_arm_regname_option (current); |
| 2662 | } |
| 2663 | |
| 2664 | /* arm_othernames implements the "othernames" command. This is deprecated |
| 2665 | by the "set arm disassembly" command. */ |
| 2666 | |
| 2667 | static void |
| 2668 | arm_othernames (char *names, int n) |
| 2669 | { |
| 2670 | /* Circle through the various flavors. */ |
| 2671 | current_option = (current_option + 1) % num_disassembly_options; |
| 2672 | |
| 2673 | disassembly_style = valid_disassembly_styles[current_option]; |
| 2674 | set_disassembly_style (); |
| 2675 | } |
| 2676 | |
| 2677 | /* Fetch, and possibly build, an appropriate link_map_offsets structure |
| 2678 | for ARM linux targets using the struct offsets defined in <link.h>. |
| 2679 | Note, however, that link.h is not actually referred to in this file. |
| 2680 | Instead, the relevant structs offsets were obtained from examining |
| 2681 | link.h. (We can't refer to link.h from this file because the host |
| 2682 | system won't necessarily have it, or if it does, the structs which |
| 2683 | it defines will refer to the host system, not the target). */ |
| 2684 | |
| 2685 | struct link_map_offsets * |
| 2686 | arm_linux_svr4_fetch_link_map_offsets (void) |
| 2687 | { |
| 2688 | static struct link_map_offsets lmo; |
| 2689 | static struct link_map_offsets *lmp = 0; |
| 2690 | |
| 2691 | if (lmp == 0) |
| 2692 | { |
| 2693 | lmp = &lmo; |
| 2694 | |
| 2695 | lmo.r_debug_size = 8; /* Actual size is 20, but this is all we |
| 2696 | need. */ |
| 2697 | |
| 2698 | lmo.r_map_offset = 4; |
| 2699 | lmo.r_map_size = 4; |
| 2700 | |
| 2701 | lmo.link_map_size = 20; /* Actual size is 552, but this is all we |
| 2702 | need. */ |
| 2703 | |
| 2704 | lmo.l_addr_offset = 0; |
| 2705 | lmo.l_addr_size = 4; |
| 2706 | |
| 2707 | lmo.l_name_offset = 4; |
| 2708 | lmo.l_name_size = 4; |
| 2709 | |
| 2710 | lmo.l_next_offset = 12; |
| 2711 | lmo.l_next_size = 4; |
| 2712 | |
| 2713 | lmo.l_prev_offset = 16; |
| 2714 | lmo.l_prev_size = 4; |
| 2715 | } |
| 2716 | |
| 2717 | return lmp; |
| 2718 | } |
| 2719 | |
| 2720 | /* Test whether the coff symbol specific value corresponds to a Thumb |
| 2721 | function. */ |
| 2722 | |
| 2723 | static int |
| 2724 | coff_sym_is_thumb (int val) |
| 2725 | { |
| 2726 | return (val == C_THUMBEXT || |
| 2727 | val == C_THUMBSTAT || |
| 2728 | val == C_THUMBEXTFUNC || |
| 2729 | val == C_THUMBSTATFUNC || |
| 2730 | val == C_THUMBLABEL); |
| 2731 | } |
| 2732 | |
| 2733 | /* arm_coff_make_msymbol_special() |
| 2734 | arm_elf_make_msymbol_special() |
| 2735 | |
| 2736 | These functions test whether the COFF or ELF symbol corresponds to |
| 2737 | an address in thumb code, and set a "special" bit in a minimal |
| 2738 | symbol to indicate that it does. */ |
| 2739 | |
| 2740 | static void |
| 2741 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
| 2742 | { |
| 2743 | /* Thumb symbols are of type STT_LOPROC, (synonymous with |
| 2744 | STT_ARM_TFUNC). */ |
| 2745 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) |
| 2746 | == STT_LOPROC) |
| 2747 | MSYMBOL_SET_SPECIAL (msym); |
| 2748 | } |
| 2749 | |
| 2750 | static void |
| 2751 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
| 2752 | { |
| 2753 | if (coff_sym_is_thumb (val)) |
| 2754 | MSYMBOL_SET_SPECIAL (msym); |
| 2755 | } |
| 2756 | |
| 2757 | \f |
| 2758 | static enum gdb_osabi |
| 2759 | arm_elf_osabi_sniffer (bfd *abfd) |
| 2760 | { |
| 2761 | unsigned int elfosabi, eflags; |
| 2762 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
| 2763 | |
| 2764 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
| 2765 | |
| 2766 | switch (elfosabi) |
| 2767 | { |
| 2768 | case ELFOSABI_NONE: |
| 2769 | /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the |
| 2770 | file are conforming to the base specification for that machine |
| 2771 | (there are no OS-specific extensions). In order to determine the |
| 2772 | real OS in use we must look for OS notes that have been added. */ |
| 2773 | bfd_map_over_sections (abfd, |
| 2774 | generic_elf_osabi_sniff_abi_tag_sections, |
| 2775 | &osabi); |
| 2776 | if (osabi == GDB_OSABI_UNKNOWN) |
| 2777 | { |
| 2778 | /* Existing ARM tools don't set this field, so look at the EI_FLAGS |
| 2779 | field for more information. */ |
| 2780 | eflags = EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags); |
| 2781 | switch (eflags) |
| 2782 | { |
| 2783 | case EF_ARM_EABI_VER1: |
| 2784 | osabi = GDB_OSABI_ARM_EABI_V1; |
| 2785 | break; |
| 2786 | |
| 2787 | case EF_ARM_EABI_VER2: |
| 2788 | osabi = GDB_OSABI_ARM_EABI_V2; |
| 2789 | break; |
| 2790 | |
| 2791 | case EF_ARM_EABI_UNKNOWN: |
| 2792 | /* Assume GNU tools. */ |
| 2793 | osabi = GDB_OSABI_ARM_APCS; |
| 2794 | break; |
| 2795 | |
| 2796 | default: |
| 2797 | internal_error (__FILE__, __LINE__, |
| 2798 | "arm_elf_osabi_sniffer: Unknown ARM EABI " |
| 2799 | "version 0x%x", eflags); |
| 2800 | } |
| 2801 | } |
| 2802 | break; |
| 2803 | |
| 2804 | case ELFOSABI_ARM: |
| 2805 | /* GNU tools use this value. Check note sections in this case, |
| 2806 | as well. */ |
| 2807 | bfd_map_over_sections (abfd, |
| 2808 | generic_elf_osabi_sniff_abi_tag_sections, |
| 2809 | &osabi); |
| 2810 | if (osabi == GDB_OSABI_UNKNOWN) |
| 2811 | { |
| 2812 | /* Assume APCS ABI. */ |
| 2813 | osabi = GDB_OSABI_ARM_APCS; |
| 2814 | } |
| 2815 | break; |
| 2816 | |
| 2817 | case ELFOSABI_FREEBSD: |
| 2818 | osabi = GDB_OSABI_FREEBSD_ELF; |
| 2819 | break; |
| 2820 | |
| 2821 | case ELFOSABI_NETBSD: |
| 2822 | osabi = GDB_OSABI_NETBSD_ELF; |
| 2823 | break; |
| 2824 | |
| 2825 | case ELFOSABI_LINUX: |
| 2826 | osabi = GDB_OSABI_LINUX; |
| 2827 | break; |
| 2828 | } |
| 2829 | |
| 2830 | return osabi; |
| 2831 | } |
| 2832 | |
| 2833 | \f |
| 2834 | /* Initialize the current architecture based on INFO. If possible, |
| 2835 | re-use an architecture from ARCHES, which is a list of |
| 2836 | architectures already created during this debugging session. |
| 2837 | |
| 2838 | Called e.g. at program startup, when reading a core file, and when |
| 2839 | reading a binary file. */ |
| 2840 | |
| 2841 | static struct gdbarch * |
| 2842 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 2843 | { |
| 2844 | struct gdbarch_tdep *tdep; |
| 2845 | struct gdbarch *gdbarch; |
| 2846 | |
| 2847 | /* Try to deterimine the ABI of the object we are loading. */ |
| 2848 | |
| 2849 | if (info.abfd != NULL && info.osabi == GDB_OSABI_UNKNOWN) |
| 2850 | { |
| 2851 | switch (bfd_get_flavour (info.abfd)) |
| 2852 | { |
| 2853 | case bfd_target_aout_flavour: |
| 2854 | /* Assume it's an old APCS-style ABI. */ |
| 2855 | info.osabi = GDB_OSABI_ARM_APCS; |
| 2856 | break; |
| 2857 | |
| 2858 | case bfd_target_coff_flavour: |
| 2859 | /* Assume it's an old APCS-style ABI. */ |
| 2860 | /* XXX WinCE? */ |
| 2861 | info.osabi = GDB_OSABI_ARM_APCS; |
| 2862 | break; |
| 2863 | |
| 2864 | default: |
| 2865 | /* Leave it as "unknown". */ |
| 2866 | break; |
| 2867 | } |
| 2868 | } |
| 2869 | |
| 2870 | /* If there is already a candidate, use it. */ |
| 2871 | arches = gdbarch_list_lookup_by_info (arches, &info); |
| 2872 | if (arches != NULL) |
| 2873 | return arches->gdbarch; |
| 2874 | |
| 2875 | tdep = xmalloc (sizeof (struct gdbarch_tdep)); |
| 2876 | gdbarch = gdbarch_alloc (&info, tdep); |
| 2877 | |
| 2878 | /* NOTE: cagney/2002-12-06: This can be deleted when this arch is |
| 2879 | ready to unwind the PC first (see frame.c:get_prev_frame()). */ |
| 2880 | set_gdbarch_deprecated_init_frame_pc (gdbarch, init_frame_pc_default); |
| 2881 | |
| 2882 | /* We used to default to FPA for generic ARM, but almost nobody uses that |
| 2883 | now, and we now provide a way for the user to force the model. So |
| 2884 | default to the most useful variant. */ |
| 2885 | tdep->fp_model = ARM_FLOAT_SOFT_FPA; |
| 2886 | |
| 2887 | /* Breakpoints. */ |
| 2888 | switch (info.byte_order) |
| 2889 | { |
| 2890 | case BFD_ENDIAN_BIG: |
| 2891 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
| 2892 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); |
| 2893 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; |
| 2894 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); |
| 2895 | |
| 2896 | break; |
| 2897 | |
| 2898 | case BFD_ENDIAN_LITTLE: |
| 2899 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
| 2900 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); |
| 2901 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; |
| 2902 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); |
| 2903 | |
| 2904 | break; |
| 2905 | |
| 2906 | default: |
| 2907 | internal_error (__FILE__, __LINE__, |
| 2908 | "arm_gdbarch_init: bad byte order for float format"); |
| 2909 | } |
| 2910 | |
| 2911 | /* On ARM targets char defaults to unsigned. */ |
| 2912 | set_gdbarch_char_signed (gdbarch, 0); |
| 2913 | |
| 2914 | /* This should be low enough for everything. */ |
| 2915 | tdep->lowest_pc = 0x20; |
| 2916 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
| 2917 | |
| 2918 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); |
| 2919 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); |
| 2920 | |
| 2921 | set_gdbarch_call_dummy_p (gdbarch, 1); |
| 2922 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); |
| 2923 | |
| 2924 | set_gdbarch_call_dummy_words (gdbarch, arm_call_dummy_words); |
| 2925 | set_gdbarch_sizeof_call_dummy_words (gdbarch, 0); |
| 2926 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); |
| 2927 | set_gdbarch_call_dummy_length (gdbarch, 0); |
| 2928 | |
| 2929 | set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy); |
| 2930 | |
| 2931 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); |
| 2932 | set_gdbarch_push_return_address (gdbarch, arm_push_return_address); |
| 2933 | |
| 2934 | set_gdbarch_push_arguments (gdbarch, arm_push_arguments); |
| 2935 | |
| 2936 | /* Frame handling. */ |
| 2937 | set_gdbarch_frame_chain_valid (gdbarch, arm_frame_chain_valid); |
| 2938 | set_gdbarch_deprecated_init_extra_frame_info (gdbarch, arm_init_extra_frame_info); |
| 2939 | set_gdbarch_read_fp (gdbarch, arm_read_fp); |
| 2940 | set_gdbarch_frame_chain (gdbarch, arm_frame_chain); |
| 2941 | set_gdbarch_frameless_function_invocation |
| 2942 | (gdbarch, arm_frameless_function_invocation); |
| 2943 | set_gdbarch_deprecated_frame_saved_pc (gdbarch, arm_frame_saved_pc); |
| 2944 | set_gdbarch_frame_args_address (gdbarch, arm_frame_args_address); |
| 2945 | set_gdbarch_frame_locals_address (gdbarch, arm_frame_locals_address); |
| 2946 | set_gdbarch_frame_num_args (gdbarch, arm_frame_num_args); |
| 2947 | set_gdbarch_frame_args_skip (gdbarch, 0); |
| 2948 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, arm_frame_init_saved_regs); |
| 2949 | set_gdbarch_deprecated_pop_frame (gdbarch, arm_pop_frame); |
| 2950 | |
| 2951 | /* Address manipulation. */ |
| 2952 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); |
| 2953 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); |
| 2954 | |
| 2955 | /* Offset from address of function to start of its code. */ |
| 2956 | set_gdbarch_function_start_offset (gdbarch, 0); |
| 2957 | |
| 2958 | /* Advance PC across function entry code. */ |
| 2959 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); |
| 2960 | |
| 2961 | /* Get the PC when a frame might not be available. */ |
| 2962 | set_gdbarch_saved_pc_after_call (gdbarch, arm_saved_pc_after_call); |
| 2963 | |
| 2964 | /* The stack grows downward. */ |
| 2965 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 2966 | |
| 2967 | /* Breakpoint manipulation. */ |
| 2968 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); |
| 2969 | set_gdbarch_decr_pc_after_break (gdbarch, 0); |
| 2970 | |
| 2971 | /* Information about registers, etc. */ |
| 2972 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); |
| 2973 | set_gdbarch_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
| 2974 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
| 2975 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); |
| 2976 | set_gdbarch_register_byte (gdbarch, arm_register_byte); |
| 2977 | set_gdbarch_register_bytes (gdbarch, |
| 2978 | (NUM_GREGS * INT_REGISTER_RAW_SIZE |
| 2979 | + NUM_FREGS * FP_REGISTER_RAW_SIZE |
| 2980 | + NUM_SREGS * STATUS_REGISTER_SIZE)); |
| 2981 | set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS); |
| 2982 | set_gdbarch_register_raw_size (gdbarch, arm_register_raw_size); |
| 2983 | set_gdbarch_register_virtual_size (gdbarch, arm_register_virtual_size); |
| 2984 | set_gdbarch_deprecated_max_register_raw_size (gdbarch, FP_REGISTER_RAW_SIZE); |
| 2985 | set_gdbarch_deprecated_max_register_virtual_size (gdbarch, FP_REGISTER_VIRTUAL_SIZE); |
| 2986 | set_gdbarch_register_virtual_type (gdbarch, arm_register_type); |
| 2987 | |
| 2988 | /* Internal <-> external register number maps. */ |
| 2989 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); |
| 2990 | |
| 2991 | /* Integer registers are 4 bytes. */ |
| 2992 | set_gdbarch_register_size (gdbarch, 4); |
| 2993 | set_gdbarch_register_name (gdbarch, arm_register_name); |
| 2994 | |
| 2995 | /* Returning results. */ |
| 2996 | set_gdbarch_extract_return_value (gdbarch, arm_extract_return_value); |
| 2997 | set_gdbarch_store_return_value (gdbarch, arm_store_return_value); |
| 2998 | set_gdbarch_store_struct_return (gdbarch, arm_store_struct_return); |
| 2999 | set_gdbarch_use_struct_convention (gdbarch, arm_use_struct_convention); |
| 3000 | set_gdbarch_extract_struct_value_address (gdbarch, |
| 3001 | arm_extract_struct_value_address); |
| 3002 | |
| 3003 | /* Single stepping. */ |
| 3004 | /* XXX For an RDI target we should ask the target if it can single-step. */ |
| 3005 | set_gdbarch_software_single_step (gdbarch, arm_software_single_step); |
| 3006 | |
| 3007 | /* Minsymbol frobbing. */ |
| 3008 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); |
| 3009 | set_gdbarch_coff_make_msymbol_special (gdbarch, |
| 3010 | arm_coff_make_msymbol_special); |
| 3011 | |
| 3012 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
| 3013 | gdbarch_init_osabi (info, gdbarch); |
| 3014 | |
| 3015 | /* Now we have tuned the configuration, set a few final things, |
| 3016 | based on what the OS ABI has told us. */ |
| 3017 | |
| 3018 | if (tdep->jb_pc >= 0) |
| 3019 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); |
| 3020 | |
| 3021 | /* Floating point sizes and format. */ |
| 3022 | switch (info.byte_order) |
| 3023 | { |
| 3024 | case BFD_ENDIAN_BIG: |
| 3025 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); |
| 3026 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big); |
| 3027 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); |
| 3028 | |
| 3029 | break; |
| 3030 | |
| 3031 | case BFD_ENDIAN_LITTLE: |
| 3032 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); |
| 3033 | arm_set_fp (gdbarch); |
| 3034 | break; |
| 3035 | |
| 3036 | default: |
| 3037 | internal_error (__FILE__, __LINE__, |
| 3038 | "arm_gdbarch_init: bad byte order for float format"); |
| 3039 | } |
| 3040 | |
| 3041 | return gdbarch; |
| 3042 | } |
| 3043 | |
| 3044 | static void |
| 3045 | arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) |
| 3046 | { |
| 3047 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 3048 | |
| 3049 | if (tdep == NULL) |
| 3050 | return; |
| 3051 | |
| 3052 | fprintf_unfiltered (file, "arm_dump_tdep: Lowest pc = 0x%lx", |
| 3053 | (unsigned long) tdep->lowest_pc); |
| 3054 | } |
| 3055 | |
| 3056 | static void |
| 3057 | arm_init_abi_eabi_v1 (struct gdbarch_info info, |
| 3058 | struct gdbarch *gdbarch) |
| 3059 | { |
| 3060 | /* Place-holder. */ |
| 3061 | } |
| 3062 | |
| 3063 | static void |
| 3064 | arm_init_abi_eabi_v2 (struct gdbarch_info info, |
| 3065 | struct gdbarch *gdbarch) |
| 3066 | { |
| 3067 | /* Place-holder. */ |
| 3068 | } |
| 3069 | |
| 3070 | static void |
| 3071 | arm_init_abi_apcs (struct gdbarch_info info, |
| 3072 | struct gdbarch *gdbarch) |
| 3073 | { |
| 3074 | /* Place-holder. */ |
| 3075 | } |
| 3076 | |
| 3077 | void |
| 3078 | _initialize_arm_tdep (void) |
| 3079 | { |
| 3080 | struct ui_file *stb; |
| 3081 | long length; |
| 3082 | struct cmd_list_element *new_set, *new_show; |
| 3083 | const char *setname; |
| 3084 | const char *setdesc; |
| 3085 | const char **regnames; |
| 3086 | int numregs, i, j; |
| 3087 | static char *helptext; |
| 3088 | |
| 3089 | if (GDB_MULTI_ARCH) |
| 3090 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
| 3091 | |
| 3092 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
| 3093 | gdbarch_register_osabi_sniffer (bfd_arch_arm, |
| 3094 | bfd_target_elf_flavour, |
| 3095 | arm_elf_osabi_sniffer); |
| 3096 | |
| 3097 | /* Register some ABI variants for embedded systems. */ |
| 3098 | gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V1, |
| 3099 | arm_init_abi_eabi_v1); |
| 3100 | gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V2, |
| 3101 | arm_init_abi_eabi_v2); |
| 3102 | gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_APCS, |
| 3103 | arm_init_abi_apcs); |
| 3104 | |
| 3105 | tm_print_insn = gdb_print_insn_arm; |
| 3106 | |
| 3107 | /* Get the number of possible sets of register names defined in opcodes. */ |
| 3108 | num_disassembly_options = get_arm_regname_num_options (); |
| 3109 | |
| 3110 | /* Add root prefix command for all "set arm"/"show arm" commands. */ |
| 3111 | add_prefix_cmd ("arm", no_class, set_arm_command, |
| 3112 | "Various ARM-specific commands.", |
| 3113 | &setarmcmdlist, "set arm ", 0, &setlist); |
| 3114 | |
| 3115 | add_prefix_cmd ("arm", no_class, show_arm_command, |
| 3116 | "Various ARM-specific commands.", |
| 3117 | &showarmcmdlist, "show arm ", 0, &showlist); |
| 3118 | |
| 3119 | /* Sync the opcode insn printer with our register viewer. */ |
| 3120 | parse_arm_disassembler_option ("reg-names-std"); |
| 3121 | |
| 3122 | /* Begin creating the help text. */ |
| 3123 | stb = mem_fileopen (); |
| 3124 | fprintf_unfiltered (stb, "Set the disassembly style.\n" |
| 3125 | "The valid values are:\n"); |
| 3126 | |
| 3127 | /* Initialize the array that will be passed to add_set_enum_cmd(). */ |
| 3128 | valid_disassembly_styles |
| 3129 | = xmalloc ((num_disassembly_options + 1) * sizeof (char *)); |
| 3130 | for (i = 0; i < num_disassembly_options; i++) |
| 3131 | { |
| 3132 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); |
| 3133 | valid_disassembly_styles[i] = setname; |
| 3134 | fprintf_unfiltered (stb, "%s - %s\n", setname, |
| 3135 | setdesc); |
| 3136 | /* Copy the default names (if found) and synchronize disassembler. */ |
| 3137 | if (!strcmp (setname, "std")) |
| 3138 | { |
| 3139 | disassembly_style = setname; |
| 3140 | current_option = i; |
| 3141 | for (j = 0; j < numregs; j++) |
| 3142 | arm_register_names[j] = (char *) regnames[j]; |
| 3143 | set_arm_regname_option (i); |
| 3144 | } |
| 3145 | } |
| 3146 | /* Mark the end of valid options. */ |
| 3147 | valid_disassembly_styles[num_disassembly_options] = NULL; |
| 3148 | |
| 3149 | /* Finish the creation of the help text. */ |
| 3150 | fprintf_unfiltered (stb, "The default is \"std\"."); |
| 3151 | helptext = ui_file_xstrdup (stb, &length); |
| 3152 | ui_file_delete (stb); |
| 3153 | |
| 3154 | /* Add the deprecated disassembly-flavor command. */ |
| 3155 | new_set = add_set_enum_cmd ("disassembly-flavor", no_class, |
| 3156 | valid_disassembly_styles, |
| 3157 | &disassembly_style, |
| 3158 | helptext, |
| 3159 | &setlist); |
| 3160 | set_cmd_sfunc (new_set, set_disassembly_style_sfunc); |
| 3161 | deprecate_cmd (new_set, "set arm disassembly"); |
| 3162 | deprecate_cmd (add_show_from_set (new_set, &showlist), |
| 3163 | "show arm disassembly"); |
| 3164 | |
| 3165 | /* And now add the new interface. */ |
| 3166 | new_set = add_set_enum_cmd ("disassembly", no_class, |
| 3167 | valid_disassembly_styles, &disassembly_style, |
| 3168 | helptext, &setarmcmdlist); |
| 3169 | |
| 3170 | set_cmd_sfunc (new_set, set_disassembly_style_sfunc); |
| 3171 | add_show_from_set (new_set, &showarmcmdlist); |
| 3172 | |
| 3173 | add_setshow_cmd_full ("apcs32", no_class, |
| 3174 | var_boolean, (char *) &arm_apcs_32, |
| 3175 | "Set usage of ARM 32-bit mode.", |
| 3176 | "Show usage of ARM 32-bit mode.", |
| 3177 | NULL, NULL, |
| 3178 | &setlist, &showlist, &new_set, &new_show); |
| 3179 | deprecate_cmd (new_set, "set arm apcs32"); |
| 3180 | deprecate_cmd (new_show, "show arm apcs32"); |
| 3181 | |
| 3182 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, |
| 3183 | "Set usage of ARM 32-bit mode. " |
| 3184 | "When off, a 26-bit PC will be used.", |
| 3185 | "Show usage of ARM 32-bit mode. " |
| 3186 | "When off, a 26-bit PC will be used.", |
| 3187 | NULL, NULL, |
| 3188 | &setarmcmdlist, &showarmcmdlist); |
| 3189 | |
| 3190 | /* Add a command to allow the user to force the FPU model. */ |
| 3191 | new_set = add_set_enum_cmd |
| 3192 | ("fpu", no_class, fp_model_strings, ¤t_fp_model, |
| 3193 | "Set the floating point type.\n" |
| 3194 | "auto - Determine the FP typefrom the OS-ABI.\n" |
| 3195 | "softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n" |
| 3196 | "fpa - FPA co-processor (GCC compiled).\n" |
| 3197 | "softvfp - Software FP with pure-endian doubles.\n" |
| 3198 | "vfp - VFP co-processor.", |
| 3199 | &setarmcmdlist); |
| 3200 | set_cmd_sfunc (new_set, set_fp_model_sfunc); |
| 3201 | set_cmd_sfunc (add_show_from_set (new_set, &showarmcmdlist), show_fp_model); |
| 3202 | |
| 3203 | /* Add the deprecated "othernames" command. */ |
| 3204 | deprecate_cmd (add_com ("othernames", class_obscure, arm_othernames, |
| 3205 | "Switch to the next set of register names."), |
| 3206 | "set arm disassembly"); |
| 3207 | |
| 3208 | /* Debugging flag. */ |
| 3209 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
| 3210 | "Set ARM debugging. " |
| 3211 | "When on, arm-specific debugging is enabled.", |
| 3212 | "Show ARM debugging. " |
| 3213 | "When on, arm-specific debugging is enabled.", |
| 3214 | NULL, NULL, |
| 3215 | &setdebuglist, &showdebuglist); |
| 3216 | } |