| 1 | /* Parameters for execution on an HP PA-RISC machine running OSF1, for GDB. |
| 2 | Contributed by the Center for Software Science at the |
| 3 | University of Utah (pa-gdb-bugs@cs.utah.edu). */ |
| 4 | |
| 5 | /* Define offsets to access CPROC stack when it does not have |
| 6 | * a kernel thread. |
| 7 | */ |
| 8 | #define MACHINE_CPROC_SP_OFFSET 20 |
| 9 | #define MACHINE_CPROC_PC_OFFSET 16 |
| 10 | #define MACHINE_CPROC_FP_OFFSET 12 |
| 11 | |
| 12 | /* |
| 13 | * Software defined PSW masks. |
| 14 | */ |
| 15 | #define PSW_SS 0x10000000 /* Kernel managed single step */ |
| 16 | |
| 17 | /* Thread flavors used in re-setting the T bit. |
| 18 | * @@ this is also bad for cross debugging. |
| 19 | */ |
| 20 | #define TRACE_FLAVOR HP800_THREAD_STATE |
| 21 | #define TRACE_FLAVOR_SIZE HP800_THREAD_STATE_COUNT |
| 22 | #define TRACE_SET(x,state) \ |
| 23 | ((struct hp800_thread_state *)state)->cr22 |= PSW_SS |
| 24 | #define TRACE_CLEAR(x,state) \ |
| 25 | ((((struct hp800_thread_state *)state)->cr22 &= ~PSW_SS), 1) |
| 26 | |
| 27 | /* For OSF1 (Should be close if not identical to BSD, but I haven't |
| 28 | tested it yet): |
| 29 | |
| 30 | The signal context structure pointer is always saved at the base |
| 31 | of the frame + 0x4. |
| 32 | |
| 33 | We get the PC & SP directly from the sigcontext structure itself. |
| 34 | For other registers we have to dive in a little deeper: |
| 35 | |
| 36 | The hardware save state pointer is at offset 0x10 within the |
| 37 | signal context structure. |
| 38 | |
| 39 | Within the hardware save state, registers are found in the same order |
| 40 | as the register numbers in GDB. */ |
| 41 | |
| 42 | #define FRAME_SAVED_PC_IN_SIGTRAMP(FRAME, TMP) \ |
| 43 | { \ |
| 44 | *(TMP) = read_memory_integer ((FRAME)->frame + 0x4, 4); \ |
| 45 | *(TMP) = read_memory_integer (*(TMP) + 0x18, 4); \ |
| 46 | } |
| 47 | |
| 48 | #define FRAME_BASE_BEFORE_SIGTRAMP(FRAME, TMP) \ |
| 49 | { \ |
| 50 | *(TMP) = read_memory_integer ((FRAME)->frame + 0x4, 4); \ |
| 51 | *(TMP) = read_memory_integer (*(TMP) + 0x8, 4); \ |
| 52 | } |
| 53 | |
| 54 | #define FRAME_FIND_SAVED_REGS_IN_SIGTRAMP(FRAME, FSR) \ |
| 55 | { \ |
| 56 | int i; \ |
| 57 | CORE_ADDR TMP; \ |
| 58 | TMP = read_memory_integer ((FRAME)->frame + 0x4, 4); \ |
| 59 | TMP = read_memory_integer (TMP + 0x10, 4); \ |
| 60 | for (i = 0; i < NUM_REGS; i++) \ |
| 61 | { \ |
| 62 | if (i == SP_REGNUM) \ |
| 63 | (FSR)->regs[SP_REGNUM] = read_memory_integer (TMP + SP_REGNUM * 4, 4); \ |
| 64 | else \ |
| 65 | (FSR)->regs[i] = TMP + i * 4; \ |
| 66 | } \ |
| 67 | } |
| 68 | |
| 69 | /* OSF1 does not need the pc space queue restored. */ |
| 70 | #define NO_PC_SPACE_QUEUE_RESTORE |
| 71 | |
| 72 | /* The mach kernel uses the recovery counter to implement single |
| 73 | stepping. While this greatly simplifies the kernel support |
| 74 | necessary for single stepping, it unfortunately does the wrong |
| 75 | thing in the presense of a nullified instruction (gives control |
| 76 | back two insns after the nullifed insn). This is an artifact |
| 77 | of the HP architecture (recovery counter doesn't tick for |
| 78 | nullified insns). |
| 79 | |
| 80 | Do our best to avoid losing in such situations. */ |
| 81 | #define INSTRUCTION_NULLIFIED \ |
| 82 | (({ \ |
| 83 | int ipsw = (int)read_register(IPSW_REGNUM); \ |
| 84 | if (ipsw & PSW_N) \ |
| 85 | { \ |
| 86 | int pcoqt = (int)read_register(PCOQ_TAIL_REGNUM); \ |
| 87 | write_register(PCOQ_HEAD_REGNUM, pcoqt); \ |
| 88 | write_register(PCOQ_TAIL_REGNUM, pcoqt + 0x4); \ |
| 89 | write_register(IPSW_REGNUM, ipsw & ~(PSW_N | PSW_B | PSW_X)); \ |
| 90 | stop_pc = pcoqt; \ |
| 91 | } \ |
| 92 | }), 0) |
| 93 | |
| 94 | /* It's mostly just the common stuff. */ |
| 95 | |
| 96 | #include "pa/tm-hppa.h" |