| 1 | /* Target dependent code for CRIS, for GDB, the GNU debugger. |
| 2 | |
| 3 | Copyright (C) 2001-2013 Free Software Foundation, Inc. |
| 4 | |
| 5 | Contributed by Axis Communications AB. |
| 6 | Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg. |
| 7 | |
| 8 | This file is part of GDB. |
| 9 | |
| 10 | This program is free software; you can redistribute it and/or modify |
| 11 | it under the terms of the GNU General Public License as published by |
| 12 | the Free Software Foundation; either version 3 of the License, or |
| 13 | (at your option) any later version. |
| 14 | |
| 15 | This program is distributed in the hope that it will be useful, |
| 16 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | GNU General Public License for more details. |
| 19 | |
| 20 | You should have received a copy of the GNU General Public License |
| 21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 22 | |
| 23 | #include "defs.h" |
| 24 | #include "frame.h" |
| 25 | #include "frame-unwind.h" |
| 26 | #include "frame-base.h" |
| 27 | #include "trad-frame.h" |
| 28 | #include "dwarf2-frame.h" |
| 29 | #include "symtab.h" |
| 30 | #include "inferior.h" |
| 31 | #include "gdbtypes.h" |
| 32 | #include "gdbcore.h" |
| 33 | #include "gdbcmd.h" |
| 34 | #include "target.h" |
| 35 | #include "value.h" |
| 36 | #include "opcode/cris.h" |
| 37 | #include "arch-utils.h" |
| 38 | #include "regcache.h" |
| 39 | #include "gdb_assert.h" |
| 40 | |
| 41 | #include "objfiles.h" |
| 42 | |
| 43 | #include "solib.h" /* Support for shared libraries. */ |
| 44 | #include "solib-svr4.h" |
| 45 | #include "gdb_string.h" |
| 46 | #include "dis-asm.h" |
| 47 | |
| 48 | enum cris_num_regs |
| 49 | { |
| 50 | /* There are no floating point registers. Used in gdbserver low-linux.c. */ |
| 51 | NUM_FREGS = 0, |
| 52 | |
| 53 | /* There are 16 general registers. */ |
| 54 | NUM_GENREGS = 16, |
| 55 | |
| 56 | /* There are 16 special registers. */ |
| 57 | NUM_SPECREGS = 16, |
| 58 | |
| 59 | /* CRISv32 has a pseudo PC register, not noted here. */ |
| 60 | |
| 61 | /* CRISv32 has 16 support registers. */ |
| 62 | NUM_SUPPREGS = 16 |
| 63 | }; |
| 64 | |
| 65 | /* Register numbers of various important registers. |
| 66 | CRIS_FP_REGNUM Contains address of executing stack frame. |
| 67 | STR_REGNUM Contains the address of structure return values. |
| 68 | RET_REGNUM Contains the return value when shorter than or equal to 32 bits |
| 69 | ARG1_REGNUM Contains the first parameter to a function. |
| 70 | ARG2_REGNUM Contains the second parameter to a function. |
| 71 | ARG3_REGNUM Contains the third parameter to a function. |
| 72 | ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack. |
| 73 | gdbarch_sp_regnum Contains address of top of stack. |
| 74 | gdbarch_pc_regnum Contains address of next instruction. |
| 75 | SRP_REGNUM Subroutine return pointer register. |
| 76 | BRP_REGNUM Breakpoint return pointer register. */ |
| 77 | |
| 78 | enum cris_regnums |
| 79 | { |
| 80 | /* Enums with respect to the general registers, valid for all |
| 81 | CRIS versions. The frame pointer is always in R8. */ |
| 82 | CRIS_FP_REGNUM = 8, |
| 83 | /* ABI related registers. */ |
| 84 | STR_REGNUM = 9, |
| 85 | RET_REGNUM = 10, |
| 86 | ARG1_REGNUM = 10, |
| 87 | ARG2_REGNUM = 11, |
| 88 | ARG3_REGNUM = 12, |
| 89 | ARG4_REGNUM = 13, |
| 90 | |
| 91 | /* Registers which happen to be common. */ |
| 92 | VR_REGNUM = 17, |
| 93 | MOF_REGNUM = 23, |
| 94 | SRP_REGNUM = 27, |
| 95 | |
| 96 | /* CRISv10 et al. specific registers. */ |
| 97 | P0_REGNUM = 16, |
| 98 | P4_REGNUM = 20, |
| 99 | CCR_REGNUM = 21, |
| 100 | P8_REGNUM = 24, |
| 101 | IBR_REGNUM = 25, |
| 102 | IRP_REGNUM = 26, |
| 103 | BAR_REGNUM = 28, |
| 104 | DCCR_REGNUM = 29, |
| 105 | BRP_REGNUM = 30, |
| 106 | USP_REGNUM = 31, |
| 107 | |
| 108 | /* CRISv32 specific registers. */ |
| 109 | ACR_REGNUM = 15, |
| 110 | BZ_REGNUM = 16, |
| 111 | PID_REGNUM = 18, |
| 112 | SRS_REGNUM = 19, |
| 113 | WZ_REGNUM = 20, |
| 114 | EXS_REGNUM = 21, |
| 115 | EDA_REGNUM = 22, |
| 116 | DZ_REGNUM = 24, |
| 117 | EBP_REGNUM = 25, |
| 118 | ERP_REGNUM = 26, |
| 119 | NRP_REGNUM = 28, |
| 120 | CCS_REGNUM = 29, |
| 121 | CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */ |
| 122 | SPC_REGNUM = 31, |
| 123 | CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */ |
| 124 | |
| 125 | S0_REGNUM = 33, |
| 126 | S1_REGNUM = 34, |
| 127 | S2_REGNUM = 35, |
| 128 | S3_REGNUM = 36, |
| 129 | S4_REGNUM = 37, |
| 130 | S5_REGNUM = 38, |
| 131 | S6_REGNUM = 39, |
| 132 | S7_REGNUM = 40, |
| 133 | S8_REGNUM = 41, |
| 134 | S9_REGNUM = 42, |
| 135 | S10_REGNUM = 43, |
| 136 | S11_REGNUM = 44, |
| 137 | S12_REGNUM = 45, |
| 138 | S13_REGNUM = 46, |
| 139 | S14_REGNUM = 47, |
| 140 | S15_REGNUM = 48, |
| 141 | }; |
| 142 | |
| 143 | extern const struct cris_spec_reg cris_spec_regs[]; |
| 144 | |
| 145 | /* CRIS version, set via the user command 'set cris-version'. Affects |
| 146 | register names and sizes. */ |
| 147 | static int usr_cmd_cris_version; |
| 148 | |
| 149 | /* Indicates whether to trust the above variable. */ |
| 150 | static int usr_cmd_cris_version_valid = 0; |
| 151 | |
| 152 | static const char cris_mode_normal[] = "normal"; |
| 153 | static const char cris_mode_guru[] = "guru"; |
| 154 | static const char *const cris_modes[] = { |
| 155 | cris_mode_normal, |
| 156 | cris_mode_guru, |
| 157 | 0 |
| 158 | }; |
| 159 | |
| 160 | /* CRIS mode, set via the user command 'set cris-mode'. Affects |
| 161 | type of break instruction among other things. */ |
| 162 | static const char *usr_cmd_cris_mode = cris_mode_normal; |
| 163 | |
| 164 | /* Whether to make use of Dwarf-2 CFI (default on). */ |
| 165 | static int usr_cmd_cris_dwarf2_cfi = 1; |
| 166 | |
| 167 | /* CRIS architecture specific information. */ |
| 168 | struct gdbarch_tdep |
| 169 | { |
| 170 | int cris_version; |
| 171 | const char *cris_mode; |
| 172 | int cris_dwarf2_cfi; |
| 173 | }; |
| 174 | |
| 175 | /* Sigtramp identification code copied from i386-linux-tdep.c. */ |
| 176 | |
| 177 | #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */ |
| 178 | #define SIGTRAMP_OFFSET0 0 |
| 179 | #define SIGTRAMP_INSN1 0xe93d /* break 13 */ |
| 180 | #define SIGTRAMP_OFFSET1 4 |
| 181 | |
| 182 | static const unsigned short sigtramp_code[] = |
| 183 | { |
| 184 | SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */ |
| 185 | SIGTRAMP_INSN1 /* break 13 */ |
| 186 | }; |
| 187 | |
| 188 | #define SIGTRAMP_LEN (sizeof sigtramp_code) |
| 189 | |
| 190 | /* Note: same length as normal sigtramp code. */ |
| 191 | |
| 192 | static const unsigned short rt_sigtramp_code[] = |
| 193 | { |
| 194 | SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */ |
| 195 | SIGTRAMP_INSN1 /* break 13 */ |
| 196 | }; |
| 197 | |
| 198 | /* If PC is in a sigtramp routine, return the address of the start of |
| 199 | the routine. Otherwise, return 0. */ |
| 200 | |
| 201 | static CORE_ADDR |
| 202 | cris_sigtramp_start (struct frame_info *this_frame) |
| 203 | { |
| 204 | CORE_ADDR pc = get_frame_pc (this_frame); |
| 205 | gdb_byte buf[SIGTRAMP_LEN]; |
| 206 | |
| 207 | if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN)) |
| 208 | return 0; |
| 209 | |
| 210 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0) |
| 211 | { |
| 212 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1) |
| 213 | return 0; |
| 214 | |
| 215 | pc -= SIGTRAMP_OFFSET1; |
| 216 | if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN)) |
| 217 | return 0; |
| 218 | } |
| 219 | |
| 220 | if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0) |
| 221 | return 0; |
| 222 | |
| 223 | return pc; |
| 224 | } |
| 225 | |
| 226 | /* If PC is in a RT sigtramp routine, return the address of the start of |
| 227 | the routine. Otherwise, return 0. */ |
| 228 | |
| 229 | static CORE_ADDR |
| 230 | cris_rt_sigtramp_start (struct frame_info *this_frame) |
| 231 | { |
| 232 | CORE_ADDR pc = get_frame_pc (this_frame); |
| 233 | gdb_byte buf[SIGTRAMP_LEN]; |
| 234 | |
| 235 | if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN)) |
| 236 | return 0; |
| 237 | |
| 238 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0) |
| 239 | { |
| 240 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1) |
| 241 | return 0; |
| 242 | |
| 243 | pc -= SIGTRAMP_OFFSET1; |
| 244 | if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN)) |
| 245 | return 0; |
| 246 | } |
| 247 | |
| 248 | if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0) |
| 249 | return 0; |
| 250 | |
| 251 | return pc; |
| 252 | } |
| 253 | |
| 254 | /* Assuming THIS_FRAME is a frame for a GNU/Linux sigtramp routine, |
| 255 | return the address of the associated sigcontext structure. */ |
| 256 | |
| 257 | static CORE_ADDR |
| 258 | cris_sigcontext_addr (struct frame_info *this_frame) |
| 259 | { |
| 260 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 261 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 262 | CORE_ADDR pc; |
| 263 | CORE_ADDR sp; |
| 264 | gdb_byte buf[4]; |
| 265 | |
| 266 | get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf); |
| 267 | sp = extract_unsigned_integer (buf, 4, byte_order); |
| 268 | |
| 269 | /* Look for normal sigtramp frame first. */ |
| 270 | pc = cris_sigtramp_start (this_frame); |
| 271 | if (pc) |
| 272 | { |
| 273 | /* struct signal_frame (arch/cris/kernel/signal.c) contains |
| 274 | struct sigcontext as its first member, meaning the SP points to |
| 275 | it already. */ |
| 276 | return sp; |
| 277 | } |
| 278 | |
| 279 | pc = cris_rt_sigtramp_start (this_frame); |
| 280 | if (pc) |
| 281 | { |
| 282 | /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains |
| 283 | a struct ucontext, which in turn contains a struct sigcontext. |
| 284 | Magic digging: |
| 285 | 4 + 4 + 128 to struct ucontext, then |
| 286 | 4 + 4 + 12 to struct sigcontext. */ |
| 287 | return (sp + 156); |
| 288 | } |
| 289 | |
| 290 | error (_("Couldn't recognize signal trampoline.")); |
| 291 | return 0; |
| 292 | } |
| 293 | |
| 294 | struct cris_unwind_cache |
| 295 | { |
| 296 | /* The previous frame's inner most stack address. Used as this |
| 297 | frame ID's stack_addr. */ |
| 298 | CORE_ADDR prev_sp; |
| 299 | /* The frame's base, optionally used by the high-level debug info. */ |
| 300 | CORE_ADDR base; |
| 301 | int size; |
| 302 | /* How far the SP and r8 (FP) have been offset from the start of |
| 303 | the stack frame (as defined by the previous frame's stack |
| 304 | pointer). */ |
| 305 | LONGEST sp_offset; |
| 306 | LONGEST r8_offset; |
| 307 | int uses_frame; |
| 308 | |
| 309 | /* From old frame_extra_info struct. */ |
| 310 | CORE_ADDR return_pc; |
| 311 | int leaf_function; |
| 312 | |
| 313 | /* Table indicating the location of each and every register. */ |
| 314 | struct trad_frame_saved_reg *saved_regs; |
| 315 | }; |
| 316 | |
| 317 | static struct cris_unwind_cache * |
| 318 | cris_sigtramp_frame_unwind_cache (struct frame_info *this_frame, |
| 319 | void **this_cache) |
| 320 | { |
| 321 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 322 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 323 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 324 | struct cris_unwind_cache *info; |
| 325 | CORE_ADDR addr; |
| 326 | gdb_byte buf[4]; |
| 327 | int i; |
| 328 | |
| 329 | if ((*this_cache)) |
| 330 | return (*this_cache); |
| 331 | |
| 332 | info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); |
| 333 | (*this_cache) = info; |
| 334 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
| 335 | |
| 336 | /* Zero all fields. */ |
| 337 | info->prev_sp = 0; |
| 338 | info->base = 0; |
| 339 | info->size = 0; |
| 340 | info->sp_offset = 0; |
| 341 | info->r8_offset = 0; |
| 342 | info->uses_frame = 0; |
| 343 | info->return_pc = 0; |
| 344 | info->leaf_function = 0; |
| 345 | |
| 346 | get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf); |
| 347 | info->base = extract_unsigned_integer (buf, 4, byte_order); |
| 348 | |
| 349 | addr = cris_sigcontext_addr (this_frame); |
| 350 | |
| 351 | /* Layout of the sigcontext struct: |
| 352 | struct sigcontext { |
| 353 | struct pt_regs regs; |
| 354 | unsigned long oldmask; |
| 355 | unsigned long usp; |
| 356 | }; */ |
| 357 | |
| 358 | if (tdep->cris_version == 10) |
| 359 | { |
| 360 | /* R0 to R13 are stored in reverse order at offset (2 * 4) in |
| 361 | struct pt_regs. */ |
| 362 | for (i = 0; i <= 13; i++) |
| 363 | info->saved_regs[i].addr = addr + ((15 - i) * 4); |
| 364 | |
| 365 | info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4); |
| 366 | info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4); |
| 367 | info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4); |
| 368 | /* Note: IRP is off by 2 at this point. There's no point in correcting |
| 369 | it though since that will mean that the backtrace will show a PC |
| 370 | different from what is shown when stopped. */ |
| 371 | info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4); |
| 372 | info->saved_regs[gdbarch_pc_regnum (gdbarch)] |
| 373 | = info->saved_regs[IRP_REGNUM]; |
| 374 | info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr = addr + (24 * 4); |
| 375 | } |
| 376 | else |
| 377 | { |
| 378 | /* CRISv32. */ |
| 379 | /* R0 to R13 are stored in order at offset (1 * 4) in |
| 380 | struct pt_regs. */ |
| 381 | for (i = 0; i <= 13; i++) |
| 382 | info->saved_regs[i].addr = addr + ((i + 1) * 4); |
| 383 | |
| 384 | info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4); |
| 385 | info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4); |
| 386 | info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4); |
| 387 | info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4); |
| 388 | info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4); |
| 389 | info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4); |
| 390 | info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4); |
| 391 | info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4); |
| 392 | info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4); |
| 393 | |
| 394 | /* FIXME: If ERP is in a delay slot at this point then the PC will |
| 395 | be wrong at this point. This problem manifests itself in the |
| 396 | sigaltstack.exp test case, which occasionally generates FAILs when |
| 397 | the signal is received while in a delay slot. |
| 398 | |
| 399 | This could be solved by a couple of read_memory_unsigned_integer and a |
| 400 | trad_frame_set_value. */ |
| 401 | info->saved_regs[gdbarch_pc_regnum (gdbarch)] |
| 402 | = info->saved_regs[ERP_REGNUM]; |
| 403 | |
| 404 | info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr |
| 405 | = addr + (25 * 4); |
| 406 | } |
| 407 | |
| 408 | return info; |
| 409 | } |
| 410 | |
| 411 | static void |
| 412 | cris_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
| 413 | struct frame_id *this_id) |
| 414 | { |
| 415 | struct cris_unwind_cache *cache = |
| 416 | cris_sigtramp_frame_unwind_cache (this_frame, this_cache); |
| 417 | (*this_id) = frame_id_build (cache->base, get_frame_pc (this_frame)); |
| 418 | } |
| 419 | |
| 420 | /* Forward declaration. */ |
| 421 | |
| 422 | static struct value *cris_frame_prev_register (struct frame_info *this_frame, |
| 423 | void **this_cache, int regnum); |
| 424 | static struct value * |
| 425 | cris_sigtramp_frame_prev_register (struct frame_info *this_frame, |
| 426 | void **this_cache, int regnum) |
| 427 | { |
| 428 | /* Make sure we've initialized the cache. */ |
| 429 | cris_sigtramp_frame_unwind_cache (this_frame, this_cache); |
| 430 | return cris_frame_prev_register (this_frame, this_cache, regnum); |
| 431 | } |
| 432 | |
| 433 | static int |
| 434 | cris_sigtramp_frame_sniffer (const struct frame_unwind *self, |
| 435 | struct frame_info *this_frame, |
| 436 | void **this_cache) |
| 437 | { |
| 438 | if (cris_sigtramp_start (this_frame) |
| 439 | || cris_rt_sigtramp_start (this_frame)) |
| 440 | return 1; |
| 441 | |
| 442 | return 0; |
| 443 | } |
| 444 | |
| 445 | static const struct frame_unwind cris_sigtramp_frame_unwind = |
| 446 | { |
| 447 | SIGTRAMP_FRAME, |
| 448 | default_frame_unwind_stop_reason, |
| 449 | cris_sigtramp_frame_this_id, |
| 450 | cris_sigtramp_frame_prev_register, |
| 451 | NULL, |
| 452 | cris_sigtramp_frame_sniffer |
| 453 | }; |
| 454 | |
| 455 | static int |
| 456 | crisv32_single_step_through_delay (struct gdbarch *gdbarch, |
| 457 | struct frame_info *this_frame) |
| 458 | { |
| 459 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 460 | ULONGEST erp; |
| 461 | int ret = 0; |
| 462 | |
| 463 | if (tdep->cris_mode == cris_mode_guru) |
| 464 | erp = get_frame_register_unsigned (this_frame, NRP_REGNUM); |
| 465 | else |
| 466 | erp = get_frame_register_unsigned (this_frame, ERP_REGNUM); |
| 467 | |
| 468 | if (erp & 0x1) |
| 469 | { |
| 470 | /* In delay slot - check if there's a breakpoint at the preceding |
| 471 | instruction. */ |
| 472 | if (breakpoint_here_p (get_frame_address_space (this_frame), erp & ~0x1)) |
| 473 | ret = 1; |
| 474 | } |
| 475 | return ret; |
| 476 | } |
| 477 | |
| 478 | /* The instruction environment needed to find single-step breakpoints. */ |
| 479 | |
| 480 | typedef |
| 481 | struct instruction_environment |
| 482 | { |
| 483 | unsigned long reg[NUM_GENREGS]; |
| 484 | unsigned long preg[NUM_SPECREGS]; |
| 485 | unsigned long branch_break_address; |
| 486 | unsigned long delay_slot_pc; |
| 487 | unsigned long prefix_value; |
| 488 | int branch_found; |
| 489 | int prefix_found; |
| 490 | int invalid; |
| 491 | int slot_needed; |
| 492 | int delay_slot_pc_active; |
| 493 | int xflag_found; |
| 494 | int disable_interrupt; |
| 495 | int byte_order; |
| 496 | } inst_env_type; |
| 497 | |
| 498 | /* Machine-dependencies in CRIS for opcodes. */ |
| 499 | |
| 500 | /* Instruction sizes. */ |
| 501 | enum cris_instruction_sizes |
| 502 | { |
| 503 | INST_BYTE_SIZE = 0, |
| 504 | INST_WORD_SIZE = 1, |
| 505 | INST_DWORD_SIZE = 2 |
| 506 | }; |
| 507 | |
| 508 | /* Addressing modes. */ |
| 509 | enum cris_addressing_modes |
| 510 | { |
| 511 | REGISTER_MODE = 1, |
| 512 | INDIRECT_MODE = 2, |
| 513 | AUTOINC_MODE = 3 |
| 514 | }; |
| 515 | |
| 516 | /* Prefix addressing modes. */ |
| 517 | enum cris_prefix_addressing_modes |
| 518 | { |
| 519 | PREFIX_INDEX_MODE = 2, |
| 520 | PREFIX_ASSIGN_MODE = 3, |
| 521 | |
| 522 | /* Handle immediate byte offset addressing mode prefix format. */ |
| 523 | PREFIX_OFFSET_MODE = 2 |
| 524 | }; |
| 525 | |
| 526 | /* Masks for opcodes. */ |
| 527 | enum cris_opcode_masks |
| 528 | { |
| 529 | BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1, |
| 530 | SIGNED_EXTEND_BIT_MASK = 0x2, |
| 531 | SIGNED_BYTE_MASK = 0x80, |
| 532 | SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00, |
| 533 | SIGNED_WORD_MASK = 0x8000, |
| 534 | SIGNED_WORD_EXTEND_MASK = 0xFFFF0000, |
| 535 | SIGNED_DWORD_MASK = 0x80000000, |
| 536 | SIGNED_QUICK_VALUE_MASK = 0x20, |
| 537 | SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0 |
| 538 | }; |
| 539 | |
| 540 | /* Functions for opcodes. The general form of the ETRAX 16-bit instruction: |
| 541 | Bit 15 - 12 Operand2 |
| 542 | 11 - 10 Mode |
| 543 | 9 - 6 Opcode |
| 544 | 5 - 4 Size |
| 545 | 3 - 0 Operand1 */ |
| 546 | |
| 547 | static int |
| 548 | cris_get_operand2 (unsigned short insn) |
| 549 | { |
| 550 | return ((insn & 0xF000) >> 12); |
| 551 | } |
| 552 | |
| 553 | static int |
| 554 | cris_get_mode (unsigned short insn) |
| 555 | { |
| 556 | return ((insn & 0x0C00) >> 10); |
| 557 | } |
| 558 | |
| 559 | static int |
| 560 | cris_get_opcode (unsigned short insn) |
| 561 | { |
| 562 | return ((insn & 0x03C0) >> 6); |
| 563 | } |
| 564 | |
| 565 | static int |
| 566 | cris_get_size (unsigned short insn) |
| 567 | { |
| 568 | return ((insn & 0x0030) >> 4); |
| 569 | } |
| 570 | |
| 571 | static int |
| 572 | cris_get_operand1 (unsigned short insn) |
| 573 | { |
| 574 | return (insn & 0x000F); |
| 575 | } |
| 576 | |
| 577 | /* Additional functions in order to handle opcodes. */ |
| 578 | |
| 579 | static int |
| 580 | cris_get_quick_value (unsigned short insn) |
| 581 | { |
| 582 | return (insn & 0x003F); |
| 583 | } |
| 584 | |
| 585 | static int |
| 586 | cris_get_bdap_quick_offset (unsigned short insn) |
| 587 | { |
| 588 | return (insn & 0x00FF); |
| 589 | } |
| 590 | |
| 591 | static int |
| 592 | cris_get_branch_short_offset (unsigned short insn) |
| 593 | { |
| 594 | return (insn & 0x00FF); |
| 595 | } |
| 596 | |
| 597 | static int |
| 598 | cris_get_asr_shift_steps (unsigned long value) |
| 599 | { |
| 600 | return (value & 0x3F); |
| 601 | } |
| 602 | |
| 603 | static int |
| 604 | cris_get_clear_size (unsigned short insn) |
| 605 | { |
| 606 | return ((insn) & 0xC000); |
| 607 | } |
| 608 | |
| 609 | static int |
| 610 | cris_is_signed_extend_bit_on (unsigned short insn) |
| 611 | { |
| 612 | return (((insn) & 0x20) == 0x20); |
| 613 | } |
| 614 | |
| 615 | static int |
| 616 | cris_is_xflag_bit_on (unsigned short insn) |
| 617 | { |
| 618 | return (((insn) & 0x1000) == 0x1000); |
| 619 | } |
| 620 | |
| 621 | static void |
| 622 | cris_set_size_to_dword (unsigned short *insn) |
| 623 | { |
| 624 | *insn &= 0xFFCF; |
| 625 | *insn |= 0x20; |
| 626 | } |
| 627 | |
| 628 | static signed char |
| 629 | cris_get_signed_offset (unsigned short insn) |
| 630 | { |
| 631 | return ((signed char) (insn & 0x00FF)); |
| 632 | } |
| 633 | |
| 634 | /* Calls an op function given the op-type, working on the insn and the |
| 635 | inst_env. */ |
| 636 | static void cris_gdb_func (struct gdbarch *, enum cris_op_type, unsigned short, |
| 637 | inst_env_type *); |
| 638 | |
| 639 | static struct gdbarch *cris_gdbarch_init (struct gdbarch_info, |
| 640 | struct gdbarch_list *); |
| 641 | |
| 642 | static void cris_dump_tdep (struct gdbarch *, struct ui_file *); |
| 643 | |
| 644 | static void set_cris_version (char *ignore_args, int from_tty, |
| 645 | struct cmd_list_element *c); |
| 646 | |
| 647 | static void set_cris_mode (char *ignore_args, int from_tty, |
| 648 | struct cmd_list_element *c); |
| 649 | |
| 650 | static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty, |
| 651 | struct cmd_list_element *c); |
| 652 | |
| 653 | static CORE_ADDR cris_scan_prologue (CORE_ADDR pc, |
| 654 | struct frame_info *this_frame, |
| 655 | struct cris_unwind_cache *info); |
| 656 | |
| 657 | static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc, |
| 658 | struct frame_info *this_frame, |
| 659 | struct cris_unwind_cache *info); |
| 660 | |
| 661 | static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch, |
| 662 | struct frame_info *next_frame); |
| 663 | |
| 664 | static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch, |
| 665 | struct frame_info *next_frame); |
| 666 | |
| 667 | /* When arguments must be pushed onto the stack, they go on in reverse |
| 668 | order. The below implements a FILO (stack) to do this. |
| 669 | Copied from d10v-tdep.c. */ |
| 670 | |
| 671 | struct stack_item |
| 672 | { |
| 673 | int len; |
| 674 | struct stack_item *prev; |
| 675 | void *data; |
| 676 | }; |
| 677 | |
| 678 | static struct stack_item * |
| 679 | push_stack_item (struct stack_item *prev, void *contents, int len) |
| 680 | { |
| 681 | struct stack_item *si; |
| 682 | si = xmalloc (sizeof (struct stack_item)); |
| 683 | si->data = xmalloc (len); |
| 684 | si->len = len; |
| 685 | si->prev = prev; |
| 686 | memcpy (si->data, contents, len); |
| 687 | return si; |
| 688 | } |
| 689 | |
| 690 | static struct stack_item * |
| 691 | pop_stack_item (struct stack_item *si) |
| 692 | { |
| 693 | struct stack_item *dead = si; |
| 694 | si = si->prev; |
| 695 | xfree (dead->data); |
| 696 | xfree (dead); |
| 697 | return si; |
| 698 | } |
| 699 | |
| 700 | /* Put here the code to store, into fi->saved_regs, the addresses of |
| 701 | the saved registers of frame described by FRAME_INFO. This |
| 702 | includes special registers such as pc and fp saved in special ways |
| 703 | in the stack frame. sp is even more special: the address we return |
| 704 | for it IS the sp for the next frame. */ |
| 705 | |
| 706 | static struct cris_unwind_cache * |
| 707 | cris_frame_unwind_cache (struct frame_info *this_frame, |
| 708 | void **this_prologue_cache) |
| 709 | { |
| 710 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 711 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 712 | struct cris_unwind_cache *info; |
| 713 | |
| 714 | if ((*this_prologue_cache)) |
| 715 | return (*this_prologue_cache); |
| 716 | |
| 717 | info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); |
| 718 | (*this_prologue_cache) = info; |
| 719 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
| 720 | |
| 721 | /* Zero all fields. */ |
| 722 | info->prev_sp = 0; |
| 723 | info->base = 0; |
| 724 | info->size = 0; |
| 725 | info->sp_offset = 0; |
| 726 | info->r8_offset = 0; |
| 727 | info->uses_frame = 0; |
| 728 | info->return_pc = 0; |
| 729 | info->leaf_function = 0; |
| 730 | |
| 731 | /* Prologue analysis does the rest... */ |
| 732 | if (tdep->cris_version == 32) |
| 733 | crisv32_scan_prologue (get_frame_func (this_frame), this_frame, info); |
| 734 | else |
| 735 | cris_scan_prologue (get_frame_func (this_frame), this_frame, info); |
| 736 | |
| 737 | return info; |
| 738 | } |
| 739 | |
| 740 | /* Given a GDB frame, determine the address of the calling function's |
| 741 | frame. This will be used to create a new GDB frame struct. */ |
| 742 | |
| 743 | static void |
| 744 | cris_frame_this_id (struct frame_info *this_frame, |
| 745 | void **this_prologue_cache, |
| 746 | struct frame_id *this_id) |
| 747 | { |
| 748 | struct cris_unwind_cache *info |
| 749 | = cris_frame_unwind_cache (this_frame, this_prologue_cache); |
| 750 | CORE_ADDR base; |
| 751 | CORE_ADDR func; |
| 752 | struct frame_id id; |
| 753 | |
| 754 | /* The FUNC is easy. */ |
| 755 | func = get_frame_func (this_frame); |
| 756 | |
| 757 | /* Hopefully the prologue analysis either correctly determined the |
| 758 | frame's base (which is the SP from the previous frame), or set |
| 759 | that base to "NULL". */ |
| 760 | base = info->prev_sp; |
| 761 | if (base == 0) |
| 762 | return; |
| 763 | |
| 764 | id = frame_id_build (base, func); |
| 765 | |
| 766 | (*this_id) = id; |
| 767 | } |
| 768 | |
| 769 | static struct value * |
| 770 | cris_frame_prev_register (struct frame_info *this_frame, |
| 771 | void **this_prologue_cache, int regnum) |
| 772 | { |
| 773 | struct cris_unwind_cache *info |
| 774 | = cris_frame_unwind_cache (this_frame, this_prologue_cache); |
| 775 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
| 776 | } |
| 777 | |
| 778 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy |
| 779 | frame. The frame ID's base needs to match the TOS value saved by |
| 780 | save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */ |
| 781 | |
| 782 | static struct frame_id |
| 783 | cris_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 784 | { |
| 785 | CORE_ADDR sp; |
| 786 | sp = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch)); |
| 787 | return frame_id_build (sp, get_frame_pc (this_frame)); |
| 788 | } |
| 789 | |
| 790 | static CORE_ADDR |
| 791 | cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) |
| 792 | { |
| 793 | /* Align to the size of an instruction (so that they can safely be |
| 794 | pushed onto the stack). */ |
| 795 | return sp & ~3; |
| 796 | } |
| 797 | |
| 798 | static CORE_ADDR |
| 799 | cris_push_dummy_code (struct gdbarch *gdbarch, |
| 800 | CORE_ADDR sp, CORE_ADDR funaddr, |
| 801 | struct value **args, int nargs, |
| 802 | struct type *value_type, |
| 803 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
| 804 | struct regcache *regcache) |
| 805 | { |
| 806 | /* Allocate space sufficient for a breakpoint. */ |
| 807 | sp = (sp - 4) & ~3; |
| 808 | /* Store the address of that breakpoint */ |
| 809 | *bp_addr = sp; |
| 810 | /* CRIS always starts the call at the callee's entry point. */ |
| 811 | *real_pc = funaddr; |
| 812 | return sp; |
| 813 | } |
| 814 | |
| 815 | static CORE_ADDR |
| 816 | cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 817 | struct regcache *regcache, CORE_ADDR bp_addr, |
| 818 | int nargs, struct value **args, CORE_ADDR sp, |
| 819 | int struct_return, CORE_ADDR struct_addr) |
| 820 | { |
| 821 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 822 | int stack_offset; |
| 823 | int argreg; |
| 824 | int argnum; |
| 825 | |
| 826 | /* The function's arguments and memory allocated by gdb for the arguments to |
| 827 | point at reside in separate areas on the stack. |
| 828 | Both frame pointers grow toward higher addresses. */ |
| 829 | CORE_ADDR fp_arg; |
| 830 | CORE_ADDR fp_mem; |
| 831 | |
| 832 | struct stack_item *si = NULL; |
| 833 | |
| 834 | /* Push the return address. */ |
| 835 | regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr); |
| 836 | |
| 837 | /* Are we returning a value using a structure return or a normal value |
| 838 | return? struct_addr is the address of the reserved space for the return |
| 839 | structure to be written on the stack. */ |
| 840 | if (struct_return) |
| 841 | { |
| 842 | regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr); |
| 843 | } |
| 844 | |
| 845 | /* Now load as many as possible of the first arguments into registers, |
| 846 | and push the rest onto the stack. */ |
| 847 | argreg = ARG1_REGNUM; |
| 848 | stack_offset = 0; |
| 849 | |
| 850 | for (argnum = 0; argnum < nargs; argnum++) |
| 851 | { |
| 852 | int len; |
| 853 | char *val; |
| 854 | int reg_demand; |
| 855 | int i; |
| 856 | |
| 857 | len = TYPE_LENGTH (value_type (args[argnum])); |
| 858 | val = (char *) value_contents (args[argnum]); |
| 859 | |
| 860 | /* How may registers worth of storage do we need for this argument? */ |
| 861 | reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0); |
| 862 | |
| 863 | if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM)) |
| 864 | { |
| 865 | /* Data passed by value. Fits in available register(s). */ |
| 866 | for (i = 0; i < reg_demand; i++) |
| 867 | { |
| 868 | regcache_cooked_write (regcache, argreg, val); |
| 869 | argreg++; |
| 870 | val += 4; |
| 871 | } |
| 872 | } |
| 873 | else if (len <= (2 * 4) && argreg <= ARG4_REGNUM) |
| 874 | { |
| 875 | /* Data passed by value. Does not fit in available register(s). |
| 876 | Use the register(s) first, then the stack. */ |
| 877 | for (i = 0; i < reg_demand; i++) |
| 878 | { |
| 879 | if (argreg <= ARG4_REGNUM) |
| 880 | { |
| 881 | regcache_cooked_write (regcache, argreg, val); |
| 882 | argreg++; |
| 883 | val += 4; |
| 884 | } |
| 885 | else |
| 886 | { |
| 887 | /* Push item for later so that pushed arguments |
| 888 | come in the right order. */ |
| 889 | si = push_stack_item (si, val, 4); |
| 890 | val += 4; |
| 891 | } |
| 892 | } |
| 893 | } |
| 894 | else if (len > (2 * 4)) |
| 895 | { |
| 896 | /* Data passed by reference. Push copy of data onto stack |
| 897 | and pass pointer to this copy as argument. */ |
| 898 | sp = (sp - len) & ~3; |
| 899 | write_memory (sp, val, len); |
| 900 | |
| 901 | if (argreg <= ARG4_REGNUM) |
| 902 | { |
| 903 | regcache_cooked_write_unsigned (regcache, argreg, sp); |
| 904 | argreg++; |
| 905 | } |
| 906 | else |
| 907 | { |
| 908 | gdb_byte buf[4]; |
| 909 | store_unsigned_integer (buf, 4, byte_order, sp); |
| 910 | si = push_stack_item (si, buf, 4); |
| 911 | } |
| 912 | } |
| 913 | else |
| 914 | { |
| 915 | /* Data passed by value. No available registers. Put it on |
| 916 | the stack. */ |
| 917 | si = push_stack_item (si, val, len); |
| 918 | } |
| 919 | } |
| 920 | |
| 921 | while (si) |
| 922 | { |
| 923 | /* fp_arg must be word-aligned (i.e., don't += len) to match |
| 924 | the function prologue. */ |
| 925 | sp = (sp - si->len) & ~3; |
| 926 | write_memory (sp, si->data, si->len); |
| 927 | si = pop_stack_item (si); |
| 928 | } |
| 929 | |
| 930 | /* Finally, update the SP register. */ |
| 931 | regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp); |
| 932 | |
| 933 | return sp; |
| 934 | } |
| 935 | |
| 936 | static const struct frame_unwind cris_frame_unwind = |
| 937 | { |
| 938 | NORMAL_FRAME, |
| 939 | default_frame_unwind_stop_reason, |
| 940 | cris_frame_this_id, |
| 941 | cris_frame_prev_register, |
| 942 | NULL, |
| 943 | default_frame_sniffer |
| 944 | }; |
| 945 | |
| 946 | static CORE_ADDR |
| 947 | cris_frame_base_address (struct frame_info *this_frame, void **this_cache) |
| 948 | { |
| 949 | struct cris_unwind_cache *info |
| 950 | = cris_frame_unwind_cache (this_frame, this_cache); |
| 951 | return info->base; |
| 952 | } |
| 953 | |
| 954 | static const struct frame_base cris_frame_base = |
| 955 | { |
| 956 | &cris_frame_unwind, |
| 957 | cris_frame_base_address, |
| 958 | cris_frame_base_address, |
| 959 | cris_frame_base_address |
| 960 | }; |
| 961 | |
| 962 | /* Frames information. The definition of the struct frame_info is |
| 963 | |
| 964 | CORE_ADDR frame |
| 965 | CORE_ADDR pc |
| 966 | enum frame_type type; |
| 967 | CORE_ADDR return_pc |
| 968 | int leaf_function |
| 969 | |
| 970 | If the compilation option -fno-omit-frame-pointer is present the |
| 971 | variable frame will be set to the content of R8 which is the frame |
| 972 | pointer register. |
| 973 | |
| 974 | The variable pc contains the address where execution is performed |
| 975 | in the present frame. The innermost frame contains the current content |
| 976 | of the register PC. All other frames contain the content of the |
| 977 | register PC in the next frame. |
| 978 | |
| 979 | The variable `type' indicates the frame's type: normal, SIGTRAMP |
| 980 | (associated with a signal handler), dummy (associated with a dummy |
| 981 | frame). |
| 982 | |
| 983 | The variable return_pc contains the address where execution should be |
| 984 | resumed when the present frame has finished, the return address. |
| 985 | |
| 986 | The variable leaf_function is 1 if the return address is in the register |
| 987 | SRP, and 0 if it is on the stack. |
| 988 | |
| 989 | Prologue instructions C-code. |
| 990 | The prologue may consist of (-fno-omit-frame-pointer) |
| 991 | 1) 2) |
| 992 | push srp |
| 993 | push r8 push r8 |
| 994 | move.d sp,r8 move.d sp,r8 |
| 995 | subq X,sp subq X,sp |
| 996 | movem rY,[sp] movem rY,[sp] |
| 997 | move.S rZ,[r8-U] move.S rZ,[r8-U] |
| 998 | |
| 999 | where 1 is a non-terminal function, and 2 is a leaf-function. |
| 1000 | |
| 1001 | Note that this assumption is extremely brittle, and will break at the |
| 1002 | slightest change in GCC's prologue. |
| 1003 | |
| 1004 | If local variables are declared or register contents are saved on stack |
| 1005 | the subq-instruction will be present with X as the number of bytes |
| 1006 | needed for storage. The reshuffle with respect to r8 may be performed |
| 1007 | with any size S (b, w, d) and any of the general registers Z={0..13}. |
| 1008 | The offset U should be representable by a signed 8-bit value in all cases. |
| 1009 | Thus, the prefix word is assumed to be immediate byte offset mode followed |
| 1010 | by another word containing the instruction. |
| 1011 | |
| 1012 | Degenerate cases: |
| 1013 | 3) |
| 1014 | push r8 |
| 1015 | move.d sp,r8 |
| 1016 | move.d r8,sp |
| 1017 | pop r8 |
| 1018 | |
| 1019 | Prologue instructions C++-code. |
| 1020 | Case 1) and 2) in the C-code may be followed by |
| 1021 | |
| 1022 | move.d r10,rS ; this |
| 1023 | move.d r11,rT ; P1 |
| 1024 | move.d r12,rU ; P2 |
| 1025 | move.d r13,rV ; P3 |
| 1026 | move.S [r8+U],rZ ; P4 |
| 1027 | |
| 1028 | if any of the call parameters are stored. The host expects these |
| 1029 | instructions to be executed in order to get the call parameters right. */ |
| 1030 | |
| 1031 | /* Examine the prologue of a function. The variable ip is the address of |
| 1032 | the first instruction of the prologue. The variable limit is the address |
| 1033 | of the first instruction after the prologue. The variable fi contains the |
| 1034 | information in struct frame_info. The variable frameless_p controls whether |
| 1035 | the entire prologue is examined (0) or just enough instructions to |
| 1036 | determine that it is a prologue (1). */ |
| 1037 | |
| 1038 | static CORE_ADDR |
| 1039 | cris_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame, |
| 1040 | struct cris_unwind_cache *info) |
| 1041 | { |
| 1042 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 1043 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1044 | |
| 1045 | /* Present instruction. */ |
| 1046 | unsigned short insn; |
| 1047 | |
| 1048 | /* Next instruction, lookahead. */ |
| 1049 | unsigned short insn_next; |
| 1050 | int regno; |
| 1051 | |
| 1052 | /* Is there a push fp? */ |
| 1053 | int have_fp; |
| 1054 | |
| 1055 | /* Number of byte on stack used for local variables and movem. */ |
| 1056 | int val; |
| 1057 | |
| 1058 | /* Highest register number in a movem. */ |
| 1059 | int regsave; |
| 1060 | |
| 1061 | /* move.d r<source_register>,rS */ |
| 1062 | short source_register; |
| 1063 | |
| 1064 | /* Scan limit. */ |
| 1065 | int limit; |
| 1066 | |
| 1067 | /* This frame is with respect to a leaf until a push srp is found. */ |
| 1068 | if (info) |
| 1069 | { |
| 1070 | info->leaf_function = 1; |
| 1071 | } |
| 1072 | |
| 1073 | /* Assume nothing on stack. */ |
| 1074 | val = 0; |
| 1075 | regsave = -1; |
| 1076 | |
| 1077 | /* If we were called without a this_frame, that means we were called |
| 1078 | from cris_skip_prologue which already tried to find the end of the |
| 1079 | prologue through the symbol information. 64 instructions past current |
| 1080 | pc is arbitrarily chosen, but at least it means we'll stop eventually. */ |
| 1081 | limit = this_frame ? get_frame_pc (this_frame) : pc + 64; |
| 1082 | |
| 1083 | /* Find the prologue instructions. */ |
| 1084 | while (pc > 0 && pc < limit) |
| 1085 | { |
| 1086 | insn = read_memory_unsigned_integer (pc, 2, byte_order); |
| 1087 | pc += 2; |
| 1088 | if (insn == 0xE1FC) |
| 1089 | { |
| 1090 | /* push <reg> 32 bit instruction. */ |
| 1091 | insn_next = read_memory_unsigned_integer (pc, 2, byte_order); |
| 1092 | pc += 2; |
| 1093 | regno = cris_get_operand2 (insn_next); |
| 1094 | if (info) |
| 1095 | { |
| 1096 | info->sp_offset += 4; |
| 1097 | } |
| 1098 | /* This check, meant to recognize srp, used to be regno == |
| 1099 | (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */ |
| 1100 | if (insn_next == 0xBE7E) |
| 1101 | { |
| 1102 | if (info) |
| 1103 | { |
| 1104 | info->leaf_function = 0; |
| 1105 | } |
| 1106 | } |
| 1107 | else if (insn_next == 0x8FEE) |
| 1108 | { |
| 1109 | /* push $r8 */ |
| 1110 | if (info) |
| 1111 | { |
| 1112 | info->r8_offset = info->sp_offset; |
| 1113 | } |
| 1114 | } |
| 1115 | } |
| 1116 | else if (insn == 0x866E) |
| 1117 | { |
| 1118 | /* move.d sp,r8 */ |
| 1119 | if (info) |
| 1120 | { |
| 1121 | info->uses_frame = 1; |
| 1122 | } |
| 1123 | continue; |
| 1124 | } |
| 1125 | else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch) |
| 1126 | && cris_get_mode (insn) == 0x0000 |
| 1127 | && cris_get_opcode (insn) == 0x000A) |
| 1128 | { |
| 1129 | /* subq <val>,sp */ |
| 1130 | if (info) |
| 1131 | { |
| 1132 | info->sp_offset += cris_get_quick_value (insn); |
| 1133 | } |
| 1134 | } |
| 1135 | else if (cris_get_mode (insn) == 0x0002 |
| 1136 | && cris_get_opcode (insn) == 0x000F |
| 1137 | && cris_get_size (insn) == 0x0003 |
| 1138 | && cris_get_operand1 (insn) == gdbarch_sp_regnum (gdbarch)) |
| 1139 | { |
| 1140 | /* movem r<regsave>,[sp] */ |
| 1141 | regsave = cris_get_operand2 (insn); |
| 1142 | } |
| 1143 | else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch) |
| 1144 | && ((insn & 0x0F00) >> 8) == 0x0001 |
| 1145 | && (cris_get_signed_offset (insn) < 0)) |
| 1146 | { |
| 1147 | /* Immediate byte offset addressing prefix word with sp as base |
| 1148 | register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val> |
| 1149 | is between 64 and 128. |
| 1150 | movem r<regsave>,[sp=sp-<val>] */ |
| 1151 | if (info) |
| 1152 | { |
| 1153 | info->sp_offset += -cris_get_signed_offset (insn); |
| 1154 | } |
| 1155 | insn_next = read_memory_unsigned_integer (pc, 2, byte_order); |
| 1156 | pc += 2; |
| 1157 | if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE |
| 1158 | && cris_get_opcode (insn_next) == 0x000F |
| 1159 | && cris_get_size (insn_next) == 0x0003 |
| 1160 | && cris_get_operand1 (insn_next) == gdbarch_sp_regnum |
| 1161 | (gdbarch)) |
| 1162 | { |
| 1163 | regsave = cris_get_operand2 (insn_next); |
| 1164 | } |
| 1165 | else |
| 1166 | { |
| 1167 | /* The prologue ended before the limit was reached. */ |
| 1168 | pc -= 4; |
| 1169 | break; |
| 1170 | } |
| 1171 | } |
| 1172 | else if (cris_get_mode (insn) == 0x0001 |
| 1173 | && cris_get_opcode (insn) == 0x0009 |
| 1174 | && cris_get_size (insn) == 0x0002) |
| 1175 | { |
| 1176 | /* move.d r<10..13>,r<0..15> */ |
| 1177 | source_register = cris_get_operand1 (insn); |
| 1178 | |
| 1179 | /* FIXME? In the glibc solibs, the prologue might contain something |
| 1180 | like (this example taken from relocate_doit): |
| 1181 | move.d $pc,$r0 |
| 1182 | sub.d 0xfffef426,$r0 |
| 1183 | which isn't covered by the source_register check below. Question |
| 1184 | is whether to add a check for this combo, or make better use of |
| 1185 | the limit variable instead. */ |
| 1186 | if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM) |
| 1187 | { |
| 1188 | /* The prologue ended before the limit was reached. */ |
| 1189 | pc -= 2; |
| 1190 | break; |
| 1191 | } |
| 1192 | } |
| 1193 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
| 1194 | /* The size is a fixed-size. */ |
| 1195 | && ((insn & 0x0F00) >> 8) == 0x0001 |
| 1196 | /* A negative offset. */ |
| 1197 | && (cris_get_signed_offset (insn) < 0)) |
| 1198 | { |
| 1199 | /* move.S rZ,[r8-U] (?) */ |
| 1200 | insn_next = read_memory_unsigned_integer (pc, 2, byte_order); |
| 1201 | pc += 2; |
| 1202 | regno = cris_get_operand2 (insn_next); |
| 1203 | if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch)) |
| 1204 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE |
| 1205 | && cris_get_opcode (insn_next) == 0x000F) |
| 1206 | { |
| 1207 | /* move.S rZ,[r8-U] */ |
| 1208 | continue; |
| 1209 | } |
| 1210 | else |
| 1211 | { |
| 1212 | /* The prologue ended before the limit was reached. */ |
| 1213 | pc -= 4; |
| 1214 | break; |
| 1215 | } |
| 1216 | } |
| 1217 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
| 1218 | /* The size is a fixed-size. */ |
| 1219 | && ((insn & 0x0F00) >> 8) == 0x0001 |
| 1220 | /* A positive offset. */ |
| 1221 | && (cris_get_signed_offset (insn) > 0)) |
| 1222 | { |
| 1223 | /* move.S [r8+U],rZ (?) */ |
| 1224 | insn_next = read_memory_unsigned_integer (pc, 2, byte_order); |
| 1225 | pc += 2; |
| 1226 | regno = cris_get_operand2 (insn_next); |
| 1227 | if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch)) |
| 1228 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE |
| 1229 | && cris_get_opcode (insn_next) == 0x0009 |
| 1230 | && cris_get_operand1 (insn_next) == regno) |
| 1231 | { |
| 1232 | /* move.S [r8+U],rZ */ |
| 1233 | continue; |
| 1234 | } |
| 1235 | else |
| 1236 | { |
| 1237 | /* The prologue ended before the limit was reached. */ |
| 1238 | pc -= 4; |
| 1239 | break; |
| 1240 | } |
| 1241 | } |
| 1242 | else |
| 1243 | { |
| 1244 | /* The prologue ended before the limit was reached. */ |
| 1245 | pc -= 2; |
| 1246 | break; |
| 1247 | } |
| 1248 | } |
| 1249 | |
| 1250 | /* We only want to know the end of the prologue when this_frame and info |
| 1251 | are NULL (called from cris_skip_prologue i.e.). */ |
| 1252 | if (this_frame == NULL && info == NULL) |
| 1253 | { |
| 1254 | return pc; |
| 1255 | } |
| 1256 | |
| 1257 | info->size = info->sp_offset; |
| 1258 | |
| 1259 | /* Compute the previous frame's stack pointer (which is also the |
| 1260 | frame's ID's stack address), and this frame's base pointer. */ |
| 1261 | if (info->uses_frame) |
| 1262 | { |
| 1263 | ULONGEST this_base; |
| 1264 | /* The SP was moved to the FP. This indicates that a new frame |
| 1265 | was created. Get THIS frame's FP value by unwinding it from |
| 1266 | the next frame. */ |
| 1267 | this_base = get_frame_register_unsigned (this_frame, CRIS_FP_REGNUM); |
| 1268 | info->base = this_base; |
| 1269 | info->saved_regs[CRIS_FP_REGNUM].addr = info->base; |
| 1270 | |
| 1271 | /* The FP points at the last saved register. Adjust the FP back |
| 1272 | to before the first saved register giving the SP. */ |
| 1273 | info->prev_sp = info->base + info->r8_offset; |
| 1274 | } |
| 1275 | else |
| 1276 | { |
| 1277 | ULONGEST this_base; |
| 1278 | /* Assume that the FP is this frame's SP but with that pushed |
| 1279 | stack space added back. */ |
| 1280 | this_base = get_frame_register_unsigned (this_frame, |
| 1281 | gdbarch_sp_regnum (gdbarch)); |
| 1282 | info->base = this_base; |
| 1283 | info->prev_sp = info->base + info->size; |
| 1284 | } |
| 1285 | |
| 1286 | /* Calculate the addresses for the saved registers on the stack. */ |
| 1287 | /* FIXME: The address calculation should really be done on the fly while |
| 1288 | we're analyzing the prologue (we only hold one regsave value as it is |
| 1289 | now). */ |
| 1290 | val = info->sp_offset; |
| 1291 | |
| 1292 | for (regno = regsave; regno >= 0; regno--) |
| 1293 | { |
| 1294 | info->saved_regs[regno].addr = info->base + info->r8_offset - val; |
| 1295 | val -= 4; |
| 1296 | } |
| 1297 | |
| 1298 | /* The previous frame's SP needed to be computed. Save the computed |
| 1299 | value. */ |
| 1300 | trad_frame_set_value (info->saved_regs, |
| 1301 | gdbarch_sp_regnum (gdbarch), info->prev_sp); |
| 1302 | |
| 1303 | if (!info->leaf_function) |
| 1304 | { |
| 1305 | /* SRP saved on the stack. But where? */ |
| 1306 | if (info->r8_offset == 0) |
| 1307 | { |
| 1308 | /* R8 not pushed yet. */ |
| 1309 | info->saved_regs[SRP_REGNUM].addr = info->base; |
| 1310 | } |
| 1311 | else |
| 1312 | { |
| 1313 | /* R8 pushed, but SP may or may not be moved to R8 yet. */ |
| 1314 | info->saved_regs[SRP_REGNUM].addr = info->base + 4; |
| 1315 | } |
| 1316 | } |
| 1317 | |
| 1318 | /* The PC is found in SRP (the actual register or located on the stack). */ |
| 1319 | info->saved_regs[gdbarch_pc_regnum (gdbarch)] |
| 1320 | = info->saved_regs[SRP_REGNUM]; |
| 1321 | |
| 1322 | return pc; |
| 1323 | } |
| 1324 | |
| 1325 | static CORE_ADDR |
| 1326 | crisv32_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame, |
| 1327 | struct cris_unwind_cache *info) |
| 1328 | { |
| 1329 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 1330 | ULONGEST this_base; |
| 1331 | |
| 1332 | /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not |
| 1333 | meant to be a full-fledged prologue scanner. It is only needed for |
| 1334 | the cases where we end up in code always lacking DWARF-2 CFI, notably: |
| 1335 | |
| 1336 | * PLT stubs (library calls) |
| 1337 | * call dummys |
| 1338 | * signal trampolines |
| 1339 | |
| 1340 | For those cases, it is assumed that there is no actual prologue; that |
| 1341 | the stack pointer is not adjusted, and (as a consequence) the return |
| 1342 | address is not pushed onto the stack. */ |
| 1343 | |
| 1344 | /* We only want to know the end of the prologue when this_frame and info |
| 1345 | are NULL (called from cris_skip_prologue i.e.). */ |
| 1346 | if (this_frame == NULL && info == NULL) |
| 1347 | { |
| 1348 | return pc; |
| 1349 | } |
| 1350 | |
| 1351 | /* The SP is assumed to be unaltered. */ |
| 1352 | this_base = get_frame_register_unsigned (this_frame, |
| 1353 | gdbarch_sp_regnum (gdbarch)); |
| 1354 | info->base = this_base; |
| 1355 | info->prev_sp = this_base; |
| 1356 | |
| 1357 | /* The PC is assumed to be found in SRP. */ |
| 1358 | info->saved_regs[gdbarch_pc_regnum (gdbarch)] |
| 1359 | = info->saved_regs[SRP_REGNUM]; |
| 1360 | |
| 1361 | return pc; |
| 1362 | } |
| 1363 | |
| 1364 | /* Advance pc beyond any function entry prologue instructions at pc |
| 1365 | to reach some "real" code. */ |
| 1366 | |
| 1367 | /* Given a PC value corresponding to the start of a function, return the PC |
| 1368 | of the first instruction after the function prologue. */ |
| 1369 | |
| 1370 | static CORE_ADDR |
| 1371 | cris_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 1372 | { |
| 1373 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1374 | CORE_ADDR func_addr, func_end; |
| 1375 | struct symtab_and_line sal; |
| 1376 | CORE_ADDR pc_after_prologue; |
| 1377 | |
| 1378 | /* If we have line debugging information, then the end of the prologue |
| 1379 | should the first assembly instruction of the first source line. */ |
| 1380 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
| 1381 | { |
| 1382 | sal = find_pc_line (func_addr, 0); |
| 1383 | if (sal.end > 0 && sal.end < func_end) |
| 1384 | return sal.end; |
| 1385 | } |
| 1386 | |
| 1387 | if (tdep->cris_version == 32) |
| 1388 | pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL); |
| 1389 | else |
| 1390 | pc_after_prologue = cris_scan_prologue (pc, NULL, NULL); |
| 1391 | |
| 1392 | return pc_after_prologue; |
| 1393 | } |
| 1394 | |
| 1395 | static CORE_ADDR |
| 1396 | cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 1397 | { |
| 1398 | ULONGEST pc; |
| 1399 | pc = frame_unwind_register_unsigned (next_frame, |
| 1400 | gdbarch_pc_regnum (gdbarch)); |
| 1401 | return pc; |
| 1402 | } |
| 1403 | |
| 1404 | static CORE_ADDR |
| 1405 | cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 1406 | { |
| 1407 | ULONGEST sp; |
| 1408 | sp = frame_unwind_register_unsigned (next_frame, |
| 1409 | gdbarch_sp_regnum (gdbarch)); |
| 1410 | return sp; |
| 1411 | } |
| 1412 | |
| 1413 | /* Use the program counter to determine the contents and size of a breakpoint |
| 1414 | instruction. It returns a pointer to a string of bytes that encode a |
| 1415 | breakpoint instruction, stores the length of the string to *lenptr, and |
| 1416 | adjusts pcptr (if necessary) to point to the actual memory location where |
| 1417 | the breakpoint should be inserted. */ |
| 1418 | |
| 1419 | static const unsigned char * |
| 1420 | cris_breakpoint_from_pc (struct gdbarch *gdbarch, |
| 1421 | CORE_ADDR *pcptr, int *lenptr) |
| 1422 | { |
| 1423 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1424 | static unsigned char break8_insn[] = {0x38, 0xe9}; |
| 1425 | static unsigned char break15_insn[] = {0x3f, 0xe9}; |
| 1426 | *lenptr = 2; |
| 1427 | |
| 1428 | if (tdep->cris_mode == cris_mode_guru) |
| 1429 | return break15_insn; |
| 1430 | else |
| 1431 | return break8_insn; |
| 1432 | } |
| 1433 | |
| 1434 | /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version, |
| 1435 | 0 otherwise. */ |
| 1436 | |
| 1437 | static int |
| 1438 | cris_spec_reg_applicable (struct gdbarch *gdbarch, |
| 1439 | struct cris_spec_reg spec_reg) |
| 1440 | { |
| 1441 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1442 | int version = tdep->cris_version; |
| 1443 | |
| 1444 | switch (spec_reg.applicable_version) |
| 1445 | { |
| 1446 | case cris_ver_version_all: |
| 1447 | return 1; |
| 1448 | case cris_ver_warning: |
| 1449 | /* Indeterminate/obsolete. */ |
| 1450 | return 0; |
| 1451 | case cris_ver_v0_3: |
| 1452 | return (version >= 0 && version <= 3); |
| 1453 | case cris_ver_v3p: |
| 1454 | return (version >= 3); |
| 1455 | case cris_ver_v8: |
| 1456 | return (version == 8 || version == 9); |
| 1457 | case cris_ver_v8p: |
| 1458 | return (version >= 8); |
| 1459 | case cris_ver_v0_10: |
| 1460 | return (version >= 0 && version <= 10); |
| 1461 | case cris_ver_v3_10: |
| 1462 | return (version >= 3 && version <= 10); |
| 1463 | case cris_ver_v8_10: |
| 1464 | return (version >= 8 && version <= 10); |
| 1465 | case cris_ver_v10: |
| 1466 | return (version == 10); |
| 1467 | case cris_ver_v10p: |
| 1468 | return (version >= 10); |
| 1469 | case cris_ver_v32p: |
| 1470 | return (version >= 32); |
| 1471 | default: |
| 1472 | /* Invalid cris version. */ |
| 1473 | return 0; |
| 1474 | } |
| 1475 | } |
| 1476 | |
| 1477 | /* Returns the register size in unit byte. Returns 0 for an unimplemented |
| 1478 | register, -1 for an invalid register. */ |
| 1479 | |
| 1480 | static int |
| 1481 | cris_register_size (struct gdbarch *gdbarch, int regno) |
| 1482 | { |
| 1483 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1484 | int i; |
| 1485 | int spec_regno; |
| 1486 | |
| 1487 | if (regno >= 0 && regno < NUM_GENREGS) |
| 1488 | { |
| 1489 | /* General registers (R0 - R15) are 32 bits. */ |
| 1490 | return 4; |
| 1491 | } |
| 1492 | else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS)) |
| 1493 | { |
| 1494 | /* Special register (R16 - R31). cris_spec_regs is zero-based. |
| 1495 | Adjust regno accordingly. */ |
| 1496 | spec_regno = regno - NUM_GENREGS; |
| 1497 | |
| 1498 | for (i = 0; cris_spec_regs[i].name != NULL; i++) |
| 1499 | { |
| 1500 | if (cris_spec_regs[i].number == spec_regno |
| 1501 | && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i])) |
| 1502 | /* Go with the first applicable register. */ |
| 1503 | return cris_spec_regs[i].reg_size; |
| 1504 | } |
| 1505 | /* Special register not applicable to this CRIS version. */ |
| 1506 | return 0; |
| 1507 | } |
| 1508 | else if (regno >= gdbarch_pc_regnum (gdbarch) |
| 1509 | && regno < gdbarch_num_regs (gdbarch)) |
| 1510 | { |
| 1511 | /* This will apply to CRISv32 only where there are additional registers |
| 1512 | after the special registers (pseudo PC and support registers). */ |
| 1513 | return 4; |
| 1514 | } |
| 1515 | |
| 1516 | |
| 1517 | return -1; |
| 1518 | } |
| 1519 | |
| 1520 | /* Nonzero if regno should not be fetched from the target. This is the case |
| 1521 | for unimplemented (size 0) and non-existant registers. */ |
| 1522 | |
| 1523 | static int |
| 1524 | cris_cannot_fetch_register (struct gdbarch *gdbarch, int regno) |
| 1525 | { |
| 1526 | return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
| 1527 | || (cris_register_size (gdbarch, regno) == 0)); |
| 1528 | } |
| 1529 | |
| 1530 | /* Nonzero if regno should not be written to the target, for various |
| 1531 | reasons. */ |
| 1532 | |
| 1533 | static int |
| 1534 | cris_cannot_store_register (struct gdbarch *gdbarch, int regno) |
| 1535 | { |
| 1536 | /* There are three kinds of registers we refuse to write to. |
| 1537 | 1. Those that not implemented. |
| 1538 | 2. Those that are read-only (depends on the processor mode). |
| 1539 | 3. Those registers to which a write has no effect. */ |
| 1540 | |
| 1541 | if (regno < 0 |
| 1542 | || regno >= gdbarch_num_regs (gdbarch) |
| 1543 | || cris_register_size (gdbarch, regno) == 0) |
| 1544 | /* Not implemented. */ |
| 1545 | return 1; |
| 1546 | |
| 1547 | else if (regno == VR_REGNUM) |
| 1548 | /* Read-only. */ |
| 1549 | return 1; |
| 1550 | |
| 1551 | else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM) |
| 1552 | /* Writing has no effect. */ |
| 1553 | return 1; |
| 1554 | |
| 1555 | /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug |
| 1556 | agent decide whether they are writable. */ |
| 1557 | |
| 1558 | return 0; |
| 1559 | } |
| 1560 | |
| 1561 | /* Nonzero if regno should not be fetched from the target. This is the case |
| 1562 | for unimplemented (size 0) and non-existant registers. */ |
| 1563 | |
| 1564 | static int |
| 1565 | crisv32_cannot_fetch_register (struct gdbarch *gdbarch, int regno) |
| 1566 | { |
| 1567 | return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
| 1568 | || (cris_register_size (gdbarch, regno) == 0)); |
| 1569 | } |
| 1570 | |
| 1571 | /* Nonzero if regno should not be written to the target, for various |
| 1572 | reasons. */ |
| 1573 | |
| 1574 | static int |
| 1575 | crisv32_cannot_store_register (struct gdbarch *gdbarch, int regno) |
| 1576 | { |
| 1577 | /* There are three kinds of registers we refuse to write to. |
| 1578 | 1. Those that not implemented. |
| 1579 | 2. Those that are read-only (depends on the processor mode). |
| 1580 | 3. Those registers to which a write has no effect. */ |
| 1581 | |
| 1582 | if (regno < 0 |
| 1583 | || regno >= gdbarch_num_regs (gdbarch) |
| 1584 | || cris_register_size (gdbarch, regno) == 0) |
| 1585 | /* Not implemented. */ |
| 1586 | return 1; |
| 1587 | |
| 1588 | else if (regno == VR_REGNUM) |
| 1589 | /* Read-only. */ |
| 1590 | return 1; |
| 1591 | |
| 1592 | else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM) |
| 1593 | /* Writing has no effect. */ |
| 1594 | return 1; |
| 1595 | |
| 1596 | /* Many special registers are read-only in user mode. Let the debug |
| 1597 | agent decide whether they are writable. */ |
| 1598 | |
| 1599 | return 0; |
| 1600 | } |
| 1601 | |
| 1602 | /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type |
| 1603 | of data in register regno. */ |
| 1604 | |
| 1605 | static struct type * |
| 1606 | cris_register_type (struct gdbarch *gdbarch, int regno) |
| 1607 | { |
| 1608 | if (regno == gdbarch_pc_regnum (gdbarch)) |
| 1609 | return builtin_type (gdbarch)->builtin_func_ptr; |
| 1610 | else if (regno == gdbarch_sp_regnum (gdbarch) |
| 1611 | || regno == CRIS_FP_REGNUM) |
| 1612 | return builtin_type (gdbarch)->builtin_data_ptr; |
| 1613 | else if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch)) |
| 1614 | || (regno >= MOF_REGNUM && regno <= USP_REGNUM)) |
| 1615 | /* Note: R8 taken care of previous clause. */ |
| 1616 | return builtin_type (gdbarch)->builtin_uint32; |
| 1617 | else if (regno >= P4_REGNUM && regno <= CCR_REGNUM) |
| 1618 | return builtin_type (gdbarch)->builtin_uint16; |
| 1619 | else if (regno >= P0_REGNUM && regno <= VR_REGNUM) |
| 1620 | return builtin_type (gdbarch)->builtin_uint8; |
| 1621 | else |
| 1622 | /* Invalid (unimplemented) register. */ |
| 1623 | return builtin_type (gdbarch)->builtin_int0; |
| 1624 | } |
| 1625 | |
| 1626 | static struct type * |
| 1627 | crisv32_register_type (struct gdbarch *gdbarch, int regno) |
| 1628 | { |
| 1629 | if (regno == gdbarch_pc_regnum (gdbarch)) |
| 1630 | return builtin_type (gdbarch)->builtin_func_ptr; |
| 1631 | else if (regno == gdbarch_sp_regnum (gdbarch) |
| 1632 | || regno == CRIS_FP_REGNUM) |
| 1633 | return builtin_type (gdbarch)->builtin_data_ptr; |
| 1634 | else if ((regno >= 0 && regno <= ACR_REGNUM) |
| 1635 | || (regno >= EXS_REGNUM && regno <= SPC_REGNUM) |
| 1636 | || (regno == PID_REGNUM) |
| 1637 | || (regno >= S0_REGNUM && regno <= S15_REGNUM)) |
| 1638 | /* Note: R8 and SP taken care of by previous clause. */ |
| 1639 | return builtin_type (gdbarch)->builtin_uint32; |
| 1640 | else if (regno == WZ_REGNUM) |
| 1641 | return builtin_type (gdbarch)->builtin_uint16; |
| 1642 | else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM) |
| 1643 | return builtin_type (gdbarch)->builtin_uint8; |
| 1644 | else |
| 1645 | { |
| 1646 | /* Invalid (unimplemented) register. Should not happen as there are |
| 1647 | no unimplemented CRISv32 registers. */ |
| 1648 | warning (_("crisv32_register_type: unknown regno %d"), regno); |
| 1649 | return builtin_type (gdbarch)->builtin_int0; |
| 1650 | } |
| 1651 | } |
| 1652 | |
| 1653 | /* Stores a function return value of type type, where valbuf is the address |
| 1654 | of the value to be stored. */ |
| 1655 | |
| 1656 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ |
| 1657 | |
| 1658 | static void |
| 1659 | cris_store_return_value (struct type *type, struct regcache *regcache, |
| 1660 | const void *valbuf) |
| 1661 | { |
| 1662 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 1663 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1664 | ULONGEST val; |
| 1665 | int len = TYPE_LENGTH (type); |
| 1666 | |
| 1667 | if (len <= 4) |
| 1668 | { |
| 1669 | /* Put the return value in R10. */ |
| 1670 | val = extract_unsigned_integer (valbuf, len, byte_order); |
| 1671 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); |
| 1672 | } |
| 1673 | else if (len <= 8) |
| 1674 | { |
| 1675 | /* Put the return value in R10 and R11. */ |
| 1676 | val = extract_unsigned_integer (valbuf, 4, byte_order); |
| 1677 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); |
| 1678 | val = extract_unsigned_integer ((char *)valbuf + 4, len - 4, byte_order); |
| 1679 | regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val); |
| 1680 | } |
| 1681 | else |
| 1682 | error (_("cris_store_return_value: type length too large.")); |
| 1683 | } |
| 1684 | |
| 1685 | /* Return the name of register regno as a string. Return NULL for an |
| 1686 | invalid or unimplemented register. */ |
| 1687 | |
| 1688 | static const char * |
| 1689 | cris_special_register_name (struct gdbarch *gdbarch, int regno) |
| 1690 | { |
| 1691 | int spec_regno; |
| 1692 | int i; |
| 1693 | |
| 1694 | /* Special register (R16 - R31). cris_spec_regs is zero-based. |
| 1695 | Adjust regno accordingly. */ |
| 1696 | spec_regno = regno - NUM_GENREGS; |
| 1697 | |
| 1698 | /* Assume nothing about the layout of the cris_spec_regs struct |
| 1699 | when searching. */ |
| 1700 | for (i = 0; cris_spec_regs[i].name != NULL; i++) |
| 1701 | { |
| 1702 | if (cris_spec_regs[i].number == spec_regno |
| 1703 | && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i])) |
| 1704 | /* Go with the first applicable register. */ |
| 1705 | return cris_spec_regs[i].name; |
| 1706 | } |
| 1707 | /* Special register not applicable to this CRIS version. */ |
| 1708 | return NULL; |
| 1709 | } |
| 1710 | |
| 1711 | static const char * |
| 1712 | cris_register_name (struct gdbarch *gdbarch, int regno) |
| 1713 | { |
| 1714 | static char *cris_genreg_names[] = |
| 1715 | { "r0", "r1", "r2", "r3", \ |
| 1716 | "r4", "r5", "r6", "r7", \ |
| 1717 | "r8", "r9", "r10", "r11", \ |
| 1718 | "r12", "r13", "sp", "pc" }; |
| 1719 | |
| 1720 | if (regno >= 0 && regno < NUM_GENREGS) |
| 1721 | { |
| 1722 | /* General register. */ |
| 1723 | return cris_genreg_names[regno]; |
| 1724 | } |
| 1725 | else if (regno >= NUM_GENREGS && regno < gdbarch_num_regs (gdbarch)) |
| 1726 | { |
| 1727 | return cris_special_register_name (gdbarch, regno); |
| 1728 | } |
| 1729 | else |
| 1730 | { |
| 1731 | /* Invalid register. */ |
| 1732 | return NULL; |
| 1733 | } |
| 1734 | } |
| 1735 | |
| 1736 | static const char * |
| 1737 | crisv32_register_name (struct gdbarch *gdbarch, int regno) |
| 1738 | { |
| 1739 | static char *crisv32_genreg_names[] = |
| 1740 | { "r0", "r1", "r2", "r3", \ |
| 1741 | "r4", "r5", "r6", "r7", \ |
| 1742 | "r8", "r9", "r10", "r11", \ |
| 1743 | "r12", "r13", "sp", "acr" |
| 1744 | }; |
| 1745 | |
| 1746 | static char *crisv32_sreg_names[] = |
| 1747 | { "s0", "s1", "s2", "s3", \ |
| 1748 | "s4", "s5", "s6", "s7", \ |
| 1749 | "s8", "s9", "s10", "s11", \ |
| 1750 | "s12", "s13", "s14", "s15" |
| 1751 | }; |
| 1752 | |
| 1753 | if (regno >= 0 && regno < NUM_GENREGS) |
| 1754 | { |
| 1755 | /* General register. */ |
| 1756 | return crisv32_genreg_names[regno]; |
| 1757 | } |
| 1758 | else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS)) |
| 1759 | { |
| 1760 | return cris_special_register_name (gdbarch, regno); |
| 1761 | } |
| 1762 | else if (regno == gdbarch_pc_regnum (gdbarch)) |
| 1763 | { |
| 1764 | return "pc"; |
| 1765 | } |
| 1766 | else if (regno >= S0_REGNUM && regno <= S15_REGNUM) |
| 1767 | { |
| 1768 | return crisv32_sreg_names[regno - S0_REGNUM]; |
| 1769 | } |
| 1770 | else |
| 1771 | { |
| 1772 | /* Invalid register. */ |
| 1773 | return NULL; |
| 1774 | } |
| 1775 | } |
| 1776 | |
| 1777 | /* Convert DWARF register number REG to the appropriate register |
| 1778 | number used by GDB. */ |
| 1779 | |
| 1780 | static int |
| 1781 | cris_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
| 1782 | { |
| 1783 | /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register |
| 1784 | numbering, MOF is 18). |
| 1785 | Adapted from gcc/config/cris/cris.h. */ |
| 1786 | static int cris_dwarf_regmap[] = { |
| 1787 | 0, 1, 2, 3, |
| 1788 | 4, 5, 6, 7, |
| 1789 | 8, 9, 10, 11, |
| 1790 | 12, 13, 14, 15, |
| 1791 | 27, -1, -1, -1, |
| 1792 | -1, -1, -1, 23, |
| 1793 | -1, -1, -1, 27, |
| 1794 | -1, -1, -1, -1 |
| 1795 | }; |
| 1796 | int regnum = -1; |
| 1797 | |
| 1798 | if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap)) |
| 1799 | regnum = cris_dwarf_regmap[reg]; |
| 1800 | |
| 1801 | if (regnum == -1) |
| 1802 | warning (_("Unmapped DWARF Register #%d encountered."), reg); |
| 1803 | |
| 1804 | return regnum; |
| 1805 | } |
| 1806 | |
| 1807 | /* DWARF-2 frame support. */ |
| 1808 | |
| 1809 | static void |
| 1810 | cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, |
| 1811 | struct dwarf2_frame_state_reg *reg, |
| 1812 | struct frame_info *this_frame) |
| 1813 | { |
| 1814 | /* The return address column. */ |
| 1815 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
| 1816 | reg->how = DWARF2_FRAME_REG_RA; |
| 1817 | |
| 1818 | /* The call frame address. */ |
| 1819 | else if (regnum == gdbarch_sp_regnum (gdbarch)) |
| 1820 | reg->how = DWARF2_FRAME_REG_CFA; |
| 1821 | } |
| 1822 | |
| 1823 | /* Extract from an array regbuf containing the raw register state a function |
| 1824 | return value of type type, and copy that, in virtual format, into |
| 1825 | valbuf. */ |
| 1826 | |
| 1827 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ |
| 1828 | |
| 1829 | static void |
| 1830 | cris_extract_return_value (struct type *type, struct regcache *regcache, |
| 1831 | void *valbuf) |
| 1832 | { |
| 1833 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 1834 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1835 | ULONGEST val; |
| 1836 | int len = TYPE_LENGTH (type); |
| 1837 | |
| 1838 | if (len <= 4) |
| 1839 | { |
| 1840 | /* Get the return value from R10. */ |
| 1841 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); |
| 1842 | store_unsigned_integer (valbuf, len, byte_order, val); |
| 1843 | } |
| 1844 | else if (len <= 8) |
| 1845 | { |
| 1846 | /* Get the return value from R10 and R11. */ |
| 1847 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); |
| 1848 | store_unsigned_integer (valbuf, 4, byte_order, val); |
| 1849 | regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val); |
| 1850 | store_unsigned_integer ((char *)valbuf + 4, len - 4, byte_order, val); |
| 1851 | } |
| 1852 | else |
| 1853 | error (_("cris_extract_return_value: type length too large")); |
| 1854 | } |
| 1855 | |
| 1856 | /* Handle the CRIS return value convention. */ |
| 1857 | |
| 1858 | static enum return_value_convention |
| 1859 | cris_return_value (struct gdbarch *gdbarch, struct value *function, |
| 1860 | struct type *type, struct regcache *regcache, |
| 1861 | gdb_byte *readbuf, const gdb_byte *writebuf) |
| 1862 | { |
| 1863 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
| 1864 | || TYPE_CODE (type) == TYPE_CODE_UNION |
| 1865 | || TYPE_LENGTH (type) > 8) |
| 1866 | /* Structs, unions, and anything larger than 8 bytes (2 registers) |
| 1867 | goes on the stack. */ |
| 1868 | return RETURN_VALUE_STRUCT_CONVENTION; |
| 1869 | |
| 1870 | if (readbuf) |
| 1871 | cris_extract_return_value (type, regcache, readbuf); |
| 1872 | if (writebuf) |
| 1873 | cris_store_return_value (type, regcache, writebuf); |
| 1874 | |
| 1875 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 1876 | } |
| 1877 | |
| 1878 | /* Calculates a value that measures how good inst_args constraints an |
| 1879 | instruction. It stems from cris_constraint, found in cris-dis.c. */ |
| 1880 | |
| 1881 | static int |
| 1882 | constraint (unsigned int insn, const signed char *inst_args, |
| 1883 | inst_env_type *inst_env) |
| 1884 | { |
| 1885 | int retval = 0; |
| 1886 | int tmp, i; |
| 1887 | |
| 1888 | const char *s = inst_args; |
| 1889 | |
| 1890 | for (; *s; s++) |
| 1891 | switch (*s) |
| 1892 | { |
| 1893 | case 'm': |
| 1894 | if ((insn & 0x30) == 0x30) |
| 1895 | return -1; |
| 1896 | break; |
| 1897 | |
| 1898 | case 'S': |
| 1899 | /* A prefix operand. */ |
| 1900 | if (inst_env->prefix_found) |
| 1901 | break; |
| 1902 | else |
| 1903 | return -1; |
| 1904 | |
| 1905 | case 'B': |
| 1906 | /* A "push" prefix. (This check was REMOVED by san 970921.) Check for |
| 1907 | valid "push" size. In case of special register, it may be != 4. */ |
| 1908 | if (inst_env->prefix_found) |
| 1909 | break; |
| 1910 | else |
| 1911 | return -1; |
| 1912 | |
| 1913 | case 'D': |
| 1914 | retval = (((insn >> 0xC) & 0xF) == (insn & 0xF)); |
| 1915 | if (!retval) |
| 1916 | return -1; |
| 1917 | else |
| 1918 | retval += 4; |
| 1919 | break; |
| 1920 | |
| 1921 | case 'P': |
| 1922 | tmp = (insn >> 0xC) & 0xF; |
| 1923 | |
| 1924 | for (i = 0; cris_spec_regs[i].name != NULL; i++) |
| 1925 | { |
| 1926 | /* Since we match four bits, we will give a value of |
| 1927 | 4 - 1 = 3 in a match. If there is a corresponding |
| 1928 | exact match of a special register in another pattern, it |
| 1929 | will get a value of 4, which will be higher. This should |
| 1930 | be correct in that an exact pattern would match better that |
| 1931 | a general pattern. |
| 1932 | Note that there is a reason for not returning zero; the |
| 1933 | pattern for "clear" is partly matched in the bit-pattern |
| 1934 | (the two lower bits must be zero), while the bit-pattern |
| 1935 | for a move from a special register is matched in the |
| 1936 | register constraint. |
| 1937 | This also means we will will have a race condition if |
| 1938 | there is a partly match in three bits in the bit pattern. */ |
| 1939 | if (tmp == cris_spec_regs[i].number) |
| 1940 | { |
| 1941 | retval += 3; |
| 1942 | break; |
| 1943 | } |
| 1944 | } |
| 1945 | |
| 1946 | if (cris_spec_regs[i].name == NULL) |
| 1947 | return -1; |
| 1948 | break; |
| 1949 | } |
| 1950 | return retval; |
| 1951 | } |
| 1952 | |
| 1953 | /* Returns the number of bits set in the variable value. */ |
| 1954 | |
| 1955 | static int |
| 1956 | number_of_bits (unsigned int value) |
| 1957 | { |
| 1958 | int number_of_bits = 0; |
| 1959 | |
| 1960 | while (value != 0) |
| 1961 | { |
| 1962 | number_of_bits += 1; |
| 1963 | value &= (value - 1); |
| 1964 | } |
| 1965 | return number_of_bits; |
| 1966 | } |
| 1967 | |
| 1968 | /* Finds the address that should contain the single step breakpoint(s). |
| 1969 | It stems from code in cris-dis.c. */ |
| 1970 | |
| 1971 | static int |
| 1972 | find_cris_op (unsigned short insn, inst_env_type *inst_env) |
| 1973 | { |
| 1974 | int i; |
| 1975 | int max_level_of_match = -1; |
| 1976 | int max_matched = -1; |
| 1977 | int level_of_match; |
| 1978 | |
| 1979 | for (i = 0; cris_opcodes[i].name != NULL; i++) |
| 1980 | { |
| 1981 | if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match) |
| 1982 | && ((cris_opcodes[i].lose & insn) == 0) |
| 1983 | /* Only CRISv10 instructions, please. */ |
| 1984 | && (cris_opcodes[i].applicable_version != cris_ver_v32p)) |
| 1985 | { |
| 1986 | level_of_match = constraint (insn, cris_opcodes[i].args, inst_env); |
| 1987 | if (level_of_match >= 0) |
| 1988 | { |
| 1989 | level_of_match += |
| 1990 | number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose); |
| 1991 | if (level_of_match > max_level_of_match) |
| 1992 | { |
| 1993 | max_matched = i; |
| 1994 | max_level_of_match = level_of_match; |
| 1995 | if (level_of_match == 16) |
| 1996 | { |
| 1997 | /* All bits matched, cannot find better. */ |
| 1998 | break; |
| 1999 | } |
| 2000 | } |
| 2001 | } |
| 2002 | } |
| 2003 | } |
| 2004 | return max_matched; |
| 2005 | } |
| 2006 | |
| 2007 | /* Attempts to find single-step breakpoints. Returns -1 on failure which is |
| 2008 | actually an internal error. */ |
| 2009 | |
| 2010 | static int |
| 2011 | find_step_target (struct frame_info *frame, inst_env_type *inst_env) |
| 2012 | { |
| 2013 | int i; |
| 2014 | int offset; |
| 2015 | unsigned short insn; |
| 2016 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 2017 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2018 | |
| 2019 | /* Create a local register image and set the initial state. */ |
| 2020 | for (i = 0; i < NUM_GENREGS; i++) |
| 2021 | { |
| 2022 | inst_env->reg[i] = |
| 2023 | (unsigned long) get_frame_register_unsigned (frame, i); |
| 2024 | } |
| 2025 | offset = NUM_GENREGS; |
| 2026 | for (i = 0; i < NUM_SPECREGS; i++) |
| 2027 | { |
| 2028 | inst_env->preg[i] = |
| 2029 | (unsigned long) get_frame_register_unsigned (frame, offset + i); |
| 2030 | } |
| 2031 | inst_env->branch_found = 0; |
| 2032 | inst_env->slot_needed = 0; |
| 2033 | inst_env->delay_slot_pc_active = 0; |
| 2034 | inst_env->prefix_found = 0; |
| 2035 | inst_env->invalid = 0; |
| 2036 | inst_env->xflag_found = 0; |
| 2037 | inst_env->disable_interrupt = 0; |
| 2038 | inst_env->byte_order = byte_order; |
| 2039 | |
| 2040 | /* Look for a step target. */ |
| 2041 | do |
| 2042 | { |
| 2043 | /* Read an instruction from the client. */ |
| 2044 | insn = read_memory_unsigned_integer |
| 2045 | (inst_env->reg[gdbarch_pc_regnum (gdbarch)], 2, byte_order); |
| 2046 | |
| 2047 | /* If the instruction is not in a delay slot the new content of the |
| 2048 | PC is [PC] + 2. If the instruction is in a delay slot it is not |
| 2049 | that simple. Since a instruction in a delay slot cannot change |
| 2050 | the content of the PC, it does not matter what value PC will have. |
| 2051 | Just make sure it is a valid instruction. */ |
| 2052 | if (!inst_env->delay_slot_pc_active) |
| 2053 | { |
| 2054 | inst_env->reg[gdbarch_pc_regnum (gdbarch)] += 2; |
| 2055 | } |
| 2056 | else |
| 2057 | { |
| 2058 | inst_env->delay_slot_pc_active = 0; |
| 2059 | inst_env->reg[gdbarch_pc_regnum (gdbarch)] |
| 2060 | = inst_env->delay_slot_pc; |
| 2061 | } |
| 2062 | /* Analyse the present instruction. */ |
| 2063 | i = find_cris_op (insn, inst_env); |
| 2064 | if (i == -1) |
| 2065 | { |
| 2066 | inst_env->invalid = 1; |
| 2067 | } |
| 2068 | else |
| 2069 | { |
| 2070 | cris_gdb_func (gdbarch, cris_opcodes[i].op, insn, inst_env); |
| 2071 | } |
| 2072 | } while (!inst_env->invalid |
| 2073 | && (inst_env->prefix_found || inst_env->xflag_found |
| 2074 | || inst_env->slot_needed)); |
| 2075 | return i; |
| 2076 | } |
| 2077 | |
| 2078 | /* There is no hardware single-step support. The function find_step_target |
| 2079 | digs through the opcodes in order to find all possible targets. |
| 2080 | Either one ordinary target or two targets for branches may be found. */ |
| 2081 | |
| 2082 | static int |
| 2083 | cris_software_single_step (struct frame_info *frame) |
| 2084 | { |
| 2085 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 2086 | struct address_space *aspace = get_frame_address_space (frame); |
| 2087 | inst_env_type inst_env; |
| 2088 | |
| 2089 | /* Analyse the present instruction environment and insert |
| 2090 | breakpoints. */ |
| 2091 | int status = find_step_target (frame, &inst_env); |
| 2092 | if (status == -1) |
| 2093 | { |
| 2094 | /* Could not find a target. Things are likely to go downhill |
| 2095 | from here. */ |
| 2096 | warning (_("CRIS software single step could not find a step target.")); |
| 2097 | } |
| 2098 | else |
| 2099 | { |
| 2100 | /* Insert at most two breakpoints. One for the next PC content |
| 2101 | and possibly another one for a branch, jump, etc. */ |
| 2102 | CORE_ADDR next_pc |
| 2103 | = (CORE_ADDR) inst_env.reg[gdbarch_pc_regnum (gdbarch)]; |
| 2104 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); |
| 2105 | if (inst_env.branch_found |
| 2106 | && (CORE_ADDR) inst_env.branch_break_address != next_pc) |
| 2107 | { |
| 2108 | CORE_ADDR branch_target_address |
| 2109 | = (CORE_ADDR) inst_env.branch_break_address; |
| 2110 | insert_single_step_breakpoint (gdbarch, |
| 2111 | aspace, branch_target_address); |
| 2112 | } |
| 2113 | } |
| 2114 | |
| 2115 | return 1; |
| 2116 | } |
| 2117 | |
| 2118 | /* Calculates the prefix value for quick offset addressing mode. */ |
| 2119 | |
| 2120 | static void |
| 2121 | quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
| 2122 | { |
| 2123 | /* It's invalid to be in a delay slot. You can't have a prefix to this |
| 2124 | instruction (not 100% sure). */ |
| 2125 | if (inst_env->slot_needed || inst_env->prefix_found) |
| 2126 | { |
| 2127 | inst_env->invalid = 1; |
| 2128 | return; |
| 2129 | } |
| 2130 | |
| 2131 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; |
| 2132 | inst_env->prefix_value += cris_get_bdap_quick_offset (inst); |
| 2133 | |
| 2134 | /* A prefix doesn't change the xflag_found. But the rest of the flags |
| 2135 | need updating. */ |
| 2136 | inst_env->slot_needed = 0; |
| 2137 | inst_env->prefix_found = 1; |
| 2138 | } |
| 2139 | |
| 2140 | /* Updates the autoincrement register. The size of the increment is derived |
| 2141 | from the size of the operation. The PC is always kept aligned on even |
| 2142 | word addresses. */ |
| 2143 | |
| 2144 | static void |
| 2145 | process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env) |
| 2146 | { |
| 2147 | if (size == INST_BYTE_SIZE) |
| 2148 | { |
| 2149 | inst_env->reg[cris_get_operand1 (inst)] += 1; |
| 2150 | |
| 2151 | /* The PC must be word aligned, so increase the PC with one |
| 2152 | word even if the size is byte. */ |
| 2153 | if (cris_get_operand1 (inst) == REG_PC) |
| 2154 | { |
| 2155 | inst_env->reg[REG_PC] += 1; |
| 2156 | } |
| 2157 | } |
| 2158 | else if (size == INST_WORD_SIZE) |
| 2159 | { |
| 2160 | inst_env->reg[cris_get_operand1 (inst)] += 2; |
| 2161 | } |
| 2162 | else if (size == INST_DWORD_SIZE) |
| 2163 | { |
| 2164 | inst_env->reg[cris_get_operand1 (inst)] += 4; |
| 2165 | } |
| 2166 | else |
| 2167 | { |
| 2168 | /* Invalid size. */ |
| 2169 | inst_env->invalid = 1; |
| 2170 | } |
| 2171 | } |
| 2172 | |
| 2173 | /* Just a forward declaration. */ |
| 2174 | |
| 2175 | static unsigned long get_data_from_address (unsigned short *inst, |
| 2176 | CORE_ADDR address, |
| 2177 | enum bfd_endian byte_order); |
| 2178 | |
| 2179 | /* Calculates the prefix value for the general case of offset addressing |
| 2180 | mode. */ |
| 2181 | |
| 2182 | static void |
| 2183 | bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
| 2184 | { |
| 2185 | /* It's invalid to be in a delay slot. */ |
| 2186 | if (inst_env->slot_needed || inst_env->prefix_found) |
| 2187 | { |
| 2188 | inst_env->invalid = 1; |
| 2189 | return; |
| 2190 | } |
| 2191 | |
| 2192 | /* The calculation of prefix_value used to be after process_autoincrement, |
| 2193 | but that fails for an instruction such as jsr [$r0+12] which is encoded |
| 2194 | as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it |
| 2195 | mustn't be incremented until we have read it and what it points at. */ |
| 2196 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; |
| 2197 | |
| 2198 | /* The offset is an indirection of the contents of the operand1 register. */ |
| 2199 | inst_env->prefix_value += |
| 2200 | get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)], |
| 2201 | inst_env->byte_order); |
| 2202 | |
| 2203 | if (cris_get_mode (inst) == AUTOINC_MODE) |
| 2204 | { |
| 2205 | process_autoincrement (cris_get_size (inst), inst, inst_env); |
| 2206 | } |
| 2207 | |
| 2208 | /* A prefix doesn't change the xflag_found. But the rest of the flags |
| 2209 | need updating. */ |
| 2210 | inst_env->slot_needed = 0; |
| 2211 | inst_env->prefix_found = 1; |
| 2212 | } |
| 2213 | |
| 2214 | /* Calculates the prefix value for the index addressing mode. */ |
| 2215 | |
| 2216 | static void |
| 2217 | biap_prefix (unsigned short inst, inst_env_type *inst_env) |
| 2218 | { |
| 2219 | /* It's invalid to be in a delay slot. I can't see that it's possible to |
| 2220 | have a prefix to this instruction. So I will treat this as invalid. */ |
| 2221 | if (inst_env->slot_needed || inst_env->prefix_found) |
| 2222 | { |
| 2223 | inst_env->invalid = 1; |
| 2224 | return; |
| 2225 | } |
| 2226 | |
| 2227 | inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)]; |
| 2228 | |
| 2229 | /* The offset is the operand2 value shifted the size of the instruction |
| 2230 | to the left. */ |
| 2231 | inst_env->prefix_value += |
| 2232 | inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst); |
| 2233 | |
| 2234 | /* If the PC is operand1 (base) the address used is the address after |
| 2235 | the main instruction, i.e. address + 2 (the PC is already compensated |
| 2236 | for the prefix operation). */ |
| 2237 | if (cris_get_operand1 (inst) == REG_PC) |
| 2238 | { |
| 2239 | inst_env->prefix_value += 2; |
| 2240 | } |
| 2241 | |
| 2242 | /* A prefix doesn't change the xflag_found. But the rest of the flags |
| 2243 | need updating. */ |
| 2244 | inst_env->slot_needed = 0; |
| 2245 | inst_env->xflag_found = 0; |
| 2246 | inst_env->prefix_found = 1; |
| 2247 | } |
| 2248 | |
| 2249 | /* Calculates the prefix value for the double indirect addressing mode. */ |
| 2250 | |
| 2251 | static void |
| 2252 | dip_prefix (unsigned short inst, inst_env_type *inst_env) |
| 2253 | { |
| 2254 | |
| 2255 | CORE_ADDR address; |
| 2256 | |
| 2257 | /* It's invalid to be in a delay slot. */ |
| 2258 | if (inst_env->slot_needed || inst_env->prefix_found) |
| 2259 | { |
| 2260 | inst_env->invalid = 1; |
| 2261 | return; |
| 2262 | } |
| 2263 | |
| 2264 | /* The prefix value is one dereference of the contents of the operand1 |
| 2265 | register. */ |
| 2266 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; |
| 2267 | inst_env->prefix_value |
| 2268 | = read_memory_unsigned_integer (address, 4, inst_env->byte_order); |
| 2269 | |
| 2270 | /* Check if the mode is autoincrement. */ |
| 2271 | if (cris_get_mode (inst) == AUTOINC_MODE) |
| 2272 | { |
| 2273 | inst_env->reg[cris_get_operand1 (inst)] += 4; |
| 2274 | } |
| 2275 | |
| 2276 | /* A prefix doesn't change the xflag_found. But the rest of the flags |
| 2277 | need updating. */ |
| 2278 | inst_env->slot_needed = 0; |
| 2279 | inst_env->xflag_found = 0; |
| 2280 | inst_env->prefix_found = 1; |
| 2281 | } |
| 2282 | |
| 2283 | /* Finds the destination for a branch with 8-bits offset. */ |
| 2284 | |
| 2285 | static void |
| 2286 | eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
| 2287 | { |
| 2288 | |
| 2289 | short offset; |
| 2290 | |
| 2291 | /* If we have a prefix or are in a delay slot it's bad. */ |
| 2292 | if (inst_env->slot_needed || inst_env->prefix_found) |
| 2293 | { |
| 2294 | inst_env->invalid = 1; |
| 2295 | return; |
| 2296 | } |
| 2297 | |
| 2298 | /* We have a branch, find out where the branch will land. */ |
| 2299 | offset = cris_get_branch_short_offset (inst); |
| 2300 | |
| 2301 | /* Check if the offset is signed. */ |
| 2302 | if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK) |
| 2303 | { |
| 2304 | offset |= 0xFF00; |
| 2305 | } |
| 2306 | |
| 2307 | /* The offset ends with the sign bit, set it to zero. The address |
| 2308 | should always be word aligned. */ |
| 2309 | offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK; |
| 2310 | |
| 2311 | inst_env->branch_found = 1; |
| 2312 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; |
| 2313 | |
| 2314 | inst_env->slot_needed = 1; |
| 2315 | inst_env->prefix_found = 0; |
| 2316 | inst_env->xflag_found = 0; |
| 2317 | inst_env->disable_interrupt = 1; |
| 2318 | } |
| 2319 | |
| 2320 | /* Finds the destination for a branch with 16-bits offset. */ |
| 2321 | |
| 2322 | static void |
| 2323 | sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
| 2324 | { |
| 2325 | short offset; |
| 2326 | |
| 2327 | /* If we have a prefix or is in a delay slot it's bad. */ |
| 2328 | if (inst_env->slot_needed || inst_env->prefix_found) |
| 2329 | { |
| 2330 | inst_env->invalid = 1; |
| 2331 | return; |
| 2332 | } |
| 2333 | |
| 2334 | /* We have a branch, find out the offset for the branch. */ |
| 2335 | offset = read_memory_integer (inst_env->reg[REG_PC], 2, |
| 2336 | inst_env->byte_order); |
| 2337 | |
| 2338 | /* The instruction is one word longer than normal, so add one word |
| 2339 | to the PC. */ |
| 2340 | inst_env->reg[REG_PC] += 2; |
| 2341 | |
| 2342 | inst_env->branch_found = 1; |
| 2343 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; |
| 2344 | |
| 2345 | |
| 2346 | inst_env->slot_needed = 1; |
| 2347 | inst_env->prefix_found = 0; |
| 2348 | inst_env->xflag_found = 0; |
| 2349 | inst_env->disable_interrupt = 1; |
| 2350 | } |
| 2351 | |
| 2352 | /* Handles the ABS instruction. */ |
| 2353 | |
| 2354 | static void |
| 2355 | abs_op (unsigned short inst, inst_env_type *inst_env) |
| 2356 | { |
| 2357 | |
| 2358 | long value; |
| 2359 | |
| 2360 | /* ABS can't have a prefix, so it's bad if it does. */ |
| 2361 | if (inst_env->prefix_found) |
| 2362 | { |
| 2363 | inst_env->invalid = 1; |
| 2364 | return; |
| 2365 | } |
| 2366 | |
| 2367 | /* Check if the operation affects the PC. */ |
| 2368 | if (cris_get_operand2 (inst) == REG_PC) |
| 2369 | { |
| 2370 | |
| 2371 | /* It's invalid to change to the PC if we are in a delay slot. */ |
| 2372 | if (inst_env->slot_needed) |
| 2373 | { |
| 2374 | inst_env->invalid = 1; |
| 2375 | return; |
| 2376 | } |
| 2377 | |
| 2378 | value = (long) inst_env->reg[REG_PC]; |
| 2379 | |
| 2380 | /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */ |
| 2381 | if (value != SIGNED_DWORD_MASK) |
| 2382 | { |
| 2383 | value = -value; |
| 2384 | inst_env->reg[REG_PC] = (long) value; |
| 2385 | } |
| 2386 | } |
| 2387 | |
| 2388 | inst_env->slot_needed = 0; |
| 2389 | inst_env->prefix_found = 0; |
| 2390 | inst_env->xflag_found = 0; |
| 2391 | inst_env->disable_interrupt = 0; |
| 2392 | } |
| 2393 | |
| 2394 | /* Handles the ADDI instruction. */ |
| 2395 | |
| 2396 | static void |
| 2397 | addi_op (unsigned short inst, inst_env_type *inst_env) |
| 2398 | { |
| 2399 | /* It's invalid to have the PC as base register. And ADDI can't have |
| 2400 | a prefix. */ |
| 2401 | if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC)) |
| 2402 | { |
| 2403 | inst_env->invalid = 1; |
| 2404 | return; |
| 2405 | } |
| 2406 | |
| 2407 | inst_env->slot_needed = 0; |
| 2408 | inst_env->prefix_found = 0; |
| 2409 | inst_env->xflag_found = 0; |
| 2410 | inst_env->disable_interrupt = 0; |
| 2411 | } |
| 2412 | |
| 2413 | /* Handles the ASR instruction. */ |
| 2414 | |
| 2415 | static void |
| 2416 | asr_op (unsigned short inst, inst_env_type *inst_env) |
| 2417 | { |
| 2418 | int shift_steps; |
| 2419 | unsigned long value; |
| 2420 | unsigned long signed_extend_mask = 0; |
| 2421 | |
| 2422 | /* ASR can't have a prefix, so check that it doesn't. */ |
| 2423 | if (inst_env->prefix_found) |
| 2424 | { |
| 2425 | inst_env->invalid = 1; |
| 2426 | return; |
| 2427 | } |
| 2428 | |
| 2429 | /* Check if the PC is the target register. */ |
| 2430 | if (cris_get_operand2 (inst) == REG_PC) |
| 2431 | { |
| 2432 | /* It's invalid to change the PC in a delay slot. */ |
| 2433 | if (inst_env->slot_needed) |
| 2434 | { |
| 2435 | inst_env->invalid = 1; |
| 2436 | return; |
| 2437 | } |
| 2438 | /* Get the number of bits to shift. */ |
| 2439 | shift_steps |
| 2440 | = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]); |
| 2441 | value = inst_env->reg[REG_PC]; |
| 2442 | |
| 2443 | /* Find out how many bits the operation should apply to. */ |
| 2444 | if (cris_get_size (inst) == INST_BYTE_SIZE) |
| 2445 | { |
| 2446 | if (value & SIGNED_BYTE_MASK) |
| 2447 | { |
| 2448 | signed_extend_mask = 0xFF; |
| 2449 | signed_extend_mask = signed_extend_mask >> shift_steps; |
| 2450 | signed_extend_mask = ~signed_extend_mask; |
| 2451 | } |
| 2452 | value = value >> shift_steps; |
| 2453 | value |= signed_extend_mask; |
| 2454 | value &= 0xFF; |
| 2455 | inst_env->reg[REG_PC] &= 0xFFFFFF00; |
| 2456 | inst_env->reg[REG_PC] |= value; |
| 2457 | } |
| 2458 | else if (cris_get_size (inst) == INST_WORD_SIZE) |
| 2459 | { |
| 2460 | if (value & SIGNED_WORD_MASK) |
| 2461 | { |
| 2462 | signed_extend_mask = 0xFFFF; |
| 2463 | signed_extend_mask = signed_extend_mask >> shift_steps; |
| 2464 | signed_extend_mask = ~signed_extend_mask; |
| 2465 | } |
| 2466 | value = value >> shift_steps; |
| 2467 | value |= signed_extend_mask; |
| 2468 | value &= 0xFFFF; |
| 2469 | inst_env->reg[REG_PC] &= 0xFFFF0000; |
| 2470 | inst_env->reg[REG_PC] |= value; |
| 2471 | } |
| 2472 | else if (cris_get_size (inst) == INST_DWORD_SIZE) |
| 2473 | { |
| 2474 | if (value & SIGNED_DWORD_MASK) |
| 2475 | { |
| 2476 | signed_extend_mask = 0xFFFFFFFF; |
| 2477 | signed_extend_mask = signed_extend_mask >> shift_steps; |
| 2478 | signed_extend_mask = ~signed_extend_mask; |
| 2479 | } |
| 2480 | value = value >> shift_steps; |
| 2481 | value |= signed_extend_mask; |
| 2482 | inst_env->reg[REG_PC] = value; |
| 2483 | } |
| 2484 | } |
| 2485 | inst_env->slot_needed = 0; |
| 2486 | inst_env->prefix_found = 0; |
| 2487 | inst_env->xflag_found = 0; |
| 2488 | inst_env->disable_interrupt = 0; |
| 2489 | } |
| 2490 | |
| 2491 | /* Handles the ASRQ instruction. */ |
| 2492 | |
| 2493 | static void |
| 2494 | asrq_op (unsigned short inst, inst_env_type *inst_env) |
| 2495 | { |
| 2496 | |
| 2497 | int shift_steps; |
| 2498 | unsigned long value; |
| 2499 | unsigned long signed_extend_mask = 0; |
| 2500 | |
| 2501 | /* ASRQ can't have a prefix, so check that it doesn't. */ |
| 2502 | if (inst_env->prefix_found) |
| 2503 | { |
| 2504 | inst_env->invalid = 1; |
| 2505 | return; |
| 2506 | } |
| 2507 | |
| 2508 | /* Check if the PC is the target register. */ |
| 2509 | if (cris_get_operand2 (inst) == REG_PC) |
| 2510 | { |
| 2511 | |
| 2512 | /* It's invalid to change the PC in a delay slot. */ |
| 2513 | if (inst_env->slot_needed) |
| 2514 | { |
| 2515 | inst_env->invalid = 1; |
| 2516 | return; |
| 2517 | } |
| 2518 | /* The shift size is given as a 5 bit quick value, i.e. we don't |
| 2519 | want the sign bit of the quick value. */ |
| 2520 | shift_steps = cris_get_asr_shift_steps (inst); |
| 2521 | value = inst_env->reg[REG_PC]; |
| 2522 | if (value & SIGNED_DWORD_MASK) |
| 2523 | { |
| 2524 | signed_extend_mask = 0xFFFFFFFF; |
| 2525 | signed_extend_mask = signed_extend_mask >> shift_steps; |
| 2526 | signed_extend_mask = ~signed_extend_mask; |
| 2527 | } |
| 2528 | value = value >> shift_steps; |
| 2529 | value |= signed_extend_mask; |
| 2530 | inst_env->reg[REG_PC] = value; |
| 2531 | } |
| 2532 | inst_env->slot_needed = 0; |
| 2533 | inst_env->prefix_found = 0; |
| 2534 | inst_env->xflag_found = 0; |
| 2535 | inst_env->disable_interrupt = 0; |
| 2536 | } |
| 2537 | |
| 2538 | /* Handles the AX, EI and SETF instruction. */ |
| 2539 | |
| 2540 | static void |
| 2541 | ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env) |
| 2542 | { |
| 2543 | if (inst_env->prefix_found) |
| 2544 | { |
| 2545 | inst_env->invalid = 1; |
| 2546 | return; |
| 2547 | } |
| 2548 | /* Check if the instruction is setting the X flag. */ |
| 2549 | if (cris_is_xflag_bit_on (inst)) |
| 2550 | { |
| 2551 | inst_env->xflag_found = 1; |
| 2552 | } |
| 2553 | else |
| 2554 | { |
| 2555 | inst_env->xflag_found = 0; |
| 2556 | } |
| 2557 | inst_env->slot_needed = 0; |
| 2558 | inst_env->prefix_found = 0; |
| 2559 | inst_env->disable_interrupt = 1; |
| 2560 | } |
| 2561 | |
| 2562 | /* Checks if the instruction is in assign mode. If so, it updates the assign |
| 2563 | register. Note that check_assign assumes that the caller has checked that |
| 2564 | there is a prefix to this instruction. The mode check depends on this. */ |
| 2565 | |
| 2566 | static void |
| 2567 | check_assign (unsigned short inst, inst_env_type *inst_env) |
| 2568 | { |
| 2569 | /* Check if it's an assign addressing mode. */ |
| 2570 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) |
| 2571 | { |
| 2572 | /* Assign the prefix value to operand 1. */ |
| 2573 | inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value; |
| 2574 | } |
| 2575 | } |
| 2576 | |
| 2577 | /* Handles the 2-operand BOUND instruction. */ |
| 2578 | |
| 2579 | static void |
| 2580 | two_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
| 2581 | { |
| 2582 | /* It's invalid to have the PC as the index operand. */ |
| 2583 | if (cris_get_operand2 (inst) == REG_PC) |
| 2584 | { |
| 2585 | inst_env->invalid = 1; |
| 2586 | return; |
| 2587 | } |
| 2588 | /* Check if we have a prefix. */ |
| 2589 | if (inst_env->prefix_found) |
| 2590 | { |
| 2591 | check_assign (inst, inst_env); |
| 2592 | } |
| 2593 | /* Check if this is an autoincrement mode. */ |
| 2594 | else if (cris_get_mode (inst) == AUTOINC_MODE) |
| 2595 | { |
| 2596 | /* It's invalid to change the PC in a delay slot. */ |
| 2597 | if (inst_env->slot_needed) |
| 2598 | { |
| 2599 | inst_env->invalid = 1; |
| 2600 | return; |
| 2601 | } |
| 2602 | process_autoincrement (cris_get_size (inst), inst, inst_env); |
| 2603 | } |
| 2604 | inst_env->slot_needed = 0; |
| 2605 | inst_env->prefix_found = 0; |
| 2606 | inst_env->xflag_found = 0; |
| 2607 | inst_env->disable_interrupt = 0; |
| 2608 | } |
| 2609 | |
| 2610 | /* Handles the 3-operand BOUND instruction. */ |
| 2611 | |
| 2612 | static void |
| 2613 | three_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
| 2614 | { |
| 2615 | /* It's an error if we haven't got a prefix. And it's also an error |
| 2616 | if the PC is the destination register. */ |
| 2617 | if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC)) |
| 2618 | { |
| 2619 | inst_env->invalid = 1; |
| 2620 | return; |
| 2621 | } |
| 2622 | inst_env->slot_needed = 0; |
| 2623 | inst_env->prefix_found = 0; |
| 2624 | inst_env->xflag_found = 0; |
| 2625 | inst_env->disable_interrupt = 0; |
| 2626 | } |
| 2627 | |
| 2628 | /* Clears the status flags in inst_env. */ |
| 2629 | |
| 2630 | static void |
| 2631 | btst_nop_op (unsigned short inst, inst_env_type *inst_env) |
| 2632 | { |
| 2633 | /* It's an error if we have got a prefix. */ |
| 2634 | if (inst_env->prefix_found) |
| 2635 | { |
| 2636 | inst_env->invalid = 1; |
| 2637 | return; |
| 2638 | } |
| 2639 | |
| 2640 | inst_env->slot_needed = 0; |
| 2641 | inst_env->prefix_found = 0; |
| 2642 | inst_env->xflag_found = 0; |
| 2643 | inst_env->disable_interrupt = 0; |
| 2644 | } |
| 2645 | |
| 2646 | /* Clears the status flags in inst_env. */ |
| 2647 | |
| 2648 | static void |
| 2649 | clearf_di_op (unsigned short inst, inst_env_type *inst_env) |
| 2650 | { |
| 2651 | /* It's an error if we have got a prefix. */ |
| 2652 | if (inst_env->prefix_found) |
| 2653 | { |
| 2654 | inst_env->invalid = 1; |
| 2655 | return; |
| 2656 | } |
| 2657 | |
| 2658 | inst_env->slot_needed = 0; |
| 2659 | inst_env->prefix_found = 0; |
| 2660 | inst_env->xflag_found = 0; |
| 2661 | inst_env->disable_interrupt = 1; |
| 2662 | } |
| 2663 | |
| 2664 | /* Handles the CLEAR instruction if it's in register mode. */ |
| 2665 | |
| 2666 | static void |
| 2667 | reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env) |
| 2668 | { |
| 2669 | /* Check if the target is the PC. */ |
| 2670 | if (cris_get_operand2 (inst) == REG_PC) |
| 2671 | { |
| 2672 | /* The instruction will clear the instruction's size bits. */ |
| 2673 | int clear_size = cris_get_clear_size (inst); |
| 2674 | if (clear_size == INST_BYTE_SIZE) |
| 2675 | { |
| 2676 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00; |
| 2677 | } |
| 2678 | if (clear_size == INST_WORD_SIZE) |
| 2679 | { |
| 2680 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000; |
| 2681 | } |
| 2682 | if (clear_size == INST_DWORD_SIZE) |
| 2683 | { |
| 2684 | inst_env->delay_slot_pc = 0x0; |
| 2685 | } |
| 2686 | /* The jump will be delayed with one delay slot. So we need a delay |
| 2687 | slot. */ |
| 2688 | inst_env->slot_needed = 1; |
| 2689 | inst_env->delay_slot_pc_active = 1; |
| 2690 | } |
| 2691 | else |
| 2692 | { |
| 2693 | /* The PC will not change => no delay slot. */ |
| 2694 | inst_env->slot_needed = 0; |
| 2695 | } |
| 2696 | inst_env->prefix_found = 0; |
| 2697 | inst_env->xflag_found = 0; |
| 2698 | inst_env->disable_interrupt = 0; |
| 2699 | } |
| 2700 | |
| 2701 | /* Handles the TEST instruction if it's in register mode. */ |
| 2702 | |
| 2703 | static void |
| 2704 | reg_mode_test_op (unsigned short inst, inst_env_type *inst_env) |
| 2705 | { |
| 2706 | /* It's an error if we have got a prefix. */ |
| 2707 | if (inst_env->prefix_found) |
| 2708 | { |
| 2709 | inst_env->invalid = 1; |
| 2710 | return; |
| 2711 | } |
| 2712 | inst_env->slot_needed = 0; |
| 2713 | inst_env->prefix_found = 0; |
| 2714 | inst_env->xflag_found = 0; |
| 2715 | inst_env->disable_interrupt = 0; |
| 2716 | |
| 2717 | } |
| 2718 | |
| 2719 | /* Handles the CLEAR and TEST instruction if the instruction isn't |
| 2720 | in register mode. */ |
| 2721 | |
| 2722 | static void |
| 2723 | none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env) |
| 2724 | { |
| 2725 | /* Check if we are in a prefix mode. */ |
| 2726 | if (inst_env->prefix_found) |
| 2727 | { |
| 2728 | /* The only way the PC can change is if this instruction is in |
| 2729 | assign addressing mode. */ |
| 2730 | check_assign (inst, inst_env); |
| 2731 | } |
| 2732 | /* Indirect mode can't change the PC so just check if the mode is |
| 2733 | autoincrement. */ |
| 2734 | else if (cris_get_mode (inst) == AUTOINC_MODE) |
| 2735 | { |
| 2736 | process_autoincrement (cris_get_size (inst), inst, inst_env); |
| 2737 | } |
| 2738 | inst_env->slot_needed = 0; |
| 2739 | inst_env->prefix_found = 0; |
| 2740 | inst_env->xflag_found = 0; |
| 2741 | inst_env->disable_interrupt = 0; |
| 2742 | } |
| 2743 | |
| 2744 | /* Checks that the PC isn't the destination register or the instructions has |
| 2745 | a prefix. */ |
| 2746 | |
| 2747 | static void |
| 2748 | dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env) |
| 2749 | { |
| 2750 | /* It's invalid to have the PC as the destination. The instruction can't |
| 2751 | have a prefix. */ |
| 2752 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) |
| 2753 | { |
| 2754 | inst_env->invalid = 1; |
| 2755 | return; |
| 2756 | } |
| 2757 | |
| 2758 | inst_env->slot_needed = 0; |
| 2759 | inst_env->prefix_found = 0; |
| 2760 | inst_env->xflag_found = 0; |
| 2761 | inst_env->disable_interrupt = 0; |
| 2762 | } |
| 2763 | |
| 2764 | /* Checks that the instruction doesn't have a prefix. */ |
| 2765 | |
| 2766 | static void |
| 2767 | break_op (unsigned short inst, inst_env_type *inst_env) |
| 2768 | { |
| 2769 | /* The instruction can't have a prefix. */ |
| 2770 | if (inst_env->prefix_found) |
| 2771 | { |
| 2772 | inst_env->invalid = 1; |
| 2773 | return; |
| 2774 | } |
| 2775 | |
| 2776 | inst_env->slot_needed = 0; |
| 2777 | inst_env->prefix_found = 0; |
| 2778 | inst_env->xflag_found = 0; |
| 2779 | inst_env->disable_interrupt = 1; |
| 2780 | } |
| 2781 | |
| 2782 | /* Checks that the PC isn't the destination register and that the instruction |
| 2783 | doesn't have a prefix. */ |
| 2784 | |
| 2785 | static void |
| 2786 | scc_op (unsigned short inst, inst_env_type *inst_env) |
| 2787 | { |
| 2788 | /* It's invalid to have the PC as the destination. The instruction can't |
| 2789 | have a prefix. */ |
| 2790 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) |
| 2791 | { |
| 2792 | inst_env->invalid = 1; |
| 2793 | return; |
| 2794 | } |
| 2795 | |
| 2796 | inst_env->slot_needed = 0; |
| 2797 | inst_env->prefix_found = 0; |
| 2798 | inst_env->xflag_found = 0; |
| 2799 | inst_env->disable_interrupt = 1; |
| 2800 | } |
| 2801 | |
| 2802 | /* Handles the register mode JUMP instruction. */ |
| 2803 | |
| 2804 | static void |
| 2805 | reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) |
| 2806 | { |
| 2807 | /* It's invalid to do a JUMP in a delay slot. The mode is register, so |
| 2808 | you can't have a prefix. */ |
| 2809 | if ((inst_env->slot_needed) || (inst_env->prefix_found)) |
| 2810 | { |
| 2811 | inst_env->invalid = 1; |
| 2812 | return; |
| 2813 | } |
| 2814 | |
| 2815 | /* Just change the PC. */ |
| 2816 | inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)]; |
| 2817 | inst_env->slot_needed = 0; |
| 2818 | inst_env->prefix_found = 0; |
| 2819 | inst_env->xflag_found = 0; |
| 2820 | inst_env->disable_interrupt = 1; |
| 2821 | } |
| 2822 | |
| 2823 | /* Handles the JUMP instruction for all modes except register. */ |
| 2824 | |
| 2825 | static void |
| 2826 | none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) |
| 2827 | { |
| 2828 | unsigned long newpc; |
| 2829 | CORE_ADDR address; |
| 2830 | |
| 2831 | /* It's invalid to do a JUMP in a delay slot. */ |
| 2832 | if (inst_env->slot_needed) |
| 2833 | { |
| 2834 | inst_env->invalid = 1; |
| 2835 | } |
| 2836 | else |
| 2837 | { |
| 2838 | /* Check if we have a prefix. */ |
| 2839 | if (inst_env->prefix_found) |
| 2840 | { |
| 2841 | check_assign (inst, inst_env); |
| 2842 | |
| 2843 | /* Get the new value for the PC. */ |
| 2844 | newpc = |
| 2845 | read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value, |
| 2846 | 4, inst_env->byte_order); |
| 2847 | } |
| 2848 | else |
| 2849 | { |
| 2850 | /* Get the new value for the PC. */ |
| 2851 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; |
| 2852 | newpc = read_memory_unsigned_integer (address, |
| 2853 | 4, inst_env->byte_order); |
| 2854 | |
| 2855 | /* Check if we should increment a register. */ |
| 2856 | if (cris_get_mode (inst) == AUTOINC_MODE) |
| 2857 | { |
| 2858 | inst_env->reg[cris_get_operand1 (inst)] += 4; |
| 2859 | } |
| 2860 | } |
| 2861 | inst_env->reg[REG_PC] = newpc; |
| 2862 | } |
| 2863 | inst_env->slot_needed = 0; |
| 2864 | inst_env->prefix_found = 0; |
| 2865 | inst_env->xflag_found = 0; |
| 2866 | inst_env->disable_interrupt = 1; |
| 2867 | } |
| 2868 | |
| 2869 | /* Handles moves to special registers (aka P-register) for all modes. */ |
| 2870 | |
| 2871 | static void |
| 2872 | move_to_preg_op (struct gdbarch *gdbarch, unsigned short inst, |
| 2873 | inst_env_type *inst_env) |
| 2874 | { |
| 2875 | if (inst_env->prefix_found) |
| 2876 | { |
| 2877 | /* The instruction has a prefix that means we are only interested if |
| 2878 | the instruction is in assign mode. */ |
| 2879 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) |
| 2880 | { |
| 2881 | /* The prefix handles the problem if we are in a delay slot. */ |
| 2882 | if (cris_get_operand1 (inst) == REG_PC) |
| 2883 | { |
| 2884 | /* Just take care of the assign. */ |
| 2885 | check_assign (inst, inst_env); |
| 2886 | } |
| 2887 | } |
| 2888 | } |
| 2889 | else if (cris_get_mode (inst) == AUTOINC_MODE) |
| 2890 | { |
| 2891 | /* The instruction doesn't have a prefix, the only case left that we |
| 2892 | are interested in is the autoincrement mode. */ |
| 2893 | if (cris_get_operand1 (inst) == REG_PC) |
| 2894 | { |
| 2895 | /* If the PC is to be incremented it's invalid to be in a |
| 2896 | delay slot. */ |
| 2897 | if (inst_env->slot_needed) |
| 2898 | { |
| 2899 | inst_env->invalid = 1; |
| 2900 | return; |
| 2901 | } |
| 2902 | |
| 2903 | /* The increment depends on the size of the special register. */ |
| 2904 | if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1) |
| 2905 | { |
| 2906 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); |
| 2907 | } |
| 2908 | else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2) |
| 2909 | { |
| 2910 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); |
| 2911 | } |
| 2912 | else |
| 2913 | { |
| 2914 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); |
| 2915 | } |
| 2916 | } |
| 2917 | } |
| 2918 | inst_env->slot_needed = 0; |
| 2919 | inst_env->prefix_found = 0; |
| 2920 | inst_env->xflag_found = 0; |
| 2921 | inst_env->disable_interrupt = 1; |
| 2922 | } |
| 2923 | |
| 2924 | /* Handles moves from special registers (aka P-register) for all modes |
| 2925 | except register. */ |
| 2926 | |
| 2927 | static void |
| 2928 | none_reg_mode_move_from_preg_op (struct gdbarch *gdbarch, unsigned short inst, |
| 2929 | inst_env_type *inst_env) |
| 2930 | { |
| 2931 | if (inst_env->prefix_found) |
| 2932 | { |
| 2933 | /* The instruction has a prefix that means we are only interested if |
| 2934 | the instruction is in assign mode. */ |
| 2935 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) |
| 2936 | { |
| 2937 | /* The prefix handles the problem if we are in a delay slot. */ |
| 2938 | if (cris_get_operand1 (inst) == REG_PC) |
| 2939 | { |
| 2940 | /* Just take care of the assign. */ |
| 2941 | check_assign (inst, inst_env); |
| 2942 | } |
| 2943 | } |
| 2944 | } |
| 2945 | /* The instruction doesn't have a prefix, the only case left that we |
| 2946 | are interested in is the autoincrement mode. */ |
| 2947 | else if (cris_get_mode (inst) == AUTOINC_MODE) |
| 2948 | { |
| 2949 | if (cris_get_operand1 (inst) == REG_PC) |
| 2950 | { |
| 2951 | /* If the PC is to be incremented it's invalid to be in a |
| 2952 | delay slot. */ |
| 2953 | if (inst_env->slot_needed) |
| 2954 | { |
| 2955 | inst_env->invalid = 1; |
| 2956 | return; |
| 2957 | } |
| 2958 | |
| 2959 | /* The increment depends on the size of the special register. */ |
| 2960 | if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1) |
| 2961 | { |
| 2962 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); |
| 2963 | } |
| 2964 | else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2) |
| 2965 | { |
| 2966 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); |
| 2967 | } |
| 2968 | else |
| 2969 | { |
| 2970 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); |
| 2971 | } |
| 2972 | } |
| 2973 | } |
| 2974 | inst_env->slot_needed = 0; |
| 2975 | inst_env->prefix_found = 0; |
| 2976 | inst_env->xflag_found = 0; |
| 2977 | inst_env->disable_interrupt = 1; |
| 2978 | } |
| 2979 | |
| 2980 | /* Handles moves from special registers (aka P-register) when the mode |
| 2981 | is register. */ |
| 2982 | |
| 2983 | static void |
| 2984 | reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) |
| 2985 | { |
| 2986 | /* Register mode move from special register can't have a prefix. */ |
| 2987 | if (inst_env->prefix_found) |
| 2988 | { |
| 2989 | inst_env->invalid = 1; |
| 2990 | return; |
| 2991 | } |
| 2992 | |
| 2993 | if (cris_get_operand1 (inst) == REG_PC) |
| 2994 | { |
| 2995 | /* It's invalid to change the PC in a delay slot. */ |
| 2996 | if (inst_env->slot_needed) |
| 2997 | { |
| 2998 | inst_env->invalid = 1; |
| 2999 | return; |
| 3000 | } |
| 3001 | /* The destination is the PC, the jump will have a delay slot. */ |
| 3002 | inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)]; |
| 3003 | inst_env->slot_needed = 1; |
| 3004 | inst_env->delay_slot_pc_active = 1; |
| 3005 | } |
| 3006 | else |
| 3007 | { |
| 3008 | /* If the destination isn't PC, there will be no jump. */ |
| 3009 | inst_env->slot_needed = 0; |
| 3010 | } |
| 3011 | inst_env->prefix_found = 0; |
| 3012 | inst_env->xflag_found = 0; |
| 3013 | inst_env->disable_interrupt = 1; |
| 3014 | } |
| 3015 | |
| 3016 | /* Handles the MOVEM from memory to general register instruction. */ |
| 3017 | |
| 3018 | static void |
| 3019 | move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env) |
| 3020 | { |
| 3021 | if (inst_env->prefix_found) |
| 3022 | { |
| 3023 | /* The prefix handles the problem if we are in a delay slot. Is the |
| 3024 | MOVEM instruction going to change the PC? */ |
| 3025 | if (cris_get_operand2 (inst) >= REG_PC) |
| 3026 | { |
| 3027 | inst_env->reg[REG_PC] = |
| 3028 | read_memory_unsigned_integer (inst_env->prefix_value, |
| 3029 | 4, inst_env->byte_order); |
| 3030 | } |
| 3031 | /* The assign value is the value after the increment. Normally, the |
| 3032 | assign value is the value before the increment. */ |
| 3033 | if ((cris_get_operand1 (inst) == REG_PC) |
| 3034 | && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) |
| 3035 | { |
| 3036 | inst_env->reg[REG_PC] = inst_env->prefix_value; |
| 3037 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); |
| 3038 | } |
| 3039 | } |
| 3040 | else |
| 3041 | { |
| 3042 | /* Is the MOVEM instruction going to change the PC? */ |
| 3043 | if (cris_get_operand2 (inst) == REG_PC) |
| 3044 | { |
| 3045 | /* It's invalid to change the PC in a delay slot. */ |
| 3046 | if (inst_env->slot_needed) |
| 3047 | { |
| 3048 | inst_env->invalid = 1; |
| 3049 | return; |
| 3050 | } |
| 3051 | inst_env->reg[REG_PC] = |
| 3052 | read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)], |
| 3053 | 4, inst_env->byte_order); |
| 3054 | } |
| 3055 | /* The increment is not depending on the size, instead it's depending |
| 3056 | on the number of registers loaded from memory. */ |
| 3057 | if ((cris_get_operand1 (inst) == REG_PC) |
| 3058 | && (cris_get_mode (inst) == AUTOINC_MODE)) |
| 3059 | { |
| 3060 | /* It's invalid to change the PC in a delay slot. */ |
| 3061 | if (inst_env->slot_needed) |
| 3062 | { |
| 3063 | inst_env->invalid = 1; |
| 3064 | return; |
| 3065 | } |
| 3066 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); |
| 3067 | } |
| 3068 | } |
| 3069 | inst_env->slot_needed = 0; |
| 3070 | inst_env->prefix_found = 0; |
| 3071 | inst_env->xflag_found = 0; |
| 3072 | inst_env->disable_interrupt = 0; |
| 3073 | } |
| 3074 | |
| 3075 | /* Handles the MOVEM to memory from general register instruction. */ |
| 3076 | |
| 3077 | static void |
| 3078 | move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env) |
| 3079 | { |
| 3080 | if (inst_env->prefix_found) |
| 3081 | { |
| 3082 | /* The assign value is the value after the increment. Normally, the |
| 3083 | assign value is the value before the increment. */ |
| 3084 | if ((cris_get_operand1 (inst) == REG_PC) |
| 3085 | && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) |
| 3086 | { |
| 3087 | /* The prefix handles the problem if we are in a delay slot. */ |
| 3088 | inst_env->reg[REG_PC] = inst_env->prefix_value; |
| 3089 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); |
| 3090 | } |
| 3091 | } |
| 3092 | else |
| 3093 | { |
| 3094 | /* The increment is not depending on the size, instead it's depending |
| 3095 | on the number of registers loaded to memory. */ |
| 3096 | if ((cris_get_operand1 (inst) == REG_PC) |
| 3097 | && (cris_get_mode (inst) == AUTOINC_MODE)) |
| 3098 | { |
| 3099 | /* It's invalid to change the PC in a delay slot. */ |
| 3100 | if (inst_env->slot_needed) |
| 3101 | { |
| 3102 | inst_env->invalid = 1; |
| 3103 | return; |
| 3104 | } |
| 3105 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); |
| 3106 | } |
| 3107 | } |
| 3108 | inst_env->slot_needed = 0; |
| 3109 | inst_env->prefix_found = 0; |
| 3110 | inst_env->xflag_found = 0; |
| 3111 | inst_env->disable_interrupt = 0; |
| 3112 | } |
| 3113 | |
| 3114 | /* Handles the intructions that's not yet implemented, by setting |
| 3115 | inst_env->invalid to true. */ |
| 3116 | |
| 3117 | static void |
| 3118 | not_implemented_op (unsigned short inst, inst_env_type *inst_env) |
| 3119 | { |
| 3120 | inst_env->invalid = 1; |
| 3121 | } |
| 3122 | |
| 3123 | /* Handles the XOR instruction. */ |
| 3124 | |
| 3125 | static void |
| 3126 | xor_op (unsigned short inst, inst_env_type *inst_env) |
| 3127 | { |
| 3128 | /* XOR can't have a prefix. */ |
| 3129 | if (inst_env->prefix_found) |
| 3130 | { |
| 3131 | inst_env->invalid = 1; |
| 3132 | return; |
| 3133 | } |
| 3134 | |
| 3135 | /* Check if the PC is the target. */ |
| 3136 | if (cris_get_operand2 (inst) == REG_PC) |
| 3137 | { |
| 3138 | /* It's invalid to change the PC in a delay slot. */ |
| 3139 | if (inst_env->slot_needed) |
| 3140 | { |
| 3141 | inst_env->invalid = 1; |
| 3142 | return; |
| 3143 | } |
| 3144 | inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)]; |
| 3145 | } |
| 3146 | inst_env->slot_needed = 0; |
| 3147 | inst_env->prefix_found = 0; |
| 3148 | inst_env->xflag_found = 0; |
| 3149 | inst_env->disable_interrupt = 0; |
| 3150 | } |
| 3151 | |
| 3152 | /* Handles the MULS instruction. */ |
| 3153 | |
| 3154 | static void |
| 3155 | muls_op (unsigned short inst, inst_env_type *inst_env) |
| 3156 | { |
| 3157 | /* MULS/U can't have a prefix. */ |
| 3158 | if (inst_env->prefix_found) |
| 3159 | { |
| 3160 | inst_env->invalid = 1; |
| 3161 | return; |
| 3162 | } |
| 3163 | |
| 3164 | /* Consider it invalid if the PC is the target. */ |
| 3165 | if (cris_get_operand2 (inst) == REG_PC) |
| 3166 | { |
| 3167 | inst_env->invalid = 1; |
| 3168 | return; |
| 3169 | } |
| 3170 | inst_env->slot_needed = 0; |
| 3171 | inst_env->prefix_found = 0; |
| 3172 | inst_env->xflag_found = 0; |
| 3173 | inst_env->disable_interrupt = 0; |
| 3174 | } |
| 3175 | |
| 3176 | /* Handles the MULU instruction. */ |
| 3177 | |
| 3178 | static void |
| 3179 | mulu_op (unsigned short inst, inst_env_type *inst_env) |
| 3180 | { |
| 3181 | /* MULS/U can't have a prefix. */ |
| 3182 | if (inst_env->prefix_found) |
| 3183 | { |
| 3184 | inst_env->invalid = 1; |
| 3185 | return; |
| 3186 | } |
| 3187 | |
| 3188 | /* Consider it invalid if the PC is the target. */ |
| 3189 | if (cris_get_operand2 (inst) == REG_PC) |
| 3190 | { |
| 3191 | inst_env->invalid = 1; |
| 3192 | return; |
| 3193 | } |
| 3194 | inst_env->slot_needed = 0; |
| 3195 | inst_env->prefix_found = 0; |
| 3196 | inst_env->xflag_found = 0; |
| 3197 | inst_env->disable_interrupt = 0; |
| 3198 | } |
| 3199 | |
| 3200 | /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE. |
| 3201 | The MOVE instruction is the move from source to register. */ |
| 3202 | |
| 3203 | static void |
| 3204 | add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env, |
| 3205 | unsigned long source1, unsigned long source2) |
| 3206 | { |
| 3207 | unsigned long pc_mask; |
| 3208 | unsigned long operation_mask; |
| 3209 | |
| 3210 | /* Find out how many bits the operation should apply to. */ |
| 3211 | if (cris_get_size (inst) == INST_BYTE_SIZE) |
| 3212 | { |
| 3213 | pc_mask = 0xFFFFFF00; |
| 3214 | operation_mask = 0xFF; |
| 3215 | } |
| 3216 | else if (cris_get_size (inst) == INST_WORD_SIZE) |
| 3217 | { |
| 3218 | pc_mask = 0xFFFF0000; |
| 3219 | operation_mask = 0xFFFF; |
| 3220 | } |
| 3221 | else if (cris_get_size (inst) == INST_DWORD_SIZE) |
| 3222 | { |
| 3223 | pc_mask = 0x0; |
| 3224 | operation_mask = 0xFFFFFFFF; |
| 3225 | } |
| 3226 | else |
| 3227 | { |
| 3228 | /* The size is out of range. */ |
| 3229 | inst_env->invalid = 1; |
| 3230 | return; |
| 3231 | } |
| 3232 | |
| 3233 | /* The instruction just works on uw_operation_mask bits. */ |
| 3234 | source2 &= operation_mask; |
| 3235 | source1 &= operation_mask; |
| 3236 | |
| 3237 | /* Now calculate the result. The opcode's 3 first bits separates |
| 3238 | the different actions. */ |
| 3239 | switch (cris_get_opcode (inst) & 7) |
| 3240 | { |
| 3241 | case 0: /* add */ |
| 3242 | source1 += source2; |
| 3243 | break; |
| 3244 | |
| 3245 | case 1: /* move */ |
| 3246 | source1 = source2; |
| 3247 | break; |
| 3248 | |
| 3249 | case 2: /* subtract */ |
| 3250 | source1 -= source2; |
| 3251 | break; |
| 3252 | |
| 3253 | case 3: /* compare */ |
| 3254 | break; |
| 3255 | |
| 3256 | case 4: /* and */ |
| 3257 | source1 &= source2; |
| 3258 | break; |
| 3259 | |
| 3260 | case 5: /* or */ |
| 3261 | source1 |= source2; |
| 3262 | break; |
| 3263 | |
| 3264 | default: |
| 3265 | inst_env->invalid = 1; |
| 3266 | return; |
| 3267 | |
| 3268 | break; |
| 3269 | } |
| 3270 | |
| 3271 | /* Make sure that the result doesn't contain more than the instruction |
| 3272 | size bits. */ |
| 3273 | source2 &= operation_mask; |
| 3274 | |
| 3275 | /* Calculate the new breakpoint address. */ |
| 3276 | inst_env->reg[REG_PC] &= pc_mask; |
| 3277 | inst_env->reg[REG_PC] |= source1; |
| 3278 | |
| 3279 | } |
| 3280 | |
| 3281 | /* Extends the value from either byte or word size to a dword. If the mode |
| 3282 | is zero extend then the value is extended with zero. If instead the mode |
| 3283 | is signed extend the sign bit of the value is taken into consideration. */ |
| 3284 | |
| 3285 | static unsigned long |
| 3286 | do_sign_or_zero_extend (unsigned long value, unsigned short *inst) |
| 3287 | { |
| 3288 | /* The size can be either byte or word, check which one it is. |
| 3289 | Don't check the highest bit, it's indicating if it's a zero |
| 3290 | or sign extend. */ |
| 3291 | if (cris_get_size (*inst) & INST_WORD_SIZE) |
| 3292 | { |
| 3293 | /* Word size. */ |
| 3294 | value &= 0xFFFF; |
| 3295 | |
| 3296 | /* Check if the instruction is signed extend. If so, check if value has |
| 3297 | the sign bit on. */ |
| 3298 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK)) |
| 3299 | { |
| 3300 | value |= SIGNED_WORD_EXTEND_MASK; |
| 3301 | } |
| 3302 | } |
| 3303 | else |
| 3304 | { |
| 3305 | /* Byte size. */ |
| 3306 | value &= 0xFF; |
| 3307 | |
| 3308 | /* Check if the instruction is signed extend. If so, check if value has |
| 3309 | the sign bit on. */ |
| 3310 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK)) |
| 3311 | { |
| 3312 | value |= SIGNED_BYTE_EXTEND_MASK; |
| 3313 | } |
| 3314 | } |
| 3315 | /* The size should now be dword. */ |
| 3316 | cris_set_size_to_dword (inst); |
| 3317 | return value; |
| 3318 | } |
| 3319 | |
| 3320 | /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE |
| 3321 | instruction. The MOVE instruction is the move from source to register. */ |
| 3322 | |
| 3323 | static void |
| 3324 | reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
| 3325 | inst_env_type *inst_env) |
| 3326 | { |
| 3327 | unsigned long operand1; |
| 3328 | unsigned long operand2; |
| 3329 | |
| 3330 | /* It's invalid to have a prefix to the instruction. This is a register |
| 3331 | mode instruction and can't have a prefix. */ |
| 3332 | if (inst_env->prefix_found) |
| 3333 | { |
| 3334 | inst_env->invalid = 1; |
| 3335 | return; |
| 3336 | } |
| 3337 | /* Check if the instruction has PC as its target. */ |
| 3338 | if (cris_get_operand2 (inst) == REG_PC) |
| 3339 | { |
| 3340 | if (inst_env->slot_needed) |
| 3341 | { |
| 3342 | inst_env->invalid = 1; |
| 3343 | return; |
| 3344 | } |
| 3345 | /* The instruction has the PC as its target register. */ |
| 3346 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; |
| 3347 | operand2 = inst_env->reg[REG_PC]; |
| 3348 | |
| 3349 | /* Check if it's a extend, signed or zero instruction. */ |
| 3350 | if (cris_get_opcode (inst) < 4) |
| 3351 | { |
| 3352 | operand1 = do_sign_or_zero_extend (operand1, &inst); |
| 3353 | } |
| 3354 | /* Calculate the PC value after the instruction, i.e. where the |
| 3355 | breakpoint should be. The order of the udw_operands is vital. */ |
| 3356 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); |
| 3357 | } |
| 3358 | inst_env->slot_needed = 0; |
| 3359 | inst_env->prefix_found = 0; |
| 3360 | inst_env->xflag_found = 0; |
| 3361 | inst_env->disable_interrupt = 0; |
| 3362 | } |
| 3363 | |
| 3364 | /* Returns the data contained at address. The size of the data is derived from |
| 3365 | the size of the operation. If the instruction is a zero or signed |
| 3366 | extend instruction, the size field is changed in instruction. */ |
| 3367 | |
| 3368 | static unsigned long |
| 3369 | get_data_from_address (unsigned short *inst, CORE_ADDR address, |
| 3370 | enum bfd_endian byte_order) |
| 3371 | { |
| 3372 | int size = cris_get_size (*inst); |
| 3373 | unsigned long value; |
| 3374 | |
| 3375 | /* If it's an extend instruction we don't want the signed extend bit, |
| 3376 | because it influences the size. */ |
| 3377 | if (cris_get_opcode (*inst) < 4) |
| 3378 | { |
| 3379 | size &= ~SIGNED_EXTEND_BIT_MASK; |
| 3380 | } |
| 3381 | /* Is there a need for checking the size? Size should contain the number of |
| 3382 | bytes to read. */ |
| 3383 | size = 1 << size; |
| 3384 | value = read_memory_unsigned_integer (address, size, byte_order); |
| 3385 | |
| 3386 | /* Check if it's an extend, signed or zero instruction. */ |
| 3387 | if (cris_get_opcode (*inst) < 4) |
| 3388 | { |
| 3389 | value = do_sign_or_zero_extend (value, inst); |
| 3390 | } |
| 3391 | return value; |
| 3392 | } |
| 3393 | |
| 3394 | /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE |
| 3395 | instructions. The MOVE instruction is the move from source to register. */ |
| 3396 | |
| 3397 | static void |
| 3398 | handle_prefix_assign_mode_for_aritm_op (unsigned short inst, |
| 3399 | inst_env_type *inst_env) |
| 3400 | { |
| 3401 | unsigned long operand2; |
| 3402 | unsigned long operand3; |
| 3403 | |
| 3404 | check_assign (inst, inst_env); |
| 3405 | if (cris_get_operand2 (inst) == REG_PC) |
| 3406 | { |
| 3407 | operand2 = inst_env->reg[REG_PC]; |
| 3408 | |
| 3409 | /* Get the value of the third operand. */ |
| 3410 | operand3 = get_data_from_address (&inst, inst_env->prefix_value, |
| 3411 | inst_env->byte_order); |
| 3412 | |
| 3413 | /* Calculate the PC value after the instruction, i.e. where the |
| 3414 | breakpoint should be. The order of the udw_operands is vital. */ |
| 3415 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); |
| 3416 | } |
| 3417 | inst_env->slot_needed = 0; |
| 3418 | inst_env->prefix_found = 0; |
| 3419 | inst_env->xflag_found = 0; |
| 3420 | inst_env->disable_interrupt = 0; |
| 3421 | } |
| 3422 | |
| 3423 | /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and |
| 3424 | OR instructions. Note that for this to work as expected, the calling |
| 3425 | function must have made sure that there is a prefix to this instruction. */ |
| 3426 | |
| 3427 | static void |
| 3428 | three_operand_add_sub_cmp_and_or_op (unsigned short inst, |
| 3429 | inst_env_type *inst_env) |
| 3430 | { |
| 3431 | unsigned long operand2; |
| 3432 | unsigned long operand3; |
| 3433 | |
| 3434 | if (cris_get_operand1 (inst) == REG_PC) |
| 3435 | { |
| 3436 | /* The PC will be changed by the instruction. */ |
| 3437 | operand2 = inst_env->reg[cris_get_operand2 (inst)]; |
| 3438 | |
| 3439 | /* Get the value of the third operand. */ |
| 3440 | operand3 = get_data_from_address (&inst, inst_env->prefix_value, |
| 3441 | inst_env->byte_order); |
| 3442 | |
| 3443 | /* Calculate the PC value after the instruction, i.e. where the |
| 3444 | breakpoint should be. */ |
| 3445 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); |
| 3446 | } |
| 3447 | inst_env->slot_needed = 0; |
| 3448 | inst_env->prefix_found = 0; |
| 3449 | inst_env->xflag_found = 0; |
| 3450 | inst_env->disable_interrupt = 0; |
| 3451 | } |
| 3452 | |
| 3453 | /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE |
| 3454 | instructions. The MOVE instruction is the move from source to register. */ |
| 3455 | |
| 3456 | static void |
| 3457 | handle_prefix_index_mode_for_aritm_op (unsigned short inst, |
| 3458 | inst_env_type *inst_env) |
| 3459 | { |
| 3460 | if (cris_get_operand1 (inst) != cris_get_operand2 (inst)) |
| 3461 | { |
| 3462 | /* If the instruction is MOVE it's invalid. If the instruction is ADD, |
| 3463 | SUB, AND or OR something weird is going on (if everything works these |
| 3464 | instructions should end up in the three operand version). */ |
| 3465 | inst_env->invalid = 1; |
| 3466 | return; |
| 3467 | } |
| 3468 | else |
| 3469 | { |
| 3470 | /* three_operand_add_sub_cmp_and_or does the same as we should do here |
| 3471 | so use it. */ |
| 3472 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); |
| 3473 | } |
| 3474 | inst_env->slot_needed = 0; |
| 3475 | inst_env->prefix_found = 0; |
| 3476 | inst_env->xflag_found = 0; |
| 3477 | inst_env->disable_interrupt = 0; |
| 3478 | } |
| 3479 | |
| 3480 | /* Handles the autoincrement and indirect addresing mode for the ADD, SUB, |
| 3481 | CMP, AND OR and MOVE instruction. The MOVE instruction is the move from |
| 3482 | source to register. */ |
| 3483 | |
| 3484 | static void |
| 3485 | handle_inc_and_index_mode_for_aritm_op (unsigned short inst, |
| 3486 | inst_env_type *inst_env) |
| 3487 | { |
| 3488 | unsigned long operand1; |
| 3489 | unsigned long operand2; |
| 3490 | unsigned long operand3; |
| 3491 | int size; |
| 3492 | |
| 3493 | /* The instruction is either an indirect or autoincrement addressing mode. |
| 3494 | Check if the destination register is the PC. */ |
| 3495 | if (cris_get_operand2 (inst) == REG_PC) |
| 3496 | { |
| 3497 | /* Must be done here, get_data_from_address may change the size |
| 3498 | field. */ |
| 3499 | size = cris_get_size (inst); |
| 3500 | operand2 = inst_env->reg[REG_PC]; |
| 3501 | |
| 3502 | /* Get the value of the third operand, i.e. the indirect operand. */ |
| 3503 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; |
| 3504 | operand3 = get_data_from_address (&inst, operand1, inst_env->byte_order); |
| 3505 | |
| 3506 | /* Calculate the PC value after the instruction, i.e. where the |
| 3507 | breakpoint should be. The order of the udw_operands is vital. */ |
| 3508 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); |
| 3509 | } |
| 3510 | /* If this is an autoincrement addressing mode, check if the increment |
| 3511 | changes the PC. */ |
| 3512 | if ((cris_get_operand1 (inst) == REG_PC) |
| 3513 | && (cris_get_mode (inst) == AUTOINC_MODE)) |
| 3514 | { |
| 3515 | /* Get the size field. */ |
| 3516 | size = cris_get_size (inst); |
| 3517 | |
| 3518 | /* If it's an extend instruction we don't want the signed extend bit, |
| 3519 | because it influences the size. */ |
| 3520 | if (cris_get_opcode (inst) < 4) |
| 3521 | { |
| 3522 | size &= ~SIGNED_EXTEND_BIT_MASK; |
| 3523 | } |
| 3524 | process_autoincrement (size, inst, inst_env); |
| 3525 | } |
| 3526 | inst_env->slot_needed = 0; |
| 3527 | inst_env->prefix_found = 0; |
| 3528 | inst_env->xflag_found = 0; |
| 3529 | inst_env->disable_interrupt = 0; |
| 3530 | } |
| 3531 | |
| 3532 | /* Handles the two-operand addressing mode, all modes except register, for |
| 3533 | the ADD, SUB CMP, AND and OR instruction. */ |
| 3534 | |
| 3535 | static void |
| 3536 | none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
| 3537 | inst_env_type *inst_env) |
| 3538 | { |
| 3539 | if (inst_env->prefix_found) |
| 3540 | { |
| 3541 | if (cris_get_mode (inst) == PREFIX_INDEX_MODE) |
| 3542 | { |
| 3543 | handle_prefix_index_mode_for_aritm_op (inst, inst_env); |
| 3544 | } |
| 3545 | else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) |
| 3546 | { |
| 3547 | handle_prefix_assign_mode_for_aritm_op (inst, inst_env); |
| 3548 | } |
| 3549 | else |
| 3550 | { |
| 3551 | /* The mode is invalid for a prefixed base instruction. */ |
| 3552 | inst_env->invalid = 1; |
| 3553 | return; |
| 3554 | } |
| 3555 | } |
| 3556 | else |
| 3557 | { |
| 3558 | handle_inc_and_index_mode_for_aritm_op (inst, inst_env); |
| 3559 | } |
| 3560 | } |
| 3561 | |
| 3562 | /* Handles the quick addressing mode for the ADD and SUB instruction. */ |
| 3563 | |
| 3564 | static void |
| 3565 | quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env) |
| 3566 | { |
| 3567 | unsigned long operand1; |
| 3568 | unsigned long operand2; |
| 3569 | |
| 3570 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode |
| 3571 | instruction and can't have a prefix. */ |
| 3572 | if (inst_env->prefix_found) |
| 3573 | { |
| 3574 | inst_env->invalid = 1; |
| 3575 | return; |
| 3576 | } |
| 3577 | |
| 3578 | /* Check if the instruction has PC as its target. */ |
| 3579 | if (cris_get_operand2 (inst) == REG_PC) |
| 3580 | { |
| 3581 | if (inst_env->slot_needed) |
| 3582 | { |
| 3583 | inst_env->invalid = 1; |
| 3584 | return; |
| 3585 | } |
| 3586 | operand1 = cris_get_quick_value (inst); |
| 3587 | operand2 = inst_env->reg[REG_PC]; |
| 3588 | |
| 3589 | /* The size should now be dword. */ |
| 3590 | cris_set_size_to_dword (&inst); |
| 3591 | |
| 3592 | /* Calculate the PC value after the instruction, i.e. where the |
| 3593 | breakpoint should be. */ |
| 3594 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); |
| 3595 | } |
| 3596 | inst_env->slot_needed = 0; |
| 3597 | inst_env->prefix_found = 0; |
| 3598 | inst_env->xflag_found = 0; |
| 3599 | inst_env->disable_interrupt = 0; |
| 3600 | } |
| 3601 | |
| 3602 | /* Handles the quick addressing mode for the CMP, AND and OR instruction. */ |
| 3603 | |
| 3604 | static void |
| 3605 | quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env) |
| 3606 | { |
| 3607 | unsigned long operand1; |
| 3608 | unsigned long operand2; |
| 3609 | |
| 3610 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode |
| 3611 | instruction and can't have a prefix. */ |
| 3612 | if (inst_env->prefix_found) |
| 3613 | { |
| 3614 | inst_env->invalid = 1; |
| 3615 | return; |
| 3616 | } |
| 3617 | /* Check if the instruction has PC as its target. */ |
| 3618 | if (cris_get_operand2 (inst) == REG_PC) |
| 3619 | { |
| 3620 | if (inst_env->slot_needed) |
| 3621 | { |
| 3622 | inst_env->invalid = 1; |
| 3623 | return; |
| 3624 | } |
| 3625 | /* The instruction has the PC as its target register. */ |
| 3626 | operand1 = cris_get_quick_value (inst); |
| 3627 | operand2 = inst_env->reg[REG_PC]; |
| 3628 | |
| 3629 | /* The quick value is signed, so check if we must do a signed extend. */ |
| 3630 | if (operand1 & SIGNED_QUICK_VALUE_MASK) |
| 3631 | { |
| 3632 | /* sign extend */ |
| 3633 | operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK; |
| 3634 | } |
| 3635 | /* The size should now be dword. */ |
| 3636 | cris_set_size_to_dword (&inst); |
| 3637 | |
| 3638 | /* Calculate the PC value after the instruction, i.e. where the |
| 3639 | breakpoint should be. */ |
| 3640 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); |
| 3641 | } |
| 3642 | inst_env->slot_needed = 0; |
| 3643 | inst_env->prefix_found = 0; |
| 3644 | inst_env->xflag_found = 0; |
| 3645 | inst_env->disable_interrupt = 0; |
| 3646 | } |
| 3647 | |
| 3648 | /* Translate op_type to a function and call it. */ |
| 3649 | |
| 3650 | static void |
| 3651 | cris_gdb_func (struct gdbarch *gdbarch, enum cris_op_type op_type, |
| 3652 | unsigned short inst, inst_env_type *inst_env) |
| 3653 | { |
| 3654 | switch (op_type) |
| 3655 | { |
| 3656 | case cris_not_implemented_op: |
| 3657 | not_implemented_op (inst, inst_env); |
| 3658 | break; |
| 3659 | |
| 3660 | case cris_abs_op: |
| 3661 | abs_op (inst, inst_env); |
| 3662 | break; |
| 3663 | |
| 3664 | case cris_addi_op: |
| 3665 | addi_op (inst, inst_env); |
| 3666 | break; |
| 3667 | |
| 3668 | case cris_asr_op: |
| 3669 | asr_op (inst, inst_env); |
| 3670 | break; |
| 3671 | |
| 3672 | case cris_asrq_op: |
| 3673 | asrq_op (inst, inst_env); |
| 3674 | break; |
| 3675 | |
| 3676 | case cris_ax_ei_setf_op: |
| 3677 | ax_ei_setf_op (inst, inst_env); |
| 3678 | break; |
| 3679 | |
| 3680 | case cris_bdap_prefix: |
| 3681 | bdap_prefix (inst, inst_env); |
| 3682 | break; |
| 3683 | |
| 3684 | case cris_biap_prefix: |
| 3685 | biap_prefix (inst, inst_env); |
| 3686 | break; |
| 3687 | |
| 3688 | case cris_break_op: |
| 3689 | break_op (inst, inst_env); |
| 3690 | break; |
| 3691 | |
| 3692 | case cris_btst_nop_op: |
| 3693 | btst_nop_op (inst, inst_env); |
| 3694 | break; |
| 3695 | |
| 3696 | case cris_clearf_di_op: |
| 3697 | clearf_di_op (inst, inst_env); |
| 3698 | break; |
| 3699 | |
| 3700 | case cris_dip_prefix: |
| 3701 | dip_prefix (inst, inst_env); |
| 3702 | break; |
| 3703 | |
| 3704 | case cris_dstep_logshift_mstep_neg_not_op: |
| 3705 | dstep_logshift_mstep_neg_not_op (inst, inst_env); |
| 3706 | break; |
| 3707 | |
| 3708 | case cris_eight_bit_offset_branch_op: |
| 3709 | eight_bit_offset_branch_op (inst, inst_env); |
| 3710 | break; |
| 3711 | |
| 3712 | case cris_move_mem_to_reg_movem_op: |
| 3713 | move_mem_to_reg_movem_op (inst, inst_env); |
| 3714 | break; |
| 3715 | |
| 3716 | case cris_move_reg_to_mem_movem_op: |
| 3717 | move_reg_to_mem_movem_op (inst, inst_env); |
| 3718 | break; |
| 3719 | |
| 3720 | case cris_move_to_preg_op: |
| 3721 | move_to_preg_op (gdbarch, inst, inst_env); |
| 3722 | break; |
| 3723 | |
| 3724 | case cris_muls_op: |
| 3725 | muls_op (inst, inst_env); |
| 3726 | break; |
| 3727 | |
| 3728 | case cris_mulu_op: |
| 3729 | mulu_op (inst, inst_env); |
| 3730 | break; |
| 3731 | |
| 3732 | case cris_none_reg_mode_add_sub_cmp_and_or_move_op: |
| 3733 | none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); |
| 3734 | break; |
| 3735 | |
| 3736 | case cris_none_reg_mode_clear_test_op: |
| 3737 | none_reg_mode_clear_test_op (inst, inst_env); |
| 3738 | break; |
| 3739 | |
| 3740 | case cris_none_reg_mode_jump_op: |
| 3741 | none_reg_mode_jump_op (inst, inst_env); |
| 3742 | break; |
| 3743 | |
| 3744 | case cris_none_reg_mode_move_from_preg_op: |
| 3745 | none_reg_mode_move_from_preg_op (gdbarch, inst, inst_env); |
| 3746 | break; |
| 3747 | |
| 3748 | case cris_quick_mode_add_sub_op: |
| 3749 | quick_mode_add_sub_op (inst, inst_env); |
| 3750 | break; |
| 3751 | |
| 3752 | case cris_quick_mode_and_cmp_move_or_op: |
| 3753 | quick_mode_and_cmp_move_or_op (inst, inst_env); |
| 3754 | break; |
| 3755 | |
| 3756 | case cris_quick_mode_bdap_prefix: |
| 3757 | quick_mode_bdap_prefix (inst, inst_env); |
| 3758 | break; |
| 3759 | |
| 3760 | case cris_reg_mode_add_sub_cmp_and_or_move_op: |
| 3761 | reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); |
| 3762 | break; |
| 3763 | |
| 3764 | case cris_reg_mode_clear_op: |
| 3765 | reg_mode_clear_op (inst, inst_env); |
| 3766 | break; |
| 3767 | |
| 3768 | case cris_reg_mode_jump_op: |
| 3769 | reg_mode_jump_op (inst, inst_env); |
| 3770 | break; |
| 3771 | |
| 3772 | case cris_reg_mode_move_from_preg_op: |
| 3773 | reg_mode_move_from_preg_op (inst, inst_env); |
| 3774 | break; |
| 3775 | |
| 3776 | case cris_reg_mode_test_op: |
| 3777 | reg_mode_test_op (inst, inst_env); |
| 3778 | break; |
| 3779 | |
| 3780 | case cris_scc_op: |
| 3781 | scc_op (inst, inst_env); |
| 3782 | break; |
| 3783 | |
| 3784 | case cris_sixteen_bit_offset_branch_op: |
| 3785 | sixteen_bit_offset_branch_op (inst, inst_env); |
| 3786 | break; |
| 3787 | |
| 3788 | case cris_three_operand_add_sub_cmp_and_or_op: |
| 3789 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); |
| 3790 | break; |
| 3791 | |
| 3792 | case cris_three_operand_bound_op: |
| 3793 | three_operand_bound_op (inst, inst_env); |
| 3794 | break; |
| 3795 | |
| 3796 | case cris_two_operand_bound_op: |
| 3797 | two_operand_bound_op (inst, inst_env); |
| 3798 | break; |
| 3799 | |
| 3800 | case cris_xor_op: |
| 3801 | xor_op (inst, inst_env); |
| 3802 | break; |
| 3803 | } |
| 3804 | } |
| 3805 | |
| 3806 | /* This wrapper is to avoid cris_get_assembler being called before |
| 3807 | exec_bfd has been set. */ |
| 3808 | |
| 3809 | static int |
| 3810 | cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info) |
| 3811 | { |
| 3812 | int (*print_insn) (bfd_vma addr, struct disassemble_info *info); |
| 3813 | /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS |
| 3814 | disassembler, even when there is no BFD. Does something like |
| 3815 | "gdb; target remote; disassmeble *0x123" work? */ |
| 3816 | gdb_assert (exec_bfd != NULL); |
| 3817 | print_insn = cris_get_disassembler (exec_bfd); |
| 3818 | gdb_assert (print_insn != NULL); |
| 3819 | return print_insn (addr, info); |
| 3820 | } |
| 3821 | |
| 3822 | /* Copied from <asm/elf.h>. */ |
| 3823 | typedef unsigned long elf_greg_t; |
| 3824 | |
| 3825 | /* Same as user_regs_struct struct in <asm/user.h>. */ |
| 3826 | #define CRISV10_ELF_NGREG 35 |
| 3827 | typedef elf_greg_t elf_gregset_t[CRISV10_ELF_NGREG]; |
| 3828 | |
| 3829 | #define CRISV32_ELF_NGREG 32 |
| 3830 | typedef elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG]; |
| 3831 | |
| 3832 | /* Unpack an elf_gregset_t into GDB's register cache. */ |
| 3833 | |
| 3834 | static void |
| 3835 | cris_supply_gregset (struct regcache *regcache, elf_gregset_t *gregsetp) |
| 3836 | { |
| 3837 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 3838 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3839 | int i; |
| 3840 | elf_greg_t *regp = *gregsetp; |
| 3841 | static char zerobuf[4] = {0}; |
| 3842 | |
| 3843 | /* The kernel dumps all 32 registers as unsigned longs, but supply_register |
| 3844 | knows about the actual size of each register so that's no problem. */ |
| 3845 | for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++) |
| 3846 | { |
| 3847 | regcache_raw_supply (regcache, i, (char *)®p[i]); |
| 3848 | } |
| 3849 | |
| 3850 | if (tdep->cris_version == 32) |
| 3851 | { |
| 3852 | /* Needed to set pseudo-register PC for CRISv32. */ |
| 3853 | /* FIXME: If ERP is in a delay slot at this point then the PC will |
| 3854 | be wrong. Issue a warning to alert the user. */ |
| 3855 | regcache_raw_supply (regcache, gdbarch_pc_regnum (gdbarch), |
| 3856 | (char *)®p[ERP_REGNUM]); |
| 3857 | |
| 3858 | if (*(char *)®p[ERP_REGNUM] & 0x1) |
| 3859 | fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n"); |
| 3860 | } |
| 3861 | } |
| 3862 | |
| 3863 | /* Use a local version of this function to get the correct types for |
| 3864 | regsets, until multi-arch core support is ready. */ |
| 3865 | |
| 3866 | static void |
| 3867 | fetch_core_registers (struct regcache *regcache, |
| 3868 | char *core_reg_sect, unsigned core_reg_size, |
| 3869 | int which, CORE_ADDR reg_addr) |
| 3870 | { |
| 3871 | elf_gregset_t gregset; |
| 3872 | |
| 3873 | switch (which) |
| 3874 | { |
| 3875 | case 0: |
| 3876 | if (core_reg_size != sizeof (elf_gregset_t) |
| 3877 | && core_reg_size != sizeof (crisv32_elf_gregset_t)) |
| 3878 | { |
| 3879 | warning (_("wrong size gregset struct in core file")); |
| 3880 | } |
| 3881 | else |
| 3882 | { |
| 3883 | memcpy (&gregset, core_reg_sect, sizeof (gregset)); |
| 3884 | cris_supply_gregset (regcache, &gregset); |
| 3885 | } |
| 3886 | |
| 3887 | default: |
| 3888 | /* We've covered all the kinds of registers we know about here, |
| 3889 | so this must be something we wouldn't know what to do with |
| 3890 | anyway. Just ignore it. */ |
| 3891 | break; |
| 3892 | } |
| 3893 | } |
| 3894 | |
| 3895 | static struct core_fns cris_elf_core_fns = |
| 3896 | { |
| 3897 | bfd_target_elf_flavour, /* core_flavour */ |
| 3898 | default_check_format, /* check_format */ |
| 3899 | default_core_sniffer, /* core_sniffer */ |
| 3900 | fetch_core_registers, /* core_read_registers */ |
| 3901 | NULL /* next */ |
| 3902 | }; |
| 3903 | |
| 3904 | extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */ |
| 3905 | |
| 3906 | void |
| 3907 | _initialize_cris_tdep (void) |
| 3908 | { |
| 3909 | static struct cmd_list_element *cris_set_cmdlist; |
| 3910 | static struct cmd_list_element *cris_show_cmdlist; |
| 3911 | |
| 3912 | struct cmd_list_element *c; |
| 3913 | |
| 3914 | gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep); |
| 3915 | |
| 3916 | /* CRIS-specific user-commands. */ |
| 3917 | add_setshow_zuinteger_cmd ("cris-version", class_support, |
| 3918 | &usr_cmd_cris_version, |
| 3919 | _("Set the current CRIS version."), |
| 3920 | _("Show the current CRIS version."), |
| 3921 | _("\ |
| 3922 | Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\ |
| 3923 | Defaults to 10. "), |
| 3924 | set_cris_version, |
| 3925 | NULL, /* FIXME: i18n: Current CRIS version |
| 3926 | is %s. */ |
| 3927 | &setlist, &showlist); |
| 3928 | |
| 3929 | add_setshow_enum_cmd ("cris-mode", class_support, |
| 3930 | cris_modes, &usr_cmd_cris_mode, |
| 3931 | _("Set the current CRIS mode."), |
| 3932 | _("Show the current CRIS mode."), |
| 3933 | _("\ |
| 3934 | Set to CRIS_MODE_GURU when debugging in guru mode.\n\ |
| 3935 | Makes GDB use the NRP register instead of the ERP register in certain cases."), |
| 3936 | set_cris_mode, |
| 3937 | NULL, /* FIXME: i18n: Current CRIS version is %s. */ |
| 3938 | &setlist, &showlist); |
| 3939 | |
| 3940 | add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support, |
| 3941 | &usr_cmd_cris_dwarf2_cfi, |
| 3942 | _("Set the usage of Dwarf-2 CFI for CRIS."), |
| 3943 | _("Show the usage of Dwarf-2 CFI for CRIS."), |
| 3944 | _("Set this to \"off\" if using gcc-cris < R59."), |
| 3945 | set_cris_dwarf2_cfi, |
| 3946 | NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI |
| 3947 | for CRIS is %d. */ |
| 3948 | &setlist, &showlist); |
| 3949 | |
| 3950 | deprecated_add_core_fns (&cris_elf_core_fns); |
| 3951 | } |
| 3952 | |
| 3953 | /* Prints out all target specific values. */ |
| 3954 | |
| 3955 | static void |
| 3956 | cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
| 3957 | { |
| 3958 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3959 | if (tdep != NULL) |
| 3960 | { |
| 3961 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n", |
| 3962 | tdep->cris_version); |
| 3963 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n", |
| 3964 | tdep->cris_mode); |
| 3965 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n", |
| 3966 | tdep->cris_dwarf2_cfi); |
| 3967 | } |
| 3968 | } |
| 3969 | |
| 3970 | static void |
| 3971 | set_cris_version (char *ignore_args, int from_tty, |
| 3972 | struct cmd_list_element *c) |
| 3973 | { |
| 3974 | struct gdbarch_info info; |
| 3975 | |
| 3976 | usr_cmd_cris_version_valid = 1; |
| 3977 | |
| 3978 | /* Update the current architecture, if needed. */ |
| 3979 | gdbarch_info_init (&info); |
| 3980 | if (!gdbarch_update_p (info)) |
| 3981 | internal_error (__FILE__, __LINE__, |
| 3982 | _("cris_gdbarch_update: failed to update architecture.")); |
| 3983 | } |
| 3984 | |
| 3985 | static void |
| 3986 | set_cris_mode (char *ignore_args, int from_tty, |
| 3987 | struct cmd_list_element *c) |
| 3988 | { |
| 3989 | struct gdbarch_info info; |
| 3990 | |
| 3991 | /* Update the current architecture, if needed. */ |
| 3992 | gdbarch_info_init (&info); |
| 3993 | if (!gdbarch_update_p (info)) |
| 3994 | internal_error (__FILE__, __LINE__, |
| 3995 | "cris_gdbarch_update: failed to update architecture."); |
| 3996 | } |
| 3997 | |
| 3998 | static void |
| 3999 | set_cris_dwarf2_cfi (char *ignore_args, int from_tty, |
| 4000 | struct cmd_list_element *c) |
| 4001 | { |
| 4002 | struct gdbarch_info info; |
| 4003 | |
| 4004 | /* Update the current architecture, if needed. */ |
| 4005 | gdbarch_info_init (&info); |
| 4006 | if (!gdbarch_update_p (info)) |
| 4007 | internal_error (__FILE__, __LINE__, |
| 4008 | _("cris_gdbarch_update: failed to update architecture.")); |
| 4009 | } |
| 4010 | |
| 4011 | static struct gdbarch * |
| 4012 | cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 4013 | { |
| 4014 | struct gdbarch *gdbarch; |
| 4015 | struct gdbarch_tdep *tdep; |
| 4016 | int cris_version; |
| 4017 | |
| 4018 | if (usr_cmd_cris_version_valid) |
| 4019 | { |
| 4020 | /* Trust the user's CRIS version setting. */ |
| 4021 | cris_version = usr_cmd_cris_version; |
| 4022 | } |
| 4023 | else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32) |
| 4024 | { |
| 4025 | cris_version = 32; |
| 4026 | } |
| 4027 | else |
| 4028 | { |
| 4029 | /* Assume it's CRIS version 10. */ |
| 4030 | cris_version = 10; |
| 4031 | } |
| 4032 | |
| 4033 | /* Make the current settings visible to the user. */ |
| 4034 | usr_cmd_cris_version = cris_version; |
| 4035 | |
| 4036 | /* Find a candidate among the list of pre-declared architectures. */ |
| 4037 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
| 4038 | arches != NULL; |
| 4039 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) |
| 4040 | { |
| 4041 | if ((gdbarch_tdep (arches->gdbarch)->cris_version |
| 4042 | == usr_cmd_cris_version) |
| 4043 | && (gdbarch_tdep (arches->gdbarch)->cris_mode |
| 4044 | == usr_cmd_cris_mode) |
| 4045 | && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi |
| 4046 | == usr_cmd_cris_dwarf2_cfi)) |
| 4047 | return arches->gdbarch; |
| 4048 | } |
| 4049 | |
| 4050 | /* No matching architecture was found. Create a new one. */ |
| 4051 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
| 4052 | gdbarch = gdbarch_alloc (&info, tdep); |
| 4053 | |
| 4054 | tdep->cris_version = usr_cmd_cris_version; |
| 4055 | tdep->cris_mode = usr_cmd_cris_mode; |
| 4056 | tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi; |
| 4057 | |
| 4058 | /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */ |
| 4059 | switch (info.byte_order) |
| 4060 | { |
| 4061 | case BFD_ENDIAN_LITTLE: |
| 4062 | /* Ok. */ |
| 4063 | break; |
| 4064 | |
| 4065 | case BFD_ENDIAN_BIG: |
| 4066 | internal_error (__FILE__, __LINE__, |
| 4067 | _("cris_gdbarch_init: big endian byte order in info")); |
| 4068 | break; |
| 4069 | |
| 4070 | default: |
| 4071 | internal_error (__FILE__, __LINE__, |
| 4072 | _("cris_gdbarch_init: unknown byte order in info")); |
| 4073 | } |
| 4074 | |
| 4075 | set_gdbarch_return_value (gdbarch, cris_return_value); |
| 4076 | |
| 4077 | set_gdbarch_sp_regnum (gdbarch, 14); |
| 4078 | |
| 4079 | /* Length of ordinary registers used in push_word and a few other |
| 4080 | places. register_size() is the real way to know how big a |
| 4081 | register is. */ |
| 4082 | |
| 4083 | set_gdbarch_double_bit (gdbarch, 64); |
| 4084 | /* The default definition of a long double is 2 * gdbarch_double_bit, |
| 4085 | which means we have to set this explicitly. */ |
| 4086 | set_gdbarch_long_double_bit (gdbarch, 64); |
| 4087 | |
| 4088 | /* The total amount of space needed to store (in an array called registers) |
| 4089 | GDB's copy of the machine's register state. Note: We can not use |
| 4090 | cris_register_size at this point, since it relies on gdbarch |
| 4091 | being set. */ |
| 4092 | switch (tdep->cris_version) |
| 4093 | { |
| 4094 | case 0: |
| 4095 | case 1: |
| 4096 | case 2: |
| 4097 | case 3: |
| 4098 | case 8: |
| 4099 | case 9: |
| 4100 | /* Old versions; not supported. */ |
| 4101 | internal_error (__FILE__, __LINE__, |
| 4102 | _("cris_gdbarch_init: unsupported CRIS version")); |
| 4103 | break; |
| 4104 | |
| 4105 | case 10: |
| 4106 | case 11: |
| 4107 | /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100, |
| 4108 | P7 (32 bits), and P15 (32 bits) have been implemented. */ |
| 4109 | set_gdbarch_pc_regnum (gdbarch, 15); |
| 4110 | set_gdbarch_register_type (gdbarch, cris_register_type); |
| 4111 | /* There are 32 registers (some of which may not be implemented). */ |
| 4112 | set_gdbarch_num_regs (gdbarch, 32); |
| 4113 | set_gdbarch_register_name (gdbarch, cris_register_name); |
| 4114 | set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register); |
| 4115 | set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register); |
| 4116 | |
| 4117 | set_gdbarch_software_single_step (gdbarch, cris_software_single_step); |
| 4118 | break; |
| 4119 | |
| 4120 | case 32: |
| 4121 | /* CRIS v32. General registers R0 - R15 (32 bits), special registers |
| 4122 | P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits) |
| 4123 | and pseudo-register PC (32 bits). */ |
| 4124 | set_gdbarch_pc_regnum (gdbarch, 32); |
| 4125 | set_gdbarch_register_type (gdbarch, crisv32_register_type); |
| 4126 | /* 32 registers + pseudo-register PC + 16 support registers. */ |
| 4127 | set_gdbarch_num_regs (gdbarch, 32 + 1 + 16); |
| 4128 | set_gdbarch_register_name (gdbarch, crisv32_register_name); |
| 4129 | |
| 4130 | set_gdbarch_cannot_store_register |
| 4131 | (gdbarch, crisv32_cannot_store_register); |
| 4132 | set_gdbarch_cannot_fetch_register |
| 4133 | (gdbarch, crisv32_cannot_fetch_register); |
| 4134 | |
| 4135 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
| 4136 | |
| 4137 | set_gdbarch_single_step_through_delay |
| 4138 | (gdbarch, crisv32_single_step_through_delay); |
| 4139 | |
| 4140 | break; |
| 4141 | |
| 4142 | default: |
| 4143 | internal_error (__FILE__, __LINE__, |
| 4144 | _("cris_gdbarch_init: unknown CRIS version")); |
| 4145 | } |
| 4146 | |
| 4147 | /* Dummy frame functions (shared between CRISv10 and CRISv32 since they |
| 4148 | have the same ABI). */ |
| 4149 | set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code); |
| 4150 | set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call); |
| 4151 | set_gdbarch_frame_align (gdbarch, cris_frame_align); |
| 4152 | set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue); |
| 4153 | |
| 4154 | /* The stack grows downward. */ |
| 4155 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 4156 | |
| 4157 | set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc); |
| 4158 | |
| 4159 | set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc); |
| 4160 | set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp); |
| 4161 | set_gdbarch_dummy_id (gdbarch, cris_dummy_id); |
| 4162 | |
| 4163 | if (tdep->cris_dwarf2_cfi == 1) |
| 4164 | { |
| 4165 | /* Hook in the Dwarf-2 frame sniffer. */ |
| 4166 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum); |
| 4167 | dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg); |
| 4168 | dwarf2_append_unwinders (gdbarch); |
| 4169 | } |
| 4170 | |
| 4171 | if (tdep->cris_mode != cris_mode_guru) |
| 4172 | { |
| 4173 | frame_unwind_append_unwinder (gdbarch, &cris_sigtramp_frame_unwind); |
| 4174 | } |
| 4175 | |
| 4176 | frame_unwind_append_unwinder (gdbarch, &cris_frame_unwind); |
| 4177 | frame_base_set_default (gdbarch, &cris_frame_base); |
| 4178 | |
| 4179 | set_solib_svr4_fetch_link_map_offsets |
| 4180 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
| 4181 | |
| 4182 | /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS |
| 4183 | disassembler, even when there is no BFD. Does something like |
| 4184 | "gdb; target remote; disassmeble *0x123" work? */ |
| 4185 | set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler); |
| 4186 | |
| 4187 | return gdbarch; |
| 4188 | } |