| 1 | /* GNU/Linux/AArch64 specific low level interface, for the remote server for |
| 2 | GDB. |
| 3 | |
| 4 | Copyright (C) 2009-2015 Free Software Foundation, Inc. |
| 5 | Contributed by ARM Ltd. |
| 6 | |
| 7 | This file is part of GDB. |
| 8 | |
| 9 | This program is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 3 of the License, or |
| 12 | (at your option) any later version. |
| 13 | |
| 14 | This program is distributed in the hope that it will be useful, |
| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License |
| 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 21 | |
| 22 | #include "server.h" |
| 23 | #include "linux-low.h" |
| 24 | #include "elf/common.h" |
| 25 | |
| 26 | #include <signal.h> |
| 27 | #include <sys/user.h> |
| 28 | #include <sys/ptrace.h> |
| 29 | #include <asm/ptrace.h> |
| 30 | #include <sys/uio.h> |
| 31 | |
| 32 | #include "gdb_proc_service.h" |
| 33 | |
| 34 | /* Defined in auto-generated files. */ |
| 35 | void init_registers_aarch64 (void); |
| 36 | extern const struct target_desc *tdesc_aarch64; |
| 37 | |
| 38 | #ifdef HAVE_SYS_REG_H |
| 39 | #include <sys/reg.h> |
| 40 | #endif |
| 41 | |
| 42 | #define AARCH64_X_REGS_NUM 31 |
| 43 | #define AARCH64_V_REGS_NUM 32 |
| 44 | #define AARCH64_X0_REGNO 0 |
| 45 | #define AARCH64_SP_REGNO 31 |
| 46 | #define AARCH64_PC_REGNO 32 |
| 47 | #define AARCH64_CPSR_REGNO 33 |
| 48 | #define AARCH64_V0_REGNO 34 |
| 49 | #define AARCH64_FPSR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM) |
| 50 | #define AARCH64_FPCR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 1) |
| 51 | |
| 52 | #define AARCH64_NUM_REGS (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 2) |
| 53 | |
| 54 | /* Here starts the macro definitions, data structures, and code for |
| 55 | the hardware breakpoint and hardware watchpoint support. The |
| 56 | following is the abbreviations that are used frequently in the code |
| 57 | and comment: |
| 58 | |
| 59 | hw - hardware |
| 60 | bp - breakpoint |
| 61 | wp - watchpoint */ |
| 62 | |
| 63 | /* Maximum number of hardware breakpoint and watchpoint registers. |
| 64 | Neither of these values may exceed the width of dr_changed_t |
| 65 | measured in bits. */ |
| 66 | |
| 67 | #define AARCH64_HBP_MAX_NUM 16 |
| 68 | #define AARCH64_HWP_MAX_NUM 16 |
| 69 | |
| 70 | /* Alignment requirement in bytes of hardware breakpoint and |
| 71 | watchpoint address. This is the requirement for the addresses that |
| 72 | can be written to the hardware breakpoint/watchpoint value |
| 73 | registers. The kernel currently does not do any alignment on |
| 74 | addresses when receiving a writing request (via ptrace call) to |
| 75 | these debug registers, and it will reject any address that is |
| 76 | unaligned. |
| 77 | Some limited support has been provided in this gdbserver port for |
| 78 | unaligned watchpoints, so that from a gdb user point of view, an |
| 79 | unaligned watchpoint can still be set. This is achieved by |
| 80 | minimally enlarging the watched area to meet the alignment |
| 81 | requirement, and if necessary, splitting the watchpoint over |
| 82 | several hardware watchpoint registers. */ |
| 83 | |
| 84 | #define AARCH64_HBP_ALIGNMENT 4 |
| 85 | #define AARCH64_HWP_ALIGNMENT 8 |
| 86 | |
| 87 | /* The maximum length of a memory region that can be watched by one |
| 88 | hardware watchpoint register. */ |
| 89 | |
| 90 | #define AARCH64_HWP_MAX_LEN_PER_REG 8 |
| 91 | |
| 92 | /* Each bit of a variable of this type is used to indicate whether a |
| 93 | hardware breakpoint or watchpoint setting has been changed since |
| 94 | the last updating. Bit N corresponds to the Nth hardware |
| 95 | breakpoint or watchpoint setting which is managed in |
| 96 | aarch64_debug_reg_state. Where N is valid between 0 and the total |
| 97 | number of the hardware breakpoint or watchpoint debug registers |
| 98 | minus 1. When the bit N is 1, it indicates the corresponding |
| 99 | breakpoint or watchpoint setting is changed, and thus the |
| 100 | corresponding hardware debug register needs to be updated via the |
| 101 | ptrace interface. |
| 102 | |
| 103 | In the per-thread arch-specific data area, we define two such |
| 104 | variables for per-thread hardware breakpoint and watchpoint |
| 105 | settings respectively. |
| 106 | |
| 107 | This type is part of the mechanism which helps reduce the number of |
| 108 | ptrace calls to the kernel, i.e. avoid asking the kernel to write |
| 109 | to the debug registers with unchanged values. */ |
| 110 | |
| 111 | typedef unsigned long long dr_changed_t; |
| 112 | |
| 113 | /* Set each of the lower M bits of X to 1; assert X is wide enough. */ |
| 114 | |
| 115 | #define DR_MARK_ALL_CHANGED(x, m) \ |
| 116 | do \ |
| 117 | { \ |
| 118 | gdb_assert (sizeof ((x)) * 8 >= (m)); \ |
| 119 | (x) = (((dr_changed_t)1 << (m)) - 1); \ |
| 120 | } while (0) |
| 121 | |
| 122 | #define DR_MARK_N_CHANGED(x, n) \ |
| 123 | do \ |
| 124 | { \ |
| 125 | (x) |= ((dr_changed_t)1 << (n)); \ |
| 126 | } while (0) |
| 127 | |
| 128 | #define DR_CLEAR_CHANGED(x) \ |
| 129 | do \ |
| 130 | { \ |
| 131 | (x) = 0; \ |
| 132 | } while (0) |
| 133 | |
| 134 | #define DR_HAS_CHANGED(x) ((x) != 0) |
| 135 | #define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n))) |
| 136 | |
| 137 | /* Structure for managing the hardware breakpoint/watchpoint resources. |
| 138 | DR_ADDR_* stores the address, DR_CTRL_* stores the control register |
| 139 | content, and DR_REF_COUNT_* counts the numbers of references to the |
| 140 | corresponding bp/wp, by which way the limited hardware resources |
| 141 | are not wasted on duplicated bp/wp settings (though so far gdb has |
| 142 | done a good job by not sending duplicated bp/wp requests). */ |
| 143 | |
| 144 | struct aarch64_debug_reg_state |
| 145 | { |
| 146 | /* hardware breakpoint */ |
| 147 | CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM]; |
| 148 | unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM]; |
| 149 | unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM]; |
| 150 | |
| 151 | /* hardware watchpoint */ |
| 152 | CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM]; |
| 153 | unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM]; |
| 154 | unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM]; |
| 155 | }; |
| 156 | |
| 157 | /* Per-process arch-specific data we want to keep. */ |
| 158 | |
| 159 | struct arch_process_info |
| 160 | { |
| 161 | /* Hardware breakpoint/watchpoint data. |
| 162 | The reason for them to be per-process rather than per-thread is |
| 163 | due to the lack of information in the gdbserver environment; |
| 164 | gdbserver is not told that whether a requested hardware |
| 165 | breakpoint/watchpoint is thread specific or not, so it has to set |
| 166 | each hw bp/wp for every thread in the current process. The |
| 167 | higher level bp/wp management in gdb will resume a thread if a hw |
| 168 | bp/wp trap is not expected for it. Since the hw bp/wp setting is |
| 169 | same for each thread, it is reasonable for the data to live here. |
| 170 | */ |
| 171 | struct aarch64_debug_reg_state debug_reg_state; |
| 172 | }; |
| 173 | |
| 174 | /* Per-thread arch-specific data we want to keep. */ |
| 175 | |
| 176 | struct arch_lwp_info |
| 177 | { |
| 178 | /* When bit N is 1, it indicates the Nth hardware breakpoint or |
| 179 | watchpoint register pair needs to be updated when the thread is |
| 180 | resumed; see aarch64_linux_prepare_to_resume. */ |
| 181 | dr_changed_t dr_changed_bp; |
| 182 | dr_changed_t dr_changed_wp; |
| 183 | }; |
| 184 | |
| 185 | /* Number of hardware breakpoints/watchpoints the target supports. |
| 186 | They are initialized with values obtained via the ptrace calls |
| 187 | with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */ |
| 188 | |
| 189 | static int aarch64_num_bp_regs; |
| 190 | static int aarch64_num_wp_regs; |
| 191 | |
| 192 | /* Implementation of linux_target_ops method "cannot_store_register". */ |
| 193 | |
| 194 | static int |
| 195 | aarch64_cannot_store_register (int regno) |
| 196 | { |
| 197 | return regno >= AARCH64_NUM_REGS; |
| 198 | } |
| 199 | |
| 200 | /* Implementation of linux_target_ops method "cannot_fetch_register". */ |
| 201 | |
| 202 | static int |
| 203 | aarch64_cannot_fetch_register (int regno) |
| 204 | { |
| 205 | return regno >= AARCH64_NUM_REGS; |
| 206 | } |
| 207 | |
| 208 | static void |
| 209 | aarch64_fill_gregset (struct regcache *regcache, void *buf) |
| 210 | { |
| 211 | struct user_pt_regs *regset = buf; |
| 212 | int i; |
| 213 | |
| 214 | for (i = 0; i < AARCH64_X_REGS_NUM; i++) |
| 215 | collect_register (regcache, AARCH64_X0_REGNO + i, ®set->regs[i]); |
| 216 | collect_register (regcache, AARCH64_SP_REGNO, ®set->sp); |
| 217 | collect_register (regcache, AARCH64_PC_REGNO, ®set->pc); |
| 218 | collect_register (regcache, AARCH64_CPSR_REGNO, ®set->pstate); |
| 219 | } |
| 220 | |
| 221 | static void |
| 222 | aarch64_store_gregset (struct regcache *regcache, const void *buf) |
| 223 | { |
| 224 | const struct user_pt_regs *regset = buf; |
| 225 | int i; |
| 226 | |
| 227 | for (i = 0; i < AARCH64_X_REGS_NUM; i++) |
| 228 | supply_register (regcache, AARCH64_X0_REGNO + i, ®set->regs[i]); |
| 229 | supply_register (regcache, AARCH64_SP_REGNO, ®set->sp); |
| 230 | supply_register (regcache, AARCH64_PC_REGNO, ®set->pc); |
| 231 | supply_register (regcache, AARCH64_CPSR_REGNO, ®set->pstate); |
| 232 | } |
| 233 | |
| 234 | static void |
| 235 | aarch64_fill_fpregset (struct regcache *regcache, void *buf) |
| 236 | { |
| 237 | struct user_fpsimd_state *regset = buf; |
| 238 | int i; |
| 239 | |
| 240 | for (i = 0; i < AARCH64_V_REGS_NUM; i++) |
| 241 | collect_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]); |
| 242 | collect_register (regcache, AARCH64_FPSR_REGNO, ®set->fpsr); |
| 243 | collect_register (regcache, AARCH64_FPCR_REGNO, ®set->fpcr); |
| 244 | } |
| 245 | |
| 246 | static void |
| 247 | aarch64_store_fpregset (struct regcache *regcache, const void *buf) |
| 248 | { |
| 249 | const struct user_fpsimd_state *regset = buf; |
| 250 | int i; |
| 251 | |
| 252 | for (i = 0; i < AARCH64_V_REGS_NUM; i++) |
| 253 | supply_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]); |
| 254 | supply_register (regcache, AARCH64_FPSR_REGNO, ®set->fpsr); |
| 255 | supply_register (regcache, AARCH64_FPCR_REGNO, ®set->fpcr); |
| 256 | } |
| 257 | |
| 258 | /* Enable miscellaneous debugging output. The name is historical - it |
| 259 | was originally used to debug LinuxThreads support. */ |
| 260 | extern int debug_threads; |
| 261 | |
| 262 | /* Implementation of linux_target_ops method "get_pc". */ |
| 263 | |
| 264 | static CORE_ADDR |
| 265 | aarch64_get_pc (struct regcache *regcache) |
| 266 | { |
| 267 | unsigned long pc; |
| 268 | |
| 269 | collect_register_by_name (regcache, "pc", &pc); |
| 270 | if (debug_threads) |
| 271 | debug_printf ("stop pc is %08lx\n", pc); |
| 272 | return pc; |
| 273 | } |
| 274 | |
| 275 | /* Implementation of linux_target_ops method "set_pc". */ |
| 276 | |
| 277 | static void |
| 278 | aarch64_set_pc (struct regcache *regcache, CORE_ADDR pc) |
| 279 | { |
| 280 | unsigned long newpc = pc; |
| 281 | supply_register_by_name (regcache, "pc", &newpc); |
| 282 | } |
| 283 | |
| 284 | #define aarch64_breakpoint_len 4 |
| 285 | |
| 286 | /* AArch64 BRK software debug mode instruction. |
| 287 | This instruction needs to match gdb/aarch64-tdep.c |
| 288 | (aarch64_default_breakpoint). */ |
| 289 | static const gdb_byte aarch64_breakpoint[] = {0x00, 0x00, 0x20, 0xd4}; |
| 290 | |
| 291 | /* Implementation of linux_target_ops method "breakpoint_at". */ |
| 292 | |
| 293 | static int |
| 294 | aarch64_breakpoint_at (CORE_ADDR where) |
| 295 | { |
| 296 | gdb_byte insn[aarch64_breakpoint_len]; |
| 297 | |
| 298 | (*the_target->read_memory) (where, (unsigned char *) &insn, |
| 299 | aarch64_breakpoint_len); |
| 300 | if (memcmp (insn, aarch64_breakpoint, aarch64_breakpoint_len) == 0) |
| 301 | return 1; |
| 302 | |
| 303 | return 0; |
| 304 | } |
| 305 | |
| 306 | /* Print the values of the cached breakpoint/watchpoint registers. |
| 307 | This is enabled via the "set debug-hw-points" monitor command. */ |
| 308 | |
| 309 | static void |
| 310 | aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state, |
| 311 | const char *func, CORE_ADDR addr, |
| 312 | int len, enum target_hw_bp_type type) |
| 313 | { |
| 314 | int i; |
| 315 | |
| 316 | debug_printf ("%s", func); |
| 317 | if (addr || len) |
| 318 | debug_printf (" (addr=0x%08lx, len=%d, type=%s)", |
| 319 | (unsigned long) addr, len, |
| 320 | type == hw_write ? "hw-write-watchpoint" |
| 321 | : (type == hw_read ? "hw-read-watchpoint" |
| 322 | : (type == hw_access ? "hw-access-watchpoint" |
| 323 | : (type == hw_execute ? "hw-breakpoint" |
| 324 | : "??unknown??")))); |
| 325 | debug_printf (":\n"); |
| 326 | |
| 327 | debug_printf ("\tBREAKPOINTs:\n"); |
| 328 | for (i = 0; i < aarch64_num_bp_regs; i++) |
| 329 | debug_printf ("\tBP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n", |
| 330 | i, paddress (state->dr_addr_bp[i]), |
| 331 | state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]); |
| 332 | |
| 333 | debug_printf ("\tWATCHPOINTs:\n"); |
| 334 | for (i = 0; i < aarch64_num_wp_regs; i++) |
| 335 | debug_printf ("\tWP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n", |
| 336 | i, paddress (state->dr_addr_wp[i]), |
| 337 | state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]); |
| 338 | } |
| 339 | |
| 340 | static void |
| 341 | aarch64_init_debug_reg_state (struct aarch64_debug_reg_state *state) |
| 342 | { |
| 343 | int i; |
| 344 | |
| 345 | for (i = 0; i < AARCH64_HBP_MAX_NUM; ++i) |
| 346 | { |
| 347 | state->dr_addr_bp[i] = 0; |
| 348 | state->dr_ctrl_bp[i] = 0; |
| 349 | state->dr_ref_count_bp[i] = 0; |
| 350 | } |
| 351 | |
| 352 | for (i = 0; i < AARCH64_HWP_MAX_NUM; ++i) |
| 353 | { |
| 354 | state->dr_addr_wp[i] = 0; |
| 355 | state->dr_ctrl_wp[i] = 0; |
| 356 | state->dr_ref_count_wp[i] = 0; |
| 357 | } |
| 358 | } |
| 359 | |
| 360 | /* ptrace expects control registers to be formatted as follows: |
| 361 | |
| 362 | 31 13 5 3 1 0 |
| 363 | +--------------------------------+----------+------+------+----+ |
| 364 | | RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN | |
| 365 | +--------------------------------+----------+------+------+----+ |
| 366 | |
| 367 | The TYPE field is ignored for breakpoints. */ |
| 368 | |
| 369 | #define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1) |
| 370 | #define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff) |
| 371 | |
| 372 | /* Utility function that returns the length in bytes of a watchpoint |
| 373 | according to the content of a hardware debug control register CTRL. |
| 374 | Note that the kernel currently only supports the following Byte |
| 375 | Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means |
| 376 | that for a hardware watchpoint, its valid length can only be 1 |
| 377 | byte, 2 bytes, 4 bytes or 8 bytes. */ |
| 378 | |
| 379 | static inline unsigned int |
| 380 | aarch64_watchpoint_length (unsigned int ctrl) |
| 381 | { |
| 382 | switch (DR_CONTROL_LENGTH (ctrl)) |
| 383 | { |
| 384 | case 0x01: |
| 385 | return 1; |
| 386 | case 0x03: |
| 387 | return 2; |
| 388 | case 0x0f: |
| 389 | return 4; |
| 390 | case 0xff: |
| 391 | return 8; |
| 392 | default: |
| 393 | return 0; |
| 394 | } |
| 395 | } |
| 396 | |
| 397 | /* Given the hardware breakpoint or watchpoint type TYPE and its |
| 398 | length LEN, return the expected encoding for a hardware |
| 399 | breakpoint/watchpoint control register. */ |
| 400 | |
| 401 | static unsigned int |
| 402 | aarch64_point_encode_ctrl_reg (enum target_hw_bp_type type, int len) |
| 403 | { |
| 404 | unsigned int ctrl, ttype; |
| 405 | |
| 406 | /* type */ |
| 407 | switch (type) |
| 408 | { |
| 409 | case hw_write: |
| 410 | ttype = 2; |
| 411 | break; |
| 412 | case hw_read: |
| 413 | ttype = 1; |
| 414 | break; |
| 415 | case hw_access: |
| 416 | ttype = 3; |
| 417 | break; |
| 418 | case hw_execute: |
| 419 | ttype = 0; |
| 420 | break; |
| 421 | default: |
| 422 | perror_with_name (_("Unrecognized breakpoint/watchpoint type")); |
| 423 | } |
| 424 | |
| 425 | /* type */ |
| 426 | ctrl = ttype << 3; |
| 427 | /* length bitmask */ |
| 428 | ctrl |= ((1 << len) - 1) << 5; |
| 429 | /* enabled at el0 */ |
| 430 | ctrl |= (2 << 1) | 1; |
| 431 | |
| 432 | return ctrl; |
| 433 | } |
| 434 | |
| 435 | /* Addresses to be written to the hardware breakpoint and watchpoint |
| 436 | value registers need to be aligned; the alignment is 4-byte and |
| 437 | 8-type respectively. Linux kernel rejects any non-aligned address |
| 438 | it receives from the related ptrace call. Furthermore, the kernel |
| 439 | currently only supports the following Byte Address Select (BAS) |
| 440 | values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware |
| 441 | watchpoint to be accepted by the kernel (via ptrace call), its |
| 442 | valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes. |
| 443 | Despite these limitations, the unaligned watchpoint is supported in |
| 444 | this gdbserver port. |
| 445 | |
| 446 | Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */ |
| 447 | |
| 448 | static int |
| 449 | aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len) |
| 450 | { |
| 451 | unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT |
| 452 | : AARCH64_HBP_ALIGNMENT; |
| 453 | |
| 454 | if (addr & (alignment - 1)) |
| 455 | return 0; |
| 456 | |
| 457 | if (len != 8 && len != 4 && len != 2 && len != 1) |
| 458 | return 0; |
| 459 | |
| 460 | return 1; |
| 461 | } |
| 462 | |
| 463 | /* Given the (potentially unaligned) watchpoint address in ADDR and |
| 464 | length in LEN, return the aligned address and aligned length in |
| 465 | *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned |
| 466 | aligned address and length will be valid to be written to the |
| 467 | hardware watchpoint value and control registers. See the comment |
| 468 | above aarch64_point_is_aligned for the information about the |
| 469 | alignment requirement. The given watchpoint may get truncated if |
| 470 | more than one hardware register is needed to cover the watched |
| 471 | region. *NEXT_ADDR_P and *NEXT_LEN_P, if non-NULL, will return the |
| 472 | address and length of the remaining part of the watchpoint (which |
| 473 | can be processed by calling this routine again to generate another |
| 474 | aligned address and length pair. |
| 475 | |
| 476 | Essentially, unaligned watchpoint is achieved by minimally |
| 477 | enlarging the watched area to meet the alignment requirement, and |
| 478 | if necessary, splitting the watchpoint over several hardware |
| 479 | watchpoint registers. The trade-off is that there will be |
| 480 | false-positive hits for the read-type or the access-type hardware |
| 481 | watchpoints; for the write type, which is more commonly used, there |
| 482 | will be no such issues, as the higher-level breakpoint management |
| 483 | in gdb always examines the exact watched region for any content |
| 484 | change, and transparently resumes a thread from a watchpoint trap |
| 485 | if there is no change to the watched region. |
| 486 | |
| 487 | Another limitation is that because the watched region is enlarged, |
| 488 | the watchpoint fault address returned by |
| 489 | aarch64_stopped_data_address may be outside of the original watched |
| 490 | region, especially when the triggering instruction is accessing a |
| 491 | larger region. When the fault address is not within any known |
| 492 | range, watchpoints_triggered in gdb will get confused, as the |
| 493 | higher-level watchpoint management is only aware of original |
| 494 | watched regions, and will think that some unknown watchpoint has |
| 495 | been triggered. In such a case, gdb may stop without displaying |
| 496 | any detailed information. |
| 497 | |
| 498 | Once the kernel provides the full support for Byte Address Select |
| 499 | (BAS) in the hardware watchpoint control register, these |
| 500 | limitations can be largely relaxed with some further work. */ |
| 501 | |
| 502 | static void |
| 503 | aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p, |
| 504 | int *aligned_len_p, CORE_ADDR *next_addr_p, |
| 505 | int *next_len_p) |
| 506 | { |
| 507 | int aligned_len; |
| 508 | unsigned int offset; |
| 509 | CORE_ADDR aligned_addr; |
| 510 | const unsigned int alignment = AARCH64_HWP_ALIGNMENT; |
| 511 | const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG; |
| 512 | |
| 513 | /* As assumed by the algorithm. */ |
| 514 | gdb_assert (alignment == max_wp_len); |
| 515 | |
| 516 | if (len <= 0) |
| 517 | return; |
| 518 | |
| 519 | /* Address to be put into the hardware watchpoint value register |
| 520 | must be aligned. */ |
| 521 | offset = addr & (alignment - 1); |
| 522 | aligned_addr = addr - offset; |
| 523 | |
| 524 | gdb_assert (offset >= 0 && offset < alignment); |
| 525 | gdb_assert (aligned_addr >= 0 && aligned_addr <= addr); |
| 526 | gdb_assert ((offset + len) > 0); |
| 527 | |
| 528 | if (offset + len >= max_wp_len) |
| 529 | { |
| 530 | /* Need more than one watchpoint registers; truncate it at the |
| 531 | alignment boundary. */ |
| 532 | aligned_len = max_wp_len; |
| 533 | len -= (max_wp_len - offset); |
| 534 | addr += (max_wp_len - offset); |
| 535 | gdb_assert ((addr & (alignment - 1)) == 0); |
| 536 | } |
| 537 | else |
| 538 | { |
| 539 | /* Find the smallest valid length that is large enough to |
| 540 | accommodate this watchpoint. */ |
| 541 | static const unsigned char |
| 542 | aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] = |
| 543 | { 1, 2, 4, 4, 8, 8, 8, 8 }; |
| 544 | |
| 545 | aligned_len = aligned_len_array[offset + len - 1]; |
| 546 | addr += len; |
| 547 | len = 0; |
| 548 | } |
| 549 | |
| 550 | if (aligned_addr_p != NULL) |
| 551 | *aligned_addr_p = aligned_addr; |
| 552 | if (aligned_len_p != NULL) |
| 553 | *aligned_len_p = aligned_len; |
| 554 | if (next_addr_p != NULL) |
| 555 | *next_addr_p = addr; |
| 556 | if (next_len_p != NULL) |
| 557 | *next_len_p = len; |
| 558 | } |
| 559 | |
| 560 | /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint |
| 561 | registers with data from *STATE. */ |
| 562 | |
| 563 | static void |
| 564 | aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state, |
| 565 | int tid, int watchpoint) |
| 566 | { |
| 567 | int i, count; |
| 568 | struct iovec iov; |
| 569 | struct user_hwdebug_state regs; |
| 570 | const CORE_ADDR *addr; |
| 571 | const unsigned int *ctrl; |
| 572 | |
| 573 | memset (®s, 0, sizeof (regs)); |
| 574 | iov.iov_base = ®s; |
| 575 | count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs; |
| 576 | addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp; |
| 577 | ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp; |
| 578 | if (count == 0) |
| 579 | return; |
| 580 | iov.iov_len = (offsetof (struct user_hwdebug_state, dbg_regs[count - 1]) |
| 581 | + sizeof (regs.dbg_regs [count - 1])); |
| 582 | |
| 583 | for (i = 0; i < count; i++) |
| 584 | { |
| 585 | regs.dbg_regs[i].addr = addr[i]; |
| 586 | regs.dbg_regs[i].ctrl = ctrl[i]; |
| 587 | } |
| 588 | |
| 589 | if (ptrace (PTRACE_SETREGSET, tid, |
| 590 | watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK, |
| 591 | (void *) &iov)) |
| 592 | error (_("Unexpected error setting hardware debug registers")); |
| 593 | } |
| 594 | |
| 595 | struct aarch64_dr_update_callback_param |
| 596 | { |
| 597 | int pid; |
| 598 | int is_watchpoint; |
| 599 | unsigned int idx; |
| 600 | }; |
| 601 | |
| 602 | /* Callback function which records the information about the change of |
| 603 | one hardware breakpoint/watchpoint setting for the thread ENTRY. |
| 604 | The information is passed in via PTR. |
| 605 | N.B. The actual updating of hardware debug registers is not |
| 606 | carried out until the moment the thread is resumed. */ |
| 607 | |
| 608 | static int |
| 609 | debug_reg_change_callback (struct inferior_list_entry *entry, void *ptr) |
| 610 | { |
| 611 | struct thread_info *thread = (struct thread_info *) entry; |
| 612 | struct lwp_info *lwp = get_thread_lwp (thread); |
| 613 | struct aarch64_dr_update_callback_param *param_p |
| 614 | = (struct aarch64_dr_update_callback_param *) ptr; |
| 615 | int pid = param_p->pid; |
| 616 | int idx = param_p->idx; |
| 617 | int is_watchpoint = param_p->is_watchpoint; |
| 618 | struct arch_lwp_info *info = lwp->arch_private; |
| 619 | dr_changed_t *dr_changed_ptr; |
| 620 | dr_changed_t dr_changed; |
| 621 | |
| 622 | if (show_debug_regs) |
| 623 | { |
| 624 | fprintf (stderr, "debug_reg_change_callback: \n\tOn entry:\n"); |
| 625 | fprintf (stderr, "\tpid%d, tid: %ld, dr_changed_bp=0x%llx, " |
| 626 | "dr_changed_wp=0x%llx\n", |
| 627 | pid, lwpid_of (thread), info->dr_changed_bp, |
| 628 | info->dr_changed_wp); |
| 629 | } |
| 630 | |
| 631 | dr_changed_ptr = is_watchpoint ? &info->dr_changed_wp |
| 632 | : &info->dr_changed_bp; |
| 633 | dr_changed = *dr_changed_ptr; |
| 634 | |
| 635 | /* Only update the threads of this process. */ |
| 636 | if (pid_of (thread) == pid) |
| 637 | { |
| 638 | gdb_assert (idx >= 0 |
| 639 | && (idx <= (is_watchpoint ? aarch64_num_wp_regs |
| 640 | : aarch64_num_bp_regs))); |
| 641 | |
| 642 | /* The following assertion is not right, as there can be changes |
| 643 | that have not been made to the hardware debug registers |
| 644 | before new changes overwrite the old ones. This can happen, |
| 645 | for instance, when the breakpoint/watchpoint hit one of the |
| 646 | threads and the user enters continue; then what happens is: |
| 647 | 1) all breakpoints/watchpoints are removed for all threads; |
| 648 | 2) a single step is carried out for the thread that was hit; |
| 649 | 3) all of the points are inserted again for all threads; |
| 650 | 4) all threads are resumed. |
| 651 | The 2nd step will only affect the one thread in which the |
| 652 | bp/wp was hit, which means only that one thread is resumed; |
| 653 | remember that the actual updating only happen in |
| 654 | aarch64_linux_prepare_to_resume, so other threads remain |
| 655 | stopped during the removal and insertion of bp/wp. Therefore |
| 656 | for those threads, the change of insertion of the bp/wp |
| 657 | overwrites that of the earlier removals. (The situation may |
| 658 | be different when bp/wp is steppable, or in the non-stop |
| 659 | mode.) */ |
| 660 | /* gdb_assert (DR_N_HAS_CHANGED (dr_changed, idx) == 0); */ |
| 661 | |
| 662 | /* The actual update is done later just before resuming the lwp, |
| 663 | we just mark that one register pair needs updating. */ |
| 664 | DR_MARK_N_CHANGED (dr_changed, idx); |
| 665 | *dr_changed_ptr = dr_changed; |
| 666 | |
| 667 | /* If the lwp isn't stopped, force it to momentarily pause, so |
| 668 | we can update its debug registers. */ |
| 669 | if (!lwp->stopped) |
| 670 | linux_stop_lwp (lwp); |
| 671 | } |
| 672 | |
| 673 | if (show_debug_regs) |
| 674 | { |
| 675 | fprintf (stderr, "\tOn exit:\n\tpid%d, tid: %ld, dr_changed_bp=0x%llx, " |
| 676 | "dr_changed_wp=0x%llx\n", |
| 677 | pid, lwpid_of (thread), info->dr_changed_bp, |
| 678 | info->dr_changed_wp); |
| 679 | } |
| 680 | |
| 681 | return 0; |
| 682 | } |
| 683 | |
| 684 | /* Notify each thread that their IDXth breakpoint/watchpoint register |
| 685 | pair needs to be updated. The message will be recorded in each |
| 686 | thread's arch-specific data area, the actual updating will be done |
| 687 | when the thread is resumed. */ |
| 688 | |
| 689 | void |
| 690 | aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state *state, |
| 691 | int is_watchpoint, unsigned int idx) |
| 692 | { |
| 693 | struct aarch64_dr_update_callback_param param; |
| 694 | |
| 695 | /* Only update the threads of this process. */ |
| 696 | param.pid = pid_of (current_thread); |
| 697 | |
| 698 | param.is_watchpoint = is_watchpoint; |
| 699 | param.idx = idx; |
| 700 | |
| 701 | find_inferior (&all_threads, debug_reg_change_callback, (void *) ¶m); |
| 702 | } |
| 703 | |
| 704 | |
| 705 | /* Return the pointer to the debug register state structure in the |
| 706 | current process' arch-specific data area. */ |
| 707 | |
| 708 | static struct aarch64_debug_reg_state * |
| 709 | aarch64_get_debug_reg_state () |
| 710 | { |
| 711 | struct process_info *proc; |
| 712 | |
| 713 | proc = current_process (); |
| 714 | return &proc->priv->arch_private->debug_reg_state; |
| 715 | } |
| 716 | |
| 717 | /* Record the insertion of one breakpoint/watchpoint, as represented |
| 718 | by ADDR and CTRL, in the process' arch-specific data area *STATE. */ |
| 719 | |
| 720 | static int |
| 721 | aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state, |
| 722 | enum target_hw_bp_type type, |
| 723 | CORE_ADDR addr, int len) |
| 724 | { |
| 725 | int i, idx, num_regs, is_watchpoint; |
| 726 | unsigned int ctrl, *dr_ctrl_p, *dr_ref_count; |
| 727 | CORE_ADDR *dr_addr_p; |
| 728 | |
| 729 | /* Set up state pointers. */ |
| 730 | is_watchpoint = (type != hw_execute); |
| 731 | gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len)); |
| 732 | if (is_watchpoint) |
| 733 | { |
| 734 | num_regs = aarch64_num_wp_regs; |
| 735 | dr_addr_p = state->dr_addr_wp; |
| 736 | dr_ctrl_p = state->dr_ctrl_wp; |
| 737 | dr_ref_count = state->dr_ref_count_wp; |
| 738 | } |
| 739 | else |
| 740 | { |
| 741 | num_regs = aarch64_num_bp_regs; |
| 742 | dr_addr_p = state->dr_addr_bp; |
| 743 | dr_ctrl_p = state->dr_ctrl_bp; |
| 744 | dr_ref_count = state->dr_ref_count_bp; |
| 745 | } |
| 746 | |
| 747 | ctrl = aarch64_point_encode_ctrl_reg (type, len); |
| 748 | |
| 749 | /* Find an existing or free register in our cache. */ |
| 750 | idx = -1; |
| 751 | for (i = 0; i < num_regs; ++i) |
| 752 | { |
| 753 | if ((dr_ctrl_p[i] & 1) == 0) |
| 754 | { |
| 755 | gdb_assert (dr_ref_count[i] == 0); |
| 756 | idx = i; |
| 757 | /* no break; continue hunting for an exising one. */ |
| 758 | } |
| 759 | else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl) |
| 760 | { |
| 761 | gdb_assert (dr_ref_count[i] != 0); |
| 762 | idx = i; |
| 763 | break; |
| 764 | } |
| 765 | } |
| 766 | |
| 767 | /* No space. */ |
| 768 | if (idx == -1) |
| 769 | return -1; |
| 770 | |
| 771 | /* Update our cache. */ |
| 772 | if ((dr_ctrl_p[idx] & 1) == 0) |
| 773 | { |
| 774 | /* new entry */ |
| 775 | dr_addr_p[idx] = addr; |
| 776 | dr_ctrl_p[idx] = ctrl; |
| 777 | dr_ref_count[idx] = 1; |
| 778 | /* Notify the change. */ |
| 779 | aarch64_notify_debug_reg_change (state, is_watchpoint, idx); |
| 780 | } |
| 781 | else |
| 782 | { |
| 783 | /* existing entry */ |
| 784 | dr_ref_count[idx]++; |
| 785 | } |
| 786 | |
| 787 | return 0; |
| 788 | } |
| 789 | |
| 790 | /* Record the removal of one breakpoint/watchpoint, as represented by |
| 791 | ADDR and CTRL, in the process' arch-specific data area *STATE. */ |
| 792 | |
| 793 | static int |
| 794 | aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state, |
| 795 | enum target_hw_bp_type type, |
| 796 | CORE_ADDR addr, int len) |
| 797 | { |
| 798 | int i, num_regs, is_watchpoint; |
| 799 | unsigned int ctrl, *dr_ctrl_p, *dr_ref_count; |
| 800 | CORE_ADDR *dr_addr_p; |
| 801 | |
| 802 | /* Set up state pointers. */ |
| 803 | is_watchpoint = (type != hw_execute); |
| 804 | gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len)); |
| 805 | if (is_watchpoint) |
| 806 | { |
| 807 | num_regs = aarch64_num_wp_regs; |
| 808 | dr_addr_p = state->dr_addr_wp; |
| 809 | dr_ctrl_p = state->dr_ctrl_wp; |
| 810 | dr_ref_count = state->dr_ref_count_wp; |
| 811 | } |
| 812 | else |
| 813 | { |
| 814 | num_regs = aarch64_num_bp_regs; |
| 815 | dr_addr_p = state->dr_addr_bp; |
| 816 | dr_ctrl_p = state->dr_ctrl_bp; |
| 817 | dr_ref_count = state->dr_ref_count_bp; |
| 818 | } |
| 819 | |
| 820 | ctrl = aarch64_point_encode_ctrl_reg (type, len); |
| 821 | |
| 822 | /* Find the entry that matches the ADDR and CTRL. */ |
| 823 | for (i = 0; i < num_regs; ++i) |
| 824 | if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl) |
| 825 | { |
| 826 | gdb_assert (dr_ref_count[i] != 0); |
| 827 | break; |
| 828 | } |
| 829 | |
| 830 | /* Not found. */ |
| 831 | if (i == num_regs) |
| 832 | return -1; |
| 833 | |
| 834 | /* Clear our cache. */ |
| 835 | if (--dr_ref_count[i] == 0) |
| 836 | { |
| 837 | /* Clear the enable bit. */ |
| 838 | ctrl &= ~1; |
| 839 | dr_addr_p[i] = 0; |
| 840 | dr_ctrl_p[i] = ctrl; |
| 841 | /* Notify the change. */ |
| 842 | aarch64_notify_debug_reg_change (state, is_watchpoint, i); |
| 843 | } |
| 844 | |
| 845 | return 0; |
| 846 | } |
| 847 | |
| 848 | static int |
| 849 | aarch64_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr, |
| 850 | int len, int is_insert, |
| 851 | struct aarch64_debug_reg_state *state) |
| 852 | { |
| 853 | /* The hardware breakpoint on AArch64 should always be 4-byte |
| 854 | aligned. */ |
| 855 | if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len)) |
| 856 | return -1; |
| 857 | |
| 858 | if (is_insert) |
| 859 | return aarch64_dr_state_insert_one_point (state, type, addr, len); |
| 860 | else |
| 861 | return aarch64_dr_state_remove_one_point (state, type, addr, len); |
| 862 | } |
| 863 | |
| 864 | /* This is essentially the same as aarch64_handle_breakpoint, apart |
| 865 | from that it is an aligned watchpoint to be handled. */ |
| 866 | |
| 867 | static int |
| 868 | aarch64_handle_aligned_watchpoint (enum target_hw_bp_type type, |
| 869 | CORE_ADDR addr, int len, int is_insert, |
| 870 | struct aarch64_debug_reg_state *state) |
| 871 | { |
| 872 | if (is_insert) |
| 873 | return aarch64_dr_state_insert_one_point (state, type, addr, len); |
| 874 | else |
| 875 | return aarch64_dr_state_remove_one_point (state, type, addr, len); |
| 876 | } |
| 877 | |
| 878 | /* Insert/remove unaligned watchpoint by calling |
| 879 | aarch64_align_watchpoint repeatedly until the whole watched region, |
| 880 | as represented by ADDR and LEN, has been properly aligned and ready |
| 881 | to be written to one or more hardware watchpoint registers. |
| 882 | IS_INSERT indicates whether this is an insertion or a deletion. |
| 883 | Return 0 if succeed. */ |
| 884 | |
| 885 | static int |
| 886 | aarch64_handle_unaligned_watchpoint (enum target_hw_bp_type type, |
| 887 | CORE_ADDR addr, int len, int is_insert, |
| 888 | struct aarch64_debug_reg_state *state) |
| 889 | { |
| 890 | while (len > 0) |
| 891 | { |
| 892 | CORE_ADDR aligned_addr; |
| 893 | int aligned_len, ret; |
| 894 | |
| 895 | aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len, |
| 896 | &addr, &len); |
| 897 | |
| 898 | if (is_insert) |
| 899 | ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr, |
| 900 | aligned_len); |
| 901 | else |
| 902 | ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr, |
| 903 | aligned_len); |
| 904 | |
| 905 | if (show_debug_regs) |
| 906 | debug_printf ( |
| 907 | "handle_unaligned_watchpoint: is_insert: %d\n" |
| 908 | " aligned_addr: 0x%s, aligned_len: %d\n" |
| 909 | " next_addr: 0x%s, next_len: %d\n", |
| 910 | is_insert, paddress (aligned_addr), aligned_len, |
| 911 | paddress (addr), len); |
| 912 | |
| 913 | if (ret != 0) |
| 914 | return ret; |
| 915 | } |
| 916 | |
| 917 | return 0; |
| 918 | } |
| 919 | |
| 920 | static int |
| 921 | aarch64_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr, |
| 922 | int len, int is_insert, |
| 923 | struct aarch64_debug_reg_state *state) |
| 924 | { |
| 925 | if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len)) |
| 926 | return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert, |
| 927 | state); |
| 928 | else |
| 929 | return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert, |
| 930 | state); |
| 931 | } |
| 932 | |
| 933 | /* Implementation of linux_target_ops method "supports_z_point_type". */ |
| 934 | |
| 935 | static int |
| 936 | aarch64_supports_z_point_type (char z_type) |
| 937 | { |
| 938 | switch (z_type) |
| 939 | { |
| 940 | case Z_PACKET_SW_BP: |
| 941 | case Z_PACKET_HW_BP: |
| 942 | case Z_PACKET_WRITE_WP: |
| 943 | case Z_PACKET_READ_WP: |
| 944 | case Z_PACKET_ACCESS_WP: |
| 945 | return 1; |
| 946 | default: |
| 947 | return 0; |
| 948 | } |
| 949 | } |
| 950 | |
| 951 | /* Implementation of linux_target_ops method "insert_point". |
| 952 | |
| 953 | It actually only records the info of the to-be-inserted bp/wp; |
| 954 | the actual insertion will happen when threads are resumed. */ |
| 955 | |
| 956 | static int |
| 957 | aarch64_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, |
| 958 | int len, struct raw_breakpoint *bp) |
| 959 | { |
| 960 | int ret; |
| 961 | enum target_hw_bp_type targ_type; |
| 962 | struct aarch64_debug_reg_state *state = aarch64_get_debug_reg_state (); |
| 963 | |
| 964 | if (show_debug_regs) |
| 965 | fprintf (stderr, "insert_point on entry (addr=0x%08lx, len=%d)\n", |
| 966 | (unsigned long) addr, len); |
| 967 | |
| 968 | /* Determine the type from the raw breakpoint type. */ |
| 969 | targ_type = raw_bkpt_type_to_target_hw_bp_type (type); |
| 970 | |
| 971 | if (targ_type != hw_execute) |
| 972 | ret = |
| 973 | aarch64_handle_watchpoint (targ_type, addr, len, 1 /* is_insert */, |
| 974 | state); |
| 975 | else |
| 976 | ret = |
| 977 | aarch64_handle_breakpoint (targ_type, addr, len, 1 /* is_insert */, |
| 978 | state); |
| 979 | |
| 980 | if (show_debug_regs) |
| 981 | aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (), |
| 982 | "insert_point", addr, len, targ_type); |
| 983 | |
| 984 | return ret; |
| 985 | } |
| 986 | |
| 987 | /* Implementation of linux_target_ops method "remove_point". |
| 988 | |
| 989 | It actually only records the info of the to-be-removed bp/wp, |
| 990 | the actual removal will be done when threads are resumed. */ |
| 991 | |
| 992 | static int |
| 993 | aarch64_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, |
| 994 | int len, struct raw_breakpoint *bp) |
| 995 | { |
| 996 | int ret; |
| 997 | enum target_hw_bp_type targ_type; |
| 998 | struct aarch64_debug_reg_state *state = aarch64_get_debug_reg_state (); |
| 999 | |
| 1000 | if (show_debug_regs) |
| 1001 | fprintf (stderr, "remove_point on entry (addr=0x%08lx, len=%d)\n", |
| 1002 | (unsigned long) addr, len); |
| 1003 | |
| 1004 | /* Determine the type from the raw breakpoint type. */ |
| 1005 | targ_type = raw_bkpt_type_to_target_hw_bp_type (type); |
| 1006 | |
| 1007 | /* Set up state pointers. */ |
| 1008 | if (targ_type != hw_execute) |
| 1009 | ret = |
| 1010 | aarch64_handle_watchpoint (targ_type, addr, len, 0 /* is_insert */, |
| 1011 | state); |
| 1012 | else |
| 1013 | ret = |
| 1014 | aarch64_handle_breakpoint (targ_type, addr, len, 0 /* is_insert */, |
| 1015 | state); |
| 1016 | |
| 1017 | if (show_debug_regs) |
| 1018 | aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (), |
| 1019 | "remove_point", addr, len, targ_type); |
| 1020 | |
| 1021 | return ret; |
| 1022 | } |
| 1023 | |
| 1024 | /* Implementation of linux_target_ops method "stopped_data_address". */ |
| 1025 | |
| 1026 | static CORE_ADDR |
| 1027 | aarch64_stopped_data_address (void) |
| 1028 | { |
| 1029 | siginfo_t siginfo; |
| 1030 | int pid, i; |
| 1031 | struct aarch64_debug_reg_state *state; |
| 1032 | |
| 1033 | pid = lwpid_of (current_thread); |
| 1034 | |
| 1035 | /* Get the siginfo. */ |
| 1036 | if (ptrace (PTRACE_GETSIGINFO, pid, NULL, &siginfo) != 0) |
| 1037 | return (CORE_ADDR) 0; |
| 1038 | |
| 1039 | /* Need to be a hardware breakpoint/watchpoint trap. */ |
| 1040 | if (siginfo.si_signo != SIGTRAP |
| 1041 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) |
| 1042 | return (CORE_ADDR) 0; |
| 1043 | |
| 1044 | /* Check if the address matches any watched address. */ |
| 1045 | state = aarch64_get_debug_reg_state (); |
| 1046 | for (i = aarch64_num_wp_regs - 1; i >= 0; --i) |
| 1047 | { |
| 1048 | const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]); |
| 1049 | const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr; |
| 1050 | const CORE_ADDR addr_watch = state->dr_addr_wp[i]; |
| 1051 | if (state->dr_ref_count_wp[i] |
| 1052 | && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i]) |
| 1053 | && addr_trap >= addr_watch |
| 1054 | && addr_trap < addr_watch + len) |
| 1055 | return addr_trap; |
| 1056 | } |
| 1057 | |
| 1058 | return (CORE_ADDR) 0; |
| 1059 | } |
| 1060 | |
| 1061 | /* Implementation of linux_target_ops method "stopped_by_watchpoint". */ |
| 1062 | |
| 1063 | static int |
| 1064 | aarch64_stopped_by_watchpoint (void) |
| 1065 | { |
| 1066 | if (aarch64_stopped_data_address () != 0) |
| 1067 | return 1; |
| 1068 | else |
| 1069 | return 0; |
| 1070 | } |
| 1071 | |
| 1072 | /* Fetch the thread-local storage pointer for libthread_db. */ |
| 1073 | |
| 1074 | ps_err_e |
| 1075 | ps_get_thread_area (const struct ps_prochandle *ph, |
| 1076 | lwpid_t lwpid, int idx, void **base) |
| 1077 | { |
| 1078 | struct iovec iovec; |
| 1079 | uint64_t reg; |
| 1080 | |
| 1081 | iovec.iov_base = ® |
| 1082 | iovec.iov_len = sizeof (reg); |
| 1083 | |
| 1084 | if (ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec) != 0) |
| 1085 | return PS_ERR; |
| 1086 | |
| 1087 | /* IDX is the bias from the thread pointer to the beginning of the |
| 1088 | thread descriptor. It has to be subtracted due to implementation |
| 1089 | quirks in libthread_db. */ |
| 1090 | *base = (void *) (reg - idx); |
| 1091 | |
| 1092 | return PS_OK; |
| 1093 | } |
| 1094 | |
| 1095 | /* Implementation of linux_target_ops method "linux_new_process". */ |
| 1096 | |
| 1097 | static struct arch_process_info * |
| 1098 | aarch64_linux_new_process (void) |
| 1099 | { |
| 1100 | struct arch_process_info *info = xcalloc (1, sizeof (*info)); |
| 1101 | |
| 1102 | aarch64_init_debug_reg_state (&info->debug_reg_state); |
| 1103 | |
| 1104 | return info; |
| 1105 | } |
| 1106 | |
| 1107 | /* Implementation of linux_target_ops method "linux_new_thread". */ |
| 1108 | |
| 1109 | static void |
| 1110 | aarch64_linux_new_thread (struct lwp_info *lwp) |
| 1111 | { |
| 1112 | struct arch_lwp_info *info = xcalloc (1, sizeof (*info)); |
| 1113 | |
| 1114 | /* Mark that all the hardware breakpoint/watchpoint register pairs |
| 1115 | for this thread need to be initialized (with data from |
| 1116 | aarch_process_info.debug_reg_state). */ |
| 1117 | DR_MARK_ALL_CHANGED (info->dr_changed_bp, aarch64_num_bp_regs); |
| 1118 | DR_MARK_ALL_CHANGED (info->dr_changed_wp, aarch64_num_wp_regs); |
| 1119 | |
| 1120 | lwp->arch_private = info; |
| 1121 | } |
| 1122 | |
| 1123 | /* Implementation of linux_target_ops method "linux_new_fork". */ |
| 1124 | |
| 1125 | static void |
| 1126 | aarch64_linux_new_fork (struct process_info *parent, |
| 1127 | struct process_info *child) |
| 1128 | { |
| 1129 | /* These are allocated by linux_add_process. */ |
| 1130 | gdb_assert (parent->priv != NULL |
| 1131 | && parent->priv->arch_private != NULL); |
| 1132 | gdb_assert (child->priv != NULL |
| 1133 | && child->priv->arch_private != NULL); |
| 1134 | |
| 1135 | /* Linux kernel before 2.6.33 commit |
| 1136 | 72f674d203cd230426437cdcf7dd6f681dad8b0d |
| 1137 | will inherit hardware debug registers from parent |
| 1138 | on fork/vfork/clone. Newer Linux kernels create such tasks with |
| 1139 | zeroed debug registers. |
| 1140 | |
| 1141 | GDB core assumes the child inherits the watchpoints/hw |
| 1142 | breakpoints of the parent, and will remove them all from the |
| 1143 | forked off process. Copy the debug registers mirrors into the |
| 1144 | new process so that all breakpoints and watchpoints can be |
| 1145 | removed together. The debug registers mirror will become zeroed |
| 1146 | in the end before detaching the forked off process, thus making |
| 1147 | this compatible with older Linux kernels too. */ |
| 1148 | |
| 1149 | *child->priv->arch_private = *parent->priv->arch_private; |
| 1150 | } |
| 1151 | |
| 1152 | /* Implementation of linux_target_ops method "linux_prepare_to_resume". |
| 1153 | |
| 1154 | If the debug regs have changed, update the thread's copies. */ |
| 1155 | |
| 1156 | static void |
| 1157 | aarch64_linux_prepare_to_resume (struct lwp_info *lwp) |
| 1158 | { |
| 1159 | struct thread_info *thread = get_lwp_thread (lwp); |
| 1160 | ptid_t ptid = ptid_of (thread); |
| 1161 | struct arch_lwp_info *info = lwp->arch_private; |
| 1162 | |
| 1163 | if (DR_HAS_CHANGED (info->dr_changed_bp) |
| 1164 | || DR_HAS_CHANGED (info->dr_changed_wp)) |
| 1165 | { |
| 1166 | int tid = ptid_get_lwp (ptid); |
| 1167 | struct process_info *proc = find_process_pid (ptid_get_pid (ptid)); |
| 1168 | struct aarch64_debug_reg_state *state |
| 1169 | = &proc->priv->arch_private->debug_reg_state; |
| 1170 | |
| 1171 | if (show_debug_regs) |
| 1172 | fprintf (stderr, "prepare_to_resume thread %ld\n", lwpid_of (thread)); |
| 1173 | |
| 1174 | /* Watchpoints. */ |
| 1175 | if (DR_HAS_CHANGED (info->dr_changed_wp)) |
| 1176 | { |
| 1177 | aarch64_linux_set_debug_regs (state, tid, 1); |
| 1178 | DR_CLEAR_CHANGED (info->dr_changed_wp); |
| 1179 | } |
| 1180 | |
| 1181 | /* Breakpoints. */ |
| 1182 | if (DR_HAS_CHANGED (info->dr_changed_bp)) |
| 1183 | { |
| 1184 | aarch64_linux_set_debug_regs (state, tid, 0); |
| 1185 | DR_CLEAR_CHANGED (info->dr_changed_bp); |
| 1186 | } |
| 1187 | } |
| 1188 | } |
| 1189 | |
| 1190 | /* ptrace hardware breakpoint resource info is formatted as follows: |
| 1191 | |
| 1192 | 31 24 16 8 0 |
| 1193 | +---------------+--------------+---------------+---------------+ |
| 1194 | | RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS | |
| 1195 | +---------------+--------------+---------------+---------------+ */ |
| 1196 | |
| 1197 | #define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff) |
| 1198 | #define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff) |
| 1199 | #define AARCH64_DEBUG_ARCH_V8 0x6 |
| 1200 | |
| 1201 | /* Implementation of linux_target_ops method "arch_setup". */ |
| 1202 | |
| 1203 | static void |
| 1204 | aarch64_arch_setup (void) |
| 1205 | { |
| 1206 | int pid; |
| 1207 | struct iovec iov; |
| 1208 | struct user_hwdebug_state dreg_state; |
| 1209 | |
| 1210 | current_process ()->tdesc = tdesc_aarch64; |
| 1211 | |
| 1212 | pid = lwpid_of (current_thread); |
| 1213 | iov.iov_base = &dreg_state; |
| 1214 | iov.iov_len = sizeof (dreg_state); |
| 1215 | |
| 1216 | /* Get hardware watchpoint register info. */ |
| 1217 | if (ptrace (PTRACE_GETREGSET, pid, NT_ARM_HW_WATCH, &iov) == 0 |
| 1218 | && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8) |
| 1219 | { |
| 1220 | aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info); |
| 1221 | if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM) |
| 1222 | { |
| 1223 | warning ("Unexpected number of hardware watchpoint registers reported" |
| 1224 | " by ptrace, got %d, expected %d.", |
| 1225 | aarch64_num_wp_regs, AARCH64_HWP_MAX_NUM); |
| 1226 | aarch64_num_wp_regs = AARCH64_HWP_MAX_NUM; |
| 1227 | } |
| 1228 | } |
| 1229 | else |
| 1230 | { |
| 1231 | warning ("Unable to determine the number of hardware watchpoints" |
| 1232 | " available."); |
| 1233 | aarch64_num_wp_regs = 0; |
| 1234 | } |
| 1235 | |
| 1236 | /* Get hardware breakpoint register info. */ |
| 1237 | if (ptrace (PTRACE_GETREGSET, pid, NT_ARM_HW_BREAK, &iov) == 0 |
| 1238 | && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8) |
| 1239 | { |
| 1240 | aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info); |
| 1241 | if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM) |
| 1242 | { |
| 1243 | warning ("Unexpected number of hardware breakpoint registers reported" |
| 1244 | " by ptrace, got %d, expected %d.", |
| 1245 | aarch64_num_bp_regs, AARCH64_HBP_MAX_NUM); |
| 1246 | aarch64_num_bp_regs = AARCH64_HBP_MAX_NUM; |
| 1247 | } |
| 1248 | } |
| 1249 | else |
| 1250 | { |
| 1251 | warning ("Unable to determine the number of hardware breakpoints" |
| 1252 | " available."); |
| 1253 | aarch64_num_bp_regs = 0; |
| 1254 | } |
| 1255 | } |
| 1256 | |
| 1257 | static struct regset_info aarch64_regsets[] = |
| 1258 | { |
| 1259 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS, |
| 1260 | sizeof (struct user_pt_regs), GENERAL_REGS, |
| 1261 | aarch64_fill_gregset, aarch64_store_gregset }, |
| 1262 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET, |
| 1263 | sizeof (struct user_fpsimd_state), FP_REGS, |
| 1264 | aarch64_fill_fpregset, aarch64_store_fpregset |
| 1265 | }, |
| 1266 | { 0, 0, 0, -1, -1, NULL, NULL } |
| 1267 | }; |
| 1268 | |
| 1269 | static struct regsets_info aarch64_regsets_info = |
| 1270 | { |
| 1271 | aarch64_regsets, /* regsets */ |
| 1272 | 0, /* num_regsets */ |
| 1273 | NULL, /* disabled_regsets */ |
| 1274 | }; |
| 1275 | |
| 1276 | static struct regs_info regs_info = |
| 1277 | { |
| 1278 | NULL, /* regset_bitmap */ |
| 1279 | NULL, /* usrregs */ |
| 1280 | &aarch64_regsets_info, |
| 1281 | }; |
| 1282 | |
| 1283 | /* Implementation of linux_target_ops method "regs_info". */ |
| 1284 | |
| 1285 | static const struct regs_info * |
| 1286 | aarch64_regs_info (void) |
| 1287 | { |
| 1288 | return ®s_info; |
| 1289 | } |
| 1290 | |
| 1291 | /* Implementation of linux_target_ops method "supports_tracepoints". */ |
| 1292 | |
| 1293 | static int |
| 1294 | aarch64_supports_tracepoints (void) |
| 1295 | { |
| 1296 | return 1; |
| 1297 | } |
| 1298 | |
| 1299 | /* Implementation of linux_target_ops method "supports_range_stepping". */ |
| 1300 | |
| 1301 | static int |
| 1302 | aarch64_supports_range_stepping (void) |
| 1303 | { |
| 1304 | return 1; |
| 1305 | } |
| 1306 | |
| 1307 | struct linux_target_ops the_low_target = |
| 1308 | { |
| 1309 | aarch64_arch_setup, |
| 1310 | aarch64_regs_info, |
| 1311 | aarch64_cannot_fetch_register, |
| 1312 | aarch64_cannot_store_register, |
| 1313 | NULL, /* fetch_register */ |
| 1314 | aarch64_get_pc, |
| 1315 | aarch64_set_pc, |
| 1316 | (const unsigned char *) &aarch64_breakpoint, |
| 1317 | aarch64_breakpoint_len, |
| 1318 | NULL, /* breakpoint_reinsert_addr */ |
| 1319 | 0, /* decr_pc_after_break */ |
| 1320 | aarch64_breakpoint_at, |
| 1321 | aarch64_supports_z_point_type, |
| 1322 | aarch64_insert_point, |
| 1323 | aarch64_remove_point, |
| 1324 | aarch64_stopped_by_watchpoint, |
| 1325 | aarch64_stopped_data_address, |
| 1326 | NULL, /* collect_ptrace_register */ |
| 1327 | NULL, /* supply_ptrace_register */ |
| 1328 | NULL, /* siginfo_fixup */ |
| 1329 | aarch64_linux_new_process, |
| 1330 | aarch64_linux_new_thread, |
| 1331 | aarch64_linux_new_fork, |
| 1332 | aarch64_linux_prepare_to_resume, |
| 1333 | NULL, /* process_qsupported */ |
| 1334 | aarch64_supports_tracepoints, |
| 1335 | NULL, /* get_thread_area */ |
| 1336 | NULL, /* install_fast_tracepoint_jump_pad */ |
| 1337 | NULL, /* emit_ops */ |
| 1338 | NULL, /* get_min_fast_tracepoint_insn_len */ |
| 1339 | aarch64_supports_range_stepping, |
| 1340 | }; |
| 1341 | |
| 1342 | void |
| 1343 | initialize_low_arch (void) |
| 1344 | { |
| 1345 | init_registers_aarch64 (); |
| 1346 | |
| 1347 | initialize_regsets_info (&aarch64_regsets_info); |
| 1348 | } |