| 1 | /* GNU/Linux/CRIS specific low level interface, for the remote server for GDB. |
| 2 | Copyright (C) 1995-2013 Free Software Foundation, Inc. |
| 3 | |
| 4 | This file is part of GDB. |
| 5 | |
| 6 | This program is free software; you can redistribute it and/or modify |
| 7 | it under the terms of the GNU General Public License as published by |
| 8 | the Free Software Foundation; either version 3 of the License, or |
| 9 | (at your option) any later version. |
| 10 | |
| 11 | This program is distributed in the hope that it will be useful, |
| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | GNU General Public License for more details. |
| 15 | |
| 16 | You should have received a copy of the GNU General Public License |
| 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 18 | |
| 19 | #include "server.h" |
| 20 | #include "linux-low.h" |
| 21 | #include <sys/ptrace.h> |
| 22 | |
| 23 | /* Defined in auto-generated file reg-crisv32.c. */ |
| 24 | void init_registers_crisv32 (void); |
| 25 | |
| 26 | /* CRISv32 */ |
| 27 | #define cris_num_regs 49 |
| 28 | |
| 29 | /* Note: Ignoring USP (having the stack pointer in two locations causes trouble |
| 30 | without any significant gain). */ |
| 31 | |
| 32 | /* Locations need to match <include/asm/arch/ptrace.h>. */ |
| 33 | static int cris_regmap[] = { |
| 34 | 1*4, 2*4, 3*4, 4*4, |
| 35 | 5*4, 6*4, 7*4, 8*4, |
| 36 | 9*4, 10*4, 11*4, 12*4, |
| 37 | 13*4, 14*4, 24*4, 15*4, |
| 38 | |
| 39 | -1, -1, -1, 16*4, |
| 40 | -1, 22*4, 23*4, 17*4, |
| 41 | -1, -1, 21*4, 20*4, |
| 42 | -1, 19*4, -1, 18*4, |
| 43 | |
| 44 | 25*4, |
| 45 | |
| 46 | 26*4, -1, -1, 29*4, |
| 47 | 30*4, 31*4, 32*4, 33*4, |
| 48 | 34*4, 35*4, 36*4, 37*4, |
| 49 | 38*4, 39*4, 40*4, -1 |
| 50 | |
| 51 | }; |
| 52 | |
| 53 | extern int debug_threads; |
| 54 | |
| 55 | static CORE_ADDR |
| 56 | cris_get_pc (struct regcache *regcache) |
| 57 | { |
| 58 | unsigned long pc; |
| 59 | collect_register_by_name (regcache, "pc", &pc); |
| 60 | if (debug_threads) |
| 61 | fprintf (stderr, "stop pc is %08lx\n", pc); |
| 62 | return pc; |
| 63 | } |
| 64 | |
| 65 | static void |
| 66 | cris_set_pc (struct regcache *regcache, CORE_ADDR pc) |
| 67 | { |
| 68 | unsigned long newpc = pc; |
| 69 | supply_register_by_name (regcache, "pc", &newpc); |
| 70 | } |
| 71 | |
| 72 | static const unsigned short cris_breakpoint = 0xe938; |
| 73 | #define cris_breakpoint_len 2 |
| 74 | |
| 75 | static int |
| 76 | cris_breakpoint_at (CORE_ADDR where) |
| 77 | { |
| 78 | unsigned short insn; |
| 79 | |
| 80 | (*the_target->read_memory) (where, (unsigned char *) &insn, |
| 81 | cris_breakpoint_len); |
| 82 | if (insn == cris_breakpoint) |
| 83 | return 1; |
| 84 | |
| 85 | /* If necessary, recognize more trap instructions here. GDB only uses the |
| 86 | one. */ |
| 87 | return 0; |
| 88 | } |
| 89 | |
| 90 | /* We only place breakpoints in empty marker functions, and thread locking |
| 91 | is outside of the function. So rather than importing software single-step, |
| 92 | we can just run until exit. */ |
| 93 | |
| 94 | /* FIXME: This function should not be needed, since we have PTRACE_SINGLESTEP |
| 95 | for CRISv32. Without it, td_ta_event_getmsg in thread_db_create_event |
| 96 | will fail when debugging multi-threaded applications. */ |
| 97 | |
| 98 | static CORE_ADDR |
| 99 | cris_reinsert_addr (void) |
| 100 | { |
| 101 | struct regcache *regcache = get_thread_regcache (current_inferior, 1); |
| 102 | unsigned long pc; |
| 103 | collect_register_by_name (regcache, "srp", &pc); |
| 104 | return pc; |
| 105 | } |
| 106 | |
| 107 | static void |
| 108 | cris_write_data_breakpoint (struct regcache *regcache, |
| 109 | int bp, unsigned long start, unsigned long end) |
| 110 | { |
| 111 | switch (bp) |
| 112 | { |
| 113 | case 0: |
| 114 | supply_register_by_name (regcache, "s3", &start); |
| 115 | supply_register_by_name (regcache, "s4", &end); |
| 116 | break; |
| 117 | case 1: |
| 118 | supply_register_by_name (regcache, "s5", &start); |
| 119 | supply_register_by_name (regcache, "s6", &end); |
| 120 | break; |
| 121 | case 2: |
| 122 | supply_register_by_name (regcache, "s7", &start); |
| 123 | supply_register_by_name (regcache, "s8", &end); |
| 124 | break; |
| 125 | case 3: |
| 126 | supply_register_by_name (regcache, "s9", &start); |
| 127 | supply_register_by_name (regcache, "s10", &end); |
| 128 | break; |
| 129 | case 4: |
| 130 | supply_register_by_name (regcache, "s11", &start); |
| 131 | supply_register_by_name (regcache, "s12", &end); |
| 132 | break; |
| 133 | case 5: |
| 134 | supply_register_by_name (regcache, "s13", &start); |
| 135 | supply_register_by_name (regcache, "s14", &end); |
| 136 | break; |
| 137 | } |
| 138 | } |
| 139 | |
| 140 | static int |
| 141 | cris_insert_point (char type, CORE_ADDR addr, int len) |
| 142 | { |
| 143 | int bp; |
| 144 | unsigned long bp_ctrl; |
| 145 | unsigned long start, end; |
| 146 | unsigned long ccs; |
| 147 | struct regcache *regcache; |
| 148 | |
| 149 | /* Breakpoint/watchpoint types (GDB terminology): |
| 150 | 0 = memory breakpoint for instructions |
| 151 | (not supported; done via memory write instead) |
| 152 | 1 = hardware breakpoint for instructions (not supported) |
| 153 | 2 = write watchpoint (supported) |
| 154 | 3 = read watchpoint (supported) |
| 155 | 4 = access watchpoint (supported). */ |
| 156 | |
| 157 | if (type < '2' || type > '4') |
| 158 | { |
| 159 | /* Unsupported. */ |
| 160 | return 1; |
| 161 | } |
| 162 | |
| 163 | regcache = get_thread_regcache (current_inferior, 1); |
| 164 | |
| 165 | /* Read watchpoints are set as access watchpoints, because of GDB's |
| 166 | inability to deal with pure read watchpoints. */ |
| 167 | if (type == '3') |
| 168 | type = '4'; |
| 169 | |
| 170 | /* Get the configuration register. */ |
| 171 | collect_register_by_name (regcache, "s0", &bp_ctrl); |
| 172 | |
| 173 | /* The watchpoint allocation scheme is the simplest possible. |
| 174 | For example, if a region is watched for read and |
| 175 | a write watch is requested, a new watchpoint will |
| 176 | be used. Also, if a watch for a region that is already |
| 177 | covered by one or more existing watchpoints, a new |
| 178 | watchpoint will be used. */ |
| 179 | |
| 180 | /* First, find a free data watchpoint. */ |
| 181 | for (bp = 0; bp < 6; bp++) |
| 182 | { |
| 183 | /* Each data watchpoint's control registers occupy 2 bits |
| 184 | (hence the 3), starting at bit 2 for D0 (hence the 2) |
| 185 | with 4 bits between for each watchpoint (yes, the 4). */ |
| 186 | if (!(bp_ctrl & (0x3 << (2 + (bp * 4))))) |
| 187 | break; |
| 188 | } |
| 189 | |
| 190 | if (bp > 5) |
| 191 | { |
| 192 | /* We're out of watchpoints. */ |
| 193 | return -1; |
| 194 | } |
| 195 | |
| 196 | /* Configure the control register first. */ |
| 197 | if (type == '3' || type == '4') |
| 198 | { |
| 199 | /* Trigger on read. */ |
| 200 | bp_ctrl |= (1 << (2 + bp * 4)); |
| 201 | } |
| 202 | if (type == '2' || type == '4') |
| 203 | { |
| 204 | /* Trigger on write. */ |
| 205 | bp_ctrl |= (2 << (2 + bp * 4)); |
| 206 | } |
| 207 | |
| 208 | /* Setup the configuration register. */ |
| 209 | supply_register_by_name (regcache, "s0", &bp_ctrl); |
| 210 | |
| 211 | /* Setup the range. */ |
| 212 | start = addr; |
| 213 | end = addr + len - 1; |
| 214 | |
| 215 | /* Configure the watchpoint register. */ |
| 216 | cris_write_data_breakpoint (regcache, bp, start, end); |
| 217 | |
| 218 | collect_register_by_name (regcache, "ccs", &ccs); |
| 219 | /* Set the S1 flag to enable watchpoints. */ |
| 220 | ccs |= (1 << 19); |
| 221 | supply_register_by_name (regcache, "ccs", &ccs); |
| 222 | |
| 223 | return 0; |
| 224 | } |
| 225 | |
| 226 | static int |
| 227 | cris_remove_point (char type, CORE_ADDR addr, int len) |
| 228 | { |
| 229 | int bp; |
| 230 | unsigned long bp_ctrl; |
| 231 | unsigned long start, end; |
| 232 | struct regcache *regcache; |
| 233 | unsigned long bp_d_regs[12]; |
| 234 | |
| 235 | /* Breakpoint/watchpoint types: |
| 236 | 0 = memory breakpoint for instructions |
| 237 | (not supported; done via memory write instead) |
| 238 | 1 = hardware breakpoint for instructions (not supported) |
| 239 | 2 = write watchpoint (supported) |
| 240 | 3 = read watchpoint (supported) |
| 241 | 4 = access watchpoint (supported). */ |
| 242 | if (type < '2' || type > '4') |
| 243 | return -1; |
| 244 | |
| 245 | regcache = get_thread_regcache (current_inferior, 1); |
| 246 | |
| 247 | /* Read watchpoints are set as access watchpoints, because of GDB's |
| 248 | inability to deal with pure read watchpoints. */ |
| 249 | if (type == '3') |
| 250 | type = '4'; |
| 251 | |
| 252 | /* Get the configuration register. */ |
| 253 | collect_register_by_name (regcache, "s0", &bp_ctrl); |
| 254 | |
| 255 | /* Try to find a watchpoint that is configured for the |
| 256 | specified range, then check that read/write also matches. */ |
| 257 | |
| 258 | /* Ugly pointer arithmetic, since I cannot rely on a |
| 259 | single switch (addr) as there may be several watchpoints with |
| 260 | the same start address for example. */ |
| 261 | |
| 262 | /* Get all range registers to simplify search. */ |
| 263 | collect_register_by_name (regcache, "s3", &bp_d_regs[0]); |
| 264 | collect_register_by_name (regcache, "s4", &bp_d_regs[1]); |
| 265 | collect_register_by_name (regcache, "s5", &bp_d_regs[2]); |
| 266 | collect_register_by_name (regcache, "s6", &bp_d_regs[3]); |
| 267 | collect_register_by_name (regcache, "s7", &bp_d_regs[4]); |
| 268 | collect_register_by_name (regcache, "s8", &bp_d_regs[5]); |
| 269 | collect_register_by_name (regcache, "s9", &bp_d_regs[6]); |
| 270 | collect_register_by_name (regcache, "s10", &bp_d_regs[7]); |
| 271 | collect_register_by_name (regcache, "s11", &bp_d_regs[8]); |
| 272 | collect_register_by_name (regcache, "s12", &bp_d_regs[9]); |
| 273 | collect_register_by_name (regcache, "s13", &bp_d_regs[10]); |
| 274 | collect_register_by_name (regcache, "s14", &bp_d_regs[11]); |
| 275 | |
| 276 | for (bp = 0; bp < 6; bp++) |
| 277 | { |
| 278 | if (bp_d_regs[bp * 2] == addr |
| 279 | && bp_d_regs[bp * 2 + 1] == (addr + len - 1)) { |
| 280 | /* Matching range. */ |
| 281 | int bitpos = 2 + bp * 4; |
| 282 | int rw_bits; |
| 283 | |
| 284 | /* Read/write bits for this BP. */ |
| 285 | rw_bits = (bp_ctrl & (0x3 << bitpos)) >> bitpos; |
| 286 | |
| 287 | if ((type == '3' && rw_bits == 0x1) |
| 288 | || (type == '2' && rw_bits == 0x2) |
| 289 | || (type == '4' && rw_bits == 0x3)) |
| 290 | { |
| 291 | /* Read/write matched. */ |
| 292 | break; |
| 293 | } |
| 294 | } |
| 295 | } |
| 296 | |
| 297 | if (bp > 5) |
| 298 | { |
| 299 | /* No watchpoint matched. */ |
| 300 | return -1; |
| 301 | } |
| 302 | |
| 303 | /* Found a matching watchpoint. Now, deconfigure it by |
| 304 | both disabling read/write in bp_ctrl and zeroing its |
| 305 | start/end addresses. */ |
| 306 | bp_ctrl &= ~(3 << (2 + (bp * 4))); |
| 307 | /* Setup the configuration register. */ |
| 308 | supply_register_by_name (regcache, "s0", &bp_ctrl); |
| 309 | |
| 310 | start = end = 0; |
| 311 | /* Configure the watchpoint register. */ |
| 312 | cris_write_data_breakpoint (regcache, bp, start, end); |
| 313 | |
| 314 | /* Note that we don't clear the S1 flag here. It's done when continuing. */ |
| 315 | return 0; |
| 316 | } |
| 317 | |
| 318 | static int |
| 319 | cris_stopped_by_watchpoint (void) |
| 320 | { |
| 321 | unsigned long exs; |
| 322 | struct regcache *regcache = get_thread_regcache (current_inferior, 1); |
| 323 | |
| 324 | collect_register_by_name (regcache, "exs", &exs); |
| 325 | |
| 326 | return (((exs & 0xff00) >> 8) == 0xc); |
| 327 | } |
| 328 | |
| 329 | static CORE_ADDR |
| 330 | cris_stopped_data_address (void) |
| 331 | { |
| 332 | unsigned long eda; |
| 333 | struct regcache *regcache = get_thread_regcache (current_inferior, 1); |
| 334 | |
| 335 | collect_register_by_name (regcache, "eda", &eda); |
| 336 | |
| 337 | /* FIXME: Possibly adjust to match watched range. */ |
| 338 | return eda; |
| 339 | } |
| 340 | |
| 341 | static void |
| 342 | cris_fill_gregset (struct regcache *regcache, void *buf) |
| 343 | { |
| 344 | int i; |
| 345 | |
| 346 | for (i = 0; i < cris_num_regs; i++) |
| 347 | { |
| 348 | if (cris_regmap[i] != -1) |
| 349 | collect_register (regcache, i, ((char *) buf) + cris_regmap[i]); |
| 350 | } |
| 351 | } |
| 352 | |
| 353 | static void |
| 354 | cris_store_gregset (struct regcache *regcache, const void *buf) |
| 355 | { |
| 356 | int i; |
| 357 | |
| 358 | for (i = 0; i < cris_num_regs; i++) |
| 359 | { |
| 360 | if (cris_regmap[i] != -1) |
| 361 | supply_register (regcache, i, ((char *) buf) + cris_regmap[i]); |
| 362 | } |
| 363 | } |
| 364 | |
| 365 | struct regset_info target_regsets[] = { |
| 366 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, cris_num_regs * 4, |
| 367 | GENERAL_REGS, cris_fill_gregset, cris_store_gregset }, |
| 368 | { 0, 0, 0, -1, -1, NULL, NULL } |
| 369 | }; |
| 370 | |
| 371 | struct linux_target_ops the_low_target = { |
| 372 | init_registers_crisv32, |
| 373 | -1, |
| 374 | NULL, |
| 375 | NULL, |
| 376 | NULL, |
| 377 | NULL, |
| 378 | NULL, /* fetch_register */ |
| 379 | cris_get_pc, |
| 380 | cris_set_pc, |
| 381 | (const unsigned char *) &cris_breakpoint, |
| 382 | cris_breakpoint_len, |
| 383 | cris_reinsert_addr, |
| 384 | 0, |
| 385 | cris_breakpoint_at, |
| 386 | cris_insert_point, |
| 387 | cris_remove_point, |
| 388 | cris_stopped_by_watchpoint, |
| 389 | cris_stopped_data_address, |
| 390 | }; |