| 1 | /* GNU/Linux/PowerPC specific low level interface, for the remote server for |
| 2 | GDB. |
| 3 | Copyright (C) 1995-2016 Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 19 | |
| 20 | #include "server.h" |
| 21 | #include "linux-low.h" |
| 22 | |
| 23 | #include <elf.h> |
| 24 | #include <asm/ptrace.h> |
| 25 | |
| 26 | #include "nat/ppc-linux.h" |
| 27 | |
| 28 | static unsigned long ppc_hwcap; |
| 29 | |
| 30 | |
| 31 | /* Defined in auto-generated file powerpc-32l.c. */ |
| 32 | void init_registers_powerpc_32l (void); |
| 33 | extern const struct target_desc *tdesc_powerpc_32l; |
| 34 | |
| 35 | /* Defined in auto-generated file powerpc-altivec32l.c. */ |
| 36 | void init_registers_powerpc_altivec32l (void); |
| 37 | extern const struct target_desc *tdesc_powerpc_altivec32l; |
| 38 | |
| 39 | /* Defined in auto-generated file powerpc-cell32l.c. */ |
| 40 | void init_registers_powerpc_cell32l (void); |
| 41 | extern const struct target_desc *tdesc_powerpc_cell32l; |
| 42 | |
| 43 | /* Defined in auto-generated file powerpc-vsx32l.c. */ |
| 44 | void init_registers_powerpc_vsx32l (void); |
| 45 | extern const struct target_desc *tdesc_powerpc_vsx32l; |
| 46 | |
| 47 | /* Defined in auto-generated file powerpc-isa205-32l.c. */ |
| 48 | void init_registers_powerpc_isa205_32l (void); |
| 49 | extern const struct target_desc *tdesc_powerpc_isa205_32l; |
| 50 | |
| 51 | /* Defined in auto-generated file powerpc-isa205-altivec32l.c. */ |
| 52 | void init_registers_powerpc_isa205_altivec32l (void); |
| 53 | extern const struct target_desc *tdesc_powerpc_isa205_altivec32l; |
| 54 | |
| 55 | /* Defined in auto-generated file powerpc-isa205-vsx32l.c. */ |
| 56 | void init_registers_powerpc_isa205_vsx32l (void); |
| 57 | extern const struct target_desc *tdesc_powerpc_isa205_vsx32l; |
| 58 | |
| 59 | /* Defined in auto-generated file powerpc-e500l.c. */ |
| 60 | void init_registers_powerpc_e500l (void); |
| 61 | extern const struct target_desc *tdesc_powerpc_e500l; |
| 62 | |
| 63 | /* Defined in auto-generated file powerpc-64l.c. */ |
| 64 | void init_registers_powerpc_64l (void); |
| 65 | extern const struct target_desc *tdesc_powerpc_64l; |
| 66 | |
| 67 | /* Defined in auto-generated file powerpc-altivec64l.c. */ |
| 68 | void init_registers_powerpc_altivec64l (void); |
| 69 | extern const struct target_desc *tdesc_powerpc_altivec64l; |
| 70 | |
| 71 | /* Defined in auto-generated file powerpc-cell64l.c. */ |
| 72 | void init_registers_powerpc_cell64l (void); |
| 73 | extern const struct target_desc *tdesc_powerpc_cell64l; |
| 74 | |
| 75 | /* Defined in auto-generated file powerpc-vsx64l.c. */ |
| 76 | void init_registers_powerpc_vsx64l (void); |
| 77 | extern const struct target_desc *tdesc_powerpc_vsx64l; |
| 78 | |
| 79 | /* Defined in auto-generated file powerpc-isa205-64l.c. */ |
| 80 | void init_registers_powerpc_isa205_64l (void); |
| 81 | extern const struct target_desc *tdesc_powerpc_isa205_64l; |
| 82 | |
| 83 | /* Defined in auto-generated file powerpc-isa205-altivec64l.c. */ |
| 84 | void init_registers_powerpc_isa205_altivec64l (void); |
| 85 | extern const struct target_desc *tdesc_powerpc_isa205_altivec64l; |
| 86 | |
| 87 | /* Defined in auto-generated file powerpc-isa205-vsx64l.c. */ |
| 88 | void init_registers_powerpc_isa205_vsx64l (void); |
| 89 | extern const struct target_desc *tdesc_powerpc_isa205_vsx64l; |
| 90 | |
| 91 | #define ppc_num_regs 73 |
| 92 | |
| 93 | #ifdef __powerpc64__ |
| 94 | /* We use a constant for FPSCR instead of PT_FPSCR, because |
| 95 | many shipped PPC64 kernels had the wrong value in ptrace.h. */ |
| 96 | static int ppc_regmap[] = |
| 97 | {PT_R0 * 8, PT_R1 * 8, PT_R2 * 8, PT_R3 * 8, |
| 98 | PT_R4 * 8, PT_R5 * 8, PT_R6 * 8, PT_R7 * 8, |
| 99 | PT_R8 * 8, PT_R9 * 8, PT_R10 * 8, PT_R11 * 8, |
| 100 | PT_R12 * 8, PT_R13 * 8, PT_R14 * 8, PT_R15 * 8, |
| 101 | PT_R16 * 8, PT_R17 * 8, PT_R18 * 8, PT_R19 * 8, |
| 102 | PT_R20 * 8, PT_R21 * 8, PT_R22 * 8, PT_R23 * 8, |
| 103 | PT_R24 * 8, PT_R25 * 8, PT_R26 * 8, PT_R27 * 8, |
| 104 | PT_R28 * 8, PT_R29 * 8, PT_R30 * 8, PT_R31 * 8, |
| 105 | PT_FPR0*8, PT_FPR0*8 + 8, PT_FPR0*8+16, PT_FPR0*8+24, |
| 106 | PT_FPR0*8+32, PT_FPR0*8+40, PT_FPR0*8+48, PT_FPR0*8+56, |
| 107 | PT_FPR0*8+64, PT_FPR0*8+72, PT_FPR0*8+80, PT_FPR0*8+88, |
| 108 | PT_FPR0*8+96, PT_FPR0*8+104, PT_FPR0*8+112, PT_FPR0*8+120, |
| 109 | PT_FPR0*8+128, PT_FPR0*8+136, PT_FPR0*8+144, PT_FPR0*8+152, |
| 110 | PT_FPR0*8+160, PT_FPR0*8+168, PT_FPR0*8+176, PT_FPR0*8+184, |
| 111 | PT_FPR0*8+192, PT_FPR0*8+200, PT_FPR0*8+208, PT_FPR0*8+216, |
| 112 | PT_FPR0*8+224, PT_FPR0*8+232, PT_FPR0*8+240, PT_FPR0*8+248, |
| 113 | PT_NIP * 8, PT_MSR * 8, PT_CCR * 8, PT_LNK * 8, |
| 114 | PT_CTR * 8, PT_XER * 8, PT_FPR0*8 + 256, |
| 115 | PT_ORIG_R3 * 8, PT_TRAP * 8 }; |
| 116 | #else |
| 117 | /* Currently, don't check/send MQ. */ |
| 118 | static int ppc_regmap[] = |
| 119 | {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4, |
| 120 | PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4, |
| 121 | PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4, |
| 122 | PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4, |
| 123 | PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4, |
| 124 | PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4, |
| 125 | PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4, |
| 126 | PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4, |
| 127 | PT_FPR0*4, PT_FPR0*4 + 8, PT_FPR0*4+16, PT_FPR0*4+24, |
| 128 | PT_FPR0*4+32, PT_FPR0*4+40, PT_FPR0*4+48, PT_FPR0*4+56, |
| 129 | PT_FPR0*4+64, PT_FPR0*4+72, PT_FPR0*4+80, PT_FPR0*4+88, |
| 130 | PT_FPR0*4+96, PT_FPR0*4+104, PT_FPR0*4+112, PT_FPR0*4+120, |
| 131 | PT_FPR0*4+128, PT_FPR0*4+136, PT_FPR0*4+144, PT_FPR0*4+152, |
| 132 | PT_FPR0*4+160, PT_FPR0*4+168, PT_FPR0*4+176, PT_FPR0*4+184, |
| 133 | PT_FPR0*4+192, PT_FPR0*4+200, PT_FPR0*4+208, PT_FPR0*4+216, |
| 134 | PT_FPR0*4+224, PT_FPR0*4+232, PT_FPR0*4+240, PT_FPR0*4+248, |
| 135 | PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4, |
| 136 | PT_CTR * 4, PT_XER * 4, PT_FPSCR * 4, |
| 137 | PT_ORIG_R3 * 4, PT_TRAP * 4 |
| 138 | }; |
| 139 | |
| 140 | static int ppc_regmap_e500[] = |
| 141 | {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4, |
| 142 | PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4, |
| 143 | PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4, |
| 144 | PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4, |
| 145 | PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4, |
| 146 | PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4, |
| 147 | PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4, |
| 148 | PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4, |
| 149 | -1, -1, -1, -1, |
| 150 | -1, -1, -1, -1, |
| 151 | -1, -1, -1, -1, |
| 152 | -1, -1, -1, -1, |
| 153 | -1, -1, -1, -1, |
| 154 | -1, -1, -1, -1, |
| 155 | -1, -1, -1, -1, |
| 156 | -1, -1, -1, -1, |
| 157 | PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4, |
| 158 | PT_CTR * 4, PT_XER * 4, -1, |
| 159 | PT_ORIG_R3 * 4, PT_TRAP * 4 |
| 160 | }; |
| 161 | #endif |
| 162 | |
| 163 | static int |
| 164 | ppc_cannot_store_register (int regno) |
| 165 | { |
| 166 | const struct target_desc *tdesc = current_process ()->tdesc; |
| 167 | |
| 168 | #ifndef __powerpc64__ |
| 169 | /* Some kernels do not allow us to store fpscr. */ |
| 170 | if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE) |
| 171 | && regno == find_regno (tdesc, "fpscr")) |
| 172 | return 2; |
| 173 | #endif |
| 174 | |
| 175 | /* Some kernels do not allow us to store orig_r3 or trap. */ |
| 176 | if (regno == find_regno (tdesc, "orig_r3") |
| 177 | || regno == find_regno (tdesc, "trap")) |
| 178 | return 2; |
| 179 | |
| 180 | return 0; |
| 181 | } |
| 182 | |
| 183 | static int |
| 184 | ppc_cannot_fetch_register (int regno) |
| 185 | { |
| 186 | return 0; |
| 187 | } |
| 188 | |
| 189 | static void |
| 190 | ppc_collect_ptrace_register (struct regcache *regcache, int regno, char *buf) |
| 191 | { |
| 192 | memset (buf, 0, sizeof (long)); |
| 193 | |
| 194 | if (__BYTE_ORDER == __LITTLE_ENDIAN) |
| 195 | { |
| 196 | /* Little-endian values always sit at the left end of the buffer. */ |
| 197 | collect_register (regcache, regno, buf); |
| 198 | } |
| 199 | else if (__BYTE_ORDER == __BIG_ENDIAN) |
| 200 | { |
| 201 | /* Big-endian values sit at the right end of the buffer. In case of |
| 202 | registers whose sizes are smaller than sizeof (long), we must use a |
| 203 | padding to access them correctly. */ |
| 204 | int size = register_size (regcache->tdesc, regno); |
| 205 | |
| 206 | if (size < sizeof (long)) |
| 207 | collect_register (regcache, regno, buf + sizeof (long) - size); |
| 208 | else |
| 209 | collect_register (regcache, regno, buf); |
| 210 | } |
| 211 | else |
| 212 | perror_with_name ("Unexpected byte order"); |
| 213 | } |
| 214 | |
| 215 | static void |
| 216 | ppc_supply_ptrace_register (struct regcache *regcache, |
| 217 | int regno, const char *buf) |
| 218 | { |
| 219 | if (__BYTE_ORDER == __LITTLE_ENDIAN) |
| 220 | { |
| 221 | /* Little-endian values always sit at the left end of the buffer. */ |
| 222 | supply_register (regcache, regno, buf); |
| 223 | } |
| 224 | else if (__BYTE_ORDER == __BIG_ENDIAN) |
| 225 | { |
| 226 | /* Big-endian values sit at the right end of the buffer. In case of |
| 227 | registers whose sizes are smaller than sizeof (long), we must use a |
| 228 | padding to access them correctly. */ |
| 229 | int size = register_size (regcache->tdesc, regno); |
| 230 | |
| 231 | if (size < sizeof (long)) |
| 232 | supply_register (regcache, regno, buf + sizeof (long) - size); |
| 233 | else |
| 234 | supply_register (regcache, regno, buf); |
| 235 | } |
| 236 | else |
| 237 | perror_with_name ("Unexpected byte order"); |
| 238 | } |
| 239 | |
| 240 | |
| 241 | #define INSTR_SC 0x44000002 |
| 242 | #define NR_spu_run 0x0116 |
| 243 | |
| 244 | /* If the PPU thread is currently stopped on a spu_run system call, |
| 245 | return to FD and ADDR the file handle and NPC parameter address |
| 246 | used with the system call. Return non-zero if successful. */ |
| 247 | static int |
| 248 | parse_spufs_run (struct regcache *regcache, int *fd, CORE_ADDR *addr) |
| 249 | { |
| 250 | CORE_ADDR curr_pc; |
| 251 | int curr_insn; |
| 252 | int curr_r0; |
| 253 | |
| 254 | if (register_size (regcache->tdesc, 0) == 4) |
| 255 | { |
| 256 | unsigned int pc, r0, r3, r4; |
| 257 | collect_register_by_name (regcache, "pc", &pc); |
| 258 | collect_register_by_name (regcache, "r0", &r0); |
| 259 | collect_register_by_name (regcache, "orig_r3", &r3); |
| 260 | collect_register_by_name (regcache, "r4", &r4); |
| 261 | curr_pc = (CORE_ADDR) pc; |
| 262 | curr_r0 = (int) r0; |
| 263 | *fd = (int) r3; |
| 264 | *addr = (CORE_ADDR) r4; |
| 265 | } |
| 266 | else |
| 267 | { |
| 268 | unsigned long pc, r0, r3, r4; |
| 269 | collect_register_by_name (regcache, "pc", &pc); |
| 270 | collect_register_by_name (regcache, "r0", &r0); |
| 271 | collect_register_by_name (regcache, "orig_r3", &r3); |
| 272 | collect_register_by_name (regcache, "r4", &r4); |
| 273 | curr_pc = (CORE_ADDR) pc; |
| 274 | curr_r0 = (int) r0; |
| 275 | *fd = (int) r3; |
| 276 | *addr = (CORE_ADDR) r4; |
| 277 | } |
| 278 | |
| 279 | /* Fetch instruction preceding current NIP. */ |
| 280 | if ((*the_target->read_memory) (curr_pc - 4, |
| 281 | (unsigned char *) &curr_insn, 4) != 0) |
| 282 | return 0; |
| 283 | /* It should be a "sc" instruction. */ |
| 284 | if (curr_insn != INSTR_SC) |
| 285 | return 0; |
| 286 | /* System call number should be NR_spu_run. */ |
| 287 | if (curr_r0 != NR_spu_run) |
| 288 | return 0; |
| 289 | |
| 290 | return 1; |
| 291 | } |
| 292 | |
| 293 | static CORE_ADDR |
| 294 | ppc_get_pc (struct regcache *regcache) |
| 295 | { |
| 296 | CORE_ADDR addr; |
| 297 | int fd; |
| 298 | |
| 299 | if (parse_spufs_run (regcache, &fd, &addr)) |
| 300 | { |
| 301 | unsigned int pc; |
| 302 | (*the_target->read_memory) (addr, (unsigned char *) &pc, 4); |
| 303 | return ((CORE_ADDR)1 << 63) |
| 304 | | ((CORE_ADDR)fd << 32) | (CORE_ADDR) (pc - 4); |
| 305 | } |
| 306 | else if (register_size (regcache->tdesc, 0) == 4) |
| 307 | { |
| 308 | unsigned int pc; |
| 309 | collect_register_by_name (regcache, "pc", &pc); |
| 310 | return (CORE_ADDR) pc; |
| 311 | } |
| 312 | else |
| 313 | { |
| 314 | unsigned long pc; |
| 315 | collect_register_by_name (regcache, "pc", &pc); |
| 316 | return (CORE_ADDR) pc; |
| 317 | } |
| 318 | } |
| 319 | |
| 320 | static void |
| 321 | ppc_set_pc (struct regcache *regcache, CORE_ADDR pc) |
| 322 | { |
| 323 | CORE_ADDR addr; |
| 324 | int fd; |
| 325 | |
| 326 | if (parse_spufs_run (regcache, &fd, &addr)) |
| 327 | { |
| 328 | unsigned int newpc = pc; |
| 329 | (*the_target->write_memory) (addr, (unsigned char *) &newpc, 4); |
| 330 | } |
| 331 | else if (register_size (regcache->tdesc, 0) == 4) |
| 332 | { |
| 333 | unsigned int newpc = pc; |
| 334 | supply_register_by_name (regcache, "pc", &newpc); |
| 335 | } |
| 336 | else |
| 337 | { |
| 338 | unsigned long newpc = pc; |
| 339 | supply_register_by_name (regcache, "pc", &newpc); |
| 340 | } |
| 341 | } |
| 342 | |
| 343 | |
| 344 | static int |
| 345 | ppc_get_hwcap (unsigned long *valp) |
| 346 | { |
| 347 | const struct target_desc *tdesc = current_process ()->tdesc; |
| 348 | int wordsize = register_size (tdesc, 0); |
| 349 | unsigned char *data = (unsigned char *) alloca (2 * wordsize); |
| 350 | int offset = 0; |
| 351 | |
| 352 | while ((*the_target->read_auxv) (offset, data, 2 * wordsize) == 2 * wordsize) |
| 353 | { |
| 354 | if (wordsize == 4) |
| 355 | { |
| 356 | unsigned int *data_p = (unsigned int *)data; |
| 357 | if (data_p[0] == AT_HWCAP) |
| 358 | { |
| 359 | *valp = data_p[1]; |
| 360 | return 1; |
| 361 | } |
| 362 | } |
| 363 | else |
| 364 | { |
| 365 | unsigned long *data_p = (unsigned long *)data; |
| 366 | if (data_p[0] == AT_HWCAP) |
| 367 | { |
| 368 | *valp = data_p[1]; |
| 369 | return 1; |
| 370 | } |
| 371 | } |
| 372 | |
| 373 | offset += 2 * wordsize; |
| 374 | } |
| 375 | |
| 376 | *valp = 0; |
| 377 | return 0; |
| 378 | } |
| 379 | |
| 380 | #ifndef __powerpc64__ |
| 381 | static int ppc_regmap_adjusted; |
| 382 | #endif |
| 383 | |
| 384 | |
| 385 | /* Correct in either endianness. |
| 386 | This instruction is "twge r2, r2", which GDB uses as a software |
| 387 | breakpoint. */ |
| 388 | static const unsigned int ppc_breakpoint = 0x7d821008; |
| 389 | #define ppc_breakpoint_len 4 |
| 390 | |
| 391 | /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */ |
| 392 | |
| 393 | static const gdb_byte * |
| 394 | ppc_sw_breakpoint_from_kind (int kind, int *size) |
| 395 | { |
| 396 | *size = ppc_breakpoint_len; |
| 397 | return (const gdb_byte *) &ppc_breakpoint; |
| 398 | } |
| 399 | |
| 400 | static int |
| 401 | ppc_breakpoint_at (CORE_ADDR where) |
| 402 | { |
| 403 | unsigned int insn; |
| 404 | |
| 405 | if (where & ((CORE_ADDR)1 << 63)) |
| 406 | { |
| 407 | char mem_annex[32]; |
| 408 | sprintf (mem_annex, "%d/mem", (int)((where >> 32) & 0x7fffffff)); |
| 409 | (*the_target->qxfer_spu) (mem_annex, (unsigned char *) &insn, |
| 410 | NULL, where & 0xffffffff, 4); |
| 411 | if (insn == 0x3fff) |
| 412 | return 1; |
| 413 | } |
| 414 | else |
| 415 | { |
| 416 | (*the_target->read_memory) (where, (unsigned char *) &insn, 4); |
| 417 | if (insn == ppc_breakpoint) |
| 418 | return 1; |
| 419 | /* If necessary, recognize more trap instructions here. GDB only uses |
| 420 | the one. */ |
| 421 | } |
| 422 | |
| 423 | return 0; |
| 424 | } |
| 425 | |
| 426 | /* Implement supports_z_point_type target-ops. |
| 427 | Returns true if type Z_TYPE breakpoint is supported. |
| 428 | |
| 429 | Handling software breakpoint at server side, so tracepoints |
| 430 | and breakpoints can be inserted at the same location. */ |
| 431 | |
| 432 | static int |
| 433 | ppc_supports_z_point_type (char z_type) |
| 434 | { |
| 435 | switch (z_type) |
| 436 | { |
| 437 | case Z_PACKET_SW_BP: |
| 438 | return 1; |
| 439 | case Z_PACKET_HW_BP: |
| 440 | case Z_PACKET_WRITE_WP: |
| 441 | case Z_PACKET_ACCESS_WP: |
| 442 | default: |
| 443 | return 0; |
| 444 | } |
| 445 | } |
| 446 | |
| 447 | /* Implement insert_point target-ops. |
| 448 | Returns 0 on success, -1 on failure and 1 on unsupported. */ |
| 449 | |
| 450 | static int |
| 451 | ppc_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, |
| 452 | int size, struct raw_breakpoint *bp) |
| 453 | { |
| 454 | switch (type) |
| 455 | { |
| 456 | case raw_bkpt_type_sw: |
| 457 | return insert_memory_breakpoint (bp); |
| 458 | |
| 459 | case raw_bkpt_type_hw: |
| 460 | case raw_bkpt_type_write_wp: |
| 461 | case raw_bkpt_type_access_wp: |
| 462 | default: |
| 463 | /* Unsupported. */ |
| 464 | return 1; |
| 465 | } |
| 466 | } |
| 467 | |
| 468 | /* Implement remove_point target-ops. |
| 469 | Returns 0 on success, -1 on failure and 1 on unsupported. */ |
| 470 | |
| 471 | static int |
| 472 | ppc_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, |
| 473 | int size, struct raw_breakpoint *bp) |
| 474 | { |
| 475 | switch (type) |
| 476 | { |
| 477 | case raw_bkpt_type_sw: |
| 478 | return remove_memory_breakpoint (bp); |
| 479 | |
| 480 | case raw_bkpt_type_hw: |
| 481 | case raw_bkpt_type_write_wp: |
| 482 | case raw_bkpt_type_access_wp: |
| 483 | default: |
| 484 | /* Unsupported. */ |
| 485 | return 1; |
| 486 | } |
| 487 | } |
| 488 | |
| 489 | /* Provide only a fill function for the general register set. ps_lgetregs |
| 490 | will use this for NPTL support. */ |
| 491 | |
| 492 | static void ppc_fill_gregset (struct regcache *regcache, void *buf) |
| 493 | { |
| 494 | int i; |
| 495 | |
| 496 | for (i = 0; i < 32; i++) |
| 497 | ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]); |
| 498 | |
| 499 | for (i = 64; i < 70; i++) |
| 500 | ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]); |
| 501 | |
| 502 | for (i = 71; i < 73; i++) |
| 503 | ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]); |
| 504 | } |
| 505 | |
| 506 | #define SIZEOF_VSXREGS 32*8 |
| 507 | |
| 508 | static void |
| 509 | ppc_fill_vsxregset (struct regcache *regcache, void *buf) |
| 510 | { |
| 511 | int i, base; |
| 512 | char *regset = (char *) buf; |
| 513 | |
| 514 | if (!(ppc_hwcap & PPC_FEATURE_HAS_VSX)) |
| 515 | return; |
| 516 | |
| 517 | base = find_regno (regcache->tdesc, "vs0h"); |
| 518 | for (i = 0; i < 32; i++) |
| 519 | collect_register (regcache, base + i, ®set[i * 8]); |
| 520 | } |
| 521 | |
| 522 | static void |
| 523 | ppc_store_vsxregset (struct regcache *regcache, const void *buf) |
| 524 | { |
| 525 | int i, base; |
| 526 | const char *regset = (const char *) buf; |
| 527 | |
| 528 | if (!(ppc_hwcap & PPC_FEATURE_HAS_VSX)) |
| 529 | return; |
| 530 | |
| 531 | base = find_regno (regcache->tdesc, "vs0h"); |
| 532 | for (i = 0; i < 32; i++) |
| 533 | supply_register (regcache, base + i, ®set[i * 8]); |
| 534 | } |
| 535 | |
| 536 | #define SIZEOF_VRREGS 33*16+4 |
| 537 | |
| 538 | static void |
| 539 | ppc_fill_vrregset (struct regcache *regcache, void *buf) |
| 540 | { |
| 541 | int i, base; |
| 542 | char *regset = (char *) buf; |
| 543 | |
| 544 | if (!(ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)) |
| 545 | return; |
| 546 | |
| 547 | base = find_regno (regcache->tdesc, "vr0"); |
| 548 | for (i = 0; i < 32; i++) |
| 549 | collect_register (regcache, base + i, ®set[i * 16]); |
| 550 | |
| 551 | collect_register_by_name (regcache, "vscr", ®set[32 * 16 + 12]); |
| 552 | collect_register_by_name (regcache, "vrsave", ®set[33 * 16]); |
| 553 | } |
| 554 | |
| 555 | static void |
| 556 | ppc_store_vrregset (struct regcache *regcache, const void *buf) |
| 557 | { |
| 558 | int i, base; |
| 559 | const char *regset = (const char *) buf; |
| 560 | |
| 561 | if (!(ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)) |
| 562 | return; |
| 563 | |
| 564 | base = find_regno (regcache->tdesc, "vr0"); |
| 565 | for (i = 0; i < 32; i++) |
| 566 | supply_register (regcache, base + i, ®set[i * 16]); |
| 567 | |
| 568 | supply_register_by_name (regcache, "vscr", ®set[32 * 16 + 12]); |
| 569 | supply_register_by_name (regcache, "vrsave", ®set[33 * 16]); |
| 570 | } |
| 571 | |
| 572 | struct gdb_evrregset_t |
| 573 | { |
| 574 | unsigned long evr[32]; |
| 575 | unsigned long long acc; |
| 576 | unsigned long spefscr; |
| 577 | }; |
| 578 | |
| 579 | static void |
| 580 | ppc_fill_evrregset (struct regcache *regcache, void *buf) |
| 581 | { |
| 582 | int i, ev0; |
| 583 | struct gdb_evrregset_t *regset = (struct gdb_evrregset_t *) buf; |
| 584 | |
| 585 | if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE)) |
| 586 | return; |
| 587 | |
| 588 | ev0 = find_regno (regcache->tdesc, "ev0h"); |
| 589 | for (i = 0; i < 32; i++) |
| 590 | collect_register (regcache, ev0 + i, ®set->evr[i]); |
| 591 | |
| 592 | collect_register_by_name (regcache, "acc", ®set->acc); |
| 593 | collect_register_by_name (regcache, "spefscr", ®set->spefscr); |
| 594 | } |
| 595 | |
| 596 | static void |
| 597 | ppc_store_evrregset (struct regcache *regcache, const void *buf) |
| 598 | { |
| 599 | int i, ev0; |
| 600 | const struct gdb_evrregset_t *regset = (const struct gdb_evrregset_t *) buf; |
| 601 | |
| 602 | if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE)) |
| 603 | return; |
| 604 | |
| 605 | ev0 = find_regno (regcache->tdesc, "ev0h"); |
| 606 | for (i = 0; i < 32; i++) |
| 607 | supply_register (regcache, ev0 + i, ®set->evr[i]); |
| 608 | |
| 609 | supply_register_by_name (regcache, "acc", ®set->acc); |
| 610 | supply_register_by_name (regcache, "spefscr", ®set->spefscr); |
| 611 | } |
| 612 | |
| 613 | /* Support for hardware single step. */ |
| 614 | |
| 615 | static int |
| 616 | ppc_supports_hardware_single_step (void) |
| 617 | { |
| 618 | return 1; |
| 619 | } |
| 620 | |
| 621 | static struct regset_info ppc_regsets[] = { |
| 622 | /* List the extra register sets before GENERAL_REGS. That way we will |
| 623 | fetch them every time, but still fall back to PTRACE_PEEKUSER for the |
| 624 | general registers. Some kernels support these, but not the newer |
| 625 | PPC_PTRACE_GETREGS. */ |
| 626 | { PTRACE_GETVSXREGS, PTRACE_SETVSXREGS, 0, SIZEOF_VSXREGS, EXTENDED_REGS, |
| 627 | ppc_fill_vsxregset, ppc_store_vsxregset }, |
| 628 | { PTRACE_GETVRREGS, PTRACE_SETVRREGS, 0, SIZEOF_VRREGS, EXTENDED_REGS, |
| 629 | ppc_fill_vrregset, ppc_store_vrregset }, |
| 630 | { PTRACE_GETEVRREGS, PTRACE_SETEVRREGS, 0, 32 * 4 + 8 + 4, EXTENDED_REGS, |
| 631 | ppc_fill_evrregset, ppc_store_evrregset }, |
| 632 | { 0, 0, 0, 0, GENERAL_REGS, ppc_fill_gregset, NULL }, |
| 633 | NULL_REGSET |
| 634 | }; |
| 635 | |
| 636 | static struct usrregs_info ppc_usrregs_info = |
| 637 | { |
| 638 | ppc_num_regs, |
| 639 | ppc_regmap, |
| 640 | }; |
| 641 | |
| 642 | static struct regsets_info ppc_regsets_info = |
| 643 | { |
| 644 | ppc_regsets, /* regsets */ |
| 645 | 0, /* num_regsets */ |
| 646 | NULL, /* disabled_regsets */ |
| 647 | }; |
| 648 | |
| 649 | static struct regs_info regs_info = |
| 650 | { |
| 651 | NULL, /* regset_bitmap */ |
| 652 | &ppc_usrregs_info, |
| 653 | &ppc_regsets_info |
| 654 | }; |
| 655 | |
| 656 | static const struct regs_info * |
| 657 | ppc_regs_info (void) |
| 658 | { |
| 659 | return ®s_info; |
| 660 | } |
| 661 | |
| 662 | static void |
| 663 | ppc_arch_setup (void) |
| 664 | { |
| 665 | const struct target_desc *tdesc; |
| 666 | #ifdef __powerpc64__ |
| 667 | long msr; |
| 668 | struct regcache *regcache; |
| 669 | |
| 670 | /* On a 64-bit host, assume 64-bit inferior process with no |
| 671 | AltiVec registers. Reset ppc_hwcap to ensure that the |
| 672 | collect_register call below does not fail. */ |
| 673 | tdesc = tdesc_powerpc_64l; |
| 674 | current_process ()->tdesc = tdesc; |
| 675 | ppc_hwcap = 0; |
| 676 | |
| 677 | regcache = new_register_cache (tdesc); |
| 678 | fetch_inferior_registers (regcache, find_regno (tdesc, "msr")); |
| 679 | collect_register_by_name (regcache, "msr", &msr); |
| 680 | free_register_cache (regcache); |
| 681 | if (ppc64_64bit_inferior_p (msr)) |
| 682 | { |
| 683 | ppc_get_hwcap (&ppc_hwcap); |
| 684 | if (ppc_hwcap & PPC_FEATURE_CELL) |
| 685 | tdesc = tdesc_powerpc_cell64l; |
| 686 | else if (ppc_hwcap & PPC_FEATURE_HAS_VSX) |
| 687 | { |
| 688 | /* Power ISA 2.05 (implemented by Power 6 and newer processors) |
| 689 | increases the FPSCR from 32 bits to 64 bits. Even though Power 7 |
| 690 | supports this ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 |
| 691 | set, only PPC_FEATURE_ARCH_2_06. Since for now the only bits |
| 692 | used in the higher half of the register are for Decimal Floating |
| 693 | Point, we check if that feature is available to decide the size |
| 694 | of the FPSCR. */ |
| 695 | if (ppc_hwcap & PPC_FEATURE_HAS_DFP) |
| 696 | tdesc = tdesc_powerpc_isa205_vsx64l; |
| 697 | else |
| 698 | tdesc = tdesc_powerpc_vsx64l; |
| 699 | } |
| 700 | else if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC) |
| 701 | { |
| 702 | if (ppc_hwcap & PPC_FEATURE_HAS_DFP) |
| 703 | tdesc = tdesc_powerpc_isa205_altivec64l; |
| 704 | else |
| 705 | tdesc = tdesc_powerpc_altivec64l; |
| 706 | } |
| 707 | |
| 708 | current_process ()->tdesc = tdesc; |
| 709 | return; |
| 710 | } |
| 711 | #endif |
| 712 | |
| 713 | /* OK, we have a 32-bit inferior. */ |
| 714 | tdesc = tdesc_powerpc_32l; |
| 715 | current_process ()->tdesc = tdesc; |
| 716 | |
| 717 | ppc_get_hwcap (&ppc_hwcap); |
| 718 | if (ppc_hwcap & PPC_FEATURE_CELL) |
| 719 | tdesc = tdesc_powerpc_cell32l; |
| 720 | else if (ppc_hwcap & PPC_FEATURE_HAS_VSX) |
| 721 | { |
| 722 | if (ppc_hwcap & PPC_FEATURE_HAS_DFP) |
| 723 | tdesc = tdesc_powerpc_isa205_vsx32l; |
| 724 | else |
| 725 | tdesc = tdesc_powerpc_vsx32l; |
| 726 | } |
| 727 | else if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC) |
| 728 | { |
| 729 | if (ppc_hwcap & PPC_FEATURE_HAS_DFP) |
| 730 | tdesc = tdesc_powerpc_isa205_altivec32l; |
| 731 | else |
| 732 | tdesc = tdesc_powerpc_altivec32l; |
| 733 | } |
| 734 | |
| 735 | /* On 32-bit machines, check for SPE registers. |
| 736 | Set the low target's regmap field as appropriately. */ |
| 737 | #ifndef __powerpc64__ |
| 738 | if (ppc_hwcap & PPC_FEATURE_HAS_SPE) |
| 739 | tdesc = tdesc_powerpc_e500l; |
| 740 | |
| 741 | if (!ppc_regmap_adjusted) |
| 742 | { |
| 743 | if (ppc_hwcap & PPC_FEATURE_HAS_SPE) |
| 744 | ppc_usrregs_info.regmap = ppc_regmap_e500; |
| 745 | |
| 746 | /* If the FPSCR is 64-bit wide, we need to fetch the whole |
| 747 | 64-bit slot and not just its second word. The PT_FPSCR |
| 748 | supplied in a 32-bit GDB compilation doesn't reflect |
| 749 | this. */ |
| 750 | if (register_size (tdesc, 70) == 8) |
| 751 | ppc_regmap[70] = (48 + 2*32) * sizeof (long); |
| 752 | |
| 753 | ppc_regmap_adjusted = 1; |
| 754 | } |
| 755 | #endif |
| 756 | current_process ()->tdesc = tdesc; |
| 757 | } |
| 758 | |
| 759 | static int |
| 760 | ppc_supports_tracepoints (void) |
| 761 | { |
| 762 | return 1; |
| 763 | } |
| 764 | |
| 765 | struct linux_target_ops the_low_target = { |
| 766 | ppc_arch_setup, |
| 767 | ppc_regs_info, |
| 768 | ppc_cannot_fetch_register, |
| 769 | ppc_cannot_store_register, |
| 770 | NULL, /* fetch_register */ |
| 771 | ppc_get_pc, |
| 772 | ppc_set_pc, |
| 773 | NULL, /* breakpoint_kind_from_pc */ |
| 774 | ppc_sw_breakpoint_from_kind, |
| 775 | NULL, |
| 776 | 0, |
| 777 | ppc_breakpoint_at, |
| 778 | ppc_supports_z_point_type, |
| 779 | ppc_insert_point, |
| 780 | ppc_remove_point, |
| 781 | NULL, |
| 782 | NULL, |
| 783 | ppc_collect_ptrace_register, |
| 784 | ppc_supply_ptrace_register, |
| 785 | NULL, /* siginfo_fixup */ |
| 786 | NULL, /* new_process */ |
| 787 | NULL, /* new_thread */ |
| 788 | NULL, /* new_fork */ |
| 789 | NULL, /* prepare_to_resume */ |
| 790 | NULL, /* process_qsupported */ |
| 791 | ppc_supports_tracepoints, |
| 792 | NULL, /* get_thread_area */ |
| 793 | NULL, /* install_fast_tracepoint_jump_pad */ |
| 794 | NULL, /* emit_ops */ |
| 795 | NULL, /* get_min_fast_tracepoint_insn_len */ |
| 796 | NULL, /* supports_range_stepping */ |
| 797 | NULL, /* breakpoint_kind_from_current_state */ |
| 798 | ppc_supports_hardware_single_step, |
| 799 | }; |
| 800 | |
| 801 | void |
| 802 | initialize_low_arch (void) |
| 803 | { |
| 804 | /* Initialize the Linux target descriptions. */ |
| 805 | |
| 806 | init_registers_powerpc_32l (); |
| 807 | init_registers_powerpc_altivec32l (); |
| 808 | init_registers_powerpc_cell32l (); |
| 809 | init_registers_powerpc_vsx32l (); |
| 810 | init_registers_powerpc_isa205_32l (); |
| 811 | init_registers_powerpc_isa205_altivec32l (); |
| 812 | init_registers_powerpc_isa205_vsx32l (); |
| 813 | init_registers_powerpc_e500l (); |
| 814 | init_registers_powerpc_64l (); |
| 815 | init_registers_powerpc_altivec64l (); |
| 816 | init_registers_powerpc_cell64l (); |
| 817 | init_registers_powerpc_vsx64l (); |
| 818 | init_registers_powerpc_isa205_64l (); |
| 819 | init_registers_powerpc_isa205_altivec64l (); |
| 820 | init_registers_powerpc_isa205_vsx64l (); |
| 821 | |
| 822 | initialize_regsets_info (&ppc_regsets_info); |
| 823 | } |