| 1 | /* GNU/Linux/x86-64 specific low level interface, for the remote server |
| 2 | for GDB. |
| 3 | Copyright (C) 2002-2017 Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 19 | |
| 20 | #include "server.h" |
| 21 | #include <signal.h> |
| 22 | #include <limits.h> |
| 23 | #include <inttypes.h> |
| 24 | #include "linux-low.h" |
| 25 | #include "i387-fp.h" |
| 26 | #include "x86-low.h" |
| 27 | #include "x86-xstate.h" |
| 28 | #include "nat/gdb_ptrace.h" |
| 29 | |
| 30 | #ifdef __x86_64__ |
| 31 | #include "nat/amd64-linux-siginfo.h" |
| 32 | #endif |
| 33 | |
| 34 | #include "gdb_proc_service.h" |
| 35 | /* Don't include elf/common.h if linux/elf.h got included by |
| 36 | gdb_proc_service.h. */ |
| 37 | #ifndef ELFMAG0 |
| 38 | #include "elf/common.h" |
| 39 | #endif |
| 40 | |
| 41 | #include "agent.h" |
| 42 | #include "tdesc.h" |
| 43 | #include "tracepoint.h" |
| 44 | #include "ax.h" |
| 45 | #include "nat/linux-nat.h" |
| 46 | #include "nat/x86-linux.h" |
| 47 | #include "nat/x86-linux-dregs.h" |
| 48 | #include "linux-x86-tdesc.h" |
| 49 | |
| 50 | #ifdef __x86_64__ |
| 51 | static struct target_desc *tdesc_amd64_linux_no_xml; |
| 52 | #endif |
| 53 | static struct target_desc *tdesc_i386_linux_no_xml; |
| 54 | |
| 55 | |
| 56 | static unsigned char jump_insn[] = { 0xe9, 0, 0, 0, 0 }; |
| 57 | static unsigned char small_jump_insn[] = { 0x66, 0xe9, 0, 0 }; |
| 58 | |
| 59 | /* Backward compatibility for gdb without XML support. */ |
| 60 | |
| 61 | static const char *xmltarget_i386_linux_no_xml = "@<target>\ |
| 62 | <architecture>i386</architecture>\ |
| 63 | <osabi>GNU/Linux</osabi>\ |
| 64 | </target>"; |
| 65 | |
| 66 | #ifdef __x86_64__ |
| 67 | static const char *xmltarget_amd64_linux_no_xml = "@<target>\ |
| 68 | <architecture>i386:x86-64</architecture>\ |
| 69 | <osabi>GNU/Linux</osabi>\ |
| 70 | </target>"; |
| 71 | #endif |
| 72 | |
| 73 | #include <sys/reg.h> |
| 74 | #include <sys/procfs.h> |
| 75 | #include "nat/gdb_ptrace.h" |
| 76 | #include <sys/uio.h> |
| 77 | |
| 78 | #ifndef PTRACE_GET_THREAD_AREA |
| 79 | #define PTRACE_GET_THREAD_AREA 25 |
| 80 | #endif |
| 81 | |
| 82 | /* This definition comes from prctl.h, but some kernels may not have it. */ |
| 83 | #ifndef PTRACE_ARCH_PRCTL |
| 84 | #define PTRACE_ARCH_PRCTL 30 |
| 85 | #endif |
| 86 | |
| 87 | /* The following definitions come from prctl.h, but may be absent |
| 88 | for certain configurations. */ |
| 89 | #ifndef ARCH_GET_FS |
| 90 | #define ARCH_SET_GS 0x1001 |
| 91 | #define ARCH_SET_FS 0x1002 |
| 92 | #define ARCH_GET_FS 0x1003 |
| 93 | #define ARCH_GET_GS 0x1004 |
| 94 | #endif |
| 95 | |
| 96 | /* Per-process arch-specific data we want to keep. */ |
| 97 | |
| 98 | struct arch_process_info |
| 99 | { |
| 100 | struct x86_debug_reg_state debug_reg_state; |
| 101 | }; |
| 102 | |
| 103 | #ifdef __x86_64__ |
| 104 | |
| 105 | /* Mapping between the general-purpose registers in `struct user' |
| 106 | format and GDB's register array layout. |
| 107 | Note that the transfer layout uses 64-bit regs. */ |
| 108 | static /*const*/ int i386_regmap[] = |
| 109 | { |
| 110 | RAX * 8, RCX * 8, RDX * 8, RBX * 8, |
| 111 | RSP * 8, RBP * 8, RSI * 8, RDI * 8, |
| 112 | RIP * 8, EFLAGS * 8, CS * 8, SS * 8, |
| 113 | DS * 8, ES * 8, FS * 8, GS * 8 |
| 114 | }; |
| 115 | |
| 116 | #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0])) |
| 117 | |
| 118 | /* So code below doesn't have to care, i386 or amd64. */ |
| 119 | #define ORIG_EAX ORIG_RAX |
| 120 | #define REGSIZE 8 |
| 121 | |
| 122 | static const int x86_64_regmap[] = |
| 123 | { |
| 124 | RAX * 8, RBX * 8, RCX * 8, RDX * 8, |
| 125 | RSI * 8, RDI * 8, RBP * 8, RSP * 8, |
| 126 | R8 * 8, R9 * 8, R10 * 8, R11 * 8, |
| 127 | R12 * 8, R13 * 8, R14 * 8, R15 * 8, |
| 128 | RIP * 8, EFLAGS * 8, CS * 8, SS * 8, |
| 129 | DS * 8, ES * 8, FS * 8, GS * 8, |
| 130 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 131 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 132 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 133 | -1, |
| 134 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 135 | ORIG_RAX * 8, |
| 136 | #ifdef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE |
| 137 | 21 * 8, 22 * 8, |
| 138 | #else |
| 139 | -1, -1, |
| 140 | #endif |
| 141 | -1, -1, -1, -1, /* MPX registers BND0 ... BND3. */ |
| 142 | -1, -1, /* MPX registers BNDCFGU, BNDSTATUS. */ |
| 143 | -1, -1, -1, -1, -1, -1, -1, -1, /* xmm16 ... xmm31 (AVX512) */ |
| 144 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 145 | -1, -1, -1, -1, -1, -1, -1, -1, /* ymm16 ... ymm31 (AVX512) */ |
| 146 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 147 | -1, -1, -1, -1, -1, -1, -1, -1, /* k0 ... k7 (AVX512) */ |
| 148 | -1, -1, -1, -1, -1, -1, -1, -1, /* zmm0 ... zmm31 (AVX512) */ |
| 149 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 150 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 151 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 152 | -1 /* pkru */ |
| 153 | }; |
| 154 | |
| 155 | #define X86_64_NUM_REGS (sizeof (x86_64_regmap) / sizeof (x86_64_regmap[0])) |
| 156 | #define X86_64_USER_REGS (GS + 1) |
| 157 | |
| 158 | #else /* ! __x86_64__ */ |
| 159 | |
| 160 | /* Mapping between the general-purpose registers in `struct user' |
| 161 | format and GDB's register array layout. */ |
| 162 | static /*const*/ int i386_regmap[] = |
| 163 | { |
| 164 | EAX * 4, ECX * 4, EDX * 4, EBX * 4, |
| 165 | UESP * 4, EBP * 4, ESI * 4, EDI * 4, |
| 166 | EIP * 4, EFL * 4, CS * 4, SS * 4, |
| 167 | DS * 4, ES * 4, FS * 4, GS * 4 |
| 168 | }; |
| 169 | |
| 170 | #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0])) |
| 171 | |
| 172 | #define REGSIZE 4 |
| 173 | |
| 174 | #endif |
| 175 | |
| 176 | #ifdef __x86_64__ |
| 177 | |
| 178 | /* Returns true if the current inferior belongs to a x86-64 process, |
| 179 | per the tdesc. */ |
| 180 | |
| 181 | static int |
| 182 | is_64bit_tdesc (void) |
| 183 | { |
| 184 | struct regcache *regcache = get_thread_regcache (current_thread, 0); |
| 185 | |
| 186 | return register_size (regcache->tdesc, 0) == 8; |
| 187 | } |
| 188 | |
| 189 | #endif |
| 190 | |
| 191 | \f |
| 192 | /* Called by libthread_db. */ |
| 193 | |
| 194 | ps_err_e |
| 195 | ps_get_thread_area (struct ps_prochandle *ph, |
| 196 | lwpid_t lwpid, int idx, void **base) |
| 197 | { |
| 198 | #ifdef __x86_64__ |
| 199 | int use_64bit = is_64bit_tdesc (); |
| 200 | |
| 201 | if (use_64bit) |
| 202 | { |
| 203 | switch (idx) |
| 204 | { |
| 205 | case FS: |
| 206 | if (ptrace (PTRACE_ARCH_PRCTL, lwpid, base, ARCH_GET_FS) == 0) |
| 207 | return PS_OK; |
| 208 | break; |
| 209 | case GS: |
| 210 | if (ptrace (PTRACE_ARCH_PRCTL, lwpid, base, ARCH_GET_GS) == 0) |
| 211 | return PS_OK; |
| 212 | break; |
| 213 | default: |
| 214 | return PS_BADADDR; |
| 215 | } |
| 216 | return PS_ERR; |
| 217 | } |
| 218 | #endif |
| 219 | |
| 220 | { |
| 221 | unsigned int desc[4]; |
| 222 | |
| 223 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, |
| 224 | (void *) (intptr_t) idx, (unsigned long) &desc) < 0) |
| 225 | return PS_ERR; |
| 226 | |
| 227 | /* Ensure we properly extend the value to 64-bits for x86_64. */ |
| 228 | *base = (void *) (uintptr_t) desc[1]; |
| 229 | return PS_OK; |
| 230 | } |
| 231 | } |
| 232 | |
| 233 | /* Get the thread area address. This is used to recognize which |
| 234 | thread is which when tracing with the in-process agent library. We |
| 235 | don't read anything from the address, and treat it as opaque; it's |
| 236 | the address itself that we assume is unique per-thread. */ |
| 237 | |
| 238 | static int |
| 239 | x86_get_thread_area (int lwpid, CORE_ADDR *addr) |
| 240 | { |
| 241 | #ifdef __x86_64__ |
| 242 | int use_64bit = is_64bit_tdesc (); |
| 243 | |
| 244 | if (use_64bit) |
| 245 | { |
| 246 | void *base; |
| 247 | if (ptrace (PTRACE_ARCH_PRCTL, lwpid, &base, ARCH_GET_FS) == 0) |
| 248 | { |
| 249 | *addr = (CORE_ADDR) (uintptr_t) base; |
| 250 | return 0; |
| 251 | } |
| 252 | |
| 253 | return -1; |
| 254 | } |
| 255 | #endif |
| 256 | |
| 257 | { |
| 258 | struct lwp_info *lwp = find_lwp_pid (pid_to_ptid (lwpid)); |
| 259 | struct thread_info *thr = get_lwp_thread (lwp); |
| 260 | struct regcache *regcache = get_thread_regcache (thr, 1); |
| 261 | unsigned int desc[4]; |
| 262 | ULONGEST gs = 0; |
| 263 | const int reg_thread_area = 3; /* bits to scale down register value. */ |
| 264 | int idx; |
| 265 | |
| 266 | collect_register_by_name (regcache, "gs", &gs); |
| 267 | |
| 268 | idx = gs >> reg_thread_area; |
| 269 | |
| 270 | if (ptrace (PTRACE_GET_THREAD_AREA, |
| 271 | lwpid_of (thr), |
| 272 | (void *) (long) idx, (unsigned long) &desc) < 0) |
| 273 | return -1; |
| 274 | |
| 275 | *addr = desc[1]; |
| 276 | return 0; |
| 277 | } |
| 278 | } |
| 279 | |
| 280 | |
| 281 | \f |
| 282 | static int |
| 283 | x86_cannot_store_register (int regno) |
| 284 | { |
| 285 | #ifdef __x86_64__ |
| 286 | if (is_64bit_tdesc ()) |
| 287 | return 0; |
| 288 | #endif |
| 289 | |
| 290 | return regno >= I386_NUM_REGS; |
| 291 | } |
| 292 | |
| 293 | static int |
| 294 | x86_cannot_fetch_register (int regno) |
| 295 | { |
| 296 | #ifdef __x86_64__ |
| 297 | if (is_64bit_tdesc ()) |
| 298 | return 0; |
| 299 | #endif |
| 300 | |
| 301 | return regno >= I386_NUM_REGS; |
| 302 | } |
| 303 | |
| 304 | static void |
| 305 | x86_fill_gregset (struct regcache *regcache, void *buf) |
| 306 | { |
| 307 | int i; |
| 308 | |
| 309 | #ifdef __x86_64__ |
| 310 | if (register_size (regcache->tdesc, 0) == 8) |
| 311 | { |
| 312 | for (i = 0; i < X86_64_NUM_REGS; i++) |
| 313 | if (x86_64_regmap[i] != -1) |
| 314 | collect_register (regcache, i, ((char *) buf) + x86_64_regmap[i]); |
| 315 | |
| 316 | #ifndef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE |
| 317 | { |
| 318 | unsigned long base; |
| 319 | int lwpid = lwpid_of (current_thread); |
| 320 | |
| 321 | collect_register_by_name (regcache, "fs_base", &base); |
| 322 | ptrace (PTRACE_ARCH_PRCTL, lwpid, &base, ARCH_SET_FS); |
| 323 | |
| 324 | collect_register_by_name (regcache, "gs_base", &base); |
| 325 | ptrace (PTRACE_ARCH_PRCTL, lwpid, &base, ARCH_SET_GS); |
| 326 | } |
| 327 | #endif |
| 328 | |
| 329 | return; |
| 330 | } |
| 331 | |
| 332 | /* 32-bit inferior registers need to be zero-extended. |
| 333 | Callers would read uninitialized memory otherwise. */ |
| 334 | memset (buf, 0x00, X86_64_USER_REGS * 8); |
| 335 | #endif |
| 336 | |
| 337 | for (i = 0; i < I386_NUM_REGS; i++) |
| 338 | collect_register (regcache, i, ((char *) buf) + i386_regmap[i]); |
| 339 | |
| 340 | collect_register_by_name (regcache, "orig_eax", |
| 341 | ((char *) buf) + ORIG_EAX * REGSIZE); |
| 342 | } |
| 343 | |
| 344 | static void |
| 345 | x86_store_gregset (struct regcache *regcache, const void *buf) |
| 346 | { |
| 347 | int i; |
| 348 | |
| 349 | #ifdef __x86_64__ |
| 350 | if (register_size (regcache->tdesc, 0) == 8) |
| 351 | { |
| 352 | for (i = 0; i < X86_64_NUM_REGS; i++) |
| 353 | if (x86_64_regmap[i] != -1) |
| 354 | supply_register (regcache, i, ((char *) buf) + x86_64_regmap[i]); |
| 355 | |
| 356 | #ifndef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE |
| 357 | { |
| 358 | unsigned long base; |
| 359 | int lwpid = lwpid_of (current_thread); |
| 360 | |
| 361 | if (ptrace (PTRACE_ARCH_PRCTL, lwpid, &base, ARCH_GET_FS) == 0) |
| 362 | supply_register_by_name (regcache, "fs_base", &base); |
| 363 | |
| 364 | if (ptrace (PTRACE_ARCH_PRCTL, lwpid, &base, ARCH_GET_GS) == 0) |
| 365 | supply_register_by_name (regcache, "gs_base", &base); |
| 366 | } |
| 367 | #endif |
| 368 | return; |
| 369 | } |
| 370 | #endif |
| 371 | |
| 372 | for (i = 0; i < I386_NUM_REGS; i++) |
| 373 | supply_register (regcache, i, ((char *) buf) + i386_regmap[i]); |
| 374 | |
| 375 | supply_register_by_name (regcache, "orig_eax", |
| 376 | ((char *) buf) + ORIG_EAX * REGSIZE); |
| 377 | } |
| 378 | |
| 379 | static void |
| 380 | x86_fill_fpregset (struct regcache *regcache, void *buf) |
| 381 | { |
| 382 | #ifdef __x86_64__ |
| 383 | i387_cache_to_fxsave (regcache, buf); |
| 384 | #else |
| 385 | i387_cache_to_fsave (regcache, buf); |
| 386 | #endif |
| 387 | } |
| 388 | |
| 389 | static void |
| 390 | x86_store_fpregset (struct regcache *regcache, const void *buf) |
| 391 | { |
| 392 | #ifdef __x86_64__ |
| 393 | i387_fxsave_to_cache (regcache, buf); |
| 394 | #else |
| 395 | i387_fsave_to_cache (regcache, buf); |
| 396 | #endif |
| 397 | } |
| 398 | |
| 399 | #ifndef __x86_64__ |
| 400 | |
| 401 | static void |
| 402 | x86_fill_fpxregset (struct regcache *regcache, void *buf) |
| 403 | { |
| 404 | i387_cache_to_fxsave (regcache, buf); |
| 405 | } |
| 406 | |
| 407 | static void |
| 408 | x86_store_fpxregset (struct regcache *regcache, const void *buf) |
| 409 | { |
| 410 | i387_fxsave_to_cache (regcache, buf); |
| 411 | } |
| 412 | |
| 413 | #endif |
| 414 | |
| 415 | static void |
| 416 | x86_fill_xstateregset (struct regcache *regcache, void *buf) |
| 417 | { |
| 418 | i387_cache_to_xsave (regcache, buf); |
| 419 | } |
| 420 | |
| 421 | static void |
| 422 | x86_store_xstateregset (struct regcache *regcache, const void *buf) |
| 423 | { |
| 424 | i387_xsave_to_cache (regcache, buf); |
| 425 | } |
| 426 | |
| 427 | /* ??? The non-biarch i386 case stores all the i387 regs twice. |
| 428 | Once in i387_.*fsave.* and once in i387_.*fxsave.*. |
| 429 | This is, presumably, to handle the case where PTRACE_[GS]ETFPXREGS |
| 430 | doesn't work. IWBN to avoid the duplication in the case where it |
| 431 | does work. Maybe the arch_setup routine could check whether it works |
| 432 | and update the supported regsets accordingly. */ |
| 433 | |
| 434 | static struct regset_info x86_regsets[] = |
| 435 | { |
| 436 | #ifdef HAVE_PTRACE_GETREGS |
| 437 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), |
| 438 | GENERAL_REGS, |
| 439 | x86_fill_gregset, x86_store_gregset }, |
| 440 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_X86_XSTATE, 0, |
| 441 | EXTENDED_REGS, x86_fill_xstateregset, x86_store_xstateregset }, |
| 442 | # ifndef __x86_64__ |
| 443 | # ifdef HAVE_PTRACE_GETFPXREGS |
| 444 | { PTRACE_GETFPXREGS, PTRACE_SETFPXREGS, 0, sizeof (elf_fpxregset_t), |
| 445 | EXTENDED_REGS, |
| 446 | x86_fill_fpxregset, x86_store_fpxregset }, |
| 447 | # endif |
| 448 | # endif |
| 449 | { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, sizeof (elf_fpregset_t), |
| 450 | FP_REGS, |
| 451 | x86_fill_fpregset, x86_store_fpregset }, |
| 452 | #endif /* HAVE_PTRACE_GETREGS */ |
| 453 | NULL_REGSET |
| 454 | }; |
| 455 | |
| 456 | static CORE_ADDR |
| 457 | x86_get_pc (struct regcache *regcache) |
| 458 | { |
| 459 | int use_64bit = register_size (regcache->tdesc, 0) == 8; |
| 460 | |
| 461 | if (use_64bit) |
| 462 | { |
| 463 | uint64_t pc; |
| 464 | |
| 465 | collect_register_by_name (regcache, "rip", &pc); |
| 466 | return (CORE_ADDR) pc; |
| 467 | } |
| 468 | else |
| 469 | { |
| 470 | uint32_t pc; |
| 471 | |
| 472 | collect_register_by_name (regcache, "eip", &pc); |
| 473 | return (CORE_ADDR) pc; |
| 474 | } |
| 475 | } |
| 476 | |
| 477 | static void |
| 478 | x86_set_pc (struct regcache *regcache, CORE_ADDR pc) |
| 479 | { |
| 480 | int use_64bit = register_size (regcache->tdesc, 0) == 8; |
| 481 | |
| 482 | if (use_64bit) |
| 483 | { |
| 484 | uint64_t newpc = pc; |
| 485 | |
| 486 | supply_register_by_name (regcache, "rip", &newpc); |
| 487 | } |
| 488 | else |
| 489 | { |
| 490 | uint32_t newpc = pc; |
| 491 | |
| 492 | supply_register_by_name (regcache, "eip", &newpc); |
| 493 | } |
| 494 | } |
| 495 | \f |
| 496 | static const gdb_byte x86_breakpoint[] = { 0xCC }; |
| 497 | #define x86_breakpoint_len 1 |
| 498 | |
| 499 | static int |
| 500 | x86_breakpoint_at (CORE_ADDR pc) |
| 501 | { |
| 502 | unsigned char c; |
| 503 | |
| 504 | (*the_target->read_memory) (pc, &c, 1); |
| 505 | if (c == 0xCC) |
| 506 | return 1; |
| 507 | |
| 508 | return 0; |
| 509 | } |
| 510 | \f |
| 511 | /* Low-level function vector. */ |
| 512 | struct x86_dr_low_type x86_dr_low = |
| 513 | { |
| 514 | x86_linux_dr_set_control, |
| 515 | x86_linux_dr_set_addr, |
| 516 | x86_linux_dr_get_addr, |
| 517 | x86_linux_dr_get_status, |
| 518 | x86_linux_dr_get_control, |
| 519 | sizeof (void *), |
| 520 | }; |
| 521 | \f |
| 522 | /* Breakpoint/Watchpoint support. */ |
| 523 | |
| 524 | static int |
| 525 | x86_supports_z_point_type (char z_type) |
| 526 | { |
| 527 | switch (z_type) |
| 528 | { |
| 529 | case Z_PACKET_SW_BP: |
| 530 | case Z_PACKET_HW_BP: |
| 531 | case Z_PACKET_WRITE_WP: |
| 532 | case Z_PACKET_ACCESS_WP: |
| 533 | return 1; |
| 534 | default: |
| 535 | return 0; |
| 536 | } |
| 537 | } |
| 538 | |
| 539 | static int |
| 540 | x86_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, |
| 541 | int size, struct raw_breakpoint *bp) |
| 542 | { |
| 543 | struct process_info *proc = current_process (); |
| 544 | |
| 545 | switch (type) |
| 546 | { |
| 547 | case raw_bkpt_type_hw: |
| 548 | case raw_bkpt_type_write_wp: |
| 549 | case raw_bkpt_type_access_wp: |
| 550 | { |
| 551 | enum target_hw_bp_type hw_type |
| 552 | = raw_bkpt_type_to_target_hw_bp_type (type); |
| 553 | struct x86_debug_reg_state *state |
| 554 | = &proc->priv->arch_private->debug_reg_state; |
| 555 | |
| 556 | return x86_dr_insert_watchpoint (state, hw_type, addr, size); |
| 557 | } |
| 558 | |
| 559 | default: |
| 560 | /* Unsupported. */ |
| 561 | return 1; |
| 562 | } |
| 563 | } |
| 564 | |
| 565 | static int |
| 566 | x86_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, |
| 567 | int size, struct raw_breakpoint *bp) |
| 568 | { |
| 569 | struct process_info *proc = current_process (); |
| 570 | |
| 571 | switch (type) |
| 572 | { |
| 573 | case raw_bkpt_type_hw: |
| 574 | case raw_bkpt_type_write_wp: |
| 575 | case raw_bkpt_type_access_wp: |
| 576 | { |
| 577 | enum target_hw_bp_type hw_type |
| 578 | = raw_bkpt_type_to_target_hw_bp_type (type); |
| 579 | struct x86_debug_reg_state *state |
| 580 | = &proc->priv->arch_private->debug_reg_state; |
| 581 | |
| 582 | return x86_dr_remove_watchpoint (state, hw_type, addr, size); |
| 583 | } |
| 584 | default: |
| 585 | /* Unsupported. */ |
| 586 | return 1; |
| 587 | } |
| 588 | } |
| 589 | |
| 590 | static int |
| 591 | x86_stopped_by_watchpoint (void) |
| 592 | { |
| 593 | struct process_info *proc = current_process (); |
| 594 | return x86_dr_stopped_by_watchpoint (&proc->priv->arch_private->debug_reg_state); |
| 595 | } |
| 596 | |
| 597 | static CORE_ADDR |
| 598 | x86_stopped_data_address (void) |
| 599 | { |
| 600 | struct process_info *proc = current_process (); |
| 601 | CORE_ADDR addr; |
| 602 | if (x86_dr_stopped_data_address (&proc->priv->arch_private->debug_reg_state, |
| 603 | &addr)) |
| 604 | return addr; |
| 605 | return 0; |
| 606 | } |
| 607 | \f |
| 608 | /* Called when a new process is created. */ |
| 609 | |
| 610 | static struct arch_process_info * |
| 611 | x86_linux_new_process (void) |
| 612 | { |
| 613 | struct arch_process_info *info = XCNEW (struct arch_process_info); |
| 614 | |
| 615 | x86_low_init_dregs (&info->debug_reg_state); |
| 616 | |
| 617 | return info; |
| 618 | } |
| 619 | |
| 620 | /* Target routine for linux_new_fork. */ |
| 621 | |
| 622 | static void |
| 623 | x86_linux_new_fork (struct process_info *parent, struct process_info *child) |
| 624 | { |
| 625 | /* These are allocated by linux_add_process. */ |
| 626 | gdb_assert (parent->priv != NULL |
| 627 | && parent->priv->arch_private != NULL); |
| 628 | gdb_assert (child->priv != NULL |
| 629 | && child->priv->arch_private != NULL); |
| 630 | |
| 631 | /* Linux kernel before 2.6.33 commit |
| 632 | 72f674d203cd230426437cdcf7dd6f681dad8b0d |
| 633 | will inherit hardware debug registers from parent |
| 634 | on fork/vfork/clone. Newer Linux kernels create such tasks with |
| 635 | zeroed debug registers. |
| 636 | |
| 637 | GDB core assumes the child inherits the watchpoints/hw |
| 638 | breakpoints of the parent, and will remove them all from the |
| 639 | forked off process. Copy the debug registers mirrors into the |
| 640 | new process so that all breakpoints and watchpoints can be |
| 641 | removed together. The debug registers mirror will become zeroed |
| 642 | in the end before detaching the forked off process, thus making |
| 643 | this compatible with older Linux kernels too. */ |
| 644 | |
| 645 | *child->priv->arch_private = *parent->priv->arch_private; |
| 646 | } |
| 647 | |
| 648 | /* See nat/x86-dregs.h. */ |
| 649 | |
| 650 | struct x86_debug_reg_state * |
| 651 | x86_debug_reg_state (pid_t pid) |
| 652 | { |
| 653 | struct process_info *proc = find_process_pid (pid); |
| 654 | |
| 655 | return &proc->priv->arch_private->debug_reg_state; |
| 656 | } |
| 657 | \f |
| 658 | /* When GDBSERVER is built as a 64-bit application on linux, the |
| 659 | PTRACE_GETSIGINFO data is always presented in 64-bit layout. Since |
| 660 | debugging a 32-bit inferior with a 64-bit GDBSERVER should look the same |
| 661 | as debugging it with a 32-bit GDBSERVER, we do the 32-bit <-> 64-bit |
| 662 | conversion in-place ourselves. */ |
| 663 | |
| 664 | /* Convert a ptrace/host siginfo object, into/from the siginfo in the |
| 665 | layout of the inferiors' architecture. Returns true if any |
| 666 | conversion was done; false otherwise. If DIRECTION is 1, then copy |
| 667 | from INF to PTRACE. If DIRECTION is 0, copy from PTRACE to |
| 668 | INF. */ |
| 669 | |
| 670 | static int |
| 671 | x86_siginfo_fixup (siginfo_t *ptrace, gdb_byte *inf, int direction) |
| 672 | { |
| 673 | #ifdef __x86_64__ |
| 674 | unsigned int machine; |
| 675 | int tid = lwpid_of (current_thread); |
| 676 | int is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine); |
| 677 | |
| 678 | /* Is the inferior 32-bit? If so, then fixup the siginfo object. */ |
| 679 | if (!is_64bit_tdesc ()) |
| 680 | return amd64_linux_siginfo_fixup_common (ptrace, inf, direction, |
| 681 | FIXUP_32); |
| 682 | /* No fixup for native x32 GDB. */ |
| 683 | else if (!is_elf64 && sizeof (void *) == 8) |
| 684 | return amd64_linux_siginfo_fixup_common (ptrace, inf, direction, |
| 685 | FIXUP_X32); |
| 686 | #endif |
| 687 | |
| 688 | return 0; |
| 689 | } |
| 690 | \f |
| 691 | static int use_xml; |
| 692 | |
| 693 | /* Format of XSAVE extended state is: |
| 694 | struct |
| 695 | { |
| 696 | fxsave_bytes[0..463] |
| 697 | sw_usable_bytes[464..511] |
| 698 | xstate_hdr_bytes[512..575] |
| 699 | avx_bytes[576..831] |
| 700 | future_state etc |
| 701 | }; |
| 702 | |
| 703 | Same memory layout will be used for the coredump NT_X86_XSTATE |
| 704 | representing the XSAVE extended state registers. |
| 705 | |
| 706 | The first 8 bytes of the sw_usable_bytes[464..467] is the OS enabled |
| 707 | extended state mask, which is the same as the extended control register |
| 708 | 0 (the XFEATURE_ENABLED_MASK register), XCR0. We can use this mask |
| 709 | together with the mask saved in the xstate_hdr_bytes to determine what |
| 710 | states the processor/OS supports and what state, used or initialized, |
| 711 | the process/thread is in. */ |
| 712 | #define I386_LINUX_XSAVE_XCR0_OFFSET 464 |
| 713 | |
| 714 | /* Does the current host support the GETFPXREGS request? The header |
| 715 | file may or may not define it, and even if it is defined, the |
| 716 | kernel will return EIO if it's running on a pre-SSE processor. */ |
| 717 | int have_ptrace_getfpxregs = |
| 718 | #ifdef HAVE_PTRACE_GETFPXREGS |
| 719 | -1 |
| 720 | #else |
| 721 | 0 |
| 722 | #endif |
| 723 | ; |
| 724 | |
| 725 | /* Get Linux/x86 target description from running target. */ |
| 726 | |
| 727 | static const struct target_desc * |
| 728 | x86_linux_read_description (void) |
| 729 | { |
| 730 | unsigned int machine; |
| 731 | int is_elf64; |
| 732 | int xcr0_features; |
| 733 | int tid; |
| 734 | static uint64_t xcr0; |
| 735 | struct regset_info *regset; |
| 736 | |
| 737 | tid = lwpid_of (current_thread); |
| 738 | |
| 739 | is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine); |
| 740 | |
| 741 | if (sizeof (void *) == 4) |
| 742 | { |
| 743 | if (is_elf64 > 0) |
| 744 | error (_("Can't debug 64-bit process with 32-bit GDBserver")); |
| 745 | #ifndef __x86_64__ |
| 746 | else if (machine == EM_X86_64) |
| 747 | error (_("Can't debug x86-64 process with 32-bit GDBserver")); |
| 748 | #endif |
| 749 | } |
| 750 | |
| 751 | #if !defined __x86_64__ && defined HAVE_PTRACE_GETFPXREGS |
| 752 | if (machine == EM_386 && have_ptrace_getfpxregs == -1) |
| 753 | { |
| 754 | elf_fpxregset_t fpxregs; |
| 755 | |
| 756 | if (ptrace (PTRACE_GETFPXREGS, tid, 0, (long) &fpxregs) < 0) |
| 757 | { |
| 758 | have_ptrace_getfpxregs = 0; |
| 759 | have_ptrace_getregset = 0; |
| 760 | return i386_linux_read_description (X86_XSTATE_X87); |
| 761 | } |
| 762 | else |
| 763 | have_ptrace_getfpxregs = 1; |
| 764 | } |
| 765 | #endif |
| 766 | |
| 767 | if (!use_xml) |
| 768 | { |
| 769 | x86_xcr0 = X86_XSTATE_SSE_MASK; |
| 770 | |
| 771 | /* Don't use XML. */ |
| 772 | #ifdef __x86_64__ |
| 773 | if (machine == EM_X86_64) |
| 774 | return tdesc_amd64_linux_no_xml; |
| 775 | else |
| 776 | #endif |
| 777 | return tdesc_i386_linux_no_xml; |
| 778 | } |
| 779 | |
| 780 | if (have_ptrace_getregset == -1) |
| 781 | { |
| 782 | uint64_t xstateregs[(X86_XSTATE_SSE_SIZE / sizeof (uint64_t))]; |
| 783 | struct iovec iov; |
| 784 | |
| 785 | iov.iov_base = xstateregs; |
| 786 | iov.iov_len = sizeof (xstateregs); |
| 787 | |
| 788 | /* Check if PTRACE_GETREGSET works. */ |
| 789 | if (ptrace (PTRACE_GETREGSET, tid, |
| 790 | (unsigned int) NT_X86_XSTATE, (long) &iov) < 0) |
| 791 | have_ptrace_getregset = 0; |
| 792 | else |
| 793 | { |
| 794 | have_ptrace_getregset = 1; |
| 795 | |
| 796 | /* Get XCR0 from XSAVE extended state. */ |
| 797 | xcr0 = xstateregs[(I386_LINUX_XSAVE_XCR0_OFFSET |
| 798 | / sizeof (uint64_t))]; |
| 799 | |
| 800 | /* Use PTRACE_GETREGSET if it is available. */ |
| 801 | for (regset = x86_regsets; |
| 802 | regset->fill_function != NULL; regset++) |
| 803 | if (regset->get_request == PTRACE_GETREGSET) |
| 804 | regset->size = X86_XSTATE_SIZE (xcr0); |
| 805 | else if (regset->type != GENERAL_REGS) |
| 806 | regset->size = 0; |
| 807 | } |
| 808 | } |
| 809 | |
| 810 | /* Check the native XCR0 only if PTRACE_GETREGSET is available. */ |
| 811 | xcr0_features = (have_ptrace_getregset |
| 812 | && (xcr0 & X86_XSTATE_ALL_MASK)); |
| 813 | |
| 814 | if (xcr0_features) |
| 815 | x86_xcr0 = xcr0; |
| 816 | |
| 817 | if (machine == EM_X86_64) |
| 818 | { |
| 819 | #ifdef __x86_64__ |
| 820 | if (is_elf64) |
| 821 | { |
| 822 | if (xcr0_features) |
| 823 | { |
| 824 | switch (xcr0 & X86_XSTATE_ALL_MASK) |
| 825 | { |
| 826 | case X86_XSTATE_AVX_MPX_AVX512_PKU_MASK: |
| 827 | return tdesc_amd64_avx_mpx_avx512_pku_linux; |
| 828 | |
| 829 | case X86_XSTATE_AVX_AVX512_MASK: |
| 830 | return tdesc_amd64_avx_avx512_linux; |
| 831 | |
| 832 | case X86_XSTATE_AVX_MPX_MASK: |
| 833 | return tdesc_amd64_avx_mpx_linux; |
| 834 | |
| 835 | case X86_XSTATE_MPX_MASK: |
| 836 | return tdesc_amd64_mpx_linux; |
| 837 | |
| 838 | case X86_XSTATE_AVX_MASK: |
| 839 | return tdesc_amd64_avx_linux; |
| 840 | |
| 841 | default: |
| 842 | return tdesc_amd64_linux; |
| 843 | } |
| 844 | } |
| 845 | else |
| 846 | return tdesc_amd64_linux; |
| 847 | } |
| 848 | else |
| 849 | { |
| 850 | if (xcr0_features) |
| 851 | { |
| 852 | switch (xcr0 & X86_XSTATE_ALL_MASK) |
| 853 | { |
| 854 | case X86_XSTATE_AVX_MPX_AVX512_PKU_MASK: |
| 855 | /* No x32 MPX and PKU, fall back to avx_avx512. */ |
| 856 | return tdesc_x32_avx_avx512_linux; |
| 857 | |
| 858 | case X86_XSTATE_AVX_AVX512_MASK: |
| 859 | return tdesc_x32_avx_avx512_linux; |
| 860 | |
| 861 | case X86_XSTATE_MPX_MASK: /* No MPX on x32. */ |
| 862 | case X86_XSTATE_AVX_MASK: |
| 863 | return tdesc_x32_avx_linux; |
| 864 | |
| 865 | default: |
| 866 | return tdesc_x32_linux; |
| 867 | } |
| 868 | } |
| 869 | else |
| 870 | return tdesc_x32_linux; |
| 871 | } |
| 872 | #endif |
| 873 | } |
| 874 | else |
| 875 | { |
| 876 | const target_desc *tdesc = NULL; |
| 877 | |
| 878 | if (xcr0_features) |
| 879 | tdesc = i386_linux_read_description (xcr0 & X86_XSTATE_ALL_MASK); |
| 880 | |
| 881 | if (tdesc == NULL) |
| 882 | tdesc = i386_linux_read_description (X86_XSTATE_SSE); |
| 883 | |
| 884 | return tdesc; |
| 885 | } |
| 886 | |
| 887 | gdb_assert_not_reached ("failed to return tdesc"); |
| 888 | } |
| 889 | |
| 890 | /* Callback for find_inferior. Stops iteration when a thread with a |
| 891 | given PID is found. */ |
| 892 | |
| 893 | static int |
| 894 | same_process_callback (struct inferior_list_entry *entry, void *data) |
| 895 | { |
| 896 | int pid = *(int *) data; |
| 897 | |
| 898 | return (ptid_get_pid (entry->id) == pid); |
| 899 | } |
| 900 | |
| 901 | /* Callback for for_each_inferior. Calls the arch_setup routine for |
| 902 | each process. */ |
| 903 | |
| 904 | static void |
| 905 | x86_arch_setup_process_callback (struct inferior_list_entry *entry) |
| 906 | { |
| 907 | int pid = ptid_get_pid (entry->id); |
| 908 | |
| 909 | /* Look up any thread of this processes. */ |
| 910 | current_thread |
| 911 | = (struct thread_info *) find_inferior (&all_threads, |
| 912 | same_process_callback, &pid); |
| 913 | |
| 914 | the_low_target.arch_setup (); |
| 915 | } |
| 916 | |
| 917 | /* Update all the target description of all processes; a new GDB |
| 918 | connected, and it may or not support xml target descriptions. */ |
| 919 | |
| 920 | static void |
| 921 | x86_linux_update_xmltarget (void) |
| 922 | { |
| 923 | struct thread_info *saved_thread = current_thread; |
| 924 | |
| 925 | /* Before changing the register cache's internal layout, flush the |
| 926 | contents of the current valid caches back to the threads, and |
| 927 | release the current regcache objects. */ |
| 928 | regcache_release (); |
| 929 | |
| 930 | for_each_inferior (&all_processes, x86_arch_setup_process_callback); |
| 931 | |
| 932 | current_thread = saved_thread; |
| 933 | } |
| 934 | |
| 935 | /* Process qSupported query, "xmlRegisters=". Update the buffer size for |
| 936 | PTRACE_GETREGSET. */ |
| 937 | |
| 938 | static void |
| 939 | x86_linux_process_qsupported (char **features, int count) |
| 940 | { |
| 941 | int i; |
| 942 | |
| 943 | /* Return if gdb doesn't support XML. If gdb sends "xmlRegisters=" |
| 944 | with "i386" in qSupported query, it supports x86 XML target |
| 945 | descriptions. */ |
| 946 | use_xml = 0; |
| 947 | for (i = 0; i < count; i++) |
| 948 | { |
| 949 | const char *feature = features[i]; |
| 950 | |
| 951 | if (startswith (feature, "xmlRegisters=")) |
| 952 | { |
| 953 | char *copy = xstrdup (feature + 13); |
| 954 | char *p; |
| 955 | |
| 956 | for (p = strtok (copy, ","); p != NULL; p = strtok (NULL, ",")) |
| 957 | { |
| 958 | if (strcmp (p, "i386") == 0) |
| 959 | { |
| 960 | use_xml = 1; |
| 961 | break; |
| 962 | } |
| 963 | } |
| 964 | |
| 965 | free (copy); |
| 966 | } |
| 967 | } |
| 968 | x86_linux_update_xmltarget (); |
| 969 | } |
| 970 | |
| 971 | /* Common for x86/x86-64. */ |
| 972 | |
| 973 | static struct regsets_info x86_regsets_info = |
| 974 | { |
| 975 | x86_regsets, /* regsets */ |
| 976 | 0, /* num_regsets */ |
| 977 | NULL, /* disabled_regsets */ |
| 978 | }; |
| 979 | |
| 980 | #ifdef __x86_64__ |
| 981 | static struct regs_info amd64_linux_regs_info = |
| 982 | { |
| 983 | NULL, /* regset_bitmap */ |
| 984 | NULL, /* usrregs_info */ |
| 985 | &x86_regsets_info |
| 986 | }; |
| 987 | #endif |
| 988 | static struct usrregs_info i386_linux_usrregs_info = |
| 989 | { |
| 990 | I386_NUM_REGS, |
| 991 | i386_regmap, |
| 992 | }; |
| 993 | |
| 994 | static struct regs_info i386_linux_regs_info = |
| 995 | { |
| 996 | NULL, /* regset_bitmap */ |
| 997 | &i386_linux_usrregs_info, |
| 998 | &x86_regsets_info |
| 999 | }; |
| 1000 | |
| 1001 | const struct regs_info * |
| 1002 | x86_linux_regs_info (void) |
| 1003 | { |
| 1004 | #ifdef __x86_64__ |
| 1005 | if (is_64bit_tdesc ()) |
| 1006 | return &amd64_linux_regs_info; |
| 1007 | else |
| 1008 | #endif |
| 1009 | return &i386_linux_regs_info; |
| 1010 | } |
| 1011 | |
| 1012 | /* Initialize the target description for the architecture of the |
| 1013 | inferior. */ |
| 1014 | |
| 1015 | static void |
| 1016 | x86_arch_setup (void) |
| 1017 | { |
| 1018 | current_process ()->tdesc = x86_linux_read_description (); |
| 1019 | } |
| 1020 | |
| 1021 | /* Fill *SYSNO and *SYSRET with the syscall nr trapped and the syscall return |
| 1022 | code. This should only be called if LWP got a SYSCALL_SIGTRAP. */ |
| 1023 | |
| 1024 | static void |
| 1025 | x86_get_syscall_trapinfo (struct regcache *regcache, int *sysno) |
| 1026 | { |
| 1027 | int use_64bit = register_size (regcache->tdesc, 0) == 8; |
| 1028 | |
| 1029 | if (use_64bit) |
| 1030 | { |
| 1031 | long l_sysno; |
| 1032 | |
| 1033 | collect_register_by_name (regcache, "orig_rax", &l_sysno); |
| 1034 | *sysno = (int) l_sysno; |
| 1035 | } |
| 1036 | else |
| 1037 | collect_register_by_name (regcache, "orig_eax", sysno); |
| 1038 | } |
| 1039 | |
| 1040 | static int |
| 1041 | x86_supports_tracepoints (void) |
| 1042 | { |
| 1043 | return 1; |
| 1044 | } |
| 1045 | |
| 1046 | static void |
| 1047 | append_insns (CORE_ADDR *to, size_t len, const unsigned char *buf) |
| 1048 | { |
| 1049 | write_inferior_memory (*to, buf, len); |
| 1050 | *to += len; |
| 1051 | } |
| 1052 | |
| 1053 | static int |
| 1054 | push_opcode (unsigned char *buf, const char *op) |
| 1055 | { |
| 1056 | unsigned char *buf_org = buf; |
| 1057 | |
| 1058 | while (1) |
| 1059 | { |
| 1060 | char *endptr; |
| 1061 | unsigned long ul = strtoul (op, &endptr, 16); |
| 1062 | |
| 1063 | if (endptr == op) |
| 1064 | break; |
| 1065 | |
| 1066 | *buf++ = ul; |
| 1067 | op = endptr; |
| 1068 | } |
| 1069 | |
| 1070 | return buf - buf_org; |
| 1071 | } |
| 1072 | |
| 1073 | #ifdef __x86_64__ |
| 1074 | |
| 1075 | /* Build a jump pad that saves registers and calls a collection |
| 1076 | function. Writes a jump instruction to the jump pad to |
| 1077 | JJUMPAD_INSN. The caller is responsible to write it in at the |
| 1078 | tracepoint address. */ |
| 1079 | |
| 1080 | static int |
| 1081 | amd64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr, |
| 1082 | CORE_ADDR collector, |
| 1083 | CORE_ADDR lockaddr, |
| 1084 | ULONGEST orig_size, |
| 1085 | CORE_ADDR *jump_entry, |
| 1086 | CORE_ADDR *trampoline, |
| 1087 | ULONGEST *trampoline_size, |
| 1088 | unsigned char *jjump_pad_insn, |
| 1089 | ULONGEST *jjump_pad_insn_size, |
| 1090 | CORE_ADDR *adjusted_insn_addr, |
| 1091 | CORE_ADDR *adjusted_insn_addr_end, |
| 1092 | char *err) |
| 1093 | { |
| 1094 | unsigned char buf[40]; |
| 1095 | int i, offset; |
| 1096 | int64_t loffset; |
| 1097 | |
| 1098 | CORE_ADDR buildaddr = *jump_entry; |
| 1099 | |
| 1100 | /* Build the jump pad. */ |
| 1101 | |
| 1102 | /* First, do tracepoint data collection. Save registers. */ |
| 1103 | i = 0; |
| 1104 | /* Need to ensure stack pointer saved first. */ |
| 1105 | buf[i++] = 0x54; /* push %rsp */ |
| 1106 | buf[i++] = 0x55; /* push %rbp */ |
| 1107 | buf[i++] = 0x57; /* push %rdi */ |
| 1108 | buf[i++] = 0x56; /* push %rsi */ |
| 1109 | buf[i++] = 0x52; /* push %rdx */ |
| 1110 | buf[i++] = 0x51; /* push %rcx */ |
| 1111 | buf[i++] = 0x53; /* push %rbx */ |
| 1112 | buf[i++] = 0x50; /* push %rax */ |
| 1113 | buf[i++] = 0x41; buf[i++] = 0x57; /* push %r15 */ |
| 1114 | buf[i++] = 0x41; buf[i++] = 0x56; /* push %r14 */ |
| 1115 | buf[i++] = 0x41; buf[i++] = 0x55; /* push %r13 */ |
| 1116 | buf[i++] = 0x41; buf[i++] = 0x54; /* push %r12 */ |
| 1117 | buf[i++] = 0x41; buf[i++] = 0x53; /* push %r11 */ |
| 1118 | buf[i++] = 0x41; buf[i++] = 0x52; /* push %r10 */ |
| 1119 | buf[i++] = 0x41; buf[i++] = 0x51; /* push %r9 */ |
| 1120 | buf[i++] = 0x41; buf[i++] = 0x50; /* push %r8 */ |
| 1121 | buf[i++] = 0x9c; /* pushfq */ |
| 1122 | buf[i++] = 0x48; /* movabs <addr>,%rdi */ |
| 1123 | buf[i++] = 0xbf; |
| 1124 | memcpy (buf + i, &tpaddr, 8); |
| 1125 | i += 8; |
| 1126 | buf[i++] = 0x57; /* push %rdi */ |
| 1127 | append_insns (&buildaddr, i, buf); |
| 1128 | |
| 1129 | /* Stack space for the collecting_t object. */ |
| 1130 | i = 0; |
| 1131 | i += push_opcode (&buf[i], "48 83 ec 18"); /* sub $0x18,%rsp */ |
| 1132 | i += push_opcode (&buf[i], "48 b8"); /* mov <tpoint>,%rax */ |
| 1133 | memcpy (buf + i, &tpoint, 8); |
| 1134 | i += 8; |
| 1135 | i += push_opcode (&buf[i], "48 89 04 24"); /* mov %rax,(%rsp) */ |
| 1136 | i += push_opcode (&buf[i], |
| 1137 | "64 48 8b 04 25 00 00 00 00"); /* mov %fs:0x0,%rax */ |
| 1138 | i += push_opcode (&buf[i], "48 89 44 24 08"); /* mov %rax,0x8(%rsp) */ |
| 1139 | append_insns (&buildaddr, i, buf); |
| 1140 | |
| 1141 | /* spin-lock. */ |
| 1142 | i = 0; |
| 1143 | i += push_opcode (&buf[i], "48 be"); /* movl <lockaddr>,%rsi */ |
| 1144 | memcpy (&buf[i], (void *) &lockaddr, 8); |
| 1145 | i += 8; |
| 1146 | i += push_opcode (&buf[i], "48 89 e1"); /* mov %rsp,%rcx */ |
| 1147 | i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */ |
| 1148 | i += push_opcode (&buf[i], "f0 48 0f b1 0e"); /* lock cmpxchg %rcx,(%rsi) */ |
| 1149 | i += push_opcode (&buf[i], "48 85 c0"); /* test %rax,%rax */ |
| 1150 | i += push_opcode (&buf[i], "75 f4"); /* jne <again> */ |
| 1151 | append_insns (&buildaddr, i, buf); |
| 1152 | |
| 1153 | /* Set up the gdb_collect call. */ |
| 1154 | /* At this point, (stack pointer + 0x18) is the base of our saved |
| 1155 | register block. */ |
| 1156 | |
| 1157 | i = 0; |
| 1158 | i += push_opcode (&buf[i], "48 89 e6"); /* mov %rsp,%rsi */ |
| 1159 | i += push_opcode (&buf[i], "48 83 c6 18"); /* add $0x18,%rsi */ |
| 1160 | |
| 1161 | /* tpoint address may be 64-bit wide. */ |
| 1162 | i += push_opcode (&buf[i], "48 bf"); /* movl <addr>,%rdi */ |
| 1163 | memcpy (buf + i, &tpoint, 8); |
| 1164 | i += 8; |
| 1165 | append_insns (&buildaddr, i, buf); |
| 1166 | |
| 1167 | /* The collector function being in the shared library, may be |
| 1168 | >31-bits away off the jump pad. */ |
| 1169 | i = 0; |
| 1170 | i += push_opcode (&buf[i], "48 b8"); /* mov $collector,%rax */ |
| 1171 | memcpy (buf + i, &collector, 8); |
| 1172 | i += 8; |
| 1173 | i += push_opcode (&buf[i], "ff d0"); /* callq *%rax */ |
| 1174 | append_insns (&buildaddr, i, buf); |
| 1175 | |
| 1176 | /* Clear the spin-lock. */ |
| 1177 | i = 0; |
| 1178 | i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */ |
| 1179 | i += push_opcode (&buf[i], "48 a3"); /* mov %rax, lockaddr */ |
| 1180 | memcpy (buf + i, &lockaddr, 8); |
| 1181 | i += 8; |
| 1182 | append_insns (&buildaddr, i, buf); |
| 1183 | |
| 1184 | /* Remove stack that had been used for the collect_t object. */ |
| 1185 | i = 0; |
| 1186 | i += push_opcode (&buf[i], "48 83 c4 18"); /* add $0x18,%rsp */ |
| 1187 | append_insns (&buildaddr, i, buf); |
| 1188 | |
| 1189 | /* Restore register state. */ |
| 1190 | i = 0; |
| 1191 | buf[i++] = 0x48; /* add $0x8,%rsp */ |
| 1192 | buf[i++] = 0x83; |
| 1193 | buf[i++] = 0xc4; |
| 1194 | buf[i++] = 0x08; |
| 1195 | buf[i++] = 0x9d; /* popfq */ |
| 1196 | buf[i++] = 0x41; buf[i++] = 0x58; /* pop %r8 */ |
| 1197 | buf[i++] = 0x41; buf[i++] = 0x59; /* pop %r9 */ |
| 1198 | buf[i++] = 0x41; buf[i++] = 0x5a; /* pop %r10 */ |
| 1199 | buf[i++] = 0x41; buf[i++] = 0x5b; /* pop %r11 */ |
| 1200 | buf[i++] = 0x41; buf[i++] = 0x5c; /* pop %r12 */ |
| 1201 | buf[i++] = 0x41; buf[i++] = 0x5d; /* pop %r13 */ |
| 1202 | buf[i++] = 0x41; buf[i++] = 0x5e; /* pop %r14 */ |
| 1203 | buf[i++] = 0x41; buf[i++] = 0x5f; /* pop %r15 */ |
| 1204 | buf[i++] = 0x58; /* pop %rax */ |
| 1205 | buf[i++] = 0x5b; /* pop %rbx */ |
| 1206 | buf[i++] = 0x59; /* pop %rcx */ |
| 1207 | buf[i++] = 0x5a; /* pop %rdx */ |
| 1208 | buf[i++] = 0x5e; /* pop %rsi */ |
| 1209 | buf[i++] = 0x5f; /* pop %rdi */ |
| 1210 | buf[i++] = 0x5d; /* pop %rbp */ |
| 1211 | buf[i++] = 0x5c; /* pop %rsp */ |
| 1212 | append_insns (&buildaddr, i, buf); |
| 1213 | |
| 1214 | /* Now, adjust the original instruction to execute in the jump |
| 1215 | pad. */ |
| 1216 | *adjusted_insn_addr = buildaddr; |
| 1217 | relocate_instruction (&buildaddr, tpaddr); |
| 1218 | *adjusted_insn_addr_end = buildaddr; |
| 1219 | |
| 1220 | /* Finally, write a jump back to the program. */ |
| 1221 | |
| 1222 | loffset = (tpaddr + orig_size) - (buildaddr + sizeof (jump_insn)); |
| 1223 | if (loffset > INT_MAX || loffset < INT_MIN) |
| 1224 | { |
| 1225 | sprintf (err, |
| 1226 | "E.Jump back from jump pad too far from tracepoint " |
| 1227 | "(offset 0x%" PRIx64 " > int32).", loffset); |
| 1228 | return 1; |
| 1229 | } |
| 1230 | |
| 1231 | offset = (int) loffset; |
| 1232 | memcpy (buf, jump_insn, sizeof (jump_insn)); |
| 1233 | memcpy (buf + 1, &offset, 4); |
| 1234 | append_insns (&buildaddr, sizeof (jump_insn), buf); |
| 1235 | |
| 1236 | /* The jump pad is now built. Wire in a jump to our jump pad. This |
| 1237 | is always done last (by our caller actually), so that we can |
| 1238 | install fast tracepoints with threads running. This relies on |
| 1239 | the agent's atomic write support. */ |
| 1240 | loffset = *jump_entry - (tpaddr + sizeof (jump_insn)); |
| 1241 | if (loffset > INT_MAX || loffset < INT_MIN) |
| 1242 | { |
| 1243 | sprintf (err, |
| 1244 | "E.Jump pad too far from tracepoint " |
| 1245 | "(offset 0x%" PRIx64 " > int32).", loffset); |
| 1246 | return 1; |
| 1247 | } |
| 1248 | |
| 1249 | offset = (int) loffset; |
| 1250 | |
| 1251 | memcpy (buf, jump_insn, sizeof (jump_insn)); |
| 1252 | memcpy (buf + 1, &offset, 4); |
| 1253 | memcpy (jjump_pad_insn, buf, sizeof (jump_insn)); |
| 1254 | *jjump_pad_insn_size = sizeof (jump_insn); |
| 1255 | |
| 1256 | /* Return the end address of our pad. */ |
| 1257 | *jump_entry = buildaddr; |
| 1258 | |
| 1259 | return 0; |
| 1260 | } |
| 1261 | |
| 1262 | #endif /* __x86_64__ */ |
| 1263 | |
| 1264 | /* Build a jump pad that saves registers and calls a collection |
| 1265 | function. Writes a jump instruction to the jump pad to |
| 1266 | JJUMPAD_INSN. The caller is responsible to write it in at the |
| 1267 | tracepoint address. */ |
| 1268 | |
| 1269 | static int |
| 1270 | i386_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr, |
| 1271 | CORE_ADDR collector, |
| 1272 | CORE_ADDR lockaddr, |
| 1273 | ULONGEST orig_size, |
| 1274 | CORE_ADDR *jump_entry, |
| 1275 | CORE_ADDR *trampoline, |
| 1276 | ULONGEST *trampoline_size, |
| 1277 | unsigned char *jjump_pad_insn, |
| 1278 | ULONGEST *jjump_pad_insn_size, |
| 1279 | CORE_ADDR *adjusted_insn_addr, |
| 1280 | CORE_ADDR *adjusted_insn_addr_end, |
| 1281 | char *err) |
| 1282 | { |
| 1283 | unsigned char buf[0x100]; |
| 1284 | int i, offset; |
| 1285 | CORE_ADDR buildaddr = *jump_entry; |
| 1286 | |
| 1287 | /* Build the jump pad. */ |
| 1288 | |
| 1289 | /* First, do tracepoint data collection. Save registers. */ |
| 1290 | i = 0; |
| 1291 | buf[i++] = 0x60; /* pushad */ |
| 1292 | buf[i++] = 0x68; /* push tpaddr aka $pc */ |
| 1293 | *((int *)(buf + i)) = (int) tpaddr; |
| 1294 | i += 4; |
| 1295 | buf[i++] = 0x9c; /* pushf */ |
| 1296 | buf[i++] = 0x1e; /* push %ds */ |
| 1297 | buf[i++] = 0x06; /* push %es */ |
| 1298 | buf[i++] = 0x0f; /* push %fs */ |
| 1299 | buf[i++] = 0xa0; |
| 1300 | buf[i++] = 0x0f; /* push %gs */ |
| 1301 | buf[i++] = 0xa8; |
| 1302 | buf[i++] = 0x16; /* push %ss */ |
| 1303 | buf[i++] = 0x0e; /* push %cs */ |
| 1304 | append_insns (&buildaddr, i, buf); |
| 1305 | |
| 1306 | /* Stack space for the collecting_t object. */ |
| 1307 | i = 0; |
| 1308 | i += push_opcode (&buf[i], "83 ec 08"); /* sub $0x8,%esp */ |
| 1309 | |
| 1310 | /* Build the object. */ |
| 1311 | i += push_opcode (&buf[i], "b8"); /* mov <tpoint>,%eax */ |
| 1312 | memcpy (buf + i, &tpoint, 4); |
| 1313 | i += 4; |
| 1314 | i += push_opcode (&buf[i], "89 04 24"); /* mov %eax,(%esp) */ |
| 1315 | |
| 1316 | i += push_opcode (&buf[i], "65 a1 00 00 00 00"); /* mov %gs:0x0,%eax */ |
| 1317 | i += push_opcode (&buf[i], "89 44 24 04"); /* mov %eax,0x4(%esp) */ |
| 1318 | append_insns (&buildaddr, i, buf); |
| 1319 | |
| 1320 | /* spin-lock. Note this is using cmpxchg, which leaves i386 behind. |
| 1321 | If we cared for it, this could be using xchg alternatively. */ |
| 1322 | |
| 1323 | i = 0; |
| 1324 | i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */ |
| 1325 | i += push_opcode (&buf[i], "f0 0f b1 25"); /* lock cmpxchg |
| 1326 | %esp,<lockaddr> */ |
| 1327 | memcpy (&buf[i], (void *) &lockaddr, 4); |
| 1328 | i += 4; |
| 1329 | i += push_opcode (&buf[i], "85 c0"); /* test %eax,%eax */ |
| 1330 | i += push_opcode (&buf[i], "75 f2"); /* jne <again> */ |
| 1331 | append_insns (&buildaddr, i, buf); |
| 1332 | |
| 1333 | |
| 1334 | /* Set up arguments to the gdb_collect call. */ |
| 1335 | i = 0; |
| 1336 | i += push_opcode (&buf[i], "89 e0"); /* mov %esp,%eax */ |
| 1337 | i += push_opcode (&buf[i], "83 c0 08"); /* add $0x08,%eax */ |
| 1338 | i += push_opcode (&buf[i], "89 44 24 fc"); /* mov %eax,-0x4(%esp) */ |
| 1339 | append_insns (&buildaddr, i, buf); |
| 1340 | |
| 1341 | i = 0; |
| 1342 | i += push_opcode (&buf[i], "83 ec 08"); /* sub $0x8,%esp */ |
| 1343 | append_insns (&buildaddr, i, buf); |
| 1344 | |
| 1345 | i = 0; |
| 1346 | i += push_opcode (&buf[i], "c7 04 24"); /* movl <addr>,(%esp) */ |
| 1347 | memcpy (&buf[i], (void *) &tpoint, 4); |
| 1348 | i += 4; |
| 1349 | append_insns (&buildaddr, i, buf); |
| 1350 | |
| 1351 | buf[0] = 0xe8; /* call <reladdr> */ |
| 1352 | offset = collector - (buildaddr + sizeof (jump_insn)); |
| 1353 | memcpy (buf + 1, &offset, 4); |
| 1354 | append_insns (&buildaddr, 5, buf); |
| 1355 | /* Clean up after the call. */ |
| 1356 | buf[0] = 0x83; /* add $0x8,%esp */ |
| 1357 | buf[1] = 0xc4; |
| 1358 | buf[2] = 0x08; |
| 1359 | append_insns (&buildaddr, 3, buf); |
| 1360 | |
| 1361 | |
| 1362 | /* Clear the spin-lock. This would need the LOCK prefix on older |
| 1363 | broken archs. */ |
| 1364 | i = 0; |
| 1365 | i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */ |
| 1366 | i += push_opcode (&buf[i], "a3"); /* mov %eax, lockaddr */ |
| 1367 | memcpy (buf + i, &lockaddr, 4); |
| 1368 | i += 4; |
| 1369 | append_insns (&buildaddr, i, buf); |
| 1370 | |
| 1371 | |
| 1372 | /* Remove stack that had been used for the collect_t object. */ |
| 1373 | i = 0; |
| 1374 | i += push_opcode (&buf[i], "83 c4 08"); /* add $0x08,%esp */ |
| 1375 | append_insns (&buildaddr, i, buf); |
| 1376 | |
| 1377 | i = 0; |
| 1378 | buf[i++] = 0x83; /* add $0x4,%esp (no pop of %cs, assume unchanged) */ |
| 1379 | buf[i++] = 0xc4; |
| 1380 | buf[i++] = 0x04; |
| 1381 | buf[i++] = 0x17; /* pop %ss */ |
| 1382 | buf[i++] = 0x0f; /* pop %gs */ |
| 1383 | buf[i++] = 0xa9; |
| 1384 | buf[i++] = 0x0f; /* pop %fs */ |
| 1385 | buf[i++] = 0xa1; |
| 1386 | buf[i++] = 0x07; /* pop %es */ |
| 1387 | buf[i++] = 0x1f; /* pop %ds */ |
| 1388 | buf[i++] = 0x9d; /* popf */ |
| 1389 | buf[i++] = 0x83; /* add $0x4,%esp (pop of tpaddr aka $pc) */ |
| 1390 | buf[i++] = 0xc4; |
| 1391 | buf[i++] = 0x04; |
| 1392 | buf[i++] = 0x61; /* popad */ |
| 1393 | append_insns (&buildaddr, i, buf); |
| 1394 | |
| 1395 | /* Now, adjust the original instruction to execute in the jump |
| 1396 | pad. */ |
| 1397 | *adjusted_insn_addr = buildaddr; |
| 1398 | relocate_instruction (&buildaddr, tpaddr); |
| 1399 | *adjusted_insn_addr_end = buildaddr; |
| 1400 | |
| 1401 | /* Write the jump back to the program. */ |
| 1402 | offset = (tpaddr + orig_size) - (buildaddr + sizeof (jump_insn)); |
| 1403 | memcpy (buf, jump_insn, sizeof (jump_insn)); |
| 1404 | memcpy (buf + 1, &offset, 4); |
| 1405 | append_insns (&buildaddr, sizeof (jump_insn), buf); |
| 1406 | |
| 1407 | /* The jump pad is now built. Wire in a jump to our jump pad. This |
| 1408 | is always done last (by our caller actually), so that we can |
| 1409 | install fast tracepoints with threads running. This relies on |
| 1410 | the agent's atomic write support. */ |
| 1411 | if (orig_size == 4) |
| 1412 | { |
| 1413 | /* Create a trampoline. */ |
| 1414 | *trampoline_size = sizeof (jump_insn); |
| 1415 | if (!claim_trampoline_space (*trampoline_size, trampoline)) |
| 1416 | { |
| 1417 | /* No trampoline space available. */ |
| 1418 | strcpy (err, |
| 1419 | "E.Cannot allocate trampoline space needed for fast " |
| 1420 | "tracepoints on 4-byte instructions."); |
| 1421 | return 1; |
| 1422 | } |
| 1423 | |
| 1424 | offset = *jump_entry - (*trampoline + sizeof (jump_insn)); |
| 1425 | memcpy (buf, jump_insn, sizeof (jump_insn)); |
| 1426 | memcpy (buf + 1, &offset, 4); |
| 1427 | write_inferior_memory (*trampoline, buf, sizeof (jump_insn)); |
| 1428 | |
| 1429 | /* Use a 16-bit relative jump instruction to jump to the trampoline. */ |
| 1430 | offset = (*trampoline - (tpaddr + sizeof (small_jump_insn))) & 0xffff; |
| 1431 | memcpy (buf, small_jump_insn, sizeof (small_jump_insn)); |
| 1432 | memcpy (buf + 2, &offset, 2); |
| 1433 | memcpy (jjump_pad_insn, buf, sizeof (small_jump_insn)); |
| 1434 | *jjump_pad_insn_size = sizeof (small_jump_insn); |
| 1435 | } |
| 1436 | else |
| 1437 | { |
| 1438 | /* Else use a 32-bit relative jump instruction. */ |
| 1439 | offset = *jump_entry - (tpaddr + sizeof (jump_insn)); |
| 1440 | memcpy (buf, jump_insn, sizeof (jump_insn)); |
| 1441 | memcpy (buf + 1, &offset, 4); |
| 1442 | memcpy (jjump_pad_insn, buf, sizeof (jump_insn)); |
| 1443 | *jjump_pad_insn_size = sizeof (jump_insn); |
| 1444 | } |
| 1445 | |
| 1446 | /* Return the end address of our pad. */ |
| 1447 | *jump_entry = buildaddr; |
| 1448 | |
| 1449 | return 0; |
| 1450 | } |
| 1451 | |
| 1452 | static int |
| 1453 | x86_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr, |
| 1454 | CORE_ADDR collector, |
| 1455 | CORE_ADDR lockaddr, |
| 1456 | ULONGEST orig_size, |
| 1457 | CORE_ADDR *jump_entry, |
| 1458 | CORE_ADDR *trampoline, |
| 1459 | ULONGEST *trampoline_size, |
| 1460 | unsigned char *jjump_pad_insn, |
| 1461 | ULONGEST *jjump_pad_insn_size, |
| 1462 | CORE_ADDR *adjusted_insn_addr, |
| 1463 | CORE_ADDR *adjusted_insn_addr_end, |
| 1464 | char *err) |
| 1465 | { |
| 1466 | #ifdef __x86_64__ |
| 1467 | if (is_64bit_tdesc ()) |
| 1468 | return amd64_install_fast_tracepoint_jump_pad (tpoint, tpaddr, |
| 1469 | collector, lockaddr, |
| 1470 | orig_size, jump_entry, |
| 1471 | trampoline, trampoline_size, |
| 1472 | jjump_pad_insn, |
| 1473 | jjump_pad_insn_size, |
| 1474 | adjusted_insn_addr, |
| 1475 | adjusted_insn_addr_end, |
| 1476 | err); |
| 1477 | #endif |
| 1478 | |
| 1479 | return i386_install_fast_tracepoint_jump_pad (tpoint, tpaddr, |
| 1480 | collector, lockaddr, |
| 1481 | orig_size, jump_entry, |
| 1482 | trampoline, trampoline_size, |
| 1483 | jjump_pad_insn, |
| 1484 | jjump_pad_insn_size, |
| 1485 | adjusted_insn_addr, |
| 1486 | adjusted_insn_addr_end, |
| 1487 | err); |
| 1488 | } |
| 1489 | |
| 1490 | /* Return the minimum instruction length for fast tracepoints on x86/x86-64 |
| 1491 | architectures. */ |
| 1492 | |
| 1493 | static int |
| 1494 | x86_get_min_fast_tracepoint_insn_len (void) |
| 1495 | { |
| 1496 | static int warned_about_fast_tracepoints = 0; |
| 1497 | |
| 1498 | #ifdef __x86_64__ |
| 1499 | /* On x86-64, 5-byte jump instructions with a 4-byte offset are always |
| 1500 | used for fast tracepoints. */ |
| 1501 | if (is_64bit_tdesc ()) |
| 1502 | return 5; |
| 1503 | #endif |
| 1504 | |
| 1505 | if (agent_loaded_p ()) |
| 1506 | { |
| 1507 | char errbuf[IPA_BUFSIZ]; |
| 1508 | |
| 1509 | errbuf[0] = '\0'; |
| 1510 | |
| 1511 | /* On x86, if trampolines are available, then 4-byte jump instructions |
| 1512 | with a 2-byte offset may be used, otherwise 5-byte jump instructions |
| 1513 | with a 4-byte offset are used instead. */ |
| 1514 | if (have_fast_tracepoint_trampoline_buffer (errbuf)) |
| 1515 | return 4; |
| 1516 | else |
| 1517 | { |
| 1518 | /* GDB has no channel to explain to user why a shorter fast |
| 1519 | tracepoint is not possible, but at least make GDBserver |
| 1520 | mention that something has gone awry. */ |
| 1521 | if (!warned_about_fast_tracepoints) |
| 1522 | { |
| 1523 | warning ("4-byte fast tracepoints not available; %s\n", errbuf); |
| 1524 | warned_about_fast_tracepoints = 1; |
| 1525 | } |
| 1526 | return 5; |
| 1527 | } |
| 1528 | } |
| 1529 | else |
| 1530 | { |
| 1531 | /* Indicate that the minimum length is currently unknown since the IPA |
| 1532 | has not loaded yet. */ |
| 1533 | return 0; |
| 1534 | } |
| 1535 | } |
| 1536 | |
| 1537 | static void |
| 1538 | add_insns (unsigned char *start, int len) |
| 1539 | { |
| 1540 | CORE_ADDR buildaddr = current_insn_ptr; |
| 1541 | |
| 1542 | if (debug_threads) |
| 1543 | debug_printf ("Adding %d bytes of insn at %s\n", |
| 1544 | len, paddress (buildaddr)); |
| 1545 | |
| 1546 | append_insns (&buildaddr, len, start); |
| 1547 | current_insn_ptr = buildaddr; |
| 1548 | } |
| 1549 | |
| 1550 | /* Our general strategy for emitting code is to avoid specifying raw |
| 1551 | bytes whenever possible, and instead copy a block of inline asm |
| 1552 | that is embedded in the function. This is a little messy, because |
| 1553 | we need to keep the compiler from discarding what looks like dead |
| 1554 | code, plus suppress various warnings. */ |
| 1555 | |
| 1556 | #define EMIT_ASM(NAME, INSNS) \ |
| 1557 | do \ |
| 1558 | { \ |
| 1559 | extern unsigned char start_ ## NAME, end_ ## NAME; \ |
| 1560 | add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \ |
| 1561 | __asm__ ("jmp end_" #NAME "\n" \ |
| 1562 | "\t" "start_" #NAME ":" \ |
| 1563 | "\t" INSNS "\n" \ |
| 1564 | "\t" "end_" #NAME ":"); \ |
| 1565 | } while (0) |
| 1566 | |
| 1567 | #ifdef __x86_64__ |
| 1568 | |
| 1569 | #define EMIT_ASM32(NAME,INSNS) \ |
| 1570 | do \ |
| 1571 | { \ |
| 1572 | extern unsigned char start_ ## NAME, end_ ## NAME; \ |
| 1573 | add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \ |
| 1574 | __asm__ (".code32\n" \ |
| 1575 | "\t" "jmp end_" #NAME "\n" \ |
| 1576 | "\t" "start_" #NAME ":\n" \ |
| 1577 | "\t" INSNS "\n" \ |
| 1578 | "\t" "end_" #NAME ":\n" \ |
| 1579 | ".code64\n"); \ |
| 1580 | } while (0) |
| 1581 | |
| 1582 | #else |
| 1583 | |
| 1584 | #define EMIT_ASM32(NAME,INSNS) EMIT_ASM(NAME,INSNS) |
| 1585 | |
| 1586 | #endif |
| 1587 | |
| 1588 | #ifdef __x86_64__ |
| 1589 | |
| 1590 | static void |
| 1591 | amd64_emit_prologue (void) |
| 1592 | { |
| 1593 | EMIT_ASM (amd64_prologue, |
| 1594 | "pushq %rbp\n\t" |
| 1595 | "movq %rsp,%rbp\n\t" |
| 1596 | "sub $0x20,%rsp\n\t" |
| 1597 | "movq %rdi,-8(%rbp)\n\t" |
| 1598 | "movq %rsi,-16(%rbp)"); |
| 1599 | } |
| 1600 | |
| 1601 | |
| 1602 | static void |
| 1603 | amd64_emit_epilogue (void) |
| 1604 | { |
| 1605 | EMIT_ASM (amd64_epilogue, |
| 1606 | "movq -16(%rbp),%rdi\n\t" |
| 1607 | "movq %rax,(%rdi)\n\t" |
| 1608 | "xor %rax,%rax\n\t" |
| 1609 | "leave\n\t" |
| 1610 | "ret"); |
| 1611 | } |
| 1612 | |
| 1613 | static void |
| 1614 | amd64_emit_add (void) |
| 1615 | { |
| 1616 | EMIT_ASM (amd64_add, |
| 1617 | "add (%rsp),%rax\n\t" |
| 1618 | "lea 0x8(%rsp),%rsp"); |
| 1619 | } |
| 1620 | |
| 1621 | static void |
| 1622 | amd64_emit_sub (void) |
| 1623 | { |
| 1624 | EMIT_ASM (amd64_sub, |
| 1625 | "sub %rax,(%rsp)\n\t" |
| 1626 | "pop %rax"); |
| 1627 | } |
| 1628 | |
| 1629 | static void |
| 1630 | amd64_emit_mul (void) |
| 1631 | { |
| 1632 | emit_error = 1; |
| 1633 | } |
| 1634 | |
| 1635 | static void |
| 1636 | amd64_emit_lsh (void) |
| 1637 | { |
| 1638 | emit_error = 1; |
| 1639 | } |
| 1640 | |
| 1641 | static void |
| 1642 | amd64_emit_rsh_signed (void) |
| 1643 | { |
| 1644 | emit_error = 1; |
| 1645 | } |
| 1646 | |
| 1647 | static void |
| 1648 | amd64_emit_rsh_unsigned (void) |
| 1649 | { |
| 1650 | emit_error = 1; |
| 1651 | } |
| 1652 | |
| 1653 | static void |
| 1654 | amd64_emit_ext (int arg) |
| 1655 | { |
| 1656 | switch (arg) |
| 1657 | { |
| 1658 | case 8: |
| 1659 | EMIT_ASM (amd64_ext_8, |
| 1660 | "cbtw\n\t" |
| 1661 | "cwtl\n\t" |
| 1662 | "cltq"); |
| 1663 | break; |
| 1664 | case 16: |
| 1665 | EMIT_ASM (amd64_ext_16, |
| 1666 | "cwtl\n\t" |
| 1667 | "cltq"); |
| 1668 | break; |
| 1669 | case 32: |
| 1670 | EMIT_ASM (amd64_ext_32, |
| 1671 | "cltq"); |
| 1672 | break; |
| 1673 | default: |
| 1674 | emit_error = 1; |
| 1675 | } |
| 1676 | } |
| 1677 | |
| 1678 | static void |
| 1679 | amd64_emit_log_not (void) |
| 1680 | { |
| 1681 | EMIT_ASM (amd64_log_not, |
| 1682 | "test %rax,%rax\n\t" |
| 1683 | "sete %cl\n\t" |
| 1684 | "movzbq %cl,%rax"); |
| 1685 | } |
| 1686 | |
| 1687 | static void |
| 1688 | amd64_emit_bit_and (void) |
| 1689 | { |
| 1690 | EMIT_ASM (amd64_and, |
| 1691 | "and (%rsp),%rax\n\t" |
| 1692 | "lea 0x8(%rsp),%rsp"); |
| 1693 | } |
| 1694 | |
| 1695 | static void |
| 1696 | amd64_emit_bit_or (void) |
| 1697 | { |
| 1698 | EMIT_ASM (amd64_or, |
| 1699 | "or (%rsp),%rax\n\t" |
| 1700 | "lea 0x8(%rsp),%rsp"); |
| 1701 | } |
| 1702 | |
| 1703 | static void |
| 1704 | amd64_emit_bit_xor (void) |
| 1705 | { |
| 1706 | EMIT_ASM (amd64_xor, |
| 1707 | "xor (%rsp),%rax\n\t" |
| 1708 | "lea 0x8(%rsp),%rsp"); |
| 1709 | } |
| 1710 | |
| 1711 | static void |
| 1712 | amd64_emit_bit_not (void) |
| 1713 | { |
| 1714 | EMIT_ASM (amd64_bit_not, |
| 1715 | "xorq $0xffffffffffffffff,%rax"); |
| 1716 | } |
| 1717 | |
| 1718 | static void |
| 1719 | amd64_emit_equal (void) |
| 1720 | { |
| 1721 | EMIT_ASM (amd64_equal, |
| 1722 | "cmp %rax,(%rsp)\n\t" |
| 1723 | "je .Lamd64_equal_true\n\t" |
| 1724 | "xor %rax,%rax\n\t" |
| 1725 | "jmp .Lamd64_equal_end\n\t" |
| 1726 | ".Lamd64_equal_true:\n\t" |
| 1727 | "mov $0x1,%rax\n\t" |
| 1728 | ".Lamd64_equal_end:\n\t" |
| 1729 | "lea 0x8(%rsp),%rsp"); |
| 1730 | } |
| 1731 | |
| 1732 | static void |
| 1733 | amd64_emit_less_signed (void) |
| 1734 | { |
| 1735 | EMIT_ASM (amd64_less_signed, |
| 1736 | "cmp %rax,(%rsp)\n\t" |
| 1737 | "jl .Lamd64_less_signed_true\n\t" |
| 1738 | "xor %rax,%rax\n\t" |
| 1739 | "jmp .Lamd64_less_signed_end\n\t" |
| 1740 | ".Lamd64_less_signed_true:\n\t" |
| 1741 | "mov $1,%rax\n\t" |
| 1742 | ".Lamd64_less_signed_end:\n\t" |
| 1743 | "lea 0x8(%rsp),%rsp"); |
| 1744 | } |
| 1745 | |
| 1746 | static void |
| 1747 | amd64_emit_less_unsigned (void) |
| 1748 | { |
| 1749 | EMIT_ASM (amd64_less_unsigned, |
| 1750 | "cmp %rax,(%rsp)\n\t" |
| 1751 | "jb .Lamd64_less_unsigned_true\n\t" |
| 1752 | "xor %rax,%rax\n\t" |
| 1753 | "jmp .Lamd64_less_unsigned_end\n\t" |
| 1754 | ".Lamd64_less_unsigned_true:\n\t" |
| 1755 | "mov $1,%rax\n\t" |
| 1756 | ".Lamd64_less_unsigned_end:\n\t" |
| 1757 | "lea 0x8(%rsp),%rsp"); |
| 1758 | } |
| 1759 | |
| 1760 | static void |
| 1761 | amd64_emit_ref (int size) |
| 1762 | { |
| 1763 | switch (size) |
| 1764 | { |
| 1765 | case 1: |
| 1766 | EMIT_ASM (amd64_ref1, |
| 1767 | "movb (%rax),%al"); |
| 1768 | break; |
| 1769 | case 2: |
| 1770 | EMIT_ASM (amd64_ref2, |
| 1771 | "movw (%rax),%ax"); |
| 1772 | break; |
| 1773 | case 4: |
| 1774 | EMIT_ASM (amd64_ref4, |
| 1775 | "movl (%rax),%eax"); |
| 1776 | break; |
| 1777 | case 8: |
| 1778 | EMIT_ASM (amd64_ref8, |
| 1779 | "movq (%rax),%rax"); |
| 1780 | break; |
| 1781 | } |
| 1782 | } |
| 1783 | |
| 1784 | static void |
| 1785 | amd64_emit_if_goto (int *offset_p, int *size_p) |
| 1786 | { |
| 1787 | EMIT_ASM (amd64_if_goto, |
| 1788 | "mov %rax,%rcx\n\t" |
| 1789 | "pop %rax\n\t" |
| 1790 | "cmp $0,%rcx\n\t" |
| 1791 | ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0"); |
| 1792 | if (offset_p) |
| 1793 | *offset_p = 10; |
| 1794 | if (size_p) |
| 1795 | *size_p = 4; |
| 1796 | } |
| 1797 | |
| 1798 | static void |
| 1799 | amd64_emit_goto (int *offset_p, int *size_p) |
| 1800 | { |
| 1801 | EMIT_ASM (amd64_goto, |
| 1802 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0"); |
| 1803 | if (offset_p) |
| 1804 | *offset_p = 1; |
| 1805 | if (size_p) |
| 1806 | *size_p = 4; |
| 1807 | } |
| 1808 | |
| 1809 | static void |
| 1810 | amd64_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size) |
| 1811 | { |
| 1812 | int diff = (to - (from + size)); |
| 1813 | unsigned char buf[sizeof (int)]; |
| 1814 | |
| 1815 | if (size != 4) |
| 1816 | { |
| 1817 | emit_error = 1; |
| 1818 | return; |
| 1819 | } |
| 1820 | |
| 1821 | memcpy (buf, &diff, sizeof (int)); |
| 1822 | write_inferior_memory (from, buf, sizeof (int)); |
| 1823 | } |
| 1824 | |
| 1825 | static void |
| 1826 | amd64_emit_const (LONGEST num) |
| 1827 | { |
| 1828 | unsigned char buf[16]; |
| 1829 | int i; |
| 1830 | CORE_ADDR buildaddr = current_insn_ptr; |
| 1831 | |
| 1832 | i = 0; |
| 1833 | buf[i++] = 0x48; buf[i++] = 0xb8; /* mov $<n>,%rax */ |
| 1834 | memcpy (&buf[i], &num, sizeof (num)); |
| 1835 | i += 8; |
| 1836 | append_insns (&buildaddr, i, buf); |
| 1837 | current_insn_ptr = buildaddr; |
| 1838 | } |
| 1839 | |
| 1840 | static void |
| 1841 | amd64_emit_call (CORE_ADDR fn) |
| 1842 | { |
| 1843 | unsigned char buf[16]; |
| 1844 | int i; |
| 1845 | CORE_ADDR buildaddr; |
| 1846 | LONGEST offset64; |
| 1847 | |
| 1848 | /* The destination function being in the shared library, may be |
| 1849 | >31-bits away off the compiled code pad. */ |
| 1850 | |
| 1851 | buildaddr = current_insn_ptr; |
| 1852 | |
| 1853 | offset64 = fn - (buildaddr + 1 /* call op */ + 4 /* 32-bit offset */); |
| 1854 | |
| 1855 | i = 0; |
| 1856 | |
| 1857 | if (offset64 > INT_MAX || offset64 < INT_MIN) |
| 1858 | { |
| 1859 | /* Offset is too large for a call. Use callq, but that requires |
| 1860 | a register, so avoid it if possible. Use r10, since it is |
| 1861 | call-clobbered, we don't have to push/pop it. */ |
| 1862 | buf[i++] = 0x48; /* mov $fn,%r10 */ |
| 1863 | buf[i++] = 0xba; |
| 1864 | memcpy (buf + i, &fn, 8); |
| 1865 | i += 8; |
| 1866 | buf[i++] = 0xff; /* callq *%r10 */ |
| 1867 | buf[i++] = 0xd2; |
| 1868 | } |
| 1869 | else |
| 1870 | { |
| 1871 | int offset32 = offset64; /* we know we can't overflow here. */ |
| 1872 | |
| 1873 | buf[i++] = 0xe8; /* call <reladdr> */ |
| 1874 | memcpy (buf + i, &offset32, 4); |
| 1875 | i += 4; |
| 1876 | } |
| 1877 | |
| 1878 | append_insns (&buildaddr, i, buf); |
| 1879 | current_insn_ptr = buildaddr; |
| 1880 | } |
| 1881 | |
| 1882 | static void |
| 1883 | amd64_emit_reg (int reg) |
| 1884 | { |
| 1885 | unsigned char buf[16]; |
| 1886 | int i; |
| 1887 | CORE_ADDR buildaddr; |
| 1888 | |
| 1889 | /* Assume raw_regs is still in %rdi. */ |
| 1890 | buildaddr = current_insn_ptr; |
| 1891 | i = 0; |
| 1892 | buf[i++] = 0xbe; /* mov $<n>,%esi */ |
| 1893 | memcpy (&buf[i], ®, sizeof (reg)); |
| 1894 | i += 4; |
| 1895 | append_insns (&buildaddr, i, buf); |
| 1896 | current_insn_ptr = buildaddr; |
| 1897 | amd64_emit_call (get_raw_reg_func_addr ()); |
| 1898 | } |
| 1899 | |
| 1900 | static void |
| 1901 | amd64_emit_pop (void) |
| 1902 | { |
| 1903 | EMIT_ASM (amd64_pop, |
| 1904 | "pop %rax"); |
| 1905 | } |
| 1906 | |
| 1907 | static void |
| 1908 | amd64_emit_stack_flush (void) |
| 1909 | { |
| 1910 | EMIT_ASM (amd64_stack_flush, |
| 1911 | "push %rax"); |
| 1912 | } |
| 1913 | |
| 1914 | static void |
| 1915 | amd64_emit_zero_ext (int arg) |
| 1916 | { |
| 1917 | switch (arg) |
| 1918 | { |
| 1919 | case 8: |
| 1920 | EMIT_ASM (amd64_zero_ext_8, |
| 1921 | "and $0xff,%rax"); |
| 1922 | break; |
| 1923 | case 16: |
| 1924 | EMIT_ASM (amd64_zero_ext_16, |
| 1925 | "and $0xffff,%rax"); |
| 1926 | break; |
| 1927 | case 32: |
| 1928 | EMIT_ASM (amd64_zero_ext_32, |
| 1929 | "mov $0xffffffff,%rcx\n\t" |
| 1930 | "and %rcx,%rax"); |
| 1931 | break; |
| 1932 | default: |
| 1933 | emit_error = 1; |
| 1934 | } |
| 1935 | } |
| 1936 | |
| 1937 | static void |
| 1938 | amd64_emit_swap (void) |
| 1939 | { |
| 1940 | EMIT_ASM (amd64_swap, |
| 1941 | "mov %rax,%rcx\n\t" |
| 1942 | "pop %rax\n\t" |
| 1943 | "push %rcx"); |
| 1944 | } |
| 1945 | |
| 1946 | static void |
| 1947 | amd64_emit_stack_adjust (int n) |
| 1948 | { |
| 1949 | unsigned char buf[16]; |
| 1950 | int i; |
| 1951 | CORE_ADDR buildaddr = current_insn_ptr; |
| 1952 | |
| 1953 | i = 0; |
| 1954 | buf[i++] = 0x48; /* lea $<n>(%rsp),%rsp */ |
| 1955 | buf[i++] = 0x8d; |
| 1956 | buf[i++] = 0x64; |
| 1957 | buf[i++] = 0x24; |
| 1958 | /* This only handles adjustments up to 16, but we don't expect any more. */ |
| 1959 | buf[i++] = n * 8; |
| 1960 | append_insns (&buildaddr, i, buf); |
| 1961 | current_insn_ptr = buildaddr; |
| 1962 | } |
| 1963 | |
| 1964 | /* FN's prototype is `LONGEST(*fn)(int)'. */ |
| 1965 | |
| 1966 | static void |
| 1967 | amd64_emit_int_call_1 (CORE_ADDR fn, int arg1) |
| 1968 | { |
| 1969 | unsigned char buf[16]; |
| 1970 | int i; |
| 1971 | CORE_ADDR buildaddr; |
| 1972 | |
| 1973 | buildaddr = current_insn_ptr; |
| 1974 | i = 0; |
| 1975 | buf[i++] = 0xbf; /* movl $<n>,%edi */ |
| 1976 | memcpy (&buf[i], &arg1, sizeof (arg1)); |
| 1977 | i += 4; |
| 1978 | append_insns (&buildaddr, i, buf); |
| 1979 | current_insn_ptr = buildaddr; |
| 1980 | amd64_emit_call (fn); |
| 1981 | } |
| 1982 | |
| 1983 | /* FN's prototype is `void(*fn)(int,LONGEST)'. */ |
| 1984 | |
| 1985 | static void |
| 1986 | amd64_emit_void_call_2 (CORE_ADDR fn, int arg1) |
| 1987 | { |
| 1988 | unsigned char buf[16]; |
| 1989 | int i; |
| 1990 | CORE_ADDR buildaddr; |
| 1991 | |
| 1992 | buildaddr = current_insn_ptr; |
| 1993 | i = 0; |
| 1994 | buf[i++] = 0xbf; /* movl $<n>,%edi */ |
| 1995 | memcpy (&buf[i], &arg1, sizeof (arg1)); |
| 1996 | i += 4; |
| 1997 | append_insns (&buildaddr, i, buf); |
| 1998 | current_insn_ptr = buildaddr; |
| 1999 | EMIT_ASM (amd64_void_call_2_a, |
| 2000 | /* Save away a copy of the stack top. */ |
| 2001 | "push %rax\n\t" |
| 2002 | /* Also pass top as the second argument. */ |
| 2003 | "mov %rax,%rsi"); |
| 2004 | amd64_emit_call (fn); |
| 2005 | EMIT_ASM (amd64_void_call_2_b, |
| 2006 | /* Restore the stack top, %rax may have been trashed. */ |
| 2007 | "pop %rax"); |
| 2008 | } |
| 2009 | |
| 2010 | void |
| 2011 | amd64_emit_eq_goto (int *offset_p, int *size_p) |
| 2012 | { |
| 2013 | EMIT_ASM (amd64_eq, |
| 2014 | "cmp %rax,(%rsp)\n\t" |
| 2015 | "jne .Lamd64_eq_fallthru\n\t" |
| 2016 | "lea 0x8(%rsp),%rsp\n\t" |
| 2017 | "pop %rax\n\t" |
| 2018 | /* jmp, but don't trust the assembler to choose the right jump */ |
| 2019 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" |
| 2020 | ".Lamd64_eq_fallthru:\n\t" |
| 2021 | "lea 0x8(%rsp),%rsp\n\t" |
| 2022 | "pop %rax"); |
| 2023 | |
| 2024 | if (offset_p) |
| 2025 | *offset_p = 13; |
| 2026 | if (size_p) |
| 2027 | *size_p = 4; |
| 2028 | } |
| 2029 | |
| 2030 | void |
| 2031 | amd64_emit_ne_goto (int *offset_p, int *size_p) |
| 2032 | { |
| 2033 | EMIT_ASM (amd64_ne, |
| 2034 | "cmp %rax,(%rsp)\n\t" |
| 2035 | "je .Lamd64_ne_fallthru\n\t" |
| 2036 | "lea 0x8(%rsp),%rsp\n\t" |
| 2037 | "pop %rax\n\t" |
| 2038 | /* jmp, but don't trust the assembler to choose the right jump */ |
| 2039 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" |
| 2040 | ".Lamd64_ne_fallthru:\n\t" |
| 2041 | "lea 0x8(%rsp),%rsp\n\t" |
| 2042 | "pop %rax"); |
| 2043 | |
| 2044 | if (offset_p) |
| 2045 | *offset_p = 13; |
| 2046 | if (size_p) |
| 2047 | *size_p = 4; |
| 2048 | } |
| 2049 | |
| 2050 | void |
| 2051 | amd64_emit_lt_goto (int *offset_p, int *size_p) |
| 2052 | { |
| 2053 | EMIT_ASM (amd64_lt, |
| 2054 | "cmp %rax,(%rsp)\n\t" |
| 2055 | "jnl .Lamd64_lt_fallthru\n\t" |
| 2056 | "lea 0x8(%rsp),%rsp\n\t" |
| 2057 | "pop %rax\n\t" |
| 2058 | /* jmp, but don't trust the assembler to choose the right jump */ |
| 2059 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" |
| 2060 | ".Lamd64_lt_fallthru:\n\t" |
| 2061 | "lea 0x8(%rsp),%rsp\n\t" |
| 2062 | "pop %rax"); |
| 2063 | |
| 2064 | if (offset_p) |
| 2065 | *offset_p = 13; |
| 2066 | if (size_p) |
| 2067 | *size_p = 4; |
| 2068 | } |
| 2069 | |
| 2070 | void |
| 2071 | amd64_emit_le_goto (int *offset_p, int *size_p) |
| 2072 | { |
| 2073 | EMIT_ASM (amd64_le, |
| 2074 | "cmp %rax,(%rsp)\n\t" |
| 2075 | "jnle .Lamd64_le_fallthru\n\t" |
| 2076 | "lea 0x8(%rsp),%rsp\n\t" |
| 2077 | "pop %rax\n\t" |
| 2078 | /* jmp, but don't trust the assembler to choose the right jump */ |
| 2079 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" |
| 2080 | ".Lamd64_le_fallthru:\n\t" |
| 2081 | "lea 0x8(%rsp),%rsp\n\t" |
| 2082 | "pop %rax"); |
| 2083 | |
| 2084 | if (offset_p) |
| 2085 | *offset_p = 13; |
| 2086 | if (size_p) |
| 2087 | *size_p = 4; |
| 2088 | } |
| 2089 | |
| 2090 | void |
| 2091 | amd64_emit_gt_goto (int *offset_p, int *size_p) |
| 2092 | { |
| 2093 | EMIT_ASM (amd64_gt, |
| 2094 | "cmp %rax,(%rsp)\n\t" |
| 2095 | "jng .Lamd64_gt_fallthru\n\t" |
| 2096 | "lea 0x8(%rsp),%rsp\n\t" |
| 2097 | "pop %rax\n\t" |
| 2098 | /* jmp, but don't trust the assembler to choose the right jump */ |
| 2099 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" |
| 2100 | ".Lamd64_gt_fallthru:\n\t" |
| 2101 | "lea 0x8(%rsp),%rsp\n\t" |
| 2102 | "pop %rax"); |
| 2103 | |
| 2104 | if (offset_p) |
| 2105 | *offset_p = 13; |
| 2106 | if (size_p) |
| 2107 | *size_p = 4; |
| 2108 | } |
| 2109 | |
| 2110 | void |
| 2111 | amd64_emit_ge_goto (int *offset_p, int *size_p) |
| 2112 | { |
| 2113 | EMIT_ASM (amd64_ge, |
| 2114 | "cmp %rax,(%rsp)\n\t" |
| 2115 | "jnge .Lamd64_ge_fallthru\n\t" |
| 2116 | ".Lamd64_ge_jump:\n\t" |
| 2117 | "lea 0x8(%rsp),%rsp\n\t" |
| 2118 | "pop %rax\n\t" |
| 2119 | /* jmp, but don't trust the assembler to choose the right jump */ |
| 2120 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" |
| 2121 | ".Lamd64_ge_fallthru:\n\t" |
| 2122 | "lea 0x8(%rsp),%rsp\n\t" |
| 2123 | "pop %rax"); |
| 2124 | |
| 2125 | if (offset_p) |
| 2126 | *offset_p = 13; |
| 2127 | if (size_p) |
| 2128 | *size_p = 4; |
| 2129 | } |
| 2130 | |
| 2131 | struct emit_ops amd64_emit_ops = |
| 2132 | { |
| 2133 | amd64_emit_prologue, |
| 2134 | amd64_emit_epilogue, |
| 2135 | amd64_emit_add, |
| 2136 | amd64_emit_sub, |
| 2137 | amd64_emit_mul, |
| 2138 | amd64_emit_lsh, |
| 2139 | amd64_emit_rsh_signed, |
| 2140 | amd64_emit_rsh_unsigned, |
| 2141 | amd64_emit_ext, |
| 2142 | amd64_emit_log_not, |
| 2143 | amd64_emit_bit_and, |
| 2144 | amd64_emit_bit_or, |
| 2145 | amd64_emit_bit_xor, |
| 2146 | amd64_emit_bit_not, |
| 2147 | amd64_emit_equal, |
| 2148 | amd64_emit_less_signed, |
| 2149 | amd64_emit_less_unsigned, |
| 2150 | amd64_emit_ref, |
| 2151 | amd64_emit_if_goto, |
| 2152 | amd64_emit_goto, |
| 2153 | amd64_write_goto_address, |
| 2154 | amd64_emit_const, |
| 2155 | amd64_emit_call, |
| 2156 | amd64_emit_reg, |
| 2157 | amd64_emit_pop, |
| 2158 | amd64_emit_stack_flush, |
| 2159 | amd64_emit_zero_ext, |
| 2160 | amd64_emit_swap, |
| 2161 | amd64_emit_stack_adjust, |
| 2162 | amd64_emit_int_call_1, |
| 2163 | amd64_emit_void_call_2, |
| 2164 | amd64_emit_eq_goto, |
| 2165 | amd64_emit_ne_goto, |
| 2166 | amd64_emit_lt_goto, |
| 2167 | amd64_emit_le_goto, |
| 2168 | amd64_emit_gt_goto, |
| 2169 | amd64_emit_ge_goto |
| 2170 | }; |
| 2171 | |
| 2172 | #endif /* __x86_64__ */ |
| 2173 | |
| 2174 | static void |
| 2175 | i386_emit_prologue (void) |
| 2176 | { |
| 2177 | EMIT_ASM32 (i386_prologue, |
| 2178 | "push %ebp\n\t" |
| 2179 | "mov %esp,%ebp\n\t" |
| 2180 | "push %ebx"); |
| 2181 | /* At this point, the raw regs base address is at 8(%ebp), and the |
| 2182 | value pointer is at 12(%ebp). */ |
| 2183 | } |
| 2184 | |
| 2185 | static void |
| 2186 | i386_emit_epilogue (void) |
| 2187 | { |
| 2188 | EMIT_ASM32 (i386_epilogue, |
| 2189 | "mov 12(%ebp),%ecx\n\t" |
| 2190 | "mov %eax,(%ecx)\n\t" |
| 2191 | "mov %ebx,0x4(%ecx)\n\t" |
| 2192 | "xor %eax,%eax\n\t" |
| 2193 | "pop %ebx\n\t" |
| 2194 | "pop %ebp\n\t" |
| 2195 | "ret"); |
| 2196 | } |
| 2197 | |
| 2198 | static void |
| 2199 | i386_emit_add (void) |
| 2200 | { |
| 2201 | EMIT_ASM32 (i386_add, |
| 2202 | "add (%esp),%eax\n\t" |
| 2203 | "adc 0x4(%esp),%ebx\n\t" |
| 2204 | "lea 0x8(%esp),%esp"); |
| 2205 | } |
| 2206 | |
| 2207 | static void |
| 2208 | i386_emit_sub (void) |
| 2209 | { |
| 2210 | EMIT_ASM32 (i386_sub, |
| 2211 | "subl %eax,(%esp)\n\t" |
| 2212 | "sbbl %ebx,4(%esp)\n\t" |
| 2213 | "pop %eax\n\t" |
| 2214 | "pop %ebx\n\t"); |
| 2215 | } |
| 2216 | |
| 2217 | static void |
| 2218 | i386_emit_mul (void) |
| 2219 | { |
| 2220 | emit_error = 1; |
| 2221 | } |
| 2222 | |
| 2223 | static void |
| 2224 | i386_emit_lsh (void) |
| 2225 | { |
| 2226 | emit_error = 1; |
| 2227 | } |
| 2228 | |
| 2229 | static void |
| 2230 | i386_emit_rsh_signed (void) |
| 2231 | { |
| 2232 | emit_error = 1; |
| 2233 | } |
| 2234 | |
| 2235 | static void |
| 2236 | i386_emit_rsh_unsigned (void) |
| 2237 | { |
| 2238 | emit_error = 1; |
| 2239 | } |
| 2240 | |
| 2241 | static void |
| 2242 | i386_emit_ext (int arg) |
| 2243 | { |
| 2244 | switch (arg) |
| 2245 | { |
| 2246 | case 8: |
| 2247 | EMIT_ASM32 (i386_ext_8, |
| 2248 | "cbtw\n\t" |
| 2249 | "cwtl\n\t" |
| 2250 | "movl %eax,%ebx\n\t" |
| 2251 | "sarl $31,%ebx"); |
| 2252 | break; |
| 2253 | case 16: |
| 2254 | EMIT_ASM32 (i386_ext_16, |
| 2255 | "cwtl\n\t" |
| 2256 | "movl %eax,%ebx\n\t" |
| 2257 | "sarl $31,%ebx"); |
| 2258 | break; |
| 2259 | case 32: |
| 2260 | EMIT_ASM32 (i386_ext_32, |
| 2261 | "movl %eax,%ebx\n\t" |
| 2262 | "sarl $31,%ebx"); |
| 2263 | break; |
| 2264 | default: |
| 2265 | emit_error = 1; |
| 2266 | } |
| 2267 | } |
| 2268 | |
| 2269 | static void |
| 2270 | i386_emit_log_not (void) |
| 2271 | { |
| 2272 | EMIT_ASM32 (i386_log_not, |
| 2273 | "or %ebx,%eax\n\t" |
| 2274 | "test %eax,%eax\n\t" |
| 2275 | "sete %cl\n\t" |
| 2276 | "xor %ebx,%ebx\n\t" |
| 2277 | "movzbl %cl,%eax"); |
| 2278 | } |
| 2279 | |
| 2280 | static void |
| 2281 | i386_emit_bit_and (void) |
| 2282 | { |
| 2283 | EMIT_ASM32 (i386_and, |
| 2284 | "and (%esp),%eax\n\t" |
| 2285 | "and 0x4(%esp),%ebx\n\t" |
| 2286 | "lea 0x8(%esp),%esp"); |
| 2287 | } |
| 2288 | |
| 2289 | static void |
| 2290 | i386_emit_bit_or (void) |
| 2291 | { |
| 2292 | EMIT_ASM32 (i386_or, |
| 2293 | "or (%esp),%eax\n\t" |
| 2294 | "or 0x4(%esp),%ebx\n\t" |
| 2295 | "lea 0x8(%esp),%esp"); |
| 2296 | } |
| 2297 | |
| 2298 | static void |
| 2299 | i386_emit_bit_xor (void) |
| 2300 | { |
| 2301 | EMIT_ASM32 (i386_xor, |
| 2302 | "xor (%esp),%eax\n\t" |
| 2303 | "xor 0x4(%esp),%ebx\n\t" |
| 2304 | "lea 0x8(%esp),%esp"); |
| 2305 | } |
| 2306 | |
| 2307 | static void |
| 2308 | i386_emit_bit_not (void) |
| 2309 | { |
| 2310 | EMIT_ASM32 (i386_bit_not, |
| 2311 | "xor $0xffffffff,%eax\n\t" |
| 2312 | "xor $0xffffffff,%ebx\n\t"); |
| 2313 | } |
| 2314 | |
| 2315 | static void |
| 2316 | i386_emit_equal (void) |
| 2317 | { |
| 2318 | EMIT_ASM32 (i386_equal, |
| 2319 | "cmpl %ebx,4(%esp)\n\t" |
| 2320 | "jne .Li386_equal_false\n\t" |
| 2321 | "cmpl %eax,(%esp)\n\t" |
| 2322 | "je .Li386_equal_true\n\t" |
| 2323 | ".Li386_equal_false:\n\t" |
| 2324 | "xor %eax,%eax\n\t" |
| 2325 | "jmp .Li386_equal_end\n\t" |
| 2326 | ".Li386_equal_true:\n\t" |
| 2327 | "mov $1,%eax\n\t" |
| 2328 | ".Li386_equal_end:\n\t" |
| 2329 | "xor %ebx,%ebx\n\t" |
| 2330 | "lea 0x8(%esp),%esp"); |
| 2331 | } |
| 2332 | |
| 2333 | static void |
| 2334 | i386_emit_less_signed (void) |
| 2335 | { |
| 2336 | EMIT_ASM32 (i386_less_signed, |
| 2337 | "cmpl %ebx,4(%esp)\n\t" |
| 2338 | "jl .Li386_less_signed_true\n\t" |
| 2339 | "jne .Li386_less_signed_false\n\t" |
| 2340 | "cmpl %eax,(%esp)\n\t" |
| 2341 | "jl .Li386_less_signed_true\n\t" |
| 2342 | ".Li386_less_signed_false:\n\t" |
| 2343 | "xor %eax,%eax\n\t" |
| 2344 | "jmp .Li386_less_signed_end\n\t" |
| 2345 | ".Li386_less_signed_true:\n\t" |
| 2346 | "mov $1,%eax\n\t" |
| 2347 | ".Li386_less_signed_end:\n\t" |
| 2348 | "xor %ebx,%ebx\n\t" |
| 2349 | "lea 0x8(%esp),%esp"); |
| 2350 | } |
| 2351 | |
| 2352 | static void |
| 2353 | i386_emit_less_unsigned (void) |
| 2354 | { |
| 2355 | EMIT_ASM32 (i386_less_unsigned, |
| 2356 | "cmpl %ebx,4(%esp)\n\t" |
| 2357 | "jb .Li386_less_unsigned_true\n\t" |
| 2358 | "jne .Li386_less_unsigned_false\n\t" |
| 2359 | "cmpl %eax,(%esp)\n\t" |
| 2360 | "jb .Li386_less_unsigned_true\n\t" |
| 2361 | ".Li386_less_unsigned_false:\n\t" |
| 2362 | "xor %eax,%eax\n\t" |
| 2363 | "jmp .Li386_less_unsigned_end\n\t" |
| 2364 | ".Li386_less_unsigned_true:\n\t" |
| 2365 | "mov $1,%eax\n\t" |
| 2366 | ".Li386_less_unsigned_end:\n\t" |
| 2367 | "xor %ebx,%ebx\n\t" |
| 2368 | "lea 0x8(%esp),%esp"); |
| 2369 | } |
| 2370 | |
| 2371 | static void |
| 2372 | i386_emit_ref (int size) |
| 2373 | { |
| 2374 | switch (size) |
| 2375 | { |
| 2376 | case 1: |
| 2377 | EMIT_ASM32 (i386_ref1, |
| 2378 | "movb (%eax),%al"); |
| 2379 | break; |
| 2380 | case 2: |
| 2381 | EMIT_ASM32 (i386_ref2, |
| 2382 | "movw (%eax),%ax"); |
| 2383 | break; |
| 2384 | case 4: |
| 2385 | EMIT_ASM32 (i386_ref4, |
| 2386 | "movl (%eax),%eax"); |
| 2387 | break; |
| 2388 | case 8: |
| 2389 | EMIT_ASM32 (i386_ref8, |
| 2390 | "movl 4(%eax),%ebx\n\t" |
| 2391 | "movl (%eax),%eax"); |
| 2392 | break; |
| 2393 | } |
| 2394 | } |
| 2395 | |
| 2396 | static void |
| 2397 | i386_emit_if_goto (int *offset_p, int *size_p) |
| 2398 | { |
| 2399 | EMIT_ASM32 (i386_if_goto, |
| 2400 | "mov %eax,%ecx\n\t" |
| 2401 | "or %ebx,%ecx\n\t" |
| 2402 | "pop %eax\n\t" |
| 2403 | "pop %ebx\n\t" |
| 2404 | "cmpl $0,%ecx\n\t" |
| 2405 | /* Don't trust the assembler to choose the right jump */ |
| 2406 | ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0"); |
| 2407 | |
| 2408 | if (offset_p) |
| 2409 | *offset_p = 11; /* be sure that this matches the sequence above */ |
| 2410 | if (size_p) |
| 2411 | *size_p = 4; |
| 2412 | } |
| 2413 | |
| 2414 | static void |
| 2415 | i386_emit_goto (int *offset_p, int *size_p) |
| 2416 | { |
| 2417 | EMIT_ASM32 (i386_goto, |
| 2418 | /* Don't trust the assembler to choose the right jump */ |
| 2419 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0"); |
| 2420 | if (offset_p) |
| 2421 | *offset_p = 1; |
| 2422 | if (size_p) |
| 2423 | *size_p = 4; |
| 2424 | } |
| 2425 | |
| 2426 | static void |
| 2427 | i386_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size) |
| 2428 | { |
| 2429 | int diff = (to - (from + size)); |
| 2430 | unsigned char buf[sizeof (int)]; |
| 2431 | |
| 2432 | /* We're only doing 4-byte sizes at the moment. */ |
| 2433 | if (size != 4) |
| 2434 | { |
| 2435 | emit_error = 1; |
| 2436 | return; |
| 2437 | } |
| 2438 | |
| 2439 | memcpy (buf, &diff, sizeof (int)); |
| 2440 | write_inferior_memory (from, buf, sizeof (int)); |
| 2441 | } |
| 2442 | |
| 2443 | static void |
| 2444 | i386_emit_const (LONGEST num) |
| 2445 | { |
| 2446 | unsigned char buf[16]; |
| 2447 | int i, hi, lo; |
| 2448 | CORE_ADDR buildaddr = current_insn_ptr; |
| 2449 | |
| 2450 | i = 0; |
| 2451 | buf[i++] = 0xb8; /* mov $<n>,%eax */ |
| 2452 | lo = num & 0xffffffff; |
| 2453 | memcpy (&buf[i], &lo, sizeof (lo)); |
| 2454 | i += 4; |
| 2455 | hi = ((num >> 32) & 0xffffffff); |
| 2456 | if (hi) |
| 2457 | { |
| 2458 | buf[i++] = 0xbb; /* mov $<n>,%ebx */ |
| 2459 | memcpy (&buf[i], &hi, sizeof (hi)); |
| 2460 | i += 4; |
| 2461 | } |
| 2462 | else |
| 2463 | { |
| 2464 | buf[i++] = 0x31; buf[i++] = 0xdb; /* xor %ebx,%ebx */ |
| 2465 | } |
| 2466 | append_insns (&buildaddr, i, buf); |
| 2467 | current_insn_ptr = buildaddr; |
| 2468 | } |
| 2469 | |
| 2470 | static void |
| 2471 | i386_emit_call (CORE_ADDR fn) |
| 2472 | { |
| 2473 | unsigned char buf[16]; |
| 2474 | int i, offset; |
| 2475 | CORE_ADDR buildaddr; |
| 2476 | |
| 2477 | buildaddr = current_insn_ptr; |
| 2478 | i = 0; |
| 2479 | buf[i++] = 0xe8; /* call <reladdr> */ |
| 2480 | offset = ((int) fn) - (buildaddr + 5); |
| 2481 | memcpy (buf + 1, &offset, 4); |
| 2482 | append_insns (&buildaddr, 5, buf); |
| 2483 | current_insn_ptr = buildaddr; |
| 2484 | } |
| 2485 | |
| 2486 | static void |
| 2487 | i386_emit_reg (int reg) |
| 2488 | { |
| 2489 | unsigned char buf[16]; |
| 2490 | int i; |
| 2491 | CORE_ADDR buildaddr; |
| 2492 | |
| 2493 | EMIT_ASM32 (i386_reg_a, |
| 2494 | "sub $0x8,%esp"); |
| 2495 | buildaddr = current_insn_ptr; |
| 2496 | i = 0; |
| 2497 | buf[i++] = 0xb8; /* mov $<n>,%eax */ |
| 2498 | memcpy (&buf[i], ®, sizeof (reg)); |
| 2499 | i += 4; |
| 2500 | append_insns (&buildaddr, i, buf); |
| 2501 | current_insn_ptr = buildaddr; |
| 2502 | EMIT_ASM32 (i386_reg_b, |
| 2503 | "mov %eax,4(%esp)\n\t" |
| 2504 | "mov 8(%ebp),%eax\n\t" |
| 2505 | "mov %eax,(%esp)"); |
| 2506 | i386_emit_call (get_raw_reg_func_addr ()); |
| 2507 | EMIT_ASM32 (i386_reg_c, |
| 2508 | "xor %ebx,%ebx\n\t" |
| 2509 | "lea 0x8(%esp),%esp"); |
| 2510 | } |
| 2511 | |
| 2512 | static void |
| 2513 | i386_emit_pop (void) |
| 2514 | { |
| 2515 | EMIT_ASM32 (i386_pop, |
| 2516 | "pop %eax\n\t" |
| 2517 | "pop %ebx"); |
| 2518 | } |
| 2519 | |
| 2520 | static void |
| 2521 | i386_emit_stack_flush (void) |
| 2522 | { |
| 2523 | EMIT_ASM32 (i386_stack_flush, |
| 2524 | "push %ebx\n\t" |
| 2525 | "push %eax"); |
| 2526 | } |
| 2527 | |
| 2528 | static void |
| 2529 | i386_emit_zero_ext (int arg) |
| 2530 | { |
| 2531 | switch (arg) |
| 2532 | { |
| 2533 | case 8: |
| 2534 | EMIT_ASM32 (i386_zero_ext_8, |
| 2535 | "and $0xff,%eax\n\t" |
| 2536 | "xor %ebx,%ebx"); |
| 2537 | break; |
| 2538 | case 16: |
| 2539 | EMIT_ASM32 (i386_zero_ext_16, |
| 2540 | "and $0xffff,%eax\n\t" |
| 2541 | "xor %ebx,%ebx"); |
| 2542 | break; |
| 2543 | case 32: |
| 2544 | EMIT_ASM32 (i386_zero_ext_32, |
| 2545 | "xor %ebx,%ebx"); |
| 2546 | break; |
| 2547 | default: |
| 2548 | emit_error = 1; |
| 2549 | } |
| 2550 | } |
| 2551 | |
| 2552 | static void |
| 2553 | i386_emit_swap (void) |
| 2554 | { |
| 2555 | EMIT_ASM32 (i386_swap, |
| 2556 | "mov %eax,%ecx\n\t" |
| 2557 | "mov %ebx,%edx\n\t" |
| 2558 | "pop %eax\n\t" |
| 2559 | "pop %ebx\n\t" |
| 2560 | "push %edx\n\t" |
| 2561 | "push %ecx"); |
| 2562 | } |
| 2563 | |
| 2564 | static void |
| 2565 | i386_emit_stack_adjust (int n) |
| 2566 | { |
| 2567 | unsigned char buf[16]; |
| 2568 | int i; |
| 2569 | CORE_ADDR buildaddr = current_insn_ptr; |
| 2570 | |
| 2571 | i = 0; |
| 2572 | buf[i++] = 0x8d; /* lea $<n>(%esp),%esp */ |
| 2573 | buf[i++] = 0x64; |
| 2574 | buf[i++] = 0x24; |
| 2575 | buf[i++] = n * 8; |
| 2576 | append_insns (&buildaddr, i, buf); |
| 2577 | current_insn_ptr = buildaddr; |
| 2578 | } |
| 2579 | |
| 2580 | /* FN's prototype is `LONGEST(*fn)(int)'. */ |
| 2581 | |
| 2582 | static void |
| 2583 | i386_emit_int_call_1 (CORE_ADDR fn, int arg1) |
| 2584 | { |
| 2585 | unsigned char buf[16]; |
| 2586 | int i; |
| 2587 | CORE_ADDR buildaddr; |
| 2588 | |
| 2589 | EMIT_ASM32 (i386_int_call_1_a, |
| 2590 | /* Reserve a bit of stack space. */ |
| 2591 | "sub $0x8,%esp"); |
| 2592 | /* Put the one argument on the stack. */ |
| 2593 | buildaddr = current_insn_ptr; |
| 2594 | i = 0; |
| 2595 | buf[i++] = 0xc7; /* movl $<arg1>,(%esp) */ |
| 2596 | buf[i++] = 0x04; |
| 2597 | buf[i++] = 0x24; |
| 2598 | memcpy (&buf[i], &arg1, sizeof (arg1)); |
| 2599 | i += 4; |
| 2600 | append_insns (&buildaddr, i, buf); |
| 2601 | current_insn_ptr = buildaddr; |
| 2602 | i386_emit_call (fn); |
| 2603 | EMIT_ASM32 (i386_int_call_1_c, |
| 2604 | "mov %edx,%ebx\n\t" |
| 2605 | "lea 0x8(%esp),%esp"); |
| 2606 | } |
| 2607 | |
| 2608 | /* FN's prototype is `void(*fn)(int,LONGEST)'. */ |
| 2609 | |
| 2610 | static void |
| 2611 | i386_emit_void_call_2 (CORE_ADDR fn, int arg1) |
| 2612 | { |
| 2613 | unsigned char buf[16]; |
| 2614 | int i; |
| 2615 | CORE_ADDR buildaddr; |
| 2616 | |
| 2617 | EMIT_ASM32 (i386_void_call_2_a, |
| 2618 | /* Preserve %eax only; we don't have to worry about %ebx. */ |
| 2619 | "push %eax\n\t" |
| 2620 | /* Reserve a bit of stack space for arguments. */ |
| 2621 | "sub $0x10,%esp\n\t" |
| 2622 | /* Copy "top" to the second argument position. (Note that |
| 2623 | we can't assume function won't scribble on its |
| 2624 | arguments, so don't try to restore from this.) */ |
| 2625 | "mov %eax,4(%esp)\n\t" |
| 2626 | "mov %ebx,8(%esp)"); |
| 2627 | /* Put the first argument on the stack. */ |
| 2628 | buildaddr = current_insn_ptr; |
| 2629 | i = 0; |
| 2630 | buf[i++] = 0xc7; /* movl $<arg1>,(%esp) */ |
| 2631 | buf[i++] = 0x04; |
| 2632 | buf[i++] = 0x24; |
| 2633 | memcpy (&buf[i], &arg1, sizeof (arg1)); |
| 2634 | i += 4; |
| 2635 | append_insns (&buildaddr, i, buf); |
| 2636 | current_insn_ptr = buildaddr; |
| 2637 | i386_emit_call (fn); |
| 2638 | EMIT_ASM32 (i386_void_call_2_b, |
| 2639 | "lea 0x10(%esp),%esp\n\t" |
| 2640 | /* Restore original stack top. */ |
| 2641 | "pop %eax"); |
| 2642 | } |
| 2643 | |
| 2644 | |
| 2645 | void |
| 2646 | i386_emit_eq_goto (int *offset_p, int *size_p) |
| 2647 | { |
| 2648 | EMIT_ASM32 (eq, |
| 2649 | /* Check low half first, more likely to be decider */ |
| 2650 | "cmpl %eax,(%esp)\n\t" |
| 2651 | "jne .Leq_fallthru\n\t" |
| 2652 | "cmpl %ebx,4(%esp)\n\t" |
| 2653 | "jne .Leq_fallthru\n\t" |
| 2654 | "lea 0x8(%esp),%esp\n\t" |
| 2655 | "pop %eax\n\t" |
| 2656 | "pop %ebx\n\t" |
| 2657 | /* jmp, but don't trust the assembler to choose the right jump */ |
| 2658 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" |
| 2659 | ".Leq_fallthru:\n\t" |
| 2660 | "lea 0x8(%esp),%esp\n\t" |
| 2661 | "pop %eax\n\t" |
| 2662 | "pop %ebx"); |
| 2663 | |
| 2664 | if (offset_p) |
| 2665 | *offset_p = 18; |
| 2666 | if (size_p) |
| 2667 | *size_p = 4; |
| 2668 | } |
| 2669 | |
| 2670 | void |
| 2671 | i386_emit_ne_goto (int *offset_p, int *size_p) |
| 2672 | { |
| 2673 | EMIT_ASM32 (ne, |
| 2674 | /* Check low half first, more likely to be decider */ |
| 2675 | "cmpl %eax,(%esp)\n\t" |
| 2676 | "jne .Lne_jump\n\t" |
| 2677 | "cmpl %ebx,4(%esp)\n\t" |
| 2678 | "je .Lne_fallthru\n\t" |
| 2679 | ".Lne_jump:\n\t" |
| 2680 | "lea 0x8(%esp),%esp\n\t" |
| 2681 | "pop %eax\n\t" |
| 2682 | "pop %ebx\n\t" |
| 2683 | /* jmp, but don't trust the assembler to choose the right jump */ |
| 2684 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" |
| 2685 | ".Lne_fallthru:\n\t" |
| 2686 | "lea 0x8(%esp),%esp\n\t" |
| 2687 | "pop %eax\n\t" |
| 2688 | "pop %ebx"); |
| 2689 | |
| 2690 | if (offset_p) |
| 2691 | *offset_p = 18; |
| 2692 | if (size_p) |
| 2693 | *size_p = 4; |
| 2694 | } |
| 2695 | |
| 2696 | void |
| 2697 | i386_emit_lt_goto (int *offset_p, int *size_p) |
| 2698 | { |
| 2699 | EMIT_ASM32 (lt, |
| 2700 | "cmpl %ebx,4(%esp)\n\t" |
| 2701 | "jl .Llt_jump\n\t" |
| 2702 | "jne .Llt_fallthru\n\t" |
| 2703 | "cmpl %eax,(%esp)\n\t" |
| 2704 | "jnl .Llt_fallthru\n\t" |
| 2705 | ".Llt_jump:\n\t" |
| 2706 | "lea 0x8(%esp),%esp\n\t" |
| 2707 | "pop %eax\n\t" |
| 2708 | "pop %ebx\n\t" |
| 2709 | /* jmp, but don't trust the assembler to choose the right jump */ |
| 2710 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" |
| 2711 | ".Llt_fallthru:\n\t" |
| 2712 | "lea 0x8(%esp),%esp\n\t" |
| 2713 | "pop %eax\n\t" |
| 2714 | "pop %ebx"); |
| 2715 | |
| 2716 | if (offset_p) |
| 2717 | *offset_p = 20; |
| 2718 | if (size_p) |
| 2719 | *size_p = 4; |
| 2720 | } |
| 2721 | |
| 2722 | void |
| 2723 | i386_emit_le_goto (int *offset_p, int *size_p) |
| 2724 | { |
| 2725 | EMIT_ASM32 (le, |
| 2726 | "cmpl %ebx,4(%esp)\n\t" |
| 2727 | "jle .Lle_jump\n\t" |
| 2728 | "jne .Lle_fallthru\n\t" |
| 2729 | "cmpl %eax,(%esp)\n\t" |
| 2730 | "jnle .Lle_fallthru\n\t" |
| 2731 | ".Lle_jump:\n\t" |
| 2732 | "lea 0x8(%esp),%esp\n\t" |
| 2733 | "pop %eax\n\t" |
| 2734 | "pop %ebx\n\t" |
| 2735 | /* jmp, but don't trust the assembler to choose the right jump */ |
| 2736 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" |
| 2737 | ".Lle_fallthru:\n\t" |
| 2738 | "lea 0x8(%esp),%esp\n\t" |
| 2739 | "pop %eax\n\t" |
| 2740 | "pop %ebx"); |
| 2741 | |
| 2742 | if (offset_p) |
| 2743 | *offset_p = 20; |
| 2744 | if (size_p) |
| 2745 | *size_p = 4; |
| 2746 | } |
| 2747 | |
| 2748 | void |
| 2749 | i386_emit_gt_goto (int *offset_p, int *size_p) |
| 2750 | { |
| 2751 | EMIT_ASM32 (gt, |
| 2752 | "cmpl %ebx,4(%esp)\n\t" |
| 2753 | "jg .Lgt_jump\n\t" |
| 2754 | "jne .Lgt_fallthru\n\t" |
| 2755 | "cmpl %eax,(%esp)\n\t" |
| 2756 | "jng .Lgt_fallthru\n\t" |
| 2757 | ".Lgt_jump:\n\t" |
| 2758 | "lea 0x8(%esp),%esp\n\t" |
| 2759 | "pop %eax\n\t" |
| 2760 | "pop %ebx\n\t" |
| 2761 | /* jmp, but don't trust the assembler to choose the right jump */ |
| 2762 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" |
| 2763 | ".Lgt_fallthru:\n\t" |
| 2764 | "lea 0x8(%esp),%esp\n\t" |
| 2765 | "pop %eax\n\t" |
| 2766 | "pop %ebx"); |
| 2767 | |
| 2768 | if (offset_p) |
| 2769 | *offset_p = 20; |
| 2770 | if (size_p) |
| 2771 | *size_p = 4; |
| 2772 | } |
| 2773 | |
| 2774 | void |
| 2775 | i386_emit_ge_goto (int *offset_p, int *size_p) |
| 2776 | { |
| 2777 | EMIT_ASM32 (ge, |
| 2778 | "cmpl %ebx,4(%esp)\n\t" |
| 2779 | "jge .Lge_jump\n\t" |
| 2780 | "jne .Lge_fallthru\n\t" |
| 2781 | "cmpl %eax,(%esp)\n\t" |
| 2782 | "jnge .Lge_fallthru\n\t" |
| 2783 | ".Lge_jump:\n\t" |
| 2784 | "lea 0x8(%esp),%esp\n\t" |
| 2785 | "pop %eax\n\t" |
| 2786 | "pop %ebx\n\t" |
| 2787 | /* jmp, but don't trust the assembler to choose the right jump */ |
| 2788 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" |
| 2789 | ".Lge_fallthru:\n\t" |
| 2790 | "lea 0x8(%esp),%esp\n\t" |
| 2791 | "pop %eax\n\t" |
| 2792 | "pop %ebx"); |
| 2793 | |
| 2794 | if (offset_p) |
| 2795 | *offset_p = 20; |
| 2796 | if (size_p) |
| 2797 | *size_p = 4; |
| 2798 | } |
| 2799 | |
| 2800 | struct emit_ops i386_emit_ops = |
| 2801 | { |
| 2802 | i386_emit_prologue, |
| 2803 | i386_emit_epilogue, |
| 2804 | i386_emit_add, |
| 2805 | i386_emit_sub, |
| 2806 | i386_emit_mul, |
| 2807 | i386_emit_lsh, |
| 2808 | i386_emit_rsh_signed, |
| 2809 | i386_emit_rsh_unsigned, |
| 2810 | i386_emit_ext, |
| 2811 | i386_emit_log_not, |
| 2812 | i386_emit_bit_and, |
| 2813 | i386_emit_bit_or, |
| 2814 | i386_emit_bit_xor, |
| 2815 | i386_emit_bit_not, |
| 2816 | i386_emit_equal, |
| 2817 | i386_emit_less_signed, |
| 2818 | i386_emit_less_unsigned, |
| 2819 | i386_emit_ref, |
| 2820 | i386_emit_if_goto, |
| 2821 | i386_emit_goto, |
| 2822 | i386_write_goto_address, |
| 2823 | i386_emit_const, |
| 2824 | i386_emit_call, |
| 2825 | i386_emit_reg, |
| 2826 | i386_emit_pop, |
| 2827 | i386_emit_stack_flush, |
| 2828 | i386_emit_zero_ext, |
| 2829 | i386_emit_swap, |
| 2830 | i386_emit_stack_adjust, |
| 2831 | i386_emit_int_call_1, |
| 2832 | i386_emit_void_call_2, |
| 2833 | i386_emit_eq_goto, |
| 2834 | i386_emit_ne_goto, |
| 2835 | i386_emit_lt_goto, |
| 2836 | i386_emit_le_goto, |
| 2837 | i386_emit_gt_goto, |
| 2838 | i386_emit_ge_goto |
| 2839 | }; |
| 2840 | |
| 2841 | |
| 2842 | static struct emit_ops * |
| 2843 | x86_emit_ops (void) |
| 2844 | { |
| 2845 | #ifdef __x86_64__ |
| 2846 | if (is_64bit_tdesc ()) |
| 2847 | return &amd64_emit_ops; |
| 2848 | else |
| 2849 | #endif |
| 2850 | return &i386_emit_ops; |
| 2851 | } |
| 2852 | |
| 2853 | /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */ |
| 2854 | |
| 2855 | static const gdb_byte * |
| 2856 | x86_sw_breakpoint_from_kind (int kind, int *size) |
| 2857 | { |
| 2858 | *size = x86_breakpoint_len; |
| 2859 | return x86_breakpoint; |
| 2860 | } |
| 2861 | |
| 2862 | static int |
| 2863 | x86_supports_range_stepping (void) |
| 2864 | { |
| 2865 | return 1; |
| 2866 | } |
| 2867 | |
| 2868 | /* Implementation of linux_target_ops method "supports_hardware_single_step". |
| 2869 | */ |
| 2870 | |
| 2871 | static int |
| 2872 | x86_supports_hardware_single_step (void) |
| 2873 | { |
| 2874 | return 1; |
| 2875 | } |
| 2876 | |
| 2877 | static int |
| 2878 | x86_get_ipa_tdesc_idx (void) |
| 2879 | { |
| 2880 | struct regcache *regcache = get_thread_regcache (current_thread, 0); |
| 2881 | const struct target_desc *tdesc = regcache->tdesc; |
| 2882 | |
| 2883 | #ifdef __x86_64__ |
| 2884 | if (tdesc == tdesc_amd64_linux || tdesc == tdesc_amd64_linux_no_xml |
| 2885 | || tdesc == tdesc_x32_linux) |
| 2886 | return X86_TDESC_SSE; |
| 2887 | if (tdesc == tdesc_amd64_avx_linux || tdesc == tdesc_x32_avx_linux) |
| 2888 | return X86_TDESC_AVX; |
| 2889 | if (tdesc == tdesc_amd64_mpx_linux) |
| 2890 | return X86_TDESC_MPX; |
| 2891 | if (tdesc == tdesc_amd64_avx_mpx_linux) |
| 2892 | return X86_TDESC_AVX_MPX; |
| 2893 | if (tdesc == tdesc_amd64_avx_mpx_avx512_pku_linux || tdesc == tdesc_x32_avx_avx512_linux) |
| 2894 | return X86_TDESC_AVX_MPX_AVX512_PKU; |
| 2895 | if (tdesc == tdesc_amd64_avx_avx512_linux) |
| 2896 | return X86_TDESC_AVX_AVX512; |
| 2897 | #endif |
| 2898 | |
| 2899 | if (tdesc == tdesc_i386_linux_no_xml) |
| 2900 | return X86_TDESC_SSE; |
| 2901 | |
| 2902 | return i386_get_ipa_tdesc_idx (tdesc); |
| 2903 | } |
| 2904 | |
| 2905 | /* This is initialized assuming an amd64 target. |
| 2906 | x86_arch_setup will correct it for i386 or amd64 targets. */ |
| 2907 | |
| 2908 | struct linux_target_ops the_low_target = |
| 2909 | { |
| 2910 | x86_arch_setup, |
| 2911 | x86_linux_regs_info, |
| 2912 | x86_cannot_fetch_register, |
| 2913 | x86_cannot_store_register, |
| 2914 | NULL, /* fetch_register */ |
| 2915 | x86_get_pc, |
| 2916 | x86_set_pc, |
| 2917 | NULL, /* breakpoint_kind_from_pc */ |
| 2918 | x86_sw_breakpoint_from_kind, |
| 2919 | NULL, |
| 2920 | 1, |
| 2921 | x86_breakpoint_at, |
| 2922 | x86_supports_z_point_type, |
| 2923 | x86_insert_point, |
| 2924 | x86_remove_point, |
| 2925 | x86_stopped_by_watchpoint, |
| 2926 | x86_stopped_data_address, |
| 2927 | /* collect_ptrace_register/supply_ptrace_register are not needed in the |
| 2928 | native i386 case (no registers smaller than an xfer unit), and are not |
| 2929 | used in the biarch case (HAVE_LINUX_USRREGS is not defined). */ |
| 2930 | NULL, |
| 2931 | NULL, |
| 2932 | /* need to fix up i386 siginfo if host is amd64 */ |
| 2933 | x86_siginfo_fixup, |
| 2934 | x86_linux_new_process, |
| 2935 | x86_linux_new_thread, |
| 2936 | x86_linux_new_fork, |
| 2937 | x86_linux_prepare_to_resume, |
| 2938 | x86_linux_process_qsupported, |
| 2939 | x86_supports_tracepoints, |
| 2940 | x86_get_thread_area, |
| 2941 | x86_install_fast_tracepoint_jump_pad, |
| 2942 | x86_emit_ops, |
| 2943 | x86_get_min_fast_tracepoint_insn_len, |
| 2944 | x86_supports_range_stepping, |
| 2945 | NULL, /* breakpoint_kind_from_current_state */ |
| 2946 | x86_supports_hardware_single_step, |
| 2947 | x86_get_syscall_trapinfo, |
| 2948 | x86_get_ipa_tdesc_idx, |
| 2949 | }; |
| 2950 | |
| 2951 | void |
| 2952 | initialize_low_arch (void) |
| 2953 | { |
| 2954 | /* Initialize the Linux target descriptions. */ |
| 2955 | #ifdef __x86_64__ |
| 2956 | init_registers_amd64_linux (); |
| 2957 | init_registers_amd64_avx_linux (); |
| 2958 | init_registers_amd64_mpx_linux (); |
| 2959 | init_registers_amd64_avx_mpx_linux (); |
| 2960 | init_registers_amd64_avx_avx512_linux (); |
| 2961 | init_registers_amd64_avx_mpx_avx512_pku_linux (); |
| 2962 | |
| 2963 | init_registers_x32_linux (); |
| 2964 | init_registers_x32_avx_linux (); |
| 2965 | init_registers_x32_avx_avx512_linux (); |
| 2966 | |
| 2967 | tdesc_amd64_linux_no_xml = XNEW (struct target_desc); |
| 2968 | copy_target_description (tdesc_amd64_linux_no_xml, tdesc_amd64_linux); |
| 2969 | tdesc_amd64_linux_no_xml->xmltarget = xmltarget_amd64_linux_no_xml; |
| 2970 | #endif |
| 2971 | |
| 2972 | #if GDB_SELF_TEST |
| 2973 | initialize_low_tdesc (); |
| 2974 | #endif |
| 2975 | |
| 2976 | tdesc_i386_linux_no_xml = XNEW (struct target_desc); |
| 2977 | copy_target_description (tdesc_i386_linux_no_xml, |
| 2978 | i386_linux_read_description (X86_XSTATE_SSE_MASK)); |
| 2979 | tdesc_i386_linux_no_xml->xmltarget = xmltarget_i386_linux_no_xml; |
| 2980 | |
| 2981 | initialize_regsets_info (&x86_regsets_info); |
| 2982 | } |