| 1 | /* Intel 386 target-dependent stuff. |
| 2 | |
| 3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
| 4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, |
| 5 | 2010 Free Software Foundation, Inc. |
| 6 | |
| 7 | This file is part of GDB. |
| 8 | |
| 9 | This program is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 3 of the License, or |
| 12 | (at your option) any later version. |
| 13 | |
| 14 | This program is distributed in the hope that it will be useful, |
| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License |
| 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 21 | |
| 22 | #include "defs.h" |
| 23 | #include "opcode/i386.h" |
| 24 | #include "arch-utils.h" |
| 25 | #include "command.h" |
| 26 | #include "dummy-frame.h" |
| 27 | #include "dwarf2-frame.h" |
| 28 | #include "doublest.h" |
| 29 | #include "frame.h" |
| 30 | #include "frame-base.h" |
| 31 | #include "frame-unwind.h" |
| 32 | #include "inferior.h" |
| 33 | #include "gdbcmd.h" |
| 34 | #include "gdbcore.h" |
| 35 | #include "gdbtypes.h" |
| 36 | #include "objfiles.h" |
| 37 | #include "osabi.h" |
| 38 | #include "regcache.h" |
| 39 | #include "reggroups.h" |
| 40 | #include "regset.h" |
| 41 | #include "symfile.h" |
| 42 | #include "symtab.h" |
| 43 | #include "target.h" |
| 44 | #include "value.h" |
| 45 | #include "dis-asm.h" |
| 46 | #include "disasm.h" |
| 47 | |
| 48 | #include "gdb_assert.h" |
| 49 | #include "gdb_string.h" |
| 50 | |
| 51 | #include "i386-tdep.h" |
| 52 | #include "i387-tdep.h" |
| 53 | |
| 54 | #include "record.h" |
| 55 | #include <stdint.h> |
| 56 | |
| 57 | #include "features/i386/i386.c" |
| 58 | |
| 59 | /* Register names. */ |
| 60 | |
| 61 | static const char *i386_register_names[] = |
| 62 | { |
| 63 | "eax", "ecx", "edx", "ebx", |
| 64 | "esp", "ebp", "esi", "edi", |
| 65 | "eip", "eflags", "cs", "ss", |
| 66 | "ds", "es", "fs", "gs", |
| 67 | "st0", "st1", "st2", "st3", |
| 68 | "st4", "st5", "st6", "st7", |
| 69 | "fctrl", "fstat", "ftag", "fiseg", |
| 70 | "fioff", "foseg", "fooff", "fop", |
| 71 | "xmm0", "xmm1", "xmm2", "xmm3", |
| 72 | "xmm4", "xmm5", "xmm6", "xmm7", |
| 73 | "mxcsr" |
| 74 | }; |
| 75 | |
| 76 | /* Register names for MMX pseudo-registers. */ |
| 77 | |
| 78 | static const char *i386_mmx_names[] = |
| 79 | { |
| 80 | "mm0", "mm1", "mm2", "mm3", |
| 81 | "mm4", "mm5", "mm6", "mm7" |
| 82 | }; |
| 83 | |
| 84 | /* Register names for byte pseudo-registers. */ |
| 85 | |
| 86 | static const char *i386_byte_names[] = |
| 87 | { |
| 88 | "al", "cl", "dl", "bl", |
| 89 | "ah", "ch", "dh", "bh" |
| 90 | }; |
| 91 | |
| 92 | /* Register names for word pseudo-registers. */ |
| 93 | |
| 94 | static const char *i386_word_names[] = |
| 95 | { |
| 96 | "ax", "cx", "dx", "bx", |
| 97 | "", "bp", "si", "di" |
| 98 | }; |
| 99 | |
| 100 | /* MMX register? */ |
| 101 | |
| 102 | static int |
| 103 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
| 104 | { |
| 105 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 106 | int mm0_regnum = tdep->mm0_regnum; |
| 107 | |
| 108 | if (mm0_regnum < 0) |
| 109 | return 0; |
| 110 | |
| 111 | regnum -= mm0_regnum; |
| 112 | return regnum >= 0 && regnum < tdep->num_mmx_regs; |
| 113 | } |
| 114 | |
| 115 | /* Byte register? */ |
| 116 | |
| 117 | int |
| 118 | i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) |
| 119 | { |
| 120 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 121 | |
| 122 | regnum -= tdep->al_regnum; |
| 123 | return regnum >= 0 && regnum < tdep->num_byte_regs; |
| 124 | } |
| 125 | |
| 126 | /* Word register? */ |
| 127 | |
| 128 | int |
| 129 | i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) |
| 130 | { |
| 131 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 132 | |
| 133 | regnum -= tdep->ax_regnum; |
| 134 | return regnum >= 0 && regnum < tdep->num_word_regs; |
| 135 | } |
| 136 | |
| 137 | /* Dword register? */ |
| 138 | |
| 139 | int |
| 140 | i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) |
| 141 | { |
| 142 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 143 | int eax_regnum = tdep->eax_regnum; |
| 144 | |
| 145 | if (eax_regnum < 0) |
| 146 | return 0; |
| 147 | |
| 148 | regnum -= eax_regnum; |
| 149 | return regnum >= 0 && regnum < tdep->num_dword_regs; |
| 150 | } |
| 151 | |
| 152 | /* SSE register? */ |
| 153 | |
| 154 | static int |
| 155 | i386_sse_regnum_p (struct gdbarch *gdbarch, int regnum) |
| 156 | { |
| 157 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 158 | |
| 159 | if (I387_NUM_XMM_REGS (tdep) == 0) |
| 160 | return 0; |
| 161 | |
| 162 | return (I387_XMM0_REGNUM (tdep) <= regnum |
| 163 | && regnum < I387_MXCSR_REGNUM (tdep)); |
| 164 | } |
| 165 | |
| 166 | static int |
| 167 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) |
| 168 | { |
| 169 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 170 | |
| 171 | if (I387_NUM_XMM_REGS (tdep) == 0) |
| 172 | return 0; |
| 173 | |
| 174 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
| 175 | } |
| 176 | |
| 177 | /* FP register? */ |
| 178 | |
| 179 | int |
| 180 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
| 181 | { |
| 182 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 183 | |
| 184 | if (I387_ST0_REGNUM (tdep) < 0) |
| 185 | return 0; |
| 186 | |
| 187 | return (I387_ST0_REGNUM (tdep) <= regnum |
| 188 | && regnum < I387_FCTRL_REGNUM (tdep)); |
| 189 | } |
| 190 | |
| 191 | int |
| 192 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
| 193 | { |
| 194 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 195 | |
| 196 | if (I387_ST0_REGNUM (tdep) < 0) |
| 197 | return 0; |
| 198 | |
| 199 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
| 200 | && regnum < I387_XMM0_REGNUM (tdep)); |
| 201 | } |
| 202 | |
| 203 | /* Return the name of register REGNUM. */ |
| 204 | |
| 205 | const char * |
| 206 | i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) |
| 207 | { |
| 208 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 209 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
| 210 | return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; |
| 211 | else if (i386_byte_regnum_p (gdbarch, regnum)) |
| 212 | return i386_byte_names[regnum - tdep->al_regnum]; |
| 213 | else if (i386_word_regnum_p (gdbarch, regnum)) |
| 214 | return i386_word_names[regnum - tdep->ax_regnum]; |
| 215 | |
| 216 | internal_error (__FILE__, __LINE__, _("invalid regnum")); |
| 217 | } |
| 218 | |
| 219 | /* Convert a dbx register number REG to the appropriate register |
| 220 | number used by GDB. */ |
| 221 | |
| 222 | static int |
| 223 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
| 224 | { |
| 225 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 226 | |
| 227 | /* This implements what GCC calls the "default" register map |
| 228 | (dbx_register_map[]). */ |
| 229 | |
| 230 | if (reg >= 0 && reg <= 7) |
| 231 | { |
| 232 | /* General-purpose registers. The debug info calls %ebp |
| 233 | register 4, and %esp register 5. */ |
| 234 | if (reg == 4) |
| 235 | return 5; |
| 236 | else if (reg == 5) |
| 237 | return 4; |
| 238 | else return reg; |
| 239 | } |
| 240 | else if (reg >= 12 && reg <= 19) |
| 241 | { |
| 242 | /* Floating-point registers. */ |
| 243 | return reg - 12 + I387_ST0_REGNUM (tdep); |
| 244 | } |
| 245 | else if (reg >= 21 && reg <= 28) |
| 246 | { |
| 247 | /* SSE registers. */ |
| 248 | return reg - 21 + I387_XMM0_REGNUM (tdep); |
| 249 | } |
| 250 | else if (reg >= 29 && reg <= 36) |
| 251 | { |
| 252 | /* MMX registers. */ |
| 253 | return reg - 29 + I387_MM0_REGNUM (tdep); |
| 254 | } |
| 255 | |
| 256 | /* This will hopefully provoke a warning. */ |
| 257 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
| 258 | } |
| 259 | |
| 260 | /* Convert SVR4 register number REG to the appropriate register number |
| 261 | used by GDB. */ |
| 262 | |
| 263 | static int |
| 264 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
| 265 | { |
| 266 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 267 | |
| 268 | /* This implements the GCC register map that tries to be compatible |
| 269 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ |
| 270 | |
| 271 | /* The SVR4 register numbering includes %eip and %eflags, and |
| 272 | numbers the floating point registers differently. */ |
| 273 | if (reg >= 0 && reg <= 9) |
| 274 | { |
| 275 | /* General-purpose registers. */ |
| 276 | return reg; |
| 277 | } |
| 278 | else if (reg >= 11 && reg <= 18) |
| 279 | { |
| 280 | /* Floating-point registers. */ |
| 281 | return reg - 11 + I387_ST0_REGNUM (tdep); |
| 282 | } |
| 283 | else if (reg >= 21 && reg <= 36) |
| 284 | { |
| 285 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
| 286 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
| 287 | } |
| 288 | |
| 289 | switch (reg) |
| 290 | { |
| 291 | case 37: return I387_FCTRL_REGNUM (tdep); |
| 292 | case 38: return I387_FSTAT_REGNUM (tdep); |
| 293 | case 39: return I387_MXCSR_REGNUM (tdep); |
| 294 | case 40: return I386_ES_REGNUM; |
| 295 | case 41: return I386_CS_REGNUM; |
| 296 | case 42: return I386_SS_REGNUM; |
| 297 | case 43: return I386_DS_REGNUM; |
| 298 | case 44: return I386_FS_REGNUM; |
| 299 | case 45: return I386_GS_REGNUM; |
| 300 | } |
| 301 | |
| 302 | /* This will hopefully provoke a warning. */ |
| 303 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
| 304 | } |
| 305 | |
| 306 | \f |
| 307 | |
| 308 | /* This is the variable that is set with "set disassembly-flavor", and |
| 309 | its legitimate values. */ |
| 310 | static const char att_flavor[] = "att"; |
| 311 | static const char intel_flavor[] = "intel"; |
| 312 | static const char *valid_flavors[] = |
| 313 | { |
| 314 | att_flavor, |
| 315 | intel_flavor, |
| 316 | NULL |
| 317 | }; |
| 318 | static const char *disassembly_flavor = att_flavor; |
| 319 | \f |
| 320 | |
| 321 | /* Use the program counter to determine the contents and size of a |
| 322 | breakpoint instruction. Return a pointer to a string of bytes that |
| 323 | encode a breakpoint instruction, store the length of the string in |
| 324 | *LEN and optionally adjust *PC to point to the correct memory |
| 325 | location for inserting the breakpoint. |
| 326 | |
| 327 | On the i386 we have a single breakpoint that fits in a single byte |
| 328 | and can be inserted anywhere. |
| 329 | |
| 330 | This function is 64-bit safe. */ |
| 331 | |
| 332 | static const gdb_byte * |
| 333 | i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
| 334 | { |
| 335 | static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ |
| 336 | |
| 337 | *len = sizeof (break_insn); |
| 338 | return break_insn; |
| 339 | } |
| 340 | \f |
| 341 | /* Displaced instruction handling. */ |
| 342 | |
| 343 | /* Skip the legacy instruction prefixes in INSN. |
| 344 | Not all prefixes are valid for any particular insn |
| 345 | but we needn't care, the insn will fault if it's invalid. |
| 346 | The result is a pointer to the first opcode byte, |
| 347 | or NULL if we run off the end of the buffer. */ |
| 348 | |
| 349 | static gdb_byte * |
| 350 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) |
| 351 | { |
| 352 | gdb_byte *end = insn + max_len; |
| 353 | |
| 354 | while (insn < end) |
| 355 | { |
| 356 | switch (*insn) |
| 357 | { |
| 358 | case DATA_PREFIX_OPCODE: |
| 359 | case ADDR_PREFIX_OPCODE: |
| 360 | case CS_PREFIX_OPCODE: |
| 361 | case DS_PREFIX_OPCODE: |
| 362 | case ES_PREFIX_OPCODE: |
| 363 | case FS_PREFIX_OPCODE: |
| 364 | case GS_PREFIX_OPCODE: |
| 365 | case SS_PREFIX_OPCODE: |
| 366 | case LOCK_PREFIX_OPCODE: |
| 367 | case REPE_PREFIX_OPCODE: |
| 368 | case REPNE_PREFIX_OPCODE: |
| 369 | ++insn; |
| 370 | continue; |
| 371 | default: |
| 372 | return insn; |
| 373 | } |
| 374 | } |
| 375 | |
| 376 | return NULL; |
| 377 | } |
| 378 | |
| 379 | static int |
| 380 | i386_absolute_jmp_p (const gdb_byte *insn) |
| 381 | { |
| 382 | /* jmp far (absolute address in operand) */ |
| 383 | if (insn[0] == 0xea) |
| 384 | return 1; |
| 385 | |
| 386 | if (insn[0] == 0xff) |
| 387 | { |
| 388 | /* jump near, absolute indirect (/4) */ |
| 389 | if ((insn[1] & 0x38) == 0x20) |
| 390 | return 1; |
| 391 | |
| 392 | /* jump far, absolute indirect (/5) */ |
| 393 | if ((insn[1] & 0x38) == 0x28) |
| 394 | return 1; |
| 395 | } |
| 396 | |
| 397 | return 0; |
| 398 | } |
| 399 | |
| 400 | static int |
| 401 | i386_absolute_call_p (const gdb_byte *insn) |
| 402 | { |
| 403 | /* call far, absolute */ |
| 404 | if (insn[0] == 0x9a) |
| 405 | return 1; |
| 406 | |
| 407 | if (insn[0] == 0xff) |
| 408 | { |
| 409 | /* Call near, absolute indirect (/2) */ |
| 410 | if ((insn[1] & 0x38) == 0x10) |
| 411 | return 1; |
| 412 | |
| 413 | /* Call far, absolute indirect (/3) */ |
| 414 | if ((insn[1] & 0x38) == 0x18) |
| 415 | return 1; |
| 416 | } |
| 417 | |
| 418 | return 0; |
| 419 | } |
| 420 | |
| 421 | static int |
| 422 | i386_ret_p (const gdb_byte *insn) |
| 423 | { |
| 424 | switch (insn[0]) |
| 425 | { |
| 426 | case 0xc2: /* ret near, pop N bytes */ |
| 427 | case 0xc3: /* ret near */ |
| 428 | case 0xca: /* ret far, pop N bytes */ |
| 429 | case 0xcb: /* ret far */ |
| 430 | case 0xcf: /* iret */ |
| 431 | return 1; |
| 432 | |
| 433 | default: |
| 434 | return 0; |
| 435 | } |
| 436 | } |
| 437 | |
| 438 | static int |
| 439 | i386_call_p (const gdb_byte *insn) |
| 440 | { |
| 441 | if (i386_absolute_call_p (insn)) |
| 442 | return 1; |
| 443 | |
| 444 | /* call near, relative */ |
| 445 | if (insn[0] == 0xe8) |
| 446 | return 1; |
| 447 | |
| 448 | return 0; |
| 449 | } |
| 450 | |
| 451 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
| 452 | length in bytes. Otherwise, return zero. */ |
| 453 | |
| 454 | static int |
| 455 | i386_syscall_p (const gdb_byte *insn, ULONGEST *lengthp) |
| 456 | { |
| 457 | if (insn[0] == 0xcd) |
| 458 | { |
| 459 | *lengthp = 2; |
| 460 | return 1; |
| 461 | } |
| 462 | |
| 463 | return 0; |
| 464 | } |
| 465 | |
| 466 | /* Fix up the state of registers and memory after having single-stepped |
| 467 | a displaced instruction. */ |
| 468 | |
| 469 | void |
| 470 | i386_displaced_step_fixup (struct gdbarch *gdbarch, |
| 471 | struct displaced_step_closure *closure, |
| 472 | CORE_ADDR from, CORE_ADDR to, |
| 473 | struct regcache *regs) |
| 474 | { |
| 475 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 476 | |
| 477 | /* The offset we applied to the instruction's address. |
| 478 | This could well be negative (when viewed as a signed 32-bit |
| 479 | value), but ULONGEST won't reflect that, so take care when |
| 480 | applying it. */ |
| 481 | ULONGEST insn_offset = to - from; |
| 482 | |
| 483 | /* Since we use simple_displaced_step_copy_insn, our closure is a |
| 484 | copy of the instruction. */ |
| 485 | gdb_byte *insn = (gdb_byte *) closure; |
| 486 | /* The start of the insn, needed in case we see some prefixes. */ |
| 487 | gdb_byte *insn_start = insn; |
| 488 | |
| 489 | if (debug_displaced) |
| 490 | fprintf_unfiltered (gdb_stdlog, |
| 491 | "displaced: fixup (%s, %s), " |
| 492 | "insn = 0x%02x 0x%02x ...\n", |
| 493 | paddress (gdbarch, from), paddress (gdbarch, to), |
| 494 | insn[0], insn[1]); |
| 495 | |
| 496 | /* The list of issues to contend with here is taken from |
| 497 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. |
| 498 | Yay for Free Software! */ |
| 499 | |
| 500 | /* Relocate the %eip, if necessary. */ |
| 501 | |
| 502 | /* The instruction recognizers we use assume any leading prefixes |
| 503 | have been skipped. */ |
| 504 | { |
| 505 | /* This is the size of the buffer in closure. */ |
| 506 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); |
| 507 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); |
| 508 | /* If there are too many prefixes, just ignore the insn. |
| 509 | It will fault when run. */ |
| 510 | if (opcode != NULL) |
| 511 | insn = opcode; |
| 512 | } |
| 513 | |
| 514 | /* Except in the case of absolute or indirect jump or call |
| 515 | instructions, or a return instruction, the new eip is relative to |
| 516 | the displaced instruction; make it relative. Well, signal |
| 517 | handler returns don't need relocation either, but we use the |
| 518 | value of %eip to recognize those; see below. */ |
| 519 | if (! i386_absolute_jmp_p (insn) |
| 520 | && ! i386_absolute_call_p (insn) |
| 521 | && ! i386_ret_p (insn)) |
| 522 | { |
| 523 | ULONGEST orig_eip; |
| 524 | ULONGEST insn_len; |
| 525 | |
| 526 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); |
| 527 | |
| 528 | /* A signal trampoline system call changes the %eip, resuming |
| 529 | execution of the main program after the signal handler has |
| 530 | returned. That makes them like 'return' instructions; we |
| 531 | shouldn't relocate %eip. |
| 532 | |
| 533 | But most system calls don't, and we do need to relocate %eip. |
| 534 | |
| 535 | Our heuristic for distinguishing these cases: if stepping |
| 536 | over the system call instruction left control directly after |
| 537 | the instruction, the we relocate --- control almost certainly |
| 538 | doesn't belong in the displaced copy. Otherwise, we assume |
| 539 | the instruction has put control where it belongs, and leave |
| 540 | it unrelocated. Goodness help us if there are PC-relative |
| 541 | system calls. */ |
| 542 | if (i386_syscall_p (insn, &insn_len) |
| 543 | && orig_eip != to + (insn - insn_start) + insn_len) |
| 544 | { |
| 545 | if (debug_displaced) |
| 546 | fprintf_unfiltered (gdb_stdlog, |
| 547 | "displaced: syscall changed %%eip; " |
| 548 | "not relocating\n"); |
| 549 | } |
| 550 | else |
| 551 | { |
| 552 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; |
| 553 | |
| 554 | /* If we just stepped over a breakpoint insn, we don't backup |
| 555 | the pc on purpose; this is to match behaviour without |
| 556 | stepping. */ |
| 557 | |
| 558 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); |
| 559 | |
| 560 | if (debug_displaced) |
| 561 | fprintf_unfiltered (gdb_stdlog, |
| 562 | "displaced: " |
| 563 | "relocated %%eip from %s to %s\n", |
| 564 | paddress (gdbarch, orig_eip), |
| 565 | paddress (gdbarch, eip)); |
| 566 | } |
| 567 | } |
| 568 | |
| 569 | /* If the instruction was PUSHFL, then the TF bit will be set in the |
| 570 | pushed value, and should be cleared. We'll leave this for later, |
| 571 | since GDB already messes up the TF flag when stepping over a |
| 572 | pushfl. */ |
| 573 | |
| 574 | /* If the instruction was a call, the return address now atop the |
| 575 | stack is the address following the copied instruction. We need |
| 576 | to make it the address following the original instruction. */ |
| 577 | if (i386_call_p (insn)) |
| 578 | { |
| 579 | ULONGEST esp; |
| 580 | ULONGEST retaddr; |
| 581 | const ULONGEST retaddr_len = 4; |
| 582 | |
| 583 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); |
| 584 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
| 585 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
| 586 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
| 587 | |
| 588 | if (debug_displaced) |
| 589 | fprintf_unfiltered (gdb_stdlog, |
| 590 | "displaced: relocated return addr at %s to %s\n", |
| 591 | paddress (gdbarch, esp), |
| 592 | paddress (gdbarch, retaddr)); |
| 593 | } |
| 594 | } |
| 595 | \f |
| 596 | #ifdef I386_REGNO_TO_SYMMETRY |
| 597 | #error "The Sequent Symmetry is no longer supported." |
| 598 | #endif |
| 599 | |
| 600 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
| 601 | and %esp "belong" to the calling function. Therefore these |
| 602 | registers should be saved if they're going to be modified. */ |
| 603 | |
| 604 | /* The maximum number of saved registers. This should include all |
| 605 | registers mentioned above, and %eip. */ |
| 606 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
| 607 | |
| 608 | struct i386_frame_cache |
| 609 | { |
| 610 | /* Base address. */ |
| 611 | CORE_ADDR base; |
| 612 | LONGEST sp_offset; |
| 613 | CORE_ADDR pc; |
| 614 | |
| 615 | /* Saved registers. */ |
| 616 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; |
| 617 | CORE_ADDR saved_sp; |
| 618 | int saved_sp_reg; |
| 619 | int pc_in_eax; |
| 620 | |
| 621 | /* Stack space reserved for local variables. */ |
| 622 | long locals; |
| 623 | }; |
| 624 | |
| 625 | /* Allocate and initialize a frame cache. */ |
| 626 | |
| 627 | static struct i386_frame_cache * |
| 628 | i386_alloc_frame_cache (void) |
| 629 | { |
| 630 | struct i386_frame_cache *cache; |
| 631 | int i; |
| 632 | |
| 633 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); |
| 634 | |
| 635 | /* Base address. */ |
| 636 | cache->base = 0; |
| 637 | cache->sp_offset = -4; |
| 638 | cache->pc = 0; |
| 639 | |
| 640 | /* Saved registers. We initialize these to -1 since zero is a valid |
| 641 | offset (that's where %ebp is supposed to be stored). */ |
| 642 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) |
| 643 | cache->saved_regs[i] = -1; |
| 644 | cache->saved_sp = 0; |
| 645 | cache->saved_sp_reg = -1; |
| 646 | cache->pc_in_eax = 0; |
| 647 | |
| 648 | /* Frameless until proven otherwise. */ |
| 649 | cache->locals = -1; |
| 650 | |
| 651 | return cache; |
| 652 | } |
| 653 | |
| 654 | /* If the instruction at PC is a jump, return the address of its |
| 655 | target. Otherwise, return PC. */ |
| 656 | |
| 657 | static CORE_ADDR |
| 658 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 659 | { |
| 660 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 661 | gdb_byte op; |
| 662 | long delta = 0; |
| 663 | int data16 = 0; |
| 664 | |
| 665 | target_read_memory (pc, &op, 1); |
| 666 | if (op == 0x66) |
| 667 | { |
| 668 | data16 = 1; |
| 669 | op = read_memory_unsigned_integer (pc + 1, 1, byte_order); |
| 670 | } |
| 671 | |
| 672 | switch (op) |
| 673 | { |
| 674 | case 0xe9: |
| 675 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
| 676 | if (data16) |
| 677 | { |
| 678 | delta = read_memory_integer (pc + 2, 2, byte_order); |
| 679 | |
| 680 | /* Include the size of the jmp instruction (including the |
| 681 | 0x66 prefix). */ |
| 682 | delta += 4; |
| 683 | } |
| 684 | else |
| 685 | { |
| 686 | delta = read_memory_integer (pc + 1, 4, byte_order); |
| 687 | |
| 688 | /* Include the size of the jmp instruction. */ |
| 689 | delta += 5; |
| 690 | } |
| 691 | break; |
| 692 | case 0xeb: |
| 693 | /* Relative jump, disp8 (ignore data16). */ |
| 694 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
| 695 | |
| 696 | delta += data16 + 2; |
| 697 | break; |
| 698 | } |
| 699 | |
| 700 | return pc + delta; |
| 701 | } |
| 702 | |
| 703 | /* Check whether PC points at a prologue for a function returning a |
| 704 | structure or union. If so, it updates CACHE and returns the |
| 705 | address of the first instruction after the code sequence that |
| 706 | removes the "hidden" argument from the stack or CURRENT_PC, |
| 707 | whichever is smaller. Otherwise, return PC. */ |
| 708 | |
| 709 | static CORE_ADDR |
| 710 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, |
| 711 | struct i386_frame_cache *cache) |
| 712 | { |
| 713 | /* Functions that return a structure or union start with: |
| 714 | |
| 715 | popl %eax 0x58 |
| 716 | xchgl %eax, (%esp) 0x87 0x04 0x24 |
| 717 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 |
| 718 | |
| 719 | (the System V compiler puts out the second `xchg' instruction, |
| 720 | and the assembler doesn't try to optimize it, so the 'sib' form |
| 721 | gets generated). This sequence is used to get the address of the |
| 722 | return buffer for a function that returns a structure. */ |
| 723 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
| 724 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; |
| 725 | gdb_byte buf[4]; |
| 726 | gdb_byte op; |
| 727 | |
| 728 | if (current_pc <= pc) |
| 729 | return pc; |
| 730 | |
| 731 | target_read_memory (pc, &op, 1); |
| 732 | |
| 733 | if (op != 0x58) /* popl %eax */ |
| 734 | return pc; |
| 735 | |
| 736 | target_read_memory (pc + 1, buf, 4); |
| 737 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
| 738 | return pc; |
| 739 | |
| 740 | if (current_pc == pc) |
| 741 | { |
| 742 | cache->sp_offset += 4; |
| 743 | return current_pc; |
| 744 | } |
| 745 | |
| 746 | if (current_pc == pc + 1) |
| 747 | { |
| 748 | cache->pc_in_eax = 1; |
| 749 | return current_pc; |
| 750 | } |
| 751 | |
| 752 | if (buf[1] == proto1[1]) |
| 753 | return pc + 4; |
| 754 | else |
| 755 | return pc + 5; |
| 756 | } |
| 757 | |
| 758 | static CORE_ADDR |
| 759 | i386_skip_probe (CORE_ADDR pc) |
| 760 | { |
| 761 | /* A function may start with |
| 762 | |
| 763 | pushl constant |
| 764 | call _probe |
| 765 | addl $4, %esp |
| 766 | |
| 767 | followed by |
| 768 | |
| 769 | pushl %ebp |
| 770 | |
| 771 | etc. */ |
| 772 | gdb_byte buf[8]; |
| 773 | gdb_byte op; |
| 774 | |
| 775 | target_read_memory (pc, &op, 1); |
| 776 | |
| 777 | if (op == 0x68 || op == 0x6a) |
| 778 | { |
| 779 | int delta; |
| 780 | |
| 781 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
| 782 | four-byte operand, depending on the opcode. */ |
| 783 | if (op == 0x68) |
| 784 | delta = 5; |
| 785 | else |
| 786 | delta = 2; |
| 787 | |
| 788 | /* Read the following 8 bytes, which should be `call _probe' (6 |
| 789 | bytes) followed by `addl $4,%esp' (2 bytes). */ |
| 790 | read_memory (pc + delta, buf, sizeof (buf)); |
| 791 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
| 792 | pc += delta + sizeof (buf); |
| 793 | } |
| 794 | |
| 795 | return pc; |
| 796 | } |
| 797 | |
| 798 | /* GCC 4.1 and later, can put code in the prologue to realign the |
| 799 | stack pointer. Check whether PC points to such code, and update |
| 800 | CACHE accordingly. Return the first instruction after the code |
| 801 | sequence or CURRENT_PC, whichever is smaller. If we don't |
| 802 | recognize the code, return PC. */ |
| 803 | |
| 804 | static CORE_ADDR |
| 805 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, |
| 806 | struct i386_frame_cache *cache) |
| 807 | { |
| 808 | /* There are 2 code sequences to re-align stack before the frame |
| 809 | gets set up: |
| 810 | |
| 811 | 1. Use a caller-saved saved register: |
| 812 | |
| 813 | leal 4(%esp), %reg |
| 814 | andl $-XXX, %esp |
| 815 | pushl -4(%reg) |
| 816 | |
| 817 | 2. Use a callee-saved saved register: |
| 818 | |
| 819 | pushl %reg |
| 820 | leal 8(%esp), %reg |
| 821 | andl $-XXX, %esp |
| 822 | pushl -4(%reg) |
| 823 | |
| 824 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: |
| 825 | |
| 826 | 0x83 0xe4 0xf0 andl $-16, %esp |
| 827 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp |
| 828 | */ |
| 829 | |
| 830 | gdb_byte buf[14]; |
| 831 | int reg; |
| 832 | int offset, offset_and; |
| 833 | static int regnums[8] = { |
| 834 | I386_EAX_REGNUM, /* %eax */ |
| 835 | I386_ECX_REGNUM, /* %ecx */ |
| 836 | I386_EDX_REGNUM, /* %edx */ |
| 837 | I386_EBX_REGNUM, /* %ebx */ |
| 838 | I386_ESP_REGNUM, /* %esp */ |
| 839 | I386_EBP_REGNUM, /* %ebp */ |
| 840 | I386_ESI_REGNUM, /* %esi */ |
| 841 | I386_EDI_REGNUM /* %edi */ |
| 842 | }; |
| 843 | |
| 844 | if (target_read_memory (pc, buf, sizeof buf)) |
| 845 | return pc; |
| 846 | |
| 847 | /* Check caller-saved saved register. The first instruction has |
| 848 | to be "leal 4(%esp), %reg". */ |
| 849 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) |
| 850 | { |
| 851 | /* MOD must be binary 10 and R/M must be binary 100. */ |
| 852 | if ((buf[1] & 0xc7) != 0x44) |
| 853 | return pc; |
| 854 | |
| 855 | /* REG has register number. */ |
| 856 | reg = (buf[1] >> 3) & 7; |
| 857 | offset = 4; |
| 858 | } |
| 859 | else |
| 860 | { |
| 861 | /* Check callee-saved saved register. The first instruction |
| 862 | has to be "pushl %reg". */ |
| 863 | if ((buf[0] & 0xf8) != 0x50) |
| 864 | return pc; |
| 865 | |
| 866 | /* Get register. */ |
| 867 | reg = buf[0] & 0x7; |
| 868 | |
| 869 | /* The next instruction has to be "leal 8(%esp), %reg". */ |
| 870 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) |
| 871 | return pc; |
| 872 | |
| 873 | /* MOD must be binary 10 and R/M must be binary 100. */ |
| 874 | if ((buf[2] & 0xc7) != 0x44) |
| 875 | return pc; |
| 876 | |
| 877 | /* REG has register number. Registers in pushl and leal have to |
| 878 | be the same. */ |
| 879 | if (reg != ((buf[2] >> 3) & 7)) |
| 880 | return pc; |
| 881 | |
| 882 | offset = 5; |
| 883 | } |
| 884 | |
| 885 | /* Rigister can't be %esp nor %ebp. */ |
| 886 | if (reg == 4 || reg == 5) |
| 887 | return pc; |
| 888 | |
| 889 | /* The next instruction has to be "andl $-XXX, %esp". */ |
| 890 | if (buf[offset + 1] != 0xe4 |
| 891 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) |
| 892 | return pc; |
| 893 | |
| 894 | offset_and = offset; |
| 895 | offset += buf[offset] == 0x81 ? 6 : 3; |
| 896 | |
| 897 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is |
| 898 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ |
| 899 | if (buf[offset] != 0xff |
| 900 | || buf[offset + 2] != 0xfc |
| 901 | || (buf[offset + 1] & 0xf8) != 0x70) |
| 902 | return pc; |
| 903 | |
| 904 | /* R/M has register. Registers in leal and pushl have to be the |
| 905 | same. */ |
| 906 | if (reg != (buf[offset + 1] & 7)) |
| 907 | return pc; |
| 908 | |
| 909 | if (current_pc > pc + offset_and) |
| 910 | cache->saved_sp_reg = regnums[reg]; |
| 911 | |
| 912 | return min (pc + offset + 3, current_pc); |
| 913 | } |
| 914 | |
| 915 | /* Maximum instruction length we need to handle. */ |
| 916 | #define I386_MAX_MATCHED_INSN_LEN 6 |
| 917 | |
| 918 | /* Instruction description. */ |
| 919 | struct i386_insn |
| 920 | { |
| 921 | size_t len; |
| 922 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
| 923 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; |
| 924 | }; |
| 925 | |
| 926 | /* Search for the instruction at PC in the list SKIP_INSNS. Return |
| 927 | the first instruction description that matches. Otherwise, return |
| 928 | NULL. */ |
| 929 | |
| 930 | static struct i386_insn * |
| 931 | i386_match_insn (CORE_ADDR pc, struct i386_insn *skip_insns) |
| 932 | { |
| 933 | struct i386_insn *insn; |
| 934 | gdb_byte op; |
| 935 | |
| 936 | target_read_memory (pc, &op, 1); |
| 937 | |
| 938 | for (insn = skip_insns; insn->len > 0; insn++) |
| 939 | { |
| 940 | if ((op & insn->mask[0]) == insn->insn[0]) |
| 941 | { |
| 942 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
| 943 | int insn_matched = 1; |
| 944 | size_t i; |
| 945 | |
| 946 | gdb_assert (insn->len > 1); |
| 947 | gdb_assert (insn->len <= I386_MAX_MATCHED_INSN_LEN); |
| 948 | |
| 949 | target_read_memory (pc + 1, buf, insn->len - 1); |
| 950 | for (i = 1; i < insn->len; i++) |
| 951 | { |
| 952 | if ((buf[i - 1] & insn->mask[i]) != insn->insn[i]) |
| 953 | insn_matched = 0; |
| 954 | } |
| 955 | |
| 956 | if (insn_matched) |
| 957 | return insn; |
| 958 | } |
| 959 | } |
| 960 | |
| 961 | return NULL; |
| 962 | } |
| 963 | |
| 964 | /* Some special instructions that might be migrated by GCC into the |
| 965 | part of the prologue that sets up the new stack frame. Because the |
| 966 | stack frame hasn't been setup yet, no registers have been saved |
| 967 | yet, and only the scratch registers %eax, %ecx and %edx can be |
| 968 | touched. */ |
| 969 | |
| 970 | struct i386_insn i386_frame_setup_skip_insns[] = |
| 971 | { |
| 972 | /* Check for `movb imm8, r' and `movl imm32, r'. |
| 973 | |
| 974 | ??? Should we handle 16-bit operand-sizes here? */ |
| 975 | |
| 976 | /* `movb imm8, %al' and `movb imm8, %ah' */ |
| 977 | /* `movb imm8, %cl' and `movb imm8, %ch' */ |
| 978 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, |
| 979 | /* `movb imm8, %dl' and `movb imm8, %dh' */ |
| 980 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, |
| 981 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ |
| 982 | { 5, { 0xb8 }, { 0xfe } }, |
| 983 | /* `movl imm32, %edx' */ |
| 984 | { 5, { 0xba }, { 0xff } }, |
| 985 | |
| 986 | /* Check for `mov imm32, r32'. Note that there is an alternative |
| 987 | encoding for `mov m32, %eax'. |
| 988 | |
| 989 | ??? Should we handle SIB adressing here? |
| 990 | ??? Should we handle 16-bit operand-sizes here? */ |
| 991 | |
| 992 | /* `movl m32, %eax' */ |
| 993 | { 5, { 0xa1 }, { 0xff } }, |
| 994 | /* `movl m32, %eax' and `mov; m32, %ecx' */ |
| 995 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, |
| 996 | /* `movl m32, %edx' */ |
| 997 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, |
| 998 | |
| 999 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. |
| 1000 | Because of the symmetry, there are actually two ways to encode |
| 1001 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and |
| 1002 | opcode bytes 0x31 and 0x33 for `xorl'. */ |
| 1003 | |
| 1004 | /* `subl %eax, %eax' */ |
| 1005 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, |
| 1006 | /* `subl %ecx, %ecx' */ |
| 1007 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, |
| 1008 | /* `subl %edx, %edx' */ |
| 1009 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, |
| 1010 | /* `xorl %eax, %eax' */ |
| 1011 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, |
| 1012 | /* `xorl %ecx, %ecx' */ |
| 1013 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, |
| 1014 | /* `xorl %edx, %edx' */ |
| 1015 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, |
| 1016 | { 0 } |
| 1017 | }; |
| 1018 | |
| 1019 | |
| 1020 | /* Check whether PC points to a no-op instruction. */ |
| 1021 | static CORE_ADDR |
| 1022 | i386_skip_noop (CORE_ADDR pc) |
| 1023 | { |
| 1024 | gdb_byte op; |
| 1025 | int check = 1; |
| 1026 | |
| 1027 | target_read_memory (pc, &op, 1); |
| 1028 | |
| 1029 | while (check) |
| 1030 | { |
| 1031 | check = 0; |
| 1032 | /* Ignore `nop' instruction. */ |
| 1033 | if (op == 0x90) |
| 1034 | { |
| 1035 | pc += 1; |
| 1036 | target_read_memory (pc, &op, 1); |
| 1037 | check = 1; |
| 1038 | } |
| 1039 | /* Ignore no-op instruction `mov %edi, %edi'. |
| 1040 | Microsoft system dlls often start with |
| 1041 | a `mov %edi,%edi' instruction. |
| 1042 | The 5 bytes before the function start are |
| 1043 | filled with `nop' instructions. |
| 1044 | This pattern can be used for hot-patching: |
| 1045 | The `mov %edi, %edi' instruction can be replaced by a |
| 1046 | near jump to the location of the 5 `nop' instructions |
| 1047 | which can be replaced by a 32-bit jump to anywhere |
| 1048 | in the 32-bit address space. */ |
| 1049 | |
| 1050 | else if (op == 0x8b) |
| 1051 | { |
| 1052 | target_read_memory (pc + 1, &op, 1); |
| 1053 | if (op == 0xff) |
| 1054 | { |
| 1055 | pc += 2; |
| 1056 | target_read_memory (pc, &op, 1); |
| 1057 | check = 1; |
| 1058 | } |
| 1059 | } |
| 1060 | } |
| 1061 | return pc; |
| 1062 | } |
| 1063 | |
| 1064 | /* Check whether PC points at a code that sets up a new stack frame. |
| 1065 | If so, it updates CACHE and returns the address of the first |
| 1066 | instruction after the sequence that sets up the frame or LIMIT, |
| 1067 | whichever is smaller. If we don't recognize the code, return PC. */ |
| 1068 | |
| 1069 | static CORE_ADDR |
| 1070 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
| 1071 | CORE_ADDR pc, CORE_ADDR limit, |
| 1072 | struct i386_frame_cache *cache) |
| 1073 | { |
| 1074 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1075 | struct i386_insn *insn; |
| 1076 | gdb_byte op; |
| 1077 | int skip = 0; |
| 1078 | |
| 1079 | if (limit <= pc) |
| 1080 | return limit; |
| 1081 | |
| 1082 | target_read_memory (pc, &op, 1); |
| 1083 | |
| 1084 | if (op == 0x55) /* pushl %ebp */ |
| 1085 | { |
| 1086 | /* Take into account that we've executed the `pushl %ebp' that |
| 1087 | starts this instruction sequence. */ |
| 1088 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
| 1089 | cache->sp_offset += 4; |
| 1090 | pc++; |
| 1091 | |
| 1092 | /* If that's all, return now. */ |
| 1093 | if (limit <= pc) |
| 1094 | return limit; |
| 1095 | |
| 1096 | /* Check for some special instructions that might be migrated by |
| 1097 | GCC into the prologue and skip them. At this point in the |
| 1098 | prologue, code should only touch the scratch registers %eax, |
| 1099 | %ecx and %edx, so while the number of posibilities is sheer, |
| 1100 | it is limited. |
| 1101 | |
| 1102 | Make sure we only skip these instructions if we later see the |
| 1103 | `movl %esp, %ebp' that actually sets up the frame. */ |
| 1104 | while (pc + skip < limit) |
| 1105 | { |
| 1106 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
| 1107 | if (insn == NULL) |
| 1108 | break; |
| 1109 | |
| 1110 | skip += insn->len; |
| 1111 | } |
| 1112 | |
| 1113 | /* If that's all, return now. */ |
| 1114 | if (limit <= pc + skip) |
| 1115 | return limit; |
| 1116 | |
| 1117 | target_read_memory (pc + skip, &op, 1); |
| 1118 | |
| 1119 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
| 1120 | switch (op) |
| 1121 | { |
| 1122 | case 0x8b: |
| 1123 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
| 1124 | != 0xec) |
| 1125 | return pc; |
| 1126 | break; |
| 1127 | case 0x89: |
| 1128 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
| 1129 | != 0xe5) |
| 1130 | return pc; |
| 1131 | break; |
| 1132 | default: |
| 1133 | return pc; |
| 1134 | } |
| 1135 | |
| 1136 | /* OK, we actually have a frame. We just don't know how large |
| 1137 | it is yet. Set its size to zero. We'll adjust it if |
| 1138 | necessary. We also now commit to skipping the special |
| 1139 | instructions mentioned before. */ |
| 1140 | cache->locals = 0; |
| 1141 | pc += (skip + 2); |
| 1142 | |
| 1143 | /* If that's all, return now. */ |
| 1144 | if (limit <= pc) |
| 1145 | return limit; |
| 1146 | |
| 1147 | /* Check for stack adjustment |
| 1148 | |
| 1149 | subl $XXX, %esp |
| 1150 | |
| 1151 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
| 1152 | reg, so we don't have to worry about a data16 prefix. */ |
| 1153 | target_read_memory (pc, &op, 1); |
| 1154 | if (op == 0x83) |
| 1155 | { |
| 1156 | /* `subl' with 8-bit immediate. */ |
| 1157 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
| 1158 | /* Some instruction starting with 0x83 other than `subl'. */ |
| 1159 | return pc; |
| 1160 | |
| 1161 | /* `subl' with signed 8-bit immediate (though it wouldn't |
| 1162 | make sense to be negative). */ |
| 1163 | cache->locals = read_memory_integer (pc + 2, 1, byte_order); |
| 1164 | return pc + 3; |
| 1165 | } |
| 1166 | else if (op == 0x81) |
| 1167 | { |
| 1168 | /* Maybe it is `subl' with a 32-bit immediate. */ |
| 1169 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
| 1170 | /* Some instruction starting with 0x81 other than `subl'. */ |
| 1171 | return pc; |
| 1172 | |
| 1173 | /* It is `subl' with a 32-bit immediate. */ |
| 1174 | cache->locals = read_memory_integer (pc + 2, 4, byte_order); |
| 1175 | return pc + 6; |
| 1176 | } |
| 1177 | else |
| 1178 | { |
| 1179 | /* Some instruction other than `subl'. */ |
| 1180 | return pc; |
| 1181 | } |
| 1182 | } |
| 1183 | else if (op == 0xc8) /* enter */ |
| 1184 | { |
| 1185 | cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order); |
| 1186 | return pc + 4; |
| 1187 | } |
| 1188 | |
| 1189 | return pc; |
| 1190 | } |
| 1191 | |
| 1192 | /* Check whether PC points at code that saves registers on the stack. |
| 1193 | If so, it updates CACHE and returns the address of the first |
| 1194 | instruction after the register saves or CURRENT_PC, whichever is |
| 1195 | smaller. Otherwise, return PC. */ |
| 1196 | |
| 1197 | static CORE_ADDR |
| 1198 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
| 1199 | struct i386_frame_cache *cache) |
| 1200 | { |
| 1201 | CORE_ADDR offset = 0; |
| 1202 | gdb_byte op; |
| 1203 | int i; |
| 1204 | |
| 1205 | if (cache->locals > 0) |
| 1206 | offset -= cache->locals; |
| 1207 | for (i = 0; i < 8 && pc < current_pc; i++) |
| 1208 | { |
| 1209 | target_read_memory (pc, &op, 1); |
| 1210 | if (op < 0x50 || op > 0x57) |
| 1211 | break; |
| 1212 | |
| 1213 | offset -= 4; |
| 1214 | cache->saved_regs[op - 0x50] = offset; |
| 1215 | cache->sp_offset += 4; |
| 1216 | pc++; |
| 1217 | } |
| 1218 | |
| 1219 | return pc; |
| 1220 | } |
| 1221 | |
| 1222 | /* Do a full analysis of the prologue at PC and update CACHE |
| 1223 | accordingly. Bail out early if CURRENT_PC is reached. Return the |
| 1224 | address where the analysis stopped. |
| 1225 | |
| 1226 | We handle these cases: |
| 1227 | |
| 1228 | The startup sequence can be at the start of the function, or the |
| 1229 | function can start with a branch to startup code at the end. |
| 1230 | |
| 1231 | %ebp can be set up with either the 'enter' instruction, or "pushl |
| 1232 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was |
| 1233 | once used in the System V compiler). |
| 1234 | |
| 1235 | Local space is allocated just below the saved %ebp by either the |
| 1236 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
| 1237 | 16-bit unsigned argument for space to allocate, and the 'addl' |
| 1238 | instruction could have either a signed byte, or 32-bit immediate. |
| 1239 | |
| 1240 | Next, the registers used by this function are pushed. With the |
| 1241 | System V compiler they will always be in the order: %edi, %esi, |
| 1242 | %ebx (and sometimes a harmless bug causes it to also save but not |
| 1243 | restore %eax); however, the code below is willing to see the pushes |
| 1244 | in any order, and will handle up to 8 of them. |
| 1245 | |
| 1246 | If the setup sequence is at the end of the function, then the next |
| 1247 | instruction will be a branch back to the start. */ |
| 1248 | |
| 1249 | static CORE_ADDR |
| 1250 | i386_analyze_prologue (struct gdbarch *gdbarch, |
| 1251 | CORE_ADDR pc, CORE_ADDR current_pc, |
| 1252 | struct i386_frame_cache *cache) |
| 1253 | { |
| 1254 | pc = i386_skip_noop (pc); |
| 1255 | pc = i386_follow_jump (gdbarch, pc); |
| 1256 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
| 1257 | pc = i386_skip_probe (pc); |
| 1258 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
| 1259 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
| 1260 | return i386_analyze_register_saves (pc, current_pc, cache); |
| 1261 | } |
| 1262 | |
| 1263 | /* Return PC of first real instruction. */ |
| 1264 | |
| 1265 | static CORE_ADDR |
| 1266 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
| 1267 | { |
| 1268 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1269 | |
| 1270 | static gdb_byte pic_pat[6] = |
| 1271 | { |
| 1272 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ |
| 1273 | 0x5b, /* popl %ebx */ |
| 1274 | }; |
| 1275 | struct i386_frame_cache cache; |
| 1276 | CORE_ADDR pc; |
| 1277 | gdb_byte op; |
| 1278 | int i; |
| 1279 | |
| 1280 | cache.locals = -1; |
| 1281 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
| 1282 | if (cache.locals < 0) |
| 1283 | return start_pc; |
| 1284 | |
| 1285 | /* Found valid frame setup. */ |
| 1286 | |
| 1287 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
| 1288 | to get the address of the global offset table (GOT) into register |
| 1289 | %ebx: |
| 1290 | |
| 1291 | call 0x0 |
| 1292 | popl %ebx |
| 1293 | movl %ebx,x(%ebp) (optional) |
| 1294 | addl y,%ebx |
| 1295 | |
| 1296 | This code is with the rest of the prologue (at the end of the |
| 1297 | function), so we have to skip it to get to the first real |
| 1298 | instruction at the start of the function. */ |
| 1299 | |
| 1300 | for (i = 0; i < 6; i++) |
| 1301 | { |
| 1302 | target_read_memory (pc + i, &op, 1); |
| 1303 | if (pic_pat[i] != op) |
| 1304 | break; |
| 1305 | } |
| 1306 | if (i == 6) |
| 1307 | { |
| 1308 | int delta = 6; |
| 1309 | |
| 1310 | target_read_memory (pc + delta, &op, 1); |
| 1311 | |
| 1312 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
| 1313 | { |
| 1314 | op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order); |
| 1315 | |
| 1316 | if (op == 0x5d) /* One byte offset from %ebp. */ |
| 1317 | delta += 3; |
| 1318 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
| 1319 | delta += 6; |
| 1320 | else /* Unexpected instruction. */ |
| 1321 | delta = 0; |
| 1322 | |
| 1323 | target_read_memory (pc + delta, &op, 1); |
| 1324 | } |
| 1325 | |
| 1326 | /* addl y,%ebx */ |
| 1327 | if (delta > 0 && op == 0x81 |
| 1328 | && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order) |
| 1329 | == 0xc3) |
| 1330 | { |
| 1331 | pc += delta + 6; |
| 1332 | } |
| 1333 | } |
| 1334 | |
| 1335 | /* If the function starts with a branch (to startup code at the end) |
| 1336 | the last instruction should bring us back to the first |
| 1337 | instruction of the real code. */ |
| 1338 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
| 1339 | pc = i386_follow_jump (gdbarch, pc); |
| 1340 | |
| 1341 | return pc; |
| 1342 | } |
| 1343 | |
| 1344 | /* Check that the code pointed to by PC corresponds to a call to |
| 1345 | __main, skip it if so. Return PC otherwise. */ |
| 1346 | |
| 1347 | CORE_ADDR |
| 1348 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 1349 | { |
| 1350 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1351 | gdb_byte op; |
| 1352 | |
| 1353 | target_read_memory (pc, &op, 1); |
| 1354 | if (op == 0xe8) |
| 1355 | { |
| 1356 | gdb_byte buf[4]; |
| 1357 | |
| 1358 | if (target_read_memory (pc + 1, buf, sizeof buf) == 0) |
| 1359 | { |
| 1360 | /* Make sure address is computed correctly as a 32bit |
| 1361 | integer even if CORE_ADDR is 64 bit wide. */ |
| 1362 | struct minimal_symbol *s; |
| 1363 | CORE_ADDR call_dest; |
| 1364 | |
| 1365 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
| 1366 | call_dest = call_dest & 0xffffffffU; |
| 1367 | s = lookup_minimal_symbol_by_pc (call_dest); |
| 1368 | if (s != NULL |
| 1369 | && SYMBOL_LINKAGE_NAME (s) != NULL |
| 1370 | && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0) |
| 1371 | pc += 5; |
| 1372 | } |
| 1373 | } |
| 1374 | |
| 1375 | return pc; |
| 1376 | } |
| 1377 | |
| 1378 | /* This function is 64-bit safe. */ |
| 1379 | |
| 1380 | static CORE_ADDR |
| 1381 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 1382 | { |
| 1383 | gdb_byte buf[8]; |
| 1384 | |
| 1385 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
| 1386 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
| 1387 | } |
| 1388 | \f |
| 1389 | |
| 1390 | /* Normal frames. */ |
| 1391 | |
| 1392 | static struct i386_frame_cache * |
| 1393 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) |
| 1394 | { |
| 1395 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 1396 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1397 | struct i386_frame_cache *cache; |
| 1398 | gdb_byte buf[4]; |
| 1399 | int i; |
| 1400 | |
| 1401 | if (*this_cache) |
| 1402 | return *this_cache; |
| 1403 | |
| 1404 | cache = i386_alloc_frame_cache (); |
| 1405 | *this_cache = cache; |
| 1406 | |
| 1407 | /* In principle, for normal frames, %ebp holds the frame pointer, |
| 1408 | which holds the base address for the current stack frame. |
| 1409 | However, for functions that don't need it, the frame pointer is |
| 1410 | optional. For these "frameless" functions the frame pointer is |
| 1411 | actually the frame pointer of the calling frame. Signal |
| 1412 | trampolines are just a special case of a "frameless" function. |
| 1413 | They (usually) share their frame pointer with the frame that was |
| 1414 | in progress when the signal occurred. */ |
| 1415 | |
| 1416 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
| 1417 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
| 1418 | if (cache->base == 0) |
| 1419 | return cache; |
| 1420 | |
| 1421 | /* For normal frames, %eip is stored at 4(%ebp). */ |
| 1422 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
| 1423 | |
| 1424 | cache->pc = get_frame_func (this_frame); |
| 1425 | if (cache->pc != 0) |
| 1426 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
| 1427 | cache); |
| 1428 | |
| 1429 | if (cache->saved_sp_reg != -1) |
| 1430 | { |
| 1431 | /* Saved stack pointer has been saved. */ |
| 1432 | get_frame_register (this_frame, cache->saved_sp_reg, buf); |
| 1433 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); |
| 1434 | } |
| 1435 | |
| 1436 | if (cache->locals < 0) |
| 1437 | { |
| 1438 | /* We didn't find a valid frame, which means that CACHE->base |
| 1439 | currently holds the frame pointer for our calling frame. If |
| 1440 | we're at the start of a function, or somewhere half-way its |
| 1441 | prologue, the function's frame probably hasn't been fully |
| 1442 | setup yet. Try to reconstruct the base address for the stack |
| 1443 | frame by looking at the stack pointer. For truly "frameless" |
| 1444 | functions this might work too. */ |
| 1445 | |
| 1446 | if (cache->saved_sp_reg != -1) |
| 1447 | { |
| 1448 | /* We're halfway aligning the stack. */ |
| 1449 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; |
| 1450 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; |
| 1451 | |
| 1452 | /* This will be added back below. */ |
| 1453 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; |
| 1454 | } |
| 1455 | else if (cache->pc != 0 |
| 1456 | || target_read_memory (get_frame_pc (this_frame), buf, 1)) |
| 1457 | { |
| 1458 | /* We're in a known function, but did not find a frame |
| 1459 | setup. Assume that the function does not use %ebp. |
| 1460 | Alternatively, we may have jumped to an invalid |
| 1461 | address; in that case there is definitely no new |
| 1462 | frame in %ebp. */ |
| 1463 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
| 1464 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
| 1465 | + cache->sp_offset; |
| 1466 | } |
| 1467 | else |
| 1468 | /* We're in an unknown function. We could not find the start |
| 1469 | of the function to analyze the prologue; our best option is |
| 1470 | to assume a typical frame layout with the caller's %ebp |
| 1471 | saved. */ |
| 1472 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
| 1473 | } |
| 1474 | |
| 1475 | /* Now that we have the base address for the stack frame we can |
| 1476 | calculate the value of %esp in the calling frame. */ |
| 1477 | if (cache->saved_sp == 0) |
| 1478 | cache->saved_sp = cache->base + 8; |
| 1479 | |
| 1480 | /* Adjust all the saved registers such that they contain addresses |
| 1481 | instead of offsets. */ |
| 1482 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) |
| 1483 | if (cache->saved_regs[i] != -1) |
| 1484 | cache->saved_regs[i] += cache->base; |
| 1485 | |
| 1486 | return cache; |
| 1487 | } |
| 1488 | |
| 1489 | static void |
| 1490 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
| 1491 | struct frame_id *this_id) |
| 1492 | { |
| 1493 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
| 1494 | |
| 1495 | /* This marks the outermost frame. */ |
| 1496 | if (cache->base == 0) |
| 1497 | return; |
| 1498 | |
| 1499 | /* See the end of i386_push_dummy_call. */ |
| 1500 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
| 1501 | } |
| 1502 | |
| 1503 | static struct value * |
| 1504 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, |
| 1505 | int regnum) |
| 1506 | { |
| 1507 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
| 1508 | |
| 1509 | gdb_assert (regnum >= 0); |
| 1510 | |
| 1511 | /* The System V ABI says that: |
| 1512 | |
| 1513 | "The flags register contains the system flags, such as the |
| 1514 | direction flag and the carry flag. The direction flag must be |
| 1515 | set to the forward (that is, zero) direction before entry and |
| 1516 | upon exit from a function. Other user flags have no specified |
| 1517 | role in the standard calling sequence and are not preserved." |
| 1518 | |
| 1519 | To guarantee the "upon exit" part of that statement we fake a |
| 1520 | saved flags register that has its direction flag cleared. |
| 1521 | |
| 1522 | Note that GCC doesn't seem to rely on the fact that the direction |
| 1523 | flag is cleared after a function return; it always explicitly |
| 1524 | clears the flag before operations where it matters. |
| 1525 | |
| 1526 | FIXME: kettenis/20030316: I'm not quite sure whether this is the |
| 1527 | right thing to do. The way we fake the flags register here makes |
| 1528 | it impossible to change it. */ |
| 1529 | |
| 1530 | if (regnum == I386_EFLAGS_REGNUM) |
| 1531 | { |
| 1532 | ULONGEST val; |
| 1533 | |
| 1534 | val = get_frame_register_unsigned (this_frame, regnum); |
| 1535 | val &= ~(1 << 10); |
| 1536 | return frame_unwind_got_constant (this_frame, regnum, val); |
| 1537 | } |
| 1538 | |
| 1539 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
| 1540 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
| 1541 | |
| 1542 | if (regnum == I386_ESP_REGNUM && cache->saved_sp) |
| 1543 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
| 1544 | |
| 1545 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
| 1546 | return frame_unwind_got_memory (this_frame, regnum, |
| 1547 | cache->saved_regs[regnum]); |
| 1548 | |
| 1549 | return frame_unwind_got_register (this_frame, regnum, regnum); |
| 1550 | } |
| 1551 | |
| 1552 | static const struct frame_unwind i386_frame_unwind = |
| 1553 | { |
| 1554 | NORMAL_FRAME, |
| 1555 | i386_frame_this_id, |
| 1556 | i386_frame_prev_register, |
| 1557 | NULL, |
| 1558 | default_frame_sniffer |
| 1559 | }; |
| 1560 | |
| 1561 | /* Normal frames, but in a function epilogue. */ |
| 1562 | |
| 1563 | /* The epilogue is defined here as the 'ret' instruction, which will |
| 1564 | follow any instruction such as 'leave' or 'pop %ebp' that destroys |
| 1565 | the function's stack frame. */ |
| 1566 | |
| 1567 | static int |
| 1568 | i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 1569 | { |
| 1570 | gdb_byte insn; |
| 1571 | |
| 1572 | if (target_read_memory (pc, &insn, 1)) |
| 1573 | return 0; /* Can't read memory at pc. */ |
| 1574 | |
| 1575 | if (insn != 0xc3) /* 'ret' instruction. */ |
| 1576 | return 0; |
| 1577 | |
| 1578 | return 1; |
| 1579 | } |
| 1580 | |
| 1581 | static int |
| 1582 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, |
| 1583 | struct frame_info *this_frame, |
| 1584 | void **this_prologue_cache) |
| 1585 | { |
| 1586 | if (frame_relative_level (this_frame) == 0) |
| 1587 | return i386_in_function_epilogue_p (get_frame_arch (this_frame), |
| 1588 | get_frame_pc (this_frame)); |
| 1589 | else |
| 1590 | return 0; |
| 1591 | } |
| 1592 | |
| 1593 | static struct i386_frame_cache * |
| 1594 | i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) |
| 1595 | { |
| 1596 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 1597 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1598 | struct i386_frame_cache *cache; |
| 1599 | gdb_byte buf[4]; |
| 1600 | |
| 1601 | if (*this_cache) |
| 1602 | return *this_cache; |
| 1603 | |
| 1604 | cache = i386_alloc_frame_cache (); |
| 1605 | *this_cache = cache; |
| 1606 | |
| 1607 | /* Cache base will be %esp plus cache->sp_offset (-4). */ |
| 1608 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
| 1609 | cache->base = extract_unsigned_integer (buf, 4, |
| 1610 | byte_order) + cache->sp_offset; |
| 1611 | |
| 1612 | /* Cache pc will be the frame func. */ |
| 1613 | cache->pc = get_frame_pc (this_frame); |
| 1614 | |
| 1615 | /* The saved %esp will be at cache->base plus 8. */ |
| 1616 | cache->saved_sp = cache->base + 8; |
| 1617 | |
| 1618 | /* The saved %eip will be at cache->base plus 4. */ |
| 1619 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; |
| 1620 | |
| 1621 | return cache; |
| 1622 | } |
| 1623 | |
| 1624 | static void |
| 1625 | i386_epilogue_frame_this_id (struct frame_info *this_frame, |
| 1626 | void **this_cache, |
| 1627 | struct frame_id *this_id) |
| 1628 | { |
| 1629 | struct i386_frame_cache *cache = i386_epilogue_frame_cache (this_frame, |
| 1630 | this_cache); |
| 1631 | |
| 1632 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
| 1633 | } |
| 1634 | |
| 1635 | static const struct frame_unwind i386_epilogue_frame_unwind = |
| 1636 | { |
| 1637 | NORMAL_FRAME, |
| 1638 | i386_epilogue_frame_this_id, |
| 1639 | i386_frame_prev_register, |
| 1640 | NULL, |
| 1641 | i386_epilogue_frame_sniffer |
| 1642 | }; |
| 1643 | \f |
| 1644 | |
| 1645 | /* Signal trampolines. */ |
| 1646 | |
| 1647 | static struct i386_frame_cache * |
| 1648 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
| 1649 | { |
| 1650 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 1651 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1652 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1653 | struct i386_frame_cache *cache; |
| 1654 | CORE_ADDR addr; |
| 1655 | gdb_byte buf[4]; |
| 1656 | |
| 1657 | if (*this_cache) |
| 1658 | return *this_cache; |
| 1659 | |
| 1660 | cache = i386_alloc_frame_cache (); |
| 1661 | |
| 1662 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
| 1663 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; |
| 1664 | |
| 1665 | addr = tdep->sigcontext_addr (this_frame); |
| 1666 | if (tdep->sc_reg_offset) |
| 1667 | { |
| 1668 | int i; |
| 1669 | |
| 1670 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); |
| 1671 | |
| 1672 | for (i = 0; i < tdep->sc_num_regs; i++) |
| 1673 | if (tdep->sc_reg_offset[i] != -1) |
| 1674 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; |
| 1675 | } |
| 1676 | else |
| 1677 | { |
| 1678 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; |
| 1679 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; |
| 1680 | } |
| 1681 | |
| 1682 | *this_cache = cache; |
| 1683 | return cache; |
| 1684 | } |
| 1685 | |
| 1686 | static void |
| 1687 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
| 1688 | struct frame_id *this_id) |
| 1689 | { |
| 1690 | struct i386_frame_cache *cache = |
| 1691 | i386_sigtramp_frame_cache (this_frame, this_cache); |
| 1692 | |
| 1693 | /* See the end of i386_push_dummy_call. */ |
| 1694 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); |
| 1695 | } |
| 1696 | |
| 1697 | static struct value * |
| 1698 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, |
| 1699 | void **this_cache, int regnum) |
| 1700 | { |
| 1701 | /* Make sure we've initialized the cache. */ |
| 1702 | i386_sigtramp_frame_cache (this_frame, this_cache); |
| 1703 | |
| 1704 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
| 1705 | } |
| 1706 | |
| 1707 | static int |
| 1708 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, |
| 1709 | struct frame_info *this_frame, |
| 1710 | void **this_prologue_cache) |
| 1711 | { |
| 1712 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
| 1713 | |
| 1714 | /* We shouldn't even bother if we don't have a sigcontext_addr |
| 1715 | handler. */ |
| 1716 | if (tdep->sigcontext_addr == NULL) |
| 1717 | return 0; |
| 1718 | |
| 1719 | if (tdep->sigtramp_p != NULL) |
| 1720 | { |
| 1721 | if (tdep->sigtramp_p (this_frame)) |
| 1722 | return 1; |
| 1723 | } |
| 1724 | |
| 1725 | if (tdep->sigtramp_start != 0) |
| 1726 | { |
| 1727 | CORE_ADDR pc = get_frame_pc (this_frame); |
| 1728 | |
| 1729 | gdb_assert (tdep->sigtramp_end != 0); |
| 1730 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) |
| 1731 | return 1; |
| 1732 | } |
| 1733 | |
| 1734 | return 0; |
| 1735 | } |
| 1736 | |
| 1737 | static const struct frame_unwind i386_sigtramp_frame_unwind = |
| 1738 | { |
| 1739 | SIGTRAMP_FRAME, |
| 1740 | i386_sigtramp_frame_this_id, |
| 1741 | i386_sigtramp_frame_prev_register, |
| 1742 | NULL, |
| 1743 | i386_sigtramp_frame_sniffer |
| 1744 | }; |
| 1745 | \f |
| 1746 | |
| 1747 | static CORE_ADDR |
| 1748 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
| 1749 | { |
| 1750 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
| 1751 | |
| 1752 | return cache->base; |
| 1753 | } |
| 1754 | |
| 1755 | static const struct frame_base i386_frame_base = |
| 1756 | { |
| 1757 | &i386_frame_unwind, |
| 1758 | i386_frame_base_address, |
| 1759 | i386_frame_base_address, |
| 1760 | i386_frame_base_address |
| 1761 | }; |
| 1762 | |
| 1763 | static struct frame_id |
| 1764 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 1765 | { |
| 1766 | CORE_ADDR fp; |
| 1767 | |
| 1768 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
| 1769 | |
| 1770 | /* See the end of i386_push_dummy_call. */ |
| 1771 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
| 1772 | } |
| 1773 | \f |
| 1774 | |
| 1775 | /* Figure out where the longjmp will land. Slurp the args out of the |
| 1776 | stack. We expect the first arg to be a pointer to the jmp_buf |
| 1777 | structure from which we extract the address that we will land at. |
| 1778 | This address is copied into PC. This routine returns non-zero on |
| 1779 | success. */ |
| 1780 | |
| 1781 | static int |
| 1782 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
| 1783 | { |
| 1784 | gdb_byte buf[4]; |
| 1785 | CORE_ADDR sp, jb_addr; |
| 1786 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 1787 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1788 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
| 1789 | |
| 1790 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
| 1791 | longjmp will land. */ |
| 1792 | if (jb_pc_offset == -1) |
| 1793 | return 0; |
| 1794 | |
| 1795 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
| 1796 | sp = extract_unsigned_integer (buf, 4, byte_order); |
| 1797 | if (target_read_memory (sp + 4, buf, 4)) |
| 1798 | return 0; |
| 1799 | |
| 1800 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
| 1801 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
| 1802 | return 0; |
| 1803 | |
| 1804 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
| 1805 | return 1; |
| 1806 | } |
| 1807 | \f |
| 1808 | |
| 1809 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
| 1810 | function argument. 16-byte vectors, _Decimal128 and structures or |
| 1811 | unions containing such types must be 16-byte-aligned; other |
| 1812 | arguments are 4-byte-aligned. */ |
| 1813 | |
| 1814 | static int |
| 1815 | i386_16_byte_align_p (struct type *type) |
| 1816 | { |
| 1817 | type = check_typedef (type); |
| 1818 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT |
| 1819 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) |
| 1820 | && TYPE_LENGTH (type) == 16) |
| 1821 | return 1; |
| 1822 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) |
| 1823 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); |
| 1824 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
| 1825 | || TYPE_CODE (type) == TYPE_CODE_UNION) |
| 1826 | { |
| 1827 | int i; |
| 1828 | for (i = 0; i < TYPE_NFIELDS (type); i++) |
| 1829 | { |
| 1830 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) |
| 1831 | return 1; |
| 1832 | } |
| 1833 | } |
| 1834 | return 0; |
| 1835 | } |
| 1836 | |
| 1837 | static CORE_ADDR |
| 1838 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 1839 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
| 1840 | struct value **args, CORE_ADDR sp, int struct_return, |
| 1841 | CORE_ADDR struct_addr) |
| 1842 | { |
| 1843 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1844 | gdb_byte buf[4]; |
| 1845 | int i; |
| 1846 | int write_pass; |
| 1847 | int args_space = 0; |
| 1848 | |
| 1849 | /* Determine the total space required for arguments and struct |
| 1850 | return address in a first pass (allowing for 16-byte-aligned |
| 1851 | arguments), then push arguments in a second pass. */ |
| 1852 | |
| 1853 | for (write_pass = 0; write_pass < 2; write_pass++) |
| 1854 | { |
| 1855 | int args_space_used = 0; |
| 1856 | int have_16_byte_aligned_arg = 0; |
| 1857 | |
| 1858 | if (struct_return) |
| 1859 | { |
| 1860 | if (write_pass) |
| 1861 | { |
| 1862 | /* Push value address. */ |
| 1863 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
| 1864 | write_memory (sp, buf, 4); |
| 1865 | args_space_used += 4; |
| 1866 | } |
| 1867 | else |
| 1868 | args_space += 4; |
| 1869 | } |
| 1870 | |
| 1871 | for (i = 0; i < nargs; i++) |
| 1872 | { |
| 1873 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); |
| 1874 | |
| 1875 | if (write_pass) |
| 1876 | { |
| 1877 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) |
| 1878 | args_space_used = align_up (args_space_used, 16); |
| 1879 | |
| 1880 | write_memory (sp + args_space_used, |
| 1881 | value_contents_all (args[i]), len); |
| 1882 | /* The System V ABI says that: |
| 1883 | |
| 1884 | "An argument's size is increased, if necessary, to make it a |
| 1885 | multiple of [32-bit] words. This may require tail padding, |
| 1886 | depending on the size of the argument." |
| 1887 | |
| 1888 | This makes sure the stack stays word-aligned. */ |
| 1889 | args_space_used += align_up (len, 4); |
| 1890 | } |
| 1891 | else |
| 1892 | { |
| 1893 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) |
| 1894 | { |
| 1895 | args_space = align_up (args_space, 16); |
| 1896 | have_16_byte_aligned_arg = 1; |
| 1897 | } |
| 1898 | args_space += align_up (len, 4); |
| 1899 | } |
| 1900 | } |
| 1901 | |
| 1902 | if (!write_pass) |
| 1903 | { |
| 1904 | if (have_16_byte_aligned_arg) |
| 1905 | args_space = align_up (args_space, 16); |
| 1906 | sp -= args_space; |
| 1907 | } |
| 1908 | } |
| 1909 | |
| 1910 | /* Store return address. */ |
| 1911 | sp -= 4; |
| 1912 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
| 1913 | write_memory (sp, buf, 4); |
| 1914 | |
| 1915 | /* Finally, update the stack pointer... */ |
| 1916 | store_unsigned_integer (buf, 4, byte_order, sp); |
| 1917 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); |
| 1918 | |
| 1919 | /* ...and fake a frame pointer. */ |
| 1920 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); |
| 1921 | |
| 1922 | /* MarkK wrote: This "+ 8" is all over the place: |
| 1923 | (i386_frame_this_id, i386_sigtramp_frame_this_id, |
| 1924 | i386_dummy_id). It's there, since all frame unwinders for |
| 1925 | a given target have to agree (within a certain margin) on the |
| 1926 | definition of the stack address of a frame. Otherwise frame id |
| 1927 | comparison might not work correctly. Since DWARF2/GCC uses the |
| 1928 | stack address *before* the function call as a frame's CFA. On |
| 1929 | the i386, when %ebp is used as a frame pointer, the offset |
| 1930 | between the contents %ebp and the CFA as defined by GCC. */ |
| 1931 | return sp + 8; |
| 1932 | } |
| 1933 | |
| 1934 | /* These registers are used for returning integers (and on some |
| 1935 | targets also for returning `struct' and `union' values when their |
| 1936 | size and alignment match an integer type). */ |
| 1937 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
| 1938 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ |
| 1939 | |
| 1940 | /* Read, for architecture GDBARCH, a function return value of TYPE |
| 1941 | from REGCACHE, and copy that into VALBUF. */ |
| 1942 | |
| 1943 | static void |
| 1944 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
| 1945 | struct regcache *regcache, gdb_byte *valbuf) |
| 1946 | { |
| 1947 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1948 | int len = TYPE_LENGTH (type); |
| 1949 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
| 1950 | |
| 1951 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
| 1952 | { |
| 1953 | if (tdep->st0_regnum < 0) |
| 1954 | { |
| 1955 | warning (_("Cannot find floating-point return value.")); |
| 1956 | memset (valbuf, 0, len); |
| 1957 | return; |
| 1958 | } |
| 1959 | |
| 1960 | /* Floating-point return values can be found in %st(0). Convert |
| 1961 | its contents to the desired type. This is probably not |
| 1962 | exactly how it would happen on the target itself, but it is |
| 1963 | the best we can do. */ |
| 1964 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
| 1965 | convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type); |
| 1966 | } |
| 1967 | else |
| 1968 | { |
| 1969 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
| 1970 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); |
| 1971 | |
| 1972 | if (len <= low_size) |
| 1973 | { |
| 1974 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
| 1975 | memcpy (valbuf, buf, len); |
| 1976 | } |
| 1977 | else if (len <= (low_size + high_size)) |
| 1978 | { |
| 1979 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
| 1980 | memcpy (valbuf, buf, low_size); |
| 1981 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
| 1982 | memcpy (valbuf + low_size, buf, len - low_size); |
| 1983 | } |
| 1984 | else |
| 1985 | internal_error (__FILE__, __LINE__, |
| 1986 | _("Cannot extract return value of %d bytes long."), len); |
| 1987 | } |
| 1988 | } |
| 1989 | |
| 1990 | /* Write, for architecture GDBARCH, a function return value of TYPE |
| 1991 | from VALBUF into REGCACHE. */ |
| 1992 | |
| 1993 | static void |
| 1994 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
| 1995 | struct regcache *regcache, const gdb_byte *valbuf) |
| 1996 | { |
| 1997 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1998 | int len = TYPE_LENGTH (type); |
| 1999 | |
| 2000 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
| 2001 | { |
| 2002 | ULONGEST fstat; |
| 2003 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
| 2004 | |
| 2005 | if (tdep->st0_regnum < 0) |
| 2006 | { |
| 2007 | warning (_("Cannot set floating-point return value.")); |
| 2008 | return; |
| 2009 | } |
| 2010 | |
| 2011 | /* Returning floating-point values is a bit tricky. Apart from |
| 2012 | storing the return value in %st(0), we have to simulate the |
| 2013 | state of the FPU at function return point. */ |
| 2014 | |
| 2015 | /* Convert the value found in VALBUF to the extended |
| 2016 | floating-point format used by the FPU. This is probably |
| 2017 | not exactly how it would happen on the target itself, but |
| 2018 | it is the best we can do. */ |
| 2019 | convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch)); |
| 2020 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
| 2021 | |
| 2022 | /* Set the top of the floating-point register stack to 7. The |
| 2023 | actual value doesn't really matter, but 7 is what a normal |
| 2024 | function return would end up with if the program started out |
| 2025 | with a freshly initialized FPU. */ |
| 2026 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
| 2027 | fstat |= (7 << 11); |
| 2028 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
| 2029 | |
| 2030 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
| 2031 | the floating-point register stack to 7, the appropriate value |
| 2032 | for the tag word is 0x3fff. */ |
| 2033 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
| 2034 | } |
| 2035 | else |
| 2036 | { |
| 2037 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
| 2038 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); |
| 2039 | |
| 2040 | if (len <= low_size) |
| 2041 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
| 2042 | else if (len <= (low_size + high_size)) |
| 2043 | { |
| 2044 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
| 2045 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, |
| 2046 | len - low_size, valbuf + low_size); |
| 2047 | } |
| 2048 | else |
| 2049 | internal_error (__FILE__, __LINE__, |
| 2050 | _("Cannot store return value of %d bytes long."), len); |
| 2051 | } |
| 2052 | } |
| 2053 | \f |
| 2054 | |
| 2055 | /* This is the variable that is set with "set struct-convention", and |
| 2056 | its legitimate values. */ |
| 2057 | static const char default_struct_convention[] = "default"; |
| 2058 | static const char pcc_struct_convention[] = "pcc"; |
| 2059 | static const char reg_struct_convention[] = "reg"; |
| 2060 | static const char *valid_conventions[] = |
| 2061 | { |
| 2062 | default_struct_convention, |
| 2063 | pcc_struct_convention, |
| 2064 | reg_struct_convention, |
| 2065 | NULL |
| 2066 | }; |
| 2067 | static const char *struct_convention = default_struct_convention; |
| 2068 | |
| 2069 | /* Return non-zero if TYPE, which is assumed to be a structure, |
| 2070 | a union type, or an array type, should be returned in registers |
| 2071 | for architecture GDBARCH. */ |
| 2072 | |
| 2073 | static int |
| 2074 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
| 2075 | { |
| 2076 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2077 | enum type_code code = TYPE_CODE (type); |
| 2078 | int len = TYPE_LENGTH (type); |
| 2079 | |
| 2080 | gdb_assert (code == TYPE_CODE_STRUCT |
| 2081 | || code == TYPE_CODE_UNION |
| 2082 | || code == TYPE_CODE_ARRAY); |
| 2083 | |
| 2084 | if (struct_convention == pcc_struct_convention |
| 2085 | || (struct_convention == default_struct_convention |
| 2086 | && tdep->struct_return == pcc_struct_return)) |
| 2087 | return 0; |
| 2088 | |
| 2089 | /* Structures consisting of a single `float', `double' or 'long |
| 2090 | double' member are returned in %st(0). */ |
| 2091 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
| 2092 | { |
| 2093 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); |
| 2094 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
| 2095 | return (len == 4 || len == 8 || len == 12); |
| 2096 | } |
| 2097 | |
| 2098 | return (len == 1 || len == 2 || len == 4 || len == 8); |
| 2099 | } |
| 2100 | |
| 2101 | /* Determine, for architecture GDBARCH, how a return value of TYPE |
| 2102 | should be returned. If it is supposed to be returned in registers, |
| 2103 | and READBUF is non-zero, read the appropriate value from REGCACHE, |
| 2104 | and copy it into READBUF. If WRITEBUF is non-zero, write the value |
| 2105 | from WRITEBUF into REGCACHE. */ |
| 2106 | |
| 2107 | static enum return_value_convention |
| 2108 | i386_return_value (struct gdbarch *gdbarch, struct type *func_type, |
| 2109 | struct type *type, struct regcache *regcache, |
| 2110 | gdb_byte *readbuf, const gdb_byte *writebuf) |
| 2111 | { |
| 2112 | enum type_code code = TYPE_CODE (type); |
| 2113 | |
| 2114 | if (((code == TYPE_CODE_STRUCT |
| 2115 | || code == TYPE_CODE_UNION |
| 2116 | || code == TYPE_CODE_ARRAY) |
| 2117 | && !i386_reg_struct_return_p (gdbarch, type)) |
| 2118 | /* 128-bit decimal float uses the struct return convention. */ |
| 2119 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) |
| 2120 | { |
| 2121 | /* The System V ABI says that: |
| 2122 | |
| 2123 | "A function that returns a structure or union also sets %eax |
| 2124 | to the value of the original address of the caller's area |
| 2125 | before it returns. Thus when the caller receives control |
| 2126 | again, the address of the returned object resides in register |
| 2127 | %eax and can be used to access the object." |
| 2128 | |
| 2129 | So the ABI guarantees that we can always find the return |
| 2130 | value just after the function has returned. */ |
| 2131 | |
| 2132 | /* Note that the ABI doesn't mention functions returning arrays, |
| 2133 | which is something possible in certain languages such as Ada. |
| 2134 | In this case, the value is returned as if it was wrapped in |
| 2135 | a record, so the convention applied to records also applies |
| 2136 | to arrays. */ |
| 2137 | |
| 2138 | if (readbuf) |
| 2139 | { |
| 2140 | ULONGEST addr; |
| 2141 | |
| 2142 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); |
| 2143 | read_memory (addr, readbuf, TYPE_LENGTH (type)); |
| 2144 | } |
| 2145 | |
| 2146 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; |
| 2147 | } |
| 2148 | |
| 2149 | /* This special case is for structures consisting of a single |
| 2150 | `float', `double' or 'long double' member. These structures are |
| 2151 | returned in %st(0). For these structures, we call ourselves |
| 2152 | recursively, changing TYPE into the type of the first member of |
| 2153 | the structure. Since that should work for all structures that |
| 2154 | have only one member, we don't bother to check the member's type |
| 2155 | here. */ |
| 2156 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
| 2157 | { |
| 2158 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); |
| 2159 | return i386_return_value (gdbarch, func_type, type, regcache, |
| 2160 | readbuf, writebuf); |
| 2161 | } |
| 2162 | |
| 2163 | if (readbuf) |
| 2164 | i386_extract_return_value (gdbarch, type, regcache, readbuf); |
| 2165 | if (writebuf) |
| 2166 | i386_store_return_value (gdbarch, type, regcache, writebuf); |
| 2167 | |
| 2168 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 2169 | } |
| 2170 | \f |
| 2171 | |
| 2172 | struct type * |
| 2173 | i387_ext_type (struct gdbarch *gdbarch) |
| 2174 | { |
| 2175 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2176 | |
| 2177 | if (!tdep->i387_ext_type) |
| 2178 | { |
| 2179 | tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); |
| 2180 | gdb_assert (tdep->i387_ext_type != NULL); |
| 2181 | } |
| 2182 | |
| 2183 | return tdep->i387_ext_type; |
| 2184 | } |
| 2185 | |
| 2186 | /* Construct vector type for MMX registers. */ |
| 2187 | static struct type * |
| 2188 | i386_mmx_type (struct gdbarch *gdbarch) |
| 2189 | { |
| 2190 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2191 | |
| 2192 | if (!tdep->i386_mmx_type) |
| 2193 | { |
| 2194 | const struct builtin_type *bt = builtin_type (gdbarch); |
| 2195 | |
| 2196 | /* The type we're building is this: */ |
| 2197 | #if 0 |
| 2198 | union __gdb_builtin_type_vec64i |
| 2199 | { |
| 2200 | int64_t uint64; |
| 2201 | int32_t v2_int32[2]; |
| 2202 | int16_t v4_int16[4]; |
| 2203 | int8_t v8_int8[8]; |
| 2204 | }; |
| 2205 | #endif |
| 2206 | |
| 2207 | struct type *t; |
| 2208 | |
| 2209 | t = arch_composite_type (gdbarch, |
| 2210 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); |
| 2211 | |
| 2212 | append_composite_type_field (t, "uint64", bt->builtin_int64); |
| 2213 | append_composite_type_field (t, "v2_int32", |
| 2214 | init_vector_type (bt->builtin_int32, 2)); |
| 2215 | append_composite_type_field (t, "v4_int16", |
| 2216 | init_vector_type (bt->builtin_int16, 4)); |
| 2217 | append_composite_type_field (t, "v8_int8", |
| 2218 | init_vector_type (bt->builtin_int8, 8)); |
| 2219 | |
| 2220 | TYPE_VECTOR (t) = 1; |
| 2221 | TYPE_NAME (t) = "builtin_type_vec64i"; |
| 2222 | tdep->i386_mmx_type = t; |
| 2223 | } |
| 2224 | |
| 2225 | return tdep->i386_mmx_type; |
| 2226 | } |
| 2227 | |
| 2228 | /* Return the GDB type object for the "standard" data type of data in |
| 2229 | register REGNUM. */ |
| 2230 | |
| 2231 | static struct type * |
| 2232 | i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
| 2233 | { |
| 2234 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
| 2235 | return i386_mmx_type (gdbarch); |
| 2236 | else |
| 2237 | { |
| 2238 | const struct builtin_type *bt = builtin_type (gdbarch); |
| 2239 | if (i386_byte_regnum_p (gdbarch, regnum)) |
| 2240 | return bt->builtin_int8; |
| 2241 | else if (i386_word_regnum_p (gdbarch, regnum)) |
| 2242 | return bt->builtin_int16; |
| 2243 | else if (i386_dword_regnum_p (gdbarch, regnum)) |
| 2244 | return bt->builtin_int32; |
| 2245 | } |
| 2246 | |
| 2247 | internal_error (__FILE__, __LINE__, _("invalid regnum")); |
| 2248 | } |
| 2249 | |
| 2250 | /* Map a cooked register onto a raw register or memory. For the i386, |
| 2251 | the MMX registers need to be mapped onto floating point registers. */ |
| 2252 | |
| 2253 | static int |
| 2254 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
| 2255 | { |
| 2256 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
| 2257 | int mmxreg, fpreg; |
| 2258 | ULONGEST fstat; |
| 2259 | int tos; |
| 2260 | |
| 2261 | mmxreg = regnum - tdep->mm0_regnum; |
| 2262 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
| 2263 | tos = (fstat >> 11) & 0x7; |
| 2264 | fpreg = (mmxreg + tos) % 8; |
| 2265 | |
| 2266 | return (I387_ST0_REGNUM (tdep) + fpreg); |
| 2267 | } |
| 2268 | |
| 2269 | void |
| 2270 | i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
| 2271 | int regnum, gdb_byte *buf) |
| 2272 | { |
| 2273 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
| 2274 | |
| 2275 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
| 2276 | { |
| 2277 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
| 2278 | |
| 2279 | /* Extract (always little endian). */ |
| 2280 | regcache_raw_read (regcache, fpnum, raw_buf); |
| 2281 | memcpy (buf, raw_buf, register_size (gdbarch, regnum)); |
| 2282 | } |
| 2283 | else |
| 2284 | { |
| 2285 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2286 | |
| 2287 | if (i386_word_regnum_p (gdbarch, regnum)) |
| 2288 | { |
| 2289 | int gpnum = regnum - tdep->ax_regnum; |
| 2290 | |
| 2291 | /* Extract (always little endian). */ |
| 2292 | regcache_raw_read (regcache, gpnum, raw_buf); |
| 2293 | memcpy (buf, raw_buf, 2); |
| 2294 | } |
| 2295 | else if (i386_byte_regnum_p (gdbarch, regnum)) |
| 2296 | { |
| 2297 | /* Check byte pseudo registers last since this function will |
| 2298 | be called from amd64_pseudo_register_read, which handles |
| 2299 | byte pseudo registers differently. */ |
| 2300 | int gpnum = regnum - tdep->al_regnum; |
| 2301 | |
| 2302 | /* Extract (always little endian). We read both lower and |
| 2303 | upper registers. */ |
| 2304 | regcache_raw_read (regcache, gpnum % 4, raw_buf); |
| 2305 | if (gpnum >= 4) |
| 2306 | memcpy (buf, raw_buf + 1, 1); |
| 2307 | else |
| 2308 | memcpy (buf, raw_buf, 1); |
| 2309 | } |
| 2310 | else |
| 2311 | internal_error (__FILE__, __LINE__, _("invalid regnum")); |
| 2312 | } |
| 2313 | } |
| 2314 | |
| 2315 | void |
| 2316 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
| 2317 | int regnum, const gdb_byte *buf) |
| 2318 | { |
| 2319 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
| 2320 | |
| 2321 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
| 2322 | { |
| 2323 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
| 2324 | |
| 2325 | /* Read ... */ |
| 2326 | regcache_raw_read (regcache, fpnum, raw_buf); |
| 2327 | /* ... Modify ... (always little endian). */ |
| 2328 | memcpy (raw_buf, buf, register_size (gdbarch, regnum)); |
| 2329 | /* ... Write. */ |
| 2330 | regcache_raw_write (regcache, fpnum, raw_buf); |
| 2331 | } |
| 2332 | else |
| 2333 | { |
| 2334 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2335 | |
| 2336 | if (i386_word_regnum_p (gdbarch, regnum)) |
| 2337 | { |
| 2338 | int gpnum = regnum - tdep->ax_regnum; |
| 2339 | |
| 2340 | /* Read ... */ |
| 2341 | regcache_raw_read (regcache, gpnum, raw_buf); |
| 2342 | /* ... Modify ... (always little endian). */ |
| 2343 | memcpy (raw_buf, buf, 2); |
| 2344 | /* ... Write. */ |
| 2345 | regcache_raw_write (regcache, gpnum, raw_buf); |
| 2346 | } |
| 2347 | else if (i386_byte_regnum_p (gdbarch, regnum)) |
| 2348 | { |
| 2349 | /* Check byte pseudo registers last since this function will |
| 2350 | be called from amd64_pseudo_register_read, which handles |
| 2351 | byte pseudo registers differently. */ |
| 2352 | int gpnum = regnum - tdep->al_regnum; |
| 2353 | |
| 2354 | /* Read ... We read both lower and upper registers. */ |
| 2355 | regcache_raw_read (regcache, gpnum % 4, raw_buf); |
| 2356 | /* ... Modify ... (always little endian). */ |
| 2357 | if (gpnum >= 4) |
| 2358 | memcpy (raw_buf + 1, buf, 1); |
| 2359 | else |
| 2360 | memcpy (raw_buf, buf, 1); |
| 2361 | /* ... Write. */ |
| 2362 | regcache_raw_write (regcache, gpnum % 4, raw_buf); |
| 2363 | } |
| 2364 | else |
| 2365 | internal_error (__FILE__, __LINE__, _("invalid regnum")); |
| 2366 | } |
| 2367 | } |
| 2368 | \f |
| 2369 | |
| 2370 | /* Return the register number of the register allocated by GCC after |
| 2371 | REGNUM, or -1 if there is no such register. */ |
| 2372 | |
| 2373 | static int |
| 2374 | i386_next_regnum (int regnum) |
| 2375 | { |
| 2376 | /* GCC allocates the registers in the order: |
| 2377 | |
| 2378 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... |
| 2379 | |
| 2380 | Since storing a variable in %esp doesn't make any sense we return |
| 2381 | -1 for %ebp and for %esp itself. */ |
| 2382 | static int next_regnum[] = |
| 2383 | { |
| 2384 | I386_EDX_REGNUM, /* Slot for %eax. */ |
| 2385 | I386_EBX_REGNUM, /* Slot for %ecx. */ |
| 2386 | I386_ECX_REGNUM, /* Slot for %edx. */ |
| 2387 | I386_ESI_REGNUM, /* Slot for %ebx. */ |
| 2388 | -1, -1, /* Slots for %esp and %ebp. */ |
| 2389 | I386_EDI_REGNUM, /* Slot for %esi. */ |
| 2390 | I386_EBP_REGNUM /* Slot for %edi. */ |
| 2391 | }; |
| 2392 | |
| 2393 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
| 2394 | return next_regnum[regnum]; |
| 2395 | |
| 2396 | return -1; |
| 2397 | } |
| 2398 | |
| 2399 | /* Return nonzero if a value of type TYPE stored in register REGNUM |
| 2400 | needs any special handling. */ |
| 2401 | |
| 2402 | static int |
| 2403 | i386_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type) |
| 2404 | { |
| 2405 | int len = TYPE_LENGTH (type); |
| 2406 | |
| 2407 | /* Values may be spread across multiple registers. Most debugging |
| 2408 | formats aren't expressive enough to specify the locations, so |
| 2409 | some heuristics is involved. Right now we only handle types that |
| 2410 | have a length that is a multiple of the word size, since GCC |
| 2411 | doesn't seem to put any other types into registers. */ |
| 2412 | if (len > 4 && len % 4 == 0) |
| 2413 | { |
| 2414 | int last_regnum = regnum; |
| 2415 | |
| 2416 | while (len > 4) |
| 2417 | { |
| 2418 | last_regnum = i386_next_regnum (last_regnum); |
| 2419 | len -= 4; |
| 2420 | } |
| 2421 | |
| 2422 | if (last_regnum != -1) |
| 2423 | return 1; |
| 2424 | } |
| 2425 | |
| 2426 | return i387_convert_register_p (gdbarch, regnum, type); |
| 2427 | } |
| 2428 | |
| 2429 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
| 2430 | return its contents in TO. */ |
| 2431 | |
| 2432 | static void |
| 2433 | i386_register_to_value (struct frame_info *frame, int regnum, |
| 2434 | struct type *type, gdb_byte *to) |
| 2435 | { |
| 2436 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 2437 | int len = TYPE_LENGTH (type); |
| 2438 | |
| 2439 | /* FIXME: kettenis/20030609: What should we do if REGNUM isn't |
| 2440 | available in FRAME (i.e. if it wasn't saved)? */ |
| 2441 | |
| 2442 | if (i386_fp_regnum_p (gdbarch, regnum)) |
| 2443 | { |
| 2444 | i387_register_to_value (frame, regnum, type, to); |
| 2445 | return; |
| 2446 | } |
| 2447 | |
| 2448 | /* Read a value spread across multiple registers. */ |
| 2449 | |
| 2450 | gdb_assert (len > 4 && len % 4 == 0); |
| 2451 | |
| 2452 | while (len > 0) |
| 2453 | { |
| 2454 | gdb_assert (regnum != -1); |
| 2455 | gdb_assert (register_size (gdbarch, regnum) == 4); |
| 2456 | |
| 2457 | get_frame_register (frame, regnum, to); |
| 2458 | regnum = i386_next_regnum (regnum); |
| 2459 | len -= 4; |
| 2460 | to += 4; |
| 2461 | } |
| 2462 | } |
| 2463 | |
| 2464 | /* Write the contents FROM of a value of type TYPE into register |
| 2465 | REGNUM in frame FRAME. */ |
| 2466 | |
| 2467 | static void |
| 2468 | i386_value_to_register (struct frame_info *frame, int regnum, |
| 2469 | struct type *type, const gdb_byte *from) |
| 2470 | { |
| 2471 | int len = TYPE_LENGTH (type); |
| 2472 | |
| 2473 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
| 2474 | { |
| 2475 | i387_value_to_register (frame, regnum, type, from); |
| 2476 | return; |
| 2477 | } |
| 2478 | |
| 2479 | /* Write a value spread across multiple registers. */ |
| 2480 | |
| 2481 | gdb_assert (len > 4 && len % 4 == 0); |
| 2482 | |
| 2483 | while (len > 0) |
| 2484 | { |
| 2485 | gdb_assert (regnum != -1); |
| 2486 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
| 2487 | |
| 2488 | put_frame_register (frame, regnum, from); |
| 2489 | regnum = i386_next_regnum (regnum); |
| 2490 | len -= 4; |
| 2491 | from += 4; |
| 2492 | } |
| 2493 | } |
| 2494 | \f |
| 2495 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
| 2496 | in the general-purpose register set REGSET to register cache |
| 2497 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ |
| 2498 | |
| 2499 | void |
| 2500 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
| 2501 | int regnum, const void *gregs, size_t len) |
| 2502 | { |
| 2503 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
| 2504 | const gdb_byte *regs = gregs; |
| 2505 | int i; |
| 2506 | |
| 2507 | gdb_assert (len == tdep->sizeof_gregset); |
| 2508 | |
| 2509 | for (i = 0; i < tdep->gregset_num_regs; i++) |
| 2510 | { |
| 2511 | if ((regnum == i || regnum == -1) |
| 2512 | && tdep->gregset_reg_offset[i] != -1) |
| 2513 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); |
| 2514 | } |
| 2515 | } |
| 2516 | |
| 2517 | /* Collect register REGNUM from the register cache REGCACHE and store |
| 2518 | it in the buffer specified by GREGS and LEN as described by the |
| 2519 | general-purpose register set REGSET. If REGNUM is -1, do this for |
| 2520 | all registers in REGSET. */ |
| 2521 | |
| 2522 | void |
| 2523 | i386_collect_gregset (const struct regset *regset, |
| 2524 | const struct regcache *regcache, |
| 2525 | int regnum, void *gregs, size_t len) |
| 2526 | { |
| 2527 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
| 2528 | gdb_byte *regs = gregs; |
| 2529 | int i; |
| 2530 | |
| 2531 | gdb_assert (len == tdep->sizeof_gregset); |
| 2532 | |
| 2533 | for (i = 0; i < tdep->gregset_num_regs; i++) |
| 2534 | { |
| 2535 | if ((regnum == i || regnum == -1) |
| 2536 | && tdep->gregset_reg_offset[i] != -1) |
| 2537 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); |
| 2538 | } |
| 2539 | } |
| 2540 | |
| 2541 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN |
| 2542 | in the floating-point register set REGSET to register cache |
| 2543 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ |
| 2544 | |
| 2545 | static void |
| 2546 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, |
| 2547 | int regnum, const void *fpregs, size_t len) |
| 2548 | { |
| 2549 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
| 2550 | |
| 2551 | if (len == I387_SIZEOF_FXSAVE) |
| 2552 | { |
| 2553 | i387_supply_fxsave (regcache, regnum, fpregs); |
| 2554 | return; |
| 2555 | } |
| 2556 | |
| 2557 | gdb_assert (len == tdep->sizeof_fpregset); |
| 2558 | i387_supply_fsave (regcache, regnum, fpregs); |
| 2559 | } |
| 2560 | |
| 2561 | /* Collect register REGNUM from the register cache REGCACHE and store |
| 2562 | it in the buffer specified by FPREGS and LEN as described by the |
| 2563 | floating-point register set REGSET. If REGNUM is -1, do this for |
| 2564 | all registers in REGSET. */ |
| 2565 | |
| 2566 | static void |
| 2567 | i386_collect_fpregset (const struct regset *regset, |
| 2568 | const struct regcache *regcache, |
| 2569 | int regnum, void *fpregs, size_t len) |
| 2570 | { |
| 2571 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
| 2572 | |
| 2573 | if (len == I387_SIZEOF_FXSAVE) |
| 2574 | { |
| 2575 | i387_collect_fxsave (regcache, regnum, fpregs); |
| 2576 | return; |
| 2577 | } |
| 2578 | |
| 2579 | gdb_assert (len == tdep->sizeof_fpregset); |
| 2580 | i387_collect_fsave (regcache, regnum, fpregs); |
| 2581 | } |
| 2582 | |
| 2583 | /* Return the appropriate register set for the core section identified |
| 2584 | by SECT_NAME and SECT_SIZE. */ |
| 2585 | |
| 2586 | const struct regset * |
| 2587 | i386_regset_from_core_section (struct gdbarch *gdbarch, |
| 2588 | const char *sect_name, size_t sect_size) |
| 2589 | { |
| 2590 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2591 | |
| 2592 | if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) |
| 2593 | { |
| 2594 | if (tdep->gregset == NULL) |
| 2595 | tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset, |
| 2596 | i386_collect_gregset); |
| 2597 | return tdep->gregset; |
| 2598 | } |
| 2599 | |
| 2600 | if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) |
| 2601 | || (strcmp (sect_name, ".reg-xfp") == 0 |
| 2602 | && sect_size == I387_SIZEOF_FXSAVE)) |
| 2603 | { |
| 2604 | if (tdep->fpregset == NULL) |
| 2605 | tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset, |
| 2606 | i386_collect_fpregset); |
| 2607 | return tdep->fpregset; |
| 2608 | } |
| 2609 | |
| 2610 | return NULL; |
| 2611 | } |
| 2612 | \f |
| 2613 | |
| 2614 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
| 2615 | |
| 2616 | CORE_ADDR |
| 2617 | i386_pe_skip_trampoline_code (struct frame_info *frame, |
| 2618 | CORE_ADDR pc, char *name) |
| 2619 | { |
| 2620 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 2621 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2622 | |
| 2623 | /* jmp *(dest) */ |
| 2624 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) |
| 2625 | { |
| 2626 | unsigned long indirect = |
| 2627 | read_memory_unsigned_integer (pc + 2, 4, byte_order); |
| 2628 | struct minimal_symbol *indsym = |
| 2629 | indirect ? lookup_minimal_symbol_by_pc (indirect) : 0; |
| 2630 | char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0; |
| 2631 | |
| 2632 | if (symname) |
| 2633 | { |
| 2634 | if (strncmp (symname, "__imp_", 6) == 0 |
| 2635 | || strncmp (symname, "_imp_", 5) == 0) |
| 2636 | return name ? 1 : |
| 2637 | read_memory_unsigned_integer (indirect, 4, byte_order); |
| 2638 | } |
| 2639 | } |
| 2640 | return 0; /* Not a trampoline. */ |
| 2641 | } |
| 2642 | \f |
| 2643 | |
| 2644 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
| 2645 | routine. */ |
| 2646 | |
| 2647 | int |
| 2648 | i386_sigtramp_p (struct frame_info *this_frame) |
| 2649 | { |
| 2650 | CORE_ADDR pc = get_frame_pc (this_frame); |
| 2651 | char *name; |
| 2652 | |
| 2653 | find_pc_partial_function (pc, &name, NULL, NULL); |
| 2654 | return (name && strcmp ("_sigtramp", name) == 0); |
| 2655 | } |
| 2656 | \f |
| 2657 | |
| 2658 | /* We have two flavours of disassembly. The machinery on this page |
| 2659 | deals with switching between those. */ |
| 2660 | |
| 2661 | static int |
| 2662 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
| 2663 | { |
| 2664 | gdb_assert (disassembly_flavor == att_flavor |
| 2665 | || disassembly_flavor == intel_flavor); |
| 2666 | |
| 2667 | /* FIXME: kettenis/20020915: Until disassembler_options is properly |
| 2668 | constified, cast to prevent a compiler warning. */ |
| 2669 | info->disassembler_options = (char *) disassembly_flavor; |
| 2670 | |
| 2671 | return print_insn_i386 (pc, info); |
| 2672 | } |
| 2673 | \f |
| 2674 | |
| 2675 | /* There are a few i386 architecture variants that differ only |
| 2676 | slightly from the generic i386 target. For now, we don't give them |
| 2677 | their own source file, but include them here. As a consequence, |
| 2678 | they'll always be included. */ |
| 2679 | |
| 2680 | /* System V Release 4 (SVR4). */ |
| 2681 | |
| 2682 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
| 2683 | routine. */ |
| 2684 | |
| 2685 | static int |
| 2686 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
| 2687 | { |
| 2688 | CORE_ADDR pc = get_frame_pc (this_frame); |
| 2689 | char *name; |
| 2690 | |
| 2691 | /* UnixWare uses _sigacthandler. The origin of the other symbols is |
| 2692 | currently unknown. */ |
| 2693 | find_pc_partial_function (pc, &name, NULL, NULL); |
| 2694 | return (name && (strcmp ("_sigreturn", name) == 0 |
| 2695 | || strcmp ("_sigacthandler", name) == 0 |
| 2696 | || strcmp ("sigvechandler", name) == 0)); |
| 2697 | } |
| 2698 | |
| 2699 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
| 2700 | address of the associated sigcontext (ucontext) structure. */ |
| 2701 | |
| 2702 | static CORE_ADDR |
| 2703 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
| 2704 | { |
| 2705 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 2706 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2707 | gdb_byte buf[4]; |
| 2708 | CORE_ADDR sp; |
| 2709 | |
| 2710 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
| 2711 | sp = extract_unsigned_integer (buf, 4, byte_order); |
| 2712 | |
| 2713 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
| 2714 | } |
| 2715 | \f |
| 2716 | |
| 2717 | /* Generic ELF. */ |
| 2718 | |
| 2719 | void |
| 2720 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
| 2721 | { |
| 2722 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
| 2723 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); |
| 2724 | } |
| 2725 | |
| 2726 | /* System V Release 4 (SVR4). */ |
| 2727 | |
| 2728 | void |
| 2729 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
| 2730 | { |
| 2731 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2732 | |
| 2733 | /* System V Release 4 uses ELF. */ |
| 2734 | i386_elf_init_abi (info, gdbarch); |
| 2735 | |
| 2736 | /* System V Release 4 has shared libraries. */ |
| 2737 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
| 2738 | |
| 2739 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
| 2740 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
| 2741 | tdep->sc_pc_offset = 36 + 14 * 4; |
| 2742 | tdep->sc_sp_offset = 36 + 17 * 4; |
| 2743 | |
| 2744 | tdep->jb_pc_offset = 20; |
| 2745 | } |
| 2746 | |
| 2747 | /* DJGPP. */ |
| 2748 | |
| 2749 | static void |
| 2750 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
| 2751 | { |
| 2752 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2753 | |
| 2754 | /* DJGPP doesn't have any special frames for signal handlers. */ |
| 2755 | tdep->sigtramp_p = NULL; |
| 2756 | |
| 2757 | tdep->jb_pc_offset = 36; |
| 2758 | |
| 2759 | /* DJGPP does not support the SSE registers. */ |
| 2760 | tdep->num_xmm_regs = 0; |
| 2761 | set_gdbarch_num_regs (gdbarch, I386_NUM_GREGS + I387_NUM_REGS); |
| 2762 | |
| 2763 | /* Native compiler is GCC, which uses the SVR4 register numbering |
| 2764 | even in COFF and STABS. See the comment in i386_gdbarch_init, |
| 2765 | before the calls to set_gdbarch_stab_reg_to_regnum and |
| 2766 | set_gdbarch_sdb_reg_to_regnum. */ |
| 2767 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); |
| 2768 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); |
| 2769 | } |
| 2770 | \f |
| 2771 | |
| 2772 | /* i386 register groups. In addition to the normal groups, add "mmx" |
| 2773 | and "sse". */ |
| 2774 | |
| 2775 | static struct reggroup *i386_sse_reggroup; |
| 2776 | static struct reggroup *i386_mmx_reggroup; |
| 2777 | |
| 2778 | static void |
| 2779 | i386_init_reggroups (void) |
| 2780 | { |
| 2781 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); |
| 2782 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); |
| 2783 | } |
| 2784 | |
| 2785 | static void |
| 2786 | i386_add_reggroups (struct gdbarch *gdbarch) |
| 2787 | { |
| 2788 | reggroup_add (gdbarch, i386_sse_reggroup); |
| 2789 | reggroup_add (gdbarch, i386_mmx_reggroup); |
| 2790 | reggroup_add (gdbarch, general_reggroup); |
| 2791 | reggroup_add (gdbarch, float_reggroup); |
| 2792 | reggroup_add (gdbarch, all_reggroup); |
| 2793 | reggroup_add (gdbarch, save_reggroup); |
| 2794 | reggroup_add (gdbarch, restore_reggroup); |
| 2795 | reggroup_add (gdbarch, vector_reggroup); |
| 2796 | reggroup_add (gdbarch, system_reggroup); |
| 2797 | } |
| 2798 | |
| 2799 | int |
| 2800 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
| 2801 | struct reggroup *group) |
| 2802 | { |
| 2803 | int sse_regnum_p, fp_regnum_p, mmx_regnum_p, byte_regnum_p, |
| 2804 | word_regnum_p, dword_regnum_p; |
| 2805 | |
| 2806 | /* Don't include pseudo registers, except for MMX, in any register |
| 2807 | groups. */ |
| 2808 | byte_regnum_p = i386_byte_regnum_p (gdbarch, regnum); |
| 2809 | if (byte_regnum_p) |
| 2810 | return 0; |
| 2811 | |
| 2812 | word_regnum_p = i386_word_regnum_p (gdbarch, regnum); |
| 2813 | if (word_regnum_p) |
| 2814 | return 0; |
| 2815 | |
| 2816 | dword_regnum_p = i386_dword_regnum_p (gdbarch, regnum); |
| 2817 | if (dword_regnum_p) |
| 2818 | return 0; |
| 2819 | |
| 2820 | mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); |
| 2821 | if (group == i386_mmx_reggroup) |
| 2822 | return mmx_regnum_p; |
| 2823 | |
| 2824 | sse_regnum_p = (i386_sse_regnum_p (gdbarch, regnum) |
| 2825 | || i386_mxcsr_regnum_p (gdbarch, regnum)); |
| 2826 | if (group == i386_sse_reggroup) |
| 2827 | return sse_regnum_p; |
| 2828 | if (group == vector_reggroup) |
| 2829 | return mmx_regnum_p || sse_regnum_p; |
| 2830 | |
| 2831 | fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) |
| 2832 | || i386_fpc_regnum_p (gdbarch, regnum)); |
| 2833 | if (group == float_reggroup) |
| 2834 | return fp_regnum_p; |
| 2835 | |
| 2836 | if (group == general_reggroup) |
| 2837 | return (!fp_regnum_p |
| 2838 | && !mmx_regnum_p |
| 2839 | && !sse_regnum_p |
| 2840 | && !byte_regnum_p |
| 2841 | && !word_regnum_p |
| 2842 | && !dword_regnum_p); |
| 2843 | |
| 2844 | return default_register_reggroup_p (gdbarch, regnum, group); |
| 2845 | } |
| 2846 | \f |
| 2847 | |
| 2848 | /* Get the ARGIth function argument for the current function. */ |
| 2849 | |
| 2850 | static CORE_ADDR |
| 2851 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
| 2852 | struct type *type) |
| 2853 | { |
| 2854 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 2855 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2856 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
| 2857 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
| 2858 | } |
| 2859 | |
| 2860 | static void |
| 2861 | i386_skip_permanent_breakpoint (struct regcache *regcache) |
| 2862 | { |
| 2863 | CORE_ADDR current_pc = regcache_read_pc (regcache); |
| 2864 | |
| 2865 | /* On i386, breakpoint is exactly 1 byte long, so we just |
| 2866 | adjust the PC in the regcache. */ |
| 2867 | current_pc += 1; |
| 2868 | regcache_write_pc (regcache, current_pc); |
| 2869 | } |
| 2870 | |
| 2871 | |
| 2872 | #define PREFIX_REPZ 0x01 |
| 2873 | #define PREFIX_REPNZ 0x02 |
| 2874 | #define PREFIX_LOCK 0x04 |
| 2875 | #define PREFIX_DATA 0x08 |
| 2876 | #define PREFIX_ADDR 0x10 |
| 2877 | |
| 2878 | /* operand size */ |
| 2879 | enum |
| 2880 | { |
| 2881 | OT_BYTE = 0, |
| 2882 | OT_WORD, |
| 2883 | OT_LONG, |
| 2884 | OT_QUAD, |
| 2885 | }; |
| 2886 | |
| 2887 | /* i386 arith/logic operations */ |
| 2888 | enum |
| 2889 | { |
| 2890 | OP_ADDL, |
| 2891 | OP_ORL, |
| 2892 | OP_ADCL, |
| 2893 | OP_SBBL, |
| 2894 | OP_ANDL, |
| 2895 | OP_SUBL, |
| 2896 | OP_XORL, |
| 2897 | OP_CMPL, |
| 2898 | }; |
| 2899 | |
| 2900 | struct i386_record_s |
| 2901 | { |
| 2902 | struct gdbarch *gdbarch; |
| 2903 | struct regcache *regcache; |
| 2904 | CORE_ADDR orig_addr; |
| 2905 | CORE_ADDR addr; |
| 2906 | int aflag; |
| 2907 | int dflag; |
| 2908 | int override; |
| 2909 | uint8_t modrm; |
| 2910 | uint8_t mod, reg, rm; |
| 2911 | int ot; |
| 2912 | uint8_t rex_x; |
| 2913 | uint8_t rex_b; |
| 2914 | int rip_offset; |
| 2915 | int popl_esp_hack; |
| 2916 | const int *regmap; |
| 2917 | }; |
| 2918 | |
| 2919 | /* Parse "modrm" part in current memory address that irp->addr point to |
| 2920 | Return -1 if something wrong. */ |
| 2921 | |
| 2922 | static int |
| 2923 | i386_record_modrm (struct i386_record_s *irp) |
| 2924 | { |
| 2925 | struct gdbarch *gdbarch = irp->gdbarch; |
| 2926 | |
| 2927 | if (target_read_memory (irp->addr, &irp->modrm, 1)) |
| 2928 | { |
| 2929 | if (record_debug) |
| 2930 | printf_unfiltered (_("Process record: error reading memory at " |
| 2931 | "addr %s len = 1.\n"), |
| 2932 | paddress (gdbarch, irp->addr)); |
| 2933 | return -1; |
| 2934 | } |
| 2935 | irp->addr++; |
| 2936 | irp->mod = (irp->modrm >> 6) & 3; |
| 2937 | irp->reg = (irp->modrm >> 3) & 7; |
| 2938 | irp->rm = irp->modrm & 7; |
| 2939 | |
| 2940 | return 0; |
| 2941 | } |
| 2942 | |
| 2943 | /* Get the memory address that current instruction write to and set it to |
| 2944 | the argument "addr". |
| 2945 | Return -1 if something wrong. */ |
| 2946 | |
| 2947 | static int |
| 2948 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
| 2949 | { |
| 2950 | struct gdbarch *gdbarch = irp->gdbarch; |
| 2951 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2952 | gdb_byte buf[4]; |
| 2953 | ULONGEST offset64; |
| 2954 | |
| 2955 | *addr = 0; |
| 2956 | if (irp->aflag) |
| 2957 | { |
| 2958 | /* 32 bits */ |
| 2959 | int havesib = 0; |
| 2960 | uint8_t scale = 0; |
| 2961 | uint8_t byte; |
| 2962 | uint8_t index = 0; |
| 2963 | uint8_t base = irp->rm; |
| 2964 | |
| 2965 | if (base == 4) |
| 2966 | { |
| 2967 | havesib = 1; |
| 2968 | if (target_read_memory (irp->addr, &byte, 1)) |
| 2969 | { |
| 2970 | if (record_debug) |
| 2971 | printf_unfiltered (_("Process record: error reading memory " |
| 2972 | "at addr %s len = 1.\n"), |
| 2973 | paddress (gdbarch, irp->addr)); |
| 2974 | return -1; |
| 2975 | } |
| 2976 | irp->addr++; |
| 2977 | scale = (byte >> 6) & 3; |
| 2978 | index = ((byte >> 3) & 7) | irp->rex_x; |
| 2979 | base = (byte & 7); |
| 2980 | } |
| 2981 | base |= irp->rex_b; |
| 2982 | |
| 2983 | switch (irp->mod) |
| 2984 | { |
| 2985 | case 0: |
| 2986 | if ((base & 7) == 5) |
| 2987 | { |
| 2988 | base = 0xff; |
| 2989 | if (target_read_memory (irp->addr, buf, 4)) |
| 2990 | { |
| 2991 | if (record_debug) |
| 2992 | printf_unfiltered (_("Process record: error reading " |
| 2993 | "memory at addr %s len = 4.\n"), |
| 2994 | paddress (gdbarch, irp->addr)); |
| 2995 | return -1; |
| 2996 | } |
| 2997 | irp->addr += 4; |
| 2998 | *addr = extract_signed_integer (buf, 4, byte_order); |
| 2999 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) |
| 3000 | *addr += irp->addr + irp->rip_offset; |
| 3001 | } |
| 3002 | else |
| 3003 | { |
| 3004 | *addr = 0; |
| 3005 | } |
| 3006 | break; |
| 3007 | case 1: |
| 3008 | if (target_read_memory (irp->addr, buf, 1)) |
| 3009 | { |
| 3010 | if (record_debug) |
| 3011 | printf_unfiltered (_("Process record: error reading memory " |
| 3012 | "at addr %s len = 1.\n"), |
| 3013 | paddress (gdbarch, irp->addr)); |
| 3014 | return -1; |
| 3015 | } |
| 3016 | irp->addr++; |
| 3017 | *addr = (int8_t) buf[0]; |
| 3018 | break; |
| 3019 | case 2: |
| 3020 | if (target_read_memory (irp->addr, buf, 4)) |
| 3021 | { |
| 3022 | if (record_debug) |
| 3023 | printf_unfiltered (_("Process record: error reading memory " |
| 3024 | "at addr %s len = 4.\n"), |
| 3025 | paddress (gdbarch, irp->addr)); |
| 3026 | return -1; |
| 3027 | } |
| 3028 | *addr = extract_signed_integer (buf, 4, byte_order); |
| 3029 | irp->addr += 4; |
| 3030 | break; |
| 3031 | } |
| 3032 | |
| 3033 | offset64 = 0; |
| 3034 | if (base != 0xff) |
| 3035 | { |
| 3036 | if (base == 4 && irp->popl_esp_hack) |
| 3037 | *addr += irp->popl_esp_hack; |
| 3038 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], |
| 3039 | &offset64); |
| 3040 | } |
| 3041 | if (irp->aflag == 2) |
| 3042 | { |
| 3043 | *addr += offset64; |
| 3044 | } |
| 3045 | else |
| 3046 | *addr = (uint32_t) (offset64 + *addr); |
| 3047 | |
| 3048 | if (havesib && (index != 4 || scale != 0)) |
| 3049 | { |
| 3050 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
| 3051 | &offset64); |
| 3052 | if (irp->aflag == 2) |
| 3053 | *addr += offset64 << scale; |
| 3054 | else |
| 3055 | *addr = (uint32_t) (*addr + (offset64 << scale)); |
| 3056 | } |
| 3057 | } |
| 3058 | else |
| 3059 | { |
| 3060 | /* 16 bits */ |
| 3061 | switch (irp->mod) |
| 3062 | { |
| 3063 | case 0: |
| 3064 | if (irp->rm == 6) |
| 3065 | { |
| 3066 | if (target_read_memory (irp->addr, buf, 2)) |
| 3067 | { |
| 3068 | if (record_debug) |
| 3069 | printf_unfiltered (_("Process record: error reading " |
| 3070 | "memory at addr %s len = 2.\n"), |
| 3071 | paddress (gdbarch, irp->addr)); |
| 3072 | return -1; |
| 3073 | } |
| 3074 | irp->addr += 2; |
| 3075 | *addr = extract_signed_integer (buf, 2, byte_order); |
| 3076 | irp->rm = 0; |
| 3077 | goto no_rm; |
| 3078 | } |
| 3079 | else |
| 3080 | { |
| 3081 | *addr = 0; |
| 3082 | } |
| 3083 | break; |
| 3084 | case 1: |
| 3085 | if (target_read_memory (irp->addr, buf, 1)) |
| 3086 | { |
| 3087 | if (record_debug) |
| 3088 | printf_unfiltered (_("Process record: error reading memory " |
| 3089 | "at addr %s len = 1.\n"), |
| 3090 | paddress (gdbarch, irp->addr)); |
| 3091 | return -1; |
| 3092 | } |
| 3093 | irp->addr++; |
| 3094 | *addr = (int8_t) buf[0]; |
| 3095 | break; |
| 3096 | case 2: |
| 3097 | if (target_read_memory (irp->addr, buf, 2)) |
| 3098 | { |
| 3099 | if (record_debug) |
| 3100 | printf_unfiltered (_("Process record: error reading memory " |
| 3101 | "at addr %s len = 2.\n"), |
| 3102 | paddress (gdbarch, irp->addr)); |
| 3103 | return -1; |
| 3104 | } |
| 3105 | irp->addr += 2; |
| 3106 | *addr = extract_signed_integer (buf, 2, byte_order); |
| 3107 | break; |
| 3108 | } |
| 3109 | |
| 3110 | switch (irp->rm) |
| 3111 | { |
| 3112 | case 0: |
| 3113 | regcache_raw_read_unsigned (irp->regcache, |
| 3114 | irp->regmap[X86_RECORD_REBX_REGNUM], |
| 3115 | &offset64); |
| 3116 | *addr = (uint32_t) (*addr + offset64); |
| 3117 | regcache_raw_read_unsigned (irp->regcache, |
| 3118 | irp->regmap[X86_RECORD_RESI_REGNUM], |
| 3119 | &offset64); |
| 3120 | *addr = (uint32_t) (*addr + offset64); |
| 3121 | break; |
| 3122 | case 1: |
| 3123 | regcache_raw_read_unsigned (irp->regcache, |
| 3124 | irp->regmap[X86_RECORD_REBX_REGNUM], |
| 3125 | &offset64); |
| 3126 | *addr = (uint32_t) (*addr + offset64); |
| 3127 | regcache_raw_read_unsigned (irp->regcache, |
| 3128 | irp->regmap[X86_RECORD_REDI_REGNUM], |
| 3129 | &offset64); |
| 3130 | *addr = (uint32_t) (*addr + offset64); |
| 3131 | break; |
| 3132 | case 2: |
| 3133 | regcache_raw_read_unsigned (irp->regcache, |
| 3134 | irp->regmap[X86_RECORD_REBP_REGNUM], |
| 3135 | &offset64); |
| 3136 | *addr = (uint32_t) (*addr + offset64); |
| 3137 | regcache_raw_read_unsigned (irp->regcache, |
| 3138 | irp->regmap[X86_RECORD_RESI_REGNUM], |
| 3139 | &offset64); |
| 3140 | *addr = (uint32_t) (*addr + offset64); |
| 3141 | break; |
| 3142 | case 3: |
| 3143 | regcache_raw_read_unsigned (irp->regcache, |
| 3144 | irp->regmap[X86_RECORD_REBP_REGNUM], |
| 3145 | &offset64); |
| 3146 | *addr = (uint32_t) (*addr + offset64); |
| 3147 | regcache_raw_read_unsigned (irp->regcache, |
| 3148 | irp->regmap[X86_RECORD_REDI_REGNUM], |
| 3149 | &offset64); |
| 3150 | *addr = (uint32_t) (*addr + offset64); |
| 3151 | break; |
| 3152 | case 4: |
| 3153 | regcache_raw_read_unsigned (irp->regcache, |
| 3154 | irp->regmap[X86_RECORD_RESI_REGNUM], |
| 3155 | &offset64); |
| 3156 | *addr = (uint32_t) (*addr + offset64); |
| 3157 | break; |
| 3158 | case 5: |
| 3159 | regcache_raw_read_unsigned (irp->regcache, |
| 3160 | irp->regmap[X86_RECORD_REDI_REGNUM], |
| 3161 | &offset64); |
| 3162 | *addr = (uint32_t) (*addr + offset64); |
| 3163 | break; |
| 3164 | case 6: |
| 3165 | regcache_raw_read_unsigned (irp->regcache, |
| 3166 | irp->regmap[X86_RECORD_REBP_REGNUM], |
| 3167 | &offset64); |
| 3168 | *addr = (uint32_t) (*addr + offset64); |
| 3169 | break; |
| 3170 | case 7: |
| 3171 | regcache_raw_read_unsigned (irp->regcache, |
| 3172 | irp->regmap[X86_RECORD_REBX_REGNUM], |
| 3173 | &offset64); |
| 3174 | *addr = (uint32_t) (*addr + offset64); |
| 3175 | break; |
| 3176 | } |
| 3177 | *addr &= 0xffff; |
| 3178 | } |
| 3179 | |
| 3180 | no_rm: |
| 3181 | return 0; |
| 3182 | } |
| 3183 | |
| 3184 | /* Record the value of the memory that willbe changed in current instruction |
| 3185 | to "record_arch_list". |
| 3186 | Return -1 if something wrong. */ |
| 3187 | |
| 3188 | static int |
| 3189 | i386_record_lea_modrm (struct i386_record_s *irp) |
| 3190 | { |
| 3191 | struct gdbarch *gdbarch = irp->gdbarch; |
| 3192 | uint64_t addr; |
| 3193 | |
| 3194 | if (irp->override >= 0) |
| 3195 | { |
| 3196 | warning (_("Process record ignores the memory change " |
| 3197 | "of instruction at address %s because it " |
| 3198 | "can't get the value of the segment register."), |
| 3199 | paddress (gdbarch, irp->orig_addr)); |
| 3200 | return 0; |
| 3201 | } |
| 3202 | |
| 3203 | if (i386_record_lea_modrm_addr (irp, &addr)) |
| 3204 | return -1; |
| 3205 | |
| 3206 | if (record_arch_list_add_mem (addr, 1 << irp->ot)) |
| 3207 | return -1; |
| 3208 | |
| 3209 | return 0; |
| 3210 | } |
| 3211 | |
| 3212 | /* Record the push operation to "record_arch_list". |
| 3213 | Return -1 if something wrong. */ |
| 3214 | |
| 3215 | static int |
| 3216 | i386_record_push (struct i386_record_s *irp, int size) |
| 3217 | { |
| 3218 | ULONGEST addr; |
| 3219 | |
| 3220 | if (record_arch_list_add_reg (irp->regcache, |
| 3221 | irp->regmap[X86_RECORD_RESP_REGNUM])) |
| 3222 | return -1; |
| 3223 | regcache_raw_read_unsigned (irp->regcache, |
| 3224 | irp->regmap[X86_RECORD_RESP_REGNUM], |
| 3225 | &addr); |
| 3226 | if (record_arch_list_add_mem ((CORE_ADDR) addr - size, size)) |
| 3227 | return -1; |
| 3228 | |
| 3229 | return 0; |
| 3230 | } |
| 3231 | |
| 3232 | |
| 3233 | /* Defines contents to record. */ |
| 3234 | #define I386_SAVE_FPU_REGS 0xfffd |
| 3235 | #define I386_SAVE_FPU_ENV 0xfffe |
| 3236 | #define I386_SAVE_FPU_ENV_REG_STACK 0xffff |
| 3237 | |
| 3238 | /* Record the value of floating point registers which will be changed by the |
| 3239 | current instruction to "record_arch_list". Return -1 if something is wrong. |
| 3240 | */ |
| 3241 | |
| 3242 | static int i386_record_floats (struct gdbarch *gdbarch, |
| 3243 | struct i386_record_s *ir, |
| 3244 | uint32_t iregnum) |
| 3245 | { |
| 3246 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3247 | int i; |
| 3248 | |
| 3249 | /* Oza: Because of floating point insn push/pop of fpu stack is going to |
| 3250 | happen. Currently we store st0-st7 registers, but we need not store all |
| 3251 | registers all the time, in future we use ftag register and record only |
| 3252 | those who are not marked as an empty. */ |
| 3253 | |
| 3254 | if (I386_SAVE_FPU_REGS == iregnum) |
| 3255 | { |
| 3256 | for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) |
| 3257 | { |
| 3258 | if (record_arch_list_add_reg (ir->regcache, i)) |
| 3259 | return -1; |
| 3260 | } |
| 3261 | } |
| 3262 | else if (I386_SAVE_FPU_ENV == iregnum) |
| 3263 | { |
| 3264 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) |
| 3265 | { |
| 3266 | if (record_arch_list_add_reg (ir->regcache, i)) |
| 3267 | return -1; |
| 3268 | } |
| 3269 | } |
| 3270 | else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) |
| 3271 | { |
| 3272 | for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) |
| 3273 | { |
| 3274 | if (record_arch_list_add_reg (ir->regcache, i)) |
| 3275 | return -1; |
| 3276 | } |
| 3277 | } |
| 3278 | else if ((iregnum >= I387_ST0_REGNUM (tdep)) && |
| 3279 | (iregnum <= I387_FOP_REGNUM (tdep))) |
| 3280 | { |
| 3281 | if (record_arch_list_add_reg (ir->regcache,iregnum)) |
| 3282 | return -1; |
| 3283 | } |
| 3284 | else |
| 3285 | { |
| 3286 | /* Parameter error. */ |
| 3287 | return -1; |
| 3288 | } |
| 3289 | if(I386_SAVE_FPU_ENV != iregnum) |
| 3290 | { |
| 3291 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) |
| 3292 | { |
| 3293 | if (record_arch_list_add_reg (ir->regcache, i)) |
| 3294 | return -1; |
| 3295 | } |
| 3296 | } |
| 3297 | return 0; |
| 3298 | } |
| 3299 | |
| 3300 | /* Parse the current instruction and record the values of the registers and |
| 3301 | memory that will be changed in current instruction to "record_arch_list". |
| 3302 | Return -1 if something wrong. */ |
| 3303 | |
| 3304 | #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \ |
| 3305 | record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) |
| 3306 | |
| 3307 | int |
| 3308 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
| 3309 | CORE_ADDR input_addr) |
| 3310 | { |
| 3311 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 3312 | int prefixes = 0; |
| 3313 | int regnum = 0; |
| 3314 | uint32_t opcode; |
| 3315 | uint8_t opcode8; |
| 3316 | ULONGEST addr; |
| 3317 | gdb_byte buf[MAX_REGISTER_SIZE]; |
| 3318 | struct i386_record_s ir; |
| 3319 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3320 | int rex = 0; |
| 3321 | uint8_t rex_w = -1; |
| 3322 | uint8_t rex_r = 0; |
| 3323 | |
| 3324 | memset (&ir, 0, sizeof (struct i386_record_s)); |
| 3325 | ir.regcache = regcache; |
| 3326 | ir.addr = input_addr; |
| 3327 | ir.orig_addr = input_addr; |
| 3328 | ir.aflag = 1; |
| 3329 | ir.dflag = 1; |
| 3330 | ir.override = -1; |
| 3331 | ir.popl_esp_hack = 0; |
| 3332 | ir.regmap = gdbarch_tdep (gdbarch)->record_regmap; |
| 3333 | ir.gdbarch = gdbarch; |
| 3334 | |
| 3335 | if (record_debug > 1) |
| 3336 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " |
| 3337 | "addr = %s\n", |
| 3338 | paddress (gdbarch, ir.addr)); |
| 3339 | |
| 3340 | /* prefixes */ |
| 3341 | while (1) |
| 3342 | { |
| 3343 | if (target_read_memory (ir.addr, &opcode8, 1)) |
| 3344 | { |
| 3345 | if (record_debug) |
| 3346 | printf_unfiltered (_("Process record: error reading memory at " |
| 3347 | "addr %s len = 1.\n"), |
| 3348 | paddress (gdbarch, ir.addr)); |
| 3349 | return -1; |
| 3350 | } |
| 3351 | ir.addr++; |
| 3352 | switch (opcode8) /* Instruction prefixes */ |
| 3353 | { |
| 3354 | case REPE_PREFIX_OPCODE: |
| 3355 | prefixes |= PREFIX_REPZ; |
| 3356 | break; |
| 3357 | case REPNE_PREFIX_OPCODE: |
| 3358 | prefixes |= PREFIX_REPNZ; |
| 3359 | break; |
| 3360 | case LOCK_PREFIX_OPCODE: |
| 3361 | prefixes |= PREFIX_LOCK; |
| 3362 | break; |
| 3363 | case CS_PREFIX_OPCODE: |
| 3364 | ir.override = X86_RECORD_CS_REGNUM; |
| 3365 | break; |
| 3366 | case SS_PREFIX_OPCODE: |
| 3367 | ir.override = X86_RECORD_SS_REGNUM; |
| 3368 | break; |
| 3369 | case DS_PREFIX_OPCODE: |
| 3370 | ir.override = X86_RECORD_DS_REGNUM; |
| 3371 | break; |
| 3372 | case ES_PREFIX_OPCODE: |
| 3373 | ir.override = X86_RECORD_ES_REGNUM; |
| 3374 | break; |
| 3375 | case FS_PREFIX_OPCODE: |
| 3376 | ir.override = X86_RECORD_FS_REGNUM; |
| 3377 | break; |
| 3378 | case GS_PREFIX_OPCODE: |
| 3379 | ir.override = X86_RECORD_GS_REGNUM; |
| 3380 | break; |
| 3381 | case DATA_PREFIX_OPCODE: |
| 3382 | prefixes |= PREFIX_DATA; |
| 3383 | break; |
| 3384 | case ADDR_PREFIX_OPCODE: |
| 3385 | prefixes |= PREFIX_ADDR; |
| 3386 | break; |
| 3387 | case 0x40: /* i386 inc %eax */ |
| 3388 | case 0x41: /* i386 inc %ecx */ |
| 3389 | case 0x42: /* i386 inc %edx */ |
| 3390 | case 0x43: /* i386 inc %ebx */ |
| 3391 | case 0x44: /* i386 inc %esp */ |
| 3392 | case 0x45: /* i386 inc %ebp */ |
| 3393 | case 0x46: /* i386 inc %esi */ |
| 3394 | case 0x47: /* i386 inc %edi */ |
| 3395 | case 0x48: /* i386 dec %eax */ |
| 3396 | case 0x49: /* i386 dec %ecx */ |
| 3397 | case 0x4a: /* i386 dec %edx */ |
| 3398 | case 0x4b: /* i386 dec %ebx */ |
| 3399 | case 0x4c: /* i386 dec %esp */ |
| 3400 | case 0x4d: /* i386 dec %ebp */ |
| 3401 | case 0x4e: /* i386 dec %esi */ |
| 3402 | case 0x4f: /* i386 dec %edi */ |
| 3403 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ |
| 3404 | { |
| 3405 | /* REX */ |
| 3406 | rex = 1; |
| 3407 | rex_w = (opcode8 >> 3) & 1; |
| 3408 | rex_r = (opcode8 & 0x4) << 1; |
| 3409 | ir.rex_x = (opcode8 & 0x2) << 2; |
| 3410 | ir.rex_b = (opcode8 & 0x1) << 3; |
| 3411 | } |
| 3412 | else /* 32 bit target */ |
| 3413 | goto out_prefixes; |
| 3414 | break; |
| 3415 | default: |
| 3416 | goto out_prefixes; |
| 3417 | break; |
| 3418 | } |
| 3419 | } |
| 3420 | out_prefixes: |
| 3421 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
| 3422 | { |
| 3423 | ir.dflag = 2; |
| 3424 | } |
| 3425 | else |
| 3426 | { |
| 3427 | if (prefixes & PREFIX_DATA) |
| 3428 | ir.dflag ^= 1; |
| 3429 | } |
| 3430 | if (prefixes & PREFIX_ADDR) |
| 3431 | ir.aflag ^= 1; |
| 3432 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 3433 | ir.aflag = 2; |
| 3434 | |
| 3435 | /* now check op code */ |
| 3436 | opcode = (uint32_t) opcode8; |
| 3437 | reswitch: |
| 3438 | switch (opcode) |
| 3439 | { |
| 3440 | case 0x0f: |
| 3441 | if (target_read_memory (ir.addr, &opcode8, 1)) |
| 3442 | { |
| 3443 | if (record_debug) |
| 3444 | printf_unfiltered (_("Process record: error reading memory at " |
| 3445 | "addr %s len = 1.\n"), |
| 3446 | paddress (gdbarch, ir.addr)); |
| 3447 | return -1; |
| 3448 | } |
| 3449 | ir.addr++; |
| 3450 | opcode = (uint16_t) opcode8 | 0x0f00; |
| 3451 | goto reswitch; |
| 3452 | break; |
| 3453 | |
| 3454 | case 0x00: /* arith & logic */ |
| 3455 | case 0x01: |
| 3456 | case 0x02: |
| 3457 | case 0x03: |
| 3458 | case 0x04: |
| 3459 | case 0x05: |
| 3460 | case 0x08: |
| 3461 | case 0x09: |
| 3462 | case 0x0a: |
| 3463 | case 0x0b: |
| 3464 | case 0x0c: |
| 3465 | case 0x0d: |
| 3466 | case 0x10: |
| 3467 | case 0x11: |
| 3468 | case 0x12: |
| 3469 | case 0x13: |
| 3470 | case 0x14: |
| 3471 | case 0x15: |
| 3472 | case 0x18: |
| 3473 | case 0x19: |
| 3474 | case 0x1a: |
| 3475 | case 0x1b: |
| 3476 | case 0x1c: |
| 3477 | case 0x1d: |
| 3478 | case 0x20: |
| 3479 | case 0x21: |
| 3480 | case 0x22: |
| 3481 | case 0x23: |
| 3482 | case 0x24: |
| 3483 | case 0x25: |
| 3484 | case 0x28: |
| 3485 | case 0x29: |
| 3486 | case 0x2a: |
| 3487 | case 0x2b: |
| 3488 | case 0x2c: |
| 3489 | case 0x2d: |
| 3490 | case 0x30: |
| 3491 | case 0x31: |
| 3492 | case 0x32: |
| 3493 | case 0x33: |
| 3494 | case 0x34: |
| 3495 | case 0x35: |
| 3496 | case 0x38: |
| 3497 | case 0x39: |
| 3498 | case 0x3a: |
| 3499 | case 0x3b: |
| 3500 | case 0x3c: |
| 3501 | case 0x3d: |
| 3502 | if (((opcode >> 3) & 7) != OP_CMPL) |
| 3503 | { |
| 3504 | if ((opcode & 1) == 0) |
| 3505 | ir.ot = OT_BYTE; |
| 3506 | else |
| 3507 | ir.ot = ir.dflag + OT_WORD; |
| 3508 | |
| 3509 | switch ((opcode >> 1) & 3) |
| 3510 | { |
| 3511 | case 0: /* OP Ev, Gv */ |
| 3512 | if (i386_record_modrm (&ir)) |
| 3513 | return -1; |
| 3514 | if (ir.mod != 3) |
| 3515 | { |
| 3516 | if (i386_record_lea_modrm (&ir)) |
| 3517 | return -1; |
| 3518 | } |
| 3519 | else |
| 3520 | { |
| 3521 | ir.rm |= ir.rex_b; |
| 3522 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 3523 | ir.rm &= 0x3; |
| 3524 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
| 3525 | } |
| 3526 | break; |
| 3527 | case 1: /* OP Gv, Ev */ |
| 3528 | if (i386_record_modrm (&ir)) |
| 3529 | return -1; |
| 3530 | ir.reg |= rex_r; |
| 3531 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 3532 | ir.reg &= 0x3; |
| 3533 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
| 3534 | break; |
| 3535 | case 2: /* OP A, Iv */ |
| 3536 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 3537 | break; |
| 3538 | } |
| 3539 | } |
| 3540 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 3541 | break; |
| 3542 | |
| 3543 | case 0x80: /* GRP1 */ |
| 3544 | case 0x81: |
| 3545 | case 0x82: |
| 3546 | case 0x83: |
| 3547 | if (i386_record_modrm (&ir)) |
| 3548 | return -1; |
| 3549 | |
| 3550 | if (ir.reg != OP_CMPL) |
| 3551 | { |
| 3552 | if ((opcode & 1) == 0) |
| 3553 | ir.ot = OT_BYTE; |
| 3554 | else |
| 3555 | ir.ot = ir.dflag + OT_WORD; |
| 3556 | |
| 3557 | if (ir.mod != 3) |
| 3558 | { |
| 3559 | if (opcode == 0x83) |
| 3560 | ir.rip_offset = 1; |
| 3561 | else |
| 3562 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); |
| 3563 | if (i386_record_lea_modrm (&ir)) |
| 3564 | return -1; |
| 3565 | } |
| 3566 | else |
| 3567 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
| 3568 | } |
| 3569 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 3570 | break; |
| 3571 | |
| 3572 | case 0x40: /* inc */ |
| 3573 | case 0x41: |
| 3574 | case 0x42: |
| 3575 | case 0x43: |
| 3576 | case 0x44: |
| 3577 | case 0x45: |
| 3578 | case 0x46: |
| 3579 | case 0x47: |
| 3580 | |
| 3581 | case 0x48: /* dec */ |
| 3582 | case 0x49: |
| 3583 | case 0x4a: |
| 3584 | case 0x4b: |
| 3585 | case 0x4c: |
| 3586 | case 0x4d: |
| 3587 | case 0x4e: |
| 3588 | case 0x4f: |
| 3589 | |
| 3590 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7); |
| 3591 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 3592 | break; |
| 3593 | |
| 3594 | case 0xf6: /* GRP3 */ |
| 3595 | case 0xf7: |
| 3596 | if ((opcode & 1) == 0) |
| 3597 | ir.ot = OT_BYTE; |
| 3598 | else |
| 3599 | ir.ot = ir.dflag + OT_WORD; |
| 3600 | if (i386_record_modrm (&ir)) |
| 3601 | return -1; |
| 3602 | |
| 3603 | if (ir.mod != 3 && ir.reg == 0) |
| 3604 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); |
| 3605 | |
| 3606 | switch (ir.reg) |
| 3607 | { |
| 3608 | case 0: /* test */ |
| 3609 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 3610 | break; |
| 3611 | case 2: /* not */ |
| 3612 | case 3: /* neg */ |
| 3613 | if (ir.mod != 3) |
| 3614 | { |
| 3615 | if (i386_record_lea_modrm (&ir)) |
| 3616 | return -1; |
| 3617 | } |
| 3618 | else |
| 3619 | { |
| 3620 | ir.rm |= ir.rex_b; |
| 3621 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 3622 | ir.rm &= 0x3; |
| 3623 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
| 3624 | } |
| 3625 | if (ir.reg == 3) /* neg */ |
| 3626 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 3627 | break; |
| 3628 | case 4: /* mul */ |
| 3629 | case 5: /* imul */ |
| 3630 | case 6: /* div */ |
| 3631 | case 7: /* idiv */ |
| 3632 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 3633 | if (ir.ot != OT_BYTE) |
| 3634 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
| 3635 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 3636 | break; |
| 3637 | default: |
| 3638 | ir.addr -= 2; |
| 3639 | opcode = opcode << 8 | ir.modrm; |
| 3640 | goto no_support; |
| 3641 | break; |
| 3642 | } |
| 3643 | break; |
| 3644 | |
| 3645 | case 0xfe: /* GRP4 */ |
| 3646 | case 0xff: /* GRP5 */ |
| 3647 | if (i386_record_modrm (&ir)) |
| 3648 | return -1; |
| 3649 | if (ir.reg >= 2 && opcode == 0xfe) |
| 3650 | { |
| 3651 | ir.addr -= 2; |
| 3652 | opcode = opcode << 8 | ir.modrm; |
| 3653 | goto no_support; |
| 3654 | } |
| 3655 | switch (ir.reg) |
| 3656 | { |
| 3657 | case 0: /* inc */ |
| 3658 | case 1: /* dec */ |
| 3659 | if ((opcode & 1) == 0) |
| 3660 | ir.ot = OT_BYTE; |
| 3661 | else |
| 3662 | ir.ot = ir.dflag + OT_WORD; |
| 3663 | if (ir.mod != 3) |
| 3664 | { |
| 3665 | if (i386_record_lea_modrm (&ir)) |
| 3666 | return -1; |
| 3667 | } |
| 3668 | else |
| 3669 | { |
| 3670 | ir.rm |= ir.rex_b; |
| 3671 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 3672 | ir.rm &= 0x3; |
| 3673 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
| 3674 | } |
| 3675 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 3676 | break; |
| 3677 | case 2: /* call */ |
| 3678 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
| 3679 | ir.dflag = 2; |
| 3680 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
| 3681 | return -1; |
| 3682 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 3683 | break; |
| 3684 | case 3: /* lcall */ |
| 3685 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
| 3686 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
| 3687 | return -1; |
| 3688 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 3689 | break; |
| 3690 | case 4: /* jmp */ |
| 3691 | case 5: /* ljmp */ |
| 3692 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 3693 | break; |
| 3694 | case 6: /* push */ |
| 3695 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
| 3696 | ir.dflag = 2; |
| 3697 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
| 3698 | return -1; |
| 3699 | break; |
| 3700 | default: |
| 3701 | ir.addr -= 2; |
| 3702 | opcode = opcode << 8 | ir.modrm; |
| 3703 | goto no_support; |
| 3704 | break; |
| 3705 | } |
| 3706 | break; |
| 3707 | |
| 3708 | case 0x84: /* test */ |
| 3709 | case 0x85: |
| 3710 | case 0xa8: |
| 3711 | case 0xa9: |
| 3712 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 3713 | break; |
| 3714 | |
| 3715 | case 0x98: /* CWDE/CBW */ |
| 3716 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 3717 | break; |
| 3718 | |
| 3719 | case 0x99: /* CDQ/CWD */ |
| 3720 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 3721 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
| 3722 | break; |
| 3723 | |
| 3724 | case 0x0faf: /* imul */ |
| 3725 | case 0x69: |
| 3726 | case 0x6b: |
| 3727 | ir.ot = ir.dflag + OT_WORD; |
| 3728 | if (i386_record_modrm (&ir)) |
| 3729 | return -1; |
| 3730 | if (opcode == 0x69) |
| 3731 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); |
| 3732 | else if (opcode == 0x6b) |
| 3733 | ir.rip_offset = 1; |
| 3734 | ir.reg |= rex_r; |
| 3735 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 3736 | ir.reg &= 0x3; |
| 3737 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
| 3738 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 3739 | break; |
| 3740 | |
| 3741 | case 0x0fc0: /* xadd */ |
| 3742 | case 0x0fc1: |
| 3743 | if ((opcode & 1) == 0) |
| 3744 | ir.ot = OT_BYTE; |
| 3745 | else |
| 3746 | ir.ot = ir.dflag + OT_WORD; |
| 3747 | if (i386_record_modrm (&ir)) |
| 3748 | return -1; |
| 3749 | ir.reg |= rex_r; |
| 3750 | if (ir.mod == 3) |
| 3751 | { |
| 3752 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 3753 | ir.reg &= 0x3; |
| 3754 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
| 3755 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 3756 | ir.rm &= 0x3; |
| 3757 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
| 3758 | } |
| 3759 | else |
| 3760 | { |
| 3761 | if (i386_record_lea_modrm (&ir)) |
| 3762 | return -1; |
| 3763 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 3764 | ir.reg &= 0x3; |
| 3765 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
| 3766 | } |
| 3767 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 3768 | break; |
| 3769 | |
| 3770 | case 0x0fb0: /* cmpxchg */ |
| 3771 | case 0x0fb1: |
| 3772 | if ((opcode & 1) == 0) |
| 3773 | ir.ot = OT_BYTE; |
| 3774 | else |
| 3775 | ir.ot = ir.dflag + OT_WORD; |
| 3776 | if (i386_record_modrm (&ir)) |
| 3777 | return -1; |
| 3778 | if (ir.mod == 3) |
| 3779 | { |
| 3780 | ir.reg |= rex_r; |
| 3781 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 3782 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 3783 | ir.reg &= 0x3; |
| 3784 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
| 3785 | } |
| 3786 | else |
| 3787 | { |
| 3788 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 3789 | if (i386_record_lea_modrm (&ir)) |
| 3790 | return -1; |
| 3791 | } |
| 3792 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 3793 | break; |
| 3794 | |
| 3795 | case 0x0fc7: /* cmpxchg8b */ |
| 3796 | if (i386_record_modrm (&ir)) |
| 3797 | return -1; |
| 3798 | if (ir.mod == 3) |
| 3799 | { |
| 3800 | ir.addr -= 2; |
| 3801 | opcode = opcode << 8 | ir.modrm; |
| 3802 | goto no_support; |
| 3803 | } |
| 3804 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 3805 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
| 3806 | if (i386_record_lea_modrm (&ir)) |
| 3807 | return -1; |
| 3808 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 3809 | break; |
| 3810 | |
| 3811 | case 0x50: /* push */ |
| 3812 | case 0x51: |
| 3813 | case 0x52: |
| 3814 | case 0x53: |
| 3815 | case 0x54: |
| 3816 | case 0x55: |
| 3817 | case 0x56: |
| 3818 | case 0x57: |
| 3819 | case 0x68: |
| 3820 | case 0x6a: |
| 3821 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
| 3822 | ir.dflag = 2; |
| 3823 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
| 3824 | return -1; |
| 3825 | break; |
| 3826 | |
| 3827 | case 0x06: /* push es */ |
| 3828 | case 0x0e: /* push cs */ |
| 3829 | case 0x16: /* push ss */ |
| 3830 | case 0x1e: /* push ds */ |
| 3831 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 3832 | { |
| 3833 | ir.addr -= 1; |
| 3834 | goto no_support; |
| 3835 | } |
| 3836 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
| 3837 | return -1; |
| 3838 | break; |
| 3839 | |
| 3840 | case 0x0fa0: /* push fs */ |
| 3841 | case 0x0fa8: /* push gs */ |
| 3842 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 3843 | { |
| 3844 | ir.addr -= 2; |
| 3845 | goto no_support; |
| 3846 | } |
| 3847 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
| 3848 | return -1; |
| 3849 | break; |
| 3850 | |
| 3851 | case 0x60: /* pusha */ |
| 3852 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 3853 | { |
| 3854 | ir.addr -= 1; |
| 3855 | goto no_support; |
| 3856 | } |
| 3857 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) |
| 3858 | return -1; |
| 3859 | break; |
| 3860 | |
| 3861 | case 0x58: /* pop */ |
| 3862 | case 0x59: |
| 3863 | case 0x5a: |
| 3864 | case 0x5b: |
| 3865 | case 0x5c: |
| 3866 | case 0x5d: |
| 3867 | case 0x5e: |
| 3868 | case 0x5f: |
| 3869 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
| 3870 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
| 3871 | break; |
| 3872 | |
| 3873 | case 0x61: /* popa */ |
| 3874 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 3875 | { |
| 3876 | ir.addr -= 1; |
| 3877 | goto no_support; |
| 3878 | } |
| 3879 | for (regnum = X86_RECORD_REAX_REGNUM; |
| 3880 | regnum <= X86_RECORD_REDI_REGNUM; |
| 3881 | regnum++) |
| 3882 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); |
| 3883 | break; |
| 3884 | |
| 3885 | case 0x8f: /* pop */ |
| 3886 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 3887 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; |
| 3888 | else |
| 3889 | ir.ot = ir.dflag + OT_WORD; |
| 3890 | if (i386_record_modrm (&ir)) |
| 3891 | return -1; |
| 3892 | if (ir.mod == 3) |
| 3893 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
| 3894 | else |
| 3895 | { |
| 3896 | ir.popl_esp_hack = 1 << ir.ot; |
| 3897 | if (i386_record_lea_modrm (&ir)) |
| 3898 | return -1; |
| 3899 | } |
| 3900 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
| 3901 | break; |
| 3902 | |
| 3903 | case 0xc8: /* enter */ |
| 3904 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
| 3905 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
| 3906 | ir.dflag = 2; |
| 3907 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
| 3908 | return -1; |
| 3909 | break; |
| 3910 | |
| 3911 | case 0xc9: /* leave */ |
| 3912 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
| 3913 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
| 3914 | break; |
| 3915 | |
| 3916 | case 0x07: /* pop es */ |
| 3917 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 3918 | { |
| 3919 | ir.addr -= 1; |
| 3920 | goto no_support; |
| 3921 | } |
| 3922 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
| 3923 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); |
| 3924 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 3925 | break; |
| 3926 | |
| 3927 | case 0x17: /* pop ss */ |
| 3928 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 3929 | { |
| 3930 | ir.addr -= 1; |
| 3931 | goto no_support; |
| 3932 | } |
| 3933 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
| 3934 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); |
| 3935 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 3936 | break; |
| 3937 | |
| 3938 | case 0x1f: /* pop ds */ |
| 3939 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 3940 | { |
| 3941 | ir.addr -= 1; |
| 3942 | goto no_support; |
| 3943 | } |
| 3944 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
| 3945 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); |
| 3946 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 3947 | break; |
| 3948 | |
| 3949 | case 0x0fa1: /* pop fs */ |
| 3950 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
| 3951 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); |
| 3952 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 3953 | break; |
| 3954 | |
| 3955 | case 0x0fa9: /* pop gs */ |
| 3956 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
| 3957 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); |
| 3958 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 3959 | break; |
| 3960 | |
| 3961 | case 0x88: /* mov */ |
| 3962 | case 0x89: |
| 3963 | case 0xc6: |
| 3964 | case 0xc7: |
| 3965 | if ((opcode & 1) == 0) |
| 3966 | ir.ot = OT_BYTE; |
| 3967 | else |
| 3968 | ir.ot = ir.dflag + OT_WORD; |
| 3969 | |
| 3970 | if (i386_record_modrm (&ir)) |
| 3971 | return -1; |
| 3972 | |
| 3973 | if (ir.mod != 3) |
| 3974 | { |
| 3975 | if (opcode == 0xc6 || opcode == 0xc7) |
| 3976 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); |
| 3977 | if (i386_record_lea_modrm (&ir)) |
| 3978 | return -1; |
| 3979 | } |
| 3980 | else |
| 3981 | { |
| 3982 | if (opcode == 0xc6 || opcode == 0xc7) |
| 3983 | ir.rm |= ir.rex_b; |
| 3984 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 3985 | ir.rm &= 0x3; |
| 3986 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
| 3987 | } |
| 3988 | break; |
| 3989 | |
| 3990 | case 0x8a: /* mov */ |
| 3991 | case 0x8b: |
| 3992 | if ((opcode & 1) == 0) |
| 3993 | ir.ot = OT_BYTE; |
| 3994 | else |
| 3995 | ir.ot = ir.dflag + OT_WORD; |
| 3996 | if (i386_record_modrm (&ir)) |
| 3997 | return -1; |
| 3998 | ir.reg |= rex_r; |
| 3999 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4000 | ir.reg &= 0x3; |
| 4001 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
| 4002 | break; |
| 4003 | |
| 4004 | case 0x8c: /* mov seg */ |
| 4005 | if (i386_record_modrm (&ir)) |
| 4006 | return -1; |
| 4007 | if (ir.reg > 5) |
| 4008 | { |
| 4009 | ir.addr -= 2; |
| 4010 | opcode = opcode << 8 | ir.modrm; |
| 4011 | goto no_support; |
| 4012 | } |
| 4013 | |
| 4014 | if (ir.mod == 3) |
| 4015 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
| 4016 | else |
| 4017 | { |
| 4018 | ir.ot = OT_WORD; |
| 4019 | if (i386_record_lea_modrm (&ir)) |
| 4020 | return -1; |
| 4021 | } |
| 4022 | break; |
| 4023 | |
| 4024 | case 0x8e: /* mov seg */ |
| 4025 | if (i386_record_modrm (&ir)) |
| 4026 | return -1; |
| 4027 | switch (ir.reg) |
| 4028 | { |
| 4029 | case 0: |
| 4030 | regnum = X86_RECORD_ES_REGNUM; |
| 4031 | break; |
| 4032 | case 2: |
| 4033 | regnum = X86_RECORD_SS_REGNUM; |
| 4034 | break; |
| 4035 | case 3: |
| 4036 | regnum = X86_RECORD_DS_REGNUM; |
| 4037 | break; |
| 4038 | case 4: |
| 4039 | regnum = X86_RECORD_FS_REGNUM; |
| 4040 | break; |
| 4041 | case 5: |
| 4042 | regnum = X86_RECORD_GS_REGNUM; |
| 4043 | break; |
| 4044 | default: |
| 4045 | ir.addr -= 2; |
| 4046 | opcode = opcode << 8 | ir.modrm; |
| 4047 | goto no_support; |
| 4048 | break; |
| 4049 | } |
| 4050 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); |
| 4051 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4052 | break; |
| 4053 | |
| 4054 | case 0x0fb6: /* movzbS */ |
| 4055 | case 0x0fb7: /* movzwS */ |
| 4056 | case 0x0fbe: /* movsbS */ |
| 4057 | case 0x0fbf: /* movswS */ |
| 4058 | if (i386_record_modrm (&ir)) |
| 4059 | return -1; |
| 4060 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
| 4061 | break; |
| 4062 | |
| 4063 | case 0x8d: /* lea */ |
| 4064 | if (i386_record_modrm (&ir)) |
| 4065 | return -1; |
| 4066 | if (ir.mod == 3) |
| 4067 | { |
| 4068 | ir.addr -= 2; |
| 4069 | opcode = opcode << 8 | ir.modrm; |
| 4070 | goto no_support; |
| 4071 | } |
| 4072 | ir.ot = ir.dflag; |
| 4073 | ir.reg |= rex_r; |
| 4074 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4075 | ir.reg &= 0x3; |
| 4076 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
| 4077 | break; |
| 4078 | |
| 4079 | case 0xa0: /* mov EAX */ |
| 4080 | case 0xa1: |
| 4081 | |
| 4082 | case 0xd7: /* xlat */ |
| 4083 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 4084 | break; |
| 4085 | |
| 4086 | case 0xa2: /* mov EAX */ |
| 4087 | case 0xa3: |
| 4088 | if (ir.override >= 0) |
| 4089 | { |
| 4090 | warning (_("Process record ignores the memory change " |
| 4091 | "of instruction at address %s because " |
| 4092 | "it can't get the value of the segment " |
| 4093 | "register."), |
| 4094 | paddress (gdbarch, ir.orig_addr)); |
| 4095 | } |
| 4096 | else |
| 4097 | { |
| 4098 | if ((opcode & 1) == 0) |
| 4099 | ir.ot = OT_BYTE; |
| 4100 | else |
| 4101 | ir.ot = ir.dflag + OT_WORD; |
| 4102 | if (ir.aflag == 2) |
| 4103 | { |
| 4104 | if (target_read_memory (ir.addr, buf, 8)) |
| 4105 | { |
| 4106 | if (record_debug) |
| 4107 | printf_unfiltered (_("Process record: error reading " |
| 4108 | "memory at addr 0x%s len = 8.\n"), |
| 4109 | paddress (gdbarch, ir.addr)); |
| 4110 | return -1; |
| 4111 | } |
| 4112 | ir.addr += 8; |
| 4113 | addr = extract_unsigned_integer (buf, 8, byte_order); |
| 4114 | } |
| 4115 | else if (ir.aflag) |
| 4116 | { |
| 4117 | if (target_read_memory (ir.addr, buf, 4)) |
| 4118 | { |
| 4119 | if (record_debug) |
| 4120 | printf_unfiltered (_("Process record: error reading " |
| 4121 | "memory at addr 0x%s len = 4.\n"), |
| 4122 | paddress (gdbarch, ir.addr)); |
| 4123 | return -1; |
| 4124 | } |
| 4125 | ir.addr += 4; |
| 4126 | addr = extract_unsigned_integer (buf, 4, byte_order); |
| 4127 | } |
| 4128 | else |
| 4129 | { |
| 4130 | if (target_read_memory (ir.addr, buf, 2)) |
| 4131 | { |
| 4132 | if (record_debug) |
| 4133 | printf_unfiltered (_("Process record: error reading " |
| 4134 | "memory at addr 0x%s len = 2.\n"), |
| 4135 | paddress (gdbarch, ir.addr)); |
| 4136 | return -1; |
| 4137 | } |
| 4138 | ir.addr += 2; |
| 4139 | addr = extract_unsigned_integer (buf, 2, byte_order); |
| 4140 | } |
| 4141 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) |
| 4142 | return -1; |
| 4143 | } |
| 4144 | break; |
| 4145 | |
| 4146 | case 0xb0: /* mov R, Ib */ |
| 4147 | case 0xb1: |
| 4148 | case 0xb2: |
| 4149 | case 0xb3: |
| 4150 | case 0xb4: |
| 4151 | case 0xb5: |
| 4152 | case 0xb6: |
| 4153 | case 0xb7: |
| 4154 | I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4155 | ? ((opcode & 0x7) | ir.rex_b) |
| 4156 | : ((opcode & 0x7) & 0x3)); |
| 4157 | break; |
| 4158 | |
| 4159 | case 0xb8: /* mov R, Iv */ |
| 4160 | case 0xb9: |
| 4161 | case 0xba: |
| 4162 | case 0xbb: |
| 4163 | case 0xbc: |
| 4164 | case 0xbd: |
| 4165 | case 0xbe: |
| 4166 | case 0xbf: |
| 4167 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
| 4168 | break; |
| 4169 | |
| 4170 | case 0x91: /* xchg R, EAX */ |
| 4171 | case 0x92: |
| 4172 | case 0x93: |
| 4173 | case 0x94: |
| 4174 | case 0x95: |
| 4175 | case 0x96: |
| 4176 | case 0x97: |
| 4177 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 4178 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7); |
| 4179 | break; |
| 4180 | |
| 4181 | case 0x86: /* xchg Ev, Gv */ |
| 4182 | case 0x87: |
| 4183 | if ((opcode & 1) == 0) |
| 4184 | ir.ot = OT_BYTE; |
| 4185 | else |
| 4186 | ir.ot = ir.dflag + OT_WORD; |
| 4187 | if (i386_record_modrm (&ir)) |
| 4188 | return -1; |
| 4189 | if (ir.mod == 3) |
| 4190 | { |
| 4191 | ir.rm |= ir.rex_b; |
| 4192 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4193 | ir.rm &= 0x3; |
| 4194 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
| 4195 | } |
| 4196 | else |
| 4197 | { |
| 4198 | if (i386_record_lea_modrm (&ir)) |
| 4199 | return -1; |
| 4200 | } |
| 4201 | ir.reg |= rex_r; |
| 4202 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4203 | ir.reg &= 0x3; |
| 4204 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
| 4205 | break; |
| 4206 | |
| 4207 | case 0xc4: /* les Gv */ |
| 4208 | case 0xc5: /* lds Gv */ |
| 4209 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4210 | { |
| 4211 | ir.addr -= 1; |
| 4212 | goto no_support; |
| 4213 | } |
| 4214 | case 0x0fb2: /* lss Gv */ |
| 4215 | case 0x0fb4: /* lfs Gv */ |
| 4216 | case 0x0fb5: /* lgs Gv */ |
| 4217 | if (i386_record_modrm (&ir)) |
| 4218 | return -1; |
| 4219 | if (ir.mod == 3) |
| 4220 | { |
| 4221 | if (opcode > 0xff) |
| 4222 | ir.addr -= 3; |
| 4223 | else |
| 4224 | ir.addr -= 2; |
| 4225 | opcode = opcode << 8 | ir.modrm; |
| 4226 | goto no_support; |
| 4227 | } |
| 4228 | switch (opcode) |
| 4229 | { |
| 4230 | case 0xc4: /* les Gv */ |
| 4231 | regnum = X86_RECORD_ES_REGNUM; |
| 4232 | break; |
| 4233 | case 0xc5: /* lds Gv */ |
| 4234 | regnum = X86_RECORD_DS_REGNUM; |
| 4235 | break; |
| 4236 | case 0x0fb2: /* lss Gv */ |
| 4237 | regnum = X86_RECORD_SS_REGNUM; |
| 4238 | break; |
| 4239 | case 0x0fb4: /* lfs Gv */ |
| 4240 | regnum = X86_RECORD_FS_REGNUM; |
| 4241 | break; |
| 4242 | case 0x0fb5: /* lgs Gv */ |
| 4243 | regnum = X86_RECORD_GS_REGNUM; |
| 4244 | break; |
| 4245 | } |
| 4246 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); |
| 4247 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
| 4248 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4249 | break; |
| 4250 | |
| 4251 | case 0xc0: /* shifts */ |
| 4252 | case 0xc1: |
| 4253 | case 0xd0: |
| 4254 | case 0xd1: |
| 4255 | case 0xd2: |
| 4256 | case 0xd3: |
| 4257 | if ((opcode & 1) == 0) |
| 4258 | ir.ot = OT_BYTE; |
| 4259 | else |
| 4260 | ir.ot = ir.dflag + OT_WORD; |
| 4261 | if (i386_record_modrm (&ir)) |
| 4262 | return -1; |
| 4263 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
| 4264 | { |
| 4265 | if (i386_record_lea_modrm (&ir)) |
| 4266 | return -1; |
| 4267 | } |
| 4268 | else |
| 4269 | { |
| 4270 | ir.rm |= ir.rex_b; |
| 4271 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4272 | ir.rm &= 0x3; |
| 4273 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
| 4274 | } |
| 4275 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4276 | break; |
| 4277 | |
| 4278 | case 0x0fa4: |
| 4279 | case 0x0fa5: |
| 4280 | case 0x0fac: |
| 4281 | case 0x0fad: |
| 4282 | if (i386_record_modrm (&ir)) |
| 4283 | return -1; |
| 4284 | if (ir.mod == 3) |
| 4285 | { |
| 4286 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) |
| 4287 | return -1; |
| 4288 | } |
| 4289 | else |
| 4290 | { |
| 4291 | if (i386_record_lea_modrm (&ir)) |
| 4292 | return -1; |
| 4293 | } |
| 4294 | break; |
| 4295 | |
| 4296 | case 0xd8: /* Floats. */ |
| 4297 | case 0xd9: |
| 4298 | case 0xda: |
| 4299 | case 0xdb: |
| 4300 | case 0xdc: |
| 4301 | case 0xdd: |
| 4302 | case 0xde: |
| 4303 | case 0xdf: |
| 4304 | if (i386_record_modrm (&ir)) |
| 4305 | return -1; |
| 4306 | ir.reg |= ((opcode & 7) << 3); |
| 4307 | if (ir.mod != 3) |
| 4308 | { |
| 4309 | /* Memory. */ |
| 4310 | uint64_t addr64; |
| 4311 | |
| 4312 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
| 4313 | return -1; |
| 4314 | switch (ir.reg) |
| 4315 | { |
| 4316 | case 0x02: |
| 4317 | case 0x12: |
| 4318 | case 0x22: |
| 4319 | case 0x32: |
| 4320 | /* For fcom, ficom nothing to do. */ |
| 4321 | break; |
| 4322 | case 0x03: |
| 4323 | case 0x13: |
| 4324 | case 0x23: |
| 4325 | case 0x33: |
| 4326 | /* For fcomp, ficomp pop FPU stack, store all. */ |
| 4327 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
| 4328 | return -1; |
| 4329 | break; |
| 4330 | case 0x00: |
| 4331 | case 0x01: |
| 4332 | case 0x04: |
| 4333 | case 0x05: |
| 4334 | case 0x06: |
| 4335 | case 0x07: |
| 4336 | case 0x10: |
| 4337 | case 0x11: |
| 4338 | case 0x14: |
| 4339 | case 0x15: |
| 4340 | case 0x16: |
| 4341 | case 0x17: |
| 4342 | case 0x20: |
| 4343 | case 0x21: |
| 4344 | case 0x24: |
| 4345 | case 0x25: |
| 4346 | case 0x26: |
| 4347 | case 0x27: |
| 4348 | case 0x30: |
| 4349 | case 0x31: |
| 4350 | case 0x34: |
| 4351 | case 0x35: |
| 4352 | case 0x36: |
| 4353 | case 0x37: |
| 4354 | /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, |
| 4355 | fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension |
| 4356 | of code, always affects st(0) register. */ |
| 4357 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) |
| 4358 | return -1; |
| 4359 | break; |
| 4360 | case 0x08: |
| 4361 | case 0x0a: |
| 4362 | case 0x0b: |
| 4363 | case 0x18: |
| 4364 | case 0x19: |
| 4365 | case 0x1a: |
| 4366 | case 0x1b: |
| 4367 | case 0x1d: |
| 4368 | case 0x28: |
| 4369 | case 0x29: |
| 4370 | case 0x2a: |
| 4371 | case 0x2b: |
| 4372 | case 0x38: |
| 4373 | case 0x39: |
| 4374 | case 0x3a: |
| 4375 | case 0x3b: |
| 4376 | case 0x3c: |
| 4377 | case 0x3d: |
| 4378 | switch (ir.reg & 7) |
| 4379 | { |
| 4380 | case 0: |
| 4381 | /* Handling fld, fild. */ |
| 4382 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
| 4383 | return -1; |
| 4384 | break; |
| 4385 | case 1: |
| 4386 | switch (ir.reg >> 4) |
| 4387 | { |
| 4388 | case 0: |
| 4389 | if (record_arch_list_add_mem (addr64, 4)) |
| 4390 | return -1; |
| 4391 | break; |
| 4392 | case 2: |
| 4393 | if (record_arch_list_add_mem (addr64, 8)) |
| 4394 | return -1; |
| 4395 | break; |
| 4396 | case 3: |
| 4397 | break; |
| 4398 | default: |
| 4399 | if (record_arch_list_add_mem (addr64, 2)) |
| 4400 | return -1; |
| 4401 | break; |
| 4402 | } |
| 4403 | break; |
| 4404 | default: |
| 4405 | switch (ir.reg >> 4) |
| 4406 | { |
| 4407 | case 0: |
| 4408 | if (record_arch_list_add_mem (addr64, 4)) |
| 4409 | return -1; |
| 4410 | if (3 == (ir.reg & 7)) |
| 4411 | { |
| 4412 | /* For fstp m32fp. */ |
| 4413 | if (i386_record_floats (gdbarch, &ir, |
| 4414 | I386_SAVE_FPU_REGS)) |
| 4415 | return -1; |
| 4416 | } |
| 4417 | break; |
| 4418 | case 1: |
| 4419 | if (record_arch_list_add_mem (addr64, 4)) |
| 4420 | return -1; |
| 4421 | if ((3 == (ir.reg & 7)) |
| 4422 | || (5 == (ir.reg & 7)) |
| 4423 | || (7 == (ir.reg & 7))) |
| 4424 | { |
| 4425 | /* For fstp insn. */ |
| 4426 | if (i386_record_floats (gdbarch, &ir, |
| 4427 | I386_SAVE_FPU_REGS)) |
| 4428 | return -1; |
| 4429 | } |
| 4430 | break; |
| 4431 | case 2: |
| 4432 | if (record_arch_list_add_mem (addr64, 8)) |
| 4433 | return -1; |
| 4434 | if (3 == (ir.reg & 7)) |
| 4435 | { |
| 4436 | /* For fstp m64fp. */ |
| 4437 | if (i386_record_floats (gdbarch, &ir, |
| 4438 | I386_SAVE_FPU_REGS)) |
| 4439 | return -1; |
| 4440 | } |
| 4441 | break; |
| 4442 | case 3: |
| 4443 | if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) |
| 4444 | { |
| 4445 | /* For fistp, fbld, fild, fbstp. */ |
| 4446 | if (i386_record_floats (gdbarch, &ir, |
| 4447 | I386_SAVE_FPU_REGS)) |
| 4448 | return -1; |
| 4449 | } |
| 4450 | /* Fall through */ |
| 4451 | default: |
| 4452 | if (record_arch_list_add_mem (addr64, 2)) |
| 4453 | return -1; |
| 4454 | break; |
| 4455 | } |
| 4456 | break; |
| 4457 | } |
| 4458 | break; |
| 4459 | case 0x0c: |
| 4460 | /* Insn fldenv. */ |
| 4461 | if (i386_record_floats (gdbarch, &ir, |
| 4462 | I386_SAVE_FPU_ENV_REG_STACK)) |
| 4463 | return -1; |
| 4464 | break; |
| 4465 | case 0x0d: |
| 4466 | /* Insn fldcw. */ |
| 4467 | if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) |
| 4468 | return -1; |
| 4469 | break; |
| 4470 | case 0x2c: |
| 4471 | /* Insn frstor. */ |
| 4472 | if (i386_record_floats (gdbarch, &ir, |
| 4473 | I386_SAVE_FPU_ENV_REG_STACK)) |
| 4474 | return -1; |
| 4475 | break; |
| 4476 | case 0x0e: |
| 4477 | if (ir.dflag) |
| 4478 | { |
| 4479 | if (record_arch_list_add_mem (addr64, 28)) |
| 4480 | return -1; |
| 4481 | } |
| 4482 | else |
| 4483 | { |
| 4484 | if (record_arch_list_add_mem (addr64, 14)) |
| 4485 | return -1; |
| 4486 | } |
| 4487 | break; |
| 4488 | case 0x0f: |
| 4489 | case 0x2f: |
| 4490 | if (record_arch_list_add_mem (addr64, 2)) |
| 4491 | return -1; |
| 4492 | /* Insn fstp, fbstp. */ |
| 4493 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
| 4494 | return -1; |
| 4495 | break; |
| 4496 | case 0x1f: |
| 4497 | case 0x3e: |
| 4498 | if (record_arch_list_add_mem (addr64, 10)) |
| 4499 | return -1; |
| 4500 | break; |
| 4501 | case 0x2e: |
| 4502 | if (ir.dflag) |
| 4503 | { |
| 4504 | if (record_arch_list_add_mem (addr64, 28)) |
| 4505 | return -1; |
| 4506 | addr64 += 28; |
| 4507 | } |
| 4508 | else |
| 4509 | { |
| 4510 | if (record_arch_list_add_mem (addr64, 14)) |
| 4511 | return -1; |
| 4512 | addr64 += 14; |
| 4513 | } |
| 4514 | if (record_arch_list_add_mem (addr64, 80)) |
| 4515 | return -1; |
| 4516 | /* Insn fsave. */ |
| 4517 | if (i386_record_floats (gdbarch, &ir, |
| 4518 | I386_SAVE_FPU_ENV_REG_STACK)) |
| 4519 | return -1; |
| 4520 | break; |
| 4521 | case 0x3f: |
| 4522 | if (record_arch_list_add_mem (addr64, 8)) |
| 4523 | return -1; |
| 4524 | /* Insn fistp. */ |
| 4525 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
| 4526 | return -1; |
| 4527 | break; |
| 4528 | default: |
| 4529 | ir.addr -= 2; |
| 4530 | opcode = opcode << 8 | ir.modrm; |
| 4531 | goto no_support; |
| 4532 | break; |
| 4533 | } |
| 4534 | } |
| 4535 | /* Opcode is an extension of modR/M byte. */ |
| 4536 | else |
| 4537 | { |
| 4538 | switch (opcode) |
| 4539 | { |
| 4540 | case 0xd8: |
| 4541 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) |
| 4542 | return -1; |
| 4543 | break; |
| 4544 | case 0xd9: |
| 4545 | if (0x0c == (ir.modrm >> 4)) |
| 4546 | { |
| 4547 | if ((ir.modrm & 0x0f) <= 7) |
| 4548 | { |
| 4549 | if (i386_record_floats (gdbarch, &ir, |
| 4550 | I386_SAVE_FPU_REGS)) |
| 4551 | return -1; |
| 4552 | } |
| 4553 | else |
| 4554 | { |
| 4555 | if (i386_record_floats (gdbarch, &ir, |
| 4556 | I387_ST0_REGNUM (tdep))) |
| 4557 | return -1; |
| 4558 | /* If only st(0) is changing, then we have already |
| 4559 | recorded. */ |
| 4560 | if ((ir.modrm & 0x0f) - 0x08) |
| 4561 | { |
| 4562 | if (i386_record_floats (gdbarch, &ir, |
| 4563 | I387_ST0_REGNUM (tdep) + |
| 4564 | ((ir.modrm & 0x0f) - 0x08))) |
| 4565 | return -1; |
| 4566 | } |
| 4567 | } |
| 4568 | } |
| 4569 | else |
| 4570 | { |
| 4571 | switch (ir.modrm) |
| 4572 | { |
| 4573 | case 0xe0: |
| 4574 | case 0xe1: |
| 4575 | case 0xf0: |
| 4576 | case 0xf5: |
| 4577 | case 0xf8: |
| 4578 | case 0xfa: |
| 4579 | case 0xfc: |
| 4580 | case 0xfe: |
| 4581 | case 0xff: |
| 4582 | if (i386_record_floats (gdbarch, &ir, |
| 4583 | I387_ST0_REGNUM (tdep))) |
| 4584 | return -1; |
| 4585 | break; |
| 4586 | case 0xf1: |
| 4587 | case 0xf2: |
| 4588 | case 0xf3: |
| 4589 | case 0xf4: |
| 4590 | case 0xf6: |
| 4591 | case 0xf7: |
| 4592 | case 0xe8: |
| 4593 | case 0xe9: |
| 4594 | case 0xea: |
| 4595 | case 0xeb: |
| 4596 | case 0xec: |
| 4597 | case 0xed: |
| 4598 | case 0xee: |
| 4599 | case 0xf9: |
| 4600 | case 0xfb: |
| 4601 | if (i386_record_floats (gdbarch, &ir, |
| 4602 | I386_SAVE_FPU_REGS)) |
| 4603 | return -1; |
| 4604 | break; |
| 4605 | case 0xfd: |
| 4606 | if (i386_record_floats (gdbarch, &ir, |
| 4607 | I387_ST0_REGNUM (tdep))) |
| 4608 | return -1; |
| 4609 | if (i386_record_floats (gdbarch, &ir, |
| 4610 | I387_ST0_REGNUM (tdep) + 1)) |
| 4611 | return -1; |
| 4612 | break; |
| 4613 | } |
| 4614 | } |
| 4615 | break; |
| 4616 | case 0xda: |
| 4617 | if (0xe9 == ir.modrm) |
| 4618 | { |
| 4619 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
| 4620 | return -1; |
| 4621 | } |
| 4622 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) |
| 4623 | { |
| 4624 | if (i386_record_floats (gdbarch, &ir, |
| 4625 | I387_ST0_REGNUM (tdep))) |
| 4626 | return -1; |
| 4627 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) |
| 4628 | { |
| 4629 | if (i386_record_floats (gdbarch, &ir, |
| 4630 | I387_ST0_REGNUM (tdep) + |
| 4631 | (ir.modrm & 0x0f))) |
| 4632 | return -1; |
| 4633 | } |
| 4634 | else if ((ir.modrm & 0x0f) - 0x08) |
| 4635 | { |
| 4636 | if (i386_record_floats (gdbarch, &ir, |
| 4637 | I387_ST0_REGNUM (tdep) + |
| 4638 | ((ir.modrm & 0x0f) - 0x08))) |
| 4639 | return -1; |
| 4640 | } |
| 4641 | } |
| 4642 | break; |
| 4643 | case 0xdb: |
| 4644 | if (0xe3 == ir.modrm) |
| 4645 | { |
| 4646 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) |
| 4647 | return -1; |
| 4648 | } |
| 4649 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) |
| 4650 | { |
| 4651 | if (i386_record_floats (gdbarch, &ir, |
| 4652 | I387_ST0_REGNUM (tdep))) |
| 4653 | return -1; |
| 4654 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) |
| 4655 | { |
| 4656 | if (i386_record_floats (gdbarch, &ir, |
| 4657 | I387_ST0_REGNUM (tdep) + |
| 4658 | (ir.modrm & 0x0f))) |
| 4659 | return -1; |
| 4660 | } |
| 4661 | else if ((ir.modrm & 0x0f) - 0x08) |
| 4662 | { |
| 4663 | if (i386_record_floats (gdbarch, &ir, |
| 4664 | I387_ST0_REGNUM (tdep) + |
| 4665 | ((ir.modrm & 0x0f) - 0x08))) |
| 4666 | return -1; |
| 4667 | } |
| 4668 | } |
| 4669 | break; |
| 4670 | case 0xdc: |
| 4671 | if ((0x0c == ir.modrm >> 4) |
| 4672 | || (0x0d == ir.modrm >> 4) |
| 4673 | || (0x0f == ir.modrm >> 4)) |
| 4674 | { |
| 4675 | if ((ir.modrm & 0x0f) <= 7) |
| 4676 | { |
| 4677 | if (i386_record_floats (gdbarch, &ir, |
| 4678 | I387_ST0_REGNUM (tdep) + |
| 4679 | (ir.modrm & 0x0f))) |
| 4680 | return -1; |
| 4681 | } |
| 4682 | else |
| 4683 | { |
| 4684 | if (i386_record_floats (gdbarch, &ir, |
| 4685 | I387_ST0_REGNUM (tdep) + |
| 4686 | ((ir.modrm & 0x0f) - 0x08))) |
| 4687 | return -1; |
| 4688 | } |
| 4689 | } |
| 4690 | break; |
| 4691 | case 0xdd: |
| 4692 | if (0x0c == ir.modrm >> 4) |
| 4693 | { |
| 4694 | if (i386_record_floats (gdbarch, &ir, |
| 4695 | I387_FTAG_REGNUM (tdep))) |
| 4696 | return -1; |
| 4697 | } |
| 4698 | else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) |
| 4699 | { |
| 4700 | if ((ir.modrm & 0x0f) <= 7) |
| 4701 | { |
| 4702 | if (i386_record_floats (gdbarch, &ir, |
| 4703 | I387_ST0_REGNUM (tdep) + |
| 4704 | (ir.modrm & 0x0f))) |
| 4705 | return -1; |
| 4706 | } |
| 4707 | else |
| 4708 | { |
| 4709 | if (i386_record_floats (gdbarch, &ir, |
| 4710 | I386_SAVE_FPU_REGS)) |
| 4711 | return -1; |
| 4712 | } |
| 4713 | } |
| 4714 | break; |
| 4715 | case 0xde: |
| 4716 | if ((0x0c == ir.modrm >> 4) |
| 4717 | || (0x0e == ir.modrm >> 4) |
| 4718 | || (0x0f == ir.modrm >> 4) |
| 4719 | || (0xd9 == ir.modrm)) |
| 4720 | { |
| 4721 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
| 4722 | return -1; |
| 4723 | } |
| 4724 | break; |
| 4725 | case 0xdf: |
| 4726 | if (0xe0 == ir.modrm) |
| 4727 | { |
| 4728 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) |
| 4729 | return -1; |
| 4730 | } |
| 4731 | else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) |
| 4732 | { |
| 4733 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
| 4734 | return -1; |
| 4735 | } |
| 4736 | break; |
| 4737 | } |
| 4738 | } |
| 4739 | break; |
| 4740 | /* string ops */ |
| 4741 | case 0xa4: /* movsS */ |
| 4742 | case 0xa5: |
| 4743 | case 0xaa: /* stosS */ |
| 4744 | case 0xab: |
| 4745 | case 0x6c: /* insS */ |
| 4746 | case 0x6d: |
| 4747 | regcache_raw_read_unsigned (ir.regcache, |
| 4748 | ir.regmap[X86_RECORD_RECX_REGNUM], |
| 4749 | &addr); |
| 4750 | if (addr) |
| 4751 | { |
| 4752 | ULONGEST es, ds; |
| 4753 | |
| 4754 | if ((opcode & 1) == 0) |
| 4755 | ir.ot = OT_BYTE; |
| 4756 | else |
| 4757 | ir.ot = ir.dflag + OT_WORD; |
| 4758 | regcache_raw_read_unsigned (ir.regcache, |
| 4759 | ir.regmap[X86_RECORD_REDI_REGNUM], |
| 4760 | &addr); |
| 4761 | |
| 4762 | regcache_raw_read_unsigned (ir.regcache, |
| 4763 | ir.regmap[X86_RECORD_ES_REGNUM], |
| 4764 | &es); |
| 4765 | regcache_raw_read_unsigned (ir.regcache, |
| 4766 | ir.regmap[X86_RECORD_DS_REGNUM], |
| 4767 | &ds); |
| 4768 | if (ir.aflag && (es != ds)) |
| 4769 | { |
| 4770 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ |
| 4771 | warning (_("Process record ignores the memory " |
| 4772 | "change of instruction at address %s " |
| 4773 | "because it can't get the value of the " |
| 4774 | "ES segment register."), |
| 4775 | paddress (gdbarch, ir.orig_addr)); |
| 4776 | } |
| 4777 | else |
| 4778 | { |
| 4779 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) |
| 4780 | return -1; |
| 4781 | } |
| 4782 | |
| 4783 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
| 4784 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
| 4785 | if (opcode == 0xa4 || opcode == 0xa5) |
| 4786 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
| 4787 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
| 4788 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4789 | } |
| 4790 | break; |
| 4791 | |
| 4792 | case 0xa6: /* cmpsS */ |
| 4793 | case 0xa7: |
| 4794 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
| 4795 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
| 4796 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
| 4797 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
| 4798 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4799 | break; |
| 4800 | |
| 4801 | case 0xac: /* lodsS */ |
| 4802 | case 0xad: |
| 4803 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 4804 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
| 4805 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
| 4806 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
| 4807 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4808 | break; |
| 4809 | |
| 4810 | case 0xae: /* scasS */ |
| 4811 | case 0xaf: |
| 4812 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
| 4813 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
| 4814 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
| 4815 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4816 | break; |
| 4817 | |
| 4818 | case 0x6e: /* outsS */ |
| 4819 | case 0x6f: |
| 4820 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
| 4821 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
| 4822 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
| 4823 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4824 | break; |
| 4825 | |
| 4826 | case 0xe4: /* port I/O */ |
| 4827 | case 0xe5: |
| 4828 | case 0xec: |
| 4829 | case 0xed: |
| 4830 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4831 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 4832 | break; |
| 4833 | |
| 4834 | case 0xe6: |
| 4835 | case 0xe7: |
| 4836 | case 0xee: |
| 4837 | case 0xef: |
| 4838 | break; |
| 4839 | |
| 4840 | /* control */ |
| 4841 | case 0xc2: /* ret im */ |
| 4842 | case 0xc3: /* ret */ |
| 4843 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
| 4844 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4845 | break; |
| 4846 | |
| 4847 | case 0xca: /* lret im */ |
| 4848 | case 0xcb: /* lret */ |
| 4849 | case 0xcf: /* iret */ |
| 4850 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
| 4851 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
| 4852 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4853 | break; |
| 4854 | |
| 4855 | case 0xe8: /* call im */ |
| 4856 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
| 4857 | ir.dflag = 2; |
| 4858 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
| 4859 | return -1; |
| 4860 | break; |
| 4861 | |
| 4862 | case 0x9a: /* lcall im */ |
| 4863 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4864 | { |
| 4865 | ir.addr -= 1; |
| 4866 | goto no_support; |
| 4867 | } |
| 4868 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
| 4869 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
| 4870 | return -1; |
| 4871 | break; |
| 4872 | |
| 4873 | case 0xe9: /* jmp im */ |
| 4874 | case 0xea: /* ljmp im */ |
| 4875 | case 0xeb: /* jmp Jb */ |
| 4876 | case 0x70: /* jcc Jb */ |
| 4877 | case 0x71: |
| 4878 | case 0x72: |
| 4879 | case 0x73: |
| 4880 | case 0x74: |
| 4881 | case 0x75: |
| 4882 | case 0x76: |
| 4883 | case 0x77: |
| 4884 | case 0x78: |
| 4885 | case 0x79: |
| 4886 | case 0x7a: |
| 4887 | case 0x7b: |
| 4888 | case 0x7c: |
| 4889 | case 0x7d: |
| 4890 | case 0x7e: |
| 4891 | case 0x7f: |
| 4892 | case 0x0f80: /* jcc Jv */ |
| 4893 | case 0x0f81: |
| 4894 | case 0x0f82: |
| 4895 | case 0x0f83: |
| 4896 | case 0x0f84: |
| 4897 | case 0x0f85: |
| 4898 | case 0x0f86: |
| 4899 | case 0x0f87: |
| 4900 | case 0x0f88: |
| 4901 | case 0x0f89: |
| 4902 | case 0x0f8a: |
| 4903 | case 0x0f8b: |
| 4904 | case 0x0f8c: |
| 4905 | case 0x0f8d: |
| 4906 | case 0x0f8e: |
| 4907 | case 0x0f8f: |
| 4908 | break; |
| 4909 | |
| 4910 | case 0x0f90: /* setcc Gv */ |
| 4911 | case 0x0f91: |
| 4912 | case 0x0f92: |
| 4913 | case 0x0f93: |
| 4914 | case 0x0f94: |
| 4915 | case 0x0f95: |
| 4916 | case 0x0f96: |
| 4917 | case 0x0f97: |
| 4918 | case 0x0f98: |
| 4919 | case 0x0f99: |
| 4920 | case 0x0f9a: |
| 4921 | case 0x0f9b: |
| 4922 | case 0x0f9c: |
| 4923 | case 0x0f9d: |
| 4924 | case 0x0f9e: |
| 4925 | case 0x0f9f: |
| 4926 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4927 | ir.ot = OT_BYTE; |
| 4928 | if (i386_record_modrm (&ir)) |
| 4929 | return -1; |
| 4930 | if (ir.mod == 3) |
| 4931 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
| 4932 | : (ir.rm & 0x3)); |
| 4933 | else |
| 4934 | { |
| 4935 | if (i386_record_lea_modrm (&ir)) |
| 4936 | return -1; |
| 4937 | } |
| 4938 | break; |
| 4939 | |
| 4940 | case 0x0f40: /* cmov Gv, Ev */ |
| 4941 | case 0x0f41: |
| 4942 | case 0x0f42: |
| 4943 | case 0x0f43: |
| 4944 | case 0x0f44: |
| 4945 | case 0x0f45: |
| 4946 | case 0x0f46: |
| 4947 | case 0x0f47: |
| 4948 | case 0x0f48: |
| 4949 | case 0x0f49: |
| 4950 | case 0x0f4a: |
| 4951 | case 0x0f4b: |
| 4952 | case 0x0f4c: |
| 4953 | case 0x0f4d: |
| 4954 | case 0x0f4e: |
| 4955 | case 0x0f4f: |
| 4956 | if (i386_record_modrm (&ir)) |
| 4957 | return -1; |
| 4958 | ir.reg |= rex_r; |
| 4959 | if (ir.dflag == OT_BYTE) |
| 4960 | ir.reg &= 0x3; |
| 4961 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
| 4962 | break; |
| 4963 | |
| 4964 | /* flags */ |
| 4965 | case 0x9c: /* pushf */ |
| 4966 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4967 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
| 4968 | ir.dflag = 2; |
| 4969 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
| 4970 | return -1; |
| 4971 | break; |
| 4972 | |
| 4973 | case 0x9d: /* popf */ |
| 4974 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
| 4975 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4976 | break; |
| 4977 | |
| 4978 | case 0x9e: /* sahf */ |
| 4979 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4980 | { |
| 4981 | ir.addr -= 1; |
| 4982 | goto no_support; |
| 4983 | } |
| 4984 | case 0xf5: /* cmc */ |
| 4985 | case 0xf8: /* clc */ |
| 4986 | case 0xf9: /* stc */ |
| 4987 | case 0xfc: /* cld */ |
| 4988 | case 0xfd: /* std */ |
| 4989 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4990 | break; |
| 4991 | |
| 4992 | case 0x9f: /* lahf */ |
| 4993 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4994 | { |
| 4995 | ir.addr -= 1; |
| 4996 | goto no_support; |
| 4997 | } |
| 4998 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4999 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 5000 | break; |
| 5001 | |
| 5002 | /* bit operations */ |
| 5003 | case 0x0fba: /* bt/bts/btr/btc Gv, im */ |
| 5004 | ir.ot = ir.dflag + OT_WORD; |
| 5005 | if (i386_record_modrm (&ir)) |
| 5006 | return -1; |
| 5007 | if (ir.reg < 4) |
| 5008 | { |
| 5009 | ir.addr -= 2; |
| 5010 | opcode = opcode << 8 | ir.modrm; |
| 5011 | goto no_support; |
| 5012 | } |
| 5013 | if (ir.reg != 4) |
| 5014 | { |
| 5015 | if (ir.mod == 3) |
| 5016 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
| 5017 | else |
| 5018 | { |
| 5019 | if (i386_record_lea_modrm (&ir)) |
| 5020 | return -1; |
| 5021 | } |
| 5022 | } |
| 5023 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5024 | break; |
| 5025 | |
| 5026 | case 0x0fa3: /* bt Gv, Ev */ |
| 5027 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5028 | break; |
| 5029 | |
| 5030 | case 0x0fab: /* bts */ |
| 5031 | case 0x0fb3: /* btr */ |
| 5032 | case 0x0fbb: /* btc */ |
| 5033 | ir.ot = ir.dflag + OT_WORD; |
| 5034 | if (i386_record_modrm (&ir)) |
| 5035 | return -1; |
| 5036 | if (ir.mod == 3) |
| 5037 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
| 5038 | else |
| 5039 | { |
| 5040 | uint64_t addr64; |
| 5041 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
| 5042 | return -1; |
| 5043 | regcache_raw_read_unsigned (ir.regcache, |
| 5044 | ir.regmap[ir.reg | rex_r], |
| 5045 | &addr); |
| 5046 | switch (ir.dflag) |
| 5047 | { |
| 5048 | case 0: |
| 5049 | addr64 += ((int16_t) addr >> 4) << 4; |
| 5050 | break; |
| 5051 | case 1: |
| 5052 | addr64 += ((int32_t) addr >> 5) << 5; |
| 5053 | break; |
| 5054 | case 2: |
| 5055 | addr64 += ((int64_t) addr >> 6) << 6; |
| 5056 | break; |
| 5057 | } |
| 5058 | if (record_arch_list_add_mem (addr64, 1 << ir.ot)) |
| 5059 | return -1; |
| 5060 | if (i386_record_lea_modrm (&ir)) |
| 5061 | return -1; |
| 5062 | } |
| 5063 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5064 | break; |
| 5065 | |
| 5066 | case 0x0fbc: /* bsf */ |
| 5067 | case 0x0fbd: /* bsr */ |
| 5068 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
| 5069 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5070 | break; |
| 5071 | |
| 5072 | /* bcd */ |
| 5073 | case 0x27: /* daa */ |
| 5074 | case 0x2f: /* das */ |
| 5075 | case 0x37: /* aaa */ |
| 5076 | case 0x3f: /* aas */ |
| 5077 | case 0xd4: /* aam */ |
| 5078 | case 0xd5: /* aad */ |
| 5079 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 5080 | { |
| 5081 | ir.addr -= 1; |
| 5082 | goto no_support; |
| 5083 | } |
| 5084 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 5085 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5086 | break; |
| 5087 | |
| 5088 | /* misc */ |
| 5089 | case 0x90: /* nop */ |
| 5090 | if (prefixes & PREFIX_LOCK) |
| 5091 | { |
| 5092 | ir.addr -= 1; |
| 5093 | goto no_support; |
| 5094 | } |
| 5095 | break; |
| 5096 | |
| 5097 | case 0x9b: /* fwait */ |
| 5098 | if (target_read_memory (ir.addr, &opcode8, 1)) |
| 5099 | { |
| 5100 | if (record_debug) |
| 5101 | printf_unfiltered (_("Process record: error reading memory at " |
| 5102 | "addr 0x%s len = 1.\n"), |
| 5103 | paddress (gdbarch, ir.addr)); |
| 5104 | return -1; |
| 5105 | } |
| 5106 | opcode = (uint32_t) opcode8; |
| 5107 | ir.addr++; |
| 5108 | goto reswitch; |
| 5109 | break; |
| 5110 | |
| 5111 | /* XXX */ |
| 5112 | case 0xcc: /* int3 */ |
| 5113 | printf_unfiltered (_("Process record doesn't support instruction " |
| 5114 | "int3.\n")); |
| 5115 | ir.addr -= 1; |
| 5116 | goto no_support; |
| 5117 | break; |
| 5118 | |
| 5119 | /* XXX */ |
| 5120 | case 0xcd: /* int */ |
| 5121 | { |
| 5122 | int ret; |
| 5123 | uint8_t interrupt; |
| 5124 | if (target_read_memory (ir.addr, &interrupt, 1)) |
| 5125 | { |
| 5126 | if (record_debug) |
| 5127 | printf_unfiltered (_("Process record: error reading memory " |
| 5128 | "at addr %s len = 1.\n"), |
| 5129 | paddress (gdbarch, ir.addr)); |
| 5130 | return -1; |
| 5131 | } |
| 5132 | ir.addr++; |
| 5133 | if (interrupt != 0x80 |
| 5134 | || gdbarch_tdep (gdbarch)->i386_intx80_record == NULL) |
| 5135 | { |
| 5136 | printf_unfiltered (_("Process record doesn't support " |
| 5137 | "instruction int 0x%02x.\n"), |
| 5138 | interrupt); |
| 5139 | ir.addr -= 2; |
| 5140 | goto no_support; |
| 5141 | } |
| 5142 | ret = gdbarch_tdep (gdbarch)->i386_intx80_record (ir.regcache); |
| 5143 | if (ret) |
| 5144 | return ret; |
| 5145 | } |
| 5146 | break; |
| 5147 | |
| 5148 | /* XXX */ |
| 5149 | case 0xce: /* into */ |
| 5150 | printf_unfiltered (_("Process record doesn't support " |
| 5151 | "instruction into.\n")); |
| 5152 | ir.addr -= 1; |
| 5153 | goto no_support; |
| 5154 | break; |
| 5155 | |
| 5156 | case 0xfa: /* cli */ |
| 5157 | case 0xfb: /* sti */ |
| 5158 | break; |
| 5159 | |
| 5160 | case 0x62: /* bound */ |
| 5161 | printf_unfiltered (_("Process record doesn't support " |
| 5162 | "instruction bound.\n")); |
| 5163 | ir.addr -= 1; |
| 5164 | goto no_support; |
| 5165 | break; |
| 5166 | |
| 5167 | case 0x0fc8: /* bswap reg */ |
| 5168 | case 0x0fc9: |
| 5169 | case 0x0fca: |
| 5170 | case 0x0fcb: |
| 5171 | case 0x0fcc: |
| 5172 | case 0x0fcd: |
| 5173 | case 0x0fce: |
| 5174 | case 0x0fcf: |
| 5175 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
| 5176 | break; |
| 5177 | |
| 5178 | case 0xd6: /* salc */ |
| 5179 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 5180 | { |
| 5181 | ir.addr -= 1; |
| 5182 | goto no_support; |
| 5183 | } |
| 5184 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 5185 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5186 | break; |
| 5187 | |
| 5188 | case 0xe0: /* loopnz */ |
| 5189 | case 0xe1: /* loopz */ |
| 5190 | case 0xe2: /* loop */ |
| 5191 | case 0xe3: /* jecxz */ |
| 5192 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
| 5193 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5194 | break; |
| 5195 | |
| 5196 | case 0x0f30: /* wrmsr */ |
| 5197 | printf_unfiltered (_("Process record doesn't support " |
| 5198 | "instruction wrmsr.\n")); |
| 5199 | ir.addr -= 2; |
| 5200 | goto no_support; |
| 5201 | break; |
| 5202 | |
| 5203 | case 0x0f32: /* rdmsr */ |
| 5204 | printf_unfiltered (_("Process record doesn't support " |
| 5205 | "instruction rdmsr.\n")); |
| 5206 | ir.addr -= 2; |
| 5207 | goto no_support; |
| 5208 | break; |
| 5209 | |
| 5210 | case 0x0f31: /* rdtsc */ |
| 5211 | printf_unfiltered (_("Process record doesn't support " |
| 5212 | "instruction rdtsc.\n")); |
| 5213 | ir.addr -= 2; |
| 5214 | goto no_support; |
| 5215 | break; |
| 5216 | |
| 5217 | case 0x0f34: /* sysenter */ |
| 5218 | { |
| 5219 | int ret; |
| 5220 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 5221 | { |
| 5222 | ir.addr -= 2; |
| 5223 | goto no_support; |
| 5224 | } |
| 5225 | if (gdbarch_tdep (gdbarch)->i386_sysenter_record == NULL) |
| 5226 | { |
| 5227 | printf_unfiltered (_("Process record doesn't support " |
| 5228 | "instruction sysenter.\n")); |
| 5229 | ir.addr -= 2; |
| 5230 | goto no_support; |
| 5231 | } |
| 5232 | ret = gdbarch_tdep (gdbarch)->i386_sysenter_record (ir.regcache); |
| 5233 | if (ret) |
| 5234 | return ret; |
| 5235 | } |
| 5236 | break; |
| 5237 | |
| 5238 | case 0x0f35: /* sysexit */ |
| 5239 | printf_unfiltered (_("Process record doesn't support " |
| 5240 | "instruction sysexit.\n")); |
| 5241 | ir.addr -= 2; |
| 5242 | goto no_support; |
| 5243 | break; |
| 5244 | |
| 5245 | case 0x0f05: /* syscall */ |
| 5246 | { |
| 5247 | int ret; |
| 5248 | if (gdbarch_tdep (gdbarch)->i386_syscall_record == NULL) |
| 5249 | { |
| 5250 | printf_unfiltered (_("Process record doesn't support " |
| 5251 | "instruction syscall.\n")); |
| 5252 | ir.addr -= 2; |
| 5253 | goto no_support; |
| 5254 | } |
| 5255 | ret = gdbarch_tdep (gdbarch)->i386_syscall_record (ir.regcache); |
| 5256 | if (ret) |
| 5257 | return ret; |
| 5258 | } |
| 5259 | break; |
| 5260 | |
| 5261 | case 0x0f07: /* sysret */ |
| 5262 | printf_unfiltered (_("Process record doesn't support " |
| 5263 | "instruction sysret.\n")); |
| 5264 | ir.addr -= 2; |
| 5265 | goto no_support; |
| 5266 | break; |
| 5267 | |
| 5268 | case 0x0fa2: /* cpuid */ |
| 5269 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 5270 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
| 5271 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
| 5272 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); |
| 5273 | break; |
| 5274 | |
| 5275 | case 0xf4: /* hlt */ |
| 5276 | printf_unfiltered (_("Process record doesn't support " |
| 5277 | "instruction hlt.\n")); |
| 5278 | ir.addr -= 1; |
| 5279 | goto no_support; |
| 5280 | break; |
| 5281 | |
| 5282 | case 0x0f00: |
| 5283 | if (i386_record_modrm (&ir)) |
| 5284 | return -1; |
| 5285 | switch (ir.reg) |
| 5286 | { |
| 5287 | case 0: /* sldt */ |
| 5288 | case 1: /* str */ |
| 5289 | if (ir.mod == 3) |
| 5290 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
| 5291 | else |
| 5292 | { |
| 5293 | ir.ot = OT_WORD; |
| 5294 | if (i386_record_lea_modrm (&ir)) |
| 5295 | return -1; |
| 5296 | } |
| 5297 | break; |
| 5298 | case 2: /* lldt */ |
| 5299 | case 3: /* ltr */ |
| 5300 | break; |
| 5301 | case 4: /* verr */ |
| 5302 | case 5: /* verw */ |
| 5303 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5304 | break; |
| 5305 | default: |
| 5306 | ir.addr -= 3; |
| 5307 | opcode = opcode << 8 | ir.modrm; |
| 5308 | goto no_support; |
| 5309 | break; |
| 5310 | } |
| 5311 | break; |
| 5312 | |
| 5313 | case 0x0f01: |
| 5314 | if (i386_record_modrm (&ir)) |
| 5315 | return -1; |
| 5316 | switch (ir.reg) |
| 5317 | { |
| 5318 | case 0: /* sgdt */ |
| 5319 | { |
| 5320 | uint64_t addr64; |
| 5321 | |
| 5322 | if (ir.mod == 3) |
| 5323 | { |
| 5324 | ir.addr -= 3; |
| 5325 | opcode = opcode << 8 | ir.modrm; |
| 5326 | goto no_support; |
| 5327 | } |
| 5328 | if (ir.override >= 0) |
| 5329 | { |
| 5330 | warning (_("Process record ignores the memory " |
| 5331 | "change of instruction at " |
| 5332 | "address %s because it can't get " |
| 5333 | "the value of the segment " |
| 5334 | "register."), |
| 5335 | paddress (gdbarch, ir.orig_addr)); |
| 5336 | } |
| 5337 | else |
| 5338 | { |
| 5339 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
| 5340 | return -1; |
| 5341 | if (record_arch_list_add_mem (addr64, 2)) |
| 5342 | return -1; |
| 5343 | addr64 += 2; |
| 5344 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 5345 | { |
| 5346 | if (record_arch_list_add_mem (addr64, 8)) |
| 5347 | return -1; |
| 5348 | } |
| 5349 | else |
| 5350 | { |
| 5351 | if (record_arch_list_add_mem (addr64, 4)) |
| 5352 | return -1; |
| 5353 | } |
| 5354 | } |
| 5355 | } |
| 5356 | break; |
| 5357 | case 1: |
| 5358 | if (ir.mod == 3) |
| 5359 | { |
| 5360 | switch (ir.rm) |
| 5361 | { |
| 5362 | case 0: /* monitor */ |
| 5363 | break; |
| 5364 | case 1: /* mwait */ |
| 5365 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5366 | break; |
| 5367 | default: |
| 5368 | ir.addr -= 3; |
| 5369 | opcode = opcode << 8 | ir.modrm; |
| 5370 | goto no_support; |
| 5371 | break; |
| 5372 | } |
| 5373 | } |
| 5374 | else |
| 5375 | { |
| 5376 | /* sidt */ |
| 5377 | if (ir.override >= 0) |
| 5378 | { |
| 5379 | warning (_("Process record ignores the memory " |
| 5380 | "change of instruction at " |
| 5381 | "address %s because it can't get " |
| 5382 | "the value of the segment " |
| 5383 | "register."), |
| 5384 | paddress (gdbarch, ir.orig_addr)); |
| 5385 | } |
| 5386 | else |
| 5387 | { |
| 5388 | uint64_t addr64; |
| 5389 | |
| 5390 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
| 5391 | return -1; |
| 5392 | if (record_arch_list_add_mem (addr64, 2)) |
| 5393 | return -1; |
| 5394 | addr64 += 2; |
| 5395 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 5396 | { |
| 5397 | if (record_arch_list_add_mem (addr64, 8)) |
| 5398 | return -1; |
| 5399 | } |
| 5400 | else |
| 5401 | { |
| 5402 | if (record_arch_list_add_mem (addr64, 4)) |
| 5403 | return -1; |
| 5404 | } |
| 5405 | } |
| 5406 | } |
| 5407 | break; |
| 5408 | case 2: /* lgdt */ |
| 5409 | if (ir.mod == 3) |
| 5410 | { |
| 5411 | /* xgetbv */ |
| 5412 | if (ir.rm == 0) |
| 5413 | { |
| 5414 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 5415 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
| 5416 | break; |
| 5417 | } |
| 5418 | /* xsetbv */ |
| 5419 | else if (ir.rm == 1) |
| 5420 | break; |
| 5421 | } |
| 5422 | case 3: /* lidt */ |
| 5423 | if (ir.mod == 3) |
| 5424 | { |
| 5425 | ir.addr -= 3; |
| 5426 | opcode = opcode << 8 | ir.modrm; |
| 5427 | goto no_support; |
| 5428 | } |
| 5429 | break; |
| 5430 | case 4: /* smsw */ |
| 5431 | if (ir.mod == 3) |
| 5432 | { |
| 5433 | if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
| 5434 | return -1; |
| 5435 | } |
| 5436 | else |
| 5437 | { |
| 5438 | ir.ot = OT_WORD; |
| 5439 | if (i386_record_lea_modrm (&ir)) |
| 5440 | return -1; |
| 5441 | } |
| 5442 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5443 | break; |
| 5444 | case 6: /* lmsw */ |
| 5445 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5446 | break; |
| 5447 | case 7: /* invlpg */ |
| 5448 | if (ir.mod == 3) |
| 5449 | { |
| 5450 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) |
| 5451 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); |
| 5452 | else |
| 5453 | { |
| 5454 | ir.addr -= 3; |
| 5455 | opcode = opcode << 8 | ir.modrm; |
| 5456 | goto no_support; |
| 5457 | } |
| 5458 | } |
| 5459 | else |
| 5460 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5461 | break; |
| 5462 | default: |
| 5463 | ir.addr -= 3; |
| 5464 | opcode = opcode << 8 | ir.modrm; |
| 5465 | goto no_support; |
| 5466 | break; |
| 5467 | } |
| 5468 | break; |
| 5469 | |
| 5470 | case 0x0f08: /* invd */ |
| 5471 | case 0x0f09: /* wbinvd */ |
| 5472 | break; |
| 5473 | |
| 5474 | case 0x63: /* arpl */ |
| 5475 | if (i386_record_modrm (&ir)) |
| 5476 | return -1; |
| 5477 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
| 5478 | { |
| 5479 | I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] |
| 5480 | ? (ir.reg | rex_r) : ir.rm); |
| 5481 | } |
| 5482 | else |
| 5483 | { |
| 5484 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; |
| 5485 | if (i386_record_lea_modrm (&ir)) |
| 5486 | return -1; |
| 5487 | } |
| 5488 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) |
| 5489 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5490 | break; |
| 5491 | |
| 5492 | case 0x0f02: /* lar */ |
| 5493 | case 0x0f03: /* lsl */ |
| 5494 | if (i386_record_modrm (&ir)) |
| 5495 | return -1; |
| 5496 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
| 5497 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5498 | break; |
| 5499 | |
| 5500 | case 0x0f18: |
| 5501 | if (i386_record_modrm (&ir)) |
| 5502 | return -1; |
| 5503 | if (ir.mod == 3 && ir.reg == 3) |
| 5504 | { |
| 5505 | ir.addr -= 3; |
| 5506 | opcode = opcode << 8 | ir.modrm; |
| 5507 | goto no_support; |
| 5508 | } |
| 5509 | break; |
| 5510 | |
| 5511 | case 0x0f19: |
| 5512 | case 0x0f1a: |
| 5513 | case 0x0f1b: |
| 5514 | case 0x0f1c: |
| 5515 | case 0x0f1d: |
| 5516 | case 0x0f1e: |
| 5517 | case 0x0f1f: |
| 5518 | /* nop (multi byte) */ |
| 5519 | break; |
| 5520 | |
| 5521 | case 0x0f20: /* mov reg, crN */ |
| 5522 | case 0x0f22: /* mov crN, reg */ |
| 5523 | if (i386_record_modrm (&ir)) |
| 5524 | return -1; |
| 5525 | if ((ir.modrm & 0xc0) != 0xc0) |
| 5526 | { |
| 5527 | ir.addr -= 3; |
| 5528 | opcode = opcode << 8 | ir.modrm; |
| 5529 | goto no_support; |
| 5530 | } |
| 5531 | switch (ir.reg) |
| 5532 | { |
| 5533 | case 0: |
| 5534 | case 2: |
| 5535 | case 3: |
| 5536 | case 4: |
| 5537 | case 8: |
| 5538 | if (opcode & 2) |
| 5539 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5540 | else |
| 5541 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
| 5542 | break; |
| 5543 | default: |
| 5544 | ir.addr -= 3; |
| 5545 | opcode = opcode << 8 | ir.modrm; |
| 5546 | goto no_support; |
| 5547 | break; |
| 5548 | } |
| 5549 | break; |
| 5550 | |
| 5551 | case 0x0f21: /* mov reg, drN */ |
| 5552 | case 0x0f23: /* mov drN, reg */ |
| 5553 | if (i386_record_modrm (&ir)) |
| 5554 | return -1; |
| 5555 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 |
| 5556 | || ir.reg == 5 || ir.reg >= 8) |
| 5557 | { |
| 5558 | ir.addr -= 3; |
| 5559 | opcode = opcode << 8 | ir.modrm; |
| 5560 | goto no_support; |
| 5561 | } |
| 5562 | if (opcode & 2) |
| 5563 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5564 | else |
| 5565 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
| 5566 | break; |
| 5567 | |
| 5568 | case 0x0f06: /* clts */ |
| 5569 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5570 | break; |
| 5571 | |
| 5572 | /* MMX/SSE/SSE2/PNI support */ |
| 5573 | /* XXX */ |
| 5574 | |
| 5575 | default: |
| 5576 | if (opcode > 0xff) |
| 5577 | ir.addr -= 2; |
| 5578 | else |
| 5579 | ir.addr -= 1; |
| 5580 | goto no_support; |
| 5581 | break; |
| 5582 | } |
| 5583 | |
| 5584 | /* In the future, maybe still need to deal with need_dasm. */ |
| 5585 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); |
| 5586 | if (record_arch_list_add_end ()) |
| 5587 | return -1; |
| 5588 | |
| 5589 | return 0; |
| 5590 | |
| 5591 | no_support: |
| 5592 | printf_unfiltered (_("Process record doesn't support instruction 0x%02x " |
| 5593 | "at address %s.\n"), |
| 5594 | (unsigned int) (opcode), paddress (gdbarch, ir.addr)); |
| 5595 | return -1; |
| 5596 | } |
| 5597 | |
| 5598 | static const int i386_record_regmap[] = |
| 5599 | { |
| 5600 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, |
| 5601 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, |
| 5602 | 0, 0, 0, 0, 0, 0, 0, 0, |
| 5603 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, |
| 5604 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM |
| 5605 | }; |
| 5606 | |
| 5607 | /* Check that the given address appears suitable for a fast |
| 5608 | tracepoint, which on x86 means that we need an instruction of at |
| 5609 | least 5 bytes, so that we can overwrite it with a 4-byte-offset |
| 5610 | jump and not have to worry about program jumps to an address in the |
| 5611 | middle of the tracepoint jump. Returns 1 if OK, and writes a size |
| 5612 | of instruction to replace, and 0 if not, plus an explanatory |
| 5613 | string. */ |
| 5614 | |
| 5615 | static int |
| 5616 | i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, |
| 5617 | CORE_ADDR addr, int *isize, char **msg) |
| 5618 | { |
| 5619 | int len, jumplen; |
| 5620 | static struct ui_file *gdb_null = NULL; |
| 5621 | |
| 5622 | /* This is based on the target agent using a 4-byte relative jump. |
| 5623 | Alternate future possibilities include 8-byte offset for x86-84, |
| 5624 | or 3-byte jumps if the program has trampoline space close by. */ |
| 5625 | jumplen = 5; |
| 5626 | |
| 5627 | /* Dummy file descriptor for the disassembler. */ |
| 5628 | if (!gdb_null) |
| 5629 | gdb_null = ui_file_new (); |
| 5630 | |
| 5631 | /* Check for fit. */ |
| 5632 | len = gdb_print_insn (gdbarch, addr, gdb_null, NULL); |
| 5633 | if (len < jumplen) |
| 5634 | { |
| 5635 | /* Return a bit of target-specific detail to add to the caller's |
| 5636 | generic failure message. */ |
| 5637 | if (msg) |
| 5638 | *msg = xstrprintf (_("; instruction is only %d bytes long, need at least %d bytes for the jump"), |
| 5639 | len, jumplen); |
| 5640 | return 0; |
| 5641 | } |
| 5642 | |
| 5643 | if (isize) |
| 5644 | *isize = len; |
| 5645 | if (msg) |
| 5646 | *msg = NULL; |
| 5647 | return 1; |
| 5648 | } |
| 5649 | |
| 5650 | static int |
| 5651 | i386_validate_tdesc_p (struct gdbarch_tdep *tdep, |
| 5652 | struct tdesc_arch_data *tdesc_data) |
| 5653 | { |
| 5654 | const struct target_desc *tdesc = tdep->tdesc; |
| 5655 | const struct tdesc_feature *feature_core, *feature_vector; |
| 5656 | int i, num_regs, valid_p; |
| 5657 | |
| 5658 | if (! tdesc_has_registers (tdesc)) |
| 5659 | return 0; |
| 5660 | |
| 5661 | /* Get core registers. */ |
| 5662 | feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); |
| 5663 | |
| 5664 | /* Get SSE registers. */ |
| 5665 | feature_vector = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); |
| 5666 | |
| 5667 | if (feature_core == NULL || feature_vector == NULL) |
| 5668 | return 0; |
| 5669 | |
| 5670 | valid_p = 1; |
| 5671 | |
| 5672 | num_regs = tdep->num_core_regs; |
| 5673 | for (i = 0; i < num_regs; i++) |
| 5674 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, |
| 5675 | tdep->register_names[i]); |
| 5676 | |
| 5677 | /* Need to include %mxcsr, so add one. */ |
| 5678 | num_regs += tdep->num_xmm_regs + 1; |
| 5679 | for (; i < num_regs; i++) |
| 5680 | valid_p &= tdesc_numbered_register (feature_vector, tdesc_data, i, |
| 5681 | tdep->register_names[i]); |
| 5682 | |
| 5683 | return valid_p; |
| 5684 | } |
| 5685 | |
| 5686 | \f |
| 5687 | static struct gdbarch * |
| 5688 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 5689 | { |
| 5690 | struct gdbarch_tdep *tdep; |
| 5691 | struct gdbarch *gdbarch; |
| 5692 | struct tdesc_arch_data *tdesc_data; |
| 5693 | const struct target_desc *tdesc; |
| 5694 | int mm0_regnum; |
| 5695 | |
| 5696 | /* If there is already a candidate, use it. */ |
| 5697 | arches = gdbarch_list_lookup_by_info (arches, &info); |
| 5698 | if (arches != NULL) |
| 5699 | return arches->gdbarch; |
| 5700 | |
| 5701 | /* Allocate space for the new architecture. */ |
| 5702 | tdep = XCALLOC (1, struct gdbarch_tdep); |
| 5703 | gdbarch = gdbarch_alloc (&info, tdep); |
| 5704 | |
| 5705 | /* General-purpose registers. */ |
| 5706 | tdep->gregset = NULL; |
| 5707 | tdep->gregset_reg_offset = NULL; |
| 5708 | tdep->gregset_num_regs = I386_NUM_GREGS; |
| 5709 | tdep->sizeof_gregset = 0; |
| 5710 | |
| 5711 | /* Floating-point registers. */ |
| 5712 | tdep->fpregset = NULL; |
| 5713 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; |
| 5714 | |
| 5715 | /* The default settings include the FPU registers, the MMX registers |
| 5716 | and the SSE registers. This can be overridden for a specific ABI |
| 5717 | by adjusting the members `st0_regnum', `mm0_regnum' and |
| 5718 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers |
| 5719 | will show up in the output of "info all-registers". Ideally we |
| 5720 | should try to autodetect whether they are available, such that we |
| 5721 | can prevent "info all-registers" from displaying registers that |
| 5722 | aren't available. |
| 5723 | |
| 5724 | NOTE: kevinb/2003-07-13: ... if it's a choice between printing |
| 5725 | [the SSE registers] always (even when they don't exist) or never |
| 5726 | showing them to the user (even when they do exist), I prefer the |
| 5727 | former over the latter. */ |
| 5728 | |
| 5729 | tdep->st0_regnum = I386_ST0_REGNUM; |
| 5730 | |
| 5731 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ |
| 5732 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; |
| 5733 | |
| 5734 | tdep->jb_pc_offset = -1; |
| 5735 | tdep->struct_return = pcc_struct_return; |
| 5736 | tdep->sigtramp_start = 0; |
| 5737 | tdep->sigtramp_end = 0; |
| 5738 | tdep->sigtramp_p = i386_sigtramp_p; |
| 5739 | tdep->sigcontext_addr = NULL; |
| 5740 | tdep->sc_reg_offset = NULL; |
| 5741 | tdep->sc_pc_offset = -1; |
| 5742 | tdep->sc_sp_offset = -1; |
| 5743 | |
| 5744 | tdep->record_regmap = i386_record_regmap; |
| 5745 | |
| 5746 | /* The format used for `long double' on almost all i386 targets is |
| 5747 | the i387 extended floating-point format. In fact, of all targets |
| 5748 | in the GCC 2.95 tree, only OSF/1 does it different, and insists |
| 5749 | on having a `long double' that's not `long' at all. */ |
| 5750 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); |
| 5751 | |
| 5752 | /* Although the i387 extended floating-point has only 80 significant |
| 5753 | bits, a `long double' actually takes up 96, probably to enforce |
| 5754 | alignment. */ |
| 5755 | set_gdbarch_long_double_bit (gdbarch, 96); |
| 5756 | |
| 5757 | /* Register numbers of various important registers. */ |
| 5758 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ |
| 5759 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ |
| 5760 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ |
| 5761 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ |
| 5762 | |
| 5763 | /* NOTE: kettenis/20040418: GCC does have two possible register |
| 5764 | numbering schemes on the i386: dbx and SVR4. These schemes |
| 5765 | differ in how they number %ebp, %esp, %eflags, and the |
| 5766 | floating-point registers, and are implemented by the arrays |
| 5767 | dbx_register_map[] and svr4_dbx_register_map in |
| 5768 | gcc/config/i386.c. GCC also defines a third numbering scheme in |
| 5769 | gcc/config/i386.c, which it designates as the "default" register |
| 5770 | map used in 64bit mode. This last register numbering scheme is |
| 5771 | implemented in dbx64_register_map, and is used for AMD64; see |
| 5772 | amd64-tdep.c. |
| 5773 | |
| 5774 | Currently, each GCC i386 target always uses the same register |
| 5775 | numbering scheme across all its supported debugging formats |
| 5776 | i.e. SDB (COFF), stabs and DWARF 2. This is because |
| 5777 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the |
| 5778 | DBX_REGISTER_NUMBER macro which is defined by each target's |
| 5779 | respective config header in a manner independent of the requested |
| 5780 | output debugging format. |
| 5781 | |
| 5782 | This does not match the arrangement below, which presumes that |
| 5783 | the SDB and stabs numbering schemes differ from the DWARF and |
| 5784 | DWARF 2 ones. The reason for this arrangement is that it is |
| 5785 | likely to get the numbering scheme for the target's |
| 5786 | default/native debug format right. For targets where GCC is the |
| 5787 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for |
| 5788 | targets where the native toolchain uses a different numbering |
| 5789 | scheme for a particular debug format (stabs-in-ELF on Solaris) |
| 5790 | the defaults below will have to be overridden, like |
| 5791 | i386_elf_init_abi() does. */ |
| 5792 | |
| 5793 | /* Use the dbx register numbering scheme for stabs and COFF. */ |
| 5794 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); |
| 5795 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); |
| 5796 | |
| 5797 | /* Use the SVR4 register numbering scheme for DWARF 2. */ |
| 5798 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); |
| 5799 | |
| 5800 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to |
| 5801 | be in use on any of the supported i386 targets. */ |
| 5802 | |
| 5803 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); |
| 5804 | |
| 5805 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); |
| 5806 | |
| 5807 | /* Call dummy code. */ |
| 5808 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); |
| 5809 | |
| 5810 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); |
| 5811 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); |
| 5812 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); |
| 5813 | |
| 5814 | set_gdbarch_return_value (gdbarch, i386_return_value); |
| 5815 | |
| 5816 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); |
| 5817 | |
| 5818 | /* Stack grows downward. */ |
| 5819 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 5820 | |
| 5821 | set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); |
| 5822 | set_gdbarch_decr_pc_after_break (gdbarch, 1); |
| 5823 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); |
| 5824 | |
| 5825 | set_gdbarch_frame_args_skip (gdbarch, 8); |
| 5826 | |
| 5827 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
| 5828 | |
| 5829 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); |
| 5830 | |
| 5831 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); |
| 5832 | |
| 5833 | /* Add the i386 register groups. */ |
| 5834 | i386_add_reggroups (gdbarch); |
| 5835 | tdep->register_reggroup_p = i386_register_reggroup_p; |
| 5836 | |
| 5837 | /* Helper for function argument information. */ |
| 5838 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); |
| 5839 | |
| 5840 | /* Hook the function epilogue frame unwinder. This unwinder is |
| 5841 | appended to the list first, so that it supercedes the Dwarf |
| 5842 | unwinder in function epilogues (where the Dwarf unwinder |
| 5843 | currently fails). */ |
| 5844 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); |
| 5845 | |
| 5846 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended |
| 5847 | to the list before the prologue-based unwinders, so that Dwarf |
| 5848 | CFI info will be used if it is available. */ |
| 5849 | dwarf2_append_unwinders (gdbarch); |
| 5850 | |
| 5851 | frame_base_set_default (gdbarch, &i386_frame_base); |
| 5852 | |
| 5853 | /* Pseudo registers may be changed by amd64_init_abi. */ |
| 5854 | set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read); |
| 5855 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); |
| 5856 | |
| 5857 | set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); |
| 5858 | set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); |
| 5859 | |
| 5860 | /* The default ABI includes general-purpose registers, |
| 5861 | floating-point registers, and the SSE registers. */ |
| 5862 | set_gdbarch_num_regs (gdbarch, I386_SSE_NUM_REGS); |
| 5863 | |
| 5864 | /* Get the x86 target description from INFO. */ |
| 5865 | tdesc = info.target_desc; |
| 5866 | if (! tdesc_has_registers (tdesc)) |
| 5867 | tdesc = tdesc_i386; |
| 5868 | tdep->tdesc = tdesc; |
| 5869 | |
| 5870 | tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; |
| 5871 | tdep->register_names = i386_register_names; |
| 5872 | |
| 5873 | tdep->num_byte_regs = 8; |
| 5874 | tdep->num_word_regs = 8; |
| 5875 | tdep->num_dword_regs = 0; |
| 5876 | tdep->num_mmx_regs = 8; |
| 5877 | |
| 5878 | tdesc_data = tdesc_data_alloc (); |
| 5879 | |
| 5880 | /* Hook in ABI-specific overrides, if they have been registered. */ |
| 5881 | info.tdep_info = (void *) tdesc_data; |
| 5882 | gdbarch_init_osabi (info, gdbarch); |
| 5883 | |
| 5884 | /* Wire in pseudo registers. Number of pseudo registers may be |
| 5885 | changed. */ |
| 5886 | set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs |
| 5887 | + tdep->num_word_regs |
| 5888 | + tdep->num_dword_regs |
| 5889 | + tdep->num_mmx_regs)); |
| 5890 | |
| 5891 | /* Target description may be changed. */ |
| 5892 | tdesc = tdep->tdesc; |
| 5893 | |
| 5894 | if (!i386_validate_tdesc_p (tdep, tdesc_data)) |
| 5895 | { |
| 5896 | tdesc_data_cleanup (tdesc_data); |
| 5897 | xfree (tdep); |
| 5898 | gdbarch_free (gdbarch); |
| 5899 | return NULL; |
| 5900 | } |
| 5901 | |
| 5902 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
| 5903 | |
| 5904 | /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ |
| 5905 | set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); |
| 5906 | |
| 5907 | /* Make %al the first pseudo-register. */ |
| 5908 | tdep->al_regnum = gdbarch_num_regs (gdbarch); |
| 5909 | tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; |
| 5910 | |
| 5911 | mm0_regnum = tdep->ax_regnum + tdep->num_word_regs; |
| 5912 | if (tdep->num_dword_regs) |
| 5913 | { |
| 5914 | /* Support dword pseudo-registesr if it hasn't been disabled, */ |
| 5915 | tdep->eax_regnum = mm0_regnum; |
| 5916 | mm0_regnum = tdep->eax_regnum + tdep->num_dword_regs; |
| 5917 | } |
| 5918 | else |
| 5919 | tdep->eax_regnum = -1; |
| 5920 | |
| 5921 | if (tdep->num_mmx_regs != 0) |
| 5922 | { |
| 5923 | /* Support MMX pseudo-registesr if MMX hasn't been disabled, */ |
| 5924 | tdep->mm0_regnum = mm0_regnum; |
| 5925 | } |
| 5926 | else |
| 5927 | tdep->mm0_regnum = -1; |
| 5928 | |
| 5929 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
| 5930 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
| 5931 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); |
| 5932 | |
| 5933 | /* If we have a register mapping, enable the generic core file |
| 5934 | support, unless it has already been enabled. */ |
| 5935 | if (tdep->gregset_reg_offset |
| 5936 | && !gdbarch_regset_from_core_section_p (gdbarch)) |
| 5937 | set_gdbarch_regset_from_core_section (gdbarch, |
| 5938 | i386_regset_from_core_section); |
| 5939 | |
| 5940 | set_gdbarch_skip_permanent_breakpoint (gdbarch, |
| 5941 | i386_skip_permanent_breakpoint); |
| 5942 | |
| 5943 | set_gdbarch_fast_tracepoint_valid_at (gdbarch, |
| 5944 | i386_fast_tracepoint_valid_at); |
| 5945 | |
| 5946 | return gdbarch; |
| 5947 | } |
| 5948 | |
| 5949 | static enum gdb_osabi |
| 5950 | i386_coff_osabi_sniffer (bfd *abfd) |
| 5951 | { |
| 5952 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
| 5953 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) |
| 5954 | return GDB_OSABI_GO32; |
| 5955 | |
| 5956 | return GDB_OSABI_UNKNOWN; |
| 5957 | } |
| 5958 | \f |
| 5959 | |
| 5960 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
| 5961 | void _initialize_i386_tdep (void); |
| 5962 | |
| 5963 | void |
| 5964 | _initialize_i386_tdep (void) |
| 5965 | { |
| 5966 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
| 5967 | |
| 5968 | /* Add the variable that controls the disassembly flavor. */ |
| 5969 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
| 5970 | &disassembly_flavor, _("\ |
| 5971 | Set the disassembly flavor."), _("\ |
| 5972 | Show the disassembly flavor."), _("\ |
| 5973 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), |
| 5974 | NULL, |
| 5975 | NULL, /* FIXME: i18n: */ |
| 5976 | &setlist, &showlist); |
| 5977 | |
| 5978 | /* Add the variable that controls the convention for returning |
| 5979 | structs. */ |
| 5980 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
| 5981 | &struct_convention, _("\ |
| 5982 | Set the convention for returning small structs."), _("\ |
| 5983 | Show the convention for returning small structs."), _("\ |
| 5984 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ |
| 5985 | is \"default\"."), |
| 5986 | NULL, |
| 5987 | NULL, /* FIXME: i18n: */ |
| 5988 | &setlist, &showlist); |
| 5989 | |
| 5990 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, |
| 5991 | i386_coff_osabi_sniffer); |
| 5992 | |
| 5993 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
| 5994 | i386_svr4_init_abi); |
| 5995 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
| 5996 | i386_go32_init_abi); |
| 5997 | |
| 5998 | /* Initialize the i386-specific register groups. */ |
| 5999 | i386_init_reggroups (); |
| 6000 | |
| 6001 | /* Initialize the standard target descriptions. */ |
| 6002 | initialize_tdesc_i386 (); |
| 6003 | } |