| 1 | /* Target-dependent code for GDB, the GNU debugger. |
| 2 | Copyright 2001 |
| 3 | Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 2 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program; if not, write to the Free Software |
| 19 | Foundation, Inc., 59 Temple Place - Suite 330, |
| 20 | Boston, MA 02111-1307, USA. */ |
| 21 | |
| 22 | #ifndef I386_TDEP_H |
| 23 | #define I386_TDEP_H |
| 24 | |
| 25 | #define FPU_REG_RAW_SIZE 10 |
| 26 | |
| 27 | #define XMM0_REGNUM FIRST_XMM_REGNUM |
| 28 | #define FIRST_FPU_REGNUM FP0_REGNUM |
| 29 | #define LAST_FPU_REGNUM (gdbarch_tdep (current_gdbarch)->last_fpu_regnum) |
| 30 | #define FIRST_XMM_REGNUM (gdbarch_tdep (current_gdbarch)->first_xmm_regnum) |
| 31 | #define LAST_XMM_REGNUM (gdbarch_tdep (current_gdbarch)->last_xmm_regnum) |
| 32 | #define MXCSR_REGNUM (gdbarch_tdep (current_gdbarch)->mxcsr_regnum) |
| 33 | #define FIRST_FPU_CTRL_REGNUM (gdbarch_tdep (current_gdbarch)->first_fpu_ctrl_regnum) |
| 34 | #define LAST_FPU_CTRL_REGNUM (FIRST_FPU_CTRL_REGNUM + 7) |
| 35 | |
| 36 | /* All of these control registers (except for FCOFF and FDOFF) are |
| 37 | sixteen bits long (at most) in the FPU, but are zero-extended to |
| 38 | thirty-two bits in GDB's register file. This makes it easier to |
| 39 | compute the size of the control register file, and somewhat easier |
| 40 | to convert to and from the FSAVE instruction's 32-bit format. */ |
| 41 | /* FPU control word. */ |
| 42 | #define FCTRL_REGNUM (FIRST_FPU_CTRL_REGNUM) |
| 43 | /* FPU status word. */ |
| 44 | #define FSTAT_REGNUM (FIRST_FPU_CTRL_REGNUM + 1) |
| 45 | /* FPU register tag word. */ |
| 46 | #define FTAG_REGNUM (FIRST_FPU_CTRL_REGNUM + 2) |
| 47 | /* FPU instruction's code segment selector 16 bits, called "FPU Instruction |
| 48 | Pointer Selector" in the x86 manuals. */ |
| 49 | #define FCS_REGNUM (FIRST_FPU_CTRL_REGNUM + 3) |
| 50 | /* FPU instruction's offset within segment ("Fpu Code OFFset"). */ |
| 51 | #define FCOFF_REGNUM (FIRST_FPU_CTRL_REGNUM + 4) |
| 52 | /* FPU operand's data segment. */ |
| 53 | #define FDS_REGNUM (FIRST_FPU_CTRL_REGNUM + 5) |
| 54 | /* FPU operand's offset within segment. */ |
| 55 | #define FDOFF_REGNUM (FIRST_FPU_CTRL_REGNUM + 6) |
| 56 | /* FPU opcode, bottom eleven bits. */ |
| 57 | #define FOP_REGNUM (FIRST_FPU_CTRL_REGNUM + 7) |
| 58 | |
| 59 | /* i386 architecture specific information. */ |
| 60 | struct gdbarch_tdep |
| 61 | { |
| 62 | int last_fpu_regnum; |
| 63 | int first_xmm_regnum; |
| 64 | int last_xmm_regnum; |
| 65 | int mxcsr_regnum; /* Streaming SIMD Extension control/status. */ |
| 66 | int first_fpu_ctrl_regnum; |
| 67 | }; |
| 68 | |
| 69 | #define IS_FP_REGNUM(n) (FIRST_FPU_REGNUM <= (n) && (n) <= LAST_FPU_REGNUM) |
| 70 | #define IS_FPU_CTRL_REGNUM(n) (FIRST_FPU_CTRL_REGNUM <= (n) && (n) <= LAST_FPU_CTRL_REGNUM) |
| 71 | #define IS_SSE_REGNUM(n) (FIRST_XMM_REGNUM <= (n) && (n) <= LAST_XMM_REGNUM) |
| 72 | |
| 73 | #endif |