[deliverable/binutils-gdb.git] / gdb / i386-tdep.h

/* Target-dependent code for the i386.

   Copyright 2001, 2002, 2003
   Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 59 Temple Place - Suite 330,
   Boston, MA 02111-1307, USA.  */

#ifndef I386_TDEP_H
#define I386_TDEP_H

struct frame_info;
struct gdbarch;
struct reggroup;
struct regset;

/* GDB's i386 target supports both the 32-bit Intel Architecture
   (IA-32) and the 64-bit AMD x86-64 architecture.  Internally it uses
   a similar register layout for both.

   - General purpose registers
   - FPU data registers
   - FPU control registers
   - SSE data registers
   - SSE control register

   The general purpose registers for the x86-64 architecture are quite
   different from IA-32.  Therefore, the FP0_REGNUM target macro
   determines the register number at which the FPU data registers
   start.  The number of FPU data and control registers is the same
   for both architectures.  The number of SSE registers however,
   differs and is determined by the num_xmm_regs member of `struct
   gdbarch_tdep'.  */

/* Convention for returning structures.  */

enum struct_return
{
  pcc_struct_return,		/* Return "short" structures in memory.  */
  reg_struct_return		/* Return "short" structures in registers.  */
};

/* i386 architecture specific information.  */
struct gdbarch_tdep
{
  /* General-purpose registers.  */
  struct regset *gregset;
  int *gregset_reg_offset;
  int gregset_num_regs;
  size_t sizeof_gregset;

  /* Floating-point registers.  */
  struct regset *fpregset;
  size_t sizeof_fpregset;

  /* Register number for %st(0).  The register numbers for the other
     registers follow from this one.  Set this to -1 to indicate the
     absence of an FPU.  */
  int st0_regnum;

  /* Register number for %mm0.  Set this to -1 to indicate the absence
     of MMX support.  */
  int mm0_regnum;

  /* Number of SSE registers.  */
  int num_xmm_regs;

  /* Offset of saved PC in jmp_buf.  */
  int jb_pc_offset;

  /* Convention for returning structures.  */
  enum struct_return struct_return;

  /* Address range where sigtramp lives.  */
  CORE_ADDR sigtramp_start;
  CORE_ADDR sigtramp_end;

  /* Get address of sigcontext for sigtramp.  */
  CORE_ADDR (*sigcontext_addr) (struct frame_info *);

  /* Offset of registers in `struct sigcontext'.  */
  int *sc_reg_offset;
  int sc_num_regs;

  /* Offset of saved PC and SP in `struct sigcontext'.  Usage of these
     is deprecated, please use `sc_reg_offset' instead.  */
  int sc_pc_offset;
  int sc_sp_offset;
};

/* Floating-point registers.  */

/* All FPU control regusters (except for FIOFF and FOOFF) are 16-bit
   (at most) in the FPU, but are zero-extended to 32 bits in GDB's
   register cache.  */

/* "Generic" floating point control register.  */
#define FPC_REGNUM	(FP0_REGNUM + 8)

/* FPU control word.  */
#define FCTRL_REGNUM	FPC_REGNUM

/* FPU status word.  */
#define FSTAT_REGNUM	(FPC_REGNUM + 1)

/* FPU register tag word.  */
#define FTAG_REGNUM	(FPC_REGNUM + 2)

/* FPU instruction's code segment selector, called "FPU Instruction
   Pointer Selector" in the IA-32 manuals.  */
#define FISEG_REGNUM	(FPC_REGNUM + 3)

/* FPU instruction's offset within segment.  */
#define FIOFF_REGNUM	(FPC_REGNUM + 4)

/* FPU operand's data segment.  */
#define FOSEG_REGNUM	(FPC_REGNUM + 5)

/* FPU operand's offset within segment */
#define FOOFF_REGNUM	(FPC_REGNUM + 6)

/* FPU opcode, bottom eleven bits.  */
#define FOP_REGNUM	(FPC_REGNUM + 7)

/* Return non-zero if REGNUM matches the FP register and the FP
   register set is active.  */
extern int i386_fp_regnum_p (int regnum);
extern int i386_fpc_regnum_p (int regnum);

/* SSE registers.  */

/* First SSE data register.  */
#define XMM0_REGNUM	(FPC_REGNUM + 8)

/* SSE control/status register.  */
#define MXCSR_REGNUM \
  (XMM0_REGNUM + gdbarch_tdep (current_gdbarch)->num_xmm_regs)

/* Register numbers of various important registers.  */

enum i386_regnum
{
  I386_EAX_REGNUM,		/* %eax */
  I386_ECX_REGNUM,		/* %ecx */
  I386_EDX_REGNUM,		/* %edx */
  I386_EBX_REGNUM,		/* %ebx */
  I386_ESP_REGNUM,		/* %esp */
  I386_EBP_REGNUM,		/* %ebp */
  I386_ESI_REGNUM,		/* %esi */
  I386_EDI_REGNUM,		/* %edi */
  I386_EIP_REGNUM,		/* %eip */
  I386_EFLAGS_REGNUM,		/* %eflags */
  I386_ST0_REGNUM = 16,		/* %st(0) */
};

#define I386_NUM_GREGS	16
#define I386_NUM_FREGS	16
#define I386_NUM_XREGS  9

#define I386_SSE_NUM_REGS	(I386_NUM_GREGS + I386_NUM_FREGS \
				 + I386_NUM_XREGS)

/* Size of the largest register.  */
#define I386_MAX_REGISTER_SIZE	16

/* Functions exported from i386-tdep.c.  */
extern CORE_ADDR i386_pe_skip_trampoline_code (CORE_ADDR pc, char *name);
extern int i386_frameless_signal_p (struct frame_info *frame);

/* Return the name of register REG.  */
extern char const *i386_register_name (int reg);

/* Return non-zero if REGNUM is a member of the specified group.  */
extern int i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
				     struct reggroup *group);

/* Supply register REGNUM from the general-purpose register set REGSET
   to register cache REGCACHE.  If REGNUM is -1, do this for all
   registers in REGSET.  */
extern void i386_supply_gregset (const struct regset *regset,
				 struct regcache *regcache, int regnum,
				 const void *gregs, size_t len);

/* Return the appropriate register set for the core section identified
   by SECT_NAME and SECT_SIZE.  */
extern const struct regset *
  i386_regset_from_core_section (struct gdbarch *gdbarch,
				 const char *sect_name, size_t sect_size);

/* Initialize a basic ELF architecture variant.  */
extern void i386_elf_init_abi (struct gdbarch_info, struct gdbarch *);

/* Initialize a SVR4 architecture variant.  */
extern void i386_svr4_init_abi (struct gdbarch_info, struct gdbarch *);
\f

/* Functions and variables exported from i386bsd-tdep.c.  */

extern void i386bsd_init_abi (struct gdbarch_info, struct gdbarch *);
extern CORE_ADDR i386fbsd_sigtramp_start;
extern CORE_ADDR i386fbsd_sigtramp_end;
extern CORE_ADDR i386obsd_sigtramp_start;
extern CORE_ADDR i386obsd_sigtramp_end;
extern int i386fbsd4_sc_reg_offset[];
extern int i386fbsd_sc_reg_offset[];
extern int i386nbsd_sc_reg_offset[];
extern int i386obsd_sc_reg_offset[];
extern int i386bsd_sc_reg_offset[];

#endif /* i386-tdep.h */
Commit	Line	Data
	1	/* Target-dependent code for the i386.
	2
	3	Copyright 2001, 2002, 2003
	4	Free Software Foundation, Inc.
	5
	6	This file is part of GDB.
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 2 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program; if not, write to the Free Software
	20	Foundation, Inc., 59 Temple Place - Suite 330,
	21	Boston, MA 02111-1307, USA. */
	22
	23	#ifndef I386_TDEP_H
	24	#define I386_TDEP_H
	25
	26	struct frame_info;
	27	struct gdbarch;
	28	struct reggroup;
	29	struct regset;
	30
	31	/* GDB's i386 target supports both the 32-bit Intel Architecture
	32	(IA-32) and the 64-bit AMD x86-64 architecture. Internally it uses
	33	a similar register layout for both.
	34
	35	- General purpose registers
	36	- FPU data registers
	37	- FPU control registers
	38	- SSE data registers
	39	- SSE control register
	40
	41	The general purpose registers for the x86-64 architecture are quite
	42	different from IA-32. Therefore, the FP0_REGNUM target macro
	43	determines the register number at which the FPU data registers
	44	start. The number of FPU data and control registers is the same
	45	for both architectures. The number of SSE registers however,
	46	differs and is determined by the num_xmm_regs member of `struct
	47	gdbarch_tdep'. */
	48
	49	/* Convention for returning structures. */
	50
	51	enum struct_return
	52	{
	53	pcc_struct_return, /* Return "short" structures in memory. */
	54	reg_struct_return /* Return "short" structures in registers. */
	55	};
	56
	57	/* i386 architecture specific information. */
	58	struct gdbarch_tdep
	59	{
	60	/* General-purpose registers. */
	61	struct regset *gregset;
	62	int *gregset_reg_offset;
	63	int gregset_num_regs;
	64	size_t sizeof_gregset;
	65
	66	/* Floating-point registers. */
	67	struct regset *fpregset;
	68	size_t sizeof_fpregset;
	69
	70	/* Register number for %st(0). The register numbers for the other
	71	registers follow from this one. Set this to -1 to indicate the
	72	absence of an FPU. */
	73	int st0_regnum;
	74
	75	/* Register number for %mm0. Set this to -1 to indicate the absence
	76	of MMX support. */
	77	int mm0_regnum;
	78
	79	/* Number of SSE registers. */
	80	int num_xmm_regs;
	81
	82	/* Offset of saved PC in jmp_buf. */
	83	int jb_pc_offset;
	84
	85	/* Convention for returning structures. */
	86	enum struct_return struct_return;
	87
	88	/* Address range where sigtramp lives. */
	89	CORE_ADDR sigtramp_start;
	90	CORE_ADDR sigtramp_end;
	91
	92	/* Get address of sigcontext for sigtramp. */
	93	CORE_ADDR (sigcontext_addr) (struct frame_info );
	94
	95	/* Offset of registers in `struct sigcontext'. */
	96	int *sc_reg_offset;
	97	int sc_num_regs;
	98
	99	/* Offset of saved PC and SP in `struct sigcontext'. Usage of these
	100	is deprecated, please use `sc_reg_offset' instead. */
	101	int sc_pc_offset;
	102	int sc_sp_offset;
	103	};
	104
	105	/* Floating-point registers. */
	106
	107	/* All FPU control regusters (except for FIOFF and FOOFF) are 16-bit
	108	(at most) in the FPU, but are zero-extended to 32 bits in GDB's
	109	register cache. */
	110
	111	/* "Generic" floating point control register. */
	112	#define FPC_REGNUM (FP0_REGNUM + 8)
	113
	114	/* FPU control word. */
	115	#define FCTRL_REGNUM FPC_REGNUM
	116
	117	/* FPU status word. */
	118	#define FSTAT_REGNUM (FPC_REGNUM + 1)
	119
	120	/* FPU register tag word. */
	121	#define FTAG_REGNUM (FPC_REGNUM + 2)
	122
	123	/* FPU instruction's code segment selector, called "FPU Instruction
	124	Pointer Selector" in the IA-32 manuals. */
	125	#define FISEG_REGNUM (FPC_REGNUM + 3)
	126
	127	/* FPU instruction's offset within segment. */
	128	#define FIOFF_REGNUM (FPC_REGNUM + 4)
	129
	130	/* FPU operand's data segment. */
	131	#define FOSEG_REGNUM (FPC_REGNUM + 5)
	132
	133	/* FPU operand's offset within segment */
	134	#define FOOFF_REGNUM (FPC_REGNUM + 6)
	135
	136	/* FPU opcode, bottom eleven bits. */
	137	#define FOP_REGNUM (FPC_REGNUM + 7)
	138
	139	/* Return non-zero if REGNUM matches the FP register and the FP
	140	register set is active. */
	141	extern int i386_fp_regnum_p (int regnum);
	142	extern int i386_fpc_regnum_p (int regnum);
	143
	144	/* SSE registers. */
	145
	146	/* First SSE data register. */
	147	#define XMM0_REGNUM (FPC_REGNUM + 8)
	148
	149	/* SSE control/status register. */
	150	#define MXCSR_REGNUM \
	151	(XMM0_REGNUM + gdbarch_tdep (current_gdbarch)->num_xmm_regs)
	152
	153	/* Register numbers of various important registers. */
	154
	155	enum i386_regnum
	156	{
	157	I386_EAX_REGNUM, /* %eax */
	158	I386_ECX_REGNUM, /* %ecx */
	159	I386_EDX_REGNUM, /* %edx */
	160	I386_EBX_REGNUM, /* %ebx */
	161	I386_ESP_REGNUM, /* %esp */
	162	I386_EBP_REGNUM, /* %ebp */
	163	I386_ESI_REGNUM, /* %esi */
	164	I386_EDI_REGNUM, /* %edi */
	165	I386_EIP_REGNUM, /* %eip */
	166	I386_EFLAGS_REGNUM, /* %eflags */
	167	I386_ST0_REGNUM = 16, /* %st(0) */
	168	};
	169
	170	#define I386_NUM_GREGS 16
	171	#define I386_NUM_FREGS 16
	172	#define I386_NUM_XREGS 9
	173
	174	#define I386_SSE_NUM_REGS (I386_NUM_GREGS + I386_NUM_FREGS \
	175	+ I386_NUM_XREGS)
	176
	177	/* Size of the largest register. */
	178	#define I386_MAX_REGISTER_SIZE 16
	179
	180	/* Functions exported from i386-tdep.c. */
	181	extern CORE_ADDR i386_pe_skip_trampoline_code (CORE_ADDR pc, char *name);
	182	extern int i386_frameless_signal_p (struct frame_info *frame);
	183
	184	/* Return the name of register REG. */
	185	extern char const *i386_register_name (int reg);
	186
	187	/* Return non-zero if REGNUM is a member of the specified group. */
	188	extern int i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
	189	struct reggroup *group);
	190
	191	/* Supply register REGNUM from the general-purpose register set REGSET
	192	to register cache REGCACHE. If REGNUM is -1, do this for all
	193	registers in REGSET. */
	194	extern void i386_supply_gregset (const struct regset *regset,
	195	struct regcache *regcache, int regnum,
	196	const void *gregs, size_t len);
	197
	198	/* Return the appropriate register set for the core section identified
	199	by SECT_NAME and SECT_SIZE. */
	200	extern const struct regset *
	201	i386_regset_from_core_section (struct gdbarch *gdbarch,
	202	const char *sect_name, size_t sect_size);
	203
	204	/* Initialize a basic ELF architecture variant. */
	205	extern void i386_elf_init_abi (struct gdbarch_info, struct gdbarch *);
	206
	207	/* Initialize a SVR4 architecture variant. */
	208	extern void i386_svr4_init_abi (struct gdbarch_info, struct gdbarch *);
	209	\f
	210
	211	/* Functions and variables exported from i386bsd-tdep.c. */
	212
	213	extern void i386bsd_init_abi (struct gdbarch_info, struct gdbarch *);
	214	extern CORE_ADDR i386fbsd_sigtramp_start;
	215	extern CORE_ADDR i386fbsd_sigtramp_end;
	216	extern CORE_ADDR i386obsd_sigtramp_start;
	217	extern CORE_ADDR i386obsd_sigtramp_end;
	218	extern int i386fbsd4_sc_reg_offset[];
	219	extern int i386fbsd_sc_reg_offset[];
	220	extern int i386nbsd_sc_reg_offset[];
	221	extern int i386obsd_sc_reg_offset[];
	222	extern int i386bsd_sc_reg_offset[];
	223
	224	#endif /* i386-tdep.h */