| 1 | /* Intel 387 floating point stuff. |
| 2 | |
| 3 | Copyright (C) 1988-2018 Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 19 | |
| 20 | #include "defs.h" |
| 21 | #include "frame.h" |
| 22 | #include "gdbcore.h" |
| 23 | #include "inferior.h" |
| 24 | #include "language.h" |
| 25 | #include "regcache.h" |
| 26 | #include "target-float.h" |
| 27 | #include "value.h" |
| 28 | |
| 29 | #include "i386-tdep.h" |
| 30 | #include "i387-tdep.h" |
| 31 | #include "x86-xstate.h" |
| 32 | |
| 33 | /* Print the floating point number specified by RAW. */ |
| 34 | |
| 35 | static void |
| 36 | print_i387_value (struct gdbarch *gdbarch, |
| 37 | const gdb_byte *raw, struct ui_file *file) |
| 38 | { |
| 39 | /* We try to print 19 digits. The last digit may or may not contain |
| 40 | garbage, but we'd better print one too many. We need enough room |
| 41 | to print the value, 1 position for the sign, 1 for the decimal |
| 42 | point, 19 for the digits and 6 for the exponent adds up to 27. */ |
| 43 | const struct type *type = i387_ext_type (gdbarch); |
| 44 | std::string str = target_float_to_string (raw, type, " %-+27.19g"); |
| 45 | fprintf_filtered (file, "%s", str.c_str ()); |
| 46 | } |
| 47 | |
| 48 | /* Print the classification for the register contents RAW. */ |
| 49 | |
| 50 | static void |
| 51 | print_i387_ext (struct gdbarch *gdbarch, |
| 52 | const gdb_byte *raw, struct ui_file *file) |
| 53 | { |
| 54 | int sign; |
| 55 | int integer; |
| 56 | unsigned int exponent; |
| 57 | unsigned long fraction[2]; |
| 58 | |
| 59 | sign = raw[9] & 0x80; |
| 60 | integer = raw[7] & 0x80; |
| 61 | exponent = (((raw[9] & 0x7f) << 8) | raw[8]); |
| 62 | fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]); |
| 63 | fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16) |
| 64 | | (raw[5] << 8) | raw[4]); |
| 65 | |
| 66 | if (exponent == 0x7fff && integer) |
| 67 | { |
| 68 | if (fraction[0] == 0x00000000 && fraction[1] == 0x00000000) |
| 69 | /* Infinity. */ |
| 70 | fprintf_filtered (file, " %cInf", (sign ? '-' : '+')); |
| 71 | else if (sign && fraction[0] == 0x00000000 && fraction[1] == 0x40000000) |
| 72 | /* Real Indefinite (QNaN). */ |
| 73 | fputs_unfiltered (" Real Indefinite (QNaN)", file); |
| 74 | else if (fraction[1] & 0x40000000) |
| 75 | /* QNaN. */ |
| 76 | fputs_filtered (" QNaN", file); |
| 77 | else |
| 78 | /* SNaN. */ |
| 79 | fputs_filtered (" SNaN", file); |
| 80 | } |
| 81 | else if (exponent < 0x7fff && exponent > 0x0000 && integer) |
| 82 | /* Normal. */ |
| 83 | print_i387_value (gdbarch, raw, file); |
| 84 | else if (exponent == 0x0000) |
| 85 | { |
| 86 | /* Denormal or zero. */ |
| 87 | print_i387_value (gdbarch, raw, file); |
| 88 | |
| 89 | if (integer) |
| 90 | /* Pseudo-denormal. */ |
| 91 | fputs_filtered (" Pseudo-denormal", file); |
| 92 | else if (fraction[0] || fraction[1]) |
| 93 | /* Denormal. */ |
| 94 | fputs_filtered (" Denormal", file); |
| 95 | } |
| 96 | else |
| 97 | /* Unsupported. */ |
| 98 | fputs_filtered (" Unsupported", file); |
| 99 | } |
| 100 | |
| 101 | /* Print the status word STATUS. If STATUS_P is false, then STATUS |
| 102 | was unavailable. */ |
| 103 | |
| 104 | static void |
| 105 | print_i387_status_word (int status_p, |
| 106 | unsigned int status, struct ui_file *file) |
| 107 | { |
| 108 | fprintf_filtered (file, "Status Word: "); |
| 109 | if (!status_p) |
| 110 | { |
| 111 | fprintf_filtered (file, "%s\n", _("<unavailable>")); |
| 112 | return; |
| 113 | } |
| 114 | |
| 115 | fprintf_filtered (file, "%s", hex_string_custom (status, 4)); |
| 116 | fputs_filtered (" ", file); |
| 117 | fprintf_filtered (file, " %s", (status & 0x0001) ? "IE" : " "); |
| 118 | fprintf_filtered (file, " %s", (status & 0x0002) ? "DE" : " "); |
| 119 | fprintf_filtered (file, " %s", (status & 0x0004) ? "ZE" : " "); |
| 120 | fprintf_filtered (file, " %s", (status & 0x0008) ? "OE" : " "); |
| 121 | fprintf_filtered (file, " %s", (status & 0x0010) ? "UE" : " "); |
| 122 | fprintf_filtered (file, " %s", (status & 0x0020) ? "PE" : " "); |
| 123 | fputs_filtered (" ", file); |
| 124 | fprintf_filtered (file, " %s", (status & 0x0080) ? "ES" : " "); |
| 125 | fputs_filtered (" ", file); |
| 126 | fprintf_filtered (file, " %s", (status & 0x0040) ? "SF" : " "); |
| 127 | fputs_filtered (" ", file); |
| 128 | fprintf_filtered (file, " %s", (status & 0x0100) ? "C0" : " "); |
| 129 | fprintf_filtered (file, " %s", (status & 0x0200) ? "C1" : " "); |
| 130 | fprintf_filtered (file, " %s", (status & 0x0400) ? "C2" : " "); |
| 131 | fprintf_filtered (file, " %s", (status & 0x4000) ? "C3" : " "); |
| 132 | |
| 133 | fputs_filtered ("\n", file); |
| 134 | |
| 135 | fprintf_filtered (file, |
| 136 | " TOP: %d\n", ((status >> 11) & 7)); |
| 137 | } |
| 138 | |
| 139 | /* Print the control word CONTROL. If CONTROL_P is false, then |
| 140 | CONTROL was unavailable. */ |
| 141 | |
| 142 | static void |
| 143 | print_i387_control_word (int control_p, |
| 144 | unsigned int control, struct ui_file *file) |
| 145 | { |
| 146 | fprintf_filtered (file, "Control Word: "); |
| 147 | if (!control_p) |
| 148 | { |
| 149 | fprintf_filtered (file, "%s\n", _("<unavailable>")); |
| 150 | return; |
| 151 | } |
| 152 | |
| 153 | fprintf_filtered (file, "%s", hex_string_custom (control, 4)); |
| 154 | fputs_filtered (" ", file); |
| 155 | fprintf_filtered (file, " %s", (control & 0x0001) ? "IM" : " "); |
| 156 | fprintf_filtered (file, " %s", (control & 0x0002) ? "DM" : " "); |
| 157 | fprintf_filtered (file, " %s", (control & 0x0004) ? "ZM" : " "); |
| 158 | fprintf_filtered (file, " %s", (control & 0x0008) ? "OM" : " "); |
| 159 | fprintf_filtered (file, " %s", (control & 0x0010) ? "UM" : " "); |
| 160 | fprintf_filtered (file, " %s", (control & 0x0020) ? "PM" : " "); |
| 161 | |
| 162 | fputs_filtered ("\n", file); |
| 163 | |
| 164 | fputs_filtered (" PC: ", file); |
| 165 | switch ((control >> 8) & 3) |
| 166 | { |
| 167 | case 0: |
| 168 | fputs_filtered ("Single Precision (24-bits)\n", file); |
| 169 | break; |
| 170 | case 1: |
| 171 | fputs_filtered ("Reserved\n", file); |
| 172 | break; |
| 173 | case 2: |
| 174 | fputs_filtered ("Double Precision (53-bits)\n", file); |
| 175 | break; |
| 176 | case 3: |
| 177 | fputs_filtered ("Extended Precision (64-bits)\n", file); |
| 178 | break; |
| 179 | } |
| 180 | |
| 181 | fputs_filtered (" RC: ", file); |
| 182 | switch ((control >> 10) & 3) |
| 183 | { |
| 184 | case 0: |
| 185 | fputs_filtered ("Round to nearest\n", file); |
| 186 | break; |
| 187 | case 1: |
| 188 | fputs_filtered ("Round down\n", file); |
| 189 | break; |
| 190 | case 2: |
| 191 | fputs_filtered ("Round up\n", file); |
| 192 | break; |
| 193 | case 3: |
| 194 | fputs_filtered ("Round toward zero\n", file); |
| 195 | break; |
| 196 | } |
| 197 | } |
| 198 | |
| 199 | /* Print out the i387 floating point state. Note that we ignore FRAME |
| 200 | in the code below. That's OK since floating-point registers are |
| 201 | never saved on the stack. */ |
| 202 | |
| 203 | void |
| 204 | i387_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
| 205 | struct frame_info *frame, const char *args) |
| 206 | { |
| 207 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame)); |
| 208 | ULONGEST fctrl; |
| 209 | int fctrl_p; |
| 210 | ULONGEST fstat; |
| 211 | int fstat_p; |
| 212 | ULONGEST ftag; |
| 213 | int ftag_p; |
| 214 | ULONGEST fiseg; |
| 215 | int fiseg_p; |
| 216 | ULONGEST fioff; |
| 217 | int fioff_p; |
| 218 | ULONGEST foseg; |
| 219 | int foseg_p; |
| 220 | ULONGEST fooff; |
| 221 | int fooff_p; |
| 222 | ULONGEST fop; |
| 223 | int fop_p; |
| 224 | int fpreg; |
| 225 | int top; |
| 226 | |
| 227 | gdb_assert (gdbarch == get_frame_arch (frame)); |
| 228 | |
| 229 | fctrl_p = read_frame_register_unsigned (frame, |
| 230 | I387_FCTRL_REGNUM (tdep), &fctrl); |
| 231 | fstat_p = read_frame_register_unsigned (frame, |
| 232 | I387_FSTAT_REGNUM (tdep), &fstat); |
| 233 | ftag_p = read_frame_register_unsigned (frame, |
| 234 | I387_FTAG_REGNUM (tdep), &ftag); |
| 235 | fiseg_p = read_frame_register_unsigned (frame, |
| 236 | I387_FISEG_REGNUM (tdep), &fiseg); |
| 237 | fioff_p = read_frame_register_unsigned (frame, |
| 238 | I387_FIOFF_REGNUM (tdep), &fioff); |
| 239 | foseg_p = read_frame_register_unsigned (frame, |
| 240 | I387_FOSEG_REGNUM (tdep), &foseg); |
| 241 | fooff_p = read_frame_register_unsigned (frame, |
| 242 | I387_FOOFF_REGNUM (tdep), &fooff); |
| 243 | fop_p = read_frame_register_unsigned (frame, |
| 244 | I387_FOP_REGNUM (tdep), &fop); |
| 245 | |
| 246 | if (fstat_p) |
| 247 | { |
| 248 | top = ((fstat >> 11) & 7); |
| 249 | |
| 250 | for (fpreg = 7; fpreg >= 0; fpreg--) |
| 251 | { |
| 252 | struct value *regval; |
| 253 | int regnum; |
| 254 | int i; |
| 255 | int tag = -1; |
| 256 | |
| 257 | fprintf_filtered (file, "%sR%d: ", fpreg == top ? "=>" : " ", fpreg); |
| 258 | |
| 259 | if (ftag_p) |
| 260 | { |
| 261 | tag = (ftag >> (fpreg * 2)) & 3; |
| 262 | |
| 263 | switch (tag) |
| 264 | { |
| 265 | case 0: |
| 266 | fputs_filtered ("Valid ", file); |
| 267 | break; |
| 268 | case 1: |
| 269 | fputs_filtered ("Zero ", file); |
| 270 | break; |
| 271 | case 2: |
| 272 | fputs_filtered ("Special ", file); |
| 273 | break; |
| 274 | case 3: |
| 275 | fputs_filtered ("Empty ", file); |
| 276 | break; |
| 277 | } |
| 278 | } |
| 279 | else |
| 280 | fputs_filtered ("Unknown ", file); |
| 281 | |
| 282 | regnum = (fpreg + 8 - top) % 8 + I387_ST0_REGNUM (tdep); |
| 283 | regval = get_frame_register_value (frame, regnum); |
| 284 | |
| 285 | if (value_entirely_available (regval)) |
| 286 | { |
| 287 | const gdb_byte *raw = value_contents (regval); |
| 288 | |
| 289 | fputs_filtered ("0x", file); |
| 290 | for (i = 9; i >= 0; i--) |
| 291 | fprintf_filtered (file, "%02x", raw[i]); |
| 292 | |
| 293 | if (tag != -1 && tag != 3) |
| 294 | print_i387_ext (gdbarch, raw, file); |
| 295 | } |
| 296 | else |
| 297 | fprintf_filtered (file, "%s", _("<unavailable>")); |
| 298 | |
| 299 | fputs_filtered ("\n", file); |
| 300 | } |
| 301 | } |
| 302 | |
| 303 | fputs_filtered ("\n", file); |
| 304 | print_i387_status_word (fstat_p, fstat, file); |
| 305 | print_i387_control_word (fctrl_p, fctrl, file); |
| 306 | fprintf_filtered (file, "Tag Word: %s\n", |
| 307 | ftag_p ? hex_string_custom (ftag, 4) : _("<unavailable>")); |
| 308 | fprintf_filtered (file, "Instruction Pointer: %s:", |
| 309 | fiseg_p ? hex_string_custom (fiseg, 2) : _("<unavailable>")); |
| 310 | fprintf_filtered (file, "%s\n", |
| 311 | fioff_p ? hex_string_custom (fioff, 8) : _("<unavailable>")); |
| 312 | fprintf_filtered (file, "Operand Pointer: %s:", |
| 313 | foseg_p ? hex_string_custom (foseg, 2) : _("<unavailable>")); |
| 314 | fprintf_filtered (file, "%s\n", |
| 315 | fooff_p ? hex_string_custom (fooff, 8) : _("<unavailable>")); |
| 316 | fprintf_filtered (file, "Opcode: %s\n", |
| 317 | fop_p |
| 318 | ? (hex_string_custom (fop ? (fop | 0xd800) : 0, 4)) |
| 319 | : _("<unavailable>")); |
| 320 | } |
| 321 | \f |
| 322 | |
| 323 | /* Return nonzero if a value of type TYPE stored in register REGNUM |
| 324 | needs any special handling. */ |
| 325 | |
| 326 | int |
| 327 | i387_convert_register_p (struct gdbarch *gdbarch, int regnum, |
| 328 | struct type *type) |
| 329 | { |
| 330 | if (i386_fp_regnum_p (gdbarch, regnum)) |
| 331 | { |
| 332 | /* Floating point registers must be converted unless we are |
| 333 | accessing them in their hardware type or TYPE is not float. */ |
| 334 | if (type == i387_ext_type (gdbarch) |
| 335 | || TYPE_CODE (type) != TYPE_CODE_FLT) |
| 336 | return 0; |
| 337 | else |
| 338 | return 1; |
| 339 | } |
| 340 | |
| 341 | return 0; |
| 342 | } |
| 343 | |
| 344 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
| 345 | return its contents in TO. */ |
| 346 | |
| 347 | int |
| 348 | i387_register_to_value (struct frame_info *frame, int regnum, |
| 349 | struct type *type, gdb_byte *to, |
| 350 | int *optimizedp, int *unavailablep) |
| 351 | { |
| 352 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 353 | gdb_byte from[I386_MAX_REGISTER_SIZE]; |
| 354 | |
| 355 | gdb_assert (i386_fp_regnum_p (gdbarch, regnum)); |
| 356 | |
| 357 | /* We only support floating-point values. */ |
| 358 | if (TYPE_CODE (type) != TYPE_CODE_FLT) |
| 359 | { |
| 360 | warning (_("Cannot convert floating-point register value " |
| 361 | "to non-floating-point type.")); |
| 362 | *optimizedp = *unavailablep = 0; |
| 363 | return 0; |
| 364 | } |
| 365 | |
| 366 | /* Convert to TYPE. */ |
| 367 | if (!get_frame_register_bytes (frame, regnum, 0, |
| 368 | register_size (gdbarch, regnum), |
| 369 | from, optimizedp, unavailablep)) |
| 370 | return 0; |
| 371 | |
| 372 | target_float_convert (from, i387_ext_type (gdbarch), to, type); |
| 373 | *optimizedp = *unavailablep = 0; |
| 374 | return 1; |
| 375 | } |
| 376 | |
| 377 | /* Write the contents FROM of a value of type TYPE into register |
| 378 | REGNUM in frame FRAME. */ |
| 379 | |
| 380 | void |
| 381 | i387_value_to_register (struct frame_info *frame, int regnum, |
| 382 | struct type *type, const gdb_byte *from) |
| 383 | { |
| 384 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 385 | gdb_byte to[I386_MAX_REGISTER_SIZE]; |
| 386 | |
| 387 | gdb_assert (i386_fp_regnum_p (gdbarch, regnum)); |
| 388 | |
| 389 | /* We only support floating-point values. */ |
| 390 | if (TYPE_CODE (type) != TYPE_CODE_FLT) |
| 391 | { |
| 392 | warning (_("Cannot convert non-floating-point type " |
| 393 | "to floating-point register value.")); |
| 394 | return; |
| 395 | } |
| 396 | |
| 397 | /* Convert from TYPE. */ |
| 398 | target_float_convert (from, type, to, i387_ext_type (gdbarch)); |
| 399 | put_frame_register (frame, regnum, to); |
| 400 | } |
| 401 | \f |
| 402 | |
| 403 | /* Handle FSAVE and FXSAVE formats. */ |
| 404 | |
| 405 | /* At fsave_offset[REGNUM] you'll find the offset to the location in |
| 406 | the data structure used by the "fsave" instruction where GDB |
| 407 | register REGNUM is stored. */ |
| 408 | |
| 409 | static int fsave_offset[] = |
| 410 | { |
| 411 | 28 + 0 * 10, /* %st(0) ... */ |
| 412 | 28 + 1 * 10, |
| 413 | 28 + 2 * 10, |
| 414 | 28 + 3 * 10, |
| 415 | 28 + 4 * 10, |
| 416 | 28 + 5 * 10, |
| 417 | 28 + 6 * 10, |
| 418 | 28 + 7 * 10, /* ... %st(7). */ |
| 419 | 0, /* `fctrl' (16 bits). */ |
| 420 | 4, /* `fstat' (16 bits). */ |
| 421 | 8, /* `ftag' (16 bits). */ |
| 422 | 16, /* `fiseg' (16 bits). */ |
| 423 | 12, /* `fioff'. */ |
| 424 | 24, /* `foseg' (16 bits). */ |
| 425 | 20, /* `fooff'. */ |
| 426 | 18 /* `fop' (bottom 11 bits). */ |
| 427 | }; |
| 428 | |
| 429 | #define FSAVE_ADDR(tdep, fsave, regnum) \ |
| 430 | (fsave + fsave_offset[regnum - I387_ST0_REGNUM (tdep)]) |
| 431 | \f |
| 432 | |
| 433 | /* Fill register REGNUM in REGCACHE with the appropriate value from |
| 434 | *FSAVE. This function masks off any of the reserved bits in |
| 435 | *FSAVE. */ |
| 436 | |
| 437 | void |
| 438 | i387_supply_fsave (struct regcache *regcache, int regnum, const void *fsave) |
| 439 | { |
| 440 | struct gdbarch *gdbarch = regcache->arch (); |
| 441 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 442 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 443 | const gdb_byte *regs = (const gdb_byte *) fsave; |
| 444 | int i; |
| 445 | |
| 446 | gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); |
| 447 | |
| 448 | for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++) |
| 449 | if (regnum == -1 || regnum == i) |
| 450 | { |
| 451 | if (fsave == NULL) |
| 452 | { |
| 453 | regcache->raw_supply (i, NULL); |
| 454 | continue; |
| 455 | } |
| 456 | |
| 457 | /* Most of the FPU control registers occupy only 16 bits in the |
| 458 | fsave area. Give those a special treatment. */ |
| 459 | if (i >= I387_FCTRL_REGNUM (tdep) |
| 460 | && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep)) |
| 461 | { |
| 462 | gdb_byte val[4]; |
| 463 | |
| 464 | memcpy (val, FSAVE_ADDR (tdep, regs, i), 2); |
| 465 | val[2] = val[3] = 0; |
| 466 | if (i == I387_FOP_REGNUM (tdep)) |
| 467 | val[1] &= ((1 << 3) - 1); |
| 468 | regcache->raw_supply (i, val); |
| 469 | } |
| 470 | else |
| 471 | regcache->raw_supply (i, FSAVE_ADDR (tdep, regs, i)); |
| 472 | } |
| 473 | |
| 474 | /* Provide dummy values for the SSE registers. */ |
| 475 | for (i = I387_XMM0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++) |
| 476 | if (regnum == -1 || regnum == i) |
| 477 | regcache->raw_supply (i, NULL); |
| 478 | if (regnum == -1 || regnum == I387_MXCSR_REGNUM (tdep)) |
| 479 | { |
| 480 | gdb_byte buf[4]; |
| 481 | |
| 482 | store_unsigned_integer (buf, 4, byte_order, I387_MXCSR_INIT_VAL); |
| 483 | regcache->raw_supply (I387_MXCSR_REGNUM (tdep), buf); |
| 484 | } |
| 485 | } |
| 486 | |
| 487 | /* Fill register REGNUM (if it is a floating-point register) in *FSAVE |
| 488 | with the value from REGCACHE. If REGNUM is -1, do this for all |
| 489 | registers. This function doesn't touch any of the reserved bits in |
| 490 | *FSAVE. */ |
| 491 | |
| 492 | void |
| 493 | i387_collect_fsave (const struct regcache *regcache, int regnum, void *fsave) |
| 494 | { |
| 495 | struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); |
| 496 | gdb_byte *regs = (gdb_byte *) fsave; |
| 497 | int i; |
| 498 | |
| 499 | gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); |
| 500 | |
| 501 | for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++) |
| 502 | if (regnum == -1 || regnum == i) |
| 503 | { |
| 504 | /* Most of the FPU control registers occupy only 16 bits in |
| 505 | the fsave area. Give those a special treatment. */ |
| 506 | if (i >= I387_FCTRL_REGNUM (tdep) |
| 507 | && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep)) |
| 508 | { |
| 509 | gdb_byte buf[4]; |
| 510 | |
| 511 | regcache->raw_collect (i, buf); |
| 512 | |
| 513 | if (i == I387_FOP_REGNUM (tdep)) |
| 514 | { |
| 515 | /* The opcode occupies only 11 bits. Make sure we |
| 516 | don't touch the other bits. */ |
| 517 | buf[1] &= ((1 << 3) - 1); |
| 518 | buf[1] |= ((FSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1)); |
| 519 | } |
| 520 | memcpy (FSAVE_ADDR (tdep, regs, i), buf, 2); |
| 521 | } |
| 522 | else |
| 523 | regcache->raw_collect (i, FSAVE_ADDR (tdep, regs, i)); |
| 524 | } |
| 525 | } |
| 526 | \f |
| 527 | |
| 528 | /* At fxsave_offset[REGNUM] you'll find the offset to the location in |
| 529 | the data structure used by the "fxsave" instruction where GDB |
| 530 | register REGNUM is stored. */ |
| 531 | |
| 532 | static int fxsave_offset[] = |
| 533 | { |
| 534 | 32, /* %st(0) through ... */ |
| 535 | 48, |
| 536 | 64, |
| 537 | 80, |
| 538 | 96, |
| 539 | 112, |
| 540 | 128, |
| 541 | 144, /* ... %st(7) (80 bits each). */ |
| 542 | 0, /* `fctrl' (16 bits). */ |
| 543 | 2, /* `fstat' (16 bits). */ |
| 544 | 4, /* `ftag' (16 bits). */ |
| 545 | 12, /* `fiseg' (16 bits). */ |
| 546 | 8, /* `fioff'. */ |
| 547 | 20, /* `foseg' (16 bits). */ |
| 548 | 16, /* `fooff'. */ |
| 549 | 6, /* `fop' (bottom 11 bits). */ |
| 550 | 160 + 0 * 16, /* %xmm0 through ... */ |
| 551 | 160 + 1 * 16, |
| 552 | 160 + 2 * 16, |
| 553 | 160 + 3 * 16, |
| 554 | 160 + 4 * 16, |
| 555 | 160 + 5 * 16, |
| 556 | 160 + 6 * 16, |
| 557 | 160 + 7 * 16, |
| 558 | 160 + 8 * 16, |
| 559 | 160 + 9 * 16, |
| 560 | 160 + 10 * 16, |
| 561 | 160 + 11 * 16, |
| 562 | 160 + 12 * 16, |
| 563 | 160 + 13 * 16, |
| 564 | 160 + 14 * 16, |
| 565 | 160 + 15 * 16, /* ... %xmm15 (128 bits each). */ |
| 566 | }; |
| 567 | |
| 568 | #define FXSAVE_ADDR(tdep, fxsave, regnum) \ |
| 569 | (fxsave + fxsave_offset[regnum - I387_ST0_REGNUM (tdep)]) |
| 570 | |
| 571 | /* We made an unfortunate choice in putting %mxcsr after the SSE |
| 572 | registers %xmm0-%xmm7 instead of before, since it makes supporting |
| 573 | the registers %xmm8-%xmm15 on AMD64 a bit involved. Therefore we |
| 574 | don't include the offset for %mxcsr here above. */ |
| 575 | |
| 576 | #define FXSAVE_MXCSR_ADDR(fxsave) (fxsave + 24) |
| 577 | |
| 578 | static int i387_tag (const gdb_byte *raw); |
| 579 | \f |
| 580 | |
| 581 | /* Fill register REGNUM in REGCACHE with the appropriate |
| 582 | floating-point or SSE register value from *FXSAVE. This function |
| 583 | masks off any of the reserved bits in *FXSAVE. */ |
| 584 | |
| 585 | void |
| 586 | i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave) |
| 587 | { |
| 588 | struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); |
| 589 | const gdb_byte *regs = (const gdb_byte *) fxsave; |
| 590 | int i; |
| 591 | |
| 592 | gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); |
| 593 | gdb_assert (tdep->num_xmm_regs > 0); |
| 594 | |
| 595 | for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++) |
| 596 | if (regnum == -1 || regnum == i) |
| 597 | { |
| 598 | if (regs == NULL) |
| 599 | { |
| 600 | regcache->raw_supply (i, NULL); |
| 601 | continue; |
| 602 | } |
| 603 | |
| 604 | /* Most of the FPU control registers occupy only 16 bits in |
| 605 | the fxsave area. Give those a special treatment. */ |
| 606 | if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep) |
| 607 | && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep)) |
| 608 | { |
| 609 | gdb_byte val[4]; |
| 610 | |
| 611 | memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2); |
| 612 | val[2] = val[3] = 0; |
| 613 | if (i == I387_FOP_REGNUM (tdep)) |
| 614 | val[1] &= ((1 << 3) - 1); |
| 615 | else if (i== I387_FTAG_REGNUM (tdep)) |
| 616 | { |
| 617 | /* The fxsave area contains a simplified version of |
| 618 | the tag word. We have to look at the actual 80-bit |
| 619 | FP data to recreate the traditional i387 tag word. */ |
| 620 | |
| 621 | unsigned long ftag = 0; |
| 622 | int fpreg; |
| 623 | int top; |
| 624 | |
| 625 | top = ((FXSAVE_ADDR (tdep, regs, |
| 626 | I387_FSTAT_REGNUM (tdep)))[1] >> 3); |
| 627 | top &= 0x7; |
| 628 | |
| 629 | for (fpreg = 7; fpreg >= 0; fpreg--) |
| 630 | { |
| 631 | int tag; |
| 632 | |
| 633 | if (val[0] & (1 << fpreg)) |
| 634 | { |
| 635 | int thisreg = (fpreg + 8 - top) % 8 |
| 636 | + I387_ST0_REGNUM (tdep); |
| 637 | tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg)); |
| 638 | } |
| 639 | else |
| 640 | tag = 3; /* Empty */ |
| 641 | |
| 642 | ftag |= tag << (2 * fpreg); |
| 643 | } |
| 644 | val[0] = ftag & 0xff; |
| 645 | val[1] = (ftag >> 8) & 0xff; |
| 646 | } |
| 647 | regcache->raw_supply (i, val); |
| 648 | } |
| 649 | else |
| 650 | regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i)); |
| 651 | } |
| 652 | |
| 653 | if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1) |
| 654 | { |
| 655 | if (regs == NULL) |
| 656 | regcache->raw_supply (I387_MXCSR_REGNUM (tdep), NULL); |
| 657 | else |
| 658 | regcache->raw_supply (I387_MXCSR_REGNUM (tdep), |
| 659 | FXSAVE_MXCSR_ADDR (regs)); |
| 660 | } |
| 661 | } |
| 662 | |
| 663 | /* Fill register REGNUM (if it is a floating-point or SSE register) in |
| 664 | *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for |
| 665 | all registers. This function doesn't touch any of the reserved |
| 666 | bits in *FXSAVE. */ |
| 667 | |
| 668 | void |
| 669 | i387_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave) |
| 670 | { |
| 671 | struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); |
| 672 | gdb_byte *regs = (gdb_byte *) fxsave; |
| 673 | int i; |
| 674 | |
| 675 | gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); |
| 676 | gdb_assert (tdep->num_xmm_regs > 0); |
| 677 | |
| 678 | for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++) |
| 679 | if (regnum == -1 || regnum == i) |
| 680 | { |
| 681 | /* Most of the FPU control registers occupy only 16 bits in |
| 682 | the fxsave area. Give those a special treatment. */ |
| 683 | if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep) |
| 684 | && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep)) |
| 685 | { |
| 686 | gdb_byte buf[4]; |
| 687 | |
| 688 | regcache->raw_collect (i, buf); |
| 689 | |
| 690 | if (i == I387_FOP_REGNUM (tdep)) |
| 691 | { |
| 692 | /* The opcode occupies only 11 bits. Make sure we |
| 693 | don't touch the other bits. */ |
| 694 | buf[1] &= ((1 << 3) - 1); |
| 695 | buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1)); |
| 696 | } |
| 697 | else if (i == I387_FTAG_REGNUM (tdep)) |
| 698 | { |
| 699 | /* Converting back is much easier. */ |
| 700 | |
| 701 | unsigned short ftag; |
| 702 | int fpreg; |
| 703 | |
| 704 | ftag = (buf[1] << 8) | buf[0]; |
| 705 | buf[0] = 0; |
| 706 | buf[1] = 0; |
| 707 | |
| 708 | for (fpreg = 7; fpreg >= 0; fpreg--) |
| 709 | { |
| 710 | int tag = (ftag >> (fpreg * 2)) & 3; |
| 711 | |
| 712 | if (tag != 3) |
| 713 | buf[0] |= (1 << fpreg); |
| 714 | } |
| 715 | } |
| 716 | memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2); |
| 717 | } |
| 718 | else |
| 719 | regcache->raw_collect (i, FXSAVE_ADDR (tdep, regs, i)); |
| 720 | } |
| 721 | |
| 722 | if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1) |
| 723 | regcache->raw_collect (I387_MXCSR_REGNUM (tdep), |
| 724 | FXSAVE_MXCSR_ADDR (regs)); |
| 725 | } |
| 726 | |
| 727 | /* `xstate_bv' is at byte offset 512. */ |
| 728 | #define XSAVE_XSTATE_BV_ADDR(xsave) (xsave + 512) |
| 729 | |
| 730 | /* At xsave_avxh_offset[REGNUM] you'll find the offset to the location in |
| 731 | the upper 128bit of AVX register data structure used by the "xsave" |
| 732 | instruction where GDB register REGNUM is stored. */ |
| 733 | |
| 734 | static int xsave_avxh_offset[] = |
| 735 | { |
| 736 | 576 + 0 * 16, /* Upper 128bit of %ymm0 through ... */ |
| 737 | 576 + 1 * 16, |
| 738 | 576 + 2 * 16, |
| 739 | 576 + 3 * 16, |
| 740 | 576 + 4 * 16, |
| 741 | 576 + 5 * 16, |
| 742 | 576 + 6 * 16, |
| 743 | 576 + 7 * 16, |
| 744 | 576 + 8 * 16, |
| 745 | 576 + 9 * 16, |
| 746 | 576 + 10 * 16, |
| 747 | 576 + 11 * 16, |
| 748 | 576 + 12 * 16, |
| 749 | 576 + 13 * 16, |
| 750 | 576 + 14 * 16, |
| 751 | 576 + 15 * 16 /* Upper 128bit of ... %ymm15 (128 bits each). */ |
| 752 | }; |
| 753 | |
| 754 | #define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \ |
| 755 | (xsave + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)]) |
| 756 | |
| 757 | /* At xsave_ymm_avx512_offset[REGNUM] you'll find the offset to the location in |
| 758 | the upper 128bit of ZMM register data structure used by the "xsave" |
| 759 | instruction where GDB register REGNUM is stored. */ |
| 760 | |
| 761 | static int xsave_ymm_avx512_offset[] = |
| 762 | { |
| 763 | /* HI16_ZMM_area + 16 bytes + regnum* 64 bytes. */ |
| 764 | 1664 + 16 + 0 * 64, /* %ymm16 through... */ |
| 765 | 1664 + 16 + 1 * 64, |
| 766 | 1664 + 16 + 2 * 64, |
| 767 | 1664 + 16 + 3 * 64, |
| 768 | 1664 + 16 + 4 * 64, |
| 769 | 1664 + 16 + 5 * 64, |
| 770 | 1664 + 16 + 6 * 64, |
| 771 | 1664 + 16 + 7 * 64, |
| 772 | 1664 + 16 + 8 * 64, |
| 773 | 1664 + 16 + 9 * 64, |
| 774 | 1664 + 16 + 10 * 64, |
| 775 | 1664 + 16 + 11 * 64, |
| 776 | 1664 + 16 + 12 * 64, |
| 777 | 1664 + 16 + 13 * 64, |
| 778 | 1664 + 16 + 14 * 64, |
| 779 | 1664 + 16 + 15 * 64 /* ... %ymm31 (128 bits each). */ |
| 780 | }; |
| 781 | |
| 782 | #define XSAVE_YMM_AVX512_ADDR(tdep, xsave, regnum) \ |
| 783 | (xsave + xsave_ymm_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)]) |
| 784 | |
| 785 | static int xsave_xmm_avx512_offset[] = |
| 786 | { |
| 787 | 1664 + 0 * 64, /* %ymm16 through... */ |
| 788 | 1664 + 1 * 64, |
| 789 | 1664 + 2 * 64, |
| 790 | 1664 + 3 * 64, |
| 791 | 1664 + 4 * 64, |
| 792 | 1664 + 5 * 64, |
| 793 | 1664 + 6 * 64, |
| 794 | 1664 + 7 * 64, |
| 795 | 1664 + 8 * 64, |
| 796 | 1664 + 9 * 64, |
| 797 | 1664 + 10 * 64, |
| 798 | 1664 + 11 * 64, |
| 799 | 1664 + 12 * 64, |
| 800 | 1664 + 13 * 64, |
| 801 | 1664 + 14 * 64, |
| 802 | 1664 + 15 * 64 /* ... %ymm31 (128 bits each). */ |
| 803 | }; |
| 804 | |
| 805 | #define XSAVE_XMM_AVX512_ADDR(tdep, xsave, regnum) \ |
| 806 | (xsave + xsave_xmm_avx512_offset[regnum - I387_XMM16_REGNUM (tdep)]) |
| 807 | |
| 808 | static int xsave_mpx_offset[] = { |
| 809 | 960 + 0 * 16, /* bnd0r...bnd3r registers. */ |
| 810 | 960 + 1 * 16, |
| 811 | 960 + 2 * 16, |
| 812 | 960 + 3 * 16, |
| 813 | 1024 + 0 * 8, /* bndcfg ... bndstatus. */ |
| 814 | 1024 + 1 * 8, |
| 815 | }; |
| 816 | |
| 817 | #define XSAVE_MPX_ADDR(tdep, xsave, regnum) \ |
| 818 | (xsave + xsave_mpx_offset[regnum - I387_BND0R_REGNUM (tdep)]) |
| 819 | |
| 820 | /* At xsave_avx512__h_offset[REGNUM] you find the offset to the location |
| 821 | of the AVX512 opmask register data structure used by the "xsave" |
| 822 | instruction where GDB register REGNUM is stored. */ |
| 823 | |
| 824 | static int xsave_avx512_k_offset[] = |
| 825 | { |
| 826 | 1088 + 0 * 8, /* %k0 through... */ |
| 827 | 1088 + 1 * 8, |
| 828 | 1088 + 2 * 8, |
| 829 | 1088 + 3 * 8, |
| 830 | 1088 + 4 * 8, |
| 831 | 1088 + 5 * 8, |
| 832 | 1088 + 6 * 8, |
| 833 | 1088 + 7 * 8 /* %k7 (64 bits each). */ |
| 834 | }; |
| 835 | |
| 836 | #define XSAVE_AVX512_K_ADDR(tdep, xsave, regnum) \ |
| 837 | (xsave + xsave_avx512_k_offset[regnum - I387_K0_REGNUM (tdep)]) |
| 838 | |
| 839 | /* At xsave_avx512_zmm_h_offset[REGNUM] you find the offset to the location in |
| 840 | the upper 256bit of AVX512 ZMMH register data structure used by the "xsave" |
| 841 | instruction where GDB register REGNUM is stored. */ |
| 842 | |
| 843 | static int xsave_avx512_zmm_h_offset[] = |
| 844 | { |
| 845 | 1152 + 0 * 32, |
| 846 | 1152 + 1 * 32, /* Upper 256bit of %zmmh0 through... */ |
| 847 | 1152 + 2 * 32, |
| 848 | 1152 + 3 * 32, |
| 849 | 1152 + 4 * 32, |
| 850 | 1152 + 5 * 32, |
| 851 | 1152 + 6 * 32, |
| 852 | 1152 + 7 * 32, |
| 853 | 1152 + 8 * 32, |
| 854 | 1152 + 9 * 32, |
| 855 | 1152 + 10 * 32, |
| 856 | 1152 + 11 * 32, |
| 857 | 1152 + 12 * 32, |
| 858 | 1152 + 13 * 32, |
| 859 | 1152 + 14 * 32, |
| 860 | 1152 + 15 * 32, /* Upper 256bit of... %zmmh15 (256 bits each). */ |
| 861 | 1664 + 32 + 0 * 64, /* Upper 256bit of... %zmmh16 (256 bits each). */ |
| 862 | 1664 + 32 + 1 * 64, |
| 863 | 1664 + 32 + 2 * 64, |
| 864 | 1664 + 32 + 3 * 64, |
| 865 | 1664 + 32 + 4 * 64, |
| 866 | 1664 + 32 + 5 * 64, |
| 867 | 1664 + 32 + 6 * 64, |
| 868 | 1664 + 32 + 7 * 64, |
| 869 | 1664 + 32 + 8 * 64, |
| 870 | 1664 + 32 + 9 * 64, |
| 871 | 1664 + 32 + 10 * 64, |
| 872 | 1664 + 32 + 11 * 64, |
| 873 | 1664 + 32 + 12 * 64, |
| 874 | 1664 + 32 + 13 * 64, |
| 875 | 1664 + 32 + 14 * 64, |
| 876 | 1664 + 32 + 15 * 64 /* Upper 256bit of... %zmmh31 (256 bits each). */ |
| 877 | }; |
| 878 | |
| 879 | #define XSAVE_AVX512_ZMM_H_ADDR(tdep, xsave, regnum) \ |
| 880 | (xsave + xsave_avx512_zmm_h_offset[regnum - I387_ZMM0H_REGNUM (tdep)]) |
| 881 | |
| 882 | /* At xsave_pkeys_offset[REGNUM] you find the offset to the location |
| 883 | of the PKRU register data structure used by the "xsave" |
| 884 | instruction where GDB register REGNUM is stored. */ |
| 885 | |
| 886 | static int xsave_pkeys_offset[] = |
| 887 | { |
| 888 | 2688 + 0 * 8 /* %pkru (64 bits in XSTATE, 32-bit actually used by |
| 889 | instructions and applications). */ |
| 890 | }; |
| 891 | |
| 892 | #define XSAVE_PKEYS_ADDR(tdep, xsave, regnum) \ |
| 893 | (xsave + xsave_pkeys_offset[regnum - I387_PKRU_REGNUM (tdep)]) |
| 894 | |
| 895 | |
| 896 | /* Extract from XSAVE a bitset of the features that are available on the |
| 897 | target, but which have not yet been enabled. */ |
| 898 | |
| 899 | ULONGEST |
| 900 | i387_xsave_get_clear_bv (struct gdbarch *gdbarch, const void *xsave) |
| 901 | { |
| 902 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 903 | const gdb_byte *regs = (const gdb_byte *) xsave; |
| 904 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 905 | |
| 906 | /* Get `xstat_bv'. The supported bits in `xstat_bv' are 8 bytes. */ |
| 907 | ULONGEST xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs), |
| 908 | 8, byte_order); |
| 909 | |
| 910 | /* Clear part in vector registers if its bit in xstat_bv is zero. */ |
| 911 | ULONGEST clear_bv = (~(xstate_bv)) & tdep->xcr0; |
| 912 | |
| 913 | return clear_bv; |
| 914 | } |
| 915 | |
| 916 | /* Similar to i387_supply_fxsave, but use XSAVE extended state. */ |
| 917 | |
| 918 | void |
| 919 | i387_supply_xsave (struct regcache *regcache, int regnum, |
| 920 | const void *xsave) |
| 921 | { |
| 922 | struct gdbarch *gdbarch = regcache->arch (); |
| 923 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 924 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 925 | const gdb_byte *regs = (const gdb_byte *) xsave; |
| 926 | int i; |
| 927 | /* In 64-bit mode the split between "low" and "high" ZMM registers is at |
| 928 | ZMM16. Outside of 64-bit mode there are no "high" ZMM registers at all. |
| 929 | Precalculate the number to be used for the split point, with the all |
| 930 | registers in the "low" portion outside of 64-bit mode. */ |
| 931 | unsigned int zmm_endlo_regnum = I387_ZMM0H_REGNUM (tdep) |
| 932 | + std::min (tdep->num_zmm_regs, 16); |
| 933 | ULONGEST clear_bv; |
| 934 | static const gdb_byte zero[I386_MAX_REGISTER_SIZE] = { 0 }; |
| 935 | enum |
| 936 | { |
| 937 | none = 0x0, |
| 938 | x87 = 0x1, |
| 939 | sse = 0x2, |
| 940 | avxh = 0x4, |
| 941 | mpx = 0x8, |
| 942 | avx512_k = 0x10, |
| 943 | avx512_zmm_h = 0x20, |
| 944 | avx512_ymmh_avx512 = 0x40, |
| 945 | avx512_xmm_avx512 = 0x80, |
| 946 | pkeys = 0x100, |
| 947 | all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h |
| 948 | | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys |
| 949 | } regclass; |
| 950 | |
| 951 | gdb_assert (regs != NULL); |
| 952 | gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); |
| 953 | gdb_assert (tdep->num_xmm_regs > 0); |
| 954 | |
| 955 | if (regnum == -1) |
| 956 | regclass = all; |
| 957 | else if (regnum >= I387_PKRU_REGNUM (tdep) |
| 958 | && regnum < I387_PKEYSEND_REGNUM (tdep)) |
| 959 | regclass = pkeys; |
| 960 | else if (regnum >= I387_ZMM0H_REGNUM (tdep) |
| 961 | && regnum < I387_ZMMENDH_REGNUM (tdep)) |
| 962 | regclass = avx512_zmm_h; |
| 963 | else if (regnum >= I387_K0_REGNUM (tdep) |
| 964 | && regnum < I387_KEND_REGNUM (tdep)) |
| 965 | regclass = avx512_k; |
| 966 | else if (regnum >= I387_YMM16H_REGNUM (tdep) |
| 967 | && regnum < I387_YMMH_AVX512_END_REGNUM (tdep)) |
| 968 | regclass = avx512_ymmh_avx512; |
| 969 | else if (regnum >= I387_XMM16_REGNUM (tdep) |
| 970 | && regnum < I387_XMM_AVX512_END_REGNUM (tdep)) |
| 971 | regclass = avx512_xmm_avx512; |
| 972 | else if (regnum >= I387_YMM0H_REGNUM (tdep) |
| 973 | && regnum < I387_YMMENDH_REGNUM (tdep)) |
| 974 | regclass = avxh; |
| 975 | else if (regnum >= I387_BND0R_REGNUM (tdep) |
| 976 | && regnum < I387_MPXEND_REGNUM (tdep)) |
| 977 | regclass = mpx; |
| 978 | else if (regnum >= I387_XMM0_REGNUM (tdep) |
| 979 | && regnum < I387_MXCSR_REGNUM (tdep)) |
| 980 | regclass = sse; |
| 981 | else if (regnum >= I387_ST0_REGNUM (tdep) |
| 982 | && regnum < I387_FCTRL_REGNUM (tdep)) |
| 983 | regclass = x87; |
| 984 | else |
| 985 | regclass = none; |
| 986 | |
| 987 | clear_bv = i387_xsave_get_clear_bv (gdbarch, xsave); |
| 988 | |
| 989 | /* With the delayed xsave mechanism, in between the program |
| 990 | starting, and the program accessing the vector registers for the |
| 991 | first time, the register's values are invalid. The kernel |
| 992 | initializes register states to zero when they are set the first |
| 993 | time in a program. This means that from the user-space programs' |
| 994 | perspective, it's the same as if the registers have always been |
| 995 | zero from the start of the program. Therefore, the debugger |
| 996 | should provide the same illusion to the user. */ |
| 997 | |
| 998 | switch (regclass) |
| 999 | { |
| 1000 | case none: |
| 1001 | break; |
| 1002 | |
| 1003 | case pkeys: |
| 1004 | if ((clear_bv & X86_XSTATE_PKRU)) |
| 1005 | regcache->raw_supply (regnum, zero); |
| 1006 | else |
| 1007 | regcache->raw_supply (regnum, XSAVE_PKEYS_ADDR (tdep, regs, regnum)); |
| 1008 | return; |
| 1009 | |
| 1010 | case avx512_zmm_h: |
| 1011 | if ((clear_bv & (regnum < zmm_endlo_regnum ? X86_XSTATE_ZMM_H |
| 1012 | : X86_XSTATE_ZMM))) |
| 1013 | regcache->raw_supply (regnum, zero); |
| 1014 | else |
| 1015 | regcache->raw_supply (regnum, |
| 1016 | XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum)); |
| 1017 | return; |
| 1018 | |
| 1019 | case avx512_k: |
| 1020 | if ((clear_bv & X86_XSTATE_K)) |
| 1021 | regcache->raw_supply (regnum, zero); |
| 1022 | else |
| 1023 | regcache->raw_supply (regnum, XSAVE_AVX512_K_ADDR (tdep, regs, regnum)); |
| 1024 | return; |
| 1025 | |
| 1026 | case avx512_ymmh_avx512: |
| 1027 | if ((clear_bv & X86_XSTATE_ZMM)) |
| 1028 | regcache->raw_supply (regnum, zero); |
| 1029 | else |
| 1030 | regcache->raw_supply (regnum, |
| 1031 | XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum)); |
| 1032 | return; |
| 1033 | |
| 1034 | case avx512_xmm_avx512: |
| 1035 | if ((clear_bv & X86_XSTATE_ZMM)) |
| 1036 | regcache->raw_supply (regnum, zero); |
| 1037 | else |
| 1038 | regcache->raw_supply (regnum, |
| 1039 | XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum)); |
| 1040 | return; |
| 1041 | |
| 1042 | case avxh: |
| 1043 | if ((clear_bv & X86_XSTATE_AVX)) |
| 1044 | regcache->raw_supply (regnum, zero); |
| 1045 | else |
| 1046 | regcache->raw_supply (regnum, XSAVE_AVXH_ADDR (tdep, regs, regnum)); |
| 1047 | return; |
| 1048 | |
| 1049 | case mpx: |
| 1050 | if ((clear_bv & X86_XSTATE_BNDREGS)) |
| 1051 | regcache->raw_supply (regnum, zero); |
| 1052 | else |
| 1053 | regcache->raw_supply (regnum, XSAVE_MPX_ADDR (tdep, regs, regnum)); |
| 1054 | return; |
| 1055 | |
| 1056 | case sse: |
| 1057 | if ((clear_bv & X86_XSTATE_SSE)) |
| 1058 | regcache->raw_supply (regnum, zero); |
| 1059 | else |
| 1060 | regcache->raw_supply (regnum, FXSAVE_ADDR (tdep, regs, regnum)); |
| 1061 | return; |
| 1062 | |
| 1063 | case x87: |
| 1064 | if ((clear_bv & X86_XSTATE_X87)) |
| 1065 | regcache->raw_supply (regnum, zero); |
| 1066 | else |
| 1067 | regcache->raw_supply (regnum, FXSAVE_ADDR (tdep, regs, regnum)); |
| 1068 | return; |
| 1069 | |
| 1070 | case all: |
| 1071 | /* Handle PKEYS registers. */ |
| 1072 | if ((tdep->xcr0 & X86_XSTATE_PKRU)) |
| 1073 | { |
| 1074 | if ((clear_bv & X86_XSTATE_PKRU)) |
| 1075 | { |
| 1076 | for (i = I387_PKRU_REGNUM (tdep); |
| 1077 | i < I387_PKEYSEND_REGNUM (tdep); |
| 1078 | i++) |
| 1079 | regcache->raw_supply (i, zero); |
| 1080 | } |
| 1081 | else |
| 1082 | { |
| 1083 | for (i = I387_PKRU_REGNUM (tdep); |
| 1084 | i < I387_PKEYSEND_REGNUM (tdep); |
| 1085 | i++) |
| 1086 | regcache->raw_supply (i, XSAVE_PKEYS_ADDR (tdep, regs, i)); |
| 1087 | } |
| 1088 | } |
| 1089 | |
| 1090 | /* Handle the upper halves of the low 8/16 ZMM registers. */ |
| 1091 | if ((tdep->xcr0 & X86_XSTATE_ZMM_H)) |
| 1092 | { |
| 1093 | if ((clear_bv & X86_XSTATE_ZMM_H)) |
| 1094 | { |
| 1095 | for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++) |
| 1096 | regcache->raw_supply (i, zero); |
| 1097 | } |
| 1098 | else |
| 1099 | { |
| 1100 | for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++) |
| 1101 | regcache->raw_supply (i, |
| 1102 | XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i)); |
| 1103 | } |
| 1104 | } |
| 1105 | |
| 1106 | /* Handle AVX512 OpMask registers. */ |
| 1107 | if ((tdep->xcr0 & X86_XSTATE_K)) |
| 1108 | { |
| 1109 | if ((clear_bv & X86_XSTATE_K)) |
| 1110 | { |
| 1111 | for (i = I387_K0_REGNUM (tdep); |
| 1112 | i < I387_KEND_REGNUM (tdep); |
| 1113 | i++) |
| 1114 | regcache->raw_supply (i, zero); |
| 1115 | } |
| 1116 | else |
| 1117 | { |
| 1118 | for (i = I387_K0_REGNUM (tdep); |
| 1119 | i < I387_KEND_REGNUM (tdep); |
| 1120 | i++) |
| 1121 | regcache->raw_supply (i, XSAVE_AVX512_K_ADDR (tdep, regs, i)); |
| 1122 | } |
| 1123 | } |
| 1124 | |
| 1125 | /* Handle the upper 16 ZMM/YMM/XMM registers (if any). */ |
| 1126 | if ((tdep->xcr0 & X86_XSTATE_ZMM)) |
| 1127 | { |
| 1128 | if ((clear_bv & X86_XSTATE_ZMM)) |
| 1129 | { |
| 1130 | for (i = zmm_endlo_regnum; i < I387_ZMMENDH_REGNUM (tdep); i++) |
| 1131 | regcache->raw_supply (i, zero); |
| 1132 | for (i = I387_YMM16H_REGNUM (tdep); |
| 1133 | i < I387_YMMH_AVX512_END_REGNUM (tdep); |
| 1134 | i++) |
| 1135 | regcache->raw_supply (i, zero); |
| 1136 | for (i = I387_XMM16_REGNUM (tdep); |
| 1137 | i < I387_XMM_AVX512_END_REGNUM (tdep); |
| 1138 | i++) |
| 1139 | regcache->raw_supply (i, zero); |
| 1140 | } |
| 1141 | else |
| 1142 | { |
| 1143 | for (i = zmm_endlo_regnum; i < I387_ZMMENDH_REGNUM (tdep); i++) |
| 1144 | regcache->raw_supply (i, |
| 1145 | XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i)); |
| 1146 | for (i = I387_YMM16H_REGNUM (tdep); |
| 1147 | i < I387_YMMH_AVX512_END_REGNUM (tdep); |
| 1148 | i++) |
| 1149 | regcache->raw_supply (i, XSAVE_YMM_AVX512_ADDR (tdep, regs, i)); |
| 1150 | for (i = I387_XMM16_REGNUM (tdep); |
| 1151 | i < I387_XMM_AVX512_END_REGNUM (tdep); |
| 1152 | i++) |
| 1153 | regcache->raw_supply (i, XSAVE_XMM_AVX512_ADDR (tdep, regs, i)); |
| 1154 | } |
| 1155 | } |
| 1156 | /* Handle the upper YMM registers. */ |
| 1157 | if ((tdep->xcr0 & X86_XSTATE_AVX)) |
| 1158 | { |
| 1159 | if ((clear_bv & X86_XSTATE_AVX)) |
| 1160 | { |
| 1161 | for (i = I387_YMM0H_REGNUM (tdep); |
| 1162 | i < I387_YMMENDH_REGNUM (tdep); |
| 1163 | i++) |
| 1164 | regcache->raw_supply (i, zero); |
| 1165 | } |
| 1166 | else |
| 1167 | { |
| 1168 | for (i = I387_YMM0H_REGNUM (tdep); |
| 1169 | i < I387_YMMENDH_REGNUM (tdep); |
| 1170 | i++) |
| 1171 | regcache->raw_supply (i, XSAVE_AVXH_ADDR (tdep, regs, i)); |
| 1172 | } |
| 1173 | } |
| 1174 | |
| 1175 | /* Handle the MPX registers. */ |
| 1176 | if ((tdep->xcr0 & X86_XSTATE_BNDREGS)) |
| 1177 | { |
| 1178 | if (clear_bv & X86_XSTATE_BNDREGS) |
| 1179 | { |
| 1180 | for (i = I387_BND0R_REGNUM (tdep); |
| 1181 | i < I387_BNDCFGU_REGNUM (tdep); i++) |
| 1182 | regcache->raw_supply (i, zero); |
| 1183 | } |
| 1184 | else |
| 1185 | { |
| 1186 | for (i = I387_BND0R_REGNUM (tdep); |
| 1187 | i < I387_BNDCFGU_REGNUM (tdep); i++) |
| 1188 | regcache->raw_supply (i, XSAVE_MPX_ADDR (tdep, regs, i)); |
| 1189 | } |
| 1190 | } |
| 1191 | |
| 1192 | /* Handle the MPX registers. */ |
| 1193 | if ((tdep->xcr0 & X86_XSTATE_BNDCFG)) |
| 1194 | { |
| 1195 | if (clear_bv & X86_XSTATE_BNDCFG) |
| 1196 | { |
| 1197 | for (i = I387_BNDCFGU_REGNUM (tdep); |
| 1198 | i < I387_MPXEND_REGNUM (tdep); i++) |
| 1199 | regcache->raw_supply (i, zero); |
| 1200 | } |
| 1201 | else |
| 1202 | { |
| 1203 | for (i = I387_BNDCFGU_REGNUM (tdep); |
| 1204 | i < I387_MPXEND_REGNUM (tdep); i++) |
| 1205 | regcache->raw_supply (i, XSAVE_MPX_ADDR (tdep, regs, i)); |
| 1206 | } |
| 1207 | } |
| 1208 | |
| 1209 | /* Handle the XMM registers. */ |
| 1210 | if ((tdep->xcr0 & X86_XSTATE_SSE)) |
| 1211 | { |
| 1212 | if ((clear_bv & X86_XSTATE_SSE)) |
| 1213 | { |
| 1214 | for (i = I387_XMM0_REGNUM (tdep); |
| 1215 | i < I387_MXCSR_REGNUM (tdep); |
| 1216 | i++) |
| 1217 | regcache->raw_supply (i, zero); |
| 1218 | } |
| 1219 | else |
| 1220 | { |
| 1221 | for (i = I387_XMM0_REGNUM (tdep); |
| 1222 | i < I387_MXCSR_REGNUM (tdep); i++) |
| 1223 | regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i)); |
| 1224 | } |
| 1225 | } |
| 1226 | |
| 1227 | /* Handle the x87 registers. */ |
| 1228 | if ((tdep->xcr0 & X86_XSTATE_X87)) |
| 1229 | { |
| 1230 | if ((clear_bv & X86_XSTATE_X87)) |
| 1231 | { |
| 1232 | for (i = I387_ST0_REGNUM (tdep); |
| 1233 | i < I387_FCTRL_REGNUM (tdep); |
| 1234 | i++) |
| 1235 | regcache->raw_supply (i, zero); |
| 1236 | } |
| 1237 | else |
| 1238 | { |
| 1239 | for (i = I387_ST0_REGNUM (tdep); |
| 1240 | i < I387_FCTRL_REGNUM (tdep); |
| 1241 | i++) |
| 1242 | regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i)); |
| 1243 | } |
| 1244 | } |
| 1245 | break; |
| 1246 | } |
| 1247 | |
| 1248 | /* Only handle x87 control registers. */ |
| 1249 | for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++) |
| 1250 | if (regnum == -1 || regnum == i) |
| 1251 | { |
| 1252 | if (clear_bv & X86_XSTATE_X87) |
| 1253 | { |
| 1254 | if (i == I387_FCTRL_REGNUM (tdep)) |
| 1255 | { |
| 1256 | gdb_byte buf[4]; |
| 1257 | |
| 1258 | store_unsigned_integer (buf, 4, byte_order, |
| 1259 | I387_FCTRL_INIT_VAL); |
| 1260 | regcache->raw_supply (i, buf); |
| 1261 | } |
| 1262 | else if (i == I387_FTAG_REGNUM (tdep)) |
| 1263 | { |
| 1264 | gdb_byte buf[4]; |
| 1265 | |
| 1266 | store_unsigned_integer (buf, 4, byte_order, 0xffff); |
| 1267 | regcache->raw_supply (i, buf); |
| 1268 | } |
| 1269 | else |
| 1270 | regcache->raw_supply (i, zero); |
| 1271 | } |
| 1272 | /* Most of the FPU control registers occupy only 16 bits in |
| 1273 | the xsave extended state. Give those a special treatment. */ |
| 1274 | else if (i != I387_FIOFF_REGNUM (tdep) |
| 1275 | && i != I387_FOOFF_REGNUM (tdep)) |
| 1276 | { |
| 1277 | gdb_byte val[4]; |
| 1278 | |
| 1279 | memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2); |
| 1280 | val[2] = val[3] = 0; |
| 1281 | if (i == I387_FOP_REGNUM (tdep)) |
| 1282 | val[1] &= ((1 << 3) - 1); |
| 1283 | else if (i == I387_FTAG_REGNUM (tdep)) |
| 1284 | { |
| 1285 | /* The fxsave area contains a simplified version of |
| 1286 | the tag word. We have to look at the actual 80-bit |
| 1287 | FP data to recreate the traditional i387 tag word. */ |
| 1288 | |
| 1289 | unsigned long ftag = 0; |
| 1290 | int fpreg; |
| 1291 | int top; |
| 1292 | |
| 1293 | top = ((FXSAVE_ADDR (tdep, regs, |
| 1294 | I387_FSTAT_REGNUM (tdep)))[1] >> 3); |
| 1295 | top &= 0x7; |
| 1296 | |
| 1297 | for (fpreg = 7; fpreg >= 0; fpreg--) |
| 1298 | { |
| 1299 | int tag; |
| 1300 | |
| 1301 | if (val[0] & (1 << fpreg)) |
| 1302 | { |
| 1303 | int thisreg = (fpreg + 8 - top) % 8 |
| 1304 | + I387_ST0_REGNUM (tdep); |
| 1305 | tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg)); |
| 1306 | } |
| 1307 | else |
| 1308 | tag = 3; /* Empty */ |
| 1309 | |
| 1310 | ftag |= tag << (2 * fpreg); |
| 1311 | } |
| 1312 | val[0] = ftag & 0xff; |
| 1313 | val[1] = (ftag >> 8) & 0xff; |
| 1314 | } |
| 1315 | regcache->raw_supply (i, val); |
| 1316 | } |
| 1317 | else |
| 1318 | regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i)); |
| 1319 | } |
| 1320 | |
| 1321 | if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1) |
| 1322 | { |
| 1323 | /* The MXCSR register is placed into the xsave buffer if either the |
| 1324 | AVX or SSE features are enabled. */ |
| 1325 | if ((clear_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE)) |
| 1326 | == (X86_XSTATE_AVX | X86_XSTATE_SSE)) |
| 1327 | { |
| 1328 | gdb_byte buf[4]; |
| 1329 | |
| 1330 | store_unsigned_integer (buf, 4, byte_order, I387_MXCSR_INIT_VAL); |
| 1331 | regcache->raw_supply (I387_MXCSR_REGNUM (tdep), buf); |
| 1332 | } |
| 1333 | else |
| 1334 | regcache->raw_supply (I387_MXCSR_REGNUM (tdep), |
| 1335 | FXSAVE_MXCSR_ADDR (regs)); |
| 1336 | } |
| 1337 | } |
| 1338 | |
| 1339 | /* Similar to i387_collect_fxsave, but use XSAVE extended state. */ |
| 1340 | |
| 1341 | void |
| 1342 | i387_collect_xsave (const struct regcache *regcache, int regnum, |
| 1343 | void *xsave, int gcore) |
| 1344 | { |
| 1345 | struct gdbarch *gdbarch = regcache->arch (); |
| 1346 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1347 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1348 | gdb_byte *p, *regs = (gdb_byte *) xsave; |
| 1349 | gdb_byte raw[I386_MAX_REGISTER_SIZE]; |
| 1350 | ULONGEST initial_xstate_bv, clear_bv, xstate_bv = 0; |
| 1351 | unsigned int i; |
| 1352 | /* See the comment in i387_supply_xsave(). */ |
| 1353 | unsigned int zmm_endlo_regnum = I387_ZMM0H_REGNUM (tdep) |
| 1354 | + std::min (tdep->num_zmm_regs, 16); |
| 1355 | enum |
| 1356 | { |
| 1357 | x87_ctrl_or_mxcsr = 0x1, |
| 1358 | x87 = 0x2, |
| 1359 | sse = 0x4, |
| 1360 | avxh = 0x8, |
| 1361 | mpx = 0x10, |
| 1362 | avx512_k = 0x20, |
| 1363 | avx512_zmm_h = 0x40, |
| 1364 | avx512_ymmh_avx512 = 0x80, |
| 1365 | avx512_xmm_avx512 = 0x100, |
| 1366 | pkeys = 0x200, |
| 1367 | all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h |
| 1368 | | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys |
| 1369 | } regclass; |
| 1370 | |
| 1371 | gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); |
| 1372 | gdb_assert (tdep->num_xmm_regs > 0); |
| 1373 | |
| 1374 | if (regnum == -1) |
| 1375 | regclass = all; |
| 1376 | else if (regnum >= I387_PKRU_REGNUM (tdep) |
| 1377 | && regnum < I387_PKEYSEND_REGNUM (tdep)) |
| 1378 | regclass = pkeys; |
| 1379 | else if (regnum >= I387_ZMM0H_REGNUM (tdep) |
| 1380 | && regnum < I387_ZMMENDH_REGNUM (tdep)) |
| 1381 | regclass = avx512_zmm_h; |
| 1382 | else if (regnum >= I387_K0_REGNUM (tdep) |
| 1383 | && regnum < I387_KEND_REGNUM (tdep)) |
| 1384 | regclass = avx512_k; |
| 1385 | else if (regnum >= I387_YMM16H_REGNUM (tdep) |
| 1386 | && regnum < I387_YMMH_AVX512_END_REGNUM (tdep)) |
| 1387 | regclass = avx512_ymmh_avx512; |
| 1388 | else if (regnum >= I387_XMM16_REGNUM (tdep) |
| 1389 | && regnum < I387_XMM_AVX512_END_REGNUM (tdep)) |
| 1390 | regclass = avx512_xmm_avx512; |
| 1391 | else if (regnum >= I387_YMM0H_REGNUM (tdep) |
| 1392 | && regnum < I387_YMMENDH_REGNUM (tdep)) |
| 1393 | regclass = avxh; |
| 1394 | else if (regnum >= I387_BND0R_REGNUM (tdep) |
| 1395 | && regnum < I387_MPXEND_REGNUM (tdep)) |
| 1396 | regclass = mpx; |
| 1397 | else if (regnum >= I387_XMM0_REGNUM (tdep) |
| 1398 | && regnum < I387_MXCSR_REGNUM (tdep)) |
| 1399 | regclass = sse; |
| 1400 | else if (regnum >= I387_ST0_REGNUM (tdep) |
| 1401 | && regnum < I387_FCTRL_REGNUM (tdep)) |
| 1402 | regclass = x87; |
| 1403 | else if ((regnum >= I387_FCTRL_REGNUM (tdep) |
| 1404 | && regnum < I387_XMM0_REGNUM (tdep)) |
| 1405 | || regnum == I387_MXCSR_REGNUM (tdep)) |
| 1406 | regclass = x87_ctrl_or_mxcsr; |
| 1407 | else |
| 1408 | internal_error (__FILE__, __LINE__, _("invalid i387 regnum %d"), regnum); |
| 1409 | |
| 1410 | if (gcore) |
| 1411 | { |
| 1412 | /* Clear XSAVE extended state. */ |
| 1413 | memset (regs, 0, X86_XSTATE_SIZE (tdep->xcr0)); |
| 1414 | |
| 1415 | /* Update XCR0 and `xstate_bv' with XCR0 for gcore. */ |
| 1416 | if (tdep->xsave_xcr0_offset != -1) |
| 1417 | memcpy (regs + tdep->xsave_xcr0_offset, &tdep->xcr0, 8); |
| 1418 | memcpy (XSAVE_XSTATE_BV_ADDR (regs), &tdep->xcr0, 8); |
| 1419 | } |
| 1420 | |
| 1421 | /* The supported bits in `xstat_bv' are 8 bytes. */ |
| 1422 | initial_xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs), |
| 1423 | 8, byte_order); |
| 1424 | clear_bv = (~(initial_xstate_bv)) & tdep->xcr0; |
| 1425 | |
| 1426 | /* The XSAVE buffer was filled lazily by the kernel. Only those |
| 1427 | features that are enabled were written into the buffer, disabled |
| 1428 | features left the buffer uninitialised. In order to identify if any |
| 1429 | registers have changed we will be comparing the register cache |
| 1430 | version to the version in the XSAVE buffer, it is important then that |
| 1431 | at this point we initialise to the default values any features in |
| 1432 | XSAVE that are not yet initialised. |
| 1433 | |
| 1434 | This could be made more efficient, we know which features (from |
| 1435 | REGNUM) we will be potentially updating, and could limit ourselves to |
| 1436 | only clearing that feature. However, the extra complexity does not |
| 1437 | seem justified at this point. */ |
| 1438 | if (clear_bv) |
| 1439 | { |
| 1440 | if ((clear_bv & X86_XSTATE_PKRU)) |
| 1441 | for (i = I387_PKRU_REGNUM (tdep); |
| 1442 | i < I387_PKEYSEND_REGNUM (tdep); i++) |
| 1443 | memset (XSAVE_PKEYS_ADDR (tdep, regs, i), 0, 4); |
| 1444 | |
| 1445 | if ((clear_bv & X86_XSTATE_BNDREGS)) |
| 1446 | for (i = I387_BND0R_REGNUM (tdep); |
| 1447 | i < I387_BNDCFGU_REGNUM (tdep); i++) |
| 1448 | memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 16); |
| 1449 | |
| 1450 | if ((clear_bv & X86_XSTATE_BNDCFG)) |
| 1451 | for (i = I387_BNDCFGU_REGNUM (tdep); |
| 1452 | i < I387_MPXEND_REGNUM (tdep); i++) |
| 1453 | memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 8); |
| 1454 | |
| 1455 | if ((clear_bv & X86_XSTATE_ZMM_H)) |
| 1456 | for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++) |
| 1457 | memset (XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i), 0, 32); |
| 1458 | |
| 1459 | if ((clear_bv & X86_XSTATE_K)) |
| 1460 | for (i = I387_K0_REGNUM (tdep); |
| 1461 | i < I387_KEND_REGNUM (tdep); i++) |
| 1462 | memset (XSAVE_AVX512_K_ADDR (tdep, regs, i), 0, 8); |
| 1463 | |
| 1464 | if ((clear_bv & X86_XSTATE_ZMM)) |
| 1465 | { |
| 1466 | for (i = zmm_endlo_regnum; i < I387_ZMMENDH_REGNUM (tdep); i++) |
| 1467 | memset (XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i), 0, 32); |
| 1468 | for (i = I387_YMM16H_REGNUM (tdep); |
| 1469 | i < I387_YMMH_AVX512_END_REGNUM (tdep); i++) |
| 1470 | memset (XSAVE_YMM_AVX512_ADDR (tdep, regs, i), 0, 16); |
| 1471 | for (i = I387_XMM16_REGNUM (tdep); |
| 1472 | i < I387_XMM_AVX512_END_REGNUM (tdep); i++) |
| 1473 | memset (XSAVE_XMM_AVX512_ADDR (tdep, regs, i), 0, 16); |
| 1474 | } |
| 1475 | |
| 1476 | if ((clear_bv & X86_XSTATE_AVX)) |
| 1477 | for (i = I387_YMM0H_REGNUM (tdep); |
| 1478 | i < I387_YMMENDH_REGNUM (tdep); i++) |
| 1479 | memset (XSAVE_AVXH_ADDR (tdep, regs, i), 0, 16); |
| 1480 | |
| 1481 | if ((clear_bv & X86_XSTATE_SSE)) |
| 1482 | for (i = I387_XMM0_REGNUM (tdep); |
| 1483 | i < I387_MXCSR_REGNUM (tdep); i++) |
| 1484 | memset (FXSAVE_ADDR (tdep, regs, i), 0, 16); |
| 1485 | |
| 1486 | /* The mxcsr register is written into the xsave buffer if either AVX |
| 1487 | or SSE is enabled, so only clear it if both of those features |
| 1488 | require clearing. */ |
| 1489 | if ((clear_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE)) |
| 1490 | == (X86_XSTATE_AVX | X86_XSTATE_SSE)) |
| 1491 | store_unsigned_integer (FXSAVE_MXCSR_ADDR (regs), 2, byte_order, |
| 1492 | I387_MXCSR_INIT_VAL); |
| 1493 | |
| 1494 | if ((clear_bv & X86_XSTATE_X87)) |
| 1495 | { |
| 1496 | for (i = I387_ST0_REGNUM (tdep); |
| 1497 | i < I387_FCTRL_REGNUM (tdep); i++) |
| 1498 | memset (FXSAVE_ADDR (tdep, regs, i), 0, 10); |
| 1499 | |
| 1500 | for (i = I387_FCTRL_REGNUM (tdep); |
| 1501 | i < I387_XMM0_REGNUM (tdep); i++) |
| 1502 | { |
| 1503 | if (i == I387_FCTRL_REGNUM (tdep)) |
| 1504 | store_unsigned_integer (FXSAVE_ADDR (tdep, regs, i), 2, |
| 1505 | byte_order, I387_FCTRL_INIT_VAL); |
| 1506 | else |
| 1507 | memset (FXSAVE_ADDR (tdep, regs, i), 0, |
| 1508 | regcache_register_size (regcache, i)); |
| 1509 | } |
| 1510 | } |
| 1511 | } |
| 1512 | |
| 1513 | if (regclass == all) |
| 1514 | { |
| 1515 | /* Check if any PKEYS registers are changed. */ |
| 1516 | if ((tdep->xcr0 & X86_XSTATE_PKRU)) |
| 1517 | for (i = I387_PKRU_REGNUM (tdep); |
| 1518 | i < I387_PKEYSEND_REGNUM (tdep); i++) |
| 1519 | { |
| 1520 | regcache->raw_collect (i, raw); |
| 1521 | p = XSAVE_PKEYS_ADDR (tdep, regs, i); |
| 1522 | if (memcmp (raw, p, 4) != 0) |
| 1523 | { |
| 1524 | xstate_bv |= X86_XSTATE_PKRU; |
| 1525 | memcpy (p, raw, 4); |
| 1526 | } |
| 1527 | } |
| 1528 | |
| 1529 | /* Check if any ZMMH registers are changed. */ |
| 1530 | if ((tdep->xcr0 & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM))) |
| 1531 | for (i = I387_ZMM0H_REGNUM (tdep); |
| 1532 | i < I387_ZMMENDH_REGNUM (tdep); i++) |
| 1533 | { |
| 1534 | regcache->raw_collect (i, raw); |
| 1535 | p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i); |
| 1536 | if (memcmp (raw, p, 32) != 0) |
| 1537 | { |
| 1538 | xstate_bv |= (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM); |
| 1539 | memcpy (p, raw, 32); |
| 1540 | } |
| 1541 | } |
| 1542 | |
| 1543 | /* Check if any K registers are changed. */ |
| 1544 | if ((tdep->xcr0 & X86_XSTATE_K)) |
| 1545 | for (i = I387_K0_REGNUM (tdep); |
| 1546 | i < I387_KEND_REGNUM (tdep); i++) |
| 1547 | { |
| 1548 | regcache->raw_collect (i, raw); |
| 1549 | p = XSAVE_AVX512_K_ADDR (tdep, regs, i); |
| 1550 | if (memcmp (raw, p, 8) != 0) |
| 1551 | { |
| 1552 | xstate_bv |= X86_XSTATE_K; |
| 1553 | memcpy (p, raw, 8); |
| 1554 | } |
| 1555 | } |
| 1556 | |
| 1557 | /* Check if any XMM or upper YMM registers are changed. */ |
| 1558 | if ((tdep->xcr0 & X86_XSTATE_ZMM)) |
| 1559 | { |
| 1560 | for (i = I387_YMM16H_REGNUM (tdep); |
| 1561 | i < I387_YMMH_AVX512_END_REGNUM (tdep); i++) |
| 1562 | { |
| 1563 | regcache->raw_collect (i, raw); |
| 1564 | p = XSAVE_YMM_AVX512_ADDR (tdep, regs, i); |
| 1565 | if (memcmp (raw, p, 16) != 0) |
| 1566 | { |
| 1567 | xstate_bv |= X86_XSTATE_ZMM; |
| 1568 | memcpy (p, raw, 16); |
| 1569 | } |
| 1570 | } |
| 1571 | for (i = I387_XMM16_REGNUM (tdep); |
| 1572 | i < I387_XMM_AVX512_END_REGNUM (tdep); i++) |
| 1573 | { |
| 1574 | regcache->raw_collect (i, raw); |
| 1575 | p = XSAVE_XMM_AVX512_ADDR (tdep, regs, i); |
| 1576 | if (memcmp (raw, p, 16) != 0) |
| 1577 | { |
| 1578 | xstate_bv |= X86_XSTATE_ZMM; |
| 1579 | memcpy (p, raw, 16); |
| 1580 | } |
| 1581 | } |
| 1582 | } |
| 1583 | |
| 1584 | /* Check if any upper MPX registers are changed. */ |
| 1585 | if ((tdep->xcr0 & X86_XSTATE_BNDREGS)) |
| 1586 | for (i = I387_BND0R_REGNUM (tdep); |
| 1587 | i < I387_BNDCFGU_REGNUM (tdep); i++) |
| 1588 | { |
| 1589 | regcache->raw_collect (i, raw); |
| 1590 | p = XSAVE_MPX_ADDR (tdep, regs, i); |
| 1591 | if (memcmp (raw, p, 16)) |
| 1592 | { |
| 1593 | xstate_bv |= X86_XSTATE_BNDREGS; |
| 1594 | memcpy (p, raw, 16); |
| 1595 | } |
| 1596 | } |
| 1597 | |
| 1598 | /* Check if any upper MPX registers are changed. */ |
| 1599 | if ((tdep->xcr0 & X86_XSTATE_BNDCFG)) |
| 1600 | for (i = I387_BNDCFGU_REGNUM (tdep); |
| 1601 | i < I387_MPXEND_REGNUM (tdep); i++) |
| 1602 | { |
| 1603 | regcache->raw_collect (i, raw); |
| 1604 | p = XSAVE_MPX_ADDR (tdep, regs, i); |
| 1605 | if (memcmp (raw, p, 8)) |
| 1606 | { |
| 1607 | xstate_bv |= X86_XSTATE_BNDCFG; |
| 1608 | memcpy (p, raw, 8); |
| 1609 | } |
| 1610 | } |
| 1611 | |
| 1612 | /* Check if any upper YMM registers are changed. */ |
| 1613 | if ((tdep->xcr0 & X86_XSTATE_AVX)) |
| 1614 | for (i = I387_YMM0H_REGNUM (tdep); |
| 1615 | i < I387_YMMENDH_REGNUM (tdep); i++) |
| 1616 | { |
| 1617 | regcache->raw_collect (i, raw); |
| 1618 | p = XSAVE_AVXH_ADDR (tdep, regs, i); |
| 1619 | if (memcmp (raw, p, 16)) |
| 1620 | { |
| 1621 | xstate_bv |= X86_XSTATE_AVX; |
| 1622 | memcpy (p, raw, 16); |
| 1623 | } |
| 1624 | } |
| 1625 | |
| 1626 | /* Check if any SSE registers are changed. */ |
| 1627 | if ((tdep->xcr0 & X86_XSTATE_SSE)) |
| 1628 | for (i = I387_XMM0_REGNUM (tdep); |
| 1629 | i < I387_MXCSR_REGNUM (tdep); i++) |
| 1630 | { |
| 1631 | regcache->raw_collect (i, raw); |
| 1632 | p = FXSAVE_ADDR (tdep, regs, i); |
| 1633 | if (memcmp (raw, p, 16)) |
| 1634 | { |
| 1635 | xstate_bv |= X86_XSTATE_SSE; |
| 1636 | memcpy (p, raw, 16); |
| 1637 | } |
| 1638 | } |
| 1639 | |
| 1640 | if ((tdep->xcr0 & X86_XSTATE_AVX) || (tdep->xcr0 & X86_XSTATE_SSE)) |
| 1641 | { |
| 1642 | i = I387_MXCSR_REGNUM (tdep); |
| 1643 | regcache->raw_collect (i, raw); |
| 1644 | p = FXSAVE_MXCSR_ADDR (regs); |
| 1645 | if (memcmp (raw, p, 4)) |
| 1646 | { |
| 1647 | /* Now, we need to mark one of either SSE of AVX as enabled. |
| 1648 | We could pick either. What we do is check to see if one |
| 1649 | of the features is already enabled, if it is then we leave |
| 1650 | it at that, otherwise we pick SSE. */ |
| 1651 | if ((xstate_bv & (X86_XSTATE_SSE | X86_XSTATE_AVX)) == 0) |
| 1652 | xstate_bv |= X86_XSTATE_SSE; |
| 1653 | memcpy (p, raw, 4); |
| 1654 | } |
| 1655 | } |
| 1656 | |
| 1657 | /* Check if any X87 registers are changed. Only the non-control |
| 1658 | registers are handled here, the control registers are all handled |
| 1659 | later on in this function. */ |
| 1660 | if ((tdep->xcr0 & X86_XSTATE_X87)) |
| 1661 | for (i = I387_ST0_REGNUM (tdep); |
| 1662 | i < I387_FCTRL_REGNUM (tdep); i++) |
| 1663 | { |
| 1664 | regcache->raw_collect (i, raw); |
| 1665 | p = FXSAVE_ADDR (tdep, regs, i); |
| 1666 | if (memcmp (raw, p, 10)) |
| 1667 | { |
| 1668 | xstate_bv |= X86_XSTATE_X87; |
| 1669 | memcpy (p, raw, 10); |
| 1670 | } |
| 1671 | } |
| 1672 | } |
| 1673 | else |
| 1674 | { |
| 1675 | /* Check if REGNUM is changed. */ |
| 1676 | regcache->raw_collect (regnum, raw); |
| 1677 | |
| 1678 | switch (regclass) |
| 1679 | { |
| 1680 | default: |
| 1681 | internal_error (__FILE__, __LINE__, |
| 1682 | _("invalid i387 regclass")); |
| 1683 | |
| 1684 | case pkeys: |
| 1685 | /* This is a PKEYS register. */ |
| 1686 | p = XSAVE_PKEYS_ADDR (tdep, regs, regnum); |
| 1687 | if (memcmp (raw, p, 4) != 0) |
| 1688 | { |
| 1689 | xstate_bv |= X86_XSTATE_PKRU; |
| 1690 | memcpy (p, raw, 4); |
| 1691 | } |
| 1692 | break; |
| 1693 | |
| 1694 | case avx512_zmm_h: |
| 1695 | /* This is a ZMM register. */ |
| 1696 | p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum); |
| 1697 | if (memcmp (raw, p, 32) != 0) |
| 1698 | { |
| 1699 | xstate_bv |= (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM); |
| 1700 | memcpy (p, raw, 32); |
| 1701 | } |
| 1702 | break; |
| 1703 | case avx512_k: |
| 1704 | /* This is a AVX512 mask register. */ |
| 1705 | p = XSAVE_AVX512_K_ADDR (tdep, regs, regnum); |
| 1706 | if (memcmp (raw, p, 8) != 0) |
| 1707 | { |
| 1708 | xstate_bv |= X86_XSTATE_K; |
| 1709 | memcpy (p, raw, 8); |
| 1710 | } |
| 1711 | break; |
| 1712 | |
| 1713 | case avx512_ymmh_avx512: |
| 1714 | /* This is an upper YMM16-31 register. */ |
| 1715 | p = XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum); |
| 1716 | if (memcmp (raw, p, 16) != 0) |
| 1717 | { |
| 1718 | xstate_bv |= X86_XSTATE_ZMM; |
| 1719 | memcpy (p, raw, 16); |
| 1720 | } |
| 1721 | break; |
| 1722 | |
| 1723 | case avx512_xmm_avx512: |
| 1724 | /* This is an upper XMM16-31 register. */ |
| 1725 | p = XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum); |
| 1726 | if (memcmp (raw, p, 16) != 0) |
| 1727 | { |
| 1728 | xstate_bv |= X86_XSTATE_ZMM; |
| 1729 | memcpy (p, raw, 16); |
| 1730 | } |
| 1731 | break; |
| 1732 | |
| 1733 | case avxh: |
| 1734 | /* This is an upper YMM register. */ |
| 1735 | p = XSAVE_AVXH_ADDR (tdep, regs, regnum); |
| 1736 | if (memcmp (raw, p, 16)) |
| 1737 | { |
| 1738 | xstate_bv |= X86_XSTATE_AVX; |
| 1739 | memcpy (p, raw, 16); |
| 1740 | } |
| 1741 | break; |
| 1742 | |
| 1743 | case mpx: |
| 1744 | if (regnum < I387_BNDCFGU_REGNUM (tdep)) |
| 1745 | { |
| 1746 | regcache->raw_collect (regnum, raw); |
| 1747 | p = XSAVE_MPX_ADDR (tdep, regs, regnum); |
| 1748 | if (memcmp (raw, p, 16)) |
| 1749 | { |
| 1750 | xstate_bv |= X86_XSTATE_BNDREGS; |
| 1751 | memcpy (p, raw, 16); |
| 1752 | } |
| 1753 | } |
| 1754 | else |
| 1755 | { |
| 1756 | p = XSAVE_MPX_ADDR (tdep, regs, regnum); |
| 1757 | xstate_bv |= X86_XSTATE_BNDCFG; |
| 1758 | memcpy (p, raw, 8); |
| 1759 | } |
| 1760 | break; |
| 1761 | |
| 1762 | case sse: |
| 1763 | /* This is an SSE register. */ |
| 1764 | p = FXSAVE_ADDR (tdep, regs, regnum); |
| 1765 | if (memcmp (raw, p, 16)) |
| 1766 | { |
| 1767 | xstate_bv |= X86_XSTATE_SSE; |
| 1768 | memcpy (p, raw, 16); |
| 1769 | } |
| 1770 | break; |
| 1771 | |
| 1772 | case x87: |
| 1773 | /* This is an x87 register. */ |
| 1774 | p = FXSAVE_ADDR (tdep, regs, regnum); |
| 1775 | if (memcmp (raw, p, 10)) |
| 1776 | { |
| 1777 | xstate_bv |= X86_XSTATE_X87; |
| 1778 | memcpy (p, raw, 10); |
| 1779 | } |
| 1780 | break; |
| 1781 | |
| 1782 | case x87_ctrl_or_mxcsr: |
| 1783 | /* We only handle MXCSR here. All other x87 control registers |
| 1784 | are handled separately below. */ |
| 1785 | if (regnum == I387_MXCSR_REGNUM (tdep)) |
| 1786 | { |
| 1787 | p = FXSAVE_MXCSR_ADDR (regs); |
| 1788 | if (memcmp (raw, p, 2)) |
| 1789 | { |
| 1790 | /* We're only setting MXCSR, so check the initial state |
| 1791 | to see if either of AVX or SSE are already enabled. |
| 1792 | If they are then we'll attribute this changed MXCSR to |
| 1793 | that feature. If neither feature is enabled, then |
| 1794 | we'll attribute this change to the SSE feature. */ |
| 1795 | xstate_bv |= (initial_xstate_bv |
| 1796 | & (X86_XSTATE_AVX | X86_XSTATE_SSE)); |
| 1797 | if ((xstate_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE)) == 0) |
| 1798 | xstate_bv |= X86_XSTATE_SSE; |
| 1799 | memcpy (p, raw, 2); |
| 1800 | } |
| 1801 | } |
| 1802 | } |
| 1803 | } |
| 1804 | |
| 1805 | /* Only handle x87 control registers. */ |
| 1806 | for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++) |
| 1807 | if (regnum == -1 || regnum == i) |
| 1808 | { |
| 1809 | /* Most of the FPU control registers occupy only 16 bits in |
| 1810 | the xsave extended state. Give those a special treatment. */ |
| 1811 | if (i != I387_FIOFF_REGNUM (tdep) |
| 1812 | && i != I387_FOOFF_REGNUM (tdep)) |
| 1813 | { |
| 1814 | gdb_byte buf[4]; |
| 1815 | |
| 1816 | regcache->raw_collect (i, buf); |
| 1817 | |
| 1818 | if (i == I387_FOP_REGNUM (tdep)) |
| 1819 | { |
| 1820 | /* The opcode occupies only 11 bits. Make sure we |
| 1821 | don't touch the other bits. */ |
| 1822 | buf[1] &= ((1 << 3) - 1); |
| 1823 | buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1)); |
| 1824 | } |
| 1825 | else if (i == I387_FTAG_REGNUM (tdep)) |
| 1826 | { |
| 1827 | /* Converting back is much easier. */ |
| 1828 | |
| 1829 | unsigned short ftag; |
| 1830 | int fpreg; |
| 1831 | |
| 1832 | ftag = (buf[1] << 8) | buf[0]; |
| 1833 | buf[0] = 0; |
| 1834 | buf[1] = 0; |
| 1835 | |
| 1836 | for (fpreg = 7; fpreg >= 0; fpreg--) |
| 1837 | { |
| 1838 | int tag = (ftag >> (fpreg * 2)) & 3; |
| 1839 | |
| 1840 | if (tag != 3) |
| 1841 | buf[0] |= (1 << fpreg); |
| 1842 | } |
| 1843 | } |
| 1844 | p = FXSAVE_ADDR (tdep, regs, i); |
| 1845 | if (memcmp (p, buf, 2)) |
| 1846 | { |
| 1847 | xstate_bv |= X86_XSTATE_X87; |
| 1848 | memcpy (p, buf, 2); |
| 1849 | } |
| 1850 | } |
| 1851 | else |
| 1852 | { |
| 1853 | int regsize; |
| 1854 | |
| 1855 | regcache->raw_collect (i, raw); |
| 1856 | regsize = regcache_register_size (regcache, i); |
| 1857 | p = FXSAVE_ADDR (tdep, regs, i); |
| 1858 | if (memcmp (raw, p, regsize)) |
| 1859 | { |
| 1860 | xstate_bv |= X86_XSTATE_X87; |
| 1861 | memcpy (p, raw, regsize); |
| 1862 | } |
| 1863 | } |
| 1864 | } |
| 1865 | |
| 1866 | /* Update the corresponding bits in `xstate_bv' if any |
| 1867 | registers are changed. */ |
| 1868 | if (xstate_bv) |
| 1869 | { |
| 1870 | /* The supported bits in `xstat_bv' are 8 bytes. */ |
| 1871 | initial_xstate_bv |= xstate_bv; |
| 1872 | store_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs), |
| 1873 | 8, byte_order, |
| 1874 | initial_xstate_bv); |
| 1875 | } |
| 1876 | } |
| 1877 | |
| 1878 | /* Recreate the FTW (tag word) valid bits from the 80-bit FP data in |
| 1879 | *RAW. */ |
| 1880 | |
| 1881 | static int |
| 1882 | i387_tag (const gdb_byte *raw) |
| 1883 | { |
| 1884 | int integer; |
| 1885 | unsigned int exponent; |
| 1886 | unsigned long fraction[2]; |
| 1887 | |
| 1888 | integer = raw[7] & 0x80; |
| 1889 | exponent = (((raw[9] & 0x7f) << 8) | raw[8]); |
| 1890 | fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]); |
| 1891 | fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16) |
| 1892 | | (raw[5] << 8) | raw[4]); |
| 1893 | |
| 1894 | if (exponent == 0x7fff) |
| 1895 | { |
| 1896 | /* Special. */ |
| 1897 | return (2); |
| 1898 | } |
| 1899 | else if (exponent == 0x0000) |
| 1900 | { |
| 1901 | if (fraction[0] == 0x0000 && fraction[1] == 0x0000 && !integer) |
| 1902 | { |
| 1903 | /* Zero. */ |
| 1904 | return (1); |
| 1905 | } |
| 1906 | else |
| 1907 | { |
| 1908 | /* Special. */ |
| 1909 | return (2); |
| 1910 | } |
| 1911 | } |
| 1912 | else |
| 1913 | { |
| 1914 | if (integer) |
| 1915 | { |
| 1916 | /* Valid. */ |
| 1917 | return (0); |
| 1918 | } |
| 1919 | else |
| 1920 | { |
| 1921 | /* Special. */ |
| 1922 | return (2); |
| 1923 | } |
| 1924 | } |
| 1925 | } |
| 1926 | |
| 1927 | /* Prepare the FPU stack in REGCACHE for a function return. */ |
| 1928 | |
| 1929 | void |
| 1930 | i387_return_value (struct gdbarch *gdbarch, struct regcache *regcache) |
| 1931 | { |
| 1932 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1933 | ULONGEST fstat; |
| 1934 | |
| 1935 | /* Set the top of the floating-point register stack to 7. The |
| 1936 | actual value doesn't really matter, but 7 is what a normal |
| 1937 | function return would end up with if the program started out with |
| 1938 | a freshly initialized FPU. */ |
| 1939 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
| 1940 | fstat |= (7 << 11); |
| 1941 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
| 1942 | |
| 1943 | /* Mark %st(1) through %st(7) as empty. Since we set the top of the |
| 1944 | floating-point register stack to 7, the appropriate value for the |
| 1945 | tag word is 0x3fff. */ |
| 1946 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
| 1947 | |
| 1948 | } |
| 1949 | |
| 1950 | /* See i387-tdep.h. */ |
| 1951 | |
| 1952 | void |
| 1953 | i387_reset_bnd_regs (struct gdbarch *gdbarch, struct regcache *regcache) |
| 1954 | { |
| 1955 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1956 | |
| 1957 | if (I387_BND0R_REGNUM (tdep) > 0) |
| 1958 | { |
| 1959 | gdb_byte bnd_buf[16]; |
| 1960 | |
| 1961 | memset (bnd_buf, 0, 16); |
| 1962 | for (int i = 0; i < I387_NUM_BND_REGS; i++) |
| 1963 | regcache->raw_write (I387_BND0R_REGNUM (tdep) + i, bnd_buf); |
| 1964 | } |
| 1965 | } |