| 1 | /* Functions specific to running gdb native on IA-64 running |
| 2 | GNU/Linux. |
| 3 | |
| 4 | Copyright (C) 1999-2020 Free Software Foundation, Inc. |
| 5 | |
| 6 | This file is part of GDB. |
| 7 | |
| 8 | This program is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU General Public License as published by |
| 10 | the Free Software Foundation; either version 3 of the License, or |
| 11 | (at your option) any later version. |
| 12 | |
| 13 | This program is distributed in the hope that it will be useful, |
| 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | GNU General Public License for more details. |
| 17 | |
| 18 | You should have received a copy of the GNU General Public License |
| 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 20 | |
| 21 | #include "defs.h" |
| 22 | #include "inferior.h" |
| 23 | #include "target.h" |
| 24 | #include "gdbcore.h" |
| 25 | #include "regcache.h" |
| 26 | #include "ia64-tdep.h" |
| 27 | #include "linux-nat.h" |
| 28 | |
| 29 | #include <signal.h> |
| 30 | #include "nat/gdb_ptrace.h" |
| 31 | #include "gdbsupport/gdb_wait.h" |
| 32 | #ifdef HAVE_SYS_REG_H |
| 33 | #include <sys/reg.h> |
| 34 | #endif |
| 35 | #include <sys/syscall.h> |
| 36 | #include <sys/user.h> |
| 37 | |
| 38 | #include <asm/ptrace_offsets.h> |
| 39 | #include <sys/procfs.h> |
| 40 | |
| 41 | /* Prototypes for supply_gregset etc. */ |
| 42 | #include "gregset.h" |
| 43 | |
| 44 | #include "inf-ptrace.h" |
| 45 | |
| 46 | class ia64_linux_nat_target final : public linux_nat_target |
| 47 | { |
| 48 | public: |
| 49 | /* Add our register access methods. */ |
| 50 | void fetch_registers (struct regcache *, int) override; |
| 51 | void store_registers (struct regcache *, int) override; |
| 52 | |
| 53 | enum target_xfer_status xfer_partial (enum target_object object, |
| 54 | const char *annex, |
| 55 | gdb_byte *readbuf, |
| 56 | const gdb_byte *writebuf, |
| 57 | ULONGEST offset, ULONGEST len, |
| 58 | ULONGEST *xfered_len) override; |
| 59 | |
| 60 | /* Override watchpoint routines. */ |
| 61 | |
| 62 | /* The IA-64 architecture can step over a watch point (without |
| 63 | triggering it again) if the "dd" (data debug fault disable) bit |
| 64 | in the processor status word is set. |
| 65 | |
| 66 | This PSR bit is set in |
| 67 | ia64_linux_nat_target::stopped_by_watchpoint when the code there |
| 68 | has determined that a hardware watchpoint has indeed been hit. |
| 69 | The CPU will then be able to execute one instruction without |
| 70 | triggering a watchpoint. */ |
| 71 | bool have_steppable_watchpoint () override { return true; } |
| 72 | |
| 73 | int can_use_hw_breakpoint (enum bptype, int, int) override; |
| 74 | bool stopped_by_watchpoint () override; |
| 75 | bool stopped_data_address (CORE_ADDR *) override; |
| 76 | int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, |
| 77 | struct expression *) override; |
| 78 | int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, |
| 79 | struct expression *) override; |
| 80 | /* Override linux_nat_target low methods. */ |
| 81 | void low_new_thread (struct lwp_info *lp) override; |
| 82 | bool low_status_is_event (int status) override; |
| 83 | }; |
| 84 | |
| 85 | static ia64_linux_nat_target the_ia64_linux_nat_target; |
| 86 | |
| 87 | /* These must match the order of the register names. |
| 88 | |
| 89 | Some sort of lookup table is needed because the offsets associated |
| 90 | with the registers are all over the board. */ |
| 91 | |
| 92 | static int u_offsets[] = |
| 93 | { |
| 94 | /* general registers */ |
| 95 | -1, /* gr0 not available; i.e, it's always zero. */ |
| 96 | PT_R1, |
| 97 | PT_R2, |
| 98 | PT_R3, |
| 99 | PT_R4, |
| 100 | PT_R5, |
| 101 | PT_R6, |
| 102 | PT_R7, |
| 103 | PT_R8, |
| 104 | PT_R9, |
| 105 | PT_R10, |
| 106 | PT_R11, |
| 107 | PT_R12, |
| 108 | PT_R13, |
| 109 | PT_R14, |
| 110 | PT_R15, |
| 111 | PT_R16, |
| 112 | PT_R17, |
| 113 | PT_R18, |
| 114 | PT_R19, |
| 115 | PT_R20, |
| 116 | PT_R21, |
| 117 | PT_R22, |
| 118 | PT_R23, |
| 119 | PT_R24, |
| 120 | PT_R25, |
| 121 | PT_R26, |
| 122 | PT_R27, |
| 123 | PT_R28, |
| 124 | PT_R29, |
| 125 | PT_R30, |
| 126 | PT_R31, |
| 127 | /* gr32 through gr127 not directly available via the ptrace interface. */ |
| 128 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 129 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 130 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 131 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 132 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 133 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 134 | /* Floating point registers */ |
| 135 | -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0). */ |
| 136 | PT_F2, |
| 137 | PT_F3, |
| 138 | PT_F4, |
| 139 | PT_F5, |
| 140 | PT_F6, |
| 141 | PT_F7, |
| 142 | PT_F8, |
| 143 | PT_F9, |
| 144 | PT_F10, |
| 145 | PT_F11, |
| 146 | PT_F12, |
| 147 | PT_F13, |
| 148 | PT_F14, |
| 149 | PT_F15, |
| 150 | PT_F16, |
| 151 | PT_F17, |
| 152 | PT_F18, |
| 153 | PT_F19, |
| 154 | PT_F20, |
| 155 | PT_F21, |
| 156 | PT_F22, |
| 157 | PT_F23, |
| 158 | PT_F24, |
| 159 | PT_F25, |
| 160 | PT_F26, |
| 161 | PT_F27, |
| 162 | PT_F28, |
| 163 | PT_F29, |
| 164 | PT_F30, |
| 165 | PT_F31, |
| 166 | PT_F32, |
| 167 | PT_F33, |
| 168 | PT_F34, |
| 169 | PT_F35, |
| 170 | PT_F36, |
| 171 | PT_F37, |
| 172 | PT_F38, |
| 173 | PT_F39, |
| 174 | PT_F40, |
| 175 | PT_F41, |
| 176 | PT_F42, |
| 177 | PT_F43, |
| 178 | PT_F44, |
| 179 | PT_F45, |
| 180 | PT_F46, |
| 181 | PT_F47, |
| 182 | PT_F48, |
| 183 | PT_F49, |
| 184 | PT_F50, |
| 185 | PT_F51, |
| 186 | PT_F52, |
| 187 | PT_F53, |
| 188 | PT_F54, |
| 189 | PT_F55, |
| 190 | PT_F56, |
| 191 | PT_F57, |
| 192 | PT_F58, |
| 193 | PT_F59, |
| 194 | PT_F60, |
| 195 | PT_F61, |
| 196 | PT_F62, |
| 197 | PT_F63, |
| 198 | PT_F64, |
| 199 | PT_F65, |
| 200 | PT_F66, |
| 201 | PT_F67, |
| 202 | PT_F68, |
| 203 | PT_F69, |
| 204 | PT_F70, |
| 205 | PT_F71, |
| 206 | PT_F72, |
| 207 | PT_F73, |
| 208 | PT_F74, |
| 209 | PT_F75, |
| 210 | PT_F76, |
| 211 | PT_F77, |
| 212 | PT_F78, |
| 213 | PT_F79, |
| 214 | PT_F80, |
| 215 | PT_F81, |
| 216 | PT_F82, |
| 217 | PT_F83, |
| 218 | PT_F84, |
| 219 | PT_F85, |
| 220 | PT_F86, |
| 221 | PT_F87, |
| 222 | PT_F88, |
| 223 | PT_F89, |
| 224 | PT_F90, |
| 225 | PT_F91, |
| 226 | PT_F92, |
| 227 | PT_F93, |
| 228 | PT_F94, |
| 229 | PT_F95, |
| 230 | PT_F96, |
| 231 | PT_F97, |
| 232 | PT_F98, |
| 233 | PT_F99, |
| 234 | PT_F100, |
| 235 | PT_F101, |
| 236 | PT_F102, |
| 237 | PT_F103, |
| 238 | PT_F104, |
| 239 | PT_F105, |
| 240 | PT_F106, |
| 241 | PT_F107, |
| 242 | PT_F108, |
| 243 | PT_F109, |
| 244 | PT_F110, |
| 245 | PT_F111, |
| 246 | PT_F112, |
| 247 | PT_F113, |
| 248 | PT_F114, |
| 249 | PT_F115, |
| 250 | PT_F116, |
| 251 | PT_F117, |
| 252 | PT_F118, |
| 253 | PT_F119, |
| 254 | PT_F120, |
| 255 | PT_F121, |
| 256 | PT_F122, |
| 257 | PT_F123, |
| 258 | PT_F124, |
| 259 | PT_F125, |
| 260 | PT_F126, |
| 261 | PT_F127, |
| 262 | /* Predicate registers - we don't fetch these individually. */ |
| 263 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 264 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 265 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 266 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 267 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 268 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 269 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 270 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 271 | /* branch registers */ |
| 272 | PT_B0, |
| 273 | PT_B1, |
| 274 | PT_B2, |
| 275 | PT_B3, |
| 276 | PT_B4, |
| 277 | PT_B5, |
| 278 | PT_B6, |
| 279 | PT_B7, |
| 280 | /* Virtual frame pointer and virtual return address pointer. */ |
| 281 | -1, -1, |
| 282 | /* other registers */ |
| 283 | PT_PR, |
| 284 | PT_CR_IIP, /* ip */ |
| 285 | PT_CR_IPSR, /* psr */ |
| 286 | PT_CFM, /* cfm */ |
| 287 | /* kernel registers not visible via ptrace interface (?) */ |
| 288 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 289 | /* hole */ |
| 290 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 291 | PT_AR_RSC, |
| 292 | PT_AR_BSP, |
| 293 | PT_AR_BSPSTORE, |
| 294 | PT_AR_RNAT, |
| 295 | -1, |
| 296 | -1, /* Not available: FCR, IA32 floating control register. */ |
| 297 | -1, -1, |
| 298 | -1, /* Not available: EFLAG */ |
| 299 | -1, /* Not available: CSD */ |
| 300 | -1, /* Not available: SSD */ |
| 301 | -1, /* Not available: CFLG */ |
| 302 | -1, /* Not available: FSR */ |
| 303 | -1, /* Not available: FIR */ |
| 304 | -1, /* Not available: FDR */ |
| 305 | -1, |
| 306 | PT_AR_CCV, |
| 307 | -1, -1, -1, |
| 308 | PT_AR_UNAT, |
| 309 | -1, -1, -1, |
| 310 | PT_AR_FPSR, |
| 311 | -1, -1, -1, |
| 312 | -1, /* Not available: ITC */ |
| 313 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 314 | -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 315 | PT_AR_PFS, |
| 316 | PT_AR_LC, |
| 317 | PT_AR_EC, |
| 318 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 319 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 320 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 321 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 322 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 323 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 324 | -1, |
| 325 | /* nat bits - not fetched directly; instead we obtain these bits from |
| 326 | either rnat or unat or from memory. */ |
| 327 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 328 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 329 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 330 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 331 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 332 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 333 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 334 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 335 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 336 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 337 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 338 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 339 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 340 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 341 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 342 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 343 | }; |
| 344 | |
| 345 | static CORE_ADDR |
| 346 | ia64_register_addr (struct gdbarch *gdbarch, int regno) |
| 347 | { |
| 348 | CORE_ADDR addr; |
| 349 | |
| 350 | if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
| 351 | error (_("Invalid register number %d."), regno); |
| 352 | |
| 353 | if (u_offsets[regno] == -1) |
| 354 | addr = 0; |
| 355 | else |
| 356 | addr = (CORE_ADDR) u_offsets[regno]; |
| 357 | |
| 358 | return addr; |
| 359 | } |
| 360 | |
| 361 | static int |
| 362 | ia64_cannot_fetch_register (struct gdbarch *gdbarch, int regno) |
| 363 | { |
| 364 | return regno < 0 |
| 365 | || regno >= gdbarch_num_regs (gdbarch) |
| 366 | || u_offsets[regno] == -1; |
| 367 | } |
| 368 | |
| 369 | static int |
| 370 | ia64_cannot_store_register (struct gdbarch *gdbarch, int regno) |
| 371 | { |
| 372 | /* Rationale behind not permitting stores to bspstore... |
| 373 | |
| 374 | The IA-64 architecture provides bspstore and bsp which refer |
| 375 | memory locations in the RSE's backing store. bspstore is the |
| 376 | next location which will be written when the RSE needs to write |
| 377 | to memory. bsp is the address at which r32 in the current frame |
| 378 | would be found if it were written to the backing store. |
| 379 | |
| 380 | The IA-64 architecture provides read-only access to bsp and |
| 381 | read/write access to bspstore (but only when the RSE is in |
| 382 | the enforced lazy mode). It should be noted that stores |
| 383 | to bspstore also affect the value of bsp. Changing bspstore |
| 384 | does not affect the number of dirty entries between bspstore |
| 385 | and bsp, so changing bspstore by N words will also cause bsp |
| 386 | to be changed by (roughly) N as well. (It could be N-1 or N+1 |
| 387 | depending upon where the NaT collection bits fall.) |
| 388 | |
| 389 | OTOH, the Linux kernel provides read/write access to bsp (and |
| 390 | currently read/write access to bspstore as well). But it |
| 391 | is definitely the case that if you change one, the other |
| 392 | will change at the same time. It is more useful to gdb to |
| 393 | be able to change bsp. So in order to prevent strange and |
| 394 | undesirable things from happening when a dummy stack frame |
| 395 | is popped (after calling an inferior function), we allow |
| 396 | bspstore to be read, but not written. (Note that popping |
| 397 | a (generic) dummy stack frame causes all registers that |
| 398 | were previously read from the inferior process to be written |
| 399 | back.) */ |
| 400 | |
| 401 | return regno < 0 |
| 402 | || regno >= gdbarch_num_regs (gdbarch) |
| 403 | || u_offsets[regno] == -1 |
| 404 | || regno == IA64_BSPSTORE_REGNUM; |
| 405 | } |
| 406 | |
| 407 | void |
| 408 | supply_gregset (struct regcache *regcache, const gregset_t *gregsetp) |
| 409 | { |
| 410 | int regi; |
| 411 | const greg_t *regp = (const greg_t *) gregsetp; |
| 412 | |
| 413 | for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++) |
| 414 | { |
| 415 | regcache->raw_supply (regi, regp + (regi - IA64_GR0_REGNUM)); |
| 416 | } |
| 417 | |
| 418 | /* FIXME: NAT collection bits are at index 32; gotta deal with these |
| 419 | somehow... */ |
| 420 | |
| 421 | regcache->raw_supply (IA64_PR_REGNUM, regp + 33); |
| 422 | |
| 423 | for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++) |
| 424 | { |
| 425 | regcache->raw_supply (regi, regp + 34 + (regi - IA64_BR0_REGNUM)); |
| 426 | } |
| 427 | |
| 428 | regcache->raw_supply (IA64_IP_REGNUM, regp + 42); |
| 429 | regcache->raw_supply (IA64_CFM_REGNUM, regp + 43); |
| 430 | regcache->raw_supply (IA64_PSR_REGNUM, regp + 44); |
| 431 | regcache->raw_supply (IA64_RSC_REGNUM, regp + 45); |
| 432 | regcache->raw_supply (IA64_BSP_REGNUM, regp + 46); |
| 433 | regcache->raw_supply (IA64_BSPSTORE_REGNUM, regp + 47); |
| 434 | regcache->raw_supply (IA64_RNAT_REGNUM, regp + 48); |
| 435 | regcache->raw_supply (IA64_CCV_REGNUM, regp + 49); |
| 436 | regcache->raw_supply (IA64_UNAT_REGNUM, regp + 50); |
| 437 | regcache->raw_supply (IA64_FPSR_REGNUM, regp + 51); |
| 438 | regcache->raw_supply (IA64_PFS_REGNUM, regp + 52); |
| 439 | regcache->raw_supply (IA64_LC_REGNUM, regp + 53); |
| 440 | regcache->raw_supply (IA64_EC_REGNUM, regp + 54); |
| 441 | } |
| 442 | |
| 443 | void |
| 444 | fill_gregset (const struct regcache *regcache, gregset_t *gregsetp, int regno) |
| 445 | { |
| 446 | int regi; |
| 447 | greg_t *regp = (greg_t *) gregsetp; |
| 448 | |
| 449 | #define COPY_REG(_idx_,_regi_) \ |
| 450 | if ((regno == -1) || regno == _regi_) \ |
| 451 | regcache->raw_collect (_regi_, regp + _idx_) |
| 452 | |
| 453 | for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++) |
| 454 | { |
| 455 | COPY_REG (regi - IA64_GR0_REGNUM, regi); |
| 456 | } |
| 457 | |
| 458 | /* FIXME: NAT collection bits at index 32? */ |
| 459 | |
| 460 | COPY_REG (33, IA64_PR_REGNUM); |
| 461 | |
| 462 | for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++) |
| 463 | { |
| 464 | COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi); |
| 465 | } |
| 466 | |
| 467 | COPY_REG (42, IA64_IP_REGNUM); |
| 468 | COPY_REG (43, IA64_CFM_REGNUM); |
| 469 | COPY_REG (44, IA64_PSR_REGNUM); |
| 470 | COPY_REG (45, IA64_RSC_REGNUM); |
| 471 | COPY_REG (46, IA64_BSP_REGNUM); |
| 472 | COPY_REG (47, IA64_BSPSTORE_REGNUM); |
| 473 | COPY_REG (48, IA64_RNAT_REGNUM); |
| 474 | COPY_REG (49, IA64_CCV_REGNUM); |
| 475 | COPY_REG (50, IA64_UNAT_REGNUM); |
| 476 | COPY_REG (51, IA64_FPSR_REGNUM); |
| 477 | COPY_REG (52, IA64_PFS_REGNUM); |
| 478 | COPY_REG (53, IA64_LC_REGNUM); |
| 479 | COPY_REG (54, IA64_EC_REGNUM); |
| 480 | } |
| 481 | |
| 482 | /* Given a pointer to a floating point register set in /proc format |
| 483 | (fpregset_t *), unpack the register contents and supply them as gdb's |
| 484 | idea of the current floating point register values. */ |
| 485 | |
| 486 | void |
| 487 | supply_fpregset (struct regcache *regcache, const fpregset_t *fpregsetp) |
| 488 | { |
| 489 | int regi; |
| 490 | const char *from; |
| 491 | const gdb_byte f_zero[16] = { 0 }; |
| 492 | const gdb_byte f_one[16] = |
| 493 | { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 }; |
| 494 | |
| 495 | /* Kernel generated cores have fr1==0 instead of 1.0. Older GDBs |
| 496 | did the same. So ignore whatever might be recorded in fpregset_t |
| 497 | for fr0/fr1 and always supply their expected values. */ |
| 498 | |
| 499 | /* fr0 is always read as zero. */ |
| 500 | regcache->raw_supply (IA64_FR0_REGNUM, f_zero); |
| 501 | /* fr1 is always read as one (1.0). */ |
| 502 | regcache->raw_supply (IA64_FR1_REGNUM, f_one); |
| 503 | |
| 504 | for (regi = IA64_FR2_REGNUM; regi <= IA64_FR127_REGNUM; regi++) |
| 505 | { |
| 506 | from = (const char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]); |
| 507 | regcache->raw_supply (regi, from); |
| 508 | } |
| 509 | } |
| 510 | |
| 511 | /* Given a pointer to a floating point register set in /proc format |
| 512 | (fpregset_t *), update the register specified by REGNO from gdb's idea |
| 513 | of the current floating point register set. If REGNO is -1, update |
| 514 | them all. */ |
| 515 | |
| 516 | void |
| 517 | fill_fpregset (const struct regcache *regcache, |
| 518 | fpregset_t *fpregsetp, int regno) |
| 519 | { |
| 520 | int regi; |
| 521 | |
| 522 | for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++) |
| 523 | { |
| 524 | if ((regno == -1) || (regno == regi)) |
| 525 | regcache->raw_collect (regi, &((*fpregsetp)[regi - IA64_FR0_REGNUM])); |
| 526 | } |
| 527 | } |
| 528 | |
| 529 | #define IA64_PSR_DB (1UL << 24) |
| 530 | #define IA64_PSR_DD (1UL << 39) |
| 531 | |
| 532 | static void |
| 533 | enable_watchpoints_in_psr (ptid_t ptid) |
| 534 | { |
| 535 | struct regcache *regcache = get_thread_regcache (ptid); |
| 536 | ULONGEST psr; |
| 537 | |
| 538 | regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr); |
| 539 | if (!(psr & IA64_PSR_DB)) |
| 540 | { |
| 541 | psr |= IA64_PSR_DB; /* Set the db bit - this enables hardware |
| 542 | watchpoints and breakpoints. */ |
| 543 | regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr); |
| 544 | } |
| 545 | } |
| 546 | |
| 547 | static long debug_registers[8]; |
| 548 | |
| 549 | static void |
| 550 | store_debug_register (ptid_t ptid, int idx, long val) |
| 551 | { |
| 552 | int tid; |
| 553 | |
| 554 | tid = ptid.lwp (); |
| 555 | if (tid == 0) |
| 556 | tid = ptid.pid (); |
| 557 | |
| 558 | (void) ptrace (PT_WRITE_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), val); |
| 559 | } |
| 560 | |
| 561 | static void |
| 562 | store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, |
| 563 | long *dbr_mask) |
| 564 | { |
| 565 | if (dbr_addr) |
| 566 | store_debug_register (ptid, 2 * idx, *dbr_addr); |
| 567 | if (dbr_mask) |
| 568 | store_debug_register (ptid, 2 * idx + 1, *dbr_mask); |
| 569 | } |
| 570 | |
| 571 | static int |
| 572 | is_power_of_2 (int val) |
| 573 | { |
| 574 | int i, onecount; |
| 575 | |
| 576 | onecount = 0; |
| 577 | for (i = 0; i < 8 * sizeof (val); i++) |
| 578 | if (val & (1 << i)) |
| 579 | onecount++; |
| 580 | |
| 581 | return onecount <= 1; |
| 582 | } |
| 583 | |
| 584 | int |
| 585 | ia64_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, |
| 586 | enum target_hw_bp_type type, |
| 587 | struct expression *cond) |
| 588 | { |
| 589 | struct lwp_info *lp; |
| 590 | int idx; |
| 591 | long dbr_addr, dbr_mask; |
| 592 | int max_watchpoints = 4; |
| 593 | |
| 594 | if (len <= 0 || !is_power_of_2 (len)) |
| 595 | return -1; |
| 596 | |
| 597 | for (idx = 0; idx < max_watchpoints; idx++) |
| 598 | { |
| 599 | dbr_mask = debug_registers[idx * 2 + 1]; |
| 600 | if ((dbr_mask & (0x3UL << 62)) == 0) |
| 601 | { |
| 602 | /* Exit loop if both r and w bits clear. */ |
| 603 | break; |
| 604 | } |
| 605 | } |
| 606 | |
| 607 | if (idx == max_watchpoints) |
| 608 | return -1; |
| 609 | |
| 610 | dbr_addr = (long) addr; |
| 611 | dbr_mask = (~(len - 1) & 0x00ffffffffffffffL); /* construct mask to match */ |
| 612 | dbr_mask |= 0x0800000000000000L; /* Only match privilege level 3 */ |
| 613 | switch (type) |
| 614 | { |
| 615 | case hw_write: |
| 616 | dbr_mask |= (1L << 62); /* Set w bit */ |
| 617 | break; |
| 618 | case hw_read: |
| 619 | dbr_mask |= (1L << 63); /* Set r bit */ |
| 620 | break; |
| 621 | case hw_access: |
| 622 | dbr_mask |= (3L << 62); /* Set both r and w bits */ |
| 623 | break; |
| 624 | default: |
| 625 | return -1; |
| 626 | } |
| 627 | |
| 628 | debug_registers[2 * idx] = dbr_addr; |
| 629 | debug_registers[2 * idx + 1] = dbr_mask; |
| 630 | ALL_LWPS (lp) |
| 631 | { |
| 632 | store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask); |
| 633 | enable_watchpoints_in_psr (lp->ptid); |
| 634 | } |
| 635 | |
| 636 | return 0; |
| 637 | } |
| 638 | |
| 639 | int |
| 640 | ia64_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len, |
| 641 | enum target_hw_bp_type type, |
| 642 | struct expression *cond) |
| 643 | { |
| 644 | int idx; |
| 645 | long dbr_addr, dbr_mask; |
| 646 | int max_watchpoints = 4; |
| 647 | |
| 648 | if (len <= 0 || !is_power_of_2 (len)) |
| 649 | return -1; |
| 650 | |
| 651 | for (idx = 0; idx < max_watchpoints; idx++) |
| 652 | { |
| 653 | dbr_addr = debug_registers[2 * idx]; |
| 654 | dbr_mask = debug_registers[2 * idx + 1]; |
| 655 | if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr) |
| 656 | { |
| 657 | struct lwp_info *lp; |
| 658 | |
| 659 | debug_registers[2 * idx] = 0; |
| 660 | debug_registers[2 * idx + 1] = 0; |
| 661 | dbr_addr = 0; |
| 662 | dbr_mask = 0; |
| 663 | |
| 664 | ALL_LWPS (lp) |
| 665 | store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask); |
| 666 | |
| 667 | return 0; |
| 668 | } |
| 669 | } |
| 670 | return -1; |
| 671 | } |
| 672 | |
| 673 | void |
| 674 | ia64_linux_nat_target::low_new_thread (struct lwp_info *lp) |
| 675 | { |
| 676 | int i, any; |
| 677 | |
| 678 | any = 0; |
| 679 | for (i = 0; i < 8; i++) |
| 680 | { |
| 681 | if (debug_registers[i] != 0) |
| 682 | any = 1; |
| 683 | store_debug_register (lp->ptid, i, debug_registers[i]); |
| 684 | } |
| 685 | |
| 686 | if (any) |
| 687 | enable_watchpoints_in_psr (lp->ptid); |
| 688 | } |
| 689 | |
| 690 | bool |
| 691 | ia64_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p) |
| 692 | { |
| 693 | CORE_ADDR psr; |
| 694 | siginfo_t siginfo; |
| 695 | struct regcache *regcache = get_current_regcache (); |
| 696 | |
| 697 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) |
| 698 | return false; |
| 699 | |
| 700 | if (siginfo.si_signo != SIGTRAP |
| 701 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) |
| 702 | return false; |
| 703 | |
| 704 | regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr); |
| 705 | psr |= IA64_PSR_DD; /* Set the dd bit - this will disable the watchpoint |
| 706 | for the next instruction. */ |
| 707 | regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr); |
| 708 | |
| 709 | *addr_p = (CORE_ADDR) siginfo.si_addr; |
| 710 | return true; |
| 711 | } |
| 712 | |
| 713 | bool |
| 714 | ia64_linux_nat_target::stopped_by_watchpoint () |
| 715 | { |
| 716 | CORE_ADDR addr; |
| 717 | return stopped_data_address (&addr); |
| 718 | } |
| 719 | |
| 720 | int |
| 721 | ia64_linux_nat_target::can_use_hw_breakpoint (enum bptype type, |
| 722 | int cnt, int othertype) |
| 723 | { |
| 724 | return 1; |
| 725 | } |
| 726 | |
| 727 | |
| 728 | /* Fetch register REGNUM from the inferior. */ |
| 729 | |
| 730 | static void |
| 731 | ia64_linux_fetch_register (struct regcache *regcache, int regnum) |
| 732 | { |
| 733 | struct gdbarch *gdbarch = regcache->arch (); |
| 734 | CORE_ADDR addr; |
| 735 | size_t size; |
| 736 | PTRACE_TYPE_RET *buf; |
| 737 | pid_t pid; |
| 738 | int i; |
| 739 | |
| 740 | /* r0 cannot be fetched but is always zero. */ |
| 741 | if (regnum == IA64_GR0_REGNUM) |
| 742 | { |
| 743 | const gdb_byte zero[8] = { 0 }; |
| 744 | |
| 745 | gdb_assert (sizeof (zero) == register_size (gdbarch, regnum)); |
| 746 | regcache->raw_supply (regnum, zero); |
| 747 | return; |
| 748 | } |
| 749 | |
| 750 | /* fr0 cannot be fetched but is always zero. */ |
| 751 | if (regnum == IA64_FR0_REGNUM) |
| 752 | { |
| 753 | const gdb_byte f_zero[16] = { 0 }; |
| 754 | |
| 755 | gdb_assert (sizeof (f_zero) == register_size (gdbarch, regnum)); |
| 756 | regcache->raw_supply (regnum, f_zero); |
| 757 | return; |
| 758 | } |
| 759 | |
| 760 | /* fr1 cannot be fetched but is always one (1.0). */ |
| 761 | if (regnum == IA64_FR1_REGNUM) |
| 762 | { |
| 763 | const gdb_byte f_one[16] = |
| 764 | { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 }; |
| 765 | |
| 766 | gdb_assert (sizeof (f_one) == register_size (gdbarch, regnum)); |
| 767 | regcache->raw_supply (regnum, f_one); |
| 768 | return; |
| 769 | } |
| 770 | |
| 771 | if (ia64_cannot_fetch_register (gdbarch, regnum)) |
| 772 | { |
| 773 | regcache->raw_supply (regnum, NULL); |
| 774 | return; |
| 775 | } |
| 776 | |
| 777 | pid = get_ptrace_pid (regcache->ptid ()); |
| 778 | |
| 779 | /* This isn't really an address, but ptrace thinks of it as one. */ |
| 780 | addr = ia64_register_addr (gdbarch, regnum); |
| 781 | size = register_size (gdbarch, regnum); |
| 782 | |
| 783 | gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0); |
| 784 | buf = (PTRACE_TYPE_RET *) alloca (size); |
| 785 | |
| 786 | /* Read the register contents from the inferior a chunk at a time. */ |
| 787 | for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++) |
| 788 | { |
| 789 | errno = 0; |
| 790 | buf[i] = ptrace (PT_READ_U, pid, (PTRACE_TYPE_ARG3)addr, 0); |
| 791 | if (errno != 0) |
| 792 | error (_("Couldn't read register %s (#%d): %s."), |
| 793 | gdbarch_register_name (gdbarch, regnum), |
| 794 | regnum, safe_strerror (errno)); |
| 795 | |
| 796 | addr += sizeof (PTRACE_TYPE_RET); |
| 797 | } |
| 798 | regcache->raw_supply (regnum, buf); |
| 799 | } |
| 800 | |
| 801 | /* Fetch register REGNUM from the inferior. If REGNUM is -1, do this |
| 802 | for all registers. */ |
| 803 | |
| 804 | void |
| 805 | ia64_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum) |
| 806 | { |
| 807 | if (regnum == -1) |
| 808 | for (regnum = 0; |
| 809 | regnum < gdbarch_num_regs (regcache->arch ()); |
| 810 | regnum++) |
| 811 | ia64_linux_fetch_register (regcache, regnum); |
| 812 | else |
| 813 | ia64_linux_fetch_register (regcache, regnum); |
| 814 | } |
| 815 | |
| 816 | /* Store register REGNUM into the inferior. */ |
| 817 | |
| 818 | static void |
| 819 | ia64_linux_store_register (const struct regcache *regcache, int regnum) |
| 820 | { |
| 821 | struct gdbarch *gdbarch = regcache->arch (); |
| 822 | CORE_ADDR addr; |
| 823 | size_t size; |
| 824 | PTRACE_TYPE_RET *buf; |
| 825 | pid_t pid; |
| 826 | int i; |
| 827 | |
| 828 | if (ia64_cannot_store_register (gdbarch, regnum)) |
| 829 | return; |
| 830 | |
| 831 | pid = get_ptrace_pid (regcache->ptid ()); |
| 832 | |
| 833 | /* This isn't really an address, but ptrace thinks of it as one. */ |
| 834 | addr = ia64_register_addr (gdbarch, regnum); |
| 835 | size = register_size (gdbarch, regnum); |
| 836 | |
| 837 | gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0); |
| 838 | buf = (PTRACE_TYPE_RET *) alloca (size); |
| 839 | |
| 840 | /* Write the register contents into the inferior a chunk at a time. */ |
| 841 | regcache->raw_collect (regnum, buf); |
| 842 | for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++) |
| 843 | { |
| 844 | errno = 0; |
| 845 | ptrace (PT_WRITE_U, pid, (PTRACE_TYPE_ARG3)addr, buf[i]); |
| 846 | if (errno != 0) |
| 847 | error (_("Couldn't write register %s (#%d): %s."), |
| 848 | gdbarch_register_name (gdbarch, regnum), |
| 849 | regnum, safe_strerror (errno)); |
| 850 | |
| 851 | addr += sizeof (PTRACE_TYPE_RET); |
| 852 | } |
| 853 | } |
| 854 | |
| 855 | /* Store register REGNUM back into the inferior. If REGNUM is -1, do |
| 856 | this for all registers. */ |
| 857 | |
| 858 | void |
| 859 | ia64_linux_nat_target::store_registers (struct regcache *regcache, int regnum) |
| 860 | { |
| 861 | if (regnum == -1) |
| 862 | for (regnum = 0; |
| 863 | regnum < gdbarch_num_regs (regcache->arch ()); |
| 864 | regnum++) |
| 865 | ia64_linux_store_register (regcache, regnum); |
| 866 | else |
| 867 | ia64_linux_store_register (regcache, regnum); |
| 868 | } |
| 869 | |
| 870 | /* Implement the xfer_partial target_ops method. */ |
| 871 | |
| 872 | enum target_xfer_status |
| 873 | ia64_linux_nat_target::xfer_partial (enum target_object object, |
| 874 | const char *annex, |
| 875 | gdb_byte *readbuf, const gdb_byte *writebuf, |
| 876 | ULONGEST offset, ULONGEST len, |
| 877 | ULONGEST *xfered_len) |
| 878 | { |
| 879 | if (object == TARGET_OBJECT_UNWIND_TABLE && readbuf != NULL) |
| 880 | { |
| 881 | static long gate_table_size; |
| 882 | gdb_byte *tmp_buf; |
| 883 | long res; |
| 884 | |
| 885 | /* Probe for the table size once. */ |
| 886 | if (gate_table_size == 0) |
| 887 | gate_table_size = syscall (__NR_getunwind, NULL, 0); |
| 888 | if (gate_table_size < 0) |
| 889 | return TARGET_XFER_E_IO; |
| 890 | |
| 891 | if (offset >= gate_table_size) |
| 892 | return TARGET_XFER_EOF; |
| 893 | |
| 894 | tmp_buf = (gdb_byte *) alloca (gate_table_size); |
| 895 | res = syscall (__NR_getunwind, tmp_buf, gate_table_size); |
| 896 | if (res < 0) |
| 897 | return TARGET_XFER_E_IO; |
| 898 | gdb_assert (res == gate_table_size); |
| 899 | |
| 900 | if (offset + len > gate_table_size) |
| 901 | len = gate_table_size - offset; |
| 902 | |
| 903 | memcpy (readbuf, tmp_buf + offset, len); |
| 904 | *xfered_len = len; |
| 905 | return TARGET_XFER_OK; |
| 906 | } |
| 907 | |
| 908 | return linux_nat_target::xfer_partial (object, annex, readbuf, writebuf, |
| 909 | offset, len, xfered_len); |
| 910 | } |
| 911 | |
| 912 | /* For break.b instruction ia64 CPU forgets the immediate value and generates |
| 913 | SIGILL with ILL_ILLOPC instead of more common SIGTRAP with TRAP_BRKPT. |
| 914 | ia64 does not use gdbarch_decr_pc_after_break so we do not have to make any |
| 915 | difference for the signals here. */ |
| 916 | |
| 917 | bool |
| 918 | ia64_linux_nat_target::low_status_is_event (int status) |
| 919 | { |
| 920 | return WIFSTOPPED (status) && (WSTOPSIG (status) == SIGTRAP |
| 921 | || WSTOPSIG (status) == SIGILL); |
| 922 | } |
| 923 | |
| 924 | void _initialize_ia64_linux_nat (); |
| 925 | void |
| 926 | _initialize_ia64_linux_nat () |
| 927 | { |
| 928 | /* Register the target. */ |
| 929 | linux_target = &the_ia64_linux_nat_target; |
| 930 | add_inf_child_target (&the_ia64_linux_nat_target); |
| 931 | } |