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1/* Target-dependent code for the IA-64 for GDB, the GNU debugger.
2
3 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
4 2009, 2010, 2011 Free Software Foundation, Inc.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21#include "defs.h"
22#include "inferior.h"
23#include "gdbcore.h"
24#include "arch-utils.h"
25#include "floatformat.h"
26#include "gdbtypes.h"
27#include "regcache.h"
28#include "reggroups.h"
29#include "frame.h"
30#include "frame-base.h"
31#include "frame-unwind.h"
32#include "doublest.h"
33#include "value.h"
34#include "gdb_assert.h"
35#include "objfiles.h"
36#include "elf/common.h" /* for DT_PLTGOT value */
37#include "elf-bfd.h"
38#include "dis-asm.h"
39#include "infcall.h"
40#include "osabi.h"
41#include "ia64-tdep.h"
42#include "cp-abi.h"
43
44#ifdef HAVE_LIBUNWIND_IA64_H
45#include "elf/ia64.h" /* for PT_IA_64_UNWIND value */
46#include "libunwind-frame.h"
47#include "libunwind-ia64.h"
48
49/* Note: KERNEL_START is supposed to be an address which is not going
50 to ever contain any valid unwind info. For ia64 linux, the choice
51 of 0xc000000000000000 is fairly safe since that's uncached space.
52
53 We use KERNEL_START as follows: after obtaining the kernel's
54 unwind table via getunwind(), we project its unwind data into
55 address-range KERNEL_START-(KERNEL_START+ktab_size) and then
56 when ia64_access_mem() sees a memory access to this
57 address-range, we redirect it to ktab instead.
58
59 None of this hackery is needed with a modern kernel/libcs
60 which uses the kernel virtual DSO to provide access to the
61 kernel's unwind info. In that case, ktab_size remains 0 and
62 hence the value of KERNEL_START doesn't matter. */
63
64#define KERNEL_START 0xc000000000000000ULL
65
66static size_t ktab_size = 0;
67struct ia64_table_entry
68 {
69 uint64_t start_offset;
70 uint64_t end_offset;
71 uint64_t info_offset;
72 };
73
74static struct ia64_table_entry *ktab = NULL;
75
76#endif
77
78/* An enumeration of the different IA-64 instruction types. */
79
80typedef enum instruction_type
81{
82 A, /* Integer ALU ; I-unit or M-unit */
83 I, /* Non-ALU integer; I-unit */
84 M, /* Memory ; M-unit */
85 F, /* Floating-point ; F-unit */
86 B, /* Branch ; B-unit */
87 L, /* Extended (L+X) ; I-unit */
88 X, /* Extended (L+X) ; I-unit */
89 undefined /* undefined or reserved */
90} instruction_type;
91
92/* We represent IA-64 PC addresses as the value of the instruction
93 pointer or'd with some bit combination in the low nibble which
94 represents the slot number in the bundle addressed by the
95 instruction pointer. The problem is that the Linux kernel
96 multiplies its slot numbers (for exceptions) by one while the
97 disassembler multiplies its slot numbers by 6. In addition, I've
98 heard it said that the simulator uses 1 as the multiplier.
99
100 I've fixed the disassembler so that the bytes_per_line field will
101 be the slot multiplier. If bytes_per_line comes in as zero, it
102 is set to six (which is how it was set up initially). -- objdump
103 displays pretty disassembly dumps with this value. For our purposes,
104 we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we
105 never want to also display the raw bytes the way objdump does. */
106
107#define SLOT_MULTIPLIER 1
108
109/* Length in bytes of an instruction bundle. */
110
111#define BUNDLE_LEN 16
112
113/* See the saved memory layout comment for ia64_memory_insert_breakpoint. */
114
115#if BREAKPOINT_MAX < BUNDLE_LEN - 2
116# error "BREAKPOINT_MAX < BUNDLE_LEN - 2"
117#endif
118
119static gdbarch_init_ftype ia64_gdbarch_init;
120
121static gdbarch_register_name_ftype ia64_register_name;
122static gdbarch_register_type_ftype ia64_register_type;
123static gdbarch_breakpoint_from_pc_ftype ia64_breakpoint_from_pc;
124static gdbarch_skip_prologue_ftype ia64_skip_prologue;
125static struct type *is_float_or_hfa_type (struct type *t);
126static CORE_ADDR ia64_find_global_pointer (struct gdbarch *gdbarch,
127 CORE_ADDR faddr);
128
129#define NUM_IA64_RAW_REGS 462
130
131static int sp_regnum = IA64_GR12_REGNUM;
132static int fp_regnum = IA64_VFP_REGNUM;
133static int lr_regnum = IA64_VRAP_REGNUM;
134
135/* NOTE: we treat the register stack registers r32-r127 as
136 pseudo-registers because they may not be accessible via the ptrace
137 register get/set interfaces. */
138
139enum pseudo_regs { FIRST_PSEUDO_REGNUM = NUM_IA64_RAW_REGS,
140 VBOF_REGNUM = IA64_NAT127_REGNUM + 1, V32_REGNUM,
141 V127_REGNUM = V32_REGNUM + 95,
142 VP0_REGNUM, VP16_REGNUM = VP0_REGNUM + 16,
143 VP63_REGNUM = VP0_REGNUM + 63, LAST_PSEUDO_REGNUM };
144
145/* Array of register names; There should be ia64_num_regs strings in
146 the initializer. */
147
148static char *ia64_register_names[] =
149{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
150 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
151 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
152 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
153 "", "", "", "", "", "", "", "",
154 "", "", "", "", "", "", "", "",
155 "", "", "", "", "", "", "", "",
156 "", "", "", "", "", "", "", "",
157 "", "", "", "", "", "", "", "",
158 "", "", "", "", "", "", "", "",
159 "", "", "", "", "", "", "", "",
160 "", "", "", "", "", "", "", "",
161 "", "", "", "", "", "", "", "",
162 "", "", "", "", "", "", "", "",
163 "", "", "", "", "", "", "", "",
164 "", "", "", "", "", "", "", "",
165
166 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
167 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
168 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
169 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
170 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
171 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
172 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
173 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
174 "f64", "f65", "f66", "f67", "f68", "f69", "f70", "f71",
175 "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
176 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87",
177 "f88", "f89", "f90", "f91", "f92", "f93", "f94", "f95",
178 "f96", "f97", "f98", "f99", "f100", "f101", "f102", "f103",
179 "f104", "f105", "f106", "f107", "f108", "f109", "f110", "f111",
180 "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
181 "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127",
182
183 "", "", "", "", "", "", "", "",
184 "", "", "", "", "", "", "", "",
185 "", "", "", "", "", "", "", "",
186 "", "", "", "", "", "", "", "",
187 "", "", "", "", "", "", "", "",
188 "", "", "", "", "", "", "", "",
189 "", "", "", "", "", "", "", "",
190 "", "", "", "", "", "", "", "",
191
192 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
193
194 "vfp", "vrap",
195
196 "pr", "ip", "psr", "cfm",
197
198 "kr0", "kr1", "kr2", "kr3", "kr4", "kr5", "kr6", "kr7",
199 "", "", "", "", "", "", "", "",
200 "rsc", "bsp", "bspstore", "rnat",
201 "", "fcr", "", "",
202 "eflag", "csd", "ssd", "cflg", "fsr", "fir", "fdr", "",
203 "ccv", "", "", "", "unat", "", "", "",
204 "fpsr", "", "", "", "itc",
205 "", "", "", "", "", "", "", "", "", "",
206 "", "", "", "", "", "", "", "", "",
207 "pfs", "lc", "ec",
208 "", "", "", "", "", "", "", "", "", "",
209 "", "", "", "", "", "", "", "", "", "",
210 "", "", "", "", "", "", "", "", "", "",
211 "", "", "", "", "", "", "", "", "", "",
212 "", "", "", "", "", "", "", "", "", "",
213 "", "", "", "", "", "", "", "", "", "",
214 "",
215 "nat0", "nat1", "nat2", "nat3", "nat4", "nat5", "nat6", "nat7",
216 "nat8", "nat9", "nat10", "nat11", "nat12", "nat13", "nat14", "nat15",
217 "nat16", "nat17", "nat18", "nat19", "nat20", "nat21", "nat22", "nat23",
218 "nat24", "nat25", "nat26", "nat27", "nat28", "nat29", "nat30", "nat31",
219 "nat32", "nat33", "nat34", "nat35", "nat36", "nat37", "nat38", "nat39",
220 "nat40", "nat41", "nat42", "nat43", "nat44", "nat45", "nat46", "nat47",
221 "nat48", "nat49", "nat50", "nat51", "nat52", "nat53", "nat54", "nat55",
222 "nat56", "nat57", "nat58", "nat59", "nat60", "nat61", "nat62", "nat63",
223 "nat64", "nat65", "nat66", "nat67", "nat68", "nat69", "nat70", "nat71",
224 "nat72", "nat73", "nat74", "nat75", "nat76", "nat77", "nat78", "nat79",
225 "nat80", "nat81", "nat82", "nat83", "nat84", "nat85", "nat86", "nat87",
226 "nat88", "nat89", "nat90", "nat91", "nat92", "nat93", "nat94", "nat95",
227 "nat96", "nat97", "nat98", "nat99", "nat100","nat101","nat102","nat103",
228 "nat104","nat105","nat106","nat107","nat108","nat109","nat110","nat111",
229 "nat112","nat113","nat114","nat115","nat116","nat117","nat118","nat119",
230 "nat120","nat121","nat122","nat123","nat124","nat125","nat126","nat127",
231
232 "bof",
233
234 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
235 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
236 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
237 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
238 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
239 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
240 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
241 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
242 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
243 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
244 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
245 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
246
247 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7",
248 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15",
249 "p16", "p17", "p18", "p19", "p20", "p21", "p22", "p23",
250 "p24", "p25", "p26", "p27", "p28", "p29", "p30", "p31",
251 "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39",
252 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47",
253 "p48", "p49", "p50", "p51", "p52", "p53", "p54", "p55",
254 "p56", "p57", "p58", "p59", "p60", "p61", "p62", "p63",
255};
256
257struct ia64_frame_cache
258{
259 CORE_ADDR base; /* frame pointer base for frame */
260 CORE_ADDR pc; /* function start pc for frame */
261 CORE_ADDR saved_sp; /* stack pointer for frame */
262 CORE_ADDR bsp; /* points at r32 for the current frame */
263 CORE_ADDR cfm; /* cfm value for current frame */
264 CORE_ADDR prev_cfm; /* cfm value for previous frame */
265 int frameless;
266 int sof; /* Size of frame (decoded from cfm value). */
267 int sol; /* Size of locals (decoded from cfm value). */
268 int sor; /* Number of rotating registers (decoded from
269 cfm value). */
270 CORE_ADDR after_prologue;
271 /* Address of first instruction after the last
272 prologue instruction; Note that there may
273 be instructions from the function's body
274 intermingled with the prologue. */
275 int mem_stack_frame_size;
276 /* Size of the memory stack frame (may be zero),
277 or -1 if it has not been determined yet. */
278 int fp_reg; /* Register number (if any) used a frame pointer
279 for this frame. 0 if no register is being used
280 as the frame pointer. */
281
282 /* Saved registers. */
283 CORE_ADDR saved_regs[NUM_IA64_RAW_REGS];
284
285};
286
287static int
288floatformat_valid (const struct floatformat *fmt, const void *from)
289{
290 return 1;
291}
292
293static const struct floatformat floatformat_ia64_ext =
294{
295 floatformat_little, 82, 0, 1, 17, 65535, 0x1ffff, 18, 64,
296 floatformat_intbit_yes, "floatformat_ia64_ext", floatformat_valid, NULL
297};
298
299static const struct floatformat *floatformats_ia64_ext[2] =
300{
301 &floatformat_ia64_ext,
302 &floatformat_ia64_ext
303};
304
305static struct type *
306ia64_ext_type (struct gdbarch *gdbarch)
307{
308 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
309
310 if (!tdep->ia64_ext_type)
311 tdep->ia64_ext_type
312 = arch_float_type (gdbarch, 128, "builtin_type_ia64_ext",
313 floatformats_ia64_ext);
314
315 return tdep->ia64_ext_type;
316}
317
318static int
319ia64_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
320 struct reggroup *group)
321{
322 int vector_p;
323 int float_p;
324 int raw_p;
325 if (group == all_reggroup)
326 return 1;
327 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
328 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
329 raw_p = regnum < NUM_IA64_RAW_REGS;
330 if (group == float_reggroup)
331 return float_p;
332 if (group == vector_reggroup)
333 return vector_p;
334 if (group == general_reggroup)
335 return (!vector_p && !float_p);
336 if (group == save_reggroup || group == restore_reggroup)
337 return raw_p;
338 return 0;
339}
340
341static const char *
342ia64_register_name (struct gdbarch *gdbarch, int reg)
343{
344 return ia64_register_names[reg];
345}
346
347struct type *
348ia64_register_type (struct gdbarch *arch, int reg)
349{
350 if (reg >= IA64_FR0_REGNUM && reg <= IA64_FR127_REGNUM)
351 return ia64_ext_type (arch);
352 else
353 return builtin_type (arch)->builtin_long;
354}
355
356static int
357ia64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
358{
359 if (reg >= IA64_GR32_REGNUM && reg <= IA64_GR127_REGNUM)
360 return V32_REGNUM + (reg - IA64_GR32_REGNUM);
361 return reg;
362}
363
364
365/* Extract ``len'' bits from an instruction bundle starting at
366 bit ``from''. */
367
368static long long
369extract_bit_field (const char *bundle, int from, int len)
370{
371 long long result = 0LL;
372 int to = from + len;
373 int from_byte = from / 8;
374 int to_byte = to / 8;
375 unsigned char *b = (unsigned char *) bundle;
376 unsigned char c;
377 int lshift;
378 int i;
379
380 c = b[from_byte];
381 if (from_byte == to_byte)
382 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
383 result = c >> (from % 8);
384 lshift = 8 - (from % 8);
385
386 for (i = from_byte+1; i < to_byte; i++)
387 {
388 result |= ((long long) b[i]) << lshift;
389 lshift += 8;
390 }
391
392 if (from_byte < to_byte && (to % 8 != 0))
393 {
394 c = b[to_byte];
395 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
396 result |= ((long long) c) << lshift;
397 }
398
399 return result;
400}
401
402/* Replace the specified bits in an instruction bundle. */
403
404static void
405replace_bit_field (char *bundle, long long val, int from, int len)
406{
407 int to = from + len;
408 int from_byte = from / 8;
409 int to_byte = to / 8;
410 unsigned char *b = (unsigned char *) bundle;
411 unsigned char c;
412
413 if (from_byte == to_byte)
414 {
415 unsigned char left, right;
416 c = b[from_byte];
417 left = (c >> (to % 8)) << (to % 8);
418 right = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
419 c = (unsigned char) (val & 0xff);
420 c = (unsigned char) (c << (from % 8 + 8 - to % 8)) >> (8 - to % 8);
421 c |= right | left;
422 b[from_byte] = c;
423 }
424 else
425 {
426 int i;
427 c = b[from_byte];
428 c = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
429 c = c | (val << (from % 8));
430 b[from_byte] = c;
431 val >>= 8 - from % 8;
432
433 for (i = from_byte+1; i < to_byte; i++)
434 {
435 c = val & 0xff;
436 val >>= 8;
437 b[i] = c;
438 }
439
440 if (to % 8 != 0)
441 {
442 unsigned char cv = (unsigned char) val;
443 c = b[to_byte];
444 c = c >> (to % 8) << (to % 8);
445 c |= ((unsigned char) (cv << (8 - to % 8))) >> (8 - to % 8);
446 b[to_byte] = c;
447 }
448 }
449}
450
451/* Return the contents of slot N (for N = 0, 1, or 2) in
452 and instruction bundle. */
453
454static long long
455slotN_contents (char *bundle, int slotnum)
456{
457 return extract_bit_field (bundle, 5+41*slotnum, 41);
458}
459
460/* Store an instruction in an instruction bundle. */
461
462static void
463replace_slotN_contents (char *bundle, long long instr, int slotnum)
464{
465 replace_bit_field (bundle, instr, 5+41*slotnum, 41);
466}
467
468static const enum instruction_type template_encoding_table[32][3] =
469{
470 { M, I, I }, /* 00 */
471 { M, I, I }, /* 01 */
472 { M, I, I }, /* 02 */
473 { M, I, I }, /* 03 */
474 { M, L, X }, /* 04 */
475 { M, L, X }, /* 05 */
476 { undefined, undefined, undefined }, /* 06 */
477 { undefined, undefined, undefined }, /* 07 */
478 { M, M, I }, /* 08 */
479 { M, M, I }, /* 09 */
480 { M, M, I }, /* 0A */
481 { M, M, I }, /* 0B */
482 { M, F, I }, /* 0C */
483 { M, F, I }, /* 0D */
484 { M, M, F }, /* 0E */
485 { M, M, F }, /* 0F */
486 { M, I, B }, /* 10 */
487 { M, I, B }, /* 11 */
488 { M, B, B }, /* 12 */
489 { M, B, B }, /* 13 */
490 { undefined, undefined, undefined }, /* 14 */
491 { undefined, undefined, undefined }, /* 15 */
492 { B, B, B }, /* 16 */
493 { B, B, B }, /* 17 */
494 { M, M, B }, /* 18 */
495 { M, M, B }, /* 19 */
496 { undefined, undefined, undefined }, /* 1A */
497 { undefined, undefined, undefined }, /* 1B */
498 { M, F, B }, /* 1C */
499 { M, F, B }, /* 1D */
500 { undefined, undefined, undefined }, /* 1E */
501 { undefined, undefined, undefined }, /* 1F */
502};
503
504/* Fetch and (partially) decode an instruction at ADDR and return the
505 address of the next instruction to fetch. */
506
507static CORE_ADDR
508fetch_instruction (CORE_ADDR addr, instruction_type *it, long long *instr)
509{
510 char bundle[BUNDLE_LEN];
511 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
512 long long template;
513 int val;
514
515 /* Warn about slot numbers greater than 2. We used to generate
516 an error here on the assumption that the user entered an invalid
517 address. But, sometimes GDB itself requests an invalid address.
518 This can (easily) happen when execution stops in a function for
519 which there are no symbols. The prologue scanner will attempt to
520 find the beginning of the function - if the nearest symbol
521 happens to not be aligned on a bundle boundary (16 bytes), the
522 resulting starting address will cause GDB to think that the slot
523 number is too large.
524
525 So we warn about it and set the slot number to zero. It is
526 not necessarily a fatal condition, particularly if debugging
527 at the assembly language level. */
528 if (slotnum > 2)
529 {
530 warning (_("Can't fetch instructions for slot numbers greater than 2.\n"
531 "Using slot 0 instead"));
532 slotnum = 0;
533 }
534
535 addr &= ~0x0f;
536
537 val = target_read_memory (addr, bundle, BUNDLE_LEN);
538
539 if (val != 0)
540 return 0;
541
542 *instr = slotN_contents (bundle, slotnum);
543 template = extract_bit_field (bundle, 0, 5);
544 *it = template_encoding_table[(int)template][slotnum];
545
546 if (slotnum == 2 || (slotnum == 1 && *it == L))
547 addr += 16;
548 else
549 addr += (slotnum + 1) * SLOT_MULTIPLIER;
550
551 return addr;
552}
553
554/* There are 5 different break instructions (break.i, break.b,
555 break.m, break.f, and break.x), but they all have the same
556 encoding. (The five bit template in the low five bits of the
557 instruction bundle distinguishes one from another.)
558
559 The runtime architecture manual specifies that break instructions
560 used for debugging purposes must have the upper two bits of the 21
561 bit immediate set to a 0 and a 1 respectively. A breakpoint
562 instruction encodes the most significant bit of its 21 bit
563 immediate at bit 36 of the 41 bit instruction. The penultimate msb
564 is at bit 25 which leads to the pattern below.
565
566 Originally, I had this set up to do, e.g, a "break.i 0x80000" But
567 it turns out that 0x80000 was used as the syscall break in the early
568 simulators. So I changed the pattern slightly to do "break.i 0x080001"
569 instead. But that didn't work either (I later found out that this
570 pattern was used by the simulator that I was using.) So I ended up
571 using the pattern seen below.
572
573 SHADOW_CONTENTS has byte-based addressing (PLACED_ADDRESS and SHADOW_LEN)
574 while we need bit-based addressing as the instructions length is 41 bits and
575 we must not modify/corrupt the adjacent slots in the same bundle.
576 Fortunately we may store larger memory incl. the adjacent bits with the
577 original memory content (not the possibly already stored breakpoints there).
578 We need to be careful in ia64_memory_remove_breakpoint to always restore
579 only the specific bits of this instruction ignoring any adjacent stored
580 bits.
581
582 We use the original addressing with the low nibble in the range <0..2> which
583 gets incorrectly interpreted by generic non-ia64 breakpoint_restore_shadows
584 as the direct byte offset of SHADOW_CONTENTS. We store whole BUNDLE_LEN
585 bytes just without these two possibly skipped bytes to not to exceed to the
586 next bundle.
587
588 If we would like to store the whole bundle to SHADOW_CONTENTS we would have
589 to store already the base address (`address & ~0x0f') into PLACED_ADDRESS.
590 In such case there is no other place where to store
591 SLOTNUM (`adress & 0x0f', value in the range <0..2>). We need to know
592 SLOTNUM in ia64_memory_remove_breakpoint.
593
594 There is one special case where we need to be extra careful:
595 L-X instructions, which are instructions that occupy 2 slots
596 (The L part is always in slot 1, and the X part is always in
597 slot 2). We must refuse to insert breakpoints for an address
598 that points at slot 2 of a bundle where an L-X instruction is
599 present, since there is logically no instruction at that address.
600 However, to make things more interesting, the opcode of L-X
601 instructions is located in slot 2. This means that, to insert
602 a breakpoint at an address that points to slot 1, we actually
603 need to write the breakpoint in slot 2! Slot 1 is actually
604 the extended operand, so writing the breakpoint there would not
605 have the desired effect. Another side-effect of this issue
606 is that we need to make sure that the shadow contents buffer
607 does save byte 15 of our instruction bundle (this is the tail
608 end of slot 2, which wouldn't be saved if we were to insert
609 the breakpoint in slot 1).
610
611 ia64 16-byte bundle layout:
612 | 5 bits | slot 0 with 41 bits | slot 1 with 41 bits | slot 2 with 41 bits |
613
614 The current addressing used by the code below:
615 original PC placed_address placed_size required covered
616 == bp_tgt->shadow_len reqd \subset covered
617 0xABCDE0 0xABCDE0 0x10 <0x0...0x5> <0x0..0xF>
618 0xABCDE1 0xABCDE1 0xF <0x5...0xA> <0x1..0xF>
619 0xABCDE2 0xABCDE2 0xE <0xA...0xF> <0x2..0xF>
620
621 L-X instructions are treated a little specially, as explained above:
622 0xABCDE1 0xABCDE1 0xF <0xA...0xF> <0x1..0xF>
623
624 `objdump -d' and some other tools show a bit unjustified offsets:
625 original PC byte where starts the instruction objdump offset
626 0xABCDE0 0xABCDE0 0xABCDE0
627 0xABCDE1 0xABCDE5 0xABCDE6
628 0xABCDE2 0xABCDEA 0xABCDEC
629 */
630
631#define IA64_BREAKPOINT 0x00003333300LL
632
633static int
634ia64_memory_insert_breakpoint (struct gdbarch *gdbarch,
635 struct bp_target_info *bp_tgt)
636{
637 CORE_ADDR addr = bp_tgt->placed_address;
638 gdb_byte bundle[BUNDLE_LEN];
639 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER, shadow_slotnum;
640 long long instr_breakpoint;
641 int val;
642 int template;
643 struct cleanup *cleanup;
644
645 if (slotnum > 2)
646 error (_("Can't insert breakpoint for slot numbers greater than 2."));
647
648 addr &= ~0x0f;
649
650 /* Enable the automatic memory restoration from breakpoints while
651 we read our instruction bundle for the purpose of SHADOW_CONTENTS.
652 Otherwise, we could possibly store into the shadow parts of the adjacent
653 placed breakpoints. It is due to our SHADOW_CONTENTS overlapping the real
654 breakpoint instruction bits region. */
655 cleanup = make_show_memory_breakpoints_cleanup (0);
656 val = target_read_memory (addr, bundle, BUNDLE_LEN);
657 if (val != 0)
658 {
659 do_cleanups (cleanup);
660 return val;
661 }
662
663 /* SHADOW_SLOTNUM saves the original slot number as expected by the caller
664 for addressing the SHADOW_CONTENTS placement. */
665 shadow_slotnum = slotnum;
666
667 /* Always cover the last byte of the bundle in case we are inserting
668 a breakpoint on an L-X instruction. */
669 bp_tgt->shadow_len = BUNDLE_LEN - shadow_slotnum;
670
671 template = extract_bit_field (bundle, 0, 5);
672 if (template_encoding_table[template][slotnum] == X)
673 {
674 /* X unit types can only be used in slot 2, and are actually
675 part of a 2-slot L-X instruction. We cannot break at this
676 address, as this is the second half of an instruction that
677 lives in slot 1 of that bundle. */
678 gdb_assert (slotnum == 2);
679 error (_("Can't insert breakpoint for non-existing slot X"));
680 }
681 if (template_encoding_table[template][slotnum] == L)
682 {
683 /* L unit types can only be used in slot 1. But the associated
684 opcode for that instruction is in slot 2, so bump the slot number
685 accordingly. */
686 gdb_assert (slotnum == 1);
687 slotnum = 2;
688 }
689
690 /* Store the whole bundle, except for the initial skipped bytes by the slot
691 number interpreted as bytes offset in PLACED_ADDRESS. */
692 memcpy (bp_tgt->shadow_contents, bundle + shadow_slotnum,
693 bp_tgt->shadow_len);
694
695 /* Re-read the same bundle as above except that, this time, read it in order
696 to compute the new bundle inside which we will be inserting the
697 breakpoint. Therefore, disable the automatic memory restoration from
698 breakpoints while we read our instruction bundle. Otherwise, the general
699 restoration mechanism kicks in and we would possibly remove parts of the
700 adjacent placed breakpoints. It is due to our SHADOW_CONTENTS overlapping
701 the real breakpoint instruction bits region. */
702 make_show_memory_breakpoints_cleanup (1);
703 val = target_read_memory (addr, bundle, BUNDLE_LEN);
704 if (val != 0)
705 {
706 do_cleanups (cleanup);
707 return val;
708 }
709
710 /* Breakpoints already present in the code will get deteacted and not get
711 reinserted by bp_loc_is_permanent. Multiple breakpoints at the same
712 location cannot induce the internal error as they are optimized into
713 a single instance by update_global_location_list. */
714 instr_breakpoint = slotN_contents (bundle, slotnum);
715 if (instr_breakpoint == IA64_BREAKPOINT)
716 internal_error (__FILE__, __LINE__,
717 _("Address %s already contains a breakpoint."),
718 paddress (gdbarch, bp_tgt->placed_address));
719 replace_slotN_contents (bundle, IA64_BREAKPOINT, slotnum);
720
721 bp_tgt->placed_size = bp_tgt->shadow_len;
722
723 val = target_write_memory (addr + shadow_slotnum, bundle + shadow_slotnum,
724 bp_tgt->shadow_len);
725
726 do_cleanups (cleanup);
727 return val;
728}
729
730static int
731ia64_memory_remove_breakpoint (struct gdbarch *gdbarch,
732 struct bp_target_info *bp_tgt)
733{
734 CORE_ADDR addr = bp_tgt->placed_address;
735 gdb_byte bundle_mem[BUNDLE_LEN], bundle_saved[BUNDLE_LEN];
736 int slotnum = (addr & 0x0f) / SLOT_MULTIPLIER, shadow_slotnum;
737 long long instr_breakpoint, instr_saved;
738 int val;
739 int template;
740 struct cleanup *cleanup;
741
742 addr &= ~0x0f;
743
744 /* Disable the automatic memory restoration from breakpoints while
745 we read our instruction bundle. Otherwise, the general restoration
746 mechanism kicks in and we would possibly remove parts of the adjacent
747 placed breakpoints. It is due to our SHADOW_CONTENTS overlapping the real
748 breakpoint instruction bits region. */
749 cleanup = make_show_memory_breakpoints_cleanup (1);
750 val = target_read_memory (addr, bundle_mem, BUNDLE_LEN);
751 if (val != 0)
752 {
753 do_cleanups (cleanup);
754 return val;
755 }
756
757 /* SHADOW_SLOTNUM saves the original slot number as expected by the caller
758 for addressing the SHADOW_CONTENTS placement. */
759 shadow_slotnum = slotnum;
760
761 template = extract_bit_field (bundle_mem, 0, 5);
762 if (template_encoding_table[template][slotnum] == X)
763 {
764 /* X unit types can only be used in slot 2, and are actually
765 part of a 2-slot L-X instruction. We refuse to insert
766 breakpoints at this address, so there should be no reason
767 for us attempting to remove one there, except if the program's
768 code somehow got modified in memory. */
769 gdb_assert (slotnum == 2);
770 warning (_("Cannot remove breakpoint at address %s from non-existing "
771 "X-type slot, memory has changed underneath"),
772 paddress (gdbarch, bp_tgt->placed_address));
773 do_cleanups (cleanup);
774 return -1;
775 }
776 if (template_encoding_table[template][slotnum] == L)
777 {
778 /* L unit types can only be used in slot 1. But the breakpoint
779 was actually saved using slot 2, so update the slot number
780 accordingly. */
781 gdb_assert (slotnum == 1);
782 slotnum = 2;
783 }
784
785 gdb_assert (bp_tgt->placed_size == BUNDLE_LEN - shadow_slotnum);
786 gdb_assert (bp_tgt->placed_size == bp_tgt->shadow_len);
787
788 instr_breakpoint = slotN_contents (bundle_mem, slotnum);
789 if (instr_breakpoint != IA64_BREAKPOINT)
790 {
791 warning (_("Cannot remove breakpoint at address %s, "
792 "no break instruction at such address."),
793 paddress (gdbarch, bp_tgt->placed_address));
794 do_cleanups (cleanup);
795 return -1;
796 }
797
798 /* Extract the original saved instruction from SLOTNUM normalizing its
799 bit-shift for INSTR_SAVED. */
800 memcpy (bundle_saved, bundle_mem, BUNDLE_LEN);
801 memcpy (bundle_saved + shadow_slotnum, bp_tgt->shadow_contents,
802 bp_tgt->shadow_len);
803 instr_saved = slotN_contents (bundle_saved, slotnum);
804
805 /* In BUNDLE_MEM, be careful to modify only the bits belonging to SLOTNUM
806 and not any of the other ones that are stored in SHADOW_CONTENTS. */
807 replace_slotN_contents (bundle_mem, instr_saved, slotnum);
808 val = target_write_memory (addr, bundle_mem, BUNDLE_LEN);
809
810 do_cleanups (cleanup);
811 return val;
812}
813
814/* As gdbarch_breakpoint_from_pc ranges have byte granularity and ia64
815 instruction slots ranges are bit-granular (41 bits) we have to provide an
816 extended range as described for ia64_memory_insert_breakpoint. We also take
817 care of preserving the `break' instruction 21-bit (or 62-bit) parameter to
818 make a match for permanent breakpoints. */
819
820static const gdb_byte *
821ia64_breakpoint_from_pc (struct gdbarch *gdbarch,
822 CORE_ADDR *pcptr, int *lenptr)
823{
824 CORE_ADDR addr = *pcptr;
825 static gdb_byte bundle[BUNDLE_LEN];
826 int slotnum = (int) (*pcptr & 0x0f) / SLOT_MULTIPLIER, shadow_slotnum;
827 long long instr_fetched;
828 int val;
829 int template;
830 struct cleanup *cleanup;
831
832 if (slotnum > 2)
833 error (_("Can't insert breakpoint for slot numbers greater than 2."));
834
835 addr &= ~0x0f;
836
837 /* Enable the automatic memory restoration from breakpoints while
838 we read our instruction bundle to match bp_loc_is_permanent. */
839 cleanup = make_show_memory_breakpoints_cleanup (0);
840 val = target_read_memory (addr, bundle, BUNDLE_LEN);
841 do_cleanups (cleanup);
842
843 /* The memory might be unreachable. This can happen, for instance,
844 when the user inserts a breakpoint at an invalid address. */
845 if (val != 0)
846 return NULL;
847
848 /* SHADOW_SLOTNUM saves the original slot number as expected by the caller
849 for addressing the SHADOW_CONTENTS placement. */
850 shadow_slotnum = slotnum;
851
852 /* Cover always the last byte of the bundle for the L-X slot case. */
853 *lenptr = BUNDLE_LEN - shadow_slotnum;
854
855 /* Check for L type instruction in slot 1, if present then bump up the slot
856 number to the slot 2. */
857 template = extract_bit_field (bundle, 0, 5);
858 if (template_encoding_table[template][slotnum] == X)
859 {
860 gdb_assert (slotnum == 2);
861 error (_("Can't insert breakpoint for non-existing slot X"));
862 }
863 if (template_encoding_table[template][slotnum] == L)
864 {
865 gdb_assert (slotnum == 1);
866 slotnum = 2;
867 }
868
869 /* A break instruction has its all its opcode bits cleared except for
870 the parameter value. For L+X slot pair we are at the X slot (slot 2) so
871 we should not touch the L slot - the upper 41 bits of the parameter. */
872 instr_fetched = slotN_contents (bundle, slotnum);
873 instr_fetched &= 0x1003ffffc0LL;
874 replace_slotN_contents (bundle, instr_fetched, slotnum);
875
876 return bundle + shadow_slotnum;
877}
878
879static CORE_ADDR
880ia64_read_pc (struct regcache *regcache)
881{
882 ULONGEST psr_value, pc_value;
883 int slot_num;
884
885 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr_value);
886 regcache_cooked_read_unsigned (regcache, IA64_IP_REGNUM, &pc_value);
887 slot_num = (psr_value >> 41) & 3;
888
889 return pc_value | (slot_num * SLOT_MULTIPLIER);
890}
891
892void
893ia64_write_pc (struct regcache *regcache, CORE_ADDR new_pc)
894{
895 int slot_num = (int) (new_pc & 0xf) / SLOT_MULTIPLIER;
896 ULONGEST psr_value;
897
898 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr_value);
899 psr_value &= ~(3LL << 41);
900 psr_value |= (ULONGEST)(slot_num & 0x3) << 41;
901
902 new_pc &= ~0xfLL;
903
904 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr_value);
905 regcache_cooked_write_unsigned (regcache, IA64_IP_REGNUM, new_pc);
906}
907
908#define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f)
909
910/* Returns the address of the slot that's NSLOTS slots away from
911 the address ADDR. NSLOTS may be positive or negative. */
912static CORE_ADDR
913rse_address_add(CORE_ADDR addr, int nslots)
914{
915 CORE_ADDR new_addr;
916 int mandatory_nat_slots = nslots / 63;
917 int direction = nslots < 0 ? -1 : 1;
918
919 new_addr = addr + 8 * (nslots + mandatory_nat_slots);
920
921 if ((new_addr >> 9) != ((addr + 8 * 64 * mandatory_nat_slots) >> 9))
922 new_addr += 8 * direction;
923
924 if (IS_NaT_COLLECTION_ADDR(new_addr))
925 new_addr += 8 * direction;
926
927 return new_addr;
928}
929
930static void
931ia64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
932 int regnum, gdb_byte *buf)
933{
934 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
935
936 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
937 {
938#ifdef HAVE_LIBUNWIND_IA64_H
939 /* First try and use the libunwind special reg accessor,
940 otherwise fallback to standard logic. */
941 if (!libunwind_is_initialized ()
942 || libunwind_get_reg_special (gdbarch, regcache, regnum, buf) != 0)
943#endif
944 {
945 /* The fallback position is to assume that r32-r127 are
946 found sequentially in memory starting at $bof. This
947 isn't always true, but without libunwind, this is the
948 best we can do. */
949 ULONGEST cfm;
950 ULONGEST bsp;
951 CORE_ADDR reg;
952 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
953 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
954
955 /* The bsp points at the end of the register frame so we
956 subtract the size of frame from it to get start of
957 register frame. */
958 bsp = rse_address_add (bsp, -(cfm & 0x7f));
959
960 if ((cfm & 0x7f) > regnum - V32_REGNUM)
961 {
962 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
963 reg = read_memory_integer ((CORE_ADDR)reg_addr, 8, byte_order);
964 store_unsigned_integer (buf, register_size (gdbarch, regnum),
965 byte_order, reg);
966 }
967 else
968 store_unsigned_integer (buf, register_size (gdbarch, regnum),
969 byte_order, 0);
970 }
971 }
972 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
973 {
974 ULONGEST unatN_val;
975 ULONGEST unat;
976 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
977 unatN_val = (unat & (1LL << (regnum - IA64_NAT0_REGNUM))) != 0;
978 store_unsigned_integer (buf, register_size (gdbarch, regnum),
979 byte_order, unatN_val);
980 }
981 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
982 {
983 ULONGEST natN_val = 0;
984 ULONGEST bsp;
985 ULONGEST cfm;
986 CORE_ADDR gr_addr = 0;
987 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
988 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
989
990 /* The bsp points at the end of the register frame so we
991 subtract the size of frame from it to get start of register frame. */
992 bsp = rse_address_add (bsp, -(cfm & 0x7f));
993
994 if ((cfm & 0x7f) > regnum - V32_REGNUM)
995 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
996
997 if (gr_addr != 0)
998 {
999 /* Compute address of nat collection bits. */
1000 CORE_ADDR nat_addr = gr_addr | 0x1f8;
1001 CORE_ADDR nat_collection;
1002 int nat_bit;
1003 /* If our nat collection address is bigger than bsp, we have to get
1004 the nat collection from rnat. Otherwise, we fetch the nat
1005 collection from the computed address. */
1006 if (nat_addr >= bsp)
1007 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM,
1008 &nat_collection);
1009 else
1010 nat_collection = read_memory_integer (nat_addr, 8, byte_order);
1011 nat_bit = (gr_addr >> 3) & 0x3f;
1012 natN_val = (nat_collection >> nat_bit) & 1;
1013 }
1014
1015 store_unsigned_integer (buf, register_size (gdbarch, regnum),
1016 byte_order, natN_val);
1017 }
1018 else if (regnum == VBOF_REGNUM)
1019 {
1020 /* A virtual register frame start is provided for user convenience.
1021 It can be calculated as the bsp - sof (sizeof frame). */
1022 ULONGEST bsp, vbsp;
1023 ULONGEST cfm;
1024 CORE_ADDR reg;
1025 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
1026 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
1027
1028 /* The bsp points at the end of the register frame so we
1029 subtract the size of frame from it to get beginning of frame. */
1030 vbsp = rse_address_add (bsp, -(cfm & 0x7f));
1031 store_unsigned_integer (buf, register_size (gdbarch, regnum),
1032 byte_order, vbsp);
1033 }
1034 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
1035 {
1036 ULONGEST pr;
1037 ULONGEST cfm;
1038 ULONGEST prN_val;
1039 CORE_ADDR reg;
1040 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
1041 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
1042
1043 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
1044 {
1045 /* Fetch predicate register rename base from current frame
1046 marker for this frame. */
1047 int rrb_pr = (cfm >> 32) & 0x3f;
1048
1049 /* Adjust the register number to account for register rotation. */
1050 regnum = VP16_REGNUM
1051 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
1052 }
1053 prN_val = (pr & (1LL << (regnum - VP0_REGNUM))) != 0;
1054 store_unsigned_integer (buf, register_size (gdbarch, regnum),
1055 byte_order, prN_val);
1056 }
1057 else
1058 memset (buf, 0, register_size (gdbarch, regnum));
1059}
1060
1061static void
1062ia64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1063 int regnum, const gdb_byte *buf)
1064{
1065 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1066
1067 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
1068 {
1069 ULONGEST bsp;
1070 ULONGEST cfm;
1071 CORE_ADDR reg;
1072 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
1073 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
1074
1075 bsp = rse_address_add (bsp, -(cfm & 0x7f));
1076
1077 if ((cfm & 0x7f) > regnum - V32_REGNUM)
1078 {
1079 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
1080 write_memory (reg_addr, (void *) buf, 8);
1081 }
1082 }
1083 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
1084 {
1085 ULONGEST unatN_val, unat, unatN_mask;
1086 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
1087 unatN_val = extract_unsigned_integer (buf, register_size (gdbarch,
1088 regnum),
1089 byte_order);
1090 unatN_mask = (1LL << (regnum - IA64_NAT0_REGNUM));
1091 if (unatN_val == 0)
1092 unat &= ~unatN_mask;
1093 else if (unatN_val == 1)
1094 unat |= unatN_mask;
1095 regcache_cooked_write_unsigned (regcache, IA64_UNAT_REGNUM, unat);
1096 }
1097 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
1098 {
1099 ULONGEST natN_val;
1100 ULONGEST bsp;
1101 ULONGEST cfm;
1102 CORE_ADDR gr_addr = 0;
1103 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
1104 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
1105
1106 /* The bsp points at the end of the register frame so we
1107 subtract the size of frame from it to get start of register frame. */
1108 bsp = rse_address_add (bsp, -(cfm & 0x7f));
1109
1110 if ((cfm & 0x7f) > regnum - V32_REGNUM)
1111 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
1112
1113 natN_val = extract_unsigned_integer (buf, register_size (gdbarch,
1114 regnum),
1115 byte_order);
1116
1117 if (gr_addr != 0 && (natN_val == 0 || natN_val == 1))
1118 {
1119 /* Compute address of nat collection bits. */
1120 CORE_ADDR nat_addr = gr_addr | 0x1f8;
1121 CORE_ADDR nat_collection;
1122 int natN_bit = (gr_addr >> 3) & 0x3f;
1123 ULONGEST natN_mask = (1LL << natN_bit);
1124 /* If our nat collection address is bigger than bsp, we have to get
1125 the nat collection from rnat. Otherwise, we fetch the nat
1126 collection from the computed address. */
1127 if (nat_addr >= bsp)
1128 {
1129 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM,
1130 &nat_collection);
1131 if (natN_val)
1132 nat_collection |= natN_mask;
1133 else
1134 nat_collection &= ~natN_mask;
1135 regcache_cooked_write_unsigned (regcache, IA64_RNAT_REGNUM,
1136 nat_collection);
1137 }
1138 else
1139 {
1140 char nat_buf[8];
1141 nat_collection = read_memory_integer (nat_addr, 8, byte_order);
1142 if (natN_val)
1143 nat_collection |= natN_mask;
1144 else
1145 nat_collection &= ~natN_mask;
1146 store_unsigned_integer (nat_buf, register_size (gdbarch, regnum),
1147 byte_order, nat_collection);
1148 write_memory (nat_addr, nat_buf, 8);
1149 }
1150 }
1151 }
1152 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
1153 {
1154 ULONGEST pr;
1155 ULONGEST cfm;
1156 ULONGEST prN_val;
1157 ULONGEST prN_mask;
1158
1159 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
1160 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
1161
1162 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
1163 {
1164 /* Fetch predicate register rename base from current frame
1165 marker for this frame. */
1166 int rrb_pr = (cfm >> 32) & 0x3f;
1167
1168 /* Adjust the register number to account for register rotation. */
1169 regnum = VP16_REGNUM
1170 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
1171 }
1172 prN_val = extract_unsigned_integer (buf, register_size (gdbarch, regnum),
1173 byte_order);
1174 prN_mask = (1LL << (regnum - VP0_REGNUM));
1175 if (prN_val == 0)
1176 pr &= ~prN_mask;
1177 else if (prN_val == 1)
1178 pr |= prN_mask;
1179 regcache_cooked_write_unsigned (regcache, IA64_PR_REGNUM, pr);
1180 }
1181}
1182
1183/* The ia64 needs to convert between various ieee floating-point formats
1184 and the special ia64 floating point register format. */
1185
1186static int
1187ia64_convert_register_p (struct gdbarch *gdbarch, int regno, struct type *type)
1188{
1189 return (regno >= IA64_FR0_REGNUM && regno <= IA64_FR127_REGNUM
1190 && type != ia64_ext_type (gdbarch));
1191}
1192
1193static void
1194ia64_register_to_value (struct frame_info *frame, int regnum,
1195 struct type *valtype, gdb_byte *out)
1196{
1197 struct gdbarch *gdbarch = get_frame_arch (frame);
1198 char in[MAX_REGISTER_SIZE];
1199 frame_register_read (frame, regnum, in);
1200 convert_typed_floating (in, ia64_ext_type (gdbarch), out, valtype);
1201}
1202
1203static void
1204ia64_value_to_register (struct frame_info *frame, int regnum,
1205 struct type *valtype, const gdb_byte *in)
1206{
1207 struct gdbarch *gdbarch = get_frame_arch (frame);
1208 char out[MAX_REGISTER_SIZE];
1209 convert_typed_floating (in, valtype, out, ia64_ext_type (gdbarch));
1210 put_frame_register (frame, regnum, out);
1211}
1212
1213
1214/* Limit the number of skipped non-prologue instructions since examining
1215 of the prologue is expensive. */
1216static int max_skip_non_prologue_insns = 40;
1217
1218/* Given PC representing the starting address of a function, and
1219 LIM_PC which is the (sloppy) limit to which to scan when looking
1220 for a prologue, attempt to further refine this limit by using
1221 the line data in the symbol table. If successful, a better guess
1222 on where the prologue ends is returned, otherwise the previous
1223 value of lim_pc is returned. TRUST_LIMIT is a pointer to a flag
1224 which will be set to indicate whether the returned limit may be
1225 used with no further scanning in the event that the function is
1226 frameless. */
1227
1228/* FIXME: cagney/2004-02-14: This function and logic have largely been
1229 superseded by skip_prologue_using_sal. */
1230
1231static CORE_ADDR
1232refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc, int *trust_limit)
1233{
1234 struct symtab_and_line prologue_sal;
1235 CORE_ADDR start_pc = pc;
1236 CORE_ADDR end_pc;
1237
1238 /* The prologue can not possibly go past the function end itself,
1239 so we can already adjust LIM_PC accordingly. */
1240 if (find_pc_partial_function (pc, NULL, NULL, &end_pc) && end_pc < lim_pc)
1241 lim_pc = end_pc;
1242
1243 /* Start off not trusting the limit. */
1244 *trust_limit = 0;
1245
1246 prologue_sal = find_pc_line (pc, 0);
1247 if (prologue_sal.line != 0)
1248 {
1249 int i;
1250 CORE_ADDR addr = prologue_sal.end;
1251
1252 /* Handle the case in which compiler's optimizer/scheduler
1253 has moved instructions into the prologue. We scan ahead
1254 in the function looking for address ranges whose corresponding
1255 line number is less than or equal to the first one that we
1256 found for the function. (It can be less than when the
1257 scheduler puts a body instruction before the first prologue
1258 instruction.) */
1259 for (i = 2 * max_skip_non_prologue_insns;
1260 i > 0 && (lim_pc == 0 || addr < lim_pc);
1261 i--)
1262 {
1263 struct symtab_and_line sal;
1264
1265 sal = find_pc_line (addr, 0);
1266 if (sal.line == 0)
1267 break;
1268 if (sal.line <= prologue_sal.line
1269 && sal.symtab == prologue_sal.symtab)
1270 {
1271 prologue_sal = sal;
1272 }
1273 addr = sal.end;
1274 }
1275
1276 if (lim_pc == 0 || prologue_sal.end < lim_pc)
1277 {
1278 lim_pc = prologue_sal.end;
1279 if (start_pc == get_pc_function_start (lim_pc))
1280 *trust_limit = 1;
1281 }
1282 }
1283 return lim_pc;
1284}
1285
1286#define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \
1287 || (8 <= (_regnum_) && (_regnum_) <= 11) \
1288 || (14 <= (_regnum_) && (_regnum_) <= 31))
1289#define imm9(_instr_) \
1290 ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \
1291 | (((_instr_) & 0x00008000000LL) >> 20) \
1292 | (((_instr_) & 0x00000001fc0LL) >> 6))
1293
1294/* Allocate and initialize a frame cache. */
1295
1296static struct ia64_frame_cache *
1297ia64_alloc_frame_cache (void)
1298{
1299 struct ia64_frame_cache *cache;
1300 int i;
1301
1302 cache = FRAME_OBSTACK_ZALLOC (struct ia64_frame_cache);
1303
1304 /* Base address. */
1305 cache->base = 0;
1306 cache->pc = 0;
1307 cache->cfm = 0;
1308 cache->prev_cfm = 0;
1309 cache->sof = 0;
1310 cache->sol = 0;
1311 cache->sor = 0;
1312 cache->bsp = 0;
1313 cache->fp_reg = 0;
1314 cache->frameless = 1;
1315
1316 for (i = 0; i < NUM_IA64_RAW_REGS; i++)
1317 cache->saved_regs[i] = 0;
1318
1319 return cache;
1320}
1321
1322static CORE_ADDR
1323examine_prologue (CORE_ADDR pc, CORE_ADDR lim_pc,
1324 struct frame_info *this_frame,
1325 struct ia64_frame_cache *cache)
1326{
1327 CORE_ADDR next_pc;
1328 CORE_ADDR last_prologue_pc = pc;
1329 instruction_type it;
1330 long long instr;
1331 int cfm_reg = 0;
1332 int ret_reg = 0;
1333 int fp_reg = 0;
1334 int unat_save_reg = 0;
1335 int pr_save_reg = 0;
1336 int mem_stack_frame_size = 0;
1337 int spill_reg = 0;
1338 CORE_ADDR spill_addr = 0;
1339 char instores[8];
1340 char infpstores[8];
1341 char reg_contents[256];
1342 int trust_limit;
1343 int frameless = 1;
1344 int i;
1345 CORE_ADDR addr;
1346 char buf[8];
1347 CORE_ADDR bof, sor, sol, sof, cfm, rrb_gr;
1348
1349 memset (instores, 0, sizeof instores);
1350 memset (infpstores, 0, sizeof infpstores);
1351 memset (reg_contents, 0, sizeof reg_contents);
1352
1353 if (cache->after_prologue != 0
1354 && cache->after_prologue <= lim_pc)
1355 return cache->after_prologue;
1356
1357 lim_pc = refine_prologue_limit (pc, lim_pc, &trust_limit);
1358 next_pc = fetch_instruction (pc, &it, &instr);
1359
1360 /* We want to check if we have a recognizable function start before we
1361 look ahead for a prologue. */
1362 if (pc < lim_pc && next_pc
1363 && it == M && ((instr & 0x1ee0000003fLL) == 0x02c00000000LL))
1364 {
1365 /* alloc - start of a regular function. */
1366 int sor = (int) ((instr & 0x00078000000LL) >> 27);
1367 int sol = (int) ((instr & 0x00007f00000LL) >> 20);
1368 int sof = (int) ((instr & 0x000000fe000LL) >> 13);
1369 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1370
1371 /* Verify that the current cfm matches what we think is the
1372 function start. If we have somehow jumped within a function,
1373 we do not want to interpret the prologue and calculate the
1374 addresses of various registers such as the return address.
1375 We will instead treat the frame as frameless. */
1376 if (!this_frame ||
1377 (sof == (cache->cfm & 0x7f) &&
1378 sol == ((cache->cfm >> 7) & 0x7f)))
1379 frameless = 0;
1380
1381 cfm_reg = rN;
1382 last_prologue_pc = next_pc;
1383 pc = next_pc;
1384 }
1385 else
1386 {
1387 /* Look for a leaf routine. */
1388 if (pc < lim_pc && next_pc
1389 && (it == I || it == M)
1390 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1391 {
1392 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1393 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1394 | ((instr & 0x001f8000000LL) >> 20)
1395 | ((instr & 0x000000fe000LL) >> 13));
1396 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1397 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1398 int qp = (int) (instr & 0x0000000003fLL);
1399 if (qp == 0 && rN == 2 && imm == 0 && rM == 12 && fp_reg == 0)
1400 {
1401 /* mov r2, r12 - beginning of leaf routine. */
1402 fp_reg = rN;
1403 last_prologue_pc = next_pc;
1404 }
1405 }
1406
1407 /* If we don't recognize a regular function or leaf routine, we are
1408 done. */
1409 if (!fp_reg)
1410 {
1411 pc = lim_pc;
1412 if (trust_limit)
1413 last_prologue_pc = lim_pc;
1414 }
1415 }
1416
1417 /* Loop, looking for prologue instructions, keeping track of
1418 where preserved registers were spilled. */
1419 while (pc < lim_pc)
1420 {
1421 next_pc = fetch_instruction (pc, &it, &instr);
1422 if (next_pc == 0)
1423 break;
1424
1425 if (it == B && ((instr & 0x1e1f800003fLL) != 0x04000000000LL))
1426 {
1427 /* Exit loop upon hitting a non-nop branch instruction. */
1428 if (trust_limit)
1429 lim_pc = pc;
1430 break;
1431 }
1432 else if (((instr & 0x3fLL) != 0LL) &&
1433 (frameless || ret_reg != 0))
1434 {
1435 /* Exit loop upon hitting a predicated instruction if
1436 we already have the return register or if we are frameless. */
1437 if (trust_limit)
1438 lim_pc = pc;
1439 break;
1440 }
1441 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00188000000LL))
1442 {
1443 /* Move from BR */
1444 int b2 = (int) ((instr & 0x0000000e000LL) >> 13);
1445 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1446 int qp = (int) (instr & 0x0000000003f);
1447
1448 if (qp == 0 && b2 == 0 && rN >= 32 && ret_reg == 0)
1449 {
1450 ret_reg = rN;
1451 last_prologue_pc = next_pc;
1452 }
1453 }
1454 else if ((it == I || it == M)
1455 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1456 {
1457 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1458 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1459 | ((instr & 0x001f8000000LL) >> 20)
1460 | ((instr & 0x000000fe000LL) >> 13));
1461 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1462 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1463 int qp = (int) (instr & 0x0000000003fLL);
1464
1465 if (qp == 0 && rN >= 32 && imm == 0 && rM == 12 && fp_reg == 0)
1466 {
1467 /* mov rN, r12 */
1468 fp_reg = rN;
1469 last_prologue_pc = next_pc;
1470 }
1471 else if (qp == 0 && rN == 12 && rM == 12)
1472 {
1473 /* adds r12, -mem_stack_frame_size, r12 */
1474 mem_stack_frame_size -= imm;
1475 last_prologue_pc = next_pc;
1476 }
1477 else if (qp == 0 && rN == 2
1478 && ((rM == fp_reg && fp_reg != 0) || rM == 12))
1479 {
1480 char buf[MAX_REGISTER_SIZE];
1481 CORE_ADDR saved_sp = 0;
1482 /* adds r2, spilloffset, rFramePointer
1483 or
1484 adds r2, spilloffset, r12
1485
1486 Get ready for stf.spill or st8.spill instructions.
1487 The address to start spilling at is loaded into r2.
1488 FIXME: Why r2? That's what gcc currently uses; it
1489 could well be different for other compilers. */
1490
1491 /* Hmm... whether or not this will work will depend on
1492 where the pc is. If it's still early in the prologue
1493 this'll be wrong. FIXME */
1494 if (this_frame)
1495 {
1496 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1497 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1498 get_frame_register (this_frame, sp_regnum, buf);
1499 saved_sp = extract_unsigned_integer (buf, 8, byte_order);
1500 }
1501 spill_addr = saved_sp
1502 + (rM == 12 ? 0 : mem_stack_frame_size)
1503 + imm;
1504 spill_reg = rN;
1505 last_prologue_pc = next_pc;
1506 }
1507 else if (qp == 0 && rM >= 32 && rM < 40 && !instores[rM-32] &&
1508 rN < 256 && imm == 0)
1509 {
1510 /* mov rN, rM where rM is an input register. */
1511 reg_contents[rN] = rM;
1512 last_prologue_pc = next_pc;
1513 }
1514 else if (frameless && qp == 0 && rN == fp_reg && imm == 0 &&
1515 rM == 2)
1516 {
1517 /* mov r12, r2 */
1518 last_prologue_pc = next_pc;
1519 break;
1520 }
1521 }
1522 else if (it == M
1523 && ( ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
1524 || ((instr & 0x1ffc8000000LL) == 0x0cec0000000LL) ))
1525 {
1526 /* stf.spill [rN] = fM, imm9
1527 or
1528 stf.spill [rN] = fM */
1529
1530 int imm = imm9(instr);
1531 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1532 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1533 int qp = (int) (instr & 0x0000000003fLL);
1534 if (qp == 0 && rN == spill_reg && spill_addr != 0
1535 && ((2 <= fM && fM <= 5) || (16 <= fM && fM <= 31)))
1536 {
1537 cache->saved_regs[IA64_FR0_REGNUM + fM] = spill_addr;
1538
1539 if ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
1540 spill_addr += imm;
1541 else
1542 spill_addr = 0; /* last one; must be done. */
1543 last_prologue_pc = next_pc;
1544 }
1545 }
1546 else if ((it == M && ((instr & 0x1eff8000000LL) == 0x02110000000LL))
1547 || (it == I && ((instr & 0x1eff8000000LL) == 0x00050000000LL)) )
1548 {
1549 /* mov.m rN = arM
1550 or
1551 mov.i rN = arM */
1552
1553 int arM = (int) ((instr & 0x00007f00000LL) >> 20);
1554 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1555 int qp = (int) (instr & 0x0000000003fLL);
1556 if (qp == 0 && isScratch (rN) && arM == 36 /* ar.unat */)
1557 {
1558 /* We have something like "mov.m r3 = ar.unat". Remember the
1559 r3 (or whatever) and watch for a store of this register... */
1560 unat_save_reg = rN;
1561 last_prologue_pc = next_pc;
1562 }
1563 }
1564 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00198000000LL))
1565 {
1566 /* mov rN = pr */
1567 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1568 int qp = (int) (instr & 0x0000000003fLL);
1569 if (qp == 0 && isScratch (rN))
1570 {
1571 pr_save_reg = rN;
1572 last_prologue_pc = next_pc;
1573 }
1574 }
1575 else if (it == M
1576 && ( ((instr & 0x1ffc8000000LL) == 0x08cc0000000LL)
1577 || ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)))
1578 {
1579 /* st8 [rN] = rM
1580 or
1581 st8 [rN] = rM, imm9 */
1582 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1583 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1584 int qp = (int) (instr & 0x0000000003fLL);
1585 int indirect = rM < 256 ? reg_contents[rM] : 0;
1586 if (qp == 0 && rN == spill_reg && spill_addr != 0
1587 && (rM == unat_save_reg || rM == pr_save_reg))
1588 {
1589 /* We've found a spill of either the UNAT register or the PR
1590 register. (Well, not exactly; what we've actually found is
1591 a spill of the register that UNAT or PR was moved to).
1592 Record that fact and move on... */
1593 if (rM == unat_save_reg)
1594 {
1595 /* Track UNAT register. */
1596 cache->saved_regs[IA64_UNAT_REGNUM] = spill_addr;
1597 unat_save_reg = 0;
1598 }
1599 else
1600 {
1601 /* Track PR register. */
1602 cache->saved_regs[IA64_PR_REGNUM] = spill_addr;
1603 pr_save_reg = 0;
1604 }
1605 if ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)
1606 /* st8 [rN] = rM, imm9 */
1607 spill_addr += imm9(instr);
1608 else
1609 spill_addr = 0; /* Must be done spilling. */
1610 last_prologue_pc = next_pc;
1611 }
1612 else if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1613 {
1614 /* Allow up to one store of each input register. */
1615 instores[rM-32] = 1;
1616 last_prologue_pc = next_pc;
1617 }
1618 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1619 !instores[indirect-32])
1620 {
1621 /* Allow an indirect store of an input register. */
1622 instores[indirect-32] = 1;
1623 last_prologue_pc = next_pc;
1624 }
1625 }
1626 else if (it == M && ((instr & 0x1ff08000000LL) == 0x08c00000000LL))
1627 {
1628 /* One of
1629 st1 [rN] = rM
1630 st2 [rN] = rM
1631 st4 [rN] = rM
1632 st8 [rN] = rM
1633 Note that the st8 case is handled in the clause above.
1634
1635 Advance over stores of input registers. One store per input
1636 register is permitted. */
1637 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1638 int qp = (int) (instr & 0x0000000003fLL);
1639 int indirect = rM < 256 ? reg_contents[rM] : 0;
1640 if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1641 {
1642 instores[rM-32] = 1;
1643 last_prologue_pc = next_pc;
1644 }
1645 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1646 !instores[indirect-32])
1647 {
1648 /* Allow an indirect store of an input register. */
1649 instores[indirect-32] = 1;
1650 last_prologue_pc = next_pc;
1651 }
1652 }
1653 else if (it == M && ((instr & 0x1ff88000000LL) == 0x0cc80000000LL))
1654 {
1655 /* Either
1656 stfs [rN] = fM
1657 or
1658 stfd [rN] = fM
1659
1660 Advance over stores of floating point input registers. Again
1661 one store per register is permitted. */
1662 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1663 int qp = (int) (instr & 0x0000000003fLL);
1664 if (qp == 0 && 8 <= fM && fM < 16 && !infpstores[fM - 8])
1665 {
1666 infpstores[fM-8] = 1;
1667 last_prologue_pc = next_pc;
1668 }
1669 }
1670 else if (it == M
1671 && ( ((instr & 0x1ffc8000000LL) == 0x08ec0000000LL)
1672 || ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)))
1673 {
1674 /* st8.spill [rN] = rM
1675 or
1676 st8.spill [rN] = rM, imm9 */
1677 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1678 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1679 int qp = (int) (instr & 0x0000000003fLL);
1680 if (qp == 0 && rN == spill_reg && 4 <= rM && rM <= 7)
1681 {
1682 /* We've found a spill of one of the preserved general purpose
1683 regs. Record the spill address and advance the spill
1684 register if appropriate. */
1685 cache->saved_regs[IA64_GR0_REGNUM + rM] = spill_addr;
1686 if ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)
1687 /* st8.spill [rN] = rM, imm9 */
1688 spill_addr += imm9(instr);
1689 else
1690 spill_addr = 0; /* Done spilling. */
1691 last_prologue_pc = next_pc;
1692 }
1693 }
1694
1695 pc = next_pc;
1696 }
1697
1698 /* If not frameless and we aren't called by skip_prologue, then we need
1699 to calculate registers for the previous frame which will be needed
1700 later. */
1701
1702 if (!frameless && this_frame)
1703 {
1704 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1705 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1706
1707 /* Extract the size of the rotating portion of the stack
1708 frame and the register rename base from the current
1709 frame marker. */
1710 cfm = cache->cfm;
1711 sor = cache->sor;
1712 sof = cache->sof;
1713 sol = cache->sol;
1714 rrb_gr = (cfm >> 18) & 0x7f;
1715
1716 /* Find the bof (beginning of frame). */
1717 bof = rse_address_add (cache->bsp, -sof);
1718
1719 for (i = 0, addr = bof;
1720 i < sof;
1721 i++, addr += 8)
1722 {
1723 if (IS_NaT_COLLECTION_ADDR (addr))
1724 {
1725 addr += 8;
1726 }
1727 if (i+32 == cfm_reg)
1728 cache->saved_regs[IA64_CFM_REGNUM] = addr;
1729 if (i+32 == ret_reg)
1730 cache->saved_regs[IA64_VRAP_REGNUM] = addr;
1731 if (i+32 == fp_reg)
1732 cache->saved_regs[IA64_VFP_REGNUM] = addr;
1733 }
1734
1735 /* For the previous argument registers we require the previous bof.
1736 If we can't find the previous cfm, then we can do nothing. */
1737 cfm = 0;
1738 if (cache->saved_regs[IA64_CFM_REGNUM] != 0)
1739 {
1740 cfm = read_memory_integer (cache->saved_regs[IA64_CFM_REGNUM],
1741 8, byte_order);
1742 }
1743 else if (cfm_reg != 0)
1744 {
1745 get_frame_register (this_frame, cfm_reg, buf);
1746 cfm = extract_unsigned_integer (buf, 8, byte_order);
1747 }
1748 cache->prev_cfm = cfm;
1749
1750 if (cfm != 0)
1751 {
1752 sor = ((cfm >> 14) & 0xf) * 8;
1753 sof = (cfm & 0x7f);
1754 sol = (cfm >> 7) & 0x7f;
1755 rrb_gr = (cfm >> 18) & 0x7f;
1756
1757 /* The previous bof only requires subtraction of the sol (size of
1758 locals) due to the overlap between output and input of
1759 subsequent frames. */
1760 bof = rse_address_add (bof, -sol);
1761
1762 for (i = 0, addr = bof;
1763 i < sof;
1764 i++, addr += 8)
1765 {
1766 if (IS_NaT_COLLECTION_ADDR (addr))
1767 {
1768 addr += 8;
1769 }
1770 if (i < sor)
1771 cache->saved_regs[IA64_GR32_REGNUM
1772 + ((i + (sor - rrb_gr)) % sor)]
1773 = addr;
1774 else
1775 cache->saved_regs[IA64_GR32_REGNUM + i] = addr;
1776 }
1777
1778 }
1779 }
1780
1781 /* Try and trust the lim_pc value whenever possible. */
1782 if (trust_limit && lim_pc >= last_prologue_pc)
1783 last_prologue_pc = lim_pc;
1784
1785 cache->frameless = frameless;
1786 cache->after_prologue = last_prologue_pc;
1787 cache->mem_stack_frame_size = mem_stack_frame_size;
1788 cache->fp_reg = fp_reg;
1789
1790 return last_prologue_pc;
1791}
1792
1793CORE_ADDR
1794ia64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1795{
1796 struct ia64_frame_cache cache;
1797 cache.base = 0;
1798 cache.after_prologue = 0;
1799 cache.cfm = 0;
1800 cache.bsp = 0;
1801
1802 /* Call examine_prologue with - as third argument since we don't
1803 have a next frame pointer to send. */
1804 return examine_prologue (pc, pc+1024, 0, &cache);
1805}
1806
1807
1808/* Normal frames. */
1809
1810static struct ia64_frame_cache *
1811ia64_frame_cache (struct frame_info *this_frame, void **this_cache)
1812{
1813 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1814 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1815 struct ia64_frame_cache *cache;
1816 char buf[8];
1817 CORE_ADDR cfm, sof, sol, bsp, psr;
1818 int i;
1819
1820 if (*this_cache)
1821 return *this_cache;
1822
1823 cache = ia64_alloc_frame_cache ();
1824 *this_cache = cache;
1825
1826 get_frame_register (this_frame, sp_regnum, buf);
1827 cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order);
1828
1829 /* We always want the bsp to point to the end of frame.
1830 This way, we can always get the beginning of frame (bof)
1831 by subtracting frame size. */
1832 get_frame_register (this_frame, IA64_BSP_REGNUM, buf);
1833 cache->bsp = extract_unsigned_integer (buf, 8, byte_order);
1834
1835 get_frame_register (this_frame, IA64_PSR_REGNUM, buf);
1836 psr = extract_unsigned_integer (buf, 8, byte_order);
1837
1838 get_frame_register (this_frame, IA64_CFM_REGNUM, buf);
1839 cfm = extract_unsigned_integer (buf, 8, byte_order);
1840
1841 cache->sof = (cfm & 0x7f);
1842 cache->sol = (cfm >> 7) & 0x7f;
1843 cache->sor = ((cfm >> 14) & 0xf) * 8;
1844
1845 cache->cfm = cfm;
1846
1847 cache->pc = get_frame_func (this_frame);
1848
1849 if (cache->pc != 0)
1850 examine_prologue (cache->pc, get_frame_pc (this_frame), this_frame, cache);
1851
1852 cache->base = cache->saved_sp + cache->mem_stack_frame_size;
1853
1854 return cache;
1855}
1856
1857static void
1858ia64_frame_this_id (struct frame_info *this_frame, void **this_cache,
1859 struct frame_id *this_id)
1860{
1861 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1862 struct ia64_frame_cache *cache =
1863 ia64_frame_cache (this_frame, this_cache);
1864
1865 /* If outermost frame, mark with null frame id. */
1866 if (cache->base != 0)
1867 (*this_id) = frame_id_build_special (cache->base, cache->pc, cache->bsp);
1868 if (gdbarch_debug >= 1)
1869 fprintf_unfiltered (gdb_stdlog,
1870 "regular frame id: code %s, stack %s, "
1871 "special %s, this_frame %s\n",
1872 paddress (gdbarch, this_id->code_addr),
1873 paddress (gdbarch, this_id->stack_addr),
1874 paddress (gdbarch, cache->bsp),
1875 host_address_to_string (this_frame));
1876}
1877
1878static struct value *
1879ia64_frame_prev_register (struct frame_info *this_frame, void **this_cache,
1880 int regnum)
1881{
1882 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1883 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1884 struct ia64_frame_cache *cache = ia64_frame_cache (this_frame, this_cache);
1885 char buf[8];
1886
1887 gdb_assert (regnum >= 0);
1888
1889 if (!target_has_registers)
1890 error (_("No registers."));
1891
1892 if (regnum == gdbarch_sp_regnum (gdbarch))
1893 return frame_unwind_got_constant (this_frame, regnum, cache->base);
1894
1895 else if (regnum == IA64_BSP_REGNUM)
1896 {
1897 struct value *val;
1898 CORE_ADDR prev_cfm, bsp, prev_bsp;
1899
1900 /* We want to calculate the previous bsp as the end of the previous
1901 register stack frame. This corresponds to what the hardware bsp
1902 register will be if we pop the frame back which is why we might
1903 have been called. We know the beginning of the current frame is
1904 cache->bsp - cache->sof. This value in the previous frame points
1905 to the start of the output registers. We can calculate the end of
1906 that frame by adding the size of output:
1907 (sof (size of frame) - sol (size of locals)). */
1908 val = ia64_frame_prev_register (this_frame, this_cache, IA64_CFM_REGNUM);
1909 prev_cfm = extract_unsigned_integer (value_contents_all (val),
1910 8, byte_order);
1911 bsp = rse_address_add (cache->bsp, -(cache->sof));
1912 prev_bsp =
1913 rse_address_add (bsp, (prev_cfm & 0x7f) - ((prev_cfm >> 7) & 0x7f));
1914
1915 return frame_unwind_got_constant (this_frame, regnum, prev_bsp);
1916 }
1917
1918 else if (regnum == IA64_CFM_REGNUM)
1919 {
1920 CORE_ADDR addr = cache->saved_regs[IA64_CFM_REGNUM];
1921
1922 if (addr != 0)
1923 return frame_unwind_got_memory (this_frame, regnum, addr);
1924
1925 if (cache->prev_cfm)
1926 return frame_unwind_got_constant (this_frame, regnum, cache->prev_cfm);
1927
1928 if (cache->frameless)
1929 return frame_unwind_got_register (this_frame, IA64_PFS_REGNUM,
1930 IA64_PFS_REGNUM);
1931 return frame_unwind_got_register (this_frame, regnum, 0);
1932 }
1933
1934 else if (regnum == IA64_VFP_REGNUM)
1935 {
1936 /* If the function in question uses an automatic register (r32-r127)
1937 for the frame pointer, it'll be found by ia64_find_saved_register()
1938 above. If the function lacks one of these frame pointers, we can
1939 still provide a value since we know the size of the frame. */
1940 return frame_unwind_got_constant (this_frame, regnum, cache->base);
1941 }
1942
1943 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
1944 {
1945 struct value *pr_val;
1946 ULONGEST prN;
1947
1948 pr_val = ia64_frame_prev_register (this_frame, this_cache,
1949 IA64_PR_REGNUM);
1950 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
1951 {
1952 /* Fetch predicate register rename base from current frame
1953 marker for this frame. */
1954 int rrb_pr = (cache->cfm >> 32) & 0x3f;
1955
1956 /* Adjust the register number to account for register rotation. */
1957 regnum = VP16_REGNUM + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
1958 }
1959 prN = extract_bit_field (value_contents_all (pr_val),
1960 regnum - VP0_REGNUM, 1);
1961 return frame_unwind_got_constant (this_frame, regnum, prN);
1962 }
1963
1964 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
1965 {
1966 struct value *unat_val;
1967 ULONGEST unatN;
1968 unat_val = ia64_frame_prev_register (this_frame, this_cache,
1969 IA64_UNAT_REGNUM);
1970 unatN = extract_bit_field (value_contents_all (unat_val),
1971 regnum - IA64_NAT0_REGNUM, 1);
1972 return frame_unwind_got_constant (this_frame, regnum, unatN);
1973 }
1974
1975 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
1976 {
1977 int natval = 0;
1978 /* Find address of general register corresponding to nat bit we're
1979 interested in. */
1980 CORE_ADDR gr_addr;
1981
1982 gr_addr = cache->saved_regs[regnum - IA64_NAT0_REGNUM + IA64_GR0_REGNUM];
1983
1984 if (gr_addr != 0)
1985 {
1986 /* Compute address of nat collection bits. */
1987 CORE_ADDR nat_addr = gr_addr | 0x1f8;
1988 CORE_ADDR bsp;
1989 CORE_ADDR nat_collection;
1990 int nat_bit;
1991
1992 /* If our nat collection address is bigger than bsp, we have to get
1993 the nat collection from rnat. Otherwise, we fetch the nat
1994 collection from the computed address. */
1995 get_frame_register (this_frame, IA64_BSP_REGNUM, buf);
1996 bsp = extract_unsigned_integer (buf, 8, byte_order);
1997 if (nat_addr >= bsp)
1998 {
1999 get_frame_register (this_frame, IA64_RNAT_REGNUM, buf);
2000 nat_collection = extract_unsigned_integer (buf, 8, byte_order);
2001 }
2002 else
2003 nat_collection = read_memory_integer (nat_addr, 8, byte_order);
2004 nat_bit = (gr_addr >> 3) & 0x3f;
2005 natval = (nat_collection >> nat_bit) & 1;
2006 }
2007
2008 return frame_unwind_got_constant (this_frame, regnum, natval);
2009 }
2010
2011 else if (regnum == IA64_IP_REGNUM)
2012 {
2013 CORE_ADDR pc = 0;
2014 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
2015
2016 if (addr != 0)
2017 {
2018 read_memory (addr, buf, register_size (gdbarch, IA64_IP_REGNUM));
2019 pc = extract_unsigned_integer (buf, 8, byte_order);
2020 }
2021 else if (cache->frameless)
2022 {
2023 get_frame_register (this_frame, IA64_BR0_REGNUM, buf);
2024 pc = extract_unsigned_integer (buf, 8, byte_order);
2025 }
2026 pc &= ~0xf;
2027 return frame_unwind_got_constant (this_frame, regnum, pc);
2028 }
2029
2030 else if (regnum == IA64_PSR_REGNUM)
2031 {
2032 /* We don't know how to get the complete previous PSR, but we need it
2033 for the slot information when we unwind the pc (pc is formed of IP
2034 register plus slot information from PSR). To get the previous
2035 slot information, we mask it off the return address. */
2036 ULONGEST slot_num = 0;
2037 CORE_ADDR pc = 0;
2038 CORE_ADDR psr = 0;
2039 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
2040
2041 get_frame_register (this_frame, IA64_PSR_REGNUM, buf);
2042 psr = extract_unsigned_integer (buf, 8, byte_order);
2043
2044 if (addr != 0)
2045 {
2046 read_memory (addr, buf, register_size (gdbarch, IA64_IP_REGNUM));
2047 pc = extract_unsigned_integer (buf, 8, byte_order);
2048 }
2049 else if (cache->frameless)
2050 {
2051 get_frame_register (this_frame, IA64_BR0_REGNUM, buf);
2052 pc = extract_unsigned_integer (buf, 8, byte_order);
2053 }
2054 psr &= ~(3LL << 41);
2055 slot_num = pc & 0x3LL;
2056 psr |= (CORE_ADDR)slot_num << 41;
2057 return frame_unwind_got_constant (this_frame, regnum, psr);
2058 }
2059
2060 else if (regnum == IA64_BR0_REGNUM)
2061 {
2062 CORE_ADDR addr = cache->saved_regs[IA64_BR0_REGNUM];
2063
2064 if (addr != 0)
2065 return frame_unwind_got_memory (this_frame, regnum, addr);
2066
2067 return frame_unwind_got_constant (this_frame, regnum, 0);
2068 }
2069
2070 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM)
2071 || (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
2072 {
2073 CORE_ADDR addr = 0;
2074
2075 if (regnum >= V32_REGNUM)
2076 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
2077 addr = cache->saved_regs[regnum];
2078 if (addr != 0)
2079 return frame_unwind_got_memory (this_frame, regnum, addr);
2080
2081 if (cache->frameless)
2082 {
2083 struct value *reg_val;
2084 CORE_ADDR prev_cfm, prev_bsp, prev_bof;
2085
2086 /* FIXME: brobecker/2008-05-01: Doesn't this seem redundant
2087 with the same code above? */
2088 if (regnum >= V32_REGNUM)
2089 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
2090 reg_val = ia64_frame_prev_register (this_frame, this_cache,
2091 IA64_CFM_REGNUM);
2092 prev_cfm = extract_unsigned_integer (value_contents_all (reg_val),
2093 8, byte_order);
2094 reg_val = ia64_frame_prev_register (this_frame, this_cache,
2095 IA64_BSP_REGNUM);
2096 prev_bsp = extract_unsigned_integer (value_contents_all (reg_val),
2097 8, byte_order);
2098 prev_bof = rse_address_add (prev_bsp, -(prev_cfm & 0x7f));
2099
2100 addr = rse_address_add (prev_bof, (regnum - IA64_GR32_REGNUM));
2101 return frame_unwind_got_memory (this_frame, regnum, addr);
2102 }
2103
2104 return frame_unwind_got_constant (this_frame, regnum, 0);
2105 }
2106
2107 else /* All other registers. */
2108 {
2109 CORE_ADDR addr = 0;
2110
2111 if (IA64_FR32_REGNUM <= regnum && regnum <= IA64_FR127_REGNUM)
2112 {
2113 /* Fetch floating point register rename base from current
2114 frame marker for this frame. */
2115 int rrb_fr = (cache->cfm >> 25) & 0x7f;
2116
2117 /* Adjust the floating point register number to account for
2118 register rotation. */
2119 regnum = IA64_FR32_REGNUM
2120 + ((regnum - IA64_FR32_REGNUM) + rrb_fr) % 96;
2121 }
2122
2123 /* If we have stored a memory address, access the register. */
2124 addr = cache->saved_regs[regnum];
2125 if (addr != 0)
2126 return frame_unwind_got_memory (this_frame, regnum, addr);
2127 /* Otherwise, punt and get the current value of the register. */
2128 else
2129 return frame_unwind_got_register (this_frame, regnum, regnum);
2130 }
2131}
2132
2133static const struct frame_unwind ia64_frame_unwind =
2134{
2135 NORMAL_FRAME,
2136 &ia64_frame_this_id,
2137 &ia64_frame_prev_register,
2138 NULL,
2139 default_frame_sniffer
2140};
2141
2142/* Signal trampolines. */
2143
2144static void
2145ia64_sigtramp_frame_init_saved_regs (struct frame_info *this_frame,
2146 struct ia64_frame_cache *cache)
2147{
2148 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2149 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2150
2151 if (tdep->sigcontext_register_address)
2152 {
2153 int regno;
2154
2155 cache->saved_regs[IA64_VRAP_REGNUM]
2156 = tdep->sigcontext_register_address (gdbarch, cache->base,
2157 IA64_IP_REGNUM);
2158 cache->saved_regs[IA64_CFM_REGNUM]
2159 = tdep->sigcontext_register_address (gdbarch, cache->base,
2160 IA64_CFM_REGNUM);
2161 cache->saved_regs[IA64_PSR_REGNUM]
2162 = tdep->sigcontext_register_address (gdbarch, cache->base,
2163 IA64_PSR_REGNUM);
2164 cache->saved_regs[IA64_BSP_REGNUM]
2165 = tdep->sigcontext_register_address (gdbarch, cache->base,
2166 IA64_BSP_REGNUM);
2167 cache->saved_regs[IA64_RNAT_REGNUM]
2168 = tdep->sigcontext_register_address (gdbarch, cache->base,
2169 IA64_RNAT_REGNUM);
2170 cache->saved_regs[IA64_CCV_REGNUM]
2171 = tdep->sigcontext_register_address (gdbarch, cache->base,
2172 IA64_CCV_REGNUM);
2173 cache->saved_regs[IA64_UNAT_REGNUM]
2174 = tdep->sigcontext_register_address (gdbarch, cache->base,
2175 IA64_UNAT_REGNUM);
2176 cache->saved_regs[IA64_FPSR_REGNUM]
2177 = tdep->sigcontext_register_address (gdbarch, cache->base,
2178 IA64_FPSR_REGNUM);
2179 cache->saved_regs[IA64_PFS_REGNUM]
2180 = tdep->sigcontext_register_address (gdbarch, cache->base,
2181 IA64_PFS_REGNUM);
2182 cache->saved_regs[IA64_LC_REGNUM]
2183 = tdep->sigcontext_register_address (gdbarch, cache->base,
2184 IA64_LC_REGNUM);
2185
2186 for (regno = IA64_GR1_REGNUM; regno <= IA64_GR31_REGNUM; regno++)
2187 cache->saved_regs[regno] =
2188 tdep->sigcontext_register_address (gdbarch, cache->base, regno);
2189 for (regno = IA64_BR0_REGNUM; regno <= IA64_BR7_REGNUM; regno++)
2190 cache->saved_regs[regno] =
2191 tdep->sigcontext_register_address (gdbarch, cache->base, regno);
2192 for (regno = IA64_FR2_REGNUM; regno <= IA64_FR31_REGNUM; regno++)
2193 cache->saved_regs[regno] =
2194 tdep->sigcontext_register_address (gdbarch, cache->base, regno);
2195 }
2196}
2197
2198static struct ia64_frame_cache *
2199ia64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2200{
2201 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2202 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2203 struct ia64_frame_cache *cache;
2204 CORE_ADDR addr;
2205 char buf[8];
2206 int i;
2207
2208 if (*this_cache)
2209 return *this_cache;
2210
2211 cache = ia64_alloc_frame_cache ();
2212
2213 get_frame_register (this_frame, sp_regnum, buf);
2214 /* Note that frame size is hard-coded below. We cannot calculate it
2215 via prologue examination. */
2216 cache->base = extract_unsigned_integer (buf, 8, byte_order) + 16;
2217
2218 get_frame_register (this_frame, IA64_BSP_REGNUM, buf);
2219 cache->bsp = extract_unsigned_integer (buf, 8, byte_order);
2220
2221 get_frame_register (this_frame, IA64_CFM_REGNUM, buf);
2222 cache->cfm = extract_unsigned_integer (buf, 8, byte_order);
2223 cache->sof = cache->cfm & 0x7f;
2224
2225 ia64_sigtramp_frame_init_saved_regs (this_frame, cache);
2226
2227 *this_cache = cache;
2228 return cache;
2229}
2230
2231static void
2232ia64_sigtramp_frame_this_id (struct frame_info *this_frame,
2233 void **this_cache, struct frame_id *this_id)
2234{
2235 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2236 struct ia64_frame_cache *cache =
2237 ia64_sigtramp_frame_cache (this_frame, this_cache);
2238
2239 (*this_id) = frame_id_build_special (cache->base,
2240 get_frame_pc (this_frame),
2241 cache->bsp);
2242 if (gdbarch_debug >= 1)
2243 fprintf_unfiltered (gdb_stdlog,
2244 "sigtramp frame id: code %s, stack %s, "
2245 "special %s, this_frame %s\n",
2246 paddress (gdbarch, this_id->code_addr),
2247 paddress (gdbarch, this_id->stack_addr),
2248 paddress (gdbarch, cache->bsp),
2249 host_address_to_string (this_frame));
2250}
2251
2252static struct value *
2253ia64_sigtramp_frame_prev_register (struct frame_info *this_frame,
2254 void **this_cache, int regnum)
2255{
2256 char buf[MAX_REGISTER_SIZE];
2257
2258 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2259 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2260 struct ia64_frame_cache *cache =
2261 ia64_sigtramp_frame_cache (this_frame, this_cache);
2262
2263 gdb_assert (regnum >= 0);
2264
2265 if (!target_has_registers)
2266 error (_("No registers."));
2267
2268 if (regnum == IA64_IP_REGNUM)
2269 {
2270 CORE_ADDR pc = 0;
2271 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
2272
2273 if (addr != 0)
2274 {
2275 read_memory (addr, buf, register_size (gdbarch, IA64_IP_REGNUM));
2276 pc = extract_unsigned_integer (buf, 8, byte_order);
2277 }
2278 pc &= ~0xf;
2279 return frame_unwind_got_constant (this_frame, regnum, pc);
2280 }
2281
2282 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM)
2283 || (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
2284 {
2285 CORE_ADDR addr = 0;
2286
2287 if (regnum >= V32_REGNUM)
2288 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
2289 addr = cache->saved_regs[regnum];
2290 if (addr != 0)
2291 return frame_unwind_got_memory (this_frame, regnum, addr);
2292
2293 return frame_unwind_got_constant (this_frame, regnum, 0);
2294 }
2295
2296 else /* All other registers not listed above. */
2297 {
2298 CORE_ADDR addr = cache->saved_regs[regnum];
2299
2300 if (addr != 0)
2301 return frame_unwind_got_memory (this_frame, regnum, addr);
2302
2303 return frame_unwind_got_constant (this_frame, regnum, 0);
2304 }
2305}
2306
2307static int
2308ia64_sigtramp_frame_sniffer (const struct frame_unwind *self,
2309 struct frame_info *this_frame,
2310 void **this_cache)
2311{
2312 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2313 if (tdep->pc_in_sigtramp)
2314 {
2315 CORE_ADDR pc = get_frame_pc (this_frame);
2316
2317 if (tdep->pc_in_sigtramp (pc))
2318 return 1;
2319 }
2320
2321 return 0;
2322}
2323
2324static const struct frame_unwind ia64_sigtramp_frame_unwind =
2325{
2326 SIGTRAMP_FRAME,
2327 ia64_sigtramp_frame_this_id,
2328 ia64_sigtramp_frame_prev_register,
2329 NULL,
2330 ia64_sigtramp_frame_sniffer
2331};
2332
2333\f
2334
2335static CORE_ADDR
2336ia64_frame_base_address (struct frame_info *this_frame, void **this_cache)
2337{
2338 struct ia64_frame_cache *cache = ia64_frame_cache (this_frame, this_cache);
2339
2340 return cache->base;
2341}
2342
2343static const struct frame_base ia64_frame_base =
2344{
2345 &ia64_frame_unwind,
2346 ia64_frame_base_address,
2347 ia64_frame_base_address,
2348 ia64_frame_base_address
2349};
2350
2351#ifdef HAVE_LIBUNWIND_IA64_H
2352
2353struct ia64_unwind_table_entry
2354 {
2355 unw_word_t start_offset;
2356 unw_word_t end_offset;
2357 unw_word_t info_offset;
2358 };
2359
2360static __inline__ uint64_t
2361ia64_rse_slot_num (uint64_t addr)
2362{
2363 return (addr >> 3) & 0x3f;
2364}
2365
2366/* Skip over a designated number of registers in the backing
2367 store, remembering every 64th position is for NAT. */
2368static __inline__ uint64_t
2369ia64_rse_skip_regs (uint64_t addr, long num_regs)
2370{
2371 long delta = ia64_rse_slot_num(addr) + num_regs;
2372
2373 if (num_regs < 0)
2374 delta -= 0x3e;
2375 return addr + ((num_regs + delta/0x3f) << 3);
2376}
2377
2378/* Gdb libunwind-frame callback function to convert from an ia64 gdb register
2379 number to a libunwind register number. */
2380static int
2381ia64_gdb2uw_regnum (int regnum)
2382{
2383 if (regnum == sp_regnum)
2384 return UNW_IA64_SP;
2385 else if (regnum == IA64_BSP_REGNUM)
2386 return UNW_IA64_BSP;
2387 else if ((unsigned) (regnum - IA64_GR0_REGNUM) < 128)
2388 return UNW_IA64_GR + (regnum - IA64_GR0_REGNUM);
2389 else if ((unsigned) (regnum - V32_REGNUM) < 95)
2390 return UNW_IA64_GR + 32 + (regnum - V32_REGNUM);
2391 else if ((unsigned) (regnum - IA64_FR0_REGNUM) < 128)
2392 return UNW_IA64_FR + (regnum - IA64_FR0_REGNUM);
2393 else if ((unsigned) (regnum - IA64_PR0_REGNUM) < 64)
2394 return -1;
2395 else if ((unsigned) (regnum - IA64_BR0_REGNUM) < 8)
2396 return UNW_IA64_BR + (regnum - IA64_BR0_REGNUM);
2397 else if (regnum == IA64_PR_REGNUM)
2398 return UNW_IA64_PR;
2399 else if (regnum == IA64_IP_REGNUM)
2400 return UNW_REG_IP;
2401 else if (regnum == IA64_CFM_REGNUM)
2402 return UNW_IA64_CFM;
2403 else if ((unsigned) (regnum - IA64_AR0_REGNUM) < 128)
2404 return UNW_IA64_AR + (regnum - IA64_AR0_REGNUM);
2405 else if ((unsigned) (regnum - IA64_NAT0_REGNUM) < 128)
2406 return UNW_IA64_NAT + (regnum - IA64_NAT0_REGNUM);
2407 else
2408 return -1;
2409}
2410
2411/* Gdb libunwind-frame callback function to convert from a libunwind register
2412 number to a ia64 gdb register number. */
2413static int
2414ia64_uw2gdb_regnum (int uw_regnum)
2415{
2416 if (uw_regnum == UNW_IA64_SP)
2417 return sp_regnum;
2418 else if (uw_regnum == UNW_IA64_BSP)
2419 return IA64_BSP_REGNUM;
2420 else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 32)
2421 return IA64_GR0_REGNUM + (uw_regnum - UNW_IA64_GR);
2422 else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 128)
2423 return V32_REGNUM + (uw_regnum - (IA64_GR0_REGNUM + 32));
2424 else if ((unsigned) (uw_regnum - UNW_IA64_FR) < 128)
2425 return IA64_FR0_REGNUM + (uw_regnum - UNW_IA64_FR);
2426 else if ((unsigned) (uw_regnum - UNW_IA64_BR) < 8)
2427 return IA64_BR0_REGNUM + (uw_regnum - UNW_IA64_BR);
2428 else if (uw_regnum == UNW_IA64_PR)
2429 return IA64_PR_REGNUM;
2430 else if (uw_regnum == UNW_REG_IP)
2431 return IA64_IP_REGNUM;
2432 else if (uw_regnum == UNW_IA64_CFM)
2433 return IA64_CFM_REGNUM;
2434 else if ((unsigned) (uw_regnum - UNW_IA64_AR) < 128)
2435 return IA64_AR0_REGNUM + (uw_regnum - UNW_IA64_AR);
2436 else if ((unsigned) (uw_regnum - UNW_IA64_NAT) < 128)
2437 return IA64_NAT0_REGNUM + (uw_regnum - UNW_IA64_NAT);
2438 else
2439 return -1;
2440}
2441
2442/* Gdb libunwind-frame callback function to reveal if register is a float
2443 register or not. */
2444static int
2445ia64_is_fpreg (int uw_regnum)
2446{
2447 return unw_is_fpreg (uw_regnum);
2448}
2449
2450/* Libunwind callback accessor function for general registers. */
2451static int
2452ia64_access_reg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_word_t *val,
2453 int write, void *arg)
2454{
2455 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2456 unw_word_t bsp, sof, sol, cfm, psr, ip;
2457 struct frame_info *this_frame = arg;
2458 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2459 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2460 long new_sof, old_sof;
2461 char buf[MAX_REGISTER_SIZE];
2462
2463 /* We never call any libunwind routines that need to write registers. */
2464 gdb_assert (!write);
2465
2466 switch (uw_regnum)
2467 {
2468 case UNW_REG_IP:
2469 /* Libunwind expects to see the pc value which means the slot number
2470 from the psr must be merged with the ip word address. */
2471 get_frame_register (this_frame, IA64_IP_REGNUM, buf);
2472 ip = extract_unsigned_integer (buf, 8, byte_order);
2473 get_frame_register (this_frame, IA64_PSR_REGNUM, buf);
2474 psr = extract_unsigned_integer (buf, 8, byte_order);
2475 *val = ip | ((psr >> 41) & 0x3);
2476 break;
2477
2478 case UNW_IA64_AR_BSP:
2479 /* Libunwind expects to see the beginning of the current
2480 register frame so we must account for the fact that
2481 ptrace() will return a value for bsp that points *after*
2482 the current register frame. */
2483 get_frame_register (this_frame, IA64_BSP_REGNUM, buf);
2484 bsp = extract_unsigned_integer (buf, 8, byte_order);
2485 get_frame_register (this_frame, IA64_CFM_REGNUM, buf);
2486 cfm = extract_unsigned_integer (buf, 8, byte_order);
2487 sof = (cfm & 0x7f);
2488 *val = ia64_rse_skip_regs (bsp, -sof);
2489 break;
2490
2491 case UNW_IA64_AR_BSPSTORE:
2492 /* Libunwind wants bspstore to be after the current register frame.
2493 This is what ptrace() and gdb treats as the regular bsp value. */
2494 get_frame_register (this_frame, IA64_BSP_REGNUM, buf);
2495 *val = extract_unsigned_integer (buf, 8, byte_order);
2496 break;
2497
2498 default:
2499 /* For all other registers, just unwind the value directly. */
2500 get_frame_register (this_frame, regnum, buf);
2501 *val = extract_unsigned_integer (buf, 8, byte_order);
2502 break;
2503 }
2504
2505 if (gdbarch_debug >= 1)
2506 fprintf_unfiltered (gdb_stdlog,
2507 " access_reg: from cache: %4s=%s\n",
2508 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2509 ? ia64_register_names[regnum] : "r??"),
2510 paddress (gdbarch, *val));
2511 return 0;
2512}
2513
2514/* Libunwind callback accessor function for floating-point registers. */
2515static int
2516ia64_access_fpreg (unw_addr_space_t as, unw_regnum_t uw_regnum,
2517 unw_fpreg_t *val, int write, void *arg)
2518{
2519 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2520 struct frame_info *this_frame = arg;
2521
2522 /* We never call any libunwind routines that need to write registers. */
2523 gdb_assert (!write);
2524
2525 get_frame_register (this_frame, regnum, (char *) val);
2526
2527 return 0;
2528}
2529
2530/* Libunwind callback accessor function for top-level rse registers. */
2531static int
2532ia64_access_rse_reg (unw_addr_space_t as, unw_regnum_t uw_regnum,
2533 unw_word_t *val, int write, void *arg)
2534{
2535 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2536 unw_word_t bsp, sof, sol, cfm, psr, ip;
2537 struct regcache *regcache = arg;
2538 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2539 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2540 long new_sof, old_sof;
2541 char buf[MAX_REGISTER_SIZE];
2542
2543 /* We never call any libunwind routines that need to write registers. */
2544 gdb_assert (!write);
2545
2546 switch (uw_regnum)
2547 {
2548 case UNW_REG_IP:
2549 /* Libunwind expects to see the pc value which means the slot number
2550 from the psr must be merged with the ip word address. */
2551 regcache_cooked_read (regcache, IA64_IP_REGNUM, buf);
2552 ip = extract_unsigned_integer (buf, 8, byte_order);
2553 regcache_cooked_read (regcache, IA64_PSR_REGNUM, buf);
2554 psr = extract_unsigned_integer (buf, 8, byte_order);
2555 *val = ip | ((psr >> 41) & 0x3);
2556 break;
2557
2558 case UNW_IA64_AR_BSP:
2559 /* Libunwind expects to see the beginning of the current
2560 register frame so we must account for the fact that
2561 ptrace() will return a value for bsp that points *after*
2562 the current register frame. */
2563 regcache_cooked_read (regcache, IA64_BSP_REGNUM, buf);
2564 bsp = extract_unsigned_integer (buf, 8, byte_order);
2565 regcache_cooked_read (regcache, IA64_CFM_REGNUM, buf);
2566 cfm = extract_unsigned_integer (buf, 8, byte_order);
2567 sof = (cfm & 0x7f);
2568 *val = ia64_rse_skip_regs (bsp, -sof);
2569 break;
2570
2571 case UNW_IA64_AR_BSPSTORE:
2572 /* Libunwind wants bspstore to be after the current register frame.
2573 This is what ptrace() and gdb treats as the regular bsp value. */
2574 regcache_cooked_read (regcache, IA64_BSP_REGNUM, buf);
2575 *val = extract_unsigned_integer (buf, 8, byte_order);
2576 break;
2577
2578 default:
2579 /* For all other registers, just unwind the value directly. */
2580 regcache_cooked_read (regcache, regnum, buf);
2581 *val = extract_unsigned_integer (buf, 8, byte_order);
2582 break;
2583 }
2584
2585 if (gdbarch_debug >= 1)
2586 fprintf_unfiltered (gdb_stdlog,
2587 " access_rse_reg: from cache: %4s=%s\n",
2588 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2589 ? ia64_register_names[regnum] : "r??"),
2590 paddress (gdbarch, *val));
2591
2592 return 0;
2593}
2594
2595/* Libunwind callback accessor function for top-level fp registers. */
2596static int
2597ia64_access_rse_fpreg (unw_addr_space_t as, unw_regnum_t uw_regnum,
2598 unw_fpreg_t *val, int write, void *arg)
2599{
2600 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2601 struct regcache *regcache = arg;
2602
2603 /* We never call any libunwind routines that need to write registers. */
2604 gdb_assert (!write);
2605
2606 regcache_cooked_read (regcache, regnum, (char *) val);
2607
2608 return 0;
2609}
2610
2611/* Libunwind callback accessor function for accessing memory. */
2612static int
2613ia64_access_mem (unw_addr_space_t as,
2614 unw_word_t addr, unw_word_t *val,
2615 int write, void *arg)
2616{
2617 if (addr - KERNEL_START < ktab_size)
2618 {
2619 unw_word_t *laddr = (unw_word_t*) ((char *) ktab
2620 + (addr - KERNEL_START));
2621
2622 if (write)
2623 *laddr = *val;
2624 else
2625 *val = *laddr;
2626 return 0;
2627 }
2628
2629 /* XXX do we need to normalize byte-order here? */
2630 if (write)
2631 return target_write_memory (addr, (char *) val, sizeof (unw_word_t));
2632 else
2633 return target_read_memory (addr, (char *) val, sizeof (unw_word_t));
2634}
2635
2636/* Call low-level function to access the kernel unwind table. */
2637static LONGEST
2638getunwind_table (gdb_byte **buf_p)
2639{
2640 LONGEST x;
2641
2642 /* FIXME drow/2005-09-10: This code used to call
2643 ia64_linux_xfer_unwind_table directly to fetch the unwind table
2644 for the currently running ia64-linux kernel. That data should
2645 come from the core file and be accessed via the auxv vector; if
2646 we want to preserve fall back to the running kernel's table, then
2647 we should find a way to override the corefile layer's
2648 xfer_partial method. */
2649
2650 x = target_read_alloc (&current_target, TARGET_OBJECT_UNWIND_TABLE,
2651 NULL, buf_p);
2652
2653 return x;
2654}
2655
2656/* Get the kernel unwind table. */
2657static int
2658get_kernel_table (unw_word_t ip, unw_dyn_info_t *di)
2659{
2660 static struct ia64_table_entry *etab;
2661
2662 if (!ktab)
2663 {
2664 gdb_byte *ktab_buf;
2665 LONGEST size;
2666
2667 size = getunwind_table (&ktab_buf);
2668 if (size <= 0)
2669 return -UNW_ENOINFO;
2670
2671 ktab = (struct ia64_table_entry *) ktab_buf;
2672 ktab_size = size;
2673
2674 for (etab = ktab; etab->start_offset; ++etab)
2675 etab->info_offset += KERNEL_START;
2676 }
2677
2678 if (ip < ktab[0].start_offset || ip >= etab[-1].end_offset)
2679 return -UNW_ENOINFO;
2680
2681 di->format = UNW_INFO_FORMAT_TABLE;
2682 di->gp = 0;
2683 di->start_ip = ktab[0].start_offset;
2684 di->end_ip = etab[-1].end_offset;
2685 di->u.ti.name_ptr = (unw_word_t) "<kernel>";
2686 di->u.ti.segbase = 0;
2687 di->u.ti.table_len = ((char *) etab - (char *) ktab) / sizeof (unw_word_t);
2688 di->u.ti.table_data = (unw_word_t *) ktab;
2689
2690 if (gdbarch_debug >= 1)
2691 fprintf_unfiltered (gdb_stdlog, "get_kernel_table: found table `%s': "
2692 "segbase=%s, length=%s, gp=%s\n",
2693 (char *) di->u.ti.name_ptr,
2694 hex_string (di->u.ti.segbase),
2695 pulongest (di->u.ti.table_len),
2696 hex_string (di->gp));
2697 return 0;
2698}
2699
2700/* Find the unwind table entry for a specified address. */
2701static int
2702ia64_find_unwind_table (struct objfile *objfile, unw_word_t ip,
2703 unw_dyn_info_t *dip, void **buf)
2704{
2705 Elf_Internal_Phdr *phdr, *p_text = NULL, *p_unwind = NULL;
2706 Elf_Internal_Ehdr *ehdr;
2707 unw_word_t segbase = 0;
2708 CORE_ADDR load_base;
2709 bfd *bfd;
2710 int i;
2711
2712 bfd = objfile->obfd;
2713
2714 ehdr = elf_tdata (bfd)->elf_header;
2715 phdr = elf_tdata (bfd)->phdr;
2716
2717 load_base = ANOFFSET (objfile->section_offsets, SECT_OFF_TEXT (objfile));
2718
2719 for (i = 0; i < ehdr->e_phnum; ++i)
2720 {
2721 switch (phdr[i].p_type)
2722 {
2723 case PT_LOAD:
2724 if ((unw_word_t) (ip - load_base - phdr[i].p_vaddr)
2725 < phdr[i].p_memsz)
2726 p_text = phdr + i;
2727 break;
2728
2729 case PT_IA_64_UNWIND:
2730 p_unwind = phdr + i;
2731 break;
2732
2733 default:
2734 break;
2735 }
2736 }
2737
2738 if (!p_text || !p_unwind)
2739 return -UNW_ENOINFO;
2740
2741 /* Verify that the segment that contains the IP also contains
2742 the static unwind table. If not, we may be in the Linux kernel's
2743 DSO gate page in which case the unwind table is another segment.
2744 Otherwise, we are dealing with runtime-generated code, for which we
2745 have no info here. */
2746 segbase = p_text->p_vaddr + load_base;
2747
2748 if ((p_unwind->p_vaddr - p_text->p_vaddr) >= p_text->p_memsz)
2749 {
2750 int ok = 0;
2751 for (i = 0; i < ehdr->e_phnum; ++i)
2752 {
2753 if (phdr[i].p_type == PT_LOAD
2754 && (p_unwind->p_vaddr - phdr[i].p_vaddr) < phdr[i].p_memsz)
2755 {
2756 ok = 1;
2757 /* Get the segbase from the section containing the
2758 libunwind table. */
2759 segbase = phdr[i].p_vaddr + load_base;
2760 }
2761 }
2762 if (!ok)
2763 return -UNW_ENOINFO;
2764 }
2765
2766 dip->start_ip = p_text->p_vaddr + load_base;
2767 dip->end_ip = dip->start_ip + p_text->p_memsz;
2768 dip->gp = ia64_find_global_pointer (get_objfile_arch (objfile), ip);
2769 dip->format = UNW_INFO_FORMAT_REMOTE_TABLE;
2770 dip->u.rti.name_ptr = (unw_word_t) bfd_get_filename (bfd);
2771 dip->u.rti.segbase = segbase;
2772 dip->u.rti.table_len = p_unwind->p_memsz / sizeof (unw_word_t);
2773 dip->u.rti.table_data = p_unwind->p_vaddr + load_base;
2774
2775 return 0;
2776}
2777
2778/* Libunwind callback accessor function to acquire procedure unwind-info. */
2779static int
2780ia64_find_proc_info_x (unw_addr_space_t as, unw_word_t ip, unw_proc_info_t *pi,
2781 int need_unwind_info, void *arg)
2782{
2783 struct obj_section *sec = find_pc_section (ip);
2784 unw_dyn_info_t di;
2785 int ret;
2786 void *buf = NULL;
2787
2788 if (!sec)
2789 {
2790 /* XXX This only works if the host and the target architecture are
2791 both ia64 and if the have (more or less) the same kernel
2792 version. */
2793 if (get_kernel_table (ip, &di) < 0)
2794 return -UNW_ENOINFO;
2795
2796 if (gdbarch_debug >= 1)
2797 fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: %s -> "
2798 "(name=`%s',segbase=%s,start=%s,end=%s,gp=%s,"
2799 "length=%s,data=%s)\n",
2800 hex_string (ip), (char *)di.u.ti.name_ptr,
2801 hex_string (di.u.ti.segbase),
2802 hex_string (di.start_ip), hex_string (di.end_ip),
2803 hex_string (di.gp),
2804 pulongest (di.u.ti.table_len),
2805 hex_string ((CORE_ADDR)di.u.ti.table_data));
2806 }
2807 else
2808 {
2809 ret = ia64_find_unwind_table (sec->objfile, ip, &di, &buf);
2810 if (ret < 0)
2811 return ret;
2812
2813 if (gdbarch_debug >= 1)
2814 fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: %s -> "
2815 "(name=`%s',segbase=%s,start=%s,end=%s,gp=%s,"
2816 "length=%s,data=%s)\n",
2817 hex_string (ip), (char *)di.u.rti.name_ptr,
2818 hex_string (di.u.rti.segbase),
2819 hex_string (di.start_ip), hex_string (di.end_ip),
2820 hex_string (di.gp),
2821 pulongest (di.u.rti.table_len),
2822 hex_string (di.u.rti.table_data));
2823 }
2824
2825 ret = libunwind_search_unwind_table (&as, ip, &di, pi, need_unwind_info,
2826 arg);
2827
2828 /* We no longer need the dyn info storage so free it. */
2829 xfree (buf);
2830
2831 return ret;
2832}
2833
2834/* Libunwind callback accessor function for cleanup. */
2835static void
2836ia64_put_unwind_info (unw_addr_space_t as,
2837 unw_proc_info_t *pip, void *arg)
2838{
2839 /* Nothing required for now. */
2840}
2841
2842/* Libunwind callback accessor function to get head of the dynamic
2843 unwind-info registration list. */
2844static int
2845ia64_get_dyn_info_list (unw_addr_space_t as,
2846 unw_word_t *dilap, void *arg)
2847{
2848 struct obj_section *text_sec;
2849 struct objfile *objfile;
2850 unw_word_t ip, addr;
2851 unw_dyn_info_t di;
2852 int ret;
2853
2854 if (!libunwind_is_initialized ())
2855 return -UNW_ENOINFO;
2856
2857 for (objfile = object_files; objfile; objfile = objfile->next)
2858 {
2859 void *buf = NULL;
2860
2861 text_sec = objfile->sections + SECT_OFF_TEXT (objfile);
2862 ip = obj_section_addr (text_sec);
2863 ret = ia64_find_unwind_table (objfile, ip, &di, &buf);
2864 if (ret >= 0)
2865 {
2866 addr = libunwind_find_dyn_list (as, &di, arg);
2867 /* We no longer need the dyn info storage so free it. */
2868 xfree (buf);
2869
2870 if (addr)
2871 {
2872 if (gdbarch_debug >= 1)
2873 fprintf_unfiltered (gdb_stdlog,
2874 "dynamic unwind table in objfile %s "
2875 "at %s (gp=%s)\n",
2876 bfd_get_filename (objfile->obfd),
2877 hex_string (addr), hex_string (di.gp));
2878 *dilap = addr;
2879 return 0;
2880 }
2881 }
2882 }
2883 return -UNW_ENOINFO;
2884}
2885
2886
2887/* Frame interface functions for libunwind. */
2888
2889static void
2890ia64_libunwind_frame_this_id (struct frame_info *this_frame, void **this_cache,
2891 struct frame_id *this_id)
2892{
2893 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2894 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2895 struct frame_id id = outer_frame_id;
2896 char buf[8];
2897 CORE_ADDR bsp;
2898
2899 libunwind_frame_this_id (this_frame, this_cache, &id);
2900 if (frame_id_eq (id, outer_frame_id))
2901 {
2902 (*this_id) = outer_frame_id;
2903 return;
2904 }
2905
2906 /* We must add the bsp as the special address for frame comparison
2907 purposes. */
2908 get_frame_register (this_frame, IA64_BSP_REGNUM, buf);
2909 bsp = extract_unsigned_integer (buf, 8, byte_order);
2910
2911 (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp);
2912
2913 if (gdbarch_debug >= 1)
2914 fprintf_unfiltered (gdb_stdlog,
2915 "libunwind frame id: code %s, stack %s, "
2916 "special %s, this_frame %s\n",
2917 paddress (gdbarch, id.code_addr),
2918 paddress (gdbarch, id.stack_addr),
2919 paddress (gdbarch, bsp),
2920 host_address_to_string (this_frame));
2921}
2922
2923static struct value *
2924ia64_libunwind_frame_prev_register (struct frame_info *this_frame,
2925 void **this_cache, int regnum)
2926{
2927 int reg = regnum;
2928 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2929 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2930 struct value *val;
2931
2932 if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2933 reg = IA64_PR_REGNUM;
2934 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2935 reg = IA64_UNAT_REGNUM;
2936
2937 /* Let libunwind do most of the work. */
2938 val = libunwind_frame_prev_register (this_frame, this_cache, reg);
2939
2940 if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2941 {
2942 ULONGEST prN_val;
2943
2944 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
2945 {
2946 int rrb_pr = 0;
2947 ULONGEST cfm;
2948 unsigned char buf[MAX_REGISTER_SIZE];
2949
2950 /* Fetch predicate register rename base from current frame
2951 marker for this frame. */
2952 get_frame_register (this_frame, IA64_CFM_REGNUM, buf);
2953 cfm = extract_unsigned_integer (buf, 8, byte_order);
2954 rrb_pr = (cfm >> 32) & 0x3f;
2955
2956 /* Adjust the register number to account for register rotation. */
2957 regnum = VP16_REGNUM + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
2958 }
2959 prN_val = extract_bit_field (value_contents_all (val),
2960 regnum - VP0_REGNUM, 1);
2961 return frame_unwind_got_constant (this_frame, regnum, prN_val);
2962 }
2963
2964 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2965 {
2966 ULONGEST unatN_val;
2967
2968 unatN_val = extract_bit_field (value_contents_all (val),
2969 regnum - IA64_NAT0_REGNUM, 1);
2970 return frame_unwind_got_constant (this_frame, regnum, unatN_val);
2971 }
2972
2973 else if (regnum == IA64_BSP_REGNUM)
2974 {
2975 struct value *cfm_val;
2976 CORE_ADDR prev_bsp, prev_cfm;
2977
2978 /* We want to calculate the previous bsp as the end of the previous
2979 register stack frame. This corresponds to what the hardware bsp
2980 register will be if we pop the frame back which is why we might
2981 have been called. We know that libunwind will pass us back the
2982 beginning of the current frame so we should just add sof to it. */
2983 prev_bsp = extract_unsigned_integer (value_contents_all (val),
2984 8, byte_order);
2985 cfm_val = libunwind_frame_prev_register (this_frame, this_cache,
2986 IA64_CFM_REGNUM);
2987 prev_cfm = extract_unsigned_integer (value_contents_all (cfm_val),
2988 8, byte_order);
2989 prev_bsp = rse_address_add (prev_bsp, (prev_cfm & 0x7f));
2990
2991 return frame_unwind_got_constant (this_frame, regnum, prev_bsp);
2992 }
2993 else
2994 return val;
2995}
2996
2997static int
2998ia64_libunwind_frame_sniffer (const struct frame_unwind *self,
2999 struct frame_info *this_frame,
3000 void **this_cache)
3001{
3002 if (libunwind_is_initialized ()
3003 && libunwind_frame_sniffer (self, this_frame, this_cache))
3004 return 1;
3005
3006 return 0;
3007}
3008
3009static const struct frame_unwind ia64_libunwind_frame_unwind =
3010{
3011 NORMAL_FRAME,
3012 ia64_libunwind_frame_this_id,
3013 ia64_libunwind_frame_prev_register,
3014 NULL,
3015 ia64_libunwind_frame_sniffer,
3016 libunwind_frame_dealloc_cache
3017};
3018
3019static void
3020ia64_libunwind_sigtramp_frame_this_id (struct frame_info *this_frame,
3021 void **this_cache,
3022 struct frame_id *this_id)
3023{
3024 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3025 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3026 char buf[8];
3027 CORE_ADDR bsp;
3028 struct frame_id id = outer_frame_id;
3029 CORE_ADDR prev_ip;
3030
3031 libunwind_frame_this_id (this_frame, this_cache, &id);
3032 if (frame_id_eq (id, outer_frame_id))
3033 {
3034 (*this_id) = outer_frame_id;
3035 return;
3036 }
3037
3038 /* We must add the bsp as the special address for frame comparison
3039 purposes. */
3040 get_frame_register (this_frame, IA64_BSP_REGNUM, buf);
3041 bsp = extract_unsigned_integer (buf, 8, byte_order);
3042
3043 /* For a sigtramp frame, we don't make the check for previous ip being 0. */
3044 (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp);
3045
3046 if (gdbarch_debug >= 1)
3047 fprintf_unfiltered (gdb_stdlog,
3048 "libunwind sigtramp frame id: code %s, "
3049 "stack %s, special %s, this_frame %s\n",
3050 paddress (gdbarch, id.code_addr),
3051 paddress (gdbarch, id.stack_addr),
3052 paddress (gdbarch, bsp),
3053 host_address_to_string (this_frame));
3054}
3055
3056static struct value *
3057ia64_libunwind_sigtramp_frame_prev_register (struct frame_info *this_frame,
3058 void **this_cache, int regnum)
3059{
3060 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3061 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3062 struct value *prev_ip_val;
3063 CORE_ADDR prev_ip;
3064
3065 /* If the previous frame pc value is 0, then we want to use the SIGCONTEXT
3066 method of getting previous registers. */
3067 prev_ip_val = libunwind_frame_prev_register (this_frame, this_cache,
3068 IA64_IP_REGNUM);
3069 prev_ip = extract_unsigned_integer (value_contents_all (prev_ip_val),
3070 8, byte_order);
3071
3072 if (prev_ip == 0)
3073 {
3074 void *tmp_cache = NULL;
3075 return ia64_sigtramp_frame_prev_register (this_frame, &tmp_cache,
3076 regnum);
3077 }
3078 else
3079 return ia64_libunwind_frame_prev_register (this_frame, this_cache, regnum);
3080}
3081
3082static int
3083ia64_libunwind_sigtramp_frame_sniffer (const struct frame_unwind *self,
3084 struct frame_info *this_frame,
3085 void **this_cache)
3086{
3087 if (libunwind_is_initialized ())
3088 {
3089 if (libunwind_sigtramp_frame_sniffer (self, this_frame, this_cache))
3090 return 1;
3091 return 0;
3092 }
3093 else
3094 return ia64_sigtramp_frame_sniffer (self, this_frame, this_cache);
3095}
3096
3097static const struct frame_unwind ia64_libunwind_sigtramp_frame_unwind =
3098{
3099 SIGTRAMP_FRAME,
3100 ia64_libunwind_sigtramp_frame_this_id,
3101 ia64_libunwind_sigtramp_frame_prev_register,
3102 NULL,
3103 ia64_libunwind_sigtramp_frame_sniffer
3104};
3105
3106/* Set of libunwind callback acccessor functions. */
3107static unw_accessors_t ia64_unw_accessors =
3108{
3109 ia64_find_proc_info_x,
3110 ia64_put_unwind_info,
3111 ia64_get_dyn_info_list,
3112 ia64_access_mem,
3113 ia64_access_reg,
3114 ia64_access_fpreg,
3115 /* resume */
3116 /* get_proc_name */
3117};
3118
3119/* Set of special libunwind callback acccessor functions specific for accessing
3120 the rse registers. At the top of the stack, we want libunwind to figure out
3121 how to read r32 - r127. Though usually they are found sequentially in
3122 memory starting from $bof, this is not always true. */
3123static unw_accessors_t ia64_unw_rse_accessors =
3124{
3125 ia64_find_proc_info_x,
3126 ia64_put_unwind_info,
3127 ia64_get_dyn_info_list,
3128 ia64_access_mem,
3129 ia64_access_rse_reg,
3130 ia64_access_rse_fpreg,
3131 /* resume */
3132 /* get_proc_name */
3133};
3134
3135/* Set of ia64 gdb libunwind-frame callbacks and data for generic
3136 libunwind-frame code to use. */
3137static struct libunwind_descr ia64_libunwind_descr =
3138{
3139 ia64_gdb2uw_regnum,
3140 ia64_uw2gdb_regnum,
3141 ia64_is_fpreg,
3142 &ia64_unw_accessors,
3143 &ia64_unw_rse_accessors,
3144};
3145
3146#endif /* HAVE_LIBUNWIND_IA64_H */
3147
3148static int
3149ia64_use_struct_convention (struct type *type)
3150{
3151 struct type *float_elt_type;
3152
3153 /* Don't use the struct convention for anything but structure,
3154 union, or array types. */
3155 if (!(TYPE_CODE (type) == TYPE_CODE_STRUCT
3156 || TYPE_CODE (type) == TYPE_CODE_UNION
3157 || TYPE_CODE (type) == TYPE_CODE_ARRAY))
3158 return 0;
3159
3160 /* HFAs are structures (or arrays) consisting entirely of floating
3161 point values of the same length. Up to 8 of these are returned
3162 in registers. Don't use the struct convention when this is the
3163 case. */
3164 float_elt_type = is_float_or_hfa_type (type);
3165 if (float_elt_type != NULL
3166 && TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type) <= 8)
3167 return 0;
3168
3169 /* Other structs of length 32 or less are returned in r8-r11.
3170 Don't use the struct convention for those either. */
3171 return TYPE_LENGTH (type) > 32;
3172}
3173
3174static void
3175ia64_extract_return_value (struct type *type, struct regcache *regcache,
3176 gdb_byte *valbuf)
3177{
3178 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3179 struct type *float_elt_type;
3180
3181 float_elt_type = is_float_or_hfa_type (type);
3182 if (float_elt_type != NULL)
3183 {
3184 char from[MAX_REGISTER_SIZE];
3185 int offset = 0;
3186 int regnum = IA64_FR8_REGNUM;
3187 int n = TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type);
3188
3189 while (n-- > 0)
3190 {
3191 regcache_cooked_read (regcache, regnum, from);
3192 convert_typed_floating (from, ia64_ext_type (gdbarch),
3193 (char *)valbuf + offset, float_elt_type);
3194 offset += TYPE_LENGTH (float_elt_type);
3195 regnum++;
3196 }
3197 }
3198 else
3199 {
3200 ULONGEST val;
3201 int offset = 0;
3202 int regnum = IA64_GR8_REGNUM;
3203 int reglen = TYPE_LENGTH (register_type (gdbarch, IA64_GR8_REGNUM));
3204 int n = TYPE_LENGTH (type) / reglen;
3205 int m = TYPE_LENGTH (type) % reglen;
3206
3207 while (n-- > 0)
3208 {
3209 ULONGEST val;
3210 regcache_cooked_read_unsigned (regcache, regnum, &val);
3211 memcpy ((char *)valbuf + offset, &val, reglen);
3212 offset += reglen;
3213 regnum++;
3214 }
3215
3216 if (m)
3217 {
3218 regcache_cooked_read_unsigned (regcache, regnum, &val);
3219 memcpy ((char *)valbuf + offset, &val, m);
3220 }
3221 }
3222}
3223
3224static void
3225ia64_store_return_value (struct type *type, struct regcache *regcache,
3226 const gdb_byte *valbuf)
3227{
3228 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3229 struct type *float_elt_type;
3230
3231 float_elt_type = is_float_or_hfa_type (type);
3232 if (float_elt_type != NULL)
3233 {
3234 char to[MAX_REGISTER_SIZE];
3235 int offset = 0;
3236 int regnum = IA64_FR8_REGNUM;
3237 int n = TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type);
3238
3239 while (n-- > 0)
3240 {
3241 convert_typed_floating ((char *)valbuf + offset, float_elt_type,
3242 to, ia64_ext_type (gdbarch));
3243 regcache_cooked_write (regcache, regnum, to);
3244 offset += TYPE_LENGTH (float_elt_type);
3245 regnum++;
3246 }
3247 }
3248 else
3249 {
3250 ULONGEST val;
3251 int offset = 0;
3252 int regnum = IA64_GR8_REGNUM;
3253 int reglen = TYPE_LENGTH (register_type (gdbarch, IA64_GR8_REGNUM));
3254 int n = TYPE_LENGTH (type) / reglen;
3255 int m = TYPE_LENGTH (type) % reglen;
3256
3257 while (n-- > 0)
3258 {
3259 ULONGEST val;
3260 memcpy (&val, (char *)valbuf + offset, reglen);
3261 regcache_cooked_write_unsigned (regcache, regnum, val);
3262 offset += reglen;
3263 regnum++;
3264 }
3265
3266 if (m)
3267 {
3268 memcpy (&val, (char *)valbuf + offset, m);
3269 regcache_cooked_write_unsigned (regcache, regnum, val);
3270 }
3271 }
3272}
3273
3274static enum return_value_convention
3275ia64_return_value (struct gdbarch *gdbarch, struct type *func_type,
3276 struct type *valtype, struct regcache *regcache,
3277 gdb_byte *readbuf, const gdb_byte *writebuf)
3278{
3279 int struct_return = ia64_use_struct_convention (valtype);
3280
3281 if (writebuf != NULL)
3282 {
3283 gdb_assert (!struct_return);
3284 ia64_store_return_value (valtype, regcache, writebuf);
3285 }
3286
3287 if (readbuf != NULL)
3288 {
3289 gdb_assert (!struct_return);
3290 ia64_extract_return_value (valtype, regcache, readbuf);
3291 }
3292
3293 if (struct_return)
3294 return RETURN_VALUE_STRUCT_CONVENTION;
3295 else
3296 return RETURN_VALUE_REGISTER_CONVENTION;
3297}
3298
3299static int
3300is_float_or_hfa_type_recurse (struct type *t, struct type **etp)
3301{
3302 switch (TYPE_CODE (t))
3303 {
3304 case TYPE_CODE_FLT:
3305 if (*etp)
3306 return TYPE_LENGTH (*etp) == TYPE_LENGTH (t);
3307 else
3308 {
3309 *etp = t;
3310 return 1;
3311 }
3312 break;
3313 case TYPE_CODE_ARRAY:
3314 return
3315 is_float_or_hfa_type_recurse (check_typedef (TYPE_TARGET_TYPE (t)),
3316 etp);
3317 break;
3318 case TYPE_CODE_STRUCT:
3319 {
3320 int i;
3321
3322 for (i = 0; i < TYPE_NFIELDS (t); i++)
3323 if (!is_float_or_hfa_type_recurse
3324 (check_typedef (TYPE_FIELD_TYPE (t, i)), etp))
3325 return 0;
3326 return 1;
3327 }
3328 break;
3329 default:
3330 return 0;
3331 break;
3332 }
3333}
3334
3335/* Determine if the given type is one of the floating point types or
3336 and HFA (which is a struct, array, or combination thereof whose
3337 bottom-most elements are all of the same floating point type). */
3338
3339static struct type *
3340is_float_or_hfa_type (struct type *t)
3341{
3342 struct type *et = 0;
3343
3344 return is_float_or_hfa_type_recurse (t, &et) ? et : 0;
3345}
3346
3347
3348/* Return 1 if the alignment of T is such that the next even slot
3349 should be used. Return 0, if the next available slot should
3350 be used. (See section 8.5.1 of the IA-64 Software Conventions
3351 and Runtime manual). */
3352
3353static int
3354slot_alignment_is_next_even (struct type *t)
3355{
3356 switch (TYPE_CODE (t))
3357 {
3358 case TYPE_CODE_INT:
3359 case TYPE_CODE_FLT:
3360 if (TYPE_LENGTH (t) > 8)
3361 return 1;
3362 else
3363 return 0;
3364 case TYPE_CODE_ARRAY:
3365 return
3366 slot_alignment_is_next_even (check_typedef (TYPE_TARGET_TYPE (t)));
3367 case TYPE_CODE_STRUCT:
3368 {
3369 int i;
3370
3371 for (i = 0; i < TYPE_NFIELDS (t); i++)
3372 if (slot_alignment_is_next_even
3373 (check_typedef (TYPE_FIELD_TYPE (t, i))))
3374 return 1;
3375 return 0;
3376 }
3377 default:
3378 return 0;
3379 }
3380}
3381
3382/* Attempt to find (and return) the global pointer for the given
3383 function.
3384
3385 This is a rather nasty bit of code searchs for the .dynamic section
3386 in the objfile corresponding to the pc of the function we're trying
3387 to call. Once it finds the addresses at which the .dynamic section
3388 lives in the child process, it scans the Elf64_Dyn entries for a
3389 DT_PLTGOT tag. If it finds one of these, the corresponding
3390 d_un.d_ptr value is the global pointer. */
3391
3392static CORE_ADDR
3393ia64_find_global_pointer (struct gdbarch *gdbarch, CORE_ADDR faddr)
3394{
3395 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3396 struct obj_section *faddr_sect;
3397
3398 faddr_sect = find_pc_section (faddr);
3399 if (faddr_sect != NULL)
3400 {
3401 struct obj_section *osect;
3402
3403 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
3404 {
3405 if (strcmp (osect->the_bfd_section->name, ".dynamic") == 0)
3406 break;
3407 }
3408
3409 if (osect < faddr_sect->objfile->sections_end)
3410 {
3411 CORE_ADDR addr, endaddr;
3412
3413 addr = obj_section_addr (osect);
3414 endaddr = obj_section_endaddr (osect);
3415
3416 while (addr < endaddr)
3417 {
3418 int status;
3419 LONGEST tag;
3420 char buf[8];
3421
3422 status = target_read_memory (addr, buf, sizeof (buf));
3423 if (status != 0)
3424 break;
3425 tag = extract_signed_integer (buf, sizeof (buf), byte_order);
3426
3427 if (tag == DT_PLTGOT)
3428 {
3429 CORE_ADDR global_pointer;
3430
3431 status = target_read_memory (addr + 8, buf, sizeof (buf));
3432 if (status != 0)
3433 break;
3434 global_pointer = extract_unsigned_integer (buf, sizeof (buf),
3435 byte_order);
3436
3437 /* The payoff... */
3438 return global_pointer;
3439 }
3440
3441 if (tag == DT_NULL)
3442 break;
3443
3444 addr += 16;
3445 }
3446 }
3447 }
3448 return 0;
3449}
3450
3451/* Given a function's address, attempt to find (and return) the
3452 corresponding (canonical) function descriptor. Return 0 if
3453 not found. */
3454static CORE_ADDR
3455find_extant_func_descr (struct gdbarch *gdbarch, CORE_ADDR faddr)
3456{
3457 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3458 struct obj_section *faddr_sect;
3459
3460 /* Return early if faddr is already a function descriptor. */
3461 faddr_sect = find_pc_section (faddr);
3462 if (faddr_sect && strcmp (faddr_sect->the_bfd_section->name, ".opd") == 0)
3463 return faddr;
3464
3465 if (faddr_sect != NULL)
3466 {
3467 struct obj_section *osect;
3468 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
3469 {
3470 if (strcmp (osect->the_bfd_section->name, ".opd") == 0)
3471 break;
3472 }
3473
3474 if (osect < faddr_sect->objfile->sections_end)
3475 {
3476 CORE_ADDR addr, endaddr;
3477
3478 addr = obj_section_addr (osect);
3479 endaddr = obj_section_endaddr (osect);
3480
3481 while (addr < endaddr)
3482 {
3483 int status;
3484 LONGEST faddr2;
3485 char buf[8];
3486
3487 status = target_read_memory (addr, buf, sizeof (buf));
3488 if (status != 0)
3489 break;
3490 faddr2 = extract_signed_integer (buf, sizeof (buf), byte_order);
3491
3492 if (faddr == faddr2)
3493 return addr;
3494
3495 addr += 16;
3496 }
3497 }
3498 }
3499 return 0;
3500}
3501
3502/* Attempt to find a function descriptor corresponding to the
3503 given address. If none is found, construct one on the
3504 stack using the address at fdaptr. */
3505
3506static CORE_ADDR
3507find_func_descr (struct regcache *regcache, CORE_ADDR faddr, CORE_ADDR *fdaptr)
3508{
3509 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3510 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3511 CORE_ADDR fdesc;
3512
3513 fdesc = find_extant_func_descr (gdbarch, faddr);
3514
3515 if (fdesc == 0)
3516 {
3517 ULONGEST global_pointer;
3518 char buf[16];
3519
3520 fdesc = *fdaptr;
3521 *fdaptr += 16;
3522
3523 global_pointer = ia64_find_global_pointer (gdbarch, faddr);
3524
3525 if (global_pointer == 0)
3526 regcache_cooked_read_unsigned (regcache,
3527 IA64_GR1_REGNUM, &global_pointer);
3528
3529 store_unsigned_integer (buf, 8, byte_order, faddr);
3530 store_unsigned_integer (buf + 8, 8, byte_order, global_pointer);
3531
3532 write_memory (fdesc, buf, 16);
3533 }
3534
3535 return fdesc;
3536}
3537
3538/* Use the following routine when printing out function pointers
3539 so the user can see the function address rather than just the
3540 function descriptor. */
3541static CORE_ADDR
3542ia64_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr,
3543 struct target_ops *targ)
3544{
3545 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3546 struct obj_section *s;
3547 gdb_byte buf[8];
3548
3549 s = find_pc_section (addr);
3550
3551 /* check if ADDR points to a function descriptor. */
3552 if (s && strcmp (s->the_bfd_section->name, ".opd") == 0)
3553 return read_memory_unsigned_integer (addr, 8, byte_order);
3554
3555 /* Normally, functions live inside a section that is executable.
3556 So, if ADDR points to a non-executable section, then treat it
3557 as a function descriptor and return the target address iff
3558 the target address itself points to a section that is executable.
3559 Check first the memory of the whole length of 8 bytes is readable. */
3560 if (s && (s->the_bfd_section->flags & SEC_CODE) == 0
3561 && target_read_memory (addr, buf, 8) == 0)
3562 {
3563 CORE_ADDR pc = extract_unsigned_integer (buf, 8, byte_order);
3564 struct obj_section *pc_section = find_pc_section (pc);
3565
3566 if (pc_section && (pc_section->the_bfd_section->flags & SEC_CODE))
3567 return pc;
3568 }
3569
3570 /* There are also descriptors embedded in vtables. */
3571 if (s)
3572 {
3573 struct minimal_symbol *minsym;
3574
3575 minsym = lookup_minimal_symbol_by_pc (addr);
3576
3577 if (minsym && is_vtable_name (SYMBOL_LINKAGE_NAME (minsym)))
3578 return read_memory_unsigned_integer (addr, 8, byte_order);
3579 }
3580
3581 return addr;
3582}
3583
3584static CORE_ADDR
3585ia64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3586{
3587 return sp & ~0xfLL;
3588}
3589
3590static CORE_ADDR
3591ia64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3592 struct regcache *regcache, CORE_ADDR bp_addr,
3593 int nargs, struct value **args, CORE_ADDR sp,
3594 int struct_return, CORE_ADDR struct_addr)
3595{
3596 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3597 int argno;
3598 struct value *arg;
3599 struct type *type;
3600 int len, argoffset;
3601 int nslots, rseslots, memslots, slotnum, nfuncargs;
3602 int floatreg;
3603 ULONGEST bsp, cfm, pfs, new_bsp;
3604 CORE_ADDR funcdescaddr, pc, global_pointer;
3605 CORE_ADDR func_addr = find_function_addr (function, NULL);
3606
3607 nslots = 0;
3608 nfuncargs = 0;
3609 /* Count the number of slots needed for the arguments. */
3610 for (argno = 0; argno < nargs; argno++)
3611 {
3612 arg = args[argno];
3613 type = check_typedef (value_type (arg));
3614 len = TYPE_LENGTH (type);
3615
3616 if ((nslots & 1) && slot_alignment_is_next_even (type))
3617 nslots++;
3618
3619 if (TYPE_CODE (type) == TYPE_CODE_FUNC)
3620 nfuncargs++;
3621
3622 nslots += (len + 7) / 8;
3623 }
3624
3625 /* Divvy up the slots between the RSE and the memory stack. */
3626 rseslots = (nslots > 8) ? 8 : nslots;
3627 memslots = nslots - rseslots;
3628
3629 /* Allocate a new RSE frame. */
3630 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
3631
3632 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
3633 new_bsp = rse_address_add (bsp, rseslots);
3634 regcache_cooked_write_unsigned (regcache, IA64_BSP_REGNUM, new_bsp);
3635
3636 regcache_cooked_read_unsigned (regcache, IA64_PFS_REGNUM, &pfs);
3637 pfs &= 0xc000000000000000LL;
3638 pfs |= (cfm & 0xffffffffffffLL);
3639 regcache_cooked_write_unsigned (regcache, IA64_PFS_REGNUM, pfs);
3640
3641 cfm &= 0xc000000000000000LL;
3642 cfm |= rseslots;
3643 regcache_cooked_write_unsigned (regcache, IA64_CFM_REGNUM, cfm);
3644
3645 /* We will attempt to find function descriptors in the .opd segment,
3646 but if we can't we'll construct them ourselves. That being the
3647 case, we'll need to reserve space on the stack for them. */
3648 funcdescaddr = sp - nfuncargs * 16;
3649 funcdescaddr &= ~0xfLL;
3650
3651 /* Adjust the stack pointer to it's new value. The calling conventions
3652 require us to have 16 bytes of scratch, plus whatever space is
3653 necessary for the memory slots and our function descriptors. */
3654 sp = sp - 16 - (memslots + nfuncargs) * 8;
3655 sp &= ~0xfLL; /* Maintain 16 byte alignment. */
3656
3657 /* Place the arguments where they belong. The arguments will be
3658 either placed in the RSE backing store or on the memory stack.
3659 In addition, floating point arguments or HFAs are placed in
3660 floating point registers. */
3661 slotnum = 0;
3662 floatreg = IA64_FR8_REGNUM;
3663 for (argno = 0; argno < nargs; argno++)
3664 {
3665 struct type *float_elt_type;
3666
3667 arg = args[argno];
3668 type = check_typedef (value_type (arg));
3669 len = TYPE_LENGTH (type);
3670
3671 /* Special handling for function parameters. */
3672 if (len == 8
3673 && TYPE_CODE (type) == TYPE_CODE_PTR
3674 && TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)
3675 {
3676 char val_buf[8];
3677 ULONGEST faddr = extract_unsigned_integer (value_contents (arg),
3678 8, byte_order);
3679 store_unsigned_integer (val_buf, 8, byte_order,
3680 find_func_descr (regcache, faddr,
3681 &funcdescaddr));
3682 if (slotnum < rseslots)
3683 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
3684 else
3685 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3686 slotnum++;
3687 continue;
3688 }
3689
3690 /* Normal slots. */
3691
3692 /* Skip odd slot if necessary... */
3693 if ((slotnum & 1) && slot_alignment_is_next_even (type))
3694 slotnum++;
3695
3696 argoffset = 0;
3697 while (len > 0)
3698 {
3699 char val_buf[8];
3700
3701 memset (val_buf, 0, 8);
3702 memcpy (val_buf, value_contents (arg) + argoffset,
3703 (len > 8) ? 8 : len);
3704
3705 if (slotnum < rseslots)
3706 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
3707 else
3708 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3709
3710 argoffset += 8;
3711 len -= 8;
3712 slotnum++;
3713 }
3714
3715 /* Handle floating point types (including HFAs). */
3716 float_elt_type = is_float_or_hfa_type (type);
3717 if (float_elt_type != NULL)
3718 {
3719 argoffset = 0;
3720 len = TYPE_LENGTH (type);
3721 while (len > 0 && floatreg < IA64_FR16_REGNUM)
3722 {
3723 char to[MAX_REGISTER_SIZE];
3724 convert_typed_floating (value_contents (arg) + argoffset,
3725 float_elt_type, to,
3726 ia64_ext_type (gdbarch));
3727 regcache_cooked_write (regcache, floatreg, (void *)to);
3728 floatreg++;
3729 argoffset += TYPE_LENGTH (float_elt_type);
3730 len -= TYPE_LENGTH (float_elt_type);
3731 }
3732 }
3733 }
3734
3735 /* Store the struct return value in r8 if necessary. */
3736 if (struct_return)
3737 {
3738 regcache_cooked_write_unsigned (regcache, IA64_GR8_REGNUM,
3739 (ULONGEST) struct_addr);
3740 }
3741
3742 global_pointer = ia64_find_global_pointer (gdbarch, func_addr);
3743
3744 if (global_pointer != 0)
3745 regcache_cooked_write_unsigned (regcache, IA64_GR1_REGNUM, global_pointer);
3746
3747 regcache_cooked_write_unsigned (regcache, IA64_BR0_REGNUM, bp_addr);
3748
3749 regcache_cooked_write_unsigned (regcache, sp_regnum, sp);
3750
3751 return sp;
3752}
3753
3754static struct frame_id
3755ia64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
3756{
3757 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3758 char buf[8];
3759 CORE_ADDR sp, bsp;
3760
3761 get_frame_register (this_frame, sp_regnum, buf);
3762 sp = extract_unsigned_integer (buf, 8, byte_order);
3763
3764 get_frame_register (this_frame, IA64_BSP_REGNUM, buf);
3765 bsp = extract_unsigned_integer (buf, 8, byte_order);
3766
3767 if (gdbarch_debug >= 1)
3768 fprintf_unfiltered (gdb_stdlog,
3769 "dummy frame id: code %s, stack %s, special %s\n",
3770 paddress (gdbarch, get_frame_pc (this_frame)),
3771 paddress (gdbarch, sp), paddress (gdbarch, bsp));
3772
3773 return frame_id_build_special (sp, get_frame_pc (this_frame), bsp);
3774}
3775
3776static CORE_ADDR
3777ia64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
3778{
3779 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3780 char buf[8];
3781 CORE_ADDR ip, psr, pc;
3782
3783 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
3784 ip = extract_unsigned_integer (buf, 8, byte_order);
3785 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
3786 psr = extract_unsigned_integer (buf, 8, byte_order);
3787
3788 pc = (ip & ~0xf) | ((psr >> 41) & 3);
3789 return pc;
3790}
3791
3792static int
3793ia64_print_insn (bfd_vma memaddr, struct disassemble_info *info)
3794{
3795 info->bytes_per_line = SLOT_MULTIPLIER;
3796 return print_insn_ia64 (memaddr, info);
3797}
3798
3799static struct gdbarch *
3800ia64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3801{
3802 struct gdbarch *gdbarch;
3803 struct gdbarch_tdep *tdep;
3804
3805 /* If there is already a candidate, use it. */
3806 arches = gdbarch_list_lookup_by_info (arches, &info);
3807 if (arches != NULL)
3808 return arches->gdbarch;
3809
3810 tdep = xzalloc (sizeof (struct gdbarch_tdep));
3811 gdbarch = gdbarch_alloc (&info, tdep);
3812
3813 /* According to the ia64 specs, instructions that store long double
3814 floats in memory use a long-double format different than that
3815 used in the floating registers. The memory format matches the
3816 x86 extended float format which is 80 bits. An OS may choose to
3817 use this format (e.g. GNU/Linux) or choose to use a different
3818 format for storing long doubles (e.g. HPUX). In the latter case,
3819 the setting of the format may be moved/overridden in an
3820 OS-specific tdep file. */
3821 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
3822
3823 set_gdbarch_short_bit (gdbarch, 16);
3824 set_gdbarch_int_bit (gdbarch, 32);
3825 set_gdbarch_long_bit (gdbarch, 64);
3826 set_gdbarch_long_long_bit (gdbarch, 64);
3827 set_gdbarch_float_bit (gdbarch, 32);
3828 set_gdbarch_double_bit (gdbarch, 64);
3829 set_gdbarch_long_double_bit (gdbarch, 128);
3830 set_gdbarch_ptr_bit (gdbarch, 64);
3831
3832 set_gdbarch_num_regs (gdbarch, NUM_IA64_RAW_REGS);
3833 set_gdbarch_num_pseudo_regs (gdbarch,
3834 LAST_PSEUDO_REGNUM - FIRST_PSEUDO_REGNUM);
3835 set_gdbarch_sp_regnum (gdbarch, sp_regnum);
3836 set_gdbarch_fp0_regnum (gdbarch, IA64_FR0_REGNUM);
3837
3838 set_gdbarch_register_name (gdbarch, ia64_register_name);
3839 set_gdbarch_register_type (gdbarch, ia64_register_type);
3840
3841 set_gdbarch_pseudo_register_read (gdbarch, ia64_pseudo_register_read);
3842 set_gdbarch_pseudo_register_write (gdbarch, ia64_pseudo_register_write);
3843 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, ia64_dwarf_reg_to_regnum);
3844 set_gdbarch_register_reggroup_p (gdbarch, ia64_register_reggroup_p);
3845 set_gdbarch_convert_register_p (gdbarch, ia64_convert_register_p);
3846 set_gdbarch_register_to_value (gdbarch, ia64_register_to_value);
3847 set_gdbarch_value_to_register (gdbarch, ia64_value_to_register);
3848
3849 set_gdbarch_skip_prologue (gdbarch, ia64_skip_prologue);
3850
3851 set_gdbarch_return_value (gdbarch, ia64_return_value);
3852
3853 set_gdbarch_memory_insert_breakpoint (gdbarch,
3854 ia64_memory_insert_breakpoint);
3855 set_gdbarch_memory_remove_breakpoint (gdbarch,
3856 ia64_memory_remove_breakpoint);
3857 set_gdbarch_breakpoint_from_pc (gdbarch, ia64_breakpoint_from_pc);
3858 set_gdbarch_read_pc (gdbarch, ia64_read_pc);
3859 set_gdbarch_write_pc (gdbarch, ia64_write_pc);
3860
3861 /* Settings for calling functions in the inferior. */
3862 set_gdbarch_push_dummy_call (gdbarch, ia64_push_dummy_call);
3863 set_gdbarch_frame_align (gdbarch, ia64_frame_align);
3864 set_gdbarch_dummy_id (gdbarch, ia64_dummy_id);
3865
3866 set_gdbarch_unwind_pc (gdbarch, ia64_unwind_pc);
3867#ifdef HAVE_LIBUNWIND_IA64_H
3868 frame_unwind_append_unwinder (gdbarch,
3869 &ia64_libunwind_sigtramp_frame_unwind);
3870 frame_unwind_append_unwinder (gdbarch, &ia64_libunwind_frame_unwind);
3871 frame_unwind_append_unwinder (gdbarch, &ia64_sigtramp_frame_unwind);
3872 libunwind_frame_set_descr (gdbarch, &ia64_libunwind_descr);
3873#else
3874 frame_unwind_append_unwinder (gdbarch, &ia64_sigtramp_frame_unwind);
3875#endif
3876 frame_unwind_append_unwinder (gdbarch, &ia64_frame_unwind);
3877 frame_base_set_default (gdbarch, &ia64_frame_base);
3878
3879 /* Settings that should be unnecessary. */
3880 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3881
3882 set_gdbarch_print_insn (gdbarch, ia64_print_insn);
3883 set_gdbarch_convert_from_func_ptr_addr (gdbarch,
3884 ia64_convert_from_func_ptr_addr);
3885
3886 /* The virtual table contains 16-byte descriptors, not pointers to
3887 descriptors. */
3888 set_gdbarch_vtable_function_descriptors (gdbarch, 1);
3889
3890 /* Hook in ABI-specific overrides, if they have been registered. */
3891 gdbarch_init_osabi (info, gdbarch);
3892
3893 return gdbarch;
3894}
3895
3896extern initialize_file_ftype _initialize_ia64_tdep; /* -Wmissing-prototypes */
3897
3898void
3899_initialize_ia64_tdep (void)
3900{
3901 gdbarch_register (bfd_arch_ia64, ia64_gdbarch_init, NULL);
3902}
GDB Binutils - Deliverables
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