| 1 | /* Native-dependent code for GNU/Linux on MIPS processors. |
| 2 | |
| 3 | Copyright (C) 2001-2016 Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 19 | |
| 20 | #include "defs.h" |
| 21 | #include "command.h" |
| 22 | #include "gdbcmd.h" |
| 23 | #include "inferior.h" |
| 24 | #include "mips-tdep.h" |
| 25 | #include "target.h" |
| 26 | #include "regcache.h" |
| 27 | #include "linux-nat.h" |
| 28 | #include "mips-linux-tdep.h" |
| 29 | #include "target-descriptions.h" |
| 30 | |
| 31 | #include "gdb_proc_service.h" |
| 32 | #include "gregset.h" |
| 33 | |
| 34 | #include <sgidefs.h> |
| 35 | #include "nat/gdb_ptrace.h" |
| 36 | #include <asm/ptrace.h> |
| 37 | |
| 38 | #include "nat/mips-linux-watch.h" |
| 39 | |
| 40 | #include "features/mips-linux.c" |
| 41 | #include "features/mips-dsp-linux.c" |
| 42 | #include "features/mips64-linux.c" |
| 43 | #include "features/mips64-dsp-linux.c" |
| 44 | |
| 45 | #ifndef PTRACE_GET_THREAD_AREA |
| 46 | #define PTRACE_GET_THREAD_AREA 25 |
| 47 | #endif |
| 48 | |
| 49 | /* Assume that we have PTRACE_GETREGS et al. support. If we do not, |
| 50 | we'll clear this and use PTRACE_PEEKUSER instead. */ |
| 51 | static int have_ptrace_regsets = 1; |
| 52 | |
| 53 | /* Saved function pointers to fetch and store a single register using |
| 54 | PTRACE_PEEKUSER and PTRACE_POKEUSER. */ |
| 55 | |
| 56 | static void (*super_fetch_registers) (struct target_ops *, |
| 57 | struct regcache *, int); |
| 58 | static void (*super_store_registers) (struct target_ops *, |
| 59 | struct regcache *, int); |
| 60 | |
| 61 | static void (*super_close) (struct target_ops *); |
| 62 | |
| 63 | /* Map gdb internal register number to ptrace ``address''. |
| 64 | These ``addresses'' are normally defined in <asm/ptrace.h>. |
| 65 | |
| 66 | ptrace does not provide a way to read (or set) MIPS_PS_REGNUM, |
| 67 | and there's no point in reading or setting MIPS_ZERO_REGNUM. |
| 68 | We also can not set BADVADDR, CAUSE, or FCRIR via ptrace(). */ |
| 69 | |
| 70 | static CORE_ADDR |
| 71 | mips_linux_register_addr (struct gdbarch *gdbarch, int regno, int store) |
| 72 | { |
| 73 | CORE_ADDR regaddr; |
| 74 | |
| 75 | if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
| 76 | error (_("Bogon register number %d."), regno); |
| 77 | |
| 78 | if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32) |
| 79 | regaddr = regno; |
| 80 | else if ((regno >= mips_regnum (gdbarch)->fp0) |
| 81 | && (regno < mips_regnum (gdbarch)->fp0 + 32)) |
| 82 | regaddr = FPR_BASE + (regno - mips_regnum (gdbarch)->fp0); |
| 83 | else if (regno == mips_regnum (gdbarch)->pc) |
| 84 | regaddr = PC; |
| 85 | else if (regno == mips_regnum (gdbarch)->cause) |
| 86 | regaddr = store? (CORE_ADDR) -1 : CAUSE; |
| 87 | else if (regno == mips_regnum (gdbarch)->badvaddr) |
| 88 | regaddr = store? (CORE_ADDR) -1 : BADVADDR; |
| 89 | else if (regno == mips_regnum (gdbarch)->lo) |
| 90 | regaddr = MMLO; |
| 91 | else if (regno == mips_regnum (gdbarch)->hi) |
| 92 | regaddr = MMHI; |
| 93 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
| 94 | regaddr = FPC_CSR; |
| 95 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
| 96 | regaddr = store? (CORE_ADDR) -1 : FPC_EIR; |
| 97 | else if (mips_regnum (gdbarch)->dspacc != -1 |
| 98 | && regno >= mips_regnum (gdbarch)->dspacc |
| 99 | && regno < mips_regnum (gdbarch)->dspacc + 6) |
| 100 | regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc); |
| 101 | else if (regno == mips_regnum (gdbarch)->dspctl) |
| 102 | regaddr = DSP_CONTROL; |
| 103 | else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM) |
| 104 | regaddr = 0; |
| 105 | else |
| 106 | regaddr = (CORE_ADDR) -1; |
| 107 | |
| 108 | return regaddr; |
| 109 | } |
| 110 | |
| 111 | static CORE_ADDR |
| 112 | mips64_linux_register_addr (struct gdbarch *gdbarch, int regno, int store) |
| 113 | { |
| 114 | CORE_ADDR regaddr; |
| 115 | |
| 116 | if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
| 117 | error (_("Bogon register number %d."), regno); |
| 118 | |
| 119 | if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32) |
| 120 | regaddr = regno; |
| 121 | else if ((regno >= mips_regnum (gdbarch)->fp0) |
| 122 | && (regno < mips_regnum (gdbarch)->fp0 + 32)) |
| 123 | regaddr = MIPS64_FPR_BASE + (regno - gdbarch_fp0_regnum (gdbarch)); |
| 124 | else if (regno == mips_regnum (gdbarch)->pc) |
| 125 | regaddr = MIPS64_PC; |
| 126 | else if (regno == mips_regnum (gdbarch)->cause) |
| 127 | regaddr = store? (CORE_ADDR) -1 : MIPS64_CAUSE; |
| 128 | else if (regno == mips_regnum (gdbarch)->badvaddr) |
| 129 | regaddr = store? (CORE_ADDR) -1 : MIPS64_BADVADDR; |
| 130 | else if (regno == mips_regnum (gdbarch)->lo) |
| 131 | regaddr = MIPS64_MMLO; |
| 132 | else if (regno == mips_regnum (gdbarch)->hi) |
| 133 | regaddr = MIPS64_MMHI; |
| 134 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
| 135 | regaddr = MIPS64_FPC_CSR; |
| 136 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
| 137 | regaddr = store? (CORE_ADDR) -1 : MIPS64_FPC_EIR; |
| 138 | else if (mips_regnum (gdbarch)->dspacc != -1 |
| 139 | && regno >= mips_regnum (gdbarch)->dspacc |
| 140 | && regno < mips_regnum (gdbarch)->dspacc + 6) |
| 141 | regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc); |
| 142 | else if (regno == mips_regnum (gdbarch)->dspctl) |
| 143 | regaddr = DSP_CONTROL; |
| 144 | else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM) |
| 145 | regaddr = 0; |
| 146 | else |
| 147 | regaddr = (CORE_ADDR) -1; |
| 148 | |
| 149 | return regaddr; |
| 150 | } |
| 151 | |
| 152 | /* Fetch the thread-local storage pointer for libthread_db. */ |
| 153 | |
| 154 | ps_err_e |
| 155 | ps_get_thread_area (const struct ps_prochandle *ph, |
| 156 | lwpid_t lwpid, int idx, void **base) |
| 157 | { |
| 158 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) |
| 159 | return PS_ERR; |
| 160 | |
| 161 | /* IDX is the bias from the thread pointer to the beginning of the |
| 162 | thread descriptor. It has to be subtracted due to implementation |
| 163 | quirks in libthread_db. */ |
| 164 | *base = (void *) ((char *)*base - idx); |
| 165 | |
| 166 | return PS_OK; |
| 167 | } |
| 168 | |
| 169 | /* Wrapper functions. These are only used by libthread_db. */ |
| 170 | |
| 171 | void |
| 172 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
| 173 | { |
| 174 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
| 175 | mips_supply_gregset (regcache, (const mips_elf_gregset_t *) gregsetp); |
| 176 | else |
| 177 | mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *) gregsetp); |
| 178 | } |
| 179 | |
| 180 | void |
| 181 | fill_gregset (const struct regcache *regcache, |
| 182 | gdb_gregset_t *gregsetp, int regno) |
| 183 | { |
| 184 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
| 185 | mips_fill_gregset (regcache, (mips_elf_gregset_t *) gregsetp, regno); |
| 186 | else |
| 187 | mips64_fill_gregset (regcache, (mips64_elf_gregset_t *) gregsetp, regno); |
| 188 | } |
| 189 | |
| 190 | void |
| 191 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
| 192 | { |
| 193 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
| 194 | mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *) fpregsetp); |
| 195 | else |
| 196 | mips64_supply_fpregset (regcache, |
| 197 | (const mips64_elf_fpregset_t *) fpregsetp); |
| 198 | } |
| 199 | |
| 200 | void |
| 201 | fill_fpregset (const struct regcache *regcache, |
| 202 | gdb_fpregset_t *fpregsetp, int regno) |
| 203 | { |
| 204 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
| 205 | mips_fill_fpregset (regcache, (mips_elf_fpregset_t *) fpregsetp, regno); |
| 206 | else |
| 207 | mips64_fill_fpregset (regcache, |
| 208 | (mips64_elf_fpregset_t *) fpregsetp, regno); |
| 209 | } |
| 210 | |
| 211 | |
| 212 | /* Fetch REGNO (or all registers if REGNO == -1) from the target |
| 213 | using PTRACE_GETREGS et al. */ |
| 214 | |
| 215 | static void |
| 216 | mips64_linux_regsets_fetch_registers (struct target_ops *ops, |
| 217 | struct regcache *regcache, int regno) |
| 218 | { |
| 219 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 220 | int is_fp, is_dsp; |
| 221 | int have_dsp; |
| 222 | int regi; |
| 223 | int tid; |
| 224 | |
| 225 | if (regno >= mips_regnum (gdbarch)->fp0 |
| 226 | && regno <= mips_regnum (gdbarch)->fp0 + 32) |
| 227 | is_fp = 1; |
| 228 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
| 229 | is_fp = 1; |
| 230 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
| 231 | is_fp = 1; |
| 232 | else |
| 233 | is_fp = 0; |
| 234 | |
| 235 | /* DSP registers are optional and not a part of any set. */ |
| 236 | have_dsp = mips_regnum (gdbarch)->dspctl != -1; |
| 237 | if (!have_dsp) |
| 238 | is_dsp = 0; |
| 239 | else if (regno >= mips_regnum (gdbarch)->dspacc |
| 240 | && regno < mips_regnum (gdbarch)->dspacc + 6) |
| 241 | is_dsp = 1; |
| 242 | else if (regno == mips_regnum (gdbarch)->dspctl) |
| 243 | is_dsp = 1; |
| 244 | else |
| 245 | is_dsp = 0; |
| 246 | |
| 247 | tid = ptid_get_lwp (inferior_ptid); |
| 248 | if (tid == 0) |
| 249 | tid = ptid_get_pid (inferior_ptid); |
| 250 | |
| 251 | if (regno == -1 || (!is_fp && !is_dsp)) |
| 252 | { |
| 253 | mips64_elf_gregset_t regs; |
| 254 | |
| 255 | if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) |
| 256 | { |
| 257 | if (errno == EIO) |
| 258 | { |
| 259 | have_ptrace_regsets = 0; |
| 260 | return; |
| 261 | } |
| 262 | perror_with_name (_("Couldn't get registers")); |
| 263 | } |
| 264 | |
| 265 | mips64_supply_gregset (regcache, |
| 266 | (const mips64_elf_gregset_t *) ®s); |
| 267 | } |
| 268 | |
| 269 | if (regno == -1 || is_fp) |
| 270 | { |
| 271 | mips64_elf_fpregset_t fp_regs; |
| 272 | |
| 273 | if (ptrace (PTRACE_GETFPREGS, tid, 0L, |
| 274 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) |
| 275 | { |
| 276 | if (errno == EIO) |
| 277 | { |
| 278 | have_ptrace_regsets = 0; |
| 279 | return; |
| 280 | } |
| 281 | perror_with_name (_("Couldn't get FP registers")); |
| 282 | } |
| 283 | |
| 284 | mips64_supply_fpregset (regcache, |
| 285 | (const mips64_elf_fpregset_t *) &fp_regs); |
| 286 | } |
| 287 | |
| 288 | if (is_dsp) |
| 289 | super_fetch_registers (ops, regcache, regno); |
| 290 | else if (regno == -1 && have_dsp) |
| 291 | { |
| 292 | for (regi = mips_regnum (gdbarch)->dspacc; |
| 293 | regi < mips_regnum (gdbarch)->dspacc + 6; |
| 294 | regi++) |
| 295 | super_fetch_registers (ops, regcache, regi); |
| 296 | super_fetch_registers (ops, regcache, mips_regnum (gdbarch)->dspctl); |
| 297 | } |
| 298 | } |
| 299 | |
| 300 | /* Store REGNO (or all registers if REGNO == -1) to the target |
| 301 | using PTRACE_SETREGS et al. */ |
| 302 | |
| 303 | static void |
| 304 | mips64_linux_regsets_store_registers (struct target_ops *ops, |
| 305 | struct regcache *regcache, int regno) |
| 306 | { |
| 307 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 308 | int is_fp, is_dsp; |
| 309 | int have_dsp; |
| 310 | int regi; |
| 311 | int tid; |
| 312 | |
| 313 | if (regno >= mips_regnum (gdbarch)->fp0 |
| 314 | && regno <= mips_regnum (gdbarch)->fp0 + 32) |
| 315 | is_fp = 1; |
| 316 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
| 317 | is_fp = 1; |
| 318 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
| 319 | is_fp = 1; |
| 320 | else |
| 321 | is_fp = 0; |
| 322 | |
| 323 | /* DSP registers are optional and not a part of any set. */ |
| 324 | have_dsp = mips_regnum (gdbarch)->dspctl != -1; |
| 325 | if (!have_dsp) |
| 326 | is_dsp = 0; |
| 327 | else if (regno >= mips_regnum (gdbarch)->dspacc |
| 328 | && regno < mips_regnum (gdbarch)->dspacc + 6) |
| 329 | is_dsp = 1; |
| 330 | else if (regno == mips_regnum (gdbarch)->dspctl) |
| 331 | is_dsp = 1; |
| 332 | else |
| 333 | is_dsp = 0; |
| 334 | |
| 335 | tid = ptid_get_lwp (inferior_ptid); |
| 336 | if (tid == 0) |
| 337 | tid = ptid_get_pid (inferior_ptid); |
| 338 | |
| 339 | if (regno == -1 || (!is_fp && !is_dsp)) |
| 340 | { |
| 341 | mips64_elf_gregset_t regs; |
| 342 | |
| 343 | if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) |
| 344 | perror_with_name (_("Couldn't get registers")); |
| 345 | |
| 346 | mips64_fill_gregset (regcache, ®s, regno); |
| 347 | |
| 348 | if (ptrace (PTRACE_SETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) |
| 349 | perror_with_name (_("Couldn't set registers")); |
| 350 | } |
| 351 | |
| 352 | if (regno == -1 || is_fp) |
| 353 | { |
| 354 | mips64_elf_fpregset_t fp_regs; |
| 355 | |
| 356 | if (ptrace (PTRACE_GETFPREGS, tid, 0L, |
| 357 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) |
| 358 | perror_with_name (_("Couldn't get FP registers")); |
| 359 | |
| 360 | mips64_fill_fpregset (regcache, &fp_regs, regno); |
| 361 | |
| 362 | if (ptrace (PTRACE_SETFPREGS, tid, 0L, |
| 363 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) |
| 364 | perror_with_name (_("Couldn't set FP registers")); |
| 365 | } |
| 366 | |
| 367 | if (is_dsp) |
| 368 | super_store_registers (ops, regcache, regno); |
| 369 | else if (regno == -1 && have_dsp) |
| 370 | { |
| 371 | for (regi = mips_regnum (gdbarch)->dspacc; |
| 372 | regi < mips_regnum (gdbarch)->dspacc + 6; |
| 373 | regi++) |
| 374 | super_store_registers (ops, regcache, regi); |
| 375 | super_store_registers (ops, regcache, mips_regnum (gdbarch)->dspctl); |
| 376 | } |
| 377 | } |
| 378 | |
| 379 | /* Fetch REGNO (or all registers if REGNO == -1) from the target |
| 380 | using any working method. */ |
| 381 | |
| 382 | static void |
| 383 | mips64_linux_fetch_registers (struct target_ops *ops, |
| 384 | struct regcache *regcache, int regnum) |
| 385 | { |
| 386 | /* Unless we already know that PTRACE_GETREGS does not work, try it. */ |
| 387 | if (have_ptrace_regsets) |
| 388 | mips64_linux_regsets_fetch_registers (ops, regcache, regnum); |
| 389 | |
| 390 | /* If we know, or just found out, that PTRACE_GETREGS does not work, fall |
| 391 | back to PTRACE_PEEKUSER. */ |
| 392 | if (!have_ptrace_regsets) |
| 393 | super_fetch_registers (ops, regcache, regnum); |
| 394 | } |
| 395 | |
| 396 | /* Store REGNO (or all registers if REGNO == -1) to the target |
| 397 | using any working method. */ |
| 398 | |
| 399 | static void |
| 400 | mips64_linux_store_registers (struct target_ops *ops, |
| 401 | struct regcache *regcache, int regnum) |
| 402 | { |
| 403 | /* Unless we already know that PTRACE_GETREGS does not work, try it. */ |
| 404 | if (have_ptrace_regsets) |
| 405 | mips64_linux_regsets_store_registers (ops, regcache, regnum); |
| 406 | |
| 407 | /* If we know, or just found out, that PTRACE_GETREGS does not work, fall |
| 408 | back to PTRACE_PEEKUSER. */ |
| 409 | if (!have_ptrace_regsets) |
| 410 | super_store_registers (ops, regcache, regnum); |
| 411 | } |
| 412 | |
| 413 | /* Return the address in the core dump or inferior of register |
| 414 | REGNO. */ |
| 415 | |
| 416 | static CORE_ADDR |
| 417 | mips_linux_register_u_offset (struct gdbarch *gdbarch, int regno, int store_p) |
| 418 | { |
| 419 | if (mips_abi_regsize (gdbarch) == 8) |
| 420 | return mips64_linux_register_addr (gdbarch, regno, store_p); |
| 421 | else |
| 422 | return mips_linux_register_addr (gdbarch, regno, store_p); |
| 423 | } |
| 424 | |
| 425 | static const struct target_desc * |
| 426 | mips_linux_read_description (struct target_ops *ops) |
| 427 | { |
| 428 | static int have_dsp = -1; |
| 429 | |
| 430 | if (have_dsp < 0) |
| 431 | { |
| 432 | int tid; |
| 433 | |
| 434 | tid = ptid_get_lwp (inferior_ptid); |
| 435 | if (tid == 0) |
| 436 | tid = ptid_get_pid (inferior_ptid); |
| 437 | |
| 438 | errno = 0; |
| 439 | ptrace (PTRACE_PEEKUSER, tid, DSP_CONTROL, 0); |
| 440 | switch (errno) |
| 441 | { |
| 442 | case 0: |
| 443 | have_dsp = 1; |
| 444 | break; |
| 445 | case EIO: |
| 446 | have_dsp = 0; |
| 447 | break; |
| 448 | default: |
| 449 | perror_with_name (_("Couldn't check DSP support")); |
| 450 | break; |
| 451 | } |
| 452 | } |
| 453 | |
| 454 | /* Report that target registers are a size we know for sure |
| 455 | that we can get from ptrace. */ |
| 456 | if (_MIPS_SIM == _ABIO32) |
| 457 | return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux; |
| 458 | else |
| 459 | return have_dsp ? tdesc_mips64_dsp_linux : tdesc_mips64_linux; |
| 460 | } |
| 461 | |
| 462 | /* -1 if the kernel and/or CPU do not support watch registers. |
| 463 | 1 if watch_readback is valid and we can read style, num_valid |
| 464 | and the masks. |
| 465 | 0 if we need to read the watch_readback. */ |
| 466 | |
| 467 | static int watch_readback_valid; |
| 468 | |
| 469 | /* Cached watch register read values. */ |
| 470 | |
| 471 | static struct pt_watch_regs watch_readback; |
| 472 | |
| 473 | static struct mips_watchpoint *current_watches; |
| 474 | |
| 475 | /* The current set of watch register values for writing the |
| 476 | registers. */ |
| 477 | |
| 478 | static struct pt_watch_regs watch_mirror; |
| 479 | |
| 480 | static void |
| 481 | mips_show_dr (const char *func, CORE_ADDR addr, |
| 482 | int len, enum target_hw_bp_type type) |
| 483 | { |
| 484 | int i; |
| 485 | |
| 486 | puts_unfiltered (func); |
| 487 | if (addr || len) |
| 488 | printf_unfiltered (" (addr=%s, len=%d, type=%s)", |
| 489 | paddress (target_gdbarch (), addr), len, |
| 490 | type == hw_write ? "data-write" |
| 491 | : (type == hw_read ? "data-read" |
| 492 | : (type == hw_access ? "data-read/write" |
| 493 | : (type == hw_execute ? "instruction-execute" |
| 494 | : "??unknown??")))); |
| 495 | puts_unfiltered (":\n"); |
| 496 | |
| 497 | for (i = 0; i < MAX_DEBUG_REGISTER; i++) |
| 498 | printf_unfiltered ("\tDR%d: lo=%s, hi=%s\n", i, |
| 499 | paddress (target_gdbarch (), |
| 500 | mips_linux_watch_get_watchlo (&watch_mirror, |
| 501 | i)), |
| 502 | paddress (target_gdbarch (), |
| 503 | mips_linux_watch_get_watchhi (&watch_mirror, |
| 504 | i))); |
| 505 | } |
| 506 | |
| 507 | /* Target to_can_use_hw_breakpoint implementation. Return 1 if we can |
| 508 | handle the specified watch type. */ |
| 509 | |
| 510 | static int |
| 511 | mips_linux_can_use_hw_breakpoint (struct target_ops *self, |
| 512 | enum bptype type, |
| 513 | int cnt, int ot) |
| 514 | { |
| 515 | int i; |
| 516 | uint32_t wanted_mask, irw_mask; |
| 517 | |
| 518 | if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid), |
| 519 | &watch_readback, |
| 520 | &watch_readback_valid, 0)) |
| 521 | return 0; |
| 522 | |
| 523 | switch (type) |
| 524 | { |
| 525 | case bp_hardware_watchpoint: |
| 526 | wanted_mask = W_MASK; |
| 527 | break; |
| 528 | case bp_read_watchpoint: |
| 529 | wanted_mask = R_MASK; |
| 530 | break; |
| 531 | case bp_access_watchpoint: |
| 532 | wanted_mask = R_MASK | W_MASK; |
| 533 | break; |
| 534 | default: |
| 535 | return 0; |
| 536 | } |
| 537 | |
| 538 | for (i = 0; |
| 539 | i < mips_linux_watch_get_num_valid (&watch_readback) && cnt; |
| 540 | i++) |
| 541 | { |
| 542 | irw_mask = mips_linux_watch_get_irw_mask (&watch_readback, i); |
| 543 | if ((irw_mask & wanted_mask) == wanted_mask) |
| 544 | cnt--; |
| 545 | } |
| 546 | return (cnt == 0) ? 1 : 0; |
| 547 | } |
| 548 | |
| 549 | /* Target to_stopped_by_watchpoint implementation. Return 1 if |
| 550 | stopped by watchpoint. The watchhi R and W bits indicate the watch |
| 551 | register triggered. */ |
| 552 | |
| 553 | static int |
| 554 | mips_linux_stopped_by_watchpoint (struct target_ops *ops) |
| 555 | { |
| 556 | int n; |
| 557 | int num_valid; |
| 558 | |
| 559 | if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid), |
| 560 | &watch_readback, |
| 561 | &watch_readback_valid, 1)) |
| 562 | return 0; |
| 563 | |
| 564 | num_valid = mips_linux_watch_get_num_valid (&watch_readback); |
| 565 | |
| 566 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) |
| 567 | if (mips_linux_watch_get_watchhi (&watch_readback, n) & (R_MASK | W_MASK)) |
| 568 | return 1; |
| 569 | |
| 570 | return 0; |
| 571 | } |
| 572 | |
| 573 | /* Target to_stopped_data_address implementation. Set the address |
| 574 | where the watch triggered (if known). Return 1 if the address was |
| 575 | known. */ |
| 576 | |
| 577 | static int |
| 578 | mips_linux_stopped_data_address (struct target_ops *t, CORE_ADDR *paddr) |
| 579 | { |
| 580 | /* On mips we don't know the low order 3 bits of the data address, |
| 581 | so we must return false. */ |
| 582 | return 0; |
| 583 | } |
| 584 | |
| 585 | /* Target to_region_ok_for_hw_watchpoint implementation. Return 1 if |
| 586 | the specified region can be covered by the watch registers. */ |
| 587 | |
| 588 | static int |
| 589 | mips_linux_region_ok_for_hw_watchpoint (struct target_ops *self, |
| 590 | CORE_ADDR addr, int len) |
| 591 | { |
| 592 | struct pt_watch_regs dummy_regs; |
| 593 | int i; |
| 594 | |
| 595 | if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid), |
| 596 | &watch_readback, |
| 597 | &watch_readback_valid, 0)) |
| 598 | return 0; |
| 599 | |
| 600 | dummy_regs = watch_readback; |
| 601 | /* Clear them out. */ |
| 602 | for (i = 0; i < mips_linux_watch_get_num_valid (&dummy_regs); i++) |
| 603 | mips_linux_watch_set_watchlo (&dummy_regs, i, 0); |
| 604 | return mips_linux_watch_try_one_watch (&dummy_regs, addr, len, 0); |
| 605 | } |
| 606 | |
| 607 | /* Write the mirrored watch register values for each thread. */ |
| 608 | |
| 609 | static int |
| 610 | write_watchpoint_regs (void) |
| 611 | { |
| 612 | struct lwp_info *lp; |
| 613 | int tid; |
| 614 | |
| 615 | ALL_LWPS (lp) |
| 616 | { |
| 617 | tid = ptid_get_lwp (lp->ptid); |
| 618 | if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1) |
| 619 | perror_with_name (_("Couldn't write debug register")); |
| 620 | } |
| 621 | return 0; |
| 622 | } |
| 623 | |
| 624 | /* linux_nat new_thread implementation. Write the mirrored watch |
| 625 | register values for the new thread. */ |
| 626 | |
| 627 | static void |
| 628 | mips_linux_new_thread (struct lwp_info *lp) |
| 629 | { |
| 630 | int tid; |
| 631 | |
| 632 | if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid), |
| 633 | &watch_readback, |
| 634 | &watch_readback_valid, 0)) |
| 635 | return; |
| 636 | |
| 637 | tid = ptid_get_lwp (lp->ptid); |
| 638 | if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1) |
| 639 | perror_with_name (_("Couldn't write debug register")); |
| 640 | } |
| 641 | |
| 642 | /* Target to_insert_watchpoint implementation. Try to insert a new |
| 643 | watch. Return zero on success. */ |
| 644 | |
| 645 | static int |
| 646 | mips_linux_insert_watchpoint (struct target_ops *self, |
| 647 | CORE_ADDR addr, int len, |
| 648 | enum target_hw_bp_type type, |
| 649 | struct expression *cond) |
| 650 | { |
| 651 | struct pt_watch_regs regs; |
| 652 | struct mips_watchpoint *new_watch; |
| 653 | struct mips_watchpoint **pw; |
| 654 | |
| 655 | int i; |
| 656 | int retval; |
| 657 | |
| 658 | if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid), |
| 659 | &watch_readback, |
| 660 | &watch_readback_valid, 0)) |
| 661 | return -1; |
| 662 | |
| 663 | if (len <= 0) |
| 664 | return -1; |
| 665 | |
| 666 | regs = watch_readback; |
| 667 | /* Add the current watches. */ |
| 668 | mips_linux_watch_populate_regs (current_watches, ®s); |
| 669 | |
| 670 | /* Now try to add the new watch. */ |
| 671 | if (!mips_linux_watch_try_one_watch (®s, addr, len, |
| 672 | mips_linux_watch_type_to_irw (type))) |
| 673 | return -1; |
| 674 | |
| 675 | /* It fit. Stick it on the end of the list. */ |
| 676 | new_watch = XNEW (struct mips_watchpoint); |
| 677 | new_watch->addr = addr; |
| 678 | new_watch->len = len; |
| 679 | new_watch->type = type; |
| 680 | new_watch->next = NULL; |
| 681 | |
| 682 | pw = ¤t_watches; |
| 683 | while (*pw != NULL) |
| 684 | pw = &(*pw)->next; |
| 685 | *pw = new_watch; |
| 686 | |
| 687 | watch_mirror = regs; |
| 688 | retval = write_watchpoint_regs (); |
| 689 | |
| 690 | if (show_debug_regs) |
| 691 | mips_show_dr ("insert_watchpoint", addr, len, type); |
| 692 | |
| 693 | return retval; |
| 694 | } |
| 695 | |
| 696 | /* Target to_remove_watchpoint implementation. Try to remove a watch. |
| 697 | Return zero on success. */ |
| 698 | |
| 699 | static int |
| 700 | mips_linux_remove_watchpoint (struct target_ops *self, |
| 701 | CORE_ADDR addr, int len, |
| 702 | enum target_hw_bp_type type, |
| 703 | struct expression *cond) |
| 704 | { |
| 705 | int retval; |
| 706 | int deleted_one; |
| 707 | |
| 708 | struct mips_watchpoint **pw; |
| 709 | struct mips_watchpoint *w; |
| 710 | |
| 711 | /* Search for a known watch that matches. Then unlink and free |
| 712 | it. */ |
| 713 | deleted_one = 0; |
| 714 | pw = ¤t_watches; |
| 715 | while ((w = *pw)) |
| 716 | { |
| 717 | if (w->addr == addr && w->len == len && w->type == type) |
| 718 | { |
| 719 | *pw = w->next; |
| 720 | xfree (w); |
| 721 | deleted_one = 1; |
| 722 | break; |
| 723 | } |
| 724 | pw = &(w->next); |
| 725 | } |
| 726 | |
| 727 | if (!deleted_one) |
| 728 | return -1; /* We don't know about it, fail doing nothing. */ |
| 729 | |
| 730 | /* At this point watch_readback is known to be valid because we |
| 731 | could not have added the watch without reading it. */ |
| 732 | gdb_assert (watch_readback_valid == 1); |
| 733 | |
| 734 | watch_mirror = watch_readback; |
| 735 | mips_linux_watch_populate_regs (current_watches, &watch_mirror); |
| 736 | |
| 737 | retval = write_watchpoint_regs (); |
| 738 | |
| 739 | if (show_debug_regs) |
| 740 | mips_show_dr ("remove_watchpoint", addr, len, type); |
| 741 | |
| 742 | return retval; |
| 743 | } |
| 744 | |
| 745 | /* Target to_close implementation. Free any watches and call the |
| 746 | super implementation. */ |
| 747 | |
| 748 | static void |
| 749 | mips_linux_close (struct target_ops *self) |
| 750 | { |
| 751 | struct mips_watchpoint *w; |
| 752 | struct mips_watchpoint *nw; |
| 753 | |
| 754 | /* Clean out the current_watches list. */ |
| 755 | w = current_watches; |
| 756 | while (w) |
| 757 | { |
| 758 | nw = w->next; |
| 759 | xfree (w); |
| 760 | w = nw; |
| 761 | } |
| 762 | current_watches = NULL; |
| 763 | |
| 764 | if (super_close) |
| 765 | super_close (self); |
| 766 | } |
| 767 | |
| 768 | void _initialize_mips_linux_nat (void); |
| 769 | |
| 770 | void |
| 771 | _initialize_mips_linux_nat (void) |
| 772 | { |
| 773 | struct target_ops *t; |
| 774 | |
| 775 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, |
| 776 | &show_debug_regs, _("\ |
| 777 | Set whether to show variables that mirror the mips debug registers."), _("\ |
| 778 | Show whether to show variables that mirror the mips debug registers."), _("\ |
| 779 | Use \"on\" to enable, \"off\" to disable.\n\ |
| 780 | If enabled, the debug registers values are shown when GDB inserts\n\ |
| 781 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ |
| 782 | triggers a breakpoint or watchpoint."), |
| 783 | NULL, |
| 784 | NULL, |
| 785 | &maintenance_set_cmdlist, |
| 786 | &maintenance_show_cmdlist); |
| 787 | |
| 788 | t = linux_trad_target (mips_linux_register_u_offset); |
| 789 | |
| 790 | super_close = t->to_close; |
| 791 | t->to_close = mips_linux_close; |
| 792 | |
| 793 | super_fetch_registers = t->to_fetch_registers; |
| 794 | super_store_registers = t->to_store_registers; |
| 795 | |
| 796 | t->to_fetch_registers = mips64_linux_fetch_registers; |
| 797 | t->to_store_registers = mips64_linux_store_registers; |
| 798 | |
| 799 | t->to_can_use_hw_breakpoint = mips_linux_can_use_hw_breakpoint; |
| 800 | t->to_remove_watchpoint = mips_linux_remove_watchpoint; |
| 801 | t->to_insert_watchpoint = mips_linux_insert_watchpoint; |
| 802 | t->to_stopped_by_watchpoint = mips_linux_stopped_by_watchpoint; |
| 803 | t->to_stopped_data_address = mips_linux_stopped_data_address; |
| 804 | t->to_region_ok_for_hw_watchpoint = mips_linux_region_ok_for_hw_watchpoint; |
| 805 | |
| 806 | t->to_read_description = mips_linux_read_description; |
| 807 | |
| 808 | linux_nat_add_target (t); |
| 809 | linux_nat_set_new_thread (t, mips_linux_new_thread); |
| 810 | |
| 811 | /* Initialize the standard target descriptions. */ |
| 812 | initialize_tdesc_mips_linux (); |
| 813 | initialize_tdesc_mips_dsp_linux (); |
| 814 | initialize_tdesc_mips64_linux (); |
| 815 | initialize_tdesc_mips64_dsp_linux (); |
| 816 | } |