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2012-04-20 Sergio Durigan Junior <sergiodj@redhat.com>
[deliverable/binutils-gdb.git] / gdb / mt-tdep.c
... / ...
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1/* Target-dependent code for Morpho mt processor, for GDB.
2
3 Copyright (C) 2005, 2007-2012 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20/* Contributed by Michael Snyder, msnyder@redhat.com. */
21
22#include "defs.h"
23#include "frame.h"
24#include "frame-unwind.h"
25#include "frame-base.h"
26#include "symtab.h"
27#include "dis-asm.h"
28#include "arch-utils.h"
29#include "gdbtypes.h"
30#include "gdb_string.h"
31#include "regcache.h"
32#include "reggroups.h"
33#include "gdbcore.h"
34#include "trad-frame.h"
35#include "inferior.h"
36#include "dwarf2-frame.h"
37#include "infcall.h"
38#include "gdb_assert.h"
39#include "language.h"
40#include "valprint.h"
41
42enum mt_arch_constants
43{
44 MT_MAX_STRUCT_SIZE = 16
45};
46
47enum mt_gdb_regnums
48{
49 MT_R0_REGNUM, /* 32 bit regs. */
50 MT_R1_REGNUM,
51 MT_1ST_ARGREG = MT_R1_REGNUM,
52 MT_R2_REGNUM,
53 MT_R3_REGNUM,
54 MT_R4_REGNUM,
55 MT_LAST_ARGREG = MT_R4_REGNUM,
56 MT_R5_REGNUM,
57 MT_R6_REGNUM,
58 MT_R7_REGNUM,
59 MT_R8_REGNUM,
60 MT_R9_REGNUM,
61 MT_R10_REGNUM,
62 MT_R11_REGNUM,
63 MT_R12_REGNUM,
64 MT_FP_REGNUM = MT_R12_REGNUM,
65 MT_R13_REGNUM,
66 MT_SP_REGNUM = MT_R13_REGNUM,
67 MT_R14_REGNUM,
68 MT_RA_REGNUM = MT_R14_REGNUM,
69 MT_R15_REGNUM,
70 MT_IRA_REGNUM = MT_R15_REGNUM,
71 MT_PC_REGNUM,
72
73 /* Interrupt Enable pseudo-register, exported by SID. */
74 MT_INT_ENABLE_REGNUM,
75 /* End of CPU regs. */
76
77 MT_NUM_CPU_REGS,
78
79 /* Co-processor registers. */
80 MT_COPRO_REGNUM = MT_NUM_CPU_REGS, /* 16 bit regs. */
81 MT_CPR0_REGNUM,
82 MT_CPR1_REGNUM,
83 MT_CPR2_REGNUM,
84 MT_CPR3_REGNUM,
85 MT_CPR4_REGNUM,
86 MT_CPR5_REGNUM,
87 MT_CPR6_REGNUM,
88 MT_CPR7_REGNUM,
89 MT_CPR8_REGNUM,
90 MT_CPR9_REGNUM,
91 MT_CPR10_REGNUM,
92 MT_CPR11_REGNUM,
93 MT_CPR12_REGNUM,
94 MT_CPR13_REGNUM,
95 MT_CPR14_REGNUM,
96 MT_CPR15_REGNUM,
97 MT_BYPA_REGNUM, /* 32 bit regs. */
98 MT_BYPB_REGNUM,
99 MT_BYPC_REGNUM,
100 MT_FLAG_REGNUM,
101 MT_CONTEXT_REGNUM, /* 38 bits (treat as array of
102 six bytes). */
103 MT_MAC_REGNUM, /* 32 bits. */
104 MT_Z1_REGNUM, /* 16 bits. */
105 MT_Z2_REGNUM, /* 16 bits. */
106 MT_ICHANNEL_REGNUM, /* 32 bits. */
107 MT_ISCRAMB_REGNUM, /* 32 bits. */
108 MT_QSCRAMB_REGNUM, /* 32 bits. */
109 MT_OUT_REGNUM, /* 16 bits. */
110 MT_EXMAC_REGNUM, /* 32 bits (8 used). */
111 MT_QCHANNEL_REGNUM, /* 32 bits. */
112 MT_ZI2_REGNUM, /* 16 bits. */
113 MT_ZQ2_REGNUM, /* 16 bits. */
114 MT_CHANNEL2_REGNUM, /* 32 bits. */
115 MT_ISCRAMB2_REGNUM, /* 32 bits. */
116 MT_QSCRAMB2_REGNUM, /* 32 bits. */
117 MT_QCHANNEL2_REGNUM, /* 32 bits. */
118
119 /* Number of real registers. */
120 MT_NUM_REGS,
121
122 /* Pseudo-registers. */
123 MT_COPRO_PSEUDOREG_REGNUM = MT_NUM_REGS,
124 MT_MAC_PSEUDOREG_REGNUM,
125 MT_COPRO_PSEUDOREG_ARRAY,
126
127 MT_COPRO_PSEUDOREG_DIM_1 = 2,
128 MT_COPRO_PSEUDOREG_DIM_2 = 8,
129 /* The number of pseudo-registers for each coprocessor. These
130 include the real coprocessor registers, the pseudo-registe for
131 the coprocessor number, and the pseudo-register for the MAC. */
132 MT_COPRO_PSEUDOREG_REGS = MT_NUM_REGS - MT_NUM_CPU_REGS + 2,
133 /* The register number of the MAC, relative to a given coprocessor. */
134 MT_COPRO_PSEUDOREG_MAC_REGNUM = MT_COPRO_PSEUDOREG_REGS - 1,
135
136 /* Two pseudo-regs ('coprocessor' and 'mac'). */
137 MT_NUM_PSEUDO_REGS = 2 + (MT_COPRO_PSEUDOREG_REGS
138 * MT_COPRO_PSEUDOREG_DIM_1
139 * MT_COPRO_PSEUDOREG_DIM_2)
140};
141
142/* The tdep structure. */
143struct gdbarch_tdep
144{
145 /* ISA-specific types. */
146 struct type *copro_type;
147};
148
149
150/* Return name of register number specified by REGNUM. */
151
152static const char *
153mt_register_name (struct gdbarch *gdbarch, int regnum)
154{
155 static const char *const register_names[] = {
156 /* CPU regs. */
157 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
158 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
159 "pc", "IE",
160 /* Co-processor regs. */
161 "", /* copro register. */
162 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
163 "cr8", "cr9", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15",
164 "bypa", "bypb", "bypc", "flag", "context", "" /* mac. */ , "z1", "z2",
165 "Ichannel", "Iscramb", "Qscramb", "out", "" /* ex-mac. */ , "Qchannel",
166 "zi2", "zq2", "Ichannel2", "Iscramb2", "Qscramb2", "Qchannel2",
167 /* Pseudo-registers. */
168 "coprocessor", "MAC"
169 };
170 static const char *array_names[MT_COPRO_PSEUDOREG_REGS
171 * MT_COPRO_PSEUDOREG_DIM_1
172 * MT_COPRO_PSEUDOREG_DIM_2];
173
174 if (regnum < 0)
175 return "";
176 if (regnum < ARRAY_SIZE (register_names))
177 return register_names[regnum];
178 if (array_names[regnum - MT_COPRO_PSEUDOREG_ARRAY])
179 return array_names[regnum - MT_COPRO_PSEUDOREG_ARRAY];
180
181 {
182 char *name;
183 const char *stub;
184 unsigned dim_1;
185 unsigned dim_2;
186 unsigned index;
187
188 regnum -= MT_COPRO_PSEUDOREG_ARRAY;
189 index = regnum % MT_COPRO_PSEUDOREG_REGS;
190 dim_2 = (regnum / MT_COPRO_PSEUDOREG_REGS) % MT_COPRO_PSEUDOREG_DIM_2;
191 dim_1 = ((regnum / MT_COPRO_PSEUDOREG_REGS / MT_COPRO_PSEUDOREG_DIM_2)
192 % MT_COPRO_PSEUDOREG_DIM_1);
193
194 if (index == MT_COPRO_PSEUDOREG_MAC_REGNUM)
195 stub = register_names[MT_MAC_PSEUDOREG_REGNUM];
196 else if (index >= MT_NUM_REGS - MT_CPR0_REGNUM)
197 stub = "";
198 else
199 stub = register_names[index + MT_CPR0_REGNUM];
200 if (!*stub)
201 {
202 array_names[regnum] = stub;
203 return stub;
204 }
205 name = xmalloc (30);
206 sprintf (name, "copro_%d_%d_%s", dim_1, dim_2, stub);
207 array_names[regnum] = name;
208 return name;
209 }
210}
211
212/* Return the type of a coprocessor register. */
213
214static struct type *
215mt_copro_register_type (struct gdbarch *arch, int regnum)
216{
217 switch (regnum)
218 {
219 case MT_INT_ENABLE_REGNUM:
220 case MT_ICHANNEL_REGNUM:
221 case MT_QCHANNEL_REGNUM:
222 case MT_ISCRAMB_REGNUM:
223 case MT_QSCRAMB_REGNUM:
224 return builtin_type (arch)->builtin_int32;
225 case MT_BYPA_REGNUM:
226 case MT_BYPB_REGNUM:
227 case MT_BYPC_REGNUM:
228 case MT_Z1_REGNUM:
229 case MT_Z2_REGNUM:
230 case MT_OUT_REGNUM:
231 case MT_ZI2_REGNUM:
232 case MT_ZQ2_REGNUM:
233 return builtin_type (arch)->builtin_int16;
234 case MT_EXMAC_REGNUM:
235 case MT_MAC_REGNUM:
236 return builtin_type (arch)->builtin_uint32;
237 case MT_CONTEXT_REGNUM:
238 return builtin_type (arch)->builtin_long_long;
239 case MT_FLAG_REGNUM:
240 return builtin_type (arch)->builtin_unsigned_char;
241 default:
242 if (regnum >= MT_CPR0_REGNUM && regnum <= MT_CPR15_REGNUM)
243 return builtin_type (arch)->builtin_int16;
244 else if (regnum == MT_CPR0_REGNUM + MT_COPRO_PSEUDOREG_MAC_REGNUM)
245 {
246 if (gdbarch_bfd_arch_info (arch)->mach == bfd_mach_mrisc2
247 || gdbarch_bfd_arch_info (arch)->mach == bfd_mach_ms2)
248 return builtin_type (arch)->builtin_uint64;
249 else
250 return builtin_type (arch)->builtin_uint32;
251 }
252 else
253 return builtin_type (arch)->builtin_uint32;
254 }
255}
256
257/* Given ARCH and a register number specified by REGNUM, return the
258 type of that register. */
259
260static struct type *
261mt_register_type (struct gdbarch *arch, int regnum)
262{
263 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
264
265 if (regnum >= 0 && regnum < MT_NUM_REGS + MT_NUM_PSEUDO_REGS)
266 {
267 switch (regnum)
268 {
269 case MT_PC_REGNUM:
270 case MT_RA_REGNUM:
271 case MT_IRA_REGNUM:
272 return builtin_type (arch)->builtin_func_ptr;
273 case MT_SP_REGNUM:
274 case MT_FP_REGNUM:
275 return builtin_type (arch)->builtin_data_ptr;
276 case MT_COPRO_REGNUM:
277 case MT_COPRO_PSEUDOREG_REGNUM:
278 if (tdep->copro_type == NULL)
279 {
280 struct type *elt = builtin_type (arch)->builtin_int16;
281 tdep->copro_type = lookup_array_range_type (elt, 0, 1);
282 }
283 return tdep->copro_type;
284 case MT_MAC_PSEUDOREG_REGNUM:
285 return mt_copro_register_type (arch,
286 MT_CPR0_REGNUM
287 + MT_COPRO_PSEUDOREG_MAC_REGNUM);
288 default:
289 if (regnum >= MT_R0_REGNUM && regnum <= MT_R15_REGNUM)
290 return builtin_type (arch)->builtin_int32;
291 else if (regnum < MT_COPRO_PSEUDOREG_ARRAY)
292 return mt_copro_register_type (arch, regnum);
293 else
294 {
295 regnum -= MT_COPRO_PSEUDOREG_ARRAY;
296 regnum %= MT_COPRO_PSEUDOREG_REGS;
297 regnum += MT_CPR0_REGNUM;
298 return mt_copro_register_type (arch, regnum);
299 }
300 }
301 }
302 internal_error (__FILE__, __LINE__,
303 _("mt_register_type: illegal register number %d"), regnum);
304}
305
306/* Return true if register REGNUM is a member of the register group
307 specified by GROUP. */
308
309static int
310mt_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
311 struct reggroup *group)
312{
313 /* Groups of registers that can be displayed via "info reg". */
314 if (group == all_reggroup)
315 return (regnum >= 0
316 && regnum < MT_NUM_REGS + MT_NUM_PSEUDO_REGS
317 && mt_register_name (gdbarch, regnum)[0] != '\0');
318
319 if (group == general_reggroup)
320 return (regnum >= MT_R0_REGNUM && regnum <= MT_R15_REGNUM);
321
322 if (group == float_reggroup)
323 return 0; /* No float regs. */
324
325 if (group == vector_reggroup)
326 return 0; /* No vector regs. */
327
328 /* For any that are not handled above. */
329 return default_register_reggroup_p (gdbarch, regnum, group);
330}
331
332/* Return the return value convention used for a given type TYPE.
333 Optionally, fetch or set the return value via READBUF or
334 WRITEBUF respectively using REGCACHE for the register
335 values. */
336
337static enum return_value_convention
338mt_return_value (struct gdbarch *gdbarch, struct type *func_type,
339 struct type *type, struct regcache *regcache,
340 gdb_byte *readbuf, const gdb_byte *writebuf)
341{
342 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
343
344 if (TYPE_LENGTH (type) > 4)
345 {
346 /* Return values > 4 bytes are returned in memory,
347 pointed to by R11. */
348 if (readbuf)
349 {
350 ULONGEST addr;
351
352 regcache_cooked_read_unsigned (regcache, MT_R11_REGNUM, &addr);
353 read_memory (addr, readbuf, TYPE_LENGTH (type));
354 }
355
356 if (writebuf)
357 {
358 ULONGEST addr;
359
360 regcache_cooked_read_unsigned (regcache, MT_R11_REGNUM, &addr);
361 write_memory (addr, writebuf, TYPE_LENGTH (type));
362 }
363
364 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
365 }
366 else
367 {
368 if (readbuf)
369 {
370 ULONGEST temp;
371
372 /* Return values of <= 4 bytes are returned in R11. */
373 regcache_cooked_read_unsigned (regcache, MT_R11_REGNUM, &temp);
374 store_unsigned_integer (readbuf, TYPE_LENGTH (type),
375 byte_order, temp);
376 }
377
378 if (writebuf)
379 {
380 if (TYPE_LENGTH (type) < 4)
381 {
382 gdb_byte buf[4];
383 /* Add leading zeros to the value. */
384 memset (buf, 0, sizeof (buf));
385 memcpy (buf + sizeof (buf) - TYPE_LENGTH (type),
386 writebuf, TYPE_LENGTH (type));
387 regcache_cooked_write (regcache, MT_R11_REGNUM, buf);
388 }
389 else /* (TYPE_LENGTH (type) == 4 */
390 regcache_cooked_write (regcache, MT_R11_REGNUM, writebuf);
391 }
392
393 return RETURN_VALUE_REGISTER_CONVENTION;
394 }
395}
396
397/* If the input address, PC, is in a function prologue, return the
398 address of the end of the prologue, otherwise return the input
399 address.
400
401 Note: PC is likely to be the function start, since this function
402 is mainly used for advancing a breakpoint to the first line, or
403 stepping to the first line when we have stepped into a function
404 call. */
405
406static CORE_ADDR
407mt_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
408{
409 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
410 CORE_ADDR func_addr = 0, func_end = 0;
411 const char *func_name;
412 unsigned long instr;
413
414 if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end))
415 {
416 struct symtab_and_line sal;
417 struct symbol *sym;
418
419 /* Found a function. */
420 sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL);
421 if (sym && SYMBOL_LANGUAGE (sym) != language_asm)
422 {
423 /* Don't use this trick for assembly source files. */
424 sal = find_pc_line (func_addr, 0);
425
426 if (sal.end && sal.end < func_end)
427 {
428 /* Found a line number, use it as end of prologue. */
429 return sal.end;
430 }
431 }
432 }
433
434 /* No function symbol, or no line symbol. Use prologue scanning method. */
435 for (;; pc += 4)
436 {
437 instr = read_memory_unsigned_integer (pc, 4, byte_order);
438 if (instr == 0x12000000) /* nop */
439 continue;
440 if (instr == 0x12ddc000) /* copy sp into fp */
441 continue;
442 instr >>= 16;
443 if (instr == 0x05dd) /* subi sp, sp, imm */
444 continue;
445 if (instr >= 0x43c0 && instr <= 0x43df) /* push */
446 continue;
447 /* Not an obvious prologue instruction. */
448 break;
449 }
450
451 return pc;
452}
453
454/* The breakpoint instruction must be the same size as the smallest
455 instruction in the instruction set.
456
457 The BP for ms1 is defined as 0x68000000 (BREAK).
458 The BP for ms2 is defined as 0x69000000 (illegal). */
459
460static const gdb_byte *
461mt_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr,
462 int *bp_size)
463{
464 static gdb_byte ms1_breakpoint[] = { 0x68, 0, 0, 0 };
465 static gdb_byte ms2_breakpoint[] = { 0x69, 0, 0, 0 };
466
467 *bp_size = 4;
468 if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_ms2)
469 return ms2_breakpoint;
470
471 return ms1_breakpoint;
472}
473
474/* Select the correct coprocessor register bank. Return the pseudo
475 regnum we really want to read. */
476
477static int
478mt_select_coprocessor (struct gdbarch *gdbarch,
479 struct regcache *regcache, int regno)
480{
481 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
482 unsigned index, base;
483 gdb_byte copro[4];
484
485 /* Get the copro pseudo regnum. */
486 regcache_raw_read (regcache, MT_COPRO_REGNUM, copro);
487 base = ((extract_signed_integer (&copro[0], 2, byte_order)
488 * MT_COPRO_PSEUDOREG_DIM_2)
489 + extract_signed_integer (&copro[2], 2, byte_order));
490
491 regno -= MT_COPRO_PSEUDOREG_ARRAY;
492 index = regno % MT_COPRO_PSEUDOREG_REGS;
493 regno /= MT_COPRO_PSEUDOREG_REGS;
494 if (base != regno)
495 {
496 /* Select the correct coprocessor register bank. Invalidate the
497 coprocessor register cache. */
498 unsigned ix;
499
500 store_signed_integer (&copro[0], 2, byte_order,
501 regno / MT_COPRO_PSEUDOREG_DIM_2);
502 store_signed_integer (&copro[2], 2, byte_order,
503 regno % MT_COPRO_PSEUDOREG_DIM_2);
504 regcache_raw_write (regcache, MT_COPRO_REGNUM, copro);
505
506 /* We must flush the cache, as it is now invalid. */
507 for (ix = MT_NUM_CPU_REGS; ix != MT_NUM_REGS; ix++)
508 regcache_invalidate (regcache, ix);
509 }
510
511 return index;
512}
513
514/* Fetch the pseudo registers:
515
516 There are two regular pseudo-registers:
517 1) The 'coprocessor' pseudo-register (which mirrors the
518 "real" coprocessor register sent by the target), and
519 2) The 'MAC' pseudo-register (which represents the union
520 of the original 32 bit target MAC register and the new
521 8-bit extended-MAC register).
522
523 Additionally there is an array of coprocessor registers which track
524 the coprocessor registers for each coprocessor. */
525
526static enum register_status
527mt_pseudo_register_read (struct gdbarch *gdbarch,
528 struct regcache *regcache, int regno, gdb_byte *buf)
529{
530 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
531
532 switch (regno)
533 {
534 case MT_COPRO_REGNUM:
535 case MT_COPRO_PSEUDOREG_REGNUM:
536 return regcache_raw_read (regcache, MT_COPRO_REGNUM, buf);
537 case MT_MAC_REGNUM:
538 case MT_MAC_PSEUDOREG_REGNUM:
539 if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_mrisc2
540 || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_ms2)
541 {
542 enum register_status status;
543 ULONGEST oldmac = 0, ext_mac = 0;
544 ULONGEST newmac;
545
546 status = regcache_cooked_read_unsigned (regcache, MT_MAC_REGNUM, &oldmac);
547 if (status != REG_VALID)
548 return status;
549
550 regcache_cooked_read_unsigned (regcache, MT_EXMAC_REGNUM, &ext_mac);
551 if (status != REG_VALID)
552 return status;
553
554 newmac =
555 (oldmac & 0xffffffff) | ((long long) (ext_mac & 0xff) << 32);
556 store_signed_integer (buf, 8, byte_order, newmac);
557
558 return REG_VALID;
559 }
560 else
561 return regcache_raw_read (regcache, MT_MAC_REGNUM, buf);
562 break;
563 default:
564 {
565 unsigned index = mt_select_coprocessor (gdbarch, regcache, regno);
566
567 if (index == MT_COPRO_PSEUDOREG_MAC_REGNUM)
568 return mt_pseudo_register_read (gdbarch, regcache,
569 MT_MAC_PSEUDOREG_REGNUM, buf);
570 else if (index < MT_NUM_REGS - MT_CPR0_REGNUM)
571 return regcache_raw_read (regcache, index + MT_CPR0_REGNUM, buf);
572 else
573 /* ??? */
574 return REG_VALID;
575 }
576 break;
577 }
578}
579
580/* Write the pseudo registers:
581
582 Mt pseudo-registers are stored directly to the target. The
583 'coprocessor' register is special, because when it is modified, all
584 the other coprocessor regs must be flushed from the reg cache. */
585
586static void
587mt_pseudo_register_write (struct gdbarch *gdbarch,
588 struct regcache *regcache,
589 int regno, const gdb_byte *buf)
590{
591 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
592 int i;
593
594 switch (regno)
595 {
596 case MT_COPRO_REGNUM:
597 case MT_COPRO_PSEUDOREG_REGNUM:
598 regcache_raw_write (regcache, MT_COPRO_REGNUM, buf);
599 for (i = MT_NUM_CPU_REGS; i < MT_NUM_REGS; i++)
600 regcache_invalidate (regcache, i);
601 break;
602 case MT_MAC_REGNUM:
603 case MT_MAC_PSEUDOREG_REGNUM:
604 if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_mrisc2
605 || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_ms2)
606 {
607 /* The 8-byte MAC pseudo-register must be broken down into two
608 32-byte registers. */
609 unsigned int oldmac, ext_mac;
610 ULONGEST newmac;
611
612 newmac = extract_unsigned_integer (buf, 8, byte_order);
613 oldmac = newmac & 0xffffffff;
614 ext_mac = (newmac >> 32) & 0xff;
615 regcache_cooked_write_unsigned (regcache, MT_MAC_REGNUM, oldmac);
616 regcache_cooked_write_unsigned (regcache, MT_EXMAC_REGNUM, ext_mac);
617 }
618 else
619 regcache_raw_write (regcache, MT_MAC_REGNUM, buf);
620 break;
621 default:
622 {
623 unsigned index = mt_select_coprocessor (gdbarch, regcache, regno);
624
625 if (index == MT_COPRO_PSEUDOREG_MAC_REGNUM)
626 mt_pseudo_register_write (gdbarch, regcache,
627 MT_MAC_PSEUDOREG_REGNUM, buf);
628 else if (index < MT_NUM_REGS - MT_CPR0_REGNUM)
629 regcache_raw_write (regcache, index + MT_CPR0_REGNUM, buf);
630 }
631 break;
632 }
633}
634
635static CORE_ADDR
636mt_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
637{
638 /* Register size is 4 bytes. */
639 return align_down (sp, 4);
640}
641
642/* Implements the "info registers" command. When ``all'' is non-zero,
643 the coprocessor registers will be printed in addition to the rest
644 of the registers. */
645
646static void
647mt_registers_info (struct gdbarch *gdbarch,
648 struct ui_file *file,
649 struct frame_info *frame, int regnum, int all)
650{
651 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
652
653 if (regnum == -1)
654 {
655 int lim;
656
657 lim = all ? MT_NUM_REGS : MT_NUM_CPU_REGS;
658
659 for (regnum = 0; regnum < lim; regnum++)
660 {
661 /* Don't display the Qchannel register since it will be displayed
662 along with Ichannel. (See below.) */
663 if (regnum == MT_QCHANNEL_REGNUM)
664 continue;
665
666 mt_registers_info (gdbarch, file, frame, regnum, all);
667
668 /* Display the Qchannel register immediately after Ichannel. */
669 if (regnum == MT_ICHANNEL_REGNUM)
670 mt_registers_info (gdbarch, file, frame, MT_QCHANNEL_REGNUM, all);
671 }
672 }
673 else
674 {
675 if (regnum == MT_EXMAC_REGNUM)
676 return;
677 else if (regnum == MT_CONTEXT_REGNUM)
678 {
679 /* Special output handling for 38-bit context register. */
680 unsigned char *buff;
681 unsigned int *bytes, i, regsize;
682
683 regsize = register_size (gdbarch, regnum);
684
685 buff = alloca (regsize);
686 bytes = alloca (regsize * sizeof (*bytes));
687
688 frame_register_read (frame, regnum, buff);
689
690 fputs_filtered (gdbarch_register_name
691 (gdbarch, regnum), file);
692 print_spaces_filtered (15 - strlen (gdbarch_register_name
693 (gdbarch, regnum)),
694 file);
695 fputs_filtered ("0x", file);
696
697 for (i = 0; i < regsize; i++)
698 fprintf_filtered (file, "%02x", (unsigned int)
699 extract_unsigned_integer (buff + i, 1, byte_order));
700 fputs_filtered ("\t", file);
701 print_longest (file, 'd', 0,
702 extract_unsigned_integer (buff, regsize, byte_order));
703 fputs_filtered ("\n", file);
704 }
705 else if (regnum == MT_COPRO_REGNUM
706 || regnum == MT_COPRO_PSEUDOREG_REGNUM)
707 {
708 /* Special output handling for the 'coprocessor' register. */
709 gdb_byte *buf;
710 struct value_print_options opts;
711
712 buf = alloca (register_size (gdbarch, MT_COPRO_REGNUM));
713 frame_register_read (frame, MT_COPRO_REGNUM, buf);
714 /* And print. */
715 regnum = MT_COPRO_PSEUDOREG_REGNUM;
716 fputs_filtered (gdbarch_register_name (gdbarch, regnum),
717 file);
718 print_spaces_filtered (15 - strlen (gdbarch_register_name
719 (gdbarch, regnum)),
720 file);
721 get_raw_print_options (&opts);
722 opts.deref_ref = 1;
723 val_print (register_type (gdbarch, regnum), buf,
724 0, 0, file, 0, NULL,
725 &opts, current_language);
726 fputs_filtered ("\n", file);
727 }
728 else if (regnum == MT_MAC_REGNUM || regnum == MT_MAC_PSEUDOREG_REGNUM)
729 {
730 ULONGEST oldmac, ext_mac, newmac;
731 gdb_byte buf[3 * sizeof (LONGEST)];
732
733 /* Get the two "real" mac registers. */
734 frame_register_read (frame, MT_MAC_REGNUM, buf);
735 oldmac = extract_unsigned_integer
736 (buf, register_size (gdbarch, MT_MAC_REGNUM), byte_order);
737 if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_mrisc2
738 || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_ms2)
739 {
740 frame_register_read (frame, MT_EXMAC_REGNUM, buf);
741 ext_mac = extract_unsigned_integer
742 (buf, register_size (gdbarch, MT_EXMAC_REGNUM), byte_order);
743 }
744 else
745 ext_mac = 0;
746
747 /* Add them together. */
748 newmac = (oldmac & 0xffffffff) + ((ext_mac & 0xff) << 32);
749
750 /* And print. */
751 regnum = MT_MAC_PSEUDOREG_REGNUM;
752 fputs_filtered (gdbarch_register_name (gdbarch, regnum),
753 file);
754 print_spaces_filtered (15 - strlen (gdbarch_register_name
755 (gdbarch, regnum)),
756 file);
757 fputs_filtered ("0x", file);
758 print_longest (file, 'x', 0, newmac);
759 fputs_filtered ("\t", file);
760 print_longest (file, 'u', 0, newmac);
761 fputs_filtered ("\n", file);
762 }
763 else
764 default_print_registers_info (gdbarch, file, frame, regnum, all);
765 }
766}
767
768/* Set up the callee's arguments for an inferior function call. The
769 arguments are pushed on the stack or are placed in registers as
770 appropriate. It also sets up the return address (which points to
771 the call dummy breakpoint).
772
773 Returns the updated (and aligned) stack pointer. */
774
775static CORE_ADDR
776mt_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
777 struct regcache *regcache, CORE_ADDR bp_addr,
778 int nargs, struct value **args, CORE_ADDR sp,
779 int struct_return, CORE_ADDR struct_addr)
780{
781#define wordsize 4
782 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
783 gdb_byte buf[MT_MAX_STRUCT_SIZE];
784 int argreg = MT_1ST_ARGREG;
785 int split_param_len = 0;
786 int stack_dest = sp;
787 int slacklen;
788 int typelen;
789 int i, j;
790
791 /* First handle however many args we can fit into MT_1ST_ARGREG thru
792 MT_LAST_ARGREG. */
793 for (i = 0; i < nargs && argreg <= MT_LAST_ARGREG; i++)
794 {
795 const gdb_byte *val;
796 typelen = TYPE_LENGTH (value_type (args[i]));
797 switch (typelen)
798 {
799 case 1:
800 case 2:
801 case 3:
802 case 4:
803 regcache_cooked_write_unsigned (regcache, argreg++,
804 extract_unsigned_integer
805 (value_contents (args[i]),
806 wordsize, byte_order));
807 break;
808 case 8:
809 case 12:
810 case 16:
811 val = value_contents (args[i]);
812 while (typelen > 0)
813 {
814 if (argreg <= MT_LAST_ARGREG)
815 {
816 /* This word of the argument is passed in a register. */
817 regcache_cooked_write_unsigned (regcache, argreg++,
818 extract_unsigned_integer
819 (val, wordsize, byte_order));
820 typelen -= wordsize;
821 val += wordsize;
822 }
823 else
824 {
825 /* Remainder of this arg must be passed on the stack
826 (deferred to do later). */
827 split_param_len = typelen;
828 memcpy (buf, val, typelen);
829 break; /* No more args can be handled in regs. */
830 }
831 }
832 break;
833 default:
834 /* By reverse engineering of gcc output, args bigger than
835 16 bytes go on the stack, and their address is passed
836 in the argreg. */
837 stack_dest -= typelen;
838 write_memory (stack_dest, value_contents (args[i]), typelen);
839 regcache_cooked_write_unsigned (regcache, argreg++, stack_dest);
840 break;
841 }
842 }
843
844 /* Next, the rest of the arguments go onto the stack, in reverse order. */
845 for (j = nargs - 1; j >= i; j--)
846 {
847 gdb_byte *val;
848
849 /* Right-justify the value in an aligned-length buffer. */
850 typelen = TYPE_LENGTH (value_type (args[j]));
851 slacklen = (wordsize - (typelen % wordsize)) % wordsize;
852 val = alloca (typelen + slacklen);
853 memcpy (val, value_contents (args[j]), typelen);
854 memset (val + typelen, 0, slacklen);
855 /* Now write this data to the stack. */
856 stack_dest -= typelen + slacklen;
857 write_memory (stack_dest, val, typelen + slacklen);
858 }
859
860 /* Finally, if a param needs to be split between registers and stack,
861 write the second half to the stack now. */
862 if (split_param_len != 0)
863 {
864 stack_dest -= split_param_len;
865 write_memory (stack_dest, buf, split_param_len);
866 }
867
868 /* Set up return address (provided to us as bp_addr). */
869 regcache_cooked_write_unsigned (regcache, MT_RA_REGNUM, bp_addr);
870
871 /* Store struct return address, if given. */
872 if (struct_return && struct_addr != 0)
873 regcache_cooked_write_unsigned (regcache, MT_R11_REGNUM, struct_addr);
874
875 /* Set aside 16 bytes for the callee to save regs 1-4. */
876 stack_dest -= 16;
877
878 /* Update the stack pointer. */
879 regcache_cooked_write_unsigned (regcache, MT_SP_REGNUM, stack_dest);
880
881 /* And that should do it. Return the new stack pointer. */
882 return stack_dest;
883}
884
885
886/* The 'unwind_cache' data structure. */
887
888struct mt_unwind_cache
889{
890 /* The previous frame's inner most stack address.
891 Used as this frame ID's stack_addr. */
892 CORE_ADDR prev_sp;
893 CORE_ADDR frame_base;
894 int framesize;
895 int frameless_p;
896
897 /* Table indicating the location of each and every register. */
898 struct trad_frame_saved_reg *saved_regs;
899};
900
901/* Initialize an unwind_cache. Build up the saved_regs table etc. for
902 the frame. */
903
904static struct mt_unwind_cache *
905mt_frame_unwind_cache (struct frame_info *this_frame,
906 void **this_prologue_cache)
907{
908 struct gdbarch *gdbarch;
909 struct mt_unwind_cache *info;
910 CORE_ADDR next_addr, start_addr, end_addr, prologue_end_addr;
911 unsigned long instr, upper_half, delayed_store = 0;
912 int regnum, offset;
913 ULONGEST sp, fp;
914
915 if ((*this_prologue_cache))
916 return (*this_prologue_cache);
917
918 gdbarch = get_frame_arch (this_frame);
919 info = FRAME_OBSTACK_ZALLOC (struct mt_unwind_cache);
920 (*this_prologue_cache) = info;
921
922 info->prev_sp = 0;
923 info->framesize = 0;
924 info->frame_base = 0;
925 info->frameless_p = 1;
926 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
927
928 /* Grab the frame-relative values of SP and FP, needed below.
929 The frame_saved_register function will find them on the
930 stack or in the registers as appropriate. */
931 sp = get_frame_register_unsigned (this_frame, MT_SP_REGNUM);
932 fp = get_frame_register_unsigned (this_frame, MT_FP_REGNUM);
933
934 start_addr = get_frame_func (this_frame);
935
936 /* Return early if GDB couldn't find the function. */
937 if (start_addr == 0)
938 return info;
939
940 end_addr = get_frame_pc (this_frame);
941 prologue_end_addr = skip_prologue_using_sal (gdbarch, start_addr);
942 if (end_addr == 0)
943 for (next_addr = start_addr; next_addr < end_addr; next_addr += 4)
944 {
945 instr = get_frame_memory_unsigned (this_frame, next_addr, 4);
946 if (delayed_store) /* Previous instr was a push. */
947 {
948 upper_half = delayed_store >> 16;
949 regnum = upper_half & 0xf;
950 offset = delayed_store & 0xffff;
951 switch (upper_half & 0xfff0)
952 {
953 case 0x43c0: /* push using frame pointer. */
954 info->saved_regs[regnum].addr = offset;
955 break;
956 case 0x43d0: /* push using stack pointer. */
957 info->saved_regs[regnum].addr = offset;
958 break;
959 default: /* lint */
960 break;
961 }
962 delayed_store = 0;
963 }
964
965 switch (instr)
966 {
967 case 0x12000000: /* NO-OP */
968 continue;
969 case 0x12ddc000: /* copy sp into fp */
970 info->frameless_p = 0; /* Record that the frame
971 pointer is in use. */
972 continue;
973 default:
974 upper_half = instr >> 16;
975 if (upper_half == 0x05dd || /* subi sp, sp, imm */
976 upper_half == 0x07dd) /* subui sp, sp, imm */
977 {
978 /* Record the frame size. */
979 info->framesize = instr & 0xffff;
980 continue;
981 }
982 if ((upper_half & 0xfff0) == 0x43c0 || /* frame push */
983 (upper_half & 0xfff0) == 0x43d0) /* stack push */
984 {
985 /* Save this instruction, but don't record the
986 pushed register as 'saved' until we see the
987 next instruction. That's because of deferred stores
988 on this target -- GDB won't be able to read the register
989 from the stack until one instruction later. */
990 delayed_store = instr;
991 continue;
992 }
993 /* Not a prologue instruction. Is this the end of the prologue?
994 This is the most difficult decision; when to stop scanning.
995
996 If we have no line symbol, then the best thing we can do
997 is to stop scanning when we encounter an instruction that
998 is not likely to be a part of the prologue.
999
1000 But if we do have a line symbol, then we should
1001 keep scanning until we reach it (or we reach end_addr). */
1002
1003 if (prologue_end_addr && (prologue_end_addr > (next_addr + 4)))
1004 continue; /* Keep scanning, recording saved_regs etc. */
1005 else
1006 break; /* Quit scanning: breakpoint can be set here. */
1007 }
1008 }
1009
1010 /* Special handling for the "saved" address of the SP:
1011 The SP is of course never saved on the stack at all, so
1012 by convention what we put here is simply the previous
1013 _value_ of the SP (as opposed to an address where the
1014 previous value would have been pushed). This will also
1015 give us the frame base address. */
1016
1017 if (info->frameless_p)
1018 {
1019 info->frame_base = sp + info->framesize;
1020 info->prev_sp = sp + info->framesize;
1021 }
1022 else
1023 {
1024 info->frame_base = fp + info->framesize;
1025 info->prev_sp = fp + info->framesize;
1026 }
1027 /* Save prev_sp in saved_regs as a value, not as an address. */
1028 trad_frame_set_value (info->saved_regs, MT_SP_REGNUM, info->prev_sp);
1029
1030 /* Now convert frame offsets to actual addresses (not offsets). */
1031 for (regnum = 0; regnum < MT_NUM_REGS; regnum++)
1032 if (trad_frame_addr_p (info->saved_regs, regnum))
1033 info->saved_regs[regnum].addr += info->frame_base - info->framesize;
1034
1035 /* The call instruction moves the caller's PC in the callee's RA reg.
1036 Since this is an unwind, do the reverse. Copy the location of RA
1037 into PC (the address / regnum) so that a request for PC will be
1038 converted into a request for the RA. */
1039 info->saved_regs[MT_PC_REGNUM] = info->saved_regs[MT_RA_REGNUM];
1040
1041 return info;
1042}
1043
1044static CORE_ADDR
1045mt_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1046{
1047 ULONGEST pc;
1048
1049 pc = frame_unwind_register_unsigned (next_frame, MT_PC_REGNUM);
1050 return pc;
1051}
1052
1053static CORE_ADDR
1054mt_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1055{
1056 ULONGEST sp;
1057
1058 sp = frame_unwind_register_unsigned (next_frame, MT_SP_REGNUM);
1059 return sp;
1060}
1061
1062/* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy
1063 frame. The frame ID's base needs to match the TOS value saved by
1064 save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */
1065
1066static struct frame_id
1067mt_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1068{
1069 CORE_ADDR sp = get_frame_register_unsigned (this_frame, MT_SP_REGNUM);
1070 return frame_id_build (sp, get_frame_pc (this_frame));
1071}
1072
1073/* Given a GDB frame, determine the address of the calling function's
1074 frame. This will be used to create a new GDB frame struct. */
1075
1076static void
1077mt_frame_this_id (struct frame_info *this_frame,
1078 void **this_prologue_cache, struct frame_id *this_id)
1079{
1080 struct mt_unwind_cache *info =
1081 mt_frame_unwind_cache (this_frame, this_prologue_cache);
1082
1083 if (!(info == NULL || info->prev_sp == 0))
1084 (*this_id) = frame_id_build (info->prev_sp, get_frame_func (this_frame));
1085
1086 return;
1087}
1088
1089static struct value *
1090mt_frame_prev_register (struct frame_info *this_frame,
1091 void **this_prologue_cache, int regnum)
1092{
1093 struct mt_unwind_cache *info =
1094 mt_frame_unwind_cache (this_frame, this_prologue_cache);
1095
1096 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
1097}
1098
1099static CORE_ADDR
1100mt_frame_base_address (struct frame_info *this_frame,
1101 void **this_prologue_cache)
1102{
1103 struct mt_unwind_cache *info =
1104 mt_frame_unwind_cache (this_frame, this_prologue_cache);
1105
1106 return info->frame_base;
1107}
1108
1109/* This is a shared interface: the 'frame_unwind' object is what's
1110 returned by the 'sniffer' function, and in turn specifies how to
1111 get a frame's ID and prev_regs.
1112
1113 This exports the 'prev_register' and 'this_id' methods. */
1114
1115static const struct frame_unwind mt_frame_unwind = {
1116 NORMAL_FRAME,
1117 default_frame_unwind_stop_reason,
1118 mt_frame_this_id,
1119 mt_frame_prev_register,
1120 NULL,
1121 default_frame_sniffer
1122};
1123
1124/* Another shared interface: the 'frame_base' object specifies how to
1125 unwind a frame and secure the base addresses for frame objects
1126 (locals, args). */
1127
1128static struct frame_base mt_frame_base = {
1129 &mt_frame_unwind,
1130 mt_frame_base_address,
1131 mt_frame_base_address,
1132 mt_frame_base_address
1133};
1134
1135static struct gdbarch *
1136mt_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1137{
1138 struct gdbarch *gdbarch;
1139 struct gdbarch_tdep *tdep;
1140
1141 /* Find a candidate among the list of pre-declared architectures. */
1142 arches = gdbarch_list_lookup_by_info (arches, &info);
1143 if (arches != NULL)
1144 return arches->gdbarch;
1145
1146 /* None found, create a new architecture from the information
1147 provided. */
1148 tdep = XCALLOC (1, struct gdbarch_tdep);
1149 gdbarch = gdbarch_alloc (&info, tdep);
1150
1151 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
1152 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
1153 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
1154
1155 set_gdbarch_register_name (gdbarch, mt_register_name);
1156 set_gdbarch_num_regs (gdbarch, MT_NUM_REGS);
1157 set_gdbarch_num_pseudo_regs (gdbarch, MT_NUM_PSEUDO_REGS);
1158 set_gdbarch_pc_regnum (gdbarch, MT_PC_REGNUM);
1159 set_gdbarch_sp_regnum (gdbarch, MT_SP_REGNUM);
1160 set_gdbarch_pseudo_register_read (gdbarch, mt_pseudo_register_read);
1161 set_gdbarch_pseudo_register_write (gdbarch, mt_pseudo_register_write);
1162 set_gdbarch_skip_prologue (gdbarch, mt_skip_prologue);
1163 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1164 set_gdbarch_breakpoint_from_pc (gdbarch, mt_breakpoint_from_pc);
1165 set_gdbarch_decr_pc_after_break (gdbarch, 0);
1166 set_gdbarch_frame_args_skip (gdbarch, 0);
1167 set_gdbarch_print_insn (gdbarch, print_insn_mt);
1168 set_gdbarch_register_type (gdbarch, mt_register_type);
1169 set_gdbarch_register_reggroup_p (gdbarch, mt_register_reggroup_p);
1170
1171 set_gdbarch_return_value (gdbarch, mt_return_value);
1172 set_gdbarch_sp_regnum (gdbarch, MT_SP_REGNUM);
1173
1174 set_gdbarch_frame_align (gdbarch, mt_frame_align);
1175
1176 set_gdbarch_print_registers_info (gdbarch, mt_registers_info);
1177
1178 set_gdbarch_push_dummy_call (gdbarch, mt_push_dummy_call);
1179
1180 /* Target builtin data types. */
1181 set_gdbarch_short_bit (gdbarch, 16);
1182 set_gdbarch_int_bit (gdbarch, 32);
1183 set_gdbarch_long_bit (gdbarch, 32);
1184 set_gdbarch_long_long_bit (gdbarch, 64);
1185 set_gdbarch_float_bit (gdbarch, 32);
1186 set_gdbarch_double_bit (gdbarch, 64);
1187 set_gdbarch_long_double_bit (gdbarch, 64);
1188 set_gdbarch_ptr_bit (gdbarch, 32);
1189
1190 /* Register the DWARF 2 sniffer first, and then the traditional prologue
1191 based sniffer. */
1192 dwarf2_append_unwinders (gdbarch);
1193 frame_unwind_append_unwinder (gdbarch, &mt_frame_unwind);
1194 frame_base_set_default (gdbarch, &mt_frame_base);
1195
1196 /* Register the 'unwind_pc' method. */
1197 set_gdbarch_unwind_pc (gdbarch, mt_unwind_pc);
1198 set_gdbarch_unwind_sp (gdbarch, mt_unwind_sp);
1199
1200 /* Methods for saving / extracting a dummy frame's ID.
1201 The ID's stack address must match the SP value returned by
1202 PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */
1203 set_gdbarch_dummy_id (gdbarch, mt_dummy_id);
1204
1205 return gdbarch;
1206}
1207
1208/* Provide a prototype to silence -Wmissing-prototypes. */
1209extern initialize_file_ftype _initialize_mt_tdep;
1210
1211void
1212_initialize_mt_tdep (void)
1213{
1214 register_gdbarch_init (bfd_arch_mt, mt_gdbarch_init);
1215}
GDB Binutils - Deliverables
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