| 1 | /* Native-dependent code for GNU/Linux RISC-V. |
| 2 | Copyright (C) 2018-2020 Free Software Foundation, Inc. |
| 3 | |
| 4 | This file is part of GDB. |
| 5 | |
| 6 | This program is free software; you can redistribute it and/or modify |
| 7 | it under the terms of the GNU General Public License as published by |
| 8 | the Free Software Foundation; either version 3 of the License, or |
| 9 | (at your option) any later version. |
| 10 | |
| 11 | This program is distributed in the hope that it will be useful, |
| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | GNU General Public License for more details. |
| 15 | |
| 16 | You should have received a copy of the GNU General Public License |
| 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 18 | |
| 19 | #include "defs.h" |
| 20 | #include "regcache.h" |
| 21 | #include "gregset.h" |
| 22 | #include "linux-nat.h" |
| 23 | #include "riscv-tdep.h" |
| 24 | #include "inferior.h" |
| 25 | #include "target-descriptions.h" |
| 26 | |
| 27 | #include "elf/common.h" |
| 28 | |
| 29 | #include <sys/ptrace.h> |
| 30 | |
| 31 | /* RISC-V Linux native additions to the default linux support. */ |
| 32 | |
| 33 | class riscv_linux_nat_target final : public linux_nat_target |
| 34 | { |
| 35 | public: |
| 36 | /* Add our register access methods. */ |
| 37 | void fetch_registers (struct regcache *regcache, int regnum) override; |
| 38 | void store_registers (struct regcache *regcache, int regnum) override; |
| 39 | |
| 40 | /* Read suitable target description. */ |
| 41 | const struct target_desc *read_description () override; |
| 42 | }; |
| 43 | |
| 44 | static riscv_linux_nat_target the_riscv_linux_nat_target; |
| 45 | |
| 46 | /* Copy general purpose register REGNUM (or all gp regs if REGNUM == -1) |
| 47 | from regset GREGS into REGCACHE. */ |
| 48 | |
| 49 | static void |
| 50 | supply_gregset_regnum (struct regcache *regcache, const prgregset_t *gregs, |
| 51 | int regnum) |
| 52 | { |
| 53 | int i; |
| 54 | const elf_greg_t *regp = *gregs; |
| 55 | |
| 56 | if (regnum == -1) |
| 57 | { |
| 58 | /* We only support the integer registers and PC here. */ |
| 59 | for (i = RISCV_ZERO_REGNUM + 1; i < RISCV_PC_REGNUM; i++) |
| 60 | regcache->raw_supply (i, regp + i); |
| 61 | |
| 62 | /* GDB stores PC in reg 32. Linux kernel stores it in reg 0. */ |
| 63 | regcache->raw_supply (32, regp + 0); |
| 64 | |
| 65 | /* Fill the inaccessible zero register with zero. */ |
| 66 | regcache->raw_supply_zeroed (0); |
| 67 | } |
| 68 | else if (regnum == RISCV_ZERO_REGNUM) |
| 69 | regcache->raw_supply_zeroed (0); |
| 70 | else if (regnum > RISCV_ZERO_REGNUM && regnum < RISCV_PC_REGNUM) |
| 71 | regcache->raw_supply (regnum, regp + regnum); |
| 72 | else if (regnum == RISCV_PC_REGNUM) |
| 73 | regcache->raw_supply (32, regp + 0); |
| 74 | } |
| 75 | |
| 76 | /* Copy all general purpose registers from regset GREGS into REGCACHE. */ |
| 77 | |
| 78 | void |
| 79 | supply_gregset (struct regcache *regcache, const prgregset_t *gregs) |
| 80 | { |
| 81 | supply_gregset_regnum (regcache, gregs, -1); |
| 82 | } |
| 83 | |
| 84 | /* Copy floating point register REGNUM (or all fp regs if REGNUM == -1) |
| 85 | from regset FPREGS into REGCACHE. */ |
| 86 | |
| 87 | static void |
| 88 | supply_fpregset_regnum (struct regcache *regcache, const prfpregset_t *fpregs, |
| 89 | int regnum) |
| 90 | { |
| 91 | int i; |
| 92 | |
| 93 | if (regnum == -1) |
| 94 | { |
| 95 | /* We only support the FP registers and FCSR here. */ |
| 96 | for (i = RISCV_FIRST_FP_REGNUM; i <= RISCV_LAST_FP_REGNUM; i++) |
| 97 | regcache->raw_supply (i, &fpregs->__d.__f[i - RISCV_FIRST_FP_REGNUM]); |
| 98 | |
| 99 | regcache->raw_supply (RISCV_CSR_FCSR_REGNUM, &fpregs->__d.__fcsr); |
| 100 | } |
| 101 | else if (regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM) |
| 102 | regcache->raw_supply (regnum, |
| 103 | &fpregs->__d.__f[regnum - RISCV_FIRST_FP_REGNUM]); |
| 104 | else if (regnum == RISCV_CSR_FCSR_REGNUM) |
| 105 | regcache->raw_supply (RISCV_CSR_FCSR_REGNUM, &fpregs->__d.__fcsr); |
| 106 | } |
| 107 | |
| 108 | /* Copy all floating point registers from regset FPREGS into REGCACHE. */ |
| 109 | |
| 110 | void |
| 111 | supply_fpregset (struct regcache *regcache, const prfpregset_t *fpregs) |
| 112 | { |
| 113 | supply_fpregset_regnum (regcache, fpregs, -1); |
| 114 | } |
| 115 | |
| 116 | /* Copy general purpose register REGNUM (or all gp regs if REGNUM == -1) |
| 117 | from REGCACHE into regset GREGS. */ |
| 118 | |
| 119 | void |
| 120 | fill_gregset (const struct regcache *regcache, prgregset_t *gregs, int regnum) |
| 121 | { |
| 122 | elf_greg_t *regp = *gregs; |
| 123 | |
| 124 | if (regnum == -1) |
| 125 | { |
| 126 | /* We only support the integer registers and PC here. */ |
| 127 | for (int i = RISCV_ZERO_REGNUM + 1; i < RISCV_PC_REGNUM; i++) |
| 128 | regcache->raw_collect (i, regp + i); |
| 129 | |
| 130 | regcache->raw_collect (32, regp + 0); |
| 131 | } |
| 132 | else if (regnum == RISCV_ZERO_REGNUM) |
| 133 | /* Nothing to do here. */ |
| 134 | ; |
| 135 | else if (regnum > RISCV_ZERO_REGNUM && regnum < RISCV_PC_REGNUM) |
| 136 | regcache->raw_collect (regnum, regp + regnum); |
| 137 | else if (regnum == RISCV_PC_REGNUM) |
| 138 | regcache->raw_collect (32, regp + 0); |
| 139 | } |
| 140 | |
| 141 | /* Copy floating point register REGNUM (or all fp regs if REGNUM == -1) |
| 142 | from REGCACHE into regset FPREGS. */ |
| 143 | |
| 144 | void |
| 145 | fill_fpregset (const struct regcache *regcache, prfpregset_t *fpregs, |
| 146 | int regnum) |
| 147 | { |
| 148 | if (regnum == -1) |
| 149 | { |
| 150 | /* We only support the FP registers and FCSR here. */ |
| 151 | for (int i = RISCV_FIRST_FP_REGNUM; i <= RISCV_LAST_FP_REGNUM; i++) |
| 152 | regcache->raw_collect (i, &fpregs->__d.__f[i - RISCV_FIRST_FP_REGNUM]); |
| 153 | |
| 154 | regcache->raw_collect (RISCV_CSR_FCSR_REGNUM, &fpregs->__d.__fcsr); |
| 155 | } |
| 156 | else if (regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM) |
| 157 | regcache->raw_collect (regnum, |
| 158 | &fpregs->__d.__f[regnum - RISCV_FIRST_FP_REGNUM]); |
| 159 | else if (regnum == RISCV_CSR_FCSR_REGNUM) |
| 160 | regcache->raw_collect (RISCV_CSR_FCSR_REGNUM, &fpregs->__d.__fcsr); |
| 161 | } |
| 162 | |
| 163 | /* Return a target description for the current target. */ |
| 164 | |
| 165 | const struct target_desc * |
| 166 | riscv_linux_nat_target::read_description () |
| 167 | { |
| 168 | struct riscv_gdbarch_features features; |
| 169 | struct iovec iov; |
| 170 | elf_fpregset_t regs; |
| 171 | int tid; |
| 172 | |
| 173 | /* Figuring out xlen is easy. */ |
| 174 | features.xlen = sizeof (elf_greg_t); |
| 175 | |
| 176 | tid = inferior_ptid.lwp (); |
| 177 | |
| 178 | iov.iov_base = ®s; |
| 179 | iov.iov_len = sizeof (regs); |
| 180 | |
| 181 | /* Can we fetch the f-registers? */ |
| 182 | if (ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, |
| 183 | (PTRACE_TYPE_ARG3) &iov) == -1) |
| 184 | features.flen = 0; /* No f-registers. */ |
| 185 | else |
| 186 | { |
| 187 | /* TODO: We need a way to figure out the actual length of the |
| 188 | f-registers. We could have 64-bit x-registers, with 32-bit |
| 189 | f-registers. For now, just assumed xlen and flen match. */ |
| 190 | features.flen = features.xlen; |
| 191 | } |
| 192 | |
| 193 | return riscv_create_target_description (features); |
| 194 | } |
| 195 | |
| 196 | /* Fetch REGNUM (or all registers if REGNUM == -1) from the target |
| 197 | into REGCACHE using PTRACE_GETREGSET. */ |
| 198 | |
| 199 | void |
| 200 | riscv_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum) |
| 201 | { |
| 202 | int tid; |
| 203 | |
| 204 | tid = get_ptrace_pid (regcache->ptid()); |
| 205 | |
| 206 | if ((regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_PC_REGNUM) |
| 207 | || (regnum == -1)) |
| 208 | { |
| 209 | struct iovec iov; |
| 210 | elf_gregset_t regs; |
| 211 | |
| 212 | iov.iov_base = ®s; |
| 213 | iov.iov_len = sizeof (regs); |
| 214 | |
| 215 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, |
| 216 | (PTRACE_TYPE_ARG3) &iov) == -1) |
| 217 | perror_with_name (_("Couldn't get registers")); |
| 218 | else |
| 219 | supply_gregset_regnum (regcache, ®s, regnum); |
| 220 | } |
| 221 | |
| 222 | if ((regnum >= RISCV_FIRST_FP_REGNUM |
| 223 | && regnum <= RISCV_LAST_FP_REGNUM) |
| 224 | || (regnum == RISCV_CSR_FCSR_REGNUM) |
| 225 | || (regnum == -1)) |
| 226 | { |
| 227 | struct iovec iov; |
| 228 | elf_fpregset_t regs; |
| 229 | |
| 230 | iov.iov_base = ®s; |
| 231 | iov.iov_len = sizeof (regs); |
| 232 | |
| 233 | if (ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, |
| 234 | (PTRACE_TYPE_ARG3) &iov) == -1) |
| 235 | perror_with_name (_("Couldn't get registers")); |
| 236 | else |
| 237 | supply_fpregset_regnum (regcache, ®s, regnum); |
| 238 | } |
| 239 | |
| 240 | if ((regnum == RISCV_CSR_MISA_REGNUM) |
| 241 | || (regnum == -1)) |
| 242 | { |
| 243 | /* TODO: Need to add a ptrace call for this. */ |
| 244 | regcache->raw_supply_zeroed (RISCV_CSR_MISA_REGNUM); |
| 245 | } |
| 246 | |
| 247 | /* Access to other CSRs has potential security issues, don't support them for |
| 248 | now. */ |
| 249 | } |
| 250 | |
| 251 | /* Store REGNUM (or all registers if REGNUM == -1) to the target |
| 252 | from REGCACHE using PTRACE_SETREGSET. */ |
| 253 | |
| 254 | void |
| 255 | riscv_linux_nat_target::store_registers (struct regcache *regcache, int regnum) |
| 256 | { |
| 257 | int tid; |
| 258 | |
| 259 | tid = get_ptrace_pid (regcache->ptid ()); |
| 260 | |
| 261 | if ((regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_PC_REGNUM) |
| 262 | || (regnum == -1)) |
| 263 | { |
| 264 | struct iovec iov; |
| 265 | elf_gregset_t regs; |
| 266 | |
| 267 | iov.iov_base = ®s; |
| 268 | iov.iov_len = sizeof (regs); |
| 269 | |
| 270 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, |
| 271 | (PTRACE_TYPE_ARG3) &iov) == -1) |
| 272 | perror_with_name (_("Couldn't get registers")); |
| 273 | else |
| 274 | { |
| 275 | fill_gregset (regcache, ®s, regnum); |
| 276 | |
| 277 | if (ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, |
| 278 | (PTRACE_TYPE_ARG3) &iov) == -1) |
| 279 | perror_with_name (_("Couldn't set registers")); |
| 280 | } |
| 281 | } |
| 282 | |
| 283 | if ((regnum >= RISCV_FIRST_FP_REGNUM |
| 284 | && regnum <= RISCV_LAST_FP_REGNUM) |
| 285 | || (regnum == RISCV_CSR_FCSR_REGNUM) |
| 286 | || (regnum == -1)) |
| 287 | { |
| 288 | struct iovec iov; |
| 289 | elf_fpregset_t regs; |
| 290 | |
| 291 | iov.iov_base = ®s; |
| 292 | iov.iov_len = sizeof (regs); |
| 293 | |
| 294 | if (ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, |
| 295 | (PTRACE_TYPE_ARG3) &iov) == -1) |
| 296 | perror_with_name (_("Couldn't get registers")); |
| 297 | else |
| 298 | { |
| 299 | fill_fpregset (regcache, ®s, regnum); |
| 300 | |
| 301 | if (ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, |
| 302 | (PTRACE_TYPE_ARG3) &iov) == -1) |
| 303 | perror_with_name (_("Couldn't set registers")); |
| 304 | } |
| 305 | } |
| 306 | |
| 307 | /* Access to CSRs has potential security issues, don't support them for |
| 308 | now. */ |
| 309 | } |
| 310 | |
| 311 | /* Initialize RISC-V Linux native support. */ |
| 312 | |
| 313 | void |
| 314 | _initialize_riscv_linux_nat (void) |
| 315 | { |
| 316 | /* Register the target. */ |
| 317 | linux_target = &the_riscv_linux_nat_target; |
| 318 | add_inf_child_target (&the_riscv_linux_nat_target); |
| 319 | } |