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* linux-nat.c (my_waitpid): New function.
[deliverable/binutils-gdb.git] / gdb / sparc-tdep.c
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1/* Target-dependent code for SPARC.
2
3 Copyright 2003, 2004 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22#include "defs.h"
23#include "arch-utils.h"
24#include "dis-asm.h"
25#include "floatformat.h"
26#include "frame.h"
27#include "frame-base.h"
28#include "frame-unwind.h"
29#include "gdbcore.h"
30#include "gdbtypes.h"
31#include "inferior.h"
32#include "symtab.h"
33#include "objfiles.h"
34#include "osabi.h"
35#include "regcache.h"
36#include "target.h"
37#include "value.h"
38
39#include "gdb_assert.h"
40#include "gdb_string.h"
41
42#include "sparc-tdep.h"
43
44struct regset;
45
46/* This file implements the SPARC 32-bit ABI as defined by the section
47 "Low-Level System Information" of the SPARC Compliance Definition
48 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
49 lists changes with respect to the original 32-bit psABI as defined
50 in the "System V ABI, SPARC Processor Supplement".
51
52 Note that if we talk about SunOS, we mean SunOS 4.x, which was
53 BSD-based, which is sometimes (retroactively?) referred to as
54 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
55 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
56 suffering from severe version number inflation). Solaris 2.x is
57 also known as SunOS 5.x, since that's what uname(1) says. Solaris
58 2.x is SVR4-based. */
59
60/* Please use the sparc32_-prefix for 32-bit specific code, the
61 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
62 code that can handle both. The 64-bit specific code lives in
63 sparc64-tdep.c; don't add any here. */
64
65/* The SPARC Floating-Point Quad-Precision format is similar to
66 big-endian IA-64 Quad-recision format. */
67#define floatformat_sparc_quad floatformat_ia64_quad_big
68
69/* The stack pointer is offset from the stack frame by a BIAS of 2047
70 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
71 hosts, so undefine it first. */
72#undef BIAS
73#define BIAS 2047
74
75/* Macros to extract fields from SPARC instructions. */
76#define X_OP(i) (((i) >> 30) & 0x3)
77#define X_RD(i) (((i) >> 25) & 0x1f)
78#define X_A(i) (((i) >> 29) & 1)
79#define X_COND(i) (((i) >> 25) & 0xf)
80#define X_OP2(i) (((i) >> 22) & 0x7)
81#define X_IMM22(i) ((i) & 0x3fffff)
82#define X_OP3(i) (((i) >> 19) & 0x3f)
83#define X_I(i) (((i) >> 13) & 1)
84/* Sign extension macros. */
85#define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
86#define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
87
88/* Fetch the instruction at PC. Instructions are always big-endian
89 even if the processor operates in little-endian mode. */
90
91unsigned long
92sparc_fetch_instruction (CORE_ADDR pc)
93{
94 unsigned char buf[4];
95 unsigned long insn;
96 int i;
97
98 /* If we can't read the instruction at PC, return zero. */
99 if (target_read_memory (pc, buf, sizeof (buf)))
100 return 0;
101
102 insn = 0;
103 for (i = 0; i < sizeof (buf); i++)
104 insn = (insn << 8) | buf[i];
105 return insn;
106}
107\f
108
109/* OpenBSD/sparc includes StackGhost, which according to the author's
110 website http://stackghost.cerias.purdue.edu "... transparently and
111 automatically protects applications' stack frames; more
112 specifically, it guards the return pointers. The protection
113 mechanisms require no application source or binary modification and
114 imposes only a negligible performance penalty."
115
116 The same website provides the following description of how
117 StackGhost works:
118
119 "StackGhost interfaces with the kernel trap handler that would
120 normally write out registers to the stack and the handler that
121 would read them back in. By XORing a cookie into the
122 return-address saved in the user stack when it is actually written
123 to the stack, and then XOR it out when the return-address is pulled
124 from the stack, StackGhost can cause attacker corrupted return
125 pointers to behave in a manner the attacker cannot predict.
126 StackGhost can also use several unused bits in the return pointer
127 to detect a smashed return pointer and abort the process."
128
129 For GDB this means that whenever we're reading %i7 from a stack
130 frame's window save area, we'll have to XOR the cookie.
131
132 More information on StackGuard can be found on in:
133
134 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
135 Stack Protection." 2001. Published in USENIX Security Symposium
136 '01. */
137
138/* Fetch StackGhost Per-Process XOR cookie. */
139
140ULONGEST
141sparc_fetch_wcookie (void)
142{
143 struct target_ops *ops = &current_target;
144 char buf[8];
145 int len;
146
147 len = target_read_partial (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8);
148 if (len == -1)
149 return 0;
150
151 /* We should have either an 32-bit or an 64-bit cookie. */
152 gdb_assert (len == 4 || len == 8);
153
154 return extract_unsigned_integer (buf, len);
155}
156\f
157
158/* Return the contents if register REGNUM as an address. */
159
160static CORE_ADDR
161sparc_address_from_register (int regnum)
162{
163 ULONGEST addr;
164
165 regcache_cooked_read_unsigned (current_regcache, regnum, &addr);
166 return addr;
167}
168\f
169
170/* The functions on this page are intended to be used to classify
171 function arguments. */
172
173/* Check whether TYPE is "Integral or Pointer". */
174
175static int
176sparc_integral_or_pointer_p (const struct type *type)
177{
178 switch (TYPE_CODE (type))
179 {
180 case TYPE_CODE_INT:
181 case TYPE_CODE_BOOL:
182 case TYPE_CODE_CHAR:
183 case TYPE_CODE_ENUM:
184 case TYPE_CODE_RANGE:
185 {
186 /* We have byte, half-word, word and extended-word/doubleword
187 integral types. The doubleword is an extension to the
188 original 32-bit ABI by the SCD 2.4.x. */
189 int len = TYPE_LENGTH (type);
190 return (len == 1 || len == 2 || len == 4 || len == 8);
191 }
192 return 1;
193 case TYPE_CODE_PTR:
194 case TYPE_CODE_REF:
195 {
196 /* Allow either 32-bit or 64-bit pointers. */
197 int len = TYPE_LENGTH (type);
198 return (len == 4 || len == 8);
199 }
200 return 1;
201 default:
202 break;
203 }
204
205 return 0;
206}
207
208/* Check whether TYPE is "Floating". */
209
210static int
211sparc_floating_p (const struct type *type)
212{
213 switch (TYPE_CODE (type))
214 {
215 case TYPE_CODE_FLT:
216 {
217 int len = TYPE_LENGTH (type);
218 return (len == 4 || len == 8 || len == 16);
219 }
220 default:
221 break;
222 }
223
224 return 0;
225}
226
227/* Check whether TYPE is "Structure or Union". */
228
229static int
230sparc_structure_or_union_p (const struct type *type)
231{
232 switch (TYPE_CODE (type))
233 {
234 case TYPE_CODE_STRUCT:
235 case TYPE_CODE_UNION:
236 return 1;
237 default:
238 break;
239 }
240
241 return 0;
242}
243
244/* Register information. */
245
246static const char *sparc32_register_names[] =
247{
248 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
249 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
250 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
251 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
252
253 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
254 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
255 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
256 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
257
258 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
259};
260
261/* Total number of registers. */
262#define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
263
264/* We provide the aliases %d0..%d30 for the floating registers as
265 "psuedo" registers. */
266
267static const char *sparc32_pseudo_register_names[] =
268{
269 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
270 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
271};
272
273/* Total number of pseudo registers. */
274#define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
275
276/* Return the name of register REGNUM. */
277
278static const char *
279sparc32_register_name (int regnum)
280{
281 if (regnum >= 0 && regnum < SPARC32_NUM_REGS)
282 return sparc32_register_names[regnum];
283
284 if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS)
285 return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS];
286
287 return NULL;
288}
289
290/* Return the GDB type object for the "standard" data type of data in
291 register REGNUM. */
292
293static struct type *
294sparc32_register_type (struct gdbarch *gdbarch, int regnum)
295{
296 if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM)
297 return builtin_type_float;
298
299 if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM)
300 return builtin_type_double;
301
302 if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM)
303 return builtin_type_void_data_ptr;
304
305 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
306 return builtin_type_void_func_ptr;
307
308 return builtin_type_int32;
309}
310
311static void
312sparc32_pseudo_register_read (struct gdbarch *gdbarch,
313 struct regcache *regcache,
314 int regnum, void *buf)
315{
316 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
317
318 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
319 regcache_raw_read (regcache, regnum, buf);
320 regcache_raw_read (regcache, regnum + 1, ((char *)buf) + 4);
321}
322
323static void
324sparc32_pseudo_register_write (struct gdbarch *gdbarch,
325 struct regcache *regcache,
326 int regnum, const void *buf)
327{
328 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
329
330 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
331 regcache_raw_write (regcache, regnum, buf);
332 regcache_raw_write (regcache, regnum + 1, ((const char *)buf) + 4);
333}
334\f
335
336static CORE_ADDR
337sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
338 CORE_ADDR funcaddr, int using_gcc,
339 struct value **args, int nargs,
340 struct type *value_type,
341 CORE_ADDR *real_pc, CORE_ADDR *bp_addr)
342{
343 *bp_addr = sp - 4;
344 *real_pc = funcaddr;
345
346 if (using_struct_return (value_type, using_gcc))
347 {
348 char buf[4];
349
350 /* This is an UNIMP instruction. */
351 store_unsigned_integer (buf, 4, TYPE_LENGTH (value_type) & 0x1fff);
352 write_memory (sp - 8, buf, 4);
353 return sp - 8;
354 }
355
356 return sp - 4;
357}
358
359static CORE_ADDR
360sparc32_store_arguments (struct regcache *regcache, int nargs,
361 struct value **args, CORE_ADDR sp,
362 int struct_return, CORE_ADDR struct_addr)
363{
364 /* Number of words in the "parameter array". */
365 int num_elements = 0;
366 int element = 0;
367 int i;
368
369 for (i = 0; i < nargs; i++)
370 {
371 struct type *type = value_type (args[i]);
372 int len = TYPE_LENGTH (type);
373
374 if (sparc_structure_or_union_p (type)
375 || (sparc_floating_p (type) && len == 16))
376 {
377 /* Structure, Union and Quad-Precision Arguments. */
378 sp -= len;
379
380 /* Use doubleword alignment for these values. That's always
381 correct, and wasting a few bytes shouldn't be a problem. */
382 sp &= ~0x7;
383
384 write_memory (sp, VALUE_CONTENTS (args[i]), len);
385 args[i] = value_from_pointer (lookup_pointer_type (type), sp);
386 num_elements++;
387 }
388 else if (sparc_floating_p (type))
389 {
390 /* Floating arguments. */
391 gdb_assert (len == 4 || len == 8);
392 num_elements += (len / 4);
393 }
394 else
395 {
396 /* Integral and pointer arguments. */
397 gdb_assert (sparc_integral_or_pointer_p (type));
398
399 if (len < 4)
400 args[i] = value_cast (builtin_type_int32, args[i]);
401 num_elements += ((len + 3) / 4);
402 }
403 }
404
405 /* Always allocate at least six words. */
406 sp -= max (6, num_elements) * 4;
407
408 /* The psABI says that "Software convention requires space for the
409 struct/union return value pointer, even if the word is unused." */
410 sp -= 4;
411
412 /* The psABI says that "Although software convention and the
413 operating system require every stack frame to be doubleword
414 aligned." */
415 sp &= ~0x7;
416
417 for (i = 0; i < nargs; i++)
418 {
419 char *valbuf = VALUE_CONTENTS (args[i]);
420 struct type *type = value_type (args[i]);
421 int len = TYPE_LENGTH (type);
422
423 gdb_assert (len == 4 || len == 8);
424
425 if (element < 6)
426 {
427 int regnum = SPARC_O0_REGNUM + element;
428
429 regcache_cooked_write (regcache, regnum, valbuf);
430 if (len > 4 && element < 5)
431 regcache_cooked_write (regcache, regnum + 1, valbuf + 4);
432 }
433
434 /* Always store the argument in memory. */
435 write_memory (sp + 4 + element * 4, valbuf, len);
436 element += len / 4;
437 }
438
439 gdb_assert (element == num_elements);
440
441 if (struct_return)
442 {
443 char buf[4];
444
445 store_unsigned_integer (buf, 4, struct_addr);
446 write_memory (sp, buf, 4);
447 }
448
449 return sp;
450}
451
452static CORE_ADDR
453sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
454 struct regcache *regcache, CORE_ADDR bp_addr,
455 int nargs, struct value **args, CORE_ADDR sp,
456 int struct_return, CORE_ADDR struct_addr)
457{
458 CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8));
459
460 /* Set return address. */
461 regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc);
462
463 /* Set up function arguments. */
464 sp = sparc32_store_arguments (regcache, nargs, args, sp,
465 struct_return, struct_addr);
466
467 /* Allocate the 16-word window save area. */
468 sp -= 16 * 4;
469
470 /* Stack should be doubleword aligned at this point. */
471 gdb_assert (sp % 8 == 0);
472
473 /* Finally, update the stack pointer. */
474 regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp);
475
476 return sp;
477}
478\f
479
480/* Use the program counter to determine the contents and size of a
481 breakpoint instruction. Return a pointer to a string of bytes that
482 encode a breakpoint instruction, store the length of the string in
483 *LEN and optionally adjust *PC to point to the correct memory
484 location for inserting the breakpoint. */
485
486static const unsigned char *
487sparc_breakpoint_from_pc (CORE_ADDR *pc, int *len)
488{
489 static unsigned char break_insn[] = { 0x91, 0xd0, 0x20, 0x01 };
490
491 *len = sizeof (break_insn);
492 return break_insn;
493}
494\f
495
496/* Allocate and initialize a frame cache. */
497
498static struct sparc_frame_cache *
499sparc_alloc_frame_cache (void)
500{
501 struct sparc_frame_cache *cache;
502 int i;
503
504 cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache);
505
506 /* Base address. */
507 cache->base = 0;
508 cache->pc = 0;
509
510 /* Frameless until proven otherwise. */
511 cache->frameless_p = 1;
512
513 cache->struct_return_p = 0;
514
515 return cache;
516}
517
518CORE_ADDR
519sparc_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
520 struct sparc_frame_cache *cache)
521{
522 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
523 unsigned long insn;
524 int offset = 0;
525 int dest = -1;
526
527 if (current_pc <= pc)
528 return current_pc;
529
530 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
531 SPARC the linker usually defines a symbol (typically
532 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
533 This symbol makes us end up here with PC pointing at the start of
534 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
535 would do our normal prologue analysis, we would probably conclude
536 that we've got a frame when in reality we don't, since the
537 dynamic linker patches up the first PLT with some code that
538 starts with a SAVE instruction. Patch up PC such that it points
539 at the start of our PLT entry. */
540 if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL))
541 pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size);
542
543 insn = sparc_fetch_instruction (pc);
544
545 /* Recognize a SETHI insn and record its destination. */
546 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04)
547 {
548 dest = X_RD (insn);
549 offset += 4;
550
551 insn = sparc_fetch_instruction (pc + 4);
552 }
553
554 /* Allow for an arithmetic operation on DEST or %g1. */
555 if (X_OP (insn) == 2 && X_I (insn)
556 && (X_RD (insn) == 1 || X_RD (insn) == dest))
557 {
558 offset += 4;
559
560 insn = sparc_fetch_instruction (pc + 8);
561 }
562
563 /* Check for the SAVE instruction that sets up the frame. */
564 if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c)
565 {
566 cache->frameless_p = 0;
567 return pc + offset + 4;
568 }
569
570 return pc;
571}
572
573static CORE_ADDR
574sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
575{
576 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
577 return frame_unwind_register_unsigned (next_frame, tdep->pc_regnum);
578}
579
580/* Return PC of first real instruction of the function starting at
581 START_PC. */
582
583static CORE_ADDR
584sparc32_skip_prologue (CORE_ADDR start_pc)
585{
586 struct symtab_and_line sal;
587 CORE_ADDR func_start, func_end;
588 struct sparc_frame_cache cache;
589
590 /* This is the preferred method, find the end of the prologue by
591 using the debugging information. */
592 if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end))
593 {
594 sal = find_pc_line (func_start, 0);
595
596 if (sal.end < func_end
597 && start_pc <= sal.end)
598 return sal.end;
599 }
600
601 return sparc_analyze_prologue (start_pc, 0xffffffffUL, &cache);
602}
603
604/* Normal frames. */
605
606struct sparc_frame_cache *
607sparc_frame_cache (struct frame_info *next_frame, void **this_cache)
608{
609 struct sparc_frame_cache *cache;
610
611 if (*this_cache)
612 return *this_cache;
613
614 cache = sparc_alloc_frame_cache ();
615 *this_cache = cache;
616
617 cache->pc = frame_func_unwind (next_frame);
618 if (cache->pc != 0)
619 {
620 CORE_ADDR addr_in_block = frame_unwind_address_in_block (next_frame);
621 sparc_analyze_prologue (cache->pc, addr_in_block, cache);
622 }
623
624 if (cache->frameless_p)
625 {
626 /* This function is frameless, so %fp (%i6) holds the frame
627 pointer for our calling frame. Use %sp (%o6) as this frame's
628 base address. */
629 cache->base =
630 frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM);
631 }
632 else
633 {
634 /* For normal frames, %fp (%i6) holds the frame pointer, the
635 base address for the current stack frame. */
636 cache->base =
637 frame_unwind_register_unsigned (next_frame, SPARC_FP_REGNUM);
638 }
639
640 return cache;
641}
642
643struct sparc_frame_cache *
644sparc32_frame_cache (struct frame_info *next_frame, void **this_cache)
645{
646 struct sparc_frame_cache *cache;
647 struct symbol *sym;
648
649 if (*this_cache)
650 return *this_cache;
651
652 cache = sparc_frame_cache (next_frame, this_cache);
653
654 sym = find_pc_function (cache->pc);
655 if (sym)
656 {
657 struct type *type = check_typedef (SYMBOL_TYPE (sym));
658 enum type_code code = TYPE_CODE (type);
659
660 if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD)
661 {
662 type = check_typedef (TYPE_TARGET_TYPE (type));
663 if (sparc_structure_or_union_p (type)
664 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
665 cache->struct_return_p = 1;
666 }
667 }
668
669 return cache;
670}
671
672static void
673sparc32_frame_this_id (struct frame_info *next_frame, void **this_cache,
674 struct frame_id *this_id)
675{
676 struct sparc_frame_cache *cache =
677 sparc32_frame_cache (next_frame, this_cache);
678
679 /* This marks the outermost frame. */
680 if (cache->base == 0)
681 return;
682
683 (*this_id) = frame_id_build (cache->base, cache->pc);
684}
685
686static void
687sparc32_frame_prev_register (struct frame_info *next_frame, void **this_cache,
688 int regnum, int *optimizedp,
689 enum lval_type *lvalp, CORE_ADDR *addrp,
690 int *realnump, void *valuep)
691{
692 struct sparc_frame_cache *cache =
693 sparc32_frame_cache (next_frame, this_cache);
694
695 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
696 {
697 *optimizedp = 0;
698 *lvalp = not_lval;
699 *addrp = 0;
700 *realnump = -1;
701 if (valuep)
702 {
703 CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0;
704
705 /* If this functions has a Structure, Union or
706 Quad-Precision return value, we have to skip the UNIMP
707 instruction that encodes the size of the structure. */
708 if (cache->struct_return_p)
709 pc += 4;
710
711 regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM;
712 pc += frame_unwind_register_unsigned (next_frame, regnum) + 8;
713 store_unsigned_integer (valuep, 4, pc);
714 }
715 return;
716 }
717
718 /* Handle StackGhost. */
719 {
720 ULONGEST wcookie = sparc_fetch_wcookie ();
721
722 if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM)
723 {
724 *optimizedp = 0;
725 *lvalp = not_lval;
726 *addrp = 0;
727 *realnump = -1;
728 if (valuep)
729 {
730 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
731 ULONGEST i7;
732
733 /* Read the value in from memory. */
734 i7 = get_frame_memory_unsigned (next_frame, addr, 4);
735 store_unsigned_integer (valuep, 4, i7 ^ wcookie);
736 }
737 return;
738 }
739 }
740
741 /* The previous frame's `local' and `in' registers have been saved
742 in the register save area. */
743 if (!cache->frameless_p
744 && regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM)
745 {
746 *optimizedp = 0;
747 *lvalp = lval_memory;
748 *addrp = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
749 *realnump = -1;
750 if (valuep)
751 {
752 struct gdbarch *gdbarch = get_frame_arch (next_frame);
753
754 /* Read the value in from memory. */
755 read_memory (*addrp, valuep, register_size (gdbarch, regnum));
756 }
757 return;
758 }
759
760 /* The previous frame's `out' registers are accessable as the
761 current frame's `in' registers. */
762 if (!cache->frameless_p
763 && regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM)
764 regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM);
765
766 *optimizedp = 0;
767 *lvalp = lval_register;
768 *addrp = 0;
769 *realnump = regnum;
770 if (valuep)
771 frame_unwind_register (next_frame, (*realnump), valuep);
772}
773
774static const struct frame_unwind sparc32_frame_unwind =
775{
776 NORMAL_FRAME,
777 sparc32_frame_this_id,
778 sparc32_frame_prev_register
779};
780
781static const struct frame_unwind *
782sparc32_frame_sniffer (struct frame_info *next_frame)
783{
784 return &sparc32_frame_unwind;
785}
786\f
787
788static CORE_ADDR
789sparc32_frame_base_address (struct frame_info *next_frame, void **this_cache)
790{
791 struct sparc_frame_cache *cache =
792 sparc32_frame_cache (next_frame, this_cache);
793
794 return cache->base;
795}
796
797static const struct frame_base sparc32_frame_base =
798{
799 &sparc32_frame_unwind,
800 sparc32_frame_base_address,
801 sparc32_frame_base_address,
802 sparc32_frame_base_address
803};
804
805static struct frame_id
806sparc_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
807{
808 CORE_ADDR sp;
809
810 sp = frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM);
811 return frame_id_build (sp, frame_pc_unwind (next_frame));
812}
813\f
814
815/* Extract from an array REGBUF containing the (raw) register state, a
816 function return value of TYPE, and copy that into VALBUF. */
817
818static void
819sparc32_extract_return_value (struct type *type, struct regcache *regcache,
820 void *valbuf)
821{
822 int len = TYPE_LENGTH (type);
823 char buf[8];
824
825 gdb_assert (!sparc_structure_or_union_p (type));
826 gdb_assert (!(sparc_floating_p (type) && len == 16));
827
828 if (sparc_floating_p (type))
829 {
830 /* Floating return values. */
831 regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf);
832 if (len > 4)
833 regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4);
834 memcpy (valbuf, buf, len);
835 }
836 else
837 {
838 /* Integral and pointer return values. */
839 gdb_assert (sparc_integral_or_pointer_p (type));
840
841 regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf);
842 if (len > 4)
843 {
844 regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4);
845 gdb_assert (len == 8);
846 memcpy (valbuf, buf, 8);
847 }
848 else
849 {
850 /* Just stripping off any unused bytes should preserve the
851 signed-ness just fine. */
852 memcpy (valbuf, buf + 4 - len, len);
853 }
854 }
855}
856
857/* Write into the appropriate registers a function return value stored
858 in VALBUF of type TYPE. */
859
860static void
861sparc32_store_return_value (struct type *type, struct regcache *regcache,
862 const void *valbuf)
863{
864 int len = TYPE_LENGTH (type);
865 char buf[8];
866
867 gdb_assert (!sparc_structure_or_union_p (type));
868 gdb_assert (!(sparc_floating_p (type) && len == 16));
869
870 if (sparc_floating_p (type))
871 {
872 /* Floating return values. */
873 memcpy (buf, valbuf, len);
874 regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf);
875 if (len > 4)
876 regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4);
877 }
878 else
879 {
880 /* Integral and pointer return values. */
881 gdb_assert (sparc_integral_or_pointer_p (type));
882
883 if (len > 4)
884 {
885 gdb_assert (len == 8);
886 memcpy (buf, valbuf, 8);
887 regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4);
888 }
889 else
890 {
891 /* ??? Do we need to do any sign-extension here? */
892 memcpy (buf + 4 - len, valbuf, len);
893 }
894 regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf);
895 }
896}
897
898static enum return_value_convention
899sparc32_return_value (struct gdbarch *gdbarch, struct type *type,
900 struct regcache *regcache, void *readbuf,
901 const void *writebuf)
902{
903 if (sparc_structure_or_union_p (type)
904 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
905 return RETURN_VALUE_STRUCT_CONVENTION;
906
907 if (readbuf)
908 sparc32_extract_return_value (type, regcache, readbuf);
909 if (writebuf)
910 sparc32_store_return_value (type, regcache, writebuf);
911
912 return RETURN_VALUE_REGISTER_CONVENTION;
913}
914
915#if 0
916/* NOTE: cagney/2004-01-17: For the moment disable this method. The
917 architecture and CORE-gdb will need new code (and a replacement for
918 DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS) before this can be made to
919 work robustly. Here is a possible function signature: */
920/* NOTE: cagney/2004-01-17: So far only the 32-bit SPARC ABI has been
921 identifed as having a way to robustly recover the address of a
922 struct-convention return-value (after the function has returned).
923 For all other ABIs so far examined, the calling convention makes no
924 guarenteed that the register containing the return-value will be
925 preserved and hence that the return-value's address can be
926 recovered. */
927/* Extract from REGCACHE, which contains the (raw) register state, the
928 address in which a function should return its structure value, as a
929 CORE_ADDR. */
930
931static CORE_ADDR
932sparc32_extract_struct_value_address (struct regcache *regcache)
933{
934 ULONGEST sp;
935
936 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
937 return read_memory_unsigned_integer (sp + 64, 4);
938}
939#endif
940
941static int
942sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
943{
944 return (sparc_structure_or_union_p (type)
945 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16));
946}
947
948\f
949/* The SPARC Architecture doesn't have hardware single-step support,
950 and most operating systems don't implement it either, so we provide
951 software single-step mechanism. */
952
953static CORE_ADDR
954sparc_analyze_control_transfer (CORE_ADDR pc, CORE_ADDR *npc)
955{
956 unsigned long insn = sparc_fetch_instruction (pc);
957 int conditional_p = X_COND (insn) & 0x7;
958 int branch_p = 0;
959 long offset = 0; /* Must be signed for sign-extend. */
960
961 if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0)
962 {
963 /* Branch on Integer Register with Prediction (BPr). */
964 branch_p = 1;
965 conditional_p = 1;
966 }
967 else if (X_OP (insn) == 0 && X_OP2 (insn) == 6)
968 {
969 /* Branch on Floating-Point Condition Codes (FBfcc). */
970 branch_p = 1;
971 offset = 4 * X_DISP22 (insn);
972 }
973 else if (X_OP (insn) == 0 && X_OP2 (insn) == 5)
974 {
975 /* Branch on Floating-Point Condition Codes with Prediction
976 (FBPfcc). */
977 branch_p = 1;
978 offset = 4 * X_DISP19 (insn);
979 }
980 else if (X_OP (insn) == 0 && X_OP2 (insn) == 2)
981 {
982 /* Branch on Integer Condition Codes (Bicc). */
983 branch_p = 1;
984 offset = 4 * X_DISP22 (insn);
985 }
986 else if (X_OP (insn) == 0 && X_OP2 (insn) == 1)
987 {
988 /* Branch on Integer Condition Codes with Prediction (BPcc). */
989 branch_p = 1;
990 offset = 4 * X_DISP19 (insn);
991 }
992
993 /* FIXME: Handle DONE and RETRY instructions. */
994
995 /* FIXME: Handle the Trap instruction. */
996
997 if (branch_p)
998 {
999 if (conditional_p)
1000 {
1001 /* For conditional branches, return nPC + 4 iff the annul
1002 bit is 1. */
1003 return (X_A (insn) ? *npc + 4 : 0);
1004 }
1005 else
1006 {
1007 /* For unconditional branches, return the target if its
1008 specified condition is "always" and return nPC + 4 if the
1009 condition is "never". If the annul bit is 1, set *NPC to
1010 zero. */
1011 if (X_COND (insn) == 0x0)
1012 pc = *npc, offset = 4;
1013 if (X_A (insn))
1014 *npc = 0;
1015
1016 gdb_assert (offset != 0);
1017 return pc + offset;
1018 }
1019 }
1020
1021 return 0;
1022}
1023
1024void
1025sparc_software_single_step (enum target_signal sig, int insert_breakpoints_p)
1026{
1027 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1028 static CORE_ADDR npc, nnpc;
1029 static char npc_save[4], nnpc_save[4];
1030
1031 if (insert_breakpoints_p)
1032 {
1033 CORE_ADDR pc;
1034
1035 pc = sparc_address_from_register (tdep->pc_regnum);
1036 npc = sparc_address_from_register (tdep->npc_regnum);
1037
1038 /* Analyze the instruction at PC. */
1039 nnpc = sparc_analyze_control_transfer (pc, &npc);
1040 if (npc != 0)
1041 target_insert_breakpoint (npc, npc_save);
1042 if (nnpc != 0)
1043 target_insert_breakpoint (nnpc, nnpc_save);
1044
1045 /* Assert that we have set at least one breakpoint, and that
1046 they're not set at the same spot. */
1047 gdb_assert (npc != 0 || nnpc != 0);
1048 gdb_assert (nnpc != npc);
1049 }
1050 else
1051 {
1052 if (npc != 0)
1053 target_remove_breakpoint (npc, npc_save);
1054 if (nnpc != 0)
1055 target_remove_breakpoint (nnpc, nnpc_save);
1056 }
1057}
1058
1059static void
1060sparc_write_pc (CORE_ADDR pc, ptid_t ptid)
1061{
1062 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1063
1064 write_register_pid (tdep->pc_regnum, pc, ptid);
1065 write_register_pid (tdep->npc_regnum, pc + 4, ptid);
1066}
1067\f
1068/* Unglobalize NAME. */
1069
1070char *
1071sparc_stabs_unglobalize_name (char *name)
1072{
1073 /* The Sun compilers (Sun ONE Studio, Forte Developer, Sun WorkShop,
1074 SunPRO) convert file static variables into global values, a
1075 process known as globalization. In order to do this, the
1076 compiler will create a unique prefix and prepend it to each file
1077 static variable. For static variables within a function, this
1078 globalization prefix is followed by the function name (nested
1079 static variables within a function are supposed to generate a
1080 warning message, and are left alone). The procedure is
1081 documented in the Stabs Interface Manual, which is distrubuted
1082 with the compilers, although version 4.0 of the manual seems to
1083 be incorrect in some places, at least for SPARC. The
1084 globalization prefix is encoded into an N_OPT stab, with the form
1085 "G=<prefix>". The globalization prefix always seems to start
1086 with a dollar sign '$'; a dot '.' is used as a seperator. So we
1087 simply strip everything up until the last dot. */
1088
1089 if (name[0] == '$')
1090 {
1091 char *p = strrchr (name, '.');
1092 if (p)
1093 return p + 1;
1094 }
1095
1096 return name;
1097}
1098\f
1099
1100/* Return the appropriate register set for the core section identified
1101 by SECT_NAME and SECT_SIZE. */
1102
1103const struct regset *
1104sparc_regset_from_core_section (struct gdbarch *gdbarch,
1105 const char *sect_name, size_t sect_size)
1106{
1107 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1108
1109 if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset)
1110 return tdep->gregset;
1111
1112 if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset)
1113 return tdep->fpregset;
1114
1115 return NULL;
1116}
1117\f
1118
1119static struct gdbarch *
1120sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1121{
1122 struct gdbarch_tdep *tdep;
1123 struct gdbarch *gdbarch;
1124
1125 /* If there is already a candidate, use it. */
1126 arches = gdbarch_list_lookup_by_info (arches, &info);
1127 if (arches != NULL)
1128 return arches->gdbarch;
1129
1130 /* Allocate space for the new architecture. */
1131 tdep = XMALLOC (struct gdbarch_tdep);
1132 gdbarch = gdbarch_alloc (&info, tdep);
1133
1134 tdep->pc_regnum = SPARC32_PC_REGNUM;
1135 tdep->npc_regnum = SPARC32_NPC_REGNUM;
1136 tdep->gregset = NULL;
1137 tdep->sizeof_gregset = 0;
1138 tdep->fpregset = NULL;
1139 tdep->sizeof_fpregset = 0;
1140 tdep->plt_entry_size = 0;
1141
1142 set_gdbarch_long_double_bit (gdbarch, 128);
1143 set_gdbarch_long_double_format (gdbarch, &floatformat_sparc_quad);
1144
1145 set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS);
1146 set_gdbarch_register_name (gdbarch, sparc32_register_name);
1147 set_gdbarch_register_type (gdbarch, sparc32_register_type);
1148 set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS);
1149 set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read);
1150 set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write);
1151
1152 /* Register numbers of various important registers. */
1153 set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */
1154 set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */
1155 set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */
1156
1157 /* Call dummy code. */
1158 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
1159 set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code);
1160 set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call);
1161
1162 set_gdbarch_return_value (gdbarch, sparc32_return_value);
1163 set_gdbarch_stabs_argument_has_addr
1164 (gdbarch, sparc32_stabs_argument_has_addr);
1165
1166 set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue);
1167
1168 /* Stack grows downward. */
1169 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1170
1171 set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc);
1172
1173 set_gdbarch_frame_args_skip (gdbarch, 8);
1174
1175 set_gdbarch_print_insn (gdbarch, print_insn_sparc);
1176
1177 set_gdbarch_software_single_step (gdbarch, sparc_software_single_step);
1178 set_gdbarch_write_pc (gdbarch, sparc_write_pc);
1179
1180 set_gdbarch_unwind_dummy_id (gdbarch, sparc_unwind_dummy_id);
1181
1182 set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc);
1183
1184 frame_base_set_default (gdbarch, &sparc32_frame_base);
1185
1186 /* Hook in ABI-specific overrides, if they have been registered. */
1187 gdbarch_init_osabi (info, gdbarch);
1188
1189 frame_unwind_append_sniffer (gdbarch, sparc32_frame_sniffer);
1190
1191 /* If we have register sets, enable the generic core file support. */
1192 if (tdep->gregset)
1193 set_gdbarch_regset_from_core_section (gdbarch,
1194 sparc_regset_from_core_section);
1195
1196 return gdbarch;
1197}
1198\f
1199/* Helper functions for dealing with register windows. */
1200
1201void
1202sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum)
1203{
1204 int offset = 0;
1205 char buf[8];
1206 int i;
1207
1208 if (sp & 1)
1209 {
1210 /* Registers are 64-bit. */
1211 sp += BIAS;
1212
1213 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1214 {
1215 if (regnum == i || regnum == -1)
1216 {
1217 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1218 regcache_raw_supply (regcache, i, buf);
1219 }
1220 }
1221 }
1222 else
1223 {
1224 /* Registers are 32-bit. Toss any sign-extension of the stack
1225 pointer. */
1226 sp &= 0xffffffffUL;
1227
1228 /* Clear out the top half of the temporary buffer, and put the
1229 register value in the bottom half if we're in 64-bit mode. */
1230 if (gdbarch_ptr_bit (current_gdbarch) == 64)
1231 {
1232 memset (buf, 0, 4);
1233 offset = 4;
1234 }
1235
1236 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1237 {
1238 if (regnum == i || regnum == -1)
1239 {
1240 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1241 buf + offset, 4);
1242
1243 /* Handle StackGhost. */
1244 if (i == SPARC_I7_REGNUM)
1245 {
1246 ULONGEST wcookie = sparc_fetch_wcookie ();
1247 ULONGEST i7 = extract_unsigned_integer (buf + offset, 4);
1248
1249 store_unsigned_integer (buf + offset, 4, i7 ^ wcookie);
1250 }
1251
1252 regcache_raw_supply (regcache, i, buf);
1253 }
1254 }
1255 }
1256}
1257
1258void
1259sparc_collect_rwindow (const struct regcache *regcache,
1260 CORE_ADDR sp, int regnum)
1261{
1262 int offset = 0;
1263 char buf[8];
1264 int i;
1265
1266 if (sp & 1)
1267 {
1268 /* Registers are 64-bit. */
1269 sp += BIAS;
1270
1271 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1272 {
1273 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1274 {
1275 regcache_raw_collect (regcache, i, buf);
1276 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1277 }
1278 }
1279 }
1280 else
1281 {
1282 /* Registers are 32-bit. Toss any sign-extension of the stack
1283 pointer. */
1284 sp &= 0xffffffffUL;
1285
1286 /* Only use the bottom half if we're in 64-bit mode. */
1287 if (gdbarch_ptr_bit (current_gdbarch) == 64)
1288 offset = 4;
1289
1290 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1291 {
1292 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1293 {
1294 regcache_raw_collect (regcache, i, buf);
1295
1296 /* Handle StackGhost. */
1297 if (i == SPARC_I7_REGNUM)
1298 {
1299 ULONGEST wcookie = sparc_fetch_wcookie ();
1300 ULONGEST i7 = extract_unsigned_integer (buf + offset, 4);
1301
1302 store_unsigned_integer (buf + offset, 4, i7 ^ wcookie);
1303 }
1304
1305 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1306 buf + offset, 4);
1307 }
1308 }
1309 }
1310}
1311
1312/* Helper functions for dealing with register sets. */
1313
1314void
1315sparc32_supply_gregset (const struct sparc_gregset *gregset,
1316 struct regcache *regcache,
1317 int regnum, const void *gregs)
1318{
1319 const char *regs = gregs;
1320 int i;
1321
1322 if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1323 regcache_raw_supply (regcache, SPARC32_PSR_REGNUM,
1324 regs + gregset->r_psr_offset);
1325
1326 if (regnum == SPARC32_PC_REGNUM || regnum == -1)
1327 regcache_raw_supply (regcache, SPARC32_PC_REGNUM,
1328 regs + gregset->r_pc_offset);
1329
1330 if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
1331 regcache_raw_supply (regcache, SPARC32_NPC_REGNUM,
1332 regs + gregset->r_npc_offset);
1333
1334 if (regnum == SPARC32_Y_REGNUM || regnum == -1)
1335 regcache_raw_supply (regcache, SPARC32_Y_REGNUM,
1336 regs + gregset->r_y_offset);
1337
1338 if (regnum == SPARC_G0_REGNUM || regnum == -1)
1339 regcache_raw_supply (regcache, SPARC_G0_REGNUM, NULL);
1340
1341 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
1342 {
1343 int offset = gregset->r_g1_offset;
1344
1345 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
1346 {
1347 if (regnum == i || regnum == -1)
1348 regcache_raw_supply (regcache, i, regs + offset);
1349 offset += 4;
1350 }
1351 }
1352
1353 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
1354 {
1355 /* Not all of the register set variants include Locals and
1356 Inputs. For those that don't, we read them off the stack. */
1357 if (gregset->r_l0_offset == -1)
1358 {
1359 ULONGEST sp;
1360
1361 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1362 sparc_supply_rwindow (regcache, sp, regnum);
1363 }
1364 else
1365 {
1366 int offset = gregset->r_l0_offset;
1367
1368 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1369 {
1370 if (regnum == i || regnum == -1)
1371 regcache_raw_supply (regcache, i, regs + offset);
1372 offset += 4;
1373 }
1374 }
1375 }
1376}
1377
1378void
1379sparc32_collect_gregset (const struct sparc_gregset *gregset,
1380 const struct regcache *regcache,
1381 int regnum, void *gregs)
1382{
1383 char *regs = gregs;
1384 int i;
1385
1386 if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1387 regcache_raw_collect (regcache, SPARC32_PSR_REGNUM,
1388 regs + gregset->r_psr_offset);
1389
1390 if (regnum == SPARC32_PC_REGNUM || regnum == -1)
1391 regcache_raw_collect (regcache, SPARC32_PC_REGNUM,
1392 regs + gregset->r_pc_offset);
1393
1394 if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
1395 regcache_raw_collect (regcache, SPARC32_NPC_REGNUM,
1396 regs + gregset->r_npc_offset);
1397
1398 if (regnum == SPARC32_Y_REGNUM || regnum == -1)
1399 regcache_raw_collect (regcache, SPARC32_Y_REGNUM,
1400 regs + gregset->r_y_offset);
1401
1402 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
1403 {
1404 int offset = gregset->r_g1_offset;
1405
1406 /* %g0 is always zero. */
1407 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
1408 {
1409 if (regnum == i || regnum == -1)
1410 regcache_raw_collect (regcache, i, regs + offset);
1411 offset += 4;
1412 }
1413 }
1414
1415 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
1416 {
1417 /* Not all of the register set variants include Locals and
1418 Inputs. For those that don't, we read them off the stack. */
1419 if (gregset->r_l0_offset != -1)
1420 {
1421 int offset = gregset->r_l0_offset;
1422
1423 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1424 {
1425 if (regnum == i || regnum == -1)
1426 regcache_raw_collect (regcache, i, regs + offset);
1427 offset += 4;
1428 }
1429 }
1430 }
1431}
1432
1433void
1434sparc32_supply_fpregset (struct regcache *regcache,
1435 int regnum, const void *fpregs)
1436{
1437 const char *regs = fpregs;
1438 int i;
1439
1440 for (i = 0; i < 32; i++)
1441 {
1442 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
1443 regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, regs + (i * 4));
1444 }
1445
1446 if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
1447 regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4);
1448}
1449
1450void
1451sparc32_collect_fpregset (const struct regcache *regcache,
1452 int regnum, void *fpregs)
1453{
1454 char *regs = fpregs;
1455 int i;
1456
1457 for (i = 0; i < 32; i++)
1458 {
1459 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
1460 regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, regs + (i * 4));
1461 }
1462
1463 if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
1464 regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4);
1465}
1466\f
1467
1468/* SunOS 4. */
1469
1470/* From <machine/reg.h>. */
1471const struct sparc_gregset sparc32_sunos4_gregset =
1472{
1473 0 * 4, /* %psr */
1474 1 * 4, /* %pc */
1475 2 * 4, /* %npc */
1476 3 * 4, /* %y */
1477 -1, /* %wim */
1478 -1, /* %tbr */
1479 4 * 4, /* %g1 */
1480 -1 /* %l0 */
1481};
1482\f
1483
1484/* Provide a prototype to silence -Wmissing-prototypes. */
1485void _initialize_sparc_tdep (void);
1486
1487void
1488_initialize_sparc_tdep (void)
1489{
1490 register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init);
1491}
GDB Binutils - Deliverables
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