| 1 | /* Configuration for the Xtensa architecture for GDB, the GNU debugger. |
| 2 | |
| 3 | Copyright (C) 2003, 2005, 2006, 2007 Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 19 | |
| 20 | #include "xtensa-config.h" |
| 21 | #include "defs.h" |
| 22 | #include "gdbarch.h" |
| 23 | #include "xtensa-tdep.h" |
| 24 | #include "gdbtypes.h" |
| 25 | |
| 26 | /* Check version of configuration file. */ |
| 27 | #define XTENSA_CONFIG_VERSION 0x60 |
| 28 | #if XTENSA_TDEP_VERSION != XTENSA_CONFIG_VERSION |
| 29 | #warning "xtensa-config.c version mismatch!" |
| 30 | #endif |
| 31 | |
| 32 | |
| 33 | /* Return the byte order from the configuration. |
| 34 | We need this function, because the byte order is needed even |
| 35 | before the target structure (tdep) has been set up. */ |
| 36 | |
| 37 | int |
| 38 | xtensa_config_byte_order (void) |
| 39 | { |
| 40 | return XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE; |
| 41 | } |
| 42 | |
| 43 | |
| 44 | /* This routine returns the predefined architecture-dependent |
| 45 | parameter structure (tdep) and register map. */ |
| 46 | |
| 47 | struct gdbarch_tdep xtensa_tdep; |
| 48 | |
| 49 | struct gdbarch_tdep * |
| 50 | xtensa_config_tdep (struct gdbarch_info *info) |
| 51 | { |
| 52 | return &xtensa_tdep; |
| 53 | } |
| 54 | |
| 55 | |
| 56 | /* Masked registers. */ |
| 57 | xtensa_reg_mask_t xtensa_submask0[] = { { 96, 0, 4 } }; |
| 58 | const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 }; |
| 59 | xtensa_reg_mask_t xtensa_submask1[] = { { 96, 5, 1 } }; |
| 60 | const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 }; |
| 61 | xtensa_reg_mask_t xtensa_submask2[] = { { 96, 18, 1 } }; |
| 62 | const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 }; |
| 63 | xtensa_reg_mask_t xtensa_submask3[] = { { 96, 6, 2 } }; |
| 64 | const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 }; |
| 65 | xtensa_reg_mask_t xtensa_submask4[] = { { 96, 4, 1 } }; |
| 66 | const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 }; |
| 67 | xtensa_reg_mask_t xtensa_submask5[] = { { 96, 16, 2 } }; |
| 68 | const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 }; |
| 69 | xtensa_reg_mask_t xtensa_submask6[] = { { 96, 8, 4 } }; |
| 70 | const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 }; |
| 71 | xtensa_reg_mask_t xtensa_submask7[] = { { 95, 12, 20 } }; |
| 72 | const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 }; |
| 73 | xtensa_reg_mask_t xtensa_submask8[] = { { 95, 0, 1 } }; |
| 74 | const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 }; |
| 75 | xtensa_reg_mask_t xtensa_submask9[] = { { 108, 8, 4 } }; |
| 76 | const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 }; |
| 77 | xtensa_reg_mask_t xtensa_submask10[] = { { 109, 24, 8 } }; |
| 78 | const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 }; |
| 79 | xtensa_reg_mask_t xtensa_submask11[] = { { 109, 16, 8 } }; |
| 80 | const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 }; |
| 81 | xtensa_reg_mask_t xtensa_submask12[] = { { 109, 8, 8 } }; |
| 82 | const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 }; |
| 83 | xtensa_reg_mask_t xtensa_submask13[] = { { 110, 16, 2 } }; |
| 84 | const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 }; |
| 85 | xtensa_reg_mask_t xtensa_submask14[] = { { 111, 16, 2 } }; |
| 86 | const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 }; |
| 87 | xtensa_reg_mask_t xtensa_submask15[] = { { 67, 22, 10 } }; |
| 88 | const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 }; |
| 89 | |
| 90 | |
| 91 | /* Register map. */ |
| 92 | xtensa_register_t rmap[] = |
| 93 | { |
| 94 | { /* 0000 */ "ar0", 0, xtRegisterTypeArRegfile, 0x2, 0, |
| 95 | 32, 4, 4, 0x00000100, 0x0006, 0, |
| 96 | 0, 0 }, |
| 97 | { /* 0001 */ "ar1", 4, xtRegisterTypeArRegfile, 0x2, 0, |
| 98 | 32, 4, 4, 0x00000101, 0x0006, 0, |
| 99 | 0, 0 }, |
| 100 | { /* 0002 */ "ar2", 8, xtRegisterTypeArRegfile, 0x2, 0, |
| 101 | 32, 4, 4, 0x00000102, 0x0006, 0, |
| 102 | 0, 0 }, |
| 103 | { /* 0003 */ "ar3", 12, xtRegisterTypeArRegfile, 0x2, 0, |
| 104 | 32, 4, 4, 0x00000103, 0x0006, 0, |
| 105 | 0, 0 }, |
| 106 | { /* 0004 */ "ar4", 16, xtRegisterTypeArRegfile, 0x2, 0, |
| 107 | 32, 4, 4, 0x00000104, 0x0006, 0, |
| 108 | 0, 0 }, |
| 109 | { /* 0005 */ "ar5", 20, xtRegisterTypeArRegfile, 0x2, 0, |
| 110 | 32, 4, 4, 0x00000105, 0x0006, 0, |
| 111 | 0, 0 }, |
| 112 | { /* 0006 */ "ar6", 24, xtRegisterTypeArRegfile, 0x2, 0, |
| 113 | 32, 4, 4, 0x00000106, 0x0006, 0, |
| 114 | 0, 0 }, |
| 115 | { /* 0007 */ "ar7", 28, xtRegisterTypeArRegfile, 0x2, 0, |
| 116 | 32, 4, 4, 0x00000107, 0x0006, 0, |
| 117 | 0, 0 }, |
| 118 | { /* 0008 */ "ar8", 32, xtRegisterTypeArRegfile, 0x2, 0, |
| 119 | 32, 4, 4, 0x00000108, 0x0006, 0, |
| 120 | 0, 0 }, |
| 121 | { /* 0009 */ "ar9", 36, xtRegisterTypeArRegfile, 0x2, 0, |
| 122 | 32, 4, 4, 0x00000109, 0x0006, 0, |
| 123 | 0, 0 }, |
| 124 | { /* 0010 */ "ar10", 40, xtRegisterTypeArRegfile, 0x2, 0, |
| 125 | 32, 4, 4, 0x0000010a, 0x0006, 0, |
| 126 | 0, 0 }, |
| 127 | { /* 0011 */ "ar11", 44, xtRegisterTypeArRegfile, 0x2, 0, |
| 128 | 32, 4, 4, 0x0000010b, 0x0006, 0, |
| 129 | 0, 0 }, |
| 130 | { /* 0012 */ "ar12", 48, xtRegisterTypeArRegfile, 0x2, 0, |
| 131 | 32, 4, 4, 0x0000010c, 0x0006, 0, |
| 132 | 0, 0 }, |
| 133 | { /* 0013 */ "ar13", 52, xtRegisterTypeArRegfile, 0x2, 0, |
| 134 | 32, 4, 4, 0x0000010d, 0x0006, 0, |
| 135 | 0, 0 }, |
| 136 | { /* 0014 */ "ar14", 56, xtRegisterTypeArRegfile, 0x2, 0, |
| 137 | 32, 4, 4, 0x0000010e, 0x0006, 0, |
| 138 | 0, 0 }, |
| 139 | { /* 0015 */ "ar15", 60, xtRegisterTypeArRegfile, 0x2, 0, |
| 140 | 32, 4, 4, 0x0000010f, 0x0006, 0, |
| 141 | 0, 0 }, |
| 142 | { /* 0016 */ "ar16", 64, xtRegisterTypeArRegfile, 0x2, 0, |
| 143 | 32, 4, 4, 0x00000110, 0x0006, 0, |
| 144 | 0, 0 }, |
| 145 | { /* 0017 */ "ar17", 68, xtRegisterTypeArRegfile, 0x2, 0, |
| 146 | 32, 4, 4, 0x00000111, 0x0006, 0, |
| 147 | 0, 0 }, |
| 148 | { /* 0018 */ "ar18", 72, xtRegisterTypeArRegfile, 0x2, 0, |
| 149 | 32, 4, 4, 0x00000112, 0x0006, 0, |
| 150 | 0, 0 }, |
| 151 | { /* 0019 */ "ar19", 76, xtRegisterTypeArRegfile, 0x2, 0, |
| 152 | 32, 4, 4, 0x00000113, 0x0006, 0, |
| 153 | 0, 0 }, |
| 154 | { /* 0020 */ "ar20", 80, xtRegisterTypeArRegfile, 0x2, 0, |
| 155 | 32, 4, 4, 0x00000114, 0x0006, 0, |
| 156 | 0, 0 }, |
| 157 | { /* 0021 */ "ar21", 84, xtRegisterTypeArRegfile, 0x2, 0, |
| 158 | 32, 4, 4, 0x00000115, 0x0006, 0, |
| 159 | 0, 0 }, |
| 160 | { /* 0022 */ "ar22", 88, xtRegisterTypeArRegfile, 0x2, 0, |
| 161 | 32, 4, 4, 0x00000116, 0x0006, 0, |
| 162 | 0, 0 }, |
| 163 | { /* 0023 */ "ar23", 92, xtRegisterTypeArRegfile, 0x2, 0, |
| 164 | 32, 4, 4, 0x00000117, 0x0006, 0, |
| 165 | 0, 0 }, |
| 166 | { /* 0024 */ "ar24", 96, xtRegisterTypeArRegfile, 0x2, 0, |
| 167 | 32, 4, 4, 0x00000118, 0x0006, 0, |
| 168 | 0, 0 }, |
| 169 | { /* 0025 */ "ar25", 100, xtRegisterTypeArRegfile, 0x2, 0, |
| 170 | 32, 4, 4, 0x00000119, 0x0006, 0, |
| 171 | 0, 0 }, |
| 172 | { /* 0026 */ "ar26", 104, xtRegisterTypeArRegfile, 0x2, 0, |
| 173 | 32, 4, 4, 0x0000011a, 0x0006, 0, |
| 174 | 0, 0 }, |
| 175 | { /* 0027 */ "ar27", 108, xtRegisterTypeArRegfile, 0x2, 0, |
| 176 | 32, 4, 4, 0x0000011b, 0x0006, 0, |
| 177 | 0, 0 }, |
| 178 | { /* 0028 */ "ar28", 112, xtRegisterTypeArRegfile, 0x2, 0, |
| 179 | 32, 4, 4, 0x0000011c, 0x0006, 0, |
| 180 | 0, 0 }, |
| 181 | { /* 0029 */ "ar29", 116, xtRegisterTypeArRegfile, 0x2, 0, |
| 182 | 32, 4, 4, 0x0000011d, 0x0006, 0, |
| 183 | 0, 0 }, |
| 184 | { /* 0030 */ "ar30", 120, xtRegisterTypeArRegfile, 0x2, 0, |
| 185 | 32, 4, 4, 0x0000011e, 0x0006, 0, |
| 186 | 0, 0 }, |
| 187 | { /* 0031 */ "ar31", 124, xtRegisterTypeArRegfile, 0x2, 0, |
| 188 | 32, 4, 4, 0x0000011f, 0x0006, 0, |
| 189 | 0, 0 }, |
| 190 | { /* 0032 */ "ar32", 128, xtRegisterTypeArRegfile, 0x2, 0, |
| 191 | 32, 4, 4, 0x00000120, 0x0006, 0, |
| 192 | 0, 0 }, |
| 193 | { /* 0033 */ "ar33", 132, xtRegisterTypeArRegfile, 0x2, 0, |
| 194 | 32, 4, 4, 0x00000121, 0x0006, 0, |
| 195 | 0, 0 }, |
| 196 | { /* 0034 */ "ar34", 136, xtRegisterTypeArRegfile, 0x2, 0, |
| 197 | 32, 4, 4, 0x00000122, 0x0006, 0, |
| 198 | 0, 0 }, |
| 199 | { /* 0035 */ "ar35", 140, xtRegisterTypeArRegfile, 0x2, 0, |
| 200 | 32, 4, 4, 0x00000123, 0x0006, 0, |
| 201 | 0, 0 }, |
| 202 | { /* 0036 */ "ar36", 144, xtRegisterTypeArRegfile, 0x2, 0, |
| 203 | 32, 4, 4, 0x00000124, 0x0006, 0, |
| 204 | 0, 0 }, |
| 205 | { /* 0037 */ "ar37", 148, xtRegisterTypeArRegfile, 0x2, 0, |
| 206 | 32, 4, 4, 0x00000125, 0x0006, 0, |
| 207 | 0, 0 }, |
| 208 | { /* 0038 */ "ar38", 152, xtRegisterTypeArRegfile, 0x2, 0, |
| 209 | 32, 4, 4, 0x00000126, 0x0006, 0, |
| 210 | 0, 0 }, |
| 211 | { /* 0039 */ "ar39", 156, xtRegisterTypeArRegfile, 0x2, 0, |
| 212 | 32, 4, 4, 0x00000127, 0x0006, 0, |
| 213 | 0, 0 }, |
| 214 | { /* 0040 */ "ar40", 160, xtRegisterTypeArRegfile, 0x2, 0, |
| 215 | 32, 4, 4, 0x00000128, 0x0006, 0, |
| 216 | 0, 0 }, |
| 217 | { /* 0041 */ "ar41", 164, xtRegisterTypeArRegfile, 0x2, 0, |
| 218 | 32, 4, 4, 0x00000129, 0x0006, 0, |
| 219 | 0, 0 }, |
| 220 | { /* 0042 */ "ar42", 168, xtRegisterTypeArRegfile, 0x2, 0, |
| 221 | 32, 4, 4, 0x0000012a, 0x0006, 0, |
| 222 | 0, 0 }, |
| 223 | { /* 0043 */ "ar43", 172, xtRegisterTypeArRegfile, 0x2, 0, |
| 224 | 32, 4, 4, 0x0000012b, 0x0006, 0, |
| 225 | 0, 0 }, |
| 226 | { /* 0044 */ "ar44", 176, xtRegisterTypeArRegfile, 0x2, 0, |
| 227 | 32, 4, 4, 0x0000012c, 0x0006, 0, |
| 228 | 0, 0 }, |
| 229 | { /* 0045 */ "ar45", 180, xtRegisterTypeArRegfile, 0x2, 0, |
| 230 | 32, 4, 4, 0x0000012d, 0x0006, 0, |
| 231 | 0, 0 }, |
| 232 | { /* 0046 */ "ar46", 184, xtRegisterTypeArRegfile, 0x2, 0, |
| 233 | 32, 4, 4, 0x0000012e, 0x0006, 0, |
| 234 | 0, 0 }, |
| 235 | { /* 0047 */ "ar47", 188, xtRegisterTypeArRegfile, 0x2, 0, |
| 236 | 32, 4, 4, 0x0000012f, 0x0006, 0, |
| 237 | 0, 0 }, |
| 238 | { /* 0048 */ "ar48", 192, xtRegisterTypeArRegfile, 0x2, 0, |
| 239 | 32, 4, 4, 0x00000130, 0x0006, 0, |
| 240 | 0, 0 }, |
| 241 | { /* 0049 */ "ar49", 196, xtRegisterTypeArRegfile, 0x2, 0, |
| 242 | 32, 4, 4, 0x00000131, 0x0006, 0, |
| 243 | 0, 0 }, |
| 244 | { /* 0050 */ "ar50", 200, xtRegisterTypeArRegfile, 0x2, 0, |
| 245 | 32, 4, 4, 0x00000132, 0x0006, 0, |
| 246 | 0, 0 }, |
| 247 | { /* 0051 */ "ar51", 204, xtRegisterTypeArRegfile, 0x2, 0, |
| 248 | 32, 4, 4, 0x00000133, 0x0006, 0, |
| 249 | 0, 0 }, |
| 250 | { /* 0052 */ "ar52", 208, xtRegisterTypeArRegfile, 0x2, 0, |
| 251 | 32, 4, 4, 0x00000134, 0x0006, 0, |
| 252 | 0, 0 }, |
| 253 | { /* 0053 */ "ar53", 212, xtRegisterTypeArRegfile, 0x2, 0, |
| 254 | 32, 4, 4, 0x00000135, 0x0006, 0, |
| 255 | 0, 0 }, |
| 256 | { /* 0054 */ "ar54", 216, xtRegisterTypeArRegfile, 0x2, 0, |
| 257 | 32, 4, 4, 0x00000136, 0x0006, 0, |
| 258 | 0, 0 }, |
| 259 | { /* 0055 */ "ar55", 220, xtRegisterTypeArRegfile, 0x2, 0, |
| 260 | 32, 4, 4, 0x00000137, 0x0006, 0, |
| 261 | 0, 0 }, |
| 262 | { /* 0056 */ "ar56", 224, xtRegisterTypeArRegfile, 0x2, 0, |
| 263 | 32, 4, 4, 0x00000138, 0x0006, 0, |
| 264 | 0, 0 }, |
| 265 | { /* 0057 */ "ar57", 228, xtRegisterTypeArRegfile, 0x2, 0, |
| 266 | 32, 4, 4, 0x00000139, 0x0006, 0, |
| 267 | 0, 0 }, |
| 268 | { /* 0058 */ "ar58", 232, xtRegisterTypeArRegfile, 0x2, 0, |
| 269 | 32, 4, 4, 0x0000013a, 0x0006, 0, |
| 270 | 0, 0 }, |
| 271 | { /* 0059 */ "ar59", 236, xtRegisterTypeArRegfile, 0x2, 0, |
| 272 | 32, 4, 4, 0x0000013b, 0x0006, 0, |
| 273 | 0, 0 }, |
| 274 | { /* 0060 */ "ar60", 240, xtRegisterTypeArRegfile, 0x2, 0, |
| 275 | 32, 4, 4, 0x0000013c, 0x0006, 0, |
| 276 | 0, 0 }, |
| 277 | { /* 0061 */ "ar61", 244, xtRegisterTypeArRegfile, 0x2, 0, |
| 278 | 32, 4, 4, 0x0000013d, 0x0006, 0, |
| 279 | 0, 0 }, |
| 280 | { /* 0062 */ "ar62", 248, xtRegisterTypeArRegfile, 0x2, 0, |
| 281 | 32, 4, 4, 0x0000013e, 0x0006, 0, |
| 282 | 0, 0 }, |
| 283 | { /* 0063 */ "ar63", 252, xtRegisterTypeArRegfile, 0x2, 0, |
| 284 | 32, 4, 4, 0x0000013f, 0x0006, 0, |
| 285 | 0, 0 }, |
| 286 | { /* 0064 */ "lbeg", 256, xtRegisterTypeSpecialReg, 0x1100, 0, |
| 287 | 32, 4, 4, 0x00000200, 0x0006, 0, |
| 288 | 0, 0 }, |
| 289 | { /* 0065 */ "lend", 260, xtRegisterTypeSpecialReg, 0x1100, 0, |
| 290 | 32, 4, 4, 0x00000201, 0x0006, 0, |
| 291 | 0, 0 }, |
| 292 | { /* 0066 */ "lcount", 264, xtRegisterTypeSpecialReg, 0x1100, 0, |
| 293 | 32, 4, 4, 0x00000202, 0x0006, 0, |
| 294 | 0, 0 }, |
| 295 | { /* 0067 */ "ptevaddr", 268, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 296 | 32, 4, 4, 0x00000253, 0x0007, 0, |
| 297 | 0, 0 }, |
| 298 | { /* 0068 */ "ddr", 272, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 299 | 32, 4, 4, 0x00000268, 0x0007, 0, |
| 300 | 0, 0 }, |
| 301 | { /* 0069 */ "interrupt", 276, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 302 | 17, 4, 4, 0x000002e2, 0x000b, 0, |
| 303 | 0, 0 }, |
| 304 | { /* 0070 */ "intset", 280, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 305 | 17, 4, 4, 0x000002e2, 0x000d, 0, |
| 306 | 0, 0 }, |
| 307 | { /* 0071 */ "intclear", 284, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 308 | 17, 4, 4, 0x000002e3, 0x000d, 0, |
| 309 | 0, 0 }, |
| 310 | { /* 0072 */ "ccount", 288, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 311 | 32, 4, 4, 0x000002ea, 0x000f, 0, |
| 312 | 0, 0 }, |
| 313 | { /* 0073 */ "prid", 292, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 314 | 32, 4, 4, 0x000002eb, 0x0003, 0, |
| 315 | 0, 0 }, |
| 316 | { /* 0074 */ "icount", 296, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 317 | 32, 4, 4, 0x000002ec, 0x000f, 0, |
| 318 | 0, 0 }, |
| 319 | { /* 0075 */ "ccompare0", 300, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 320 | 32, 4, 4, 0x000002f0, 0x000f, 0, |
| 321 | 0, 0 }, |
| 322 | { /* 0076 */ "ccompare1", 304, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 323 | 32, 4, 4, 0x000002f1, 0x000f, 0, |
| 324 | 0, 0 }, |
| 325 | { /* 0077 */ "ccompare2", 308, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 326 | 32, 4, 4, 0x000002f2, 0x000f, 0, |
| 327 | 0, 0 }, |
| 328 | { /* 0078 */ "epc1", 312, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 329 | 32, 4, 4, 0x000002b1, 0x0007, 0, |
| 330 | 0, 0 }, |
| 331 | { /* 0079 */ "epc2", 316, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 332 | 32, 4, 4, 0x000002b2, 0x0007, 0, |
| 333 | 0, 0 }, |
| 334 | { /* 0080 */ "epc3", 320, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 335 | 32, 4, 4, 0x000002b3, 0x0007, 0, |
| 336 | 0, 0 }, |
| 337 | { /* 0081 */ "epc4", 324, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 338 | 32, 4, 4, 0x000002b4, 0x0007, 0, |
| 339 | 0, 0 }, |
| 340 | { /* 0082 */ "excsave1", 328, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 341 | 32, 4, 4, 0x000002d1, 0x0007, 0, |
| 342 | 0, 0 }, |
| 343 | { /* 0083 */ "excsave2", 332, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 344 | 32, 4, 4, 0x000002d2, 0x0007, 0, |
| 345 | 0, 0 }, |
| 346 | { /* 0084 */ "excsave3", 336, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 347 | 32, 4, 4, 0x000002d3, 0x0007, 0, |
| 348 | 0, 0 }, |
| 349 | { /* 0085 */ "excsave4", 340, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 350 | 32, 4, 4, 0x000002d4, 0x0007, 0, |
| 351 | 0, 0 }, |
| 352 | { /* 0086 */ "eps2", 344, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 353 | 19, 4, 4, 0x000002c2, 0x0007, 0, |
| 354 | 0, 0 }, |
| 355 | { /* 0087 */ "eps3", 348, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 356 | 19, 4, 4, 0x000002c3, 0x0007, 0, |
| 357 | 0, 0 }, |
| 358 | { /* 0088 */ "eps4", 352, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 359 | 19, 4, 4, 0x000002c4, 0x0007, 0, |
| 360 | 0, 0 }, |
| 361 | { /* 0089 */ "exccause", 356, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 362 | 6, 4, 4, 0x000002e8, 0x0007, 0, |
| 363 | 0, 0 }, |
| 364 | { /* 0090 */ "depc", 360, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 365 | 32, 4, 4, 0x000002c0, 0x0007, 0, |
| 366 | 0, 0 }, |
| 367 | { /* 0091 */ "excvaddr", 364, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 368 | 32, 4, 4, 0x000002ee, 0x0007, 0, |
| 369 | 0, 0 }, |
| 370 | { /* 0092 */ "windowbase", 368, xtRegisterTypeSpecialReg, 0x1002, 0, |
| 371 | 4, 4, 4, 0x00000248, 0x0007, 0, |
| 372 | 0, 0 }, |
| 373 | { /* 0093 */ "windowstart", 372, xtRegisterTypeSpecialReg, 0x1002, 0, |
| 374 | 16, 4, 4, 0x00000249, 0x0007, 0, |
| 375 | 0, 0 }, |
| 376 | { /* 0094 */ "sar", 376, xtRegisterTypeSpecialReg, 0x1100, 0, |
| 377 | 6, 4, 4, 0x00000203, 0x0006, 0, |
| 378 | 0, 0 }, |
| 379 | { /* 0095 */ "litbase", 380, xtRegisterTypeSpecialReg, 0x1100, 0, |
| 380 | 32, 4, 4, 0x00000205, 0x0006, 0, |
| 381 | 0, 0 }, |
| 382 | { /* 0096 */ "ps", 384, xtRegisterTypeSpecialReg, 0x1100, 0, |
| 383 | 19, 4, 4, 0x000002e6, 0x0007, 0, |
| 384 | 0, 0 }, |
| 385 | { /* 0097 */ "misc0", 388, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 386 | 32, 4, 4, 0x000002f4, 0x0007, 0, |
| 387 | 0, 0 }, |
| 388 | { /* 0098 */ "misc1", 392, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 389 | 32, 4, 4, 0x000002f5, 0x0007, 0, |
| 390 | 0, 0 }, |
| 391 | { /* 0099 */ "intenable", 396, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 392 | 17, 4, 4, 0x000002e4, 0x0007, 0, |
| 393 | 0, 0 }, |
| 394 | { /* 0100 */ "dbreaka0", 400, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 395 | 32, 4, 4, 0x00000290, 0x0007, 0, |
| 396 | 0, 0 }, |
| 397 | { /* 0101 */ "dbreakc0", 404, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 398 | 32, 4, 4, 0x000002a0, 0x0007, 0, |
| 399 | 0, 0 }, |
| 400 | { /* 0102 */ "dbreaka1", 408, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 401 | 32, 4, 4, 0x00000291, 0x0007, 0, |
| 402 | 0, 0 }, |
| 403 | { /* 0103 */ "dbreakc1", 412, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 404 | 32, 4, 4, 0x000002a1, 0x0007, 0, |
| 405 | 0, 0 }, |
| 406 | { /* 0104 */ "ibreaka0", 416, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 407 | 32, 4, 4, 0x00000280, 0x0007, 0, |
| 408 | 0, 0 }, |
| 409 | { /* 0105 */ "ibreaka1", 420, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 410 | 32, 4, 4, 0x00000281, 0x0007, 0, |
| 411 | 0, 0 }, |
| 412 | { /* 0106 */ "ibreakenable", 424, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 413 | 2, 4, 4, 0x00000260, 0x0007, 0, |
| 414 | 0, 0 }, |
| 415 | { /* 0107 */ "icountlevel", 428, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 416 | 4, 4, 4, 0x000002ed, 0x0007, 0, |
| 417 | 0, 0 }, |
| 418 | { /* 0108 */ "debugcause", 432, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 419 | 12, 4, 4, 0x000002e9, 0x0003, 0, |
| 420 | 0, 0 }, |
| 421 | { /* 0109 */ "rasid", 436, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 422 | 32, 4, 4, 0x0000025a, 0x0007, 0, |
| 423 | 0, 0 }, |
| 424 | { /* 0110 */ "itlbcfg", 440, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 425 | 18, 4, 4, 0x0000025b, 0x0007, 0, |
| 426 | 0, 0 }, |
| 427 | { /* 0111 */ "dtlbcfg", 444, xtRegisterTypeSpecialReg, 0x1000, 0, |
| 428 | 18, 4, 4, 0x0000025c, 0x0007, 0, |
| 429 | 0, 0 }, |
| 430 | { /* 0112 */ "threadptr", 448, xtRegisterTypeUserReg, 0x110, 0, |
| 431 | 32, 4, 4, 0x000003e7, 0x0006, 0, |
| 432 | 0, 0 }, |
| 433 | { /* 0113 */ "pc", 452, xtRegisterTypeVirtual, 0x100, 0, |
| 434 | 32, 4, 4, 0x00000020, 0x0006, 0, |
| 435 | 0, 0 }, |
| 436 | { /* 0114 */ "a0", 456, xtRegisterTypeWindow, 0x100, 0, |
| 437 | 32, 4, 4, 0x00000000, 0x0006, 0, |
| 438 | 0, 0 }, |
| 439 | { /* 0115 */ "a1", 460, xtRegisterTypeWindow, 0x100, 0, |
| 440 | 32, 4, 4, 0x00000001, 0x0006, 0, |
| 441 | 0, 0 }, |
| 442 | { /* 0116 */ "a2", 464, xtRegisterTypeWindow, 0x100, 0, |
| 443 | 32, 4, 4, 0x00000002, 0x0006, 0, |
| 444 | 0, 0 }, |
| 445 | { /* 0117 */ "a3", 468, xtRegisterTypeWindow, 0x100, 0, |
| 446 | 32, 4, 4, 0x00000003, 0x0006, 0, |
| 447 | 0, 0 }, |
| 448 | { /* 0118 */ "a4", 472, xtRegisterTypeWindow, 0x100, 0, |
| 449 | 32, 4, 4, 0x00000004, 0x0006, 0, |
| 450 | 0, 0 }, |
| 451 | { /* 0119 */ "a5", 476, xtRegisterTypeWindow, 0x100, 0, |
| 452 | 32, 4, 4, 0x00000005, 0x0006, 0, |
| 453 | 0, 0 }, |
| 454 | { /* 0120 */ "a6", 480, xtRegisterTypeWindow, 0x100, 0, |
| 455 | 32, 4, 4, 0x00000006, 0x0006, 0, |
| 456 | 0, 0 }, |
| 457 | { /* 0121 */ "a7", 484, xtRegisterTypeWindow, 0x100, 0, |
| 458 | 32, 4, 4, 0x00000007, 0x0006, 0, |
| 459 | 0, 0 }, |
| 460 | { /* 0122 */ "a8", 488, xtRegisterTypeWindow, 0x100, 0, |
| 461 | 32, 4, 4, 0x00000008, 0x0006, 0, |
| 462 | 0, 0 }, |
| 463 | { /* 0123 */ "a9", 492, xtRegisterTypeWindow, 0x100, 0, |
| 464 | 32, 4, 4, 0x00000009, 0x0006, 0, |
| 465 | 0, 0 }, |
| 466 | { /* 0124 */ "a10", 496, xtRegisterTypeWindow, 0x100, 0, |
| 467 | 32, 4, 4, 0x0000000a, 0x0006, 0, |
| 468 | 0, 0 }, |
| 469 | { /* 0125 */ "a11", 500, xtRegisterTypeWindow, 0x100, 0, |
| 470 | 32, 4, 4, 0x0000000b, 0x0006, 0, |
| 471 | 0, 0 }, |
| 472 | { /* 0126 */ "a12", 504, xtRegisterTypeWindow, 0x100, 0, |
| 473 | 32, 4, 4, 0x0000000c, 0x0006, 0, |
| 474 | 0, 0 }, |
| 475 | { /* 0127 */ "a13", 508, xtRegisterTypeWindow, 0x100, 0, |
| 476 | 32, 4, 4, 0x0000000d, 0x0006, 0, |
| 477 | 0, 0 }, |
| 478 | { /* 0128 */ "a14", 512, xtRegisterTypeWindow, 0x100, 0, |
| 479 | 32, 4, 4, 0x0000000e, 0x0006, 0, |
| 480 | 0, 0 }, |
| 481 | { /* 0129 */ "a15", 516, xtRegisterTypeWindow, 0x100, 0, |
| 482 | 32, 4, 4, 0x0000000f, 0x0006, 0, |
| 483 | 0, 0 }, |
| 484 | { /* 0130 */ "psintlevel", 520, xtRegisterTypeMapped, 0x1010, 0, |
| 485 | 4, 4, 4, 0x00002004, 0x0006, &xtensa_mask0, |
| 486 | 0, 0 }, |
| 487 | { /* 0131 */ "psum", 524, xtRegisterTypeMapped, 0x1010, 0, |
| 488 | 1, 4, 4, 0x00002005, 0x0006, &xtensa_mask1, |
| 489 | 0, 0 }, |
| 490 | { /* 0132 */ "pswoe", 528, xtRegisterTypeMapped, 0x1010, 0, |
| 491 | 1, 4, 4, 0x00002006, 0x0006, &xtensa_mask2, |
| 492 | 0, 0 }, |
| 493 | { /* 0133 */ "psring", 532, xtRegisterTypeMapped, 0x1010, 0, |
| 494 | 2, 4, 4, 0x00002007, 0x0006, &xtensa_mask3, |
| 495 | 0, 0 }, |
| 496 | { /* 0134 */ "psexcm", 536, xtRegisterTypeMapped, 0x1010, 0, |
| 497 | 1, 4, 4, 0x00002008, 0x0006, &xtensa_mask4, |
| 498 | 0, 0 }, |
| 499 | { /* 0135 */ "pscallinc", 540, xtRegisterTypeMapped, 0x1010, 0, |
| 500 | 2, 4, 4, 0x00002009, 0x0006, &xtensa_mask5, |
| 501 | 0, 0 }, |
| 502 | { /* 0136 */ "psowb", 544, xtRegisterTypeMapped, 0x1010, 0, |
| 503 | 4, 4, 4, 0x0000200a, 0x0006, &xtensa_mask6, |
| 504 | 0, 0 }, |
| 505 | { /* 0137 */ "litbaddr", 548, xtRegisterTypeMapped, 0x1010, 0, |
| 506 | 20, 4, 4, 0x0000200b, 0x0006, &xtensa_mask7, |
| 507 | 0, 0 }, |
| 508 | { /* 0138 */ "litben", 552, xtRegisterTypeMapped, 0x1010, 0, |
| 509 | 1, 4, 4, 0x0000200c, 0x0006, &xtensa_mask8, |
| 510 | 0, 0 }, |
| 511 | { /* 0139 */ "dbnum", 556, xtRegisterTypeMapped, 0x1010, 0, |
| 512 | 4, 4, 4, 0x00002011, 0x0006, &xtensa_mask9, |
| 513 | 0, 0 }, |
| 514 | { /* 0140 */ "asid3", 560, xtRegisterTypeMapped, 0x1010, 0, |
| 515 | 8, 4, 4, 0x00002012, 0x0006, &xtensa_mask10, |
| 516 | 0, 0 }, |
| 517 | { /* 0141 */ "asid2", 564, xtRegisterTypeMapped, 0x1010, 0, |
| 518 | 8, 4, 4, 0x00002013, 0x0006, &xtensa_mask11, |
| 519 | 0, 0 }, |
| 520 | { /* 0142 */ "asid1", 568, xtRegisterTypeMapped, 0x1010, 0, |
| 521 | 8, 4, 4, 0x00002014, 0x0006, &xtensa_mask12, |
| 522 | 0, 0 }, |
| 523 | { /* 0143 */ "instpgszid4", 572, xtRegisterTypeMapped, 0x1010, 0, |
| 524 | 2, 4, 4, 0x00002015, 0x0006, &xtensa_mask13, |
| 525 | 0, 0 }, |
| 526 | { /* 0144 */ "datapgszid4", 576, xtRegisterTypeMapped, 0x1010, 0, |
| 527 | 2, 4, 4, 0x00002016, 0x0006, &xtensa_mask14, |
| 528 | 0, 0 }, |
| 529 | { /* 0145 */ "ptbase", 580, xtRegisterTypeMapped, 0x1010, 0, |
| 530 | 10, 4, 4, 0x00002017, 0x0006, &xtensa_mask15, |
| 531 | 0, 0 }, |
| 532 | }; |
| 533 | |
| 534 | |
| 535 | struct gdbarch_tdep xtensa_tdep = |
| 536 | { |
| 537 | /* target_flags */ 0, |
| 538 | /* spill_location */ -1, |
| 539 | /* spill_size */ 0, |
| 540 | /* unused */ 0, |
| 541 | /* call_abi */ 0, |
| 542 | /* debug_interrupt_level */ XCHAL_DEBUGLEVEL, |
| 543 | /* icache_line_bytes */ XCHAL_ICACHE_LINESIZE, |
| 544 | /* dcache_line_bytes */ XCHAL_DCACHE_LINESIZE, |
| 545 | /* dcache_writeback */ XCHAL_DCACHE_IS_WRITEBACK, |
| 546 | /* isa_use_windowed_registers */ XCHAL_HAVE_WINDOWED, |
| 547 | /* isa_use_density_instructions */ XCHAL_HAVE_DENSITY, |
| 548 | /* isa_use_exceptions */ 1, |
| 549 | /* isa_use_ext_l32r */ 0 /* XCHAL_USE_ABSOLUTE_LITERALS */, |
| 550 | /* isa_max_insn_size */ 3, |
| 551 | /* debug_num_ibreaks */ XCHAL_NUM_IBREAK, |
| 552 | /* debug_num_dbreaks */ XCHAL_NUM_DBREAK, |
| 553 | /* rmap */ rmap, |
| 554 | /* num_regs */ 114, |
| 555 | /* num_pseudo_regs */ 32, |
| 556 | /* num_aregs */ 64, |
| 557 | /* num_contexts */ 0, |
| 558 | /* ar_base */ 0, |
| 559 | /* a0_base */ 114, |
| 560 | /* wb_regnum */ 92, |
| 561 | /* ws_regnum */ 93, |
| 562 | /* pc_regnum */ 113, |
| 563 | /* ps_regnum */ 96, |
| 564 | /* lbeg_regnum */ 64, |
| 565 | /* lend_regnum */ 65, |
| 566 | /* lcount_regnum */ 66, |
| 567 | /* sar_regnum */ 94, |
| 568 | /* litbase_regnum */ 0, |
| 569 | /* debugcause_regnum */ 108, |
| 570 | /* exccause_regnum */ 89, |
| 571 | /* excvaddr_regnum */ 91, |
| 572 | /* max_register_raw_size */ 4, |
| 573 | /* max_register_virtual_size */ 4, |
| 574 | /* fp_layout */ 0, |
| 575 | /* fp_layout_bytes */ 0, |
| 576 | /* gregmap */ 0 |
| 577 | }; |